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radv: skip draws with instance_count == 0
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range);
61
62 const struct radv_dynamic_state default_dynamic_state = {
63 .viewport = {
64 .count = 0,
65 },
66 .scissor = {
67 .count = 0,
68 },
69 .line_width = 1.0f,
70 .depth_bias = {
71 .bias = 0.0f,
72 .clamp = 0.0f,
73 .slope = 0.0f,
74 },
75 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
76 .depth_bounds = {
77 .min = 0.0f,
78 .max = 1.0f,
79 },
80 .stencil_compare_mask = {
81 .front = ~0u,
82 .back = ~0u,
83 },
84 .stencil_write_mask = {
85 .front = ~0u,
86 .back = ~0u,
87 },
88 .stencil_reference = {
89 .front = 0u,
90 .back = 0u,
91 },
92 };
93
94 static void
95 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
96 const struct radv_dynamic_state *src)
97 {
98 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
99 uint32_t copy_mask = src->mask;
100 uint32_t dest_mask = 0;
101
102 /* Make sure to copy the number of viewports/scissors because they can
103 * only be specified at pipeline creation time.
104 */
105 dest->viewport.count = src->viewport.count;
106 dest->scissor.count = src->scissor.count;
107 dest->discard_rectangle.count = src->discard_rectangle.count;
108
109 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
110 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
111 src->viewport.count * sizeof(VkViewport))) {
112 typed_memcpy(dest->viewport.viewports,
113 src->viewport.viewports,
114 src->viewport.count);
115 dest_mask |= RADV_DYNAMIC_VIEWPORT;
116 }
117 }
118
119 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
120 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
121 src->scissor.count * sizeof(VkRect2D))) {
122 typed_memcpy(dest->scissor.scissors,
123 src->scissor.scissors, src->scissor.count);
124 dest_mask |= RADV_DYNAMIC_SCISSOR;
125 }
126 }
127
128 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
129 if (dest->line_width != src->line_width) {
130 dest->line_width = src->line_width;
131 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
132 }
133 }
134
135 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
136 if (memcmp(&dest->depth_bias, &src->depth_bias,
137 sizeof(src->depth_bias))) {
138 dest->depth_bias = src->depth_bias;
139 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
140 }
141 }
142
143 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
144 if (memcmp(&dest->blend_constants, &src->blend_constants,
145 sizeof(src->blend_constants))) {
146 typed_memcpy(dest->blend_constants,
147 src->blend_constants, 4);
148 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
149 }
150 }
151
152 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
153 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
154 sizeof(src->depth_bounds))) {
155 dest->depth_bounds = src->depth_bounds;
156 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
157 }
158 }
159
160 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
161 if (memcmp(&dest->stencil_compare_mask,
162 &src->stencil_compare_mask,
163 sizeof(src->stencil_compare_mask))) {
164 dest->stencil_compare_mask = src->stencil_compare_mask;
165 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
166 }
167 }
168
169 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
170 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
171 sizeof(src->stencil_write_mask))) {
172 dest->stencil_write_mask = src->stencil_write_mask;
173 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
174 }
175 }
176
177 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
178 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
179 sizeof(src->stencil_reference))) {
180 dest->stencil_reference = src->stencil_reference;
181 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
182 }
183 }
184
185 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
186 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
187 src->discard_rectangle.count * sizeof(VkRect2D))) {
188 typed_memcpy(dest->discard_rectangle.rectangles,
189 src->discard_rectangle.rectangles,
190 src->discard_rectangle.count);
191 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
192 }
193 }
194
195 cmd_buffer->state.dirty |= dest_mask;
196 }
197
198 static void
199 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
200 struct radv_pipeline *pipeline)
201 {
202 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
203 struct radv_shader_info *info;
204
205 if (!pipeline->streamout_shader)
206 return;
207
208 info = &pipeline->streamout_shader->info.info;
209 for (int i = 0; i < MAX_SO_BUFFERS; i++)
210 so->stride_in_dw[i] = info->so.strides[i];
211
212 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
213 }
214
215 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
216 {
217 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
218 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
219 }
220
221 enum ring_type radv_queue_family_to_ring(int f) {
222 switch (f) {
223 case RADV_QUEUE_GENERAL:
224 return RING_GFX;
225 case RADV_QUEUE_COMPUTE:
226 return RING_COMPUTE;
227 case RADV_QUEUE_TRANSFER:
228 return RING_DMA;
229 default:
230 unreachable("Unknown queue family");
231 }
232 }
233
234 static VkResult radv_create_cmd_buffer(
235 struct radv_device * device,
236 struct radv_cmd_pool * pool,
237 VkCommandBufferLevel level,
238 VkCommandBuffer* pCommandBuffer)
239 {
240 struct radv_cmd_buffer *cmd_buffer;
241 unsigned ring;
242 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
243 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
244 if (cmd_buffer == NULL)
245 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
246
247 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
248 cmd_buffer->device = device;
249 cmd_buffer->pool = pool;
250 cmd_buffer->level = level;
251
252 if (pool) {
253 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
254 cmd_buffer->queue_family_index = pool->queue_family_index;
255
256 } else {
257 /* Init the pool_link so we can safely call list_del when we destroy
258 * the command buffer
259 */
260 list_inithead(&cmd_buffer->pool_link);
261 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
262 }
263
264 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
265
266 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
267 if (!cmd_buffer->cs) {
268 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
269 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
270 }
271
272 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
273
274 list_inithead(&cmd_buffer->upload.list);
275
276 return VK_SUCCESS;
277 }
278
279 static void
280 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
281 {
282 list_del(&cmd_buffer->pool_link);
283
284 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
285 &cmd_buffer->upload.list, list) {
286 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
287 list_del(&up->list);
288 free(up);
289 }
290
291 if (cmd_buffer->upload.upload_bo)
292 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
293 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
294
295 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
296 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
297
298 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
299 }
300
301 static VkResult
302 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
303 {
304
305 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
306
307 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
308 &cmd_buffer->upload.list, list) {
309 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
310 list_del(&up->list);
311 free(up);
312 }
313
314 cmd_buffer->push_constant_stages = 0;
315 cmd_buffer->scratch_size_needed = 0;
316 cmd_buffer->compute_scratch_size_needed = 0;
317 cmd_buffer->esgs_ring_size_needed = 0;
318 cmd_buffer->gsvs_ring_size_needed = 0;
319 cmd_buffer->tess_rings_needed = false;
320 cmd_buffer->sample_positions_needed = false;
321
322 if (cmd_buffer->upload.upload_bo)
323 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
324 cmd_buffer->upload.upload_bo);
325 cmd_buffer->upload.offset = 0;
326
327 cmd_buffer->record_result = VK_SUCCESS;
328
329 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
330 cmd_buffer->descriptors[i].dirty = 0;
331 cmd_buffer->descriptors[i].valid = 0;
332 cmd_buffer->descriptors[i].push_dirty = false;
333 }
334
335 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
336 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
337 unsigned eop_bug_offset;
338 void *fence_ptr;
339
340 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
341 &cmd_buffer->gfx9_fence_offset,
342 &fence_ptr);
343 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
344
345 /* Allocate a buffer for the EOP bug on GFX9. */
346 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 0,
347 &eop_bug_offset, &fence_ptr);
348 cmd_buffer->gfx9_eop_bug_va =
349 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
350 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
351 }
352
353 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
354
355 return cmd_buffer->record_result;
356 }
357
358 static bool
359 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
360 uint64_t min_needed)
361 {
362 uint64_t new_size;
363 struct radeon_winsys_bo *bo;
364 struct radv_cmd_buffer_upload *upload;
365 struct radv_device *device = cmd_buffer->device;
366
367 new_size = MAX2(min_needed, 16 * 1024);
368 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
369
370 bo = device->ws->buffer_create(device->ws,
371 new_size, 4096,
372 RADEON_DOMAIN_GTT,
373 RADEON_FLAG_CPU_ACCESS|
374 RADEON_FLAG_NO_INTERPROCESS_SHARING |
375 RADEON_FLAG_32BIT);
376
377 if (!bo) {
378 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
379 return false;
380 }
381
382 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
383 if (cmd_buffer->upload.upload_bo) {
384 upload = malloc(sizeof(*upload));
385
386 if (!upload) {
387 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
388 device->ws->buffer_destroy(bo);
389 return false;
390 }
391
392 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
393 list_add(&upload->list, &cmd_buffer->upload.list);
394 }
395
396 cmd_buffer->upload.upload_bo = bo;
397 cmd_buffer->upload.size = new_size;
398 cmd_buffer->upload.offset = 0;
399 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
400
401 if (!cmd_buffer->upload.map) {
402 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
403 return false;
404 }
405
406 return true;
407 }
408
409 bool
410 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
411 unsigned size,
412 unsigned alignment,
413 unsigned *out_offset,
414 void **ptr)
415 {
416 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
417 if (offset + size > cmd_buffer->upload.size) {
418 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
419 return false;
420 offset = 0;
421 }
422
423 *out_offset = offset;
424 *ptr = cmd_buffer->upload.map + offset;
425
426 cmd_buffer->upload.offset = offset + size;
427 return true;
428 }
429
430 bool
431 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
432 unsigned size, unsigned alignment,
433 const void *data, unsigned *out_offset)
434 {
435 uint8_t *ptr;
436
437 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
438 out_offset, (void **)&ptr))
439 return false;
440
441 if (ptr)
442 memcpy(ptr, data, size);
443
444 return true;
445 }
446
447 static void
448 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
449 unsigned count, const uint32_t *data)
450 {
451 struct radeon_cmdbuf *cs = cmd_buffer->cs;
452
453 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
454
455 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
456 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
457 S_370_WR_CONFIRM(1) |
458 S_370_ENGINE_SEL(V_370_ME));
459 radeon_emit(cs, va);
460 radeon_emit(cs, va >> 32);
461 radeon_emit_array(cs, data, count);
462 }
463
464 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
465 {
466 struct radv_device *device = cmd_buffer->device;
467 struct radeon_cmdbuf *cs = cmd_buffer->cs;
468 uint64_t va;
469
470 va = radv_buffer_get_va(device->trace_bo);
471 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
472 va += 4;
473
474 ++cmd_buffer->state.trace_id;
475 radv_emit_write_data_packet(cmd_buffer, va, 1,
476 &cmd_buffer->state.trace_id);
477
478 radeon_check_space(cmd_buffer->device->ws, cs, 2);
479
480 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
481 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
482 }
483
484 static void
485 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
486 enum radv_cmd_flush_bits flags)
487 {
488 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
489 uint32_t *ptr = NULL;
490 uint64_t va = 0;
491
492 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
493 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
494
495 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
496 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
497 cmd_buffer->gfx9_fence_offset;
498 ptr = &cmd_buffer->gfx9_fence_idx;
499 }
500
501 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
502
503 /* Force wait for graphics or compute engines to be idle. */
504 si_cs_emit_cache_flush(cmd_buffer->cs,
505 cmd_buffer->device->physical_device->rad_info.chip_class,
506 ptr, va,
507 radv_cmd_buffer_uses_mec(cmd_buffer),
508 flags, cmd_buffer->gfx9_eop_bug_va);
509 }
510
511 if (unlikely(cmd_buffer->device->trace_bo))
512 radv_cmd_buffer_trace_emit(cmd_buffer);
513 }
514
515 static void
516 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
517 struct radv_pipeline *pipeline, enum ring_type ring)
518 {
519 struct radv_device *device = cmd_buffer->device;
520 uint32_t data[2];
521 uint64_t va;
522
523 va = radv_buffer_get_va(device->trace_bo);
524
525 switch (ring) {
526 case RING_GFX:
527 va += 8;
528 break;
529 case RING_COMPUTE:
530 va += 16;
531 break;
532 default:
533 assert(!"invalid ring type");
534 }
535
536 data[0] = (uintptr_t)pipeline;
537 data[1] = (uintptr_t)pipeline >> 32;
538
539 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
540 }
541
542 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
543 VkPipelineBindPoint bind_point,
544 struct radv_descriptor_set *set,
545 unsigned idx)
546 {
547 struct radv_descriptor_state *descriptors_state =
548 radv_get_descriptors_state(cmd_buffer, bind_point);
549
550 descriptors_state->sets[idx] = set;
551
552 descriptors_state->valid |= (1u << idx); /* active descriptors */
553 descriptors_state->dirty |= (1u << idx);
554 }
555
556 static void
557 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
558 VkPipelineBindPoint bind_point)
559 {
560 struct radv_descriptor_state *descriptors_state =
561 radv_get_descriptors_state(cmd_buffer, bind_point);
562 struct radv_device *device = cmd_buffer->device;
563 uint32_t data[MAX_SETS * 2] = {};
564 uint64_t va;
565 unsigned i;
566 va = radv_buffer_get_va(device->trace_bo) + 24;
567
568 for_each_bit(i, descriptors_state->valid) {
569 struct radv_descriptor_set *set = descriptors_state->sets[i];
570 data[i * 2] = (uintptr_t)set;
571 data[i * 2 + 1] = (uintptr_t)set >> 32;
572 }
573
574 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
575 }
576
577 struct radv_userdata_info *
578 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
579 gl_shader_stage stage,
580 int idx)
581 {
582 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
583 return &shader->info.user_sgprs_locs.shader_data[idx];
584 }
585
586 static void
587 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
588 struct radv_pipeline *pipeline,
589 gl_shader_stage stage,
590 int idx, uint64_t va)
591 {
592 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
593 uint32_t base_reg = pipeline->user_data_0[stage];
594 if (loc->sgpr_idx == -1)
595 return;
596
597 assert(loc->num_sgprs == 1);
598 assert(!loc->indirect);
599
600 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
601 base_reg + loc->sgpr_idx * 4, va, false);
602 }
603
604 static void
605 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
606 struct radv_pipeline *pipeline,
607 struct radv_descriptor_state *descriptors_state,
608 gl_shader_stage stage)
609 {
610 struct radv_device *device = cmd_buffer->device;
611 struct radeon_cmdbuf *cs = cmd_buffer->cs;
612 uint32_t sh_base = pipeline->user_data_0[stage];
613 struct radv_userdata_locations *locs =
614 &pipeline->shaders[stage]->info.user_sgprs_locs;
615 unsigned mask = locs->descriptor_sets_enabled;
616
617 mask &= descriptors_state->dirty & descriptors_state->valid;
618
619 while (mask) {
620 int start, count;
621
622 u_bit_scan_consecutive_range(&mask, &start, &count);
623
624 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
625 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
626
627 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
628 for (int i = 0; i < count; i++) {
629 struct radv_descriptor_set *set =
630 descriptors_state->sets[start + i];
631
632 radv_emit_shader_pointer_body(device, cs, set->va, true);
633 }
634 }
635 }
636
637 static void
638 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
639 struct radv_pipeline *pipeline)
640 {
641 int num_samples = pipeline->graphics.ms.num_samples;
642 struct radv_multisample_state *ms = &pipeline->graphics.ms;
643 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
644
645 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
646 cmd_buffer->sample_positions_needed = true;
647
648 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
649 return;
650
651 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
652 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
653 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
654
655 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
656
657 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
658
659 /* GFX9: Flush DFSM when the AA mode changes. */
660 if (cmd_buffer->device->dfsm_allowed) {
661 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
662 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
663 }
664 }
665
666 static void
667 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
668 struct radv_shader_variant *shader)
669 {
670 uint64_t va;
671
672 if (!shader)
673 return;
674
675 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
676
677 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
678 }
679
680 static void
681 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
682 struct radv_pipeline *pipeline,
683 bool vertex_stage_only)
684 {
685 struct radv_cmd_state *state = &cmd_buffer->state;
686 uint32_t mask = state->prefetch_L2_mask;
687
688 if (vertex_stage_only) {
689 /* Fast prefetch path for starting draws as soon as possible.
690 */
691 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
692 RADV_PREFETCH_VBO_DESCRIPTORS);
693 }
694
695 if (mask & RADV_PREFETCH_VS)
696 radv_emit_shader_prefetch(cmd_buffer,
697 pipeline->shaders[MESA_SHADER_VERTEX]);
698
699 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
700 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
701
702 if (mask & RADV_PREFETCH_TCS)
703 radv_emit_shader_prefetch(cmd_buffer,
704 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
705
706 if (mask & RADV_PREFETCH_TES)
707 radv_emit_shader_prefetch(cmd_buffer,
708 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
709
710 if (mask & RADV_PREFETCH_GS) {
711 radv_emit_shader_prefetch(cmd_buffer,
712 pipeline->shaders[MESA_SHADER_GEOMETRY]);
713 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
714 }
715
716 if (mask & RADV_PREFETCH_PS)
717 radv_emit_shader_prefetch(cmd_buffer,
718 pipeline->shaders[MESA_SHADER_FRAGMENT]);
719
720 state->prefetch_L2_mask &= ~mask;
721 }
722
723 static void
724 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
725 {
726 if (!cmd_buffer->device->physical_device->rbplus_allowed)
727 return;
728
729 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
730 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
731 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
732
733 unsigned sx_ps_downconvert = 0;
734 unsigned sx_blend_opt_epsilon = 0;
735 unsigned sx_blend_opt_control = 0;
736
737 for (unsigned i = 0; i < subpass->color_count; ++i) {
738 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
739 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
740 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
741 continue;
742 }
743
744 int idx = subpass->color_attachments[i].attachment;
745 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
746
747 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
748 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
749 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
750 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
751
752 bool has_alpha, has_rgb;
753
754 /* Set if RGB and A are present. */
755 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
756
757 if (format == V_028C70_COLOR_8 ||
758 format == V_028C70_COLOR_16 ||
759 format == V_028C70_COLOR_32)
760 has_rgb = !has_alpha;
761 else
762 has_rgb = true;
763
764 /* Check the colormask and export format. */
765 if (!(colormask & 0x7))
766 has_rgb = false;
767 if (!(colormask & 0x8))
768 has_alpha = false;
769
770 if (spi_format == V_028714_SPI_SHADER_ZERO) {
771 has_rgb = false;
772 has_alpha = false;
773 }
774
775 /* Disable value checking for disabled channels. */
776 if (!has_rgb)
777 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
778 if (!has_alpha)
779 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
780
781 /* Enable down-conversion for 32bpp and smaller formats. */
782 switch (format) {
783 case V_028C70_COLOR_8:
784 case V_028C70_COLOR_8_8:
785 case V_028C70_COLOR_8_8_8_8:
786 /* For 1 and 2-channel formats, use the superset thereof. */
787 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
788 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
789 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
790 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
791 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
792 }
793 break;
794
795 case V_028C70_COLOR_5_6_5:
796 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
797 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
798 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
799 }
800 break;
801
802 case V_028C70_COLOR_1_5_5_5:
803 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
804 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
805 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
806 }
807 break;
808
809 case V_028C70_COLOR_4_4_4_4:
810 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
811 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
812 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
813 }
814 break;
815
816 case V_028C70_COLOR_32:
817 if (swap == V_028C70_SWAP_STD &&
818 spi_format == V_028714_SPI_SHADER_32_R)
819 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
820 else if (swap == V_028C70_SWAP_ALT_REV &&
821 spi_format == V_028714_SPI_SHADER_32_AR)
822 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
823 break;
824
825 case V_028C70_COLOR_16:
826 case V_028C70_COLOR_16_16:
827 /* For 1-channel formats, use the superset thereof. */
828 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
829 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
830 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
831 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
832 if (swap == V_028C70_SWAP_STD ||
833 swap == V_028C70_SWAP_STD_REV)
834 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
835 else
836 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
837 }
838 break;
839
840 case V_028C70_COLOR_10_11_11:
841 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
842 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
843 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
844 }
845 break;
846
847 case V_028C70_COLOR_2_10_10_10:
848 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
849 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
850 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
851 }
852 break;
853 }
854 }
855
856 for (unsigned i = subpass->color_count; i < 8; ++i) {
857 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
858 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
859 }
860 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
861 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
862 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
863 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
864 }
865
866 static void
867 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
868 {
869 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
870
871 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
872 return;
873
874 radv_update_multisample_state(cmd_buffer, pipeline);
875
876 cmd_buffer->scratch_size_needed =
877 MAX2(cmd_buffer->scratch_size_needed,
878 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
879
880 if (!cmd_buffer->state.emitted_pipeline ||
881 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
882 pipeline->graphics.can_use_guardband)
883 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
884
885 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
886
887 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
888 if (!pipeline->shaders[i])
889 continue;
890
891 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
892 pipeline->shaders[i]->bo);
893 }
894
895 if (radv_pipeline_has_gs(pipeline))
896 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
897 pipeline->gs_copy_shader->bo);
898
899 if (unlikely(cmd_buffer->device->trace_bo))
900 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
901
902 cmd_buffer->state.emitted_pipeline = pipeline;
903
904 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
905 }
906
907 static void
908 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
909 {
910 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
911 cmd_buffer->state.dynamic.viewport.viewports);
912 }
913
914 static void
915 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
916 {
917 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
918
919 si_write_scissors(cmd_buffer->cs, 0, count,
920 cmd_buffer->state.dynamic.scissor.scissors,
921 cmd_buffer->state.dynamic.viewport.viewports,
922 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
923 }
924
925 static void
926 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
927 {
928 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
929 return;
930
931 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
932 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
933 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
934 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
935 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
936 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
937 S_028214_BR_Y(rect.offset.y + rect.extent.height));
938 }
939 }
940
941 static void
942 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
943 {
944 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
945
946 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
947 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
948 }
949
950 static void
951 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
952 {
953 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
954
955 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
956 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
957 }
958
959 static void
960 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
961 {
962 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
963
964 radeon_set_context_reg_seq(cmd_buffer->cs,
965 R_028430_DB_STENCILREFMASK, 2);
966 radeon_emit(cmd_buffer->cs,
967 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
968 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
969 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
970 S_028430_STENCILOPVAL(1));
971 radeon_emit(cmd_buffer->cs,
972 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
973 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
974 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
975 S_028434_STENCILOPVAL_BF(1));
976 }
977
978 static void
979 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
980 {
981 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
982
983 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
984 fui(d->depth_bounds.min));
985 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
986 fui(d->depth_bounds.max));
987 }
988
989 static void
990 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
991 {
992 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
993 unsigned slope = fui(d->depth_bias.slope * 16.0f);
994 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
995
996
997 radeon_set_context_reg_seq(cmd_buffer->cs,
998 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
999 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1000 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1001 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1002 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1003 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1004 }
1005
1006 static void
1007 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1008 int index,
1009 struct radv_attachment_info *att,
1010 struct radv_image *image,
1011 VkImageLayout layout)
1012 {
1013 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1014 struct radv_color_buffer_info *cb = &att->cb;
1015 uint32_t cb_color_info = cb->cb_color_info;
1016
1017 if (!radv_layout_dcc_compressed(image, layout,
1018 radv_image_queue_family_mask(image,
1019 cmd_buffer->queue_family_index,
1020 cmd_buffer->queue_family_index))) {
1021 cb_color_info &= C_028C70_DCC_ENABLE;
1022 }
1023
1024 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1025 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1026 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1027 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1028 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1029 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1030 radeon_emit(cmd_buffer->cs, cb_color_info);
1031 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1032 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1033 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1034 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1035 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1036 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1037
1038 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1039 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1040 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1041
1042 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1043 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1044 } else {
1045 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1046 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1047 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1048 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1049 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1050 radeon_emit(cmd_buffer->cs, cb_color_info);
1051 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1052 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1053 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1054 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1055 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1056 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1057
1058 if (is_vi) { /* DCC BASE */
1059 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1060 }
1061 }
1062
1063 if (radv_image_has_dcc(image)) {
1064 /* Drawing with DCC enabled also compresses colorbuffers. */
1065 radv_update_dcc_metadata(cmd_buffer, image, true);
1066 }
1067 }
1068
1069 static void
1070 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1071 struct radv_ds_buffer_info *ds,
1072 struct radv_image *image, VkImageLayout layout,
1073 bool requires_cond_exec)
1074 {
1075 uint32_t db_z_info = ds->db_z_info;
1076 uint32_t db_z_info_reg;
1077
1078 if (!radv_image_is_tc_compat_htile(image))
1079 return;
1080
1081 if (!radv_layout_has_htile(image, layout,
1082 radv_image_queue_family_mask(image,
1083 cmd_buffer->queue_family_index,
1084 cmd_buffer->queue_family_index))) {
1085 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1086 }
1087
1088 db_z_info &= C_028040_ZRANGE_PRECISION;
1089
1090 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1091 db_z_info_reg = R_028038_DB_Z_INFO;
1092 } else {
1093 db_z_info_reg = R_028040_DB_Z_INFO;
1094 }
1095
1096 /* When we don't know the last fast clear value we need to emit a
1097 * conditional packet that will eventually skip the following
1098 * SET_CONTEXT_REG packet.
1099 */
1100 if (requires_cond_exec) {
1101 uint64_t va = radv_buffer_get_va(image->bo);
1102 va += image->offset + image->tc_compat_zrange_offset;
1103
1104 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1105 radeon_emit(cmd_buffer->cs, va);
1106 radeon_emit(cmd_buffer->cs, va >> 32);
1107 radeon_emit(cmd_buffer->cs, 0);
1108 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1109 }
1110
1111 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1112 }
1113
1114 static void
1115 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1116 struct radv_ds_buffer_info *ds,
1117 struct radv_image *image,
1118 VkImageLayout layout)
1119 {
1120 uint32_t db_z_info = ds->db_z_info;
1121 uint32_t db_stencil_info = ds->db_stencil_info;
1122
1123 if (!radv_layout_has_htile(image, layout,
1124 radv_image_queue_family_mask(image,
1125 cmd_buffer->queue_family_index,
1126 cmd_buffer->queue_family_index))) {
1127 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1128 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1129 }
1130
1131 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1132 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1133
1134
1135 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1136 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1137 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1138 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1139 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1140
1141 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1142 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1143 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1144 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1145 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1146 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1147 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1148 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1149 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1150 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1151 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1152
1153 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1154 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1155 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1156 } else {
1157 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1158
1159 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1160 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1161 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1162 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1163 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1164 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1165 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1166 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1167 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1168 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1169
1170 }
1171
1172 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1173 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1174
1175 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1176 ds->pa_su_poly_offset_db_fmt_cntl);
1177 }
1178
1179 /**
1180 * Update the fast clear depth/stencil values if the image is bound as a
1181 * depth/stencil buffer.
1182 */
1183 static void
1184 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1185 struct radv_image *image,
1186 VkClearDepthStencilValue ds_clear_value,
1187 VkImageAspectFlags aspects)
1188 {
1189 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1190 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1191 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1192 struct radv_attachment_info *att;
1193 uint32_t att_idx;
1194
1195 if (!framebuffer || !subpass)
1196 return;
1197
1198 att_idx = subpass->depth_stencil_attachment.attachment;
1199 if (att_idx == VK_ATTACHMENT_UNUSED)
1200 return;
1201
1202 att = &framebuffer->attachments[att_idx];
1203 if (att->attachment->image != image)
1204 return;
1205
1206 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1207 radeon_emit(cs, ds_clear_value.stencil);
1208 radeon_emit(cs, fui(ds_clear_value.depth));
1209
1210 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1211 * only needed when clearing Z to 0.0.
1212 */
1213 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1214 ds_clear_value.depth == 0.0) {
1215 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1216
1217 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1218 layout, false);
1219 }
1220 }
1221
1222 /**
1223 * Set the clear depth/stencil values to the image's metadata.
1224 */
1225 static void
1226 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1227 struct radv_image *image,
1228 VkClearDepthStencilValue ds_clear_value,
1229 VkImageAspectFlags aspects)
1230 {
1231 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1232 uint64_t va = radv_buffer_get_va(image->bo);
1233 unsigned reg_offset = 0, reg_count = 0;
1234
1235 va += image->offset + image->clear_value_offset;
1236
1237 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1238 ++reg_count;
1239 } else {
1240 ++reg_offset;
1241 va += 4;
1242 }
1243 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1244 ++reg_count;
1245
1246 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1247 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1248 S_370_WR_CONFIRM(1) |
1249 S_370_ENGINE_SEL(V_370_PFP));
1250 radeon_emit(cs, va);
1251 radeon_emit(cs, va >> 32);
1252 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1253 radeon_emit(cs, ds_clear_value.stencil);
1254 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1255 radeon_emit(cs, fui(ds_clear_value.depth));
1256 }
1257
1258 /**
1259 * Update the TC-compat metadata value for this image.
1260 */
1261 static void
1262 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1263 struct radv_image *image,
1264 uint32_t value)
1265 {
1266 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1267 uint64_t va = radv_buffer_get_va(image->bo);
1268 va += image->offset + image->tc_compat_zrange_offset;
1269
1270 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1271 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1272 S_370_WR_CONFIRM(1) |
1273 S_370_ENGINE_SEL(V_370_PFP));
1274 radeon_emit(cs, va);
1275 radeon_emit(cs, va >> 32);
1276 radeon_emit(cs, value);
1277 }
1278
1279 static void
1280 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1281 struct radv_image *image,
1282 VkClearDepthStencilValue ds_clear_value)
1283 {
1284 uint64_t va = radv_buffer_get_va(image->bo);
1285 va += image->offset + image->tc_compat_zrange_offset;
1286 uint32_t cond_val;
1287
1288 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1289 * depth clear value is 0.0f.
1290 */
1291 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1292
1293 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, cond_val);
1294 }
1295
1296 /**
1297 * Update the clear depth/stencil values for this image.
1298 */
1299 void
1300 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1301 struct radv_image *image,
1302 VkClearDepthStencilValue ds_clear_value,
1303 VkImageAspectFlags aspects)
1304 {
1305 assert(radv_image_has_htile(image));
1306
1307 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1308
1309 if (radv_image_is_tc_compat_htile(image) &&
1310 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1311 radv_update_tc_compat_zrange_metadata(cmd_buffer, image,
1312 ds_clear_value);
1313 }
1314
1315 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1316 aspects);
1317 }
1318
1319 /**
1320 * Load the clear depth/stencil values from the image's metadata.
1321 */
1322 static void
1323 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1324 struct radv_image *image)
1325 {
1326 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1327 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1328 uint64_t va = radv_buffer_get_va(image->bo);
1329 unsigned reg_offset = 0, reg_count = 0;
1330
1331 va += image->offset + image->clear_value_offset;
1332
1333 if (!radv_image_has_htile(image))
1334 return;
1335
1336 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1337 ++reg_count;
1338 } else {
1339 ++reg_offset;
1340 va += 4;
1341 }
1342 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1343 ++reg_count;
1344
1345 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1346
1347 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1348 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1349 radeon_emit(cs, va);
1350 radeon_emit(cs, va >> 32);
1351 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1352 radeon_emit(cs, reg_count);
1353 } else {
1354 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1355 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1356 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1357 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1358 radeon_emit(cs, va);
1359 radeon_emit(cs, va >> 32);
1360 radeon_emit(cs, reg >> 2);
1361 radeon_emit(cs, 0);
1362
1363 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1364 radeon_emit(cs, 0);
1365 }
1366 }
1367
1368 /*
1369 * With DCC some colors don't require CMASK elimination before being
1370 * used as a texture. This sets a predicate value to determine if the
1371 * cmask eliminate is required.
1372 */
1373 void
1374 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1375 struct radv_image *image, bool value)
1376 {
1377 uint64_t pred_val = value;
1378 uint64_t va = radv_buffer_get_va(image->bo);
1379 va += image->offset + image->fce_pred_offset;
1380
1381 assert(radv_image_has_dcc(image));
1382
1383 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1384 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1385 S_370_WR_CONFIRM(1) |
1386 S_370_ENGINE_SEL(V_370_PFP));
1387 radeon_emit(cmd_buffer->cs, va);
1388 radeon_emit(cmd_buffer->cs, va >> 32);
1389 radeon_emit(cmd_buffer->cs, pred_val);
1390 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1391 }
1392
1393 /**
1394 * Update the DCC predicate to reflect the compression state.
1395 */
1396 void
1397 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1398 struct radv_image *image, bool value)
1399 {
1400 uint64_t pred_val = value;
1401 uint64_t va = radv_buffer_get_va(image->bo);
1402 va += image->offset + image->dcc_pred_offset;
1403
1404 assert(radv_image_has_dcc(image));
1405
1406 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1407 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1408 S_370_WR_CONFIRM(1) |
1409 S_370_ENGINE_SEL(V_370_PFP));
1410 radeon_emit(cmd_buffer->cs, va);
1411 radeon_emit(cmd_buffer->cs, va >> 32);
1412 radeon_emit(cmd_buffer->cs, pred_val);
1413 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1414 }
1415
1416 /**
1417 * Update the fast clear color values if the image is bound as a color buffer.
1418 */
1419 static void
1420 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1421 struct radv_image *image,
1422 int cb_idx,
1423 uint32_t color_values[2])
1424 {
1425 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1426 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1427 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1428 struct radv_attachment_info *att;
1429 uint32_t att_idx;
1430
1431 if (!framebuffer || !subpass)
1432 return;
1433
1434 att_idx = subpass->color_attachments[cb_idx].attachment;
1435 if (att_idx == VK_ATTACHMENT_UNUSED)
1436 return;
1437
1438 att = &framebuffer->attachments[att_idx];
1439 if (att->attachment->image != image)
1440 return;
1441
1442 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1443 radeon_emit(cs, color_values[0]);
1444 radeon_emit(cs, color_values[1]);
1445 }
1446
1447 /**
1448 * Set the clear color values to the image's metadata.
1449 */
1450 static void
1451 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1452 struct radv_image *image,
1453 uint32_t color_values[2])
1454 {
1455 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1456 uint64_t va = radv_buffer_get_va(image->bo);
1457
1458 va += image->offset + image->clear_value_offset;
1459
1460 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1461
1462 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1463 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1464 S_370_WR_CONFIRM(1) |
1465 S_370_ENGINE_SEL(V_370_PFP));
1466 radeon_emit(cs, va);
1467 radeon_emit(cs, va >> 32);
1468 radeon_emit(cs, color_values[0]);
1469 radeon_emit(cs, color_values[1]);
1470 }
1471
1472 /**
1473 * Update the clear color values for this image.
1474 */
1475 void
1476 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1477 struct radv_image *image,
1478 int cb_idx,
1479 uint32_t color_values[2])
1480 {
1481 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1482
1483 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
1484
1485 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1486 color_values);
1487 }
1488
1489 /**
1490 * Load the clear color values from the image's metadata.
1491 */
1492 static void
1493 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1494 struct radv_image *image,
1495 int cb_idx)
1496 {
1497 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1498 uint64_t va = radv_buffer_get_va(image->bo);
1499
1500 va += image->offset + image->clear_value_offset;
1501
1502 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1503 return;
1504
1505 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1506
1507 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1508 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1509 radeon_emit(cs, va);
1510 radeon_emit(cs, va >> 32);
1511 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1512 radeon_emit(cs, 2);
1513 } else {
1514 /* TODO: Figure out how to use LOAD_CONTEXT_REG on SI/CIK. */
1515 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1516 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1517 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1518 COPY_DATA_COUNT_SEL);
1519 radeon_emit(cs, va);
1520 radeon_emit(cs, va >> 32);
1521 radeon_emit(cs, reg >> 2);
1522 radeon_emit(cs, 0);
1523
1524 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1525 radeon_emit(cs, 0);
1526 }
1527 }
1528
1529 static void
1530 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1531 {
1532 int i;
1533 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1534 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1535 unsigned num_bpp64_colorbufs = 0;
1536
1537 /* this may happen for inherited secondary recording */
1538 if (!framebuffer)
1539 return;
1540
1541 for (i = 0; i < 8; ++i) {
1542 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1543 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1544 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1545 continue;
1546 }
1547
1548 int idx = subpass->color_attachments[i].attachment;
1549 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1550 struct radv_image *image = att->attachment->image;
1551 VkImageLayout layout = subpass->color_attachments[i].layout;
1552
1553 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1554
1555 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1556 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1557
1558 radv_load_color_clear_metadata(cmd_buffer, image, i);
1559
1560 if (image->surface.bpe >= 8)
1561 num_bpp64_colorbufs++;
1562 }
1563
1564 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1565 int idx = subpass->depth_stencil_attachment.attachment;
1566 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1567 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1568 struct radv_image *image = att->attachment->image;
1569 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1570 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1571 cmd_buffer->queue_family_index,
1572 cmd_buffer->queue_family_index);
1573 /* We currently don't support writing decompressed HTILE */
1574 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1575 radv_layout_is_htile_compressed(image, layout, queue_mask));
1576
1577 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1578
1579 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1580 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1581 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1582 }
1583 radv_load_ds_clear_metadata(cmd_buffer, image);
1584 } else {
1585 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1586 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1587 else
1588 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1589
1590 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1591 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1592 }
1593 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1594 S_028208_BR_X(framebuffer->width) |
1595 S_028208_BR_Y(framebuffer->height));
1596
1597 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1598 uint8_t watermark = 4; /* Default value for VI. */
1599
1600 /* For optimal DCC performance. */
1601 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1602 if (num_bpp64_colorbufs >= 5) {
1603 watermark = 8;
1604 } else {
1605 watermark = 6;
1606 }
1607 }
1608
1609 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
1610 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
1611 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark));
1612 }
1613
1614 if (cmd_buffer->device->dfsm_allowed) {
1615 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1616 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1617 }
1618
1619 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1620 }
1621
1622 static void
1623 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1624 {
1625 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1626 struct radv_cmd_state *state = &cmd_buffer->state;
1627
1628 if (state->index_type != state->last_index_type) {
1629 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1630 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1631 2, state->index_type);
1632 } else {
1633 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1634 radeon_emit(cs, state->index_type);
1635 }
1636
1637 state->last_index_type = state->index_type;
1638 }
1639
1640 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1641 radeon_emit(cs, state->index_va);
1642 radeon_emit(cs, state->index_va >> 32);
1643
1644 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1645 radeon_emit(cs, state->max_index_count);
1646
1647 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1648 }
1649
1650 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1651 {
1652 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1653 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1654 uint32_t pa_sc_mode_cntl_1 =
1655 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1656 uint32_t db_count_control;
1657
1658 if(!cmd_buffer->state.active_occlusion_queries) {
1659 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1660 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1661 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1662 has_perfect_queries) {
1663 /* Re-enable out-of-order rasterization if the
1664 * bound pipeline supports it and if it's has
1665 * been disabled before starting any perfect
1666 * occlusion queries.
1667 */
1668 radeon_set_context_reg(cmd_buffer->cs,
1669 R_028A4C_PA_SC_MODE_CNTL_1,
1670 pa_sc_mode_cntl_1);
1671 }
1672 }
1673 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1674 } else {
1675 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1676 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1677
1678 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1679 db_count_control =
1680 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1681 S_028004_SAMPLE_RATE(sample_rate) |
1682 S_028004_ZPASS_ENABLE(1) |
1683 S_028004_SLICE_EVEN_ENABLE(1) |
1684 S_028004_SLICE_ODD_ENABLE(1);
1685
1686 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1687 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1688 has_perfect_queries) {
1689 /* If the bound pipeline has enabled
1690 * out-of-order rasterization, we should
1691 * disable it before starting any perfect
1692 * occlusion queries.
1693 */
1694 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1695
1696 radeon_set_context_reg(cmd_buffer->cs,
1697 R_028A4C_PA_SC_MODE_CNTL_1,
1698 pa_sc_mode_cntl_1);
1699 }
1700 } else {
1701 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1702 S_028004_SAMPLE_RATE(sample_rate);
1703 }
1704 }
1705
1706 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1707 }
1708
1709 static void
1710 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1711 {
1712 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1713
1714 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1715 radv_emit_viewport(cmd_buffer);
1716
1717 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1718 !cmd_buffer->device->physical_device->has_scissor_bug)
1719 radv_emit_scissor(cmd_buffer);
1720
1721 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1722 radv_emit_line_width(cmd_buffer);
1723
1724 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1725 radv_emit_blend_constants(cmd_buffer);
1726
1727 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1728 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1729 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1730 radv_emit_stencil(cmd_buffer);
1731
1732 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1733 radv_emit_depth_bounds(cmd_buffer);
1734
1735 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1736 radv_emit_depth_bias(cmd_buffer);
1737
1738 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1739 radv_emit_discard_rectangle(cmd_buffer);
1740
1741 cmd_buffer->state.dirty &= ~states;
1742 }
1743
1744 static void
1745 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1746 VkPipelineBindPoint bind_point)
1747 {
1748 struct radv_descriptor_state *descriptors_state =
1749 radv_get_descriptors_state(cmd_buffer, bind_point);
1750 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1751 unsigned bo_offset;
1752
1753 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1754 set->mapped_ptr,
1755 &bo_offset))
1756 return;
1757
1758 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1759 set->va += bo_offset;
1760 }
1761
1762 static void
1763 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1764 VkPipelineBindPoint bind_point)
1765 {
1766 struct radv_descriptor_state *descriptors_state =
1767 radv_get_descriptors_state(cmd_buffer, bind_point);
1768 uint32_t size = MAX_SETS * 4;
1769 uint32_t offset;
1770 void *ptr;
1771
1772 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1773 256, &offset, &ptr))
1774 return;
1775
1776 for (unsigned i = 0; i < MAX_SETS; i++) {
1777 uint32_t *uptr = ((uint32_t *)ptr) + i;
1778 uint64_t set_va = 0;
1779 struct radv_descriptor_set *set = descriptors_state->sets[i];
1780 if (descriptors_state->valid & (1u << i))
1781 set_va = set->va;
1782 uptr[0] = set_va & 0xffffffff;
1783 }
1784
1785 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1786 va += offset;
1787
1788 if (cmd_buffer->state.pipeline) {
1789 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1790 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1791 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1792
1793 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1794 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1795 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1796
1797 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1798 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1799 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1800
1801 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1802 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1803 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1804
1805 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1806 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1807 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1808 }
1809
1810 if (cmd_buffer->state.compute_pipeline)
1811 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1812 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1813 }
1814
1815 static void
1816 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1817 VkShaderStageFlags stages)
1818 {
1819 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1820 VK_PIPELINE_BIND_POINT_COMPUTE :
1821 VK_PIPELINE_BIND_POINT_GRAPHICS;
1822 struct radv_descriptor_state *descriptors_state =
1823 radv_get_descriptors_state(cmd_buffer, bind_point);
1824 struct radv_cmd_state *state = &cmd_buffer->state;
1825 bool flush_indirect_descriptors;
1826
1827 if (!descriptors_state->dirty)
1828 return;
1829
1830 if (descriptors_state->push_dirty)
1831 radv_flush_push_descriptors(cmd_buffer, bind_point);
1832
1833 flush_indirect_descriptors =
1834 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
1835 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
1836 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
1837 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
1838
1839 if (flush_indirect_descriptors)
1840 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1841
1842 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1843 cmd_buffer->cs,
1844 MAX_SETS * MESA_SHADER_STAGES * 4);
1845
1846 if (cmd_buffer->state.pipeline) {
1847 radv_foreach_stage(stage, stages) {
1848 if (!cmd_buffer->state.pipeline->shaders[stage])
1849 continue;
1850
1851 radv_emit_descriptor_pointers(cmd_buffer,
1852 cmd_buffer->state.pipeline,
1853 descriptors_state, stage);
1854 }
1855 }
1856
1857 if (cmd_buffer->state.compute_pipeline &&
1858 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
1859 radv_emit_descriptor_pointers(cmd_buffer,
1860 cmd_buffer->state.compute_pipeline,
1861 descriptors_state,
1862 MESA_SHADER_COMPUTE);
1863 }
1864
1865 descriptors_state->dirty = 0;
1866 descriptors_state->push_dirty = false;
1867
1868 assert(cmd_buffer->cs->cdw <= cdw_max);
1869
1870 if (unlikely(cmd_buffer->device->trace_bo))
1871 radv_save_descriptors(cmd_buffer, bind_point);
1872 }
1873
1874 static void
1875 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1876 VkShaderStageFlags stages)
1877 {
1878 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1879 ? cmd_buffer->state.compute_pipeline
1880 : cmd_buffer->state.pipeline;
1881 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1882 VK_PIPELINE_BIND_POINT_COMPUTE :
1883 VK_PIPELINE_BIND_POINT_GRAPHICS;
1884 struct radv_descriptor_state *descriptors_state =
1885 radv_get_descriptors_state(cmd_buffer, bind_point);
1886 struct radv_pipeline_layout *layout = pipeline->layout;
1887 struct radv_shader_variant *shader, *prev_shader;
1888 unsigned offset;
1889 void *ptr;
1890 uint64_t va;
1891
1892 stages &= cmd_buffer->push_constant_stages;
1893 if (!stages ||
1894 (!layout->push_constant_size && !layout->dynamic_offset_count))
1895 return;
1896
1897 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1898 16 * layout->dynamic_offset_count,
1899 256, &offset, &ptr))
1900 return;
1901
1902 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1903 memcpy((char*)ptr + layout->push_constant_size,
1904 descriptors_state->dynamic_buffers,
1905 16 * layout->dynamic_offset_count);
1906
1907 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1908 va += offset;
1909
1910 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1911 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1912
1913 prev_shader = NULL;
1914 radv_foreach_stage(stage, stages) {
1915 shader = radv_get_shader(pipeline, stage);
1916
1917 /* Avoid redundantly emitting the address for merged stages. */
1918 if (shader && shader != prev_shader) {
1919 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1920 AC_UD_PUSH_CONSTANTS, va);
1921
1922 prev_shader = shader;
1923 }
1924 }
1925
1926 cmd_buffer->push_constant_stages &= ~stages;
1927 assert(cmd_buffer->cs->cdw <= cdw_max);
1928 }
1929
1930 static void
1931 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1932 bool pipeline_is_dirty)
1933 {
1934 if ((pipeline_is_dirty ||
1935 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1936 cmd_buffer->state.pipeline->vertex_elements.count &&
1937 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
1938 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1939 unsigned vb_offset;
1940 void *vb_ptr;
1941 uint32_t i = 0;
1942 uint32_t count = velems->count;
1943 uint64_t va;
1944
1945 /* allocate some descriptor state for vertex buffers */
1946 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1947 &vb_offset, &vb_ptr))
1948 return;
1949
1950 for (i = 0; i < count; i++) {
1951 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1952 uint32_t offset;
1953 int vb = velems->binding[i];
1954 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1955 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1956
1957 va = radv_buffer_get_va(buffer->bo);
1958
1959 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1960 va += offset + buffer->offset;
1961 desc[0] = va;
1962 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1963 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1964 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1965 else
1966 desc[2] = buffer->size - offset;
1967 desc[3] = velems->rsrc_word3[i];
1968 }
1969
1970 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1971 va += vb_offset;
1972
1973 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1974 AC_UD_VS_VERTEX_BUFFERS, va);
1975
1976 cmd_buffer->state.vb_va = va;
1977 cmd_buffer->state.vb_size = count * 16;
1978 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
1979 }
1980 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1981 }
1982
1983 static void
1984 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
1985 {
1986 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1987 struct radv_userdata_info *loc;
1988 uint32_t base_reg;
1989
1990 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
1991 if (!radv_get_shader(pipeline, stage))
1992 continue;
1993
1994 loc = radv_lookup_user_sgpr(pipeline, stage,
1995 AC_UD_STREAMOUT_BUFFERS);
1996 if (loc->sgpr_idx == -1)
1997 continue;
1998
1999 base_reg = pipeline->user_data_0[stage];
2000
2001 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2002 base_reg + loc->sgpr_idx * 4, va, false);
2003 }
2004
2005 if (pipeline->gs_copy_shader) {
2006 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2007 if (loc->sgpr_idx != -1) {
2008 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2009
2010 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2011 base_reg + loc->sgpr_idx * 4, va, false);
2012 }
2013 }
2014 }
2015
2016 static void
2017 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2018 {
2019 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2020 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2021 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2022 unsigned so_offset;
2023 void *so_ptr;
2024 uint64_t va;
2025
2026 /* Allocate some descriptor state for streamout buffers. */
2027 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2028 MAX_SO_BUFFERS * 16, 256,
2029 &so_offset, &so_ptr))
2030 return;
2031
2032 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2033 struct radv_buffer *buffer = sb[i].buffer;
2034 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2035
2036 if (!(so->enabled_mask & (1 << i)))
2037 continue;
2038
2039 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2040
2041 va += sb[i].offset;
2042
2043 /* Set the descriptor.
2044 *
2045 * On VI, the format must be non-INVALID, otherwise
2046 * the buffer will be considered not bound and store
2047 * instructions will be no-ops.
2048 */
2049 desc[0] = va;
2050 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2051 desc[2] = 0xffffffff;
2052 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2053 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2054 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2055 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2056 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2057 }
2058
2059 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2060 va += so_offset;
2061
2062 radv_emit_streamout_buffers(cmd_buffer, va);
2063 }
2064
2065 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2066 }
2067
2068 static void
2069 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2070 {
2071 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2072 radv_flush_streamout_descriptors(cmd_buffer);
2073 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2074 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2075 }
2076
2077 static void
2078 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
2079 bool instanced_draw, bool indirect_draw,
2080 uint32_t draw_vertex_count)
2081 {
2082 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2083 struct radv_cmd_state *state = &cmd_buffer->state;
2084 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2085 uint32_t ia_multi_vgt_param;
2086 int32_t primitive_reset_en;
2087
2088 /* Draw state. */
2089 ia_multi_vgt_param =
2090 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2091 indirect_draw, draw_vertex_count);
2092
2093 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2094 if (info->chip_class >= GFX9) {
2095 radeon_set_uconfig_reg_idx(cs,
2096 R_030960_IA_MULTI_VGT_PARAM,
2097 4, ia_multi_vgt_param);
2098 } else if (info->chip_class >= CIK) {
2099 radeon_set_context_reg_idx(cs,
2100 R_028AA8_IA_MULTI_VGT_PARAM,
2101 1, ia_multi_vgt_param);
2102 } else {
2103 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2104 ia_multi_vgt_param);
2105 }
2106 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2107 }
2108
2109 /* Primitive restart. */
2110 primitive_reset_en =
2111 indexed_draw && state->pipeline->graphics.prim_restart_enable;
2112
2113 if (primitive_reset_en != state->last_primitive_reset_en) {
2114 state->last_primitive_reset_en = primitive_reset_en;
2115 if (info->chip_class >= GFX9) {
2116 radeon_set_uconfig_reg(cs,
2117 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2118 primitive_reset_en);
2119 } else {
2120 radeon_set_context_reg(cs,
2121 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2122 primitive_reset_en);
2123 }
2124 }
2125
2126 if (primitive_reset_en) {
2127 uint32_t primitive_reset_index =
2128 state->index_type ? 0xffffffffu : 0xffffu;
2129
2130 if (primitive_reset_index != state->last_primitive_reset_index) {
2131 radeon_set_context_reg(cs,
2132 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2133 primitive_reset_index);
2134 state->last_primitive_reset_index = primitive_reset_index;
2135 }
2136 }
2137 }
2138
2139 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2140 VkPipelineStageFlags src_stage_mask)
2141 {
2142 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2143 VK_PIPELINE_STAGE_TRANSFER_BIT |
2144 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2145 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2146 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2147 }
2148
2149 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2150 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2151 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2152 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2153 VK_PIPELINE_STAGE_TRANSFER_BIT |
2154 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2155 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2156 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2157 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2158 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2159 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2160 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2161 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2162 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2163 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2164 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2165 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2166 }
2167 }
2168
2169 static enum radv_cmd_flush_bits
2170 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2171 VkAccessFlags src_flags,
2172 struct radv_image *image)
2173 {
2174 bool flush_CB_meta = true, flush_DB_meta = true;
2175 enum radv_cmd_flush_bits flush_bits = 0;
2176 uint32_t b;
2177
2178 if (image) {
2179 if (!radv_image_has_CB_metadata(image))
2180 flush_CB_meta = false;
2181 if (!radv_image_has_htile(image))
2182 flush_DB_meta = false;
2183 }
2184
2185 for_each_bit(b, src_flags) {
2186 switch ((VkAccessFlagBits)(1 << b)) {
2187 case VK_ACCESS_SHADER_WRITE_BIT:
2188 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2189 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2190 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2191 break;
2192 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2193 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2194 if (flush_CB_meta)
2195 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2196 break;
2197 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2198 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2199 if (flush_DB_meta)
2200 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2201 break;
2202 case VK_ACCESS_TRANSFER_WRITE_BIT:
2203 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2204 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2205 RADV_CMD_FLAG_INV_GLOBAL_L2;
2206
2207 if (flush_CB_meta)
2208 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2209 if (flush_DB_meta)
2210 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2211 break;
2212 default:
2213 break;
2214 }
2215 }
2216 return flush_bits;
2217 }
2218
2219 static enum radv_cmd_flush_bits
2220 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2221 VkAccessFlags dst_flags,
2222 struct radv_image *image)
2223 {
2224 bool flush_CB_meta = true, flush_DB_meta = true;
2225 enum radv_cmd_flush_bits flush_bits = 0;
2226 bool flush_CB = true, flush_DB = true;
2227 bool image_is_coherent = false;
2228 uint32_t b;
2229
2230 if (image) {
2231 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2232 flush_CB = false;
2233 flush_DB = false;
2234 }
2235
2236 if (!radv_image_has_CB_metadata(image))
2237 flush_CB_meta = false;
2238 if (!radv_image_has_htile(image))
2239 flush_DB_meta = false;
2240
2241 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2242 if (image->info.samples == 1 &&
2243 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2244 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2245 !vk_format_is_stencil(image->vk_format)) {
2246 /* Single-sample color and single-sample depth
2247 * (not stencil) are coherent with shaders on
2248 * GFX9.
2249 */
2250 image_is_coherent = true;
2251 }
2252 }
2253 }
2254
2255 for_each_bit(b, dst_flags) {
2256 switch ((VkAccessFlagBits)(1 << b)) {
2257 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2258 case VK_ACCESS_INDEX_READ_BIT:
2259 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2260 break;
2261 case VK_ACCESS_UNIFORM_READ_BIT:
2262 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2263 break;
2264 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2265 case VK_ACCESS_TRANSFER_READ_BIT:
2266 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2267 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2268 RADV_CMD_FLAG_INV_GLOBAL_L2;
2269 break;
2270 case VK_ACCESS_SHADER_READ_BIT:
2271 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2272
2273 if (!image_is_coherent)
2274 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2275 break;
2276 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2277 if (flush_CB)
2278 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2279 if (flush_CB_meta)
2280 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2281 break;
2282 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2283 if (flush_DB)
2284 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2285 if (flush_DB_meta)
2286 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2287 break;
2288 default:
2289 break;
2290 }
2291 }
2292 return flush_bits;
2293 }
2294
2295 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2296 const struct radv_subpass_barrier *barrier)
2297 {
2298 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2299 NULL);
2300 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2301 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2302 NULL);
2303 }
2304
2305 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2306 struct radv_subpass_attachment att)
2307 {
2308 unsigned idx = att.attachment;
2309 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2310 VkImageSubresourceRange range;
2311 range.aspectMask = 0;
2312 range.baseMipLevel = view->base_mip;
2313 range.levelCount = 1;
2314 range.baseArrayLayer = view->base_layer;
2315 range.layerCount = cmd_buffer->state.framebuffer->layers;
2316
2317 if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask) {
2318 /* If the current subpass uses multiview, the driver might have
2319 * performed a fast color/depth clear to the whole image
2320 * (including all layers). To make sure the driver will
2321 * decompress the image correctly (if needed), we have to
2322 * account for the "real" number of layers. If the view mask is
2323 * sparse, this will decompress more layers than needed.
2324 */
2325 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
2326 }
2327
2328 radv_handle_image_transition(cmd_buffer,
2329 view->image,
2330 cmd_buffer->state.attachments[idx].current_layout,
2331 att.layout, 0, 0, &range);
2332
2333 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2334
2335
2336 }
2337
2338 void
2339 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2340 const struct radv_subpass *subpass, bool transitions)
2341 {
2342 if (transitions) {
2343 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2344
2345 for (unsigned i = 0; i < subpass->color_count; ++i) {
2346 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2347 radv_handle_subpass_image_transition(cmd_buffer,
2348 subpass->color_attachments[i]);
2349 }
2350
2351 for (unsigned i = 0; i < subpass->input_count; ++i) {
2352 radv_handle_subpass_image_transition(cmd_buffer,
2353 subpass->input_attachments[i]);
2354 }
2355
2356 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2357 radv_handle_subpass_image_transition(cmd_buffer,
2358 subpass->depth_stencil_attachment);
2359 }
2360 }
2361
2362 cmd_buffer->state.subpass = subpass;
2363
2364 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2365 }
2366
2367 static VkResult
2368 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2369 struct radv_render_pass *pass,
2370 const VkRenderPassBeginInfo *info)
2371 {
2372 struct radv_cmd_state *state = &cmd_buffer->state;
2373
2374 if (pass->attachment_count == 0) {
2375 state->attachments = NULL;
2376 return VK_SUCCESS;
2377 }
2378
2379 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2380 pass->attachment_count *
2381 sizeof(state->attachments[0]),
2382 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2383 if (state->attachments == NULL) {
2384 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2385 return cmd_buffer->record_result;
2386 }
2387
2388 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2389 struct radv_render_pass_attachment *att = &pass->attachments[i];
2390 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2391 VkImageAspectFlags clear_aspects = 0;
2392
2393 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2394 /* color attachment */
2395 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2396 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2397 }
2398 } else {
2399 /* depthstencil attachment */
2400 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2401 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2402 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2403 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2404 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2405 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2406 }
2407 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2408 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2409 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2410 }
2411 }
2412
2413 state->attachments[i].pending_clear_aspects = clear_aspects;
2414 state->attachments[i].cleared_views = 0;
2415 if (clear_aspects && info) {
2416 assert(info->clearValueCount > i);
2417 state->attachments[i].clear_value = info->pClearValues[i];
2418 }
2419
2420 state->attachments[i].current_layout = att->initial_layout;
2421 }
2422
2423 return VK_SUCCESS;
2424 }
2425
2426 VkResult radv_AllocateCommandBuffers(
2427 VkDevice _device,
2428 const VkCommandBufferAllocateInfo *pAllocateInfo,
2429 VkCommandBuffer *pCommandBuffers)
2430 {
2431 RADV_FROM_HANDLE(radv_device, device, _device);
2432 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2433
2434 VkResult result = VK_SUCCESS;
2435 uint32_t i;
2436
2437 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2438
2439 if (!list_empty(&pool->free_cmd_buffers)) {
2440 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2441
2442 list_del(&cmd_buffer->pool_link);
2443 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2444
2445 result = radv_reset_cmd_buffer(cmd_buffer);
2446 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2447 cmd_buffer->level = pAllocateInfo->level;
2448
2449 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2450 } else {
2451 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2452 &pCommandBuffers[i]);
2453 }
2454 if (result != VK_SUCCESS)
2455 break;
2456 }
2457
2458 if (result != VK_SUCCESS) {
2459 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2460 i, pCommandBuffers);
2461
2462 /* From the Vulkan 1.0.66 spec:
2463 *
2464 * "vkAllocateCommandBuffers can be used to create multiple
2465 * command buffers. If the creation of any of those command
2466 * buffers fails, the implementation must destroy all
2467 * successfully created command buffer objects from this
2468 * command, set all entries of the pCommandBuffers array to
2469 * NULL and return the error."
2470 */
2471 memset(pCommandBuffers, 0,
2472 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2473 }
2474
2475 return result;
2476 }
2477
2478 void radv_FreeCommandBuffers(
2479 VkDevice device,
2480 VkCommandPool commandPool,
2481 uint32_t commandBufferCount,
2482 const VkCommandBuffer *pCommandBuffers)
2483 {
2484 for (uint32_t i = 0; i < commandBufferCount; i++) {
2485 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2486
2487 if (cmd_buffer) {
2488 if (cmd_buffer->pool) {
2489 list_del(&cmd_buffer->pool_link);
2490 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2491 } else
2492 radv_cmd_buffer_destroy(cmd_buffer);
2493
2494 }
2495 }
2496 }
2497
2498 VkResult radv_ResetCommandBuffer(
2499 VkCommandBuffer commandBuffer,
2500 VkCommandBufferResetFlags flags)
2501 {
2502 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2503 return radv_reset_cmd_buffer(cmd_buffer);
2504 }
2505
2506 VkResult radv_BeginCommandBuffer(
2507 VkCommandBuffer commandBuffer,
2508 const VkCommandBufferBeginInfo *pBeginInfo)
2509 {
2510 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2511 VkResult result = VK_SUCCESS;
2512
2513 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2514 /* If the command buffer has already been resetted with
2515 * vkResetCommandBuffer, no need to do it again.
2516 */
2517 result = radv_reset_cmd_buffer(cmd_buffer);
2518 if (result != VK_SUCCESS)
2519 return result;
2520 }
2521
2522 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2523 cmd_buffer->state.last_primitive_reset_en = -1;
2524 cmd_buffer->state.last_index_type = -1;
2525 cmd_buffer->state.last_num_instances = -1;
2526 cmd_buffer->state.last_vertex_offset = -1;
2527 cmd_buffer->state.last_first_instance = -1;
2528 cmd_buffer->state.predication_type = -1;
2529 cmd_buffer->usage_flags = pBeginInfo->flags;
2530
2531 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
2532 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
2533 assert(pBeginInfo->pInheritanceInfo);
2534 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2535 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2536
2537 struct radv_subpass *subpass =
2538 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2539
2540 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2541 if (result != VK_SUCCESS)
2542 return result;
2543
2544 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2545 }
2546
2547 if (unlikely(cmd_buffer->device->trace_bo)) {
2548 struct radv_device *device = cmd_buffer->device;
2549
2550 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
2551 device->trace_bo);
2552
2553 radv_cmd_buffer_trace_emit(cmd_buffer);
2554 }
2555
2556 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2557
2558 return result;
2559 }
2560
2561 void radv_CmdBindVertexBuffers(
2562 VkCommandBuffer commandBuffer,
2563 uint32_t firstBinding,
2564 uint32_t bindingCount,
2565 const VkBuffer* pBuffers,
2566 const VkDeviceSize* pOffsets)
2567 {
2568 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2569 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2570 bool changed = false;
2571
2572 /* We have to defer setting up vertex buffer since we need the buffer
2573 * stride from the pipeline. */
2574
2575 assert(firstBinding + bindingCount <= MAX_VBS);
2576 for (uint32_t i = 0; i < bindingCount; i++) {
2577 uint32_t idx = firstBinding + i;
2578
2579 if (!changed &&
2580 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2581 vb[idx].offset != pOffsets[i])) {
2582 changed = true;
2583 }
2584
2585 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2586 vb[idx].offset = pOffsets[i];
2587
2588 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2589 vb[idx].buffer->bo);
2590 }
2591
2592 if (!changed) {
2593 /* No state changes. */
2594 return;
2595 }
2596
2597 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2598 }
2599
2600 void radv_CmdBindIndexBuffer(
2601 VkCommandBuffer commandBuffer,
2602 VkBuffer buffer,
2603 VkDeviceSize offset,
2604 VkIndexType indexType)
2605 {
2606 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2607 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2608
2609 if (cmd_buffer->state.index_buffer == index_buffer &&
2610 cmd_buffer->state.index_offset == offset &&
2611 cmd_buffer->state.index_type == indexType) {
2612 /* No state changes. */
2613 return;
2614 }
2615
2616 cmd_buffer->state.index_buffer = index_buffer;
2617 cmd_buffer->state.index_offset = offset;
2618 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2619 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2620 cmd_buffer->state.index_va += index_buffer->offset + offset;
2621
2622 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2623 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2624 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2625 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
2626 }
2627
2628
2629 static void
2630 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2631 VkPipelineBindPoint bind_point,
2632 struct radv_descriptor_set *set, unsigned idx)
2633 {
2634 struct radeon_winsys *ws = cmd_buffer->device->ws;
2635
2636 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2637
2638 assert(set);
2639 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2640
2641 if (!cmd_buffer->device->use_global_bo_list) {
2642 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2643 if (set->descriptors[j])
2644 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
2645 }
2646
2647 if(set->bo)
2648 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
2649 }
2650
2651 void radv_CmdBindDescriptorSets(
2652 VkCommandBuffer commandBuffer,
2653 VkPipelineBindPoint pipelineBindPoint,
2654 VkPipelineLayout _layout,
2655 uint32_t firstSet,
2656 uint32_t descriptorSetCount,
2657 const VkDescriptorSet* pDescriptorSets,
2658 uint32_t dynamicOffsetCount,
2659 const uint32_t* pDynamicOffsets)
2660 {
2661 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2662 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2663 unsigned dyn_idx = 0;
2664
2665 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2666 struct radv_descriptor_state *descriptors_state =
2667 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2668
2669 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2670 unsigned idx = i + firstSet;
2671 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2672 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2673
2674 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2675 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2676 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
2677 assert(dyn_idx < dynamicOffsetCount);
2678
2679 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2680 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2681 dst[0] = va;
2682 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2683 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2684 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2685 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2686 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2687 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2688 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2689 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2690 cmd_buffer->push_constant_stages |=
2691 set->layout->dynamic_shader_stages;
2692 }
2693 }
2694 }
2695
2696 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2697 struct radv_descriptor_set *set,
2698 struct radv_descriptor_set_layout *layout,
2699 VkPipelineBindPoint bind_point)
2700 {
2701 struct radv_descriptor_state *descriptors_state =
2702 radv_get_descriptors_state(cmd_buffer, bind_point);
2703 set->size = layout->size;
2704 set->layout = layout;
2705
2706 if (descriptors_state->push_set.capacity < set->size) {
2707 size_t new_size = MAX2(set->size, 1024);
2708 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2709 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2710
2711 free(set->mapped_ptr);
2712 set->mapped_ptr = malloc(new_size);
2713
2714 if (!set->mapped_ptr) {
2715 descriptors_state->push_set.capacity = 0;
2716 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2717 return false;
2718 }
2719
2720 descriptors_state->push_set.capacity = new_size;
2721 }
2722
2723 return true;
2724 }
2725
2726 void radv_meta_push_descriptor_set(
2727 struct radv_cmd_buffer* cmd_buffer,
2728 VkPipelineBindPoint pipelineBindPoint,
2729 VkPipelineLayout _layout,
2730 uint32_t set,
2731 uint32_t descriptorWriteCount,
2732 const VkWriteDescriptorSet* pDescriptorWrites)
2733 {
2734 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2735 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2736 unsigned bo_offset;
2737
2738 assert(set == 0);
2739 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2740
2741 push_set->size = layout->set[set].layout->size;
2742 push_set->layout = layout->set[set].layout;
2743
2744 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2745 &bo_offset,
2746 (void**) &push_set->mapped_ptr))
2747 return;
2748
2749 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2750 push_set->va += bo_offset;
2751
2752 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2753 radv_descriptor_set_to_handle(push_set),
2754 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2755
2756 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2757 }
2758
2759 void radv_CmdPushDescriptorSetKHR(
2760 VkCommandBuffer commandBuffer,
2761 VkPipelineBindPoint pipelineBindPoint,
2762 VkPipelineLayout _layout,
2763 uint32_t set,
2764 uint32_t descriptorWriteCount,
2765 const VkWriteDescriptorSet* pDescriptorWrites)
2766 {
2767 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2768 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2769 struct radv_descriptor_state *descriptors_state =
2770 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2771 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2772
2773 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2774
2775 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2776 layout->set[set].layout,
2777 pipelineBindPoint))
2778 return;
2779
2780 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2781 radv_descriptor_set_to_handle(push_set),
2782 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2783
2784 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2785 descriptors_state->push_dirty = true;
2786 }
2787
2788 void radv_CmdPushDescriptorSetWithTemplateKHR(
2789 VkCommandBuffer commandBuffer,
2790 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
2791 VkPipelineLayout _layout,
2792 uint32_t set,
2793 const void* pData)
2794 {
2795 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2796 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2797 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2798 struct radv_descriptor_state *descriptors_state =
2799 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2800 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2801
2802 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2803
2804 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2805 layout->set[set].layout,
2806 templ->bind_point))
2807 return;
2808
2809 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2810 descriptorUpdateTemplate, pData);
2811
2812 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2813 descriptors_state->push_dirty = true;
2814 }
2815
2816 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2817 VkPipelineLayout layout,
2818 VkShaderStageFlags stageFlags,
2819 uint32_t offset,
2820 uint32_t size,
2821 const void* pValues)
2822 {
2823 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2824 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2825 cmd_buffer->push_constant_stages |= stageFlags;
2826 }
2827
2828 VkResult radv_EndCommandBuffer(
2829 VkCommandBuffer commandBuffer)
2830 {
2831 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2832
2833 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2834 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2835 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2836 si_emit_cache_flush(cmd_buffer);
2837 }
2838
2839 /* Make sure CP DMA is idle at the end of IBs because the kernel
2840 * doesn't wait for it.
2841 */
2842 si_cp_dma_wait_for_idle(cmd_buffer);
2843
2844 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2845
2846 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2847 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2848
2849 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2850
2851 return cmd_buffer->record_result;
2852 }
2853
2854 static void
2855 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2856 {
2857 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2858
2859 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2860 return;
2861
2862 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2863
2864 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2865 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2866
2867 cmd_buffer->compute_scratch_size_needed =
2868 MAX2(cmd_buffer->compute_scratch_size_needed,
2869 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2870
2871 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2872 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
2873
2874 if (unlikely(cmd_buffer->device->trace_bo))
2875 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2876 }
2877
2878 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2879 VkPipelineBindPoint bind_point)
2880 {
2881 struct radv_descriptor_state *descriptors_state =
2882 radv_get_descriptors_state(cmd_buffer, bind_point);
2883
2884 descriptors_state->dirty |= descriptors_state->valid;
2885 }
2886
2887 void radv_CmdBindPipeline(
2888 VkCommandBuffer commandBuffer,
2889 VkPipelineBindPoint pipelineBindPoint,
2890 VkPipeline _pipeline)
2891 {
2892 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2893 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2894
2895 switch (pipelineBindPoint) {
2896 case VK_PIPELINE_BIND_POINT_COMPUTE:
2897 if (cmd_buffer->state.compute_pipeline == pipeline)
2898 return;
2899 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2900
2901 cmd_buffer->state.compute_pipeline = pipeline;
2902 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2903 break;
2904 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2905 if (cmd_buffer->state.pipeline == pipeline)
2906 return;
2907 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2908
2909 cmd_buffer->state.pipeline = pipeline;
2910 if (!pipeline)
2911 break;
2912
2913 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2914 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2915
2916 /* the new vertex shader might not have the same user regs */
2917 cmd_buffer->state.last_first_instance = -1;
2918 cmd_buffer->state.last_vertex_offset = -1;
2919
2920 /* Prefetch all pipeline shaders at first draw time. */
2921 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
2922
2923 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2924 radv_bind_streamout_state(cmd_buffer, pipeline);
2925
2926 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2927 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2928 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2929 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2930
2931 if (radv_pipeline_has_tess(pipeline))
2932 cmd_buffer->tess_rings_needed = true;
2933 break;
2934 default:
2935 assert(!"invalid bind point");
2936 break;
2937 }
2938 }
2939
2940 void radv_CmdSetViewport(
2941 VkCommandBuffer commandBuffer,
2942 uint32_t firstViewport,
2943 uint32_t viewportCount,
2944 const VkViewport* pViewports)
2945 {
2946 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2947 struct radv_cmd_state *state = &cmd_buffer->state;
2948 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2949
2950 assert(firstViewport < MAX_VIEWPORTS);
2951 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2952
2953 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2954 viewportCount * sizeof(*pViewports));
2955
2956 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2957 }
2958
2959 void radv_CmdSetScissor(
2960 VkCommandBuffer commandBuffer,
2961 uint32_t firstScissor,
2962 uint32_t scissorCount,
2963 const VkRect2D* pScissors)
2964 {
2965 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2966 struct radv_cmd_state *state = &cmd_buffer->state;
2967 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2968
2969 assert(firstScissor < MAX_SCISSORS);
2970 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2971
2972 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2973 scissorCount * sizeof(*pScissors));
2974
2975 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2976 }
2977
2978 void radv_CmdSetLineWidth(
2979 VkCommandBuffer commandBuffer,
2980 float lineWidth)
2981 {
2982 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2983 cmd_buffer->state.dynamic.line_width = lineWidth;
2984 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2985 }
2986
2987 void radv_CmdSetDepthBias(
2988 VkCommandBuffer commandBuffer,
2989 float depthBiasConstantFactor,
2990 float depthBiasClamp,
2991 float depthBiasSlopeFactor)
2992 {
2993 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2994
2995 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2996 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2997 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2998
2999 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3000 }
3001
3002 void radv_CmdSetBlendConstants(
3003 VkCommandBuffer commandBuffer,
3004 const float blendConstants[4])
3005 {
3006 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3007
3008 memcpy(cmd_buffer->state.dynamic.blend_constants,
3009 blendConstants, sizeof(float) * 4);
3010
3011 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3012 }
3013
3014 void radv_CmdSetDepthBounds(
3015 VkCommandBuffer commandBuffer,
3016 float minDepthBounds,
3017 float maxDepthBounds)
3018 {
3019 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3020
3021 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
3022 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
3023
3024 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
3025 }
3026
3027 void radv_CmdSetStencilCompareMask(
3028 VkCommandBuffer commandBuffer,
3029 VkStencilFaceFlags faceMask,
3030 uint32_t compareMask)
3031 {
3032 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3033
3034 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3035 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
3036 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3037 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
3038
3039 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
3040 }
3041
3042 void radv_CmdSetStencilWriteMask(
3043 VkCommandBuffer commandBuffer,
3044 VkStencilFaceFlags faceMask,
3045 uint32_t writeMask)
3046 {
3047 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3048
3049 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3050 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
3051 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3052 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
3053
3054 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
3055 }
3056
3057 void radv_CmdSetStencilReference(
3058 VkCommandBuffer commandBuffer,
3059 VkStencilFaceFlags faceMask,
3060 uint32_t reference)
3061 {
3062 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3063
3064 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3065 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3066 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3067 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3068
3069 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3070 }
3071
3072 void radv_CmdSetDiscardRectangleEXT(
3073 VkCommandBuffer commandBuffer,
3074 uint32_t firstDiscardRectangle,
3075 uint32_t discardRectangleCount,
3076 const VkRect2D* pDiscardRectangles)
3077 {
3078 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3079 struct radv_cmd_state *state = &cmd_buffer->state;
3080 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3081
3082 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3083 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3084
3085 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3086 pDiscardRectangles, discardRectangleCount);
3087
3088 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3089 }
3090
3091 void radv_CmdExecuteCommands(
3092 VkCommandBuffer commandBuffer,
3093 uint32_t commandBufferCount,
3094 const VkCommandBuffer* pCmdBuffers)
3095 {
3096 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3097
3098 assert(commandBufferCount > 0);
3099
3100 /* Emit pending flushes on primary prior to executing secondary */
3101 si_emit_cache_flush(primary);
3102
3103 for (uint32_t i = 0; i < commandBufferCount; i++) {
3104 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3105
3106 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3107 secondary->scratch_size_needed);
3108 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3109 secondary->compute_scratch_size_needed);
3110
3111 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
3112 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
3113 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
3114 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
3115 if (secondary->tess_rings_needed)
3116 primary->tess_rings_needed = true;
3117 if (secondary->sample_positions_needed)
3118 primary->sample_positions_needed = true;
3119
3120 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
3121
3122
3123 /* When the secondary command buffer is compute only we don't
3124 * need to re-emit the current graphics pipeline.
3125 */
3126 if (secondary->state.emitted_pipeline) {
3127 primary->state.emitted_pipeline =
3128 secondary->state.emitted_pipeline;
3129 }
3130
3131 /* When the secondary command buffer is graphics only we don't
3132 * need to re-emit the current compute pipeline.
3133 */
3134 if (secondary->state.emitted_compute_pipeline) {
3135 primary->state.emitted_compute_pipeline =
3136 secondary->state.emitted_compute_pipeline;
3137 }
3138
3139 /* Only re-emit the draw packets when needed. */
3140 if (secondary->state.last_primitive_reset_en != -1) {
3141 primary->state.last_primitive_reset_en =
3142 secondary->state.last_primitive_reset_en;
3143 }
3144
3145 if (secondary->state.last_primitive_reset_index) {
3146 primary->state.last_primitive_reset_index =
3147 secondary->state.last_primitive_reset_index;
3148 }
3149
3150 if (secondary->state.last_ia_multi_vgt_param) {
3151 primary->state.last_ia_multi_vgt_param =
3152 secondary->state.last_ia_multi_vgt_param;
3153 }
3154
3155 primary->state.last_first_instance = secondary->state.last_first_instance;
3156 primary->state.last_num_instances = secondary->state.last_num_instances;
3157 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
3158
3159 if (secondary->state.last_index_type != -1) {
3160 primary->state.last_index_type =
3161 secondary->state.last_index_type;
3162 }
3163 }
3164
3165 /* After executing commands from secondary buffers we have to dirty
3166 * some states.
3167 */
3168 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
3169 RADV_CMD_DIRTY_INDEX_BUFFER |
3170 RADV_CMD_DIRTY_DYNAMIC_ALL;
3171 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
3172 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
3173 }
3174
3175 VkResult radv_CreateCommandPool(
3176 VkDevice _device,
3177 const VkCommandPoolCreateInfo* pCreateInfo,
3178 const VkAllocationCallbacks* pAllocator,
3179 VkCommandPool* pCmdPool)
3180 {
3181 RADV_FROM_HANDLE(radv_device, device, _device);
3182 struct radv_cmd_pool *pool;
3183
3184 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3185 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3186 if (pool == NULL)
3187 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3188
3189 if (pAllocator)
3190 pool->alloc = *pAllocator;
3191 else
3192 pool->alloc = device->alloc;
3193
3194 list_inithead(&pool->cmd_buffers);
3195 list_inithead(&pool->free_cmd_buffers);
3196
3197 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3198
3199 *pCmdPool = radv_cmd_pool_to_handle(pool);
3200
3201 return VK_SUCCESS;
3202
3203 }
3204
3205 void radv_DestroyCommandPool(
3206 VkDevice _device,
3207 VkCommandPool commandPool,
3208 const VkAllocationCallbacks* pAllocator)
3209 {
3210 RADV_FROM_HANDLE(radv_device, device, _device);
3211 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3212
3213 if (!pool)
3214 return;
3215
3216 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3217 &pool->cmd_buffers, pool_link) {
3218 radv_cmd_buffer_destroy(cmd_buffer);
3219 }
3220
3221 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3222 &pool->free_cmd_buffers, pool_link) {
3223 radv_cmd_buffer_destroy(cmd_buffer);
3224 }
3225
3226 vk_free2(&device->alloc, pAllocator, pool);
3227 }
3228
3229 VkResult radv_ResetCommandPool(
3230 VkDevice device,
3231 VkCommandPool commandPool,
3232 VkCommandPoolResetFlags flags)
3233 {
3234 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3235 VkResult result;
3236
3237 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3238 &pool->cmd_buffers, pool_link) {
3239 result = radv_reset_cmd_buffer(cmd_buffer);
3240 if (result != VK_SUCCESS)
3241 return result;
3242 }
3243
3244 return VK_SUCCESS;
3245 }
3246
3247 void radv_TrimCommandPool(
3248 VkDevice device,
3249 VkCommandPool commandPool,
3250 VkCommandPoolTrimFlags flags)
3251 {
3252 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3253
3254 if (!pool)
3255 return;
3256
3257 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3258 &pool->free_cmd_buffers, pool_link) {
3259 radv_cmd_buffer_destroy(cmd_buffer);
3260 }
3261 }
3262
3263 void radv_CmdBeginRenderPass(
3264 VkCommandBuffer commandBuffer,
3265 const VkRenderPassBeginInfo* pRenderPassBegin,
3266 VkSubpassContents contents)
3267 {
3268 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3269 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3270 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3271
3272 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3273 cmd_buffer->cs, 2048);
3274 MAYBE_UNUSED VkResult result;
3275
3276 cmd_buffer->state.framebuffer = framebuffer;
3277 cmd_buffer->state.pass = pass;
3278 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3279
3280 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3281 if (result != VK_SUCCESS)
3282 return;
3283
3284 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
3285 assert(cmd_buffer->cs->cdw <= cdw_max);
3286
3287 radv_cmd_buffer_clear_subpass(cmd_buffer);
3288 }
3289
3290 void radv_CmdBeginRenderPass2KHR(
3291 VkCommandBuffer commandBuffer,
3292 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
3293 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
3294 {
3295 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
3296 pSubpassBeginInfo->contents);
3297 }
3298
3299 void radv_CmdNextSubpass(
3300 VkCommandBuffer commandBuffer,
3301 VkSubpassContents contents)
3302 {
3303 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3304
3305 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3306
3307 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
3308 2048);
3309
3310 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
3311 radv_cmd_buffer_clear_subpass(cmd_buffer);
3312 }
3313
3314 void radv_CmdNextSubpass2KHR(
3315 VkCommandBuffer commandBuffer,
3316 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
3317 const VkSubpassEndInfoKHR* pSubpassEndInfo)
3318 {
3319 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
3320 }
3321
3322 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3323 {
3324 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3325 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3326 if (!radv_get_shader(pipeline, stage))
3327 continue;
3328
3329 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3330 if (loc->sgpr_idx == -1)
3331 continue;
3332 uint32_t base_reg = pipeline->user_data_0[stage];
3333 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3334
3335 }
3336 if (pipeline->gs_copy_shader) {
3337 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3338 if (loc->sgpr_idx != -1) {
3339 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3340 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3341 }
3342 }
3343 }
3344
3345 static void
3346 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3347 uint32_t vertex_count,
3348 bool use_opaque)
3349 {
3350 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3351 radeon_emit(cmd_buffer->cs, vertex_count);
3352 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3353 S_0287F0_USE_OPAQUE(use_opaque));
3354 }
3355
3356 static void
3357 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3358 uint64_t index_va,
3359 uint32_t index_count)
3360 {
3361 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
3362 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3363 radeon_emit(cmd_buffer->cs, index_va);
3364 radeon_emit(cmd_buffer->cs, index_va >> 32);
3365 radeon_emit(cmd_buffer->cs, index_count);
3366 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3367 }
3368
3369 static void
3370 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3371 bool indexed,
3372 uint32_t draw_count,
3373 uint64_t count_va,
3374 uint32_t stride)
3375 {
3376 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3377 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3378 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3379 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
3380 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3381 bool predicating = cmd_buffer->state.predicating;
3382 assert(base_reg);
3383
3384 /* just reset draw state for vertex data */
3385 cmd_buffer->state.last_first_instance = -1;
3386 cmd_buffer->state.last_num_instances = -1;
3387 cmd_buffer->state.last_vertex_offset = -1;
3388
3389 if (draw_count == 1 && !count_va && !draw_id_enable) {
3390 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3391 PKT3_DRAW_INDIRECT, 3, predicating));
3392 radeon_emit(cs, 0);
3393 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3394 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3395 radeon_emit(cs, di_src_sel);
3396 } else {
3397 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3398 PKT3_DRAW_INDIRECT_MULTI,
3399 8, predicating));
3400 radeon_emit(cs, 0);
3401 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3402 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3403 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3404 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3405 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3406 radeon_emit(cs, draw_count); /* count */
3407 radeon_emit(cs, count_va); /* count_addr */
3408 radeon_emit(cs, count_va >> 32);
3409 radeon_emit(cs, stride); /* stride */
3410 radeon_emit(cs, di_src_sel);
3411 }
3412 }
3413
3414 struct radv_draw_info {
3415 /**
3416 * Number of vertices.
3417 */
3418 uint32_t count;
3419
3420 /**
3421 * Index of the first vertex.
3422 */
3423 int32_t vertex_offset;
3424
3425 /**
3426 * First instance id.
3427 */
3428 uint32_t first_instance;
3429
3430 /**
3431 * Number of instances.
3432 */
3433 uint32_t instance_count;
3434
3435 /**
3436 * First index (indexed draws only).
3437 */
3438 uint32_t first_index;
3439
3440 /**
3441 * Whether it's an indexed draw.
3442 */
3443 bool indexed;
3444
3445 /**
3446 * Indirect draw parameters resource.
3447 */
3448 struct radv_buffer *indirect;
3449 uint64_t indirect_offset;
3450 uint32_t stride;
3451
3452 /**
3453 * Draw count parameters resource.
3454 */
3455 struct radv_buffer *count_buffer;
3456 uint64_t count_buffer_offset;
3457
3458 /**
3459 * Stream output parameters resource.
3460 */
3461 struct radv_buffer *strmout_buffer;
3462 uint64_t strmout_buffer_offset;
3463 };
3464
3465 static void
3466 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3467 const struct radv_draw_info *info)
3468 {
3469 struct radv_cmd_state *state = &cmd_buffer->state;
3470 struct radeon_winsys *ws = cmd_buffer->device->ws;
3471 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3472
3473 if (info->strmout_buffer) {
3474 uint64_t va = radv_buffer_get_va(info->strmout_buffer->bo);
3475
3476 va += info->strmout_buffer->offset +
3477 info->strmout_buffer_offset;
3478
3479 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
3480 info->stride);
3481
3482 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3483 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
3484 COPY_DATA_DST_SEL(COPY_DATA_REG) |
3485 COPY_DATA_WR_CONFIRM);
3486 radeon_emit(cs, va);
3487 radeon_emit(cs, va >> 32);
3488 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
3489 radeon_emit(cs, 0); /* unused */
3490
3491 radv_cs_add_buffer(ws, cs, info->strmout_buffer->bo);
3492 }
3493
3494 if (info->indirect) {
3495 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3496 uint64_t count_va = 0;
3497
3498 va += info->indirect->offset + info->indirect_offset;
3499
3500 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3501
3502 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3503 radeon_emit(cs, 1);
3504 radeon_emit(cs, va);
3505 radeon_emit(cs, va >> 32);
3506
3507 if (info->count_buffer) {
3508 count_va = radv_buffer_get_va(info->count_buffer->bo);
3509 count_va += info->count_buffer->offset +
3510 info->count_buffer_offset;
3511
3512 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
3513 }
3514
3515 if (!state->subpass->view_mask) {
3516 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3517 info->indexed,
3518 info->count,
3519 count_va,
3520 info->stride);
3521 } else {
3522 unsigned i;
3523 for_each_bit(i, state->subpass->view_mask) {
3524 radv_emit_view_index(cmd_buffer, i);
3525
3526 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3527 info->indexed,
3528 info->count,
3529 count_va,
3530 info->stride);
3531 }
3532 }
3533 } else {
3534 assert(state->pipeline->graphics.vtx_base_sgpr);
3535
3536 if (info->vertex_offset != state->last_vertex_offset ||
3537 info->first_instance != state->last_first_instance) {
3538 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3539 state->pipeline->graphics.vtx_emit_num);
3540
3541 radeon_emit(cs, info->vertex_offset);
3542 radeon_emit(cs, info->first_instance);
3543 if (state->pipeline->graphics.vtx_emit_num == 3)
3544 radeon_emit(cs, 0);
3545 state->last_first_instance = info->first_instance;
3546 state->last_vertex_offset = info->vertex_offset;
3547 }
3548
3549 if (state->last_num_instances != info->instance_count) {
3550 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3551 radeon_emit(cs, info->instance_count);
3552 state->last_num_instances = info->instance_count;
3553 }
3554
3555 if (info->indexed) {
3556 int index_size = state->index_type ? 4 : 2;
3557 uint64_t index_va;
3558
3559 index_va = state->index_va;
3560 index_va += info->first_index * index_size;
3561
3562 if (!state->subpass->view_mask) {
3563 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3564 index_va,
3565 info->count);
3566 } else {
3567 unsigned i;
3568 for_each_bit(i, state->subpass->view_mask) {
3569 radv_emit_view_index(cmd_buffer, i);
3570
3571 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3572 index_va,
3573 info->count);
3574 }
3575 }
3576 } else {
3577 if (!state->subpass->view_mask) {
3578 radv_cs_emit_draw_packet(cmd_buffer,
3579 info->count,
3580 !!info->strmout_buffer);
3581 } else {
3582 unsigned i;
3583 for_each_bit(i, state->subpass->view_mask) {
3584 radv_emit_view_index(cmd_buffer, i);
3585
3586 radv_cs_emit_draw_packet(cmd_buffer,
3587 info->count,
3588 !!info->strmout_buffer);
3589 }
3590 }
3591 }
3592 }
3593 }
3594
3595 /*
3596 * Vega and raven have a bug which triggers if there are multiple context
3597 * register contexts active at the same time with different scissor values.
3598 *
3599 * There are two possible workarounds:
3600 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3601 * there is only ever 1 active set of scissor values at the same time.
3602 *
3603 * 2) Whenever the hardware switches contexts we have to set the scissor
3604 * registers again even if it is a noop. That way the new context gets
3605 * the correct scissor values.
3606 *
3607 * This implements option 2. radv_need_late_scissor_emission needs to
3608 * return true on affected HW if radv_emit_all_graphics_states sets
3609 * any context registers.
3610 */
3611 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
3612 bool indexed_draw)
3613 {
3614 struct radv_cmd_state *state = &cmd_buffer->state;
3615
3616 if (!cmd_buffer->device->physical_device->has_scissor_bug)
3617 return false;
3618
3619 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
3620
3621 /* Index, vertex and streamout buffers don't change context regs, and
3622 * pipeline is handled later.
3623 */
3624 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
3625 RADV_CMD_DIRTY_VERTEX_BUFFER |
3626 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
3627 RADV_CMD_DIRTY_PIPELINE);
3628
3629 /* Assume all state changes except these two can imply context rolls. */
3630 if (cmd_buffer->state.dirty & used_states)
3631 return true;
3632
3633 if (cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3634 return true;
3635
3636 if (indexed_draw && state->pipeline->graphics.prim_restart_enable &&
3637 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
3638 return true;
3639
3640 return false;
3641 }
3642
3643 static void
3644 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3645 const struct radv_draw_info *info)
3646 {
3647 bool late_scissor_emission = radv_need_late_scissor_emission(cmd_buffer, info->indexed);
3648
3649 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3650 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3651 radv_emit_rbplus_state(cmd_buffer);
3652
3653 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3654 radv_emit_graphics_pipeline(cmd_buffer);
3655
3656 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3657 radv_emit_framebuffer_state(cmd_buffer);
3658
3659 if (info->indexed) {
3660 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3661 radv_emit_index_buffer(cmd_buffer);
3662 } else {
3663 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3664 * so the state must be re-emitted before the next indexed
3665 * draw.
3666 */
3667 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3668 cmd_buffer->state.last_index_type = -1;
3669 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3670 }
3671 }
3672
3673 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3674
3675 radv_emit_draw_registers(cmd_buffer, info->indexed,
3676 info->instance_count > 1, info->indirect,
3677 info->indirect ? 0 : info->count);
3678
3679 if (late_scissor_emission)
3680 radv_emit_scissor(cmd_buffer);
3681 }
3682
3683 static void
3684 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3685 const struct radv_draw_info *info)
3686 {
3687 struct radeon_info *rad_info =
3688 &cmd_buffer->device->physical_device->rad_info;
3689 bool has_prefetch =
3690 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3691 bool pipeline_is_dirty =
3692 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3693 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3694
3695 MAYBE_UNUSED unsigned cdw_max =
3696 radeon_check_space(cmd_buffer->device->ws,
3697 cmd_buffer->cs, 4096);
3698
3699 if (likely(!info->indirect)) {
3700 /* SI-CI treat instance_count==0 as instance_count==1. There is
3701 * no workaround for indirect draws, but we can at least skip
3702 * direct draws.
3703 */
3704 if (unlikely(!info->instance_count))
3705 return;
3706
3707 /* Handle count == 0. */
3708 if (unlikely(!info->count && !info->strmout_buffer))
3709 return;
3710 }
3711
3712 /* Use optimal packet order based on whether we need to sync the
3713 * pipeline.
3714 */
3715 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3716 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3717 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3718 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3719 /* If we have to wait for idle, set all states first, so that
3720 * all SET packets are processed in parallel with previous draw
3721 * calls. Then upload descriptors, set shader pointers, and
3722 * draw, and prefetch at the end. This ensures that the time
3723 * the CUs are idle is very short. (there are only SET_SH
3724 * packets between the wait and the draw)
3725 */
3726 radv_emit_all_graphics_states(cmd_buffer, info);
3727 si_emit_cache_flush(cmd_buffer);
3728 /* <-- CUs are idle here --> */
3729
3730 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3731
3732 radv_emit_draw_packets(cmd_buffer, info);
3733 /* <-- CUs are busy here --> */
3734
3735 /* Start prefetches after the draw has been started. Both will
3736 * run in parallel, but starting the draw first is more
3737 * important.
3738 */
3739 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3740 radv_emit_prefetch_L2(cmd_buffer,
3741 cmd_buffer->state.pipeline, false);
3742 }
3743 } else {
3744 /* If we don't wait for idle, start prefetches first, then set
3745 * states, and draw at the end.
3746 */
3747 si_emit_cache_flush(cmd_buffer);
3748
3749 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3750 /* Only prefetch the vertex shader and VBO descriptors
3751 * in order to start the draw as soon as possible.
3752 */
3753 radv_emit_prefetch_L2(cmd_buffer,
3754 cmd_buffer->state.pipeline, true);
3755 }
3756
3757 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3758
3759 radv_emit_all_graphics_states(cmd_buffer, info);
3760 radv_emit_draw_packets(cmd_buffer, info);
3761
3762 /* Prefetch the remaining shaders after the draw has been
3763 * started.
3764 */
3765 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3766 radv_emit_prefetch_L2(cmd_buffer,
3767 cmd_buffer->state.pipeline, false);
3768 }
3769 }
3770
3771 /* Workaround for a VGT hang when streamout is enabled.
3772 * It must be done after drawing.
3773 */
3774 if (cmd_buffer->state.streamout.streamout_enabled &&
3775 (rad_info->family == CHIP_HAWAII ||
3776 rad_info->family == CHIP_TONGA ||
3777 rad_info->family == CHIP_FIJI)) {
3778 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
3779 }
3780
3781 assert(cmd_buffer->cs->cdw <= cdw_max);
3782 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3783 }
3784
3785 void radv_CmdDraw(
3786 VkCommandBuffer commandBuffer,
3787 uint32_t vertexCount,
3788 uint32_t instanceCount,
3789 uint32_t firstVertex,
3790 uint32_t firstInstance)
3791 {
3792 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3793 struct radv_draw_info info = {};
3794
3795 info.count = vertexCount;
3796 info.instance_count = instanceCount;
3797 info.first_instance = firstInstance;
3798 info.vertex_offset = firstVertex;
3799
3800 radv_draw(cmd_buffer, &info);
3801 }
3802
3803 void radv_CmdDrawIndexed(
3804 VkCommandBuffer commandBuffer,
3805 uint32_t indexCount,
3806 uint32_t instanceCount,
3807 uint32_t firstIndex,
3808 int32_t vertexOffset,
3809 uint32_t firstInstance)
3810 {
3811 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3812 struct radv_draw_info info = {};
3813
3814 info.indexed = true;
3815 info.count = indexCount;
3816 info.instance_count = instanceCount;
3817 info.first_index = firstIndex;
3818 info.vertex_offset = vertexOffset;
3819 info.first_instance = firstInstance;
3820
3821 radv_draw(cmd_buffer, &info);
3822 }
3823
3824 void radv_CmdDrawIndirect(
3825 VkCommandBuffer commandBuffer,
3826 VkBuffer _buffer,
3827 VkDeviceSize offset,
3828 uint32_t drawCount,
3829 uint32_t stride)
3830 {
3831 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3832 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3833 struct radv_draw_info info = {};
3834
3835 info.count = drawCount;
3836 info.indirect = buffer;
3837 info.indirect_offset = offset;
3838 info.stride = stride;
3839
3840 radv_draw(cmd_buffer, &info);
3841 }
3842
3843 void radv_CmdDrawIndexedIndirect(
3844 VkCommandBuffer commandBuffer,
3845 VkBuffer _buffer,
3846 VkDeviceSize offset,
3847 uint32_t drawCount,
3848 uint32_t stride)
3849 {
3850 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3851 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3852 struct radv_draw_info info = {};
3853
3854 info.indexed = true;
3855 info.count = drawCount;
3856 info.indirect = buffer;
3857 info.indirect_offset = offset;
3858 info.stride = stride;
3859
3860 radv_draw(cmd_buffer, &info);
3861 }
3862
3863 void radv_CmdDrawIndirectCountAMD(
3864 VkCommandBuffer commandBuffer,
3865 VkBuffer _buffer,
3866 VkDeviceSize offset,
3867 VkBuffer _countBuffer,
3868 VkDeviceSize countBufferOffset,
3869 uint32_t maxDrawCount,
3870 uint32_t stride)
3871 {
3872 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3873 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3874 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3875 struct radv_draw_info info = {};
3876
3877 info.count = maxDrawCount;
3878 info.indirect = buffer;
3879 info.indirect_offset = offset;
3880 info.count_buffer = count_buffer;
3881 info.count_buffer_offset = countBufferOffset;
3882 info.stride = stride;
3883
3884 radv_draw(cmd_buffer, &info);
3885 }
3886
3887 void radv_CmdDrawIndexedIndirectCountAMD(
3888 VkCommandBuffer commandBuffer,
3889 VkBuffer _buffer,
3890 VkDeviceSize offset,
3891 VkBuffer _countBuffer,
3892 VkDeviceSize countBufferOffset,
3893 uint32_t maxDrawCount,
3894 uint32_t stride)
3895 {
3896 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3897 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3898 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3899 struct radv_draw_info info = {};
3900
3901 info.indexed = true;
3902 info.count = maxDrawCount;
3903 info.indirect = buffer;
3904 info.indirect_offset = offset;
3905 info.count_buffer = count_buffer;
3906 info.count_buffer_offset = countBufferOffset;
3907 info.stride = stride;
3908
3909 radv_draw(cmd_buffer, &info);
3910 }
3911
3912 void radv_CmdDrawIndirectCountKHR(
3913 VkCommandBuffer commandBuffer,
3914 VkBuffer _buffer,
3915 VkDeviceSize offset,
3916 VkBuffer _countBuffer,
3917 VkDeviceSize countBufferOffset,
3918 uint32_t maxDrawCount,
3919 uint32_t stride)
3920 {
3921 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3922 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3923 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3924 struct radv_draw_info info = {};
3925
3926 info.count = maxDrawCount;
3927 info.indirect = buffer;
3928 info.indirect_offset = offset;
3929 info.count_buffer = count_buffer;
3930 info.count_buffer_offset = countBufferOffset;
3931 info.stride = stride;
3932
3933 radv_draw(cmd_buffer, &info);
3934 }
3935
3936 void radv_CmdDrawIndexedIndirectCountKHR(
3937 VkCommandBuffer commandBuffer,
3938 VkBuffer _buffer,
3939 VkDeviceSize offset,
3940 VkBuffer _countBuffer,
3941 VkDeviceSize countBufferOffset,
3942 uint32_t maxDrawCount,
3943 uint32_t stride)
3944 {
3945 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3946 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3947 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3948 struct radv_draw_info info = {};
3949
3950 info.indexed = true;
3951 info.count = maxDrawCount;
3952 info.indirect = buffer;
3953 info.indirect_offset = offset;
3954 info.count_buffer = count_buffer;
3955 info.count_buffer_offset = countBufferOffset;
3956 info.stride = stride;
3957
3958 radv_draw(cmd_buffer, &info);
3959 }
3960
3961 struct radv_dispatch_info {
3962 /**
3963 * Determine the layout of the grid (in block units) to be used.
3964 */
3965 uint32_t blocks[3];
3966
3967 /**
3968 * A starting offset for the grid. If unaligned is set, the offset
3969 * must still be aligned.
3970 */
3971 uint32_t offsets[3];
3972 /**
3973 * Whether it's an unaligned compute dispatch.
3974 */
3975 bool unaligned;
3976
3977 /**
3978 * Indirect compute parameters resource.
3979 */
3980 struct radv_buffer *indirect;
3981 uint64_t indirect_offset;
3982 };
3983
3984 static void
3985 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3986 const struct radv_dispatch_info *info)
3987 {
3988 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3989 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3990 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3991 struct radeon_winsys *ws = cmd_buffer->device->ws;
3992 bool predicating = cmd_buffer->state.predicating;
3993 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3994 struct radv_userdata_info *loc;
3995
3996 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3997 AC_UD_CS_GRID_SIZE);
3998
3999 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
4000
4001 if (info->indirect) {
4002 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4003
4004 va += info->indirect->offset + info->indirect_offset;
4005
4006 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4007
4008 if (loc->sgpr_idx != -1) {
4009 for (unsigned i = 0; i < 3; ++i) {
4010 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4011 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4012 COPY_DATA_DST_SEL(COPY_DATA_REG));
4013 radeon_emit(cs, (va + 4 * i));
4014 radeon_emit(cs, (va + 4 * i) >> 32);
4015 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
4016 + loc->sgpr_idx * 4) >> 2) + i);
4017 radeon_emit(cs, 0);
4018 }
4019 }
4020
4021 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
4022 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
4023 PKT3_SHADER_TYPE_S(1));
4024 radeon_emit(cs, va);
4025 radeon_emit(cs, va >> 32);
4026 radeon_emit(cs, dispatch_initiator);
4027 } else {
4028 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
4029 PKT3_SHADER_TYPE_S(1));
4030 radeon_emit(cs, 1);
4031 radeon_emit(cs, va);
4032 radeon_emit(cs, va >> 32);
4033
4034 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
4035 PKT3_SHADER_TYPE_S(1));
4036 radeon_emit(cs, 0);
4037 radeon_emit(cs, dispatch_initiator);
4038 }
4039 } else {
4040 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
4041 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
4042
4043 if (info->unaligned) {
4044 unsigned *cs_block_size = compute_shader->info.cs.block_size;
4045 unsigned remainder[3];
4046
4047 /* If aligned, these should be an entire block size,
4048 * not 0.
4049 */
4050 remainder[0] = blocks[0] + cs_block_size[0] -
4051 align_u32_npot(blocks[0], cs_block_size[0]);
4052 remainder[1] = blocks[1] + cs_block_size[1] -
4053 align_u32_npot(blocks[1], cs_block_size[1]);
4054 remainder[2] = blocks[2] + cs_block_size[2] -
4055 align_u32_npot(blocks[2], cs_block_size[2]);
4056
4057 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
4058 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
4059 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
4060
4061 for(unsigned i = 0; i < 3; ++i) {
4062 assert(offsets[i] % cs_block_size[i] == 0);
4063 offsets[i] /= cs_block_size[i];
4064 }
4065
4066 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4067 radeon_emit(cs,
4068 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
4069 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4070 radeon_emit(cs,
4071 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4072 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4073 radeon_emit(cs,
4074 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4075 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4076
4077 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4078 }
4079
4080 if (loc->sgpr_idx != -1) {
4081 assert(!loc->indirect);
4082 assert(loc->num_sgprs == 3);
4083
4084 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4085 loc->sgpr_idx * 4, 3);
4086 radeon_emit(cs, blocks[0]);
4087 radeon_emit(cs, blocks[1]);
4088 radeon_emit(cs, blocks[2]);
4089 }
4090
4091 if (offsets[0] || offsets[1] || offsets[2]) {
4092 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4093 radeon_emit(cs, offsets[0]);
4094 radeon_emit(cs, offsets[1]);
4095 radeon_emit(cs, offsets[2]);
4096
4097 /* The blocks in the packet are not counts but end values. */
4098 for (unsigned i = 0; i < 3; ++i)
4099 blocks[i] += offsets[i];
4100 } else {
4101 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4102 }
4103
4104 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4105 PKT3_SHADER_TYPE_S(1));
4106 radeon_emit(cs, blocks[0]);
4107 radeon_emit(cs, blocks[1]);
4108 radeon_emit(cs, blocks[2]);
4109 radeon_emit(cs, dispatch_initiator);
4110 }
4111
4112 assert(cmd_buffer->cs->cdw <= cdw_max);
4113 }
4114
4115 static void
4116 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4117 {
4118 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4119 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4120 }
4121
4122 static void
4123 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4124 const struct radv_dispatch_info *info)
4125 {
4126 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4127 bool has_prefetch =
4128 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
4129 bool pipeline_is_dirty = pipeline &&
4130 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4131
4132 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4133 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4134 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4135 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4136 /* If we have to wait for idle, set all states first, so that
4137 * all SET packets are processed in parallel with previous draw
4138 * calls. Then upload descriptors, set shader pointers, and
4139 * dispatch, and prefetch at the end. This ensures that the
4140 * time the CUs are idle is very short. (there are only SET_SH
4141 * packets between the wait and the draw)
4142 */
4143 radv_emit_compute_pipeline(cmd_buffer);
4144 si_emit_cache_flush(cmd_buffer);
4145 /* <-- CUs are idle here --> */
4146
4147 radv_upload_compute_shader_descriptors(cmd_buffer);
4148
4149 radv_emit_dispatch_packets(cmd_buffer, info);
4150 /* <-- CUs are busy here --> */
4151
4152 /* Start prefetches after the dispatch has been started. Both
4153 * will run in parallel, but starting the dispatch first is
4154 * more important.
4155 */
4156 if (has_prefetch && pipeline_is_dirty) {
4157 radv_emit_shader_prefetch(cmd_buffer,
4158 pipeline->shaders[MESA_SHADER_COMPUTE]);
4159 }
4160 } else {
4161 /* If we don't wait for idle, start prefetches first, then set
4162 * states, and dispatch at the end.
4163 */
4164 si_emit_cache_flush(cmd_buffer);
4165
4166 if (has_prefetch && pipeline_is_dirty) {
4167 radv_emit_shader_prefetch(cmd_buffer,
4168 pipeline->shaders[MESA_SHADER_COMPUTE]);
4169 }
4170
4171 radv_upload_compute_shader_descriptors(cmd_buffer);
4172
4173 radv_emit_compute_pipeline(cmd_buffer);
4174 radv_emit_dispatch_packets(cmd_buffer, info);
4175 }
4176
4177 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
4178 }
4179
4180 void radv_CmdDispatchBase(
4181 VkCommandBuffer commandBuffer,
4182 uint32_t base_x,
4183 uint32_t base_y,
4184 uint32_t base_z,
4185 uint32_t x,
4186 uint32_t y,
4187 uint32_t z)
4188 {
4189 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4190 struct radv_dispatch_info info = {};
4191
4192 info.blocks[0] = x;
4193 info.blocks[1] = y;
4194 info.blocks[2] = z;
4195
4196 info.offsets[0] = base_x;
4197 info.offsets[1] = base_y;
4198 info.offsets[2] = base_z;
4199 radv_dispatch(cmd_buffer, &info);
4200 }
4201
4202 void radv_CmdDispatch(
4203 VkCommandBuffer commandBuffer,
4204 uint32_t x,
4205 uint32_t y,
4206 uint32_t z)
4207 {
4208 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4209 }
4210
4211 void radv_CmdDispatchIndirect(
4212 VkCommandBuffer commandBuffer,
4213 VkBuffer _buffer,
4214 VkDeviceSize offset)
4215 {
4216 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4217 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4218 struct radv_dispatch_info info = {};
4219
4220 info.indirect = buffer;
4221 info.indirect_offset = offset;
4222
4223 radv_dispatch(cmd_buffer, &info);
4224 }
4225
4226 void radv_unaligned_dispatch(
4227 struct radv_cmd_buffer *cmd_buffer,
4228 uint32_t x,
4229 uint32_t y,
4230 uint32_t z)
4231 {
4232 struct radv_dispatch_info info = {};
4233
4234 info.blocks[0] = x;
4235 info.blocks[1] = y;
4236 info.blocks[2] = z;
4237 info.unaligned = 1;
4238
4239 radv_dispatch(cmd_buffer, &info);
4240 }
4241
4242 void radv_CmdEndRenderPass(
4243 VkCommandBuffer commandBuffer)
4244 {
4245 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4246
4247 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
4248
4249 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4250
4251 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
4252 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
4253 radv_handle_subpass_image_transition(cmd_buffer,
4254 (struct radv_subpass_attachment){i, layout});
4255 }
4256
4257 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4258
4259 cmd_buffer->state.pass = NULL;
4260 cmd_buffer->state.subpass = NULL;
4261 cmd_buffer->state.attachments = NULL;
4262 cmd_buffer->state.framebuffer = NULL;
4263 }
4264
4265 void radv_CmdEndRenderPass2KHR(
4266 VkCommandBuffer commandBuffer,
4267 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4268 {
4269 radv_CmdEndRenderPass(commandBuffer);
4270 }
4271
4272 /*
4273 * For HTILE we have the following interesting clear words:
4274 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4275 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4276 * 0xfffffff0: Clear depth to 1.0
4277 * 0x00000000: Clear depth to 0.0
4278 */
4279 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
4280 struct radv_image *image,
4281 const VkImageSubresourceRange *range,
4282 uint32_t clear_word)
4283 {
4284 assert(range->baseMipLevel == 0);
4285 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
4286 unsigned layer_count = radv_get_layerCount(image, range);
4287 uint64_t size = image->surface.htile_slice_size * layer_count;
4288 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
4289 uint64_t offset = image->offset + image->htile_offset +
4290 image->surface.htile_slice_size * range->baseArrayLayer;
4291 struct radv_cmd_state *state = &cmd_buffer->state;
4292 VkClearDepthStencilValue value = {};
4293
4294 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4295 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4296
4297 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
4298 size, clear_word);
4299
4300 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4301
4302 if (vk_format_is_stencil(image->vk_format))
4303 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4304
4305 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4306
4307 if (radv_image_is_tc_compat_htile(image)) {
4308 /* Initialize the TC-compat metada value to 0 because by
4309 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
4310 * need have to conditionally update its value when performing
4311 * a fast depth clear.
4312 */
4313 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, 0);
4314 }
4315 }
4316
4317 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4318 struct radv_image *image,
4319 VkImageLayout src_layout,
4320 VkImageLayout dst_layout,
4321 unsigned src_queue_mask,
4322 unsigned dst_queue_mask,
4323 const VkImageSubresourceRange *range)
4324 {
4325 if (!radv_image_has_htile(image))
4326 return;
4327
4328 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
4329 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
4330 /* TODO: merge with the clear if applicable */
4331 radv_initialize_htile(cmd_buffer, image, range, 0);
4332 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4333 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4334 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4335 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4336 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4337 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4338 VkImageSubresourceRange local_range = *range;
4339 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4340 local_range.baseMipLevel = 0;
4341 local_range.levelCount = 1;
4342
4343 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4344 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4345
4346 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
4347
4348 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4349 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4350 }
4351 }
4352
4353 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4354 struct radv_image *image, uint32_t value)
4355 {
4356 struct radv_cmd_state *state = &cmd_buffer->state;
4357
4358 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4359 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4360
4361 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
4362
4363 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4364 }
4365
4366 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
4367 struct radv_image *image)
4368 {
4369 struct radv_cmd_state *state = &cmd_buffer->state;
4370 static const uint32_t fmask_clear_values[4] = {
4371 0x00000000,
4372 0x02020202,
4373 0xE4E4E4E4,
4374 0x76543210
4375 };
4376 uint32_t log2_samples = util_logbase2(image->info.samples);
4377 uint32_t value = fmask_clear_values[log2_samples];
4378
4379 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4380 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4381
4382 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, value);
4383
4384 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4385 }
4386
4387 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4388 struct radv_image *image, uint32_t value)
4389 {
4390 struct radv_cmd_state *state = &cmd_buffer->state;
4391
4392 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4393 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4394
4395 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
4396
4397 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4398 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4399 }
4400
4401 /**
4402 * Initialize DCC/FMASK/CMASK metadata for a color image.
4403 */
4404 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4405 struct radv_image *image,
4406 VkImageLayout src_layout,
4407 VkImageLayout dst_layout,
4408 unsigned src_queue_mask,
4409 unsigned dst_queue_mask)
4410 {
4411 if (radv_image_has_cmask(image)) {
4412 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4413
4414 /* TODO: clarify this. */
4415 if (radv_image_has_fmask(image)) {
4416 value = 0xccccccccu;
4417 }
4418
4419 radv_initialise_cmask(cmd_buffer, image, value);
4420 }
4421
4422 if (radv_image_has_fmask(image)) {
4423 radv_initialize_fmask(cmd_buffer, image);
4424 }
4425
4426 if (radv_image_has_dcc(image)) {
4427 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4428 bool need_decompress_pass = false;
4429
4430 if (radv_layout_dcc_compressed(image, dst_layout,
4431 dst_queue_mask)) {
4432 value = 0x20202020u;
4433 need_decompress_pass = true;
4434 }
4435
4436 radv_initialize_dcc(cmd_buffer, image, value);
4437
4438 radv_update_fce_metadata(cmd_buffer, image,
4439 need_decompress_pass);
4440 }
4441
4442 if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
4443 uint32_t color_values[2] = {};
4444 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
4445 }
4446 }
4447
4448 /**
4449 * Handle color image transitions for DCC/FMASK/CMASK.
4450 */
4451 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4452 struct radv_image *image,
4453 VkImageLayout src_layout,
4454 VkImageLayout dst_layout,
4455 unsigned src_queue_mask,
4456 unsigned dst_queue_mask,
4457 const VkImageSubresourceRange *range)
4458 {
4459 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4460 radv_init_color_image_metadata(cmd_buffer, image,
4461 src_layout, dst_layout,
4462 src_queue_mask, dst_queue_mask);
4463 return;
4464 }
4465
4466 if (radv_image_has_dcc(image)) {
4467 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4468 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4469 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4470 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4471 radv_decompress_dcc(cmd_buffer, image, range);
4472 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4473 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4474 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4475 }
4476 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
4477 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4478 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4479 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4480 }
4481
4482 if (radv_image_has_fmask(image)) {
4483 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
4484 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
4485 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
4486 }
4487 }
4488 }
4489 }
4490
4491 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4492 struct radv_image *image,
4493 VkImageLayout src_layout,
4494 VkImageLayout dst_layout,
4495 uint32_t src_family,
4496 uint32_t dst_family,
4497 const VkImageSubresourceRange *range)
4498 {
4499 if (image->exclusive && src_family != dst_family) {
4500 /* This is an acquire or a release operation and there will be
4501 * a corresponding release/acquire. Do the transition in the
4502 * most flexible queue. */
4503
4504 assert(src_family == cmd_buffer->queue_family_index ||
4505 dst_family == cmd_buffer->queue_family_index);
4506
4507 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4508 return;
4509
4510 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4511 (src_family == RADV_QUEUE_GENERAL ||
4512 dst_family == RADV_QUEUE_GENERAL))
4513 return;
4514 }
4515
4516 unsigned src_queue_mask =
4517 radv_image_queue_family_mask(image, src_family,
4518 cmd_buffer->queue_family_index);
4519 unsigned dst_queue_mask =
4520 radv_image_queue_family_mask(image, dst_family,
4521 cmd_buffer->queue_family_index);
4522
4523 if (vk_format_is_depth(image->vk_format)) {
4524 radv_handle_depth_image_transition(cmd_buffer, image,
4525 src_layout, dst_layout,
4526 src_queue_mask, dst_queue_mask,
4527 range);
4528 } else {
4529 radv_handle_color_image_transition(cmd_buffer, image,
4530 src_layout, dst_layout,
4531 src_queue_mask, dst_queue_mask,
4532 range);
4533 }
4534 }
4535
4536 struct radv_barrier_info {
4537 uint32_t eventCount;
4538 const VkEvent *pEvents;
4539 VkPipelineStageFlags srcStageMask;
4540 };
4541
4542 static void
4543 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
4544 uint32_t memoryBarrierCount,
4545 const VkMemoryBarrier *pMemoryBarriers,
4546 uint32_t bufferMemoryBarrierCount,
4547 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4548 uint32_t imageMemoryBarrierCount,
4549 const VkImageMemoryBarrier *pImageMemoryBarriers,
4550 const struct radv_barrier_info *info)
4551 {
4552 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4553 enum radv_cmd_flush_bits src_flush_bits = 0;
4554 enum radv_cmd_flush_bits dst_flush_bits = 0;
4555
4556 for (unsigned i = 0; i < info->eventCount; ++i) {
4557 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
4558 uint64_t va = radv_buffer_get_va(event->bo);
4559
4560 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4561
4562 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4563
4564 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
4565 assert(cmd_buffer->cs->cdw <= cdw_max);
4566 }
4567
4568 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4569 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
4570 NULL);
4571 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4572 NULL);
4573 }
4574
4575 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4576 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
4577 NULL);
4578 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4579 NULL);
4580 }
4581
4582 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4583 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4584
4585 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
4586 image);
4587 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4588 image);
4589 }
4590
4591 radv_stage_flush(cmd_buffer, info->srcStageMask);
4592 cmd_buffer->state.flush_bits |= src_flush_bits;
4593
4594 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4595 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4596 radv_handle_image_transition(cmd_buffer, image,
4597 pImageMemoryBarriers[i].oldLayout,
4598 pImageMemoryBarriers[i].newLayout,
4599 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4600 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4601 &pImageMemoryBarriers[i].subresourceRange);
4602 }
4603
4604 /* Make sure CP DMA is idle because the driver might have performed a
4605 * DMA operation for copying or filling buffers/images.
4606 */
4607 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
4608 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
4609 si_cp_dma_wait_for_idle(cmd_buffer);
4610
4611 cmd_buffer->state.flush_bits |= dst_flush_bits;
4612 }
4613
4614 void radv_CmdPipelineBarrier(
4615 VkCommandBuffer commandBuffer,
4616 VkPipelineStageFlags srcStageMask,
4617 VkPipelineStageFlags destStageMask,
4618 VkBool32 byRegion,
4619 uint32_t memoryBarrierCount,
4620 const VkMemoryBarrier* pMemoryBarriers,
4621 uint32_t bufferMemoryBarrierCount,
4622 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4623 uint32_t imageMemoryBarrierCount,
4624 const VkImageMemoryBarrier* pImageMemoryBarriers)
4625 {
4626 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4627 struct radv_barrier_info info;
4628
4629 info.eventCount = 0;
4630 info.pEvents = NULL;
4631 info.srcStageMask = srcStageMask;
4632
4633 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4634 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4635 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4636 }
4637
4638
4639 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4640 struct radv_event *event,
4641 VkPipelineStageFlags stageMask,
4642 unsigned value)
4643 {
4644 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4645 uint64_t va = radv_buffer_get_va(event->bo);
4646
4647 si_emit_cache_flush(cmd_buffer);
4648
4649 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4650
4651 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4652
4653 /* Flags that only require a top-of-pipe event. */
4654 VkPipelineStageFlags top_of_pipe_flags =
4655 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
4656
4657 /* Flags that only require a post-index-fetch event. */
4658 VkPipelineStageFlags post_index_fetch_flags =
4659 top_of_pipe_flags |
4660 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
4661 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
4662
4663 /* Make sure CP DMA is idle because the driver might have performed a
4664 * DMA operation for copying or filling buffers/images.
4665 */
4666 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
4667 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
4668 si_cp_dma_wait_for_idle(cmd_buffer);
4669
4670 /* TODO: Emit EOS events for syncing PS/CS stages. */
4671
4672 if (!(stageMask & ~top_of_pipe_flags)) {
4673 /* Just need to sync the PFP engine. */
4674 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4675 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
4676 S_370_WR_CONFIRM(1) |
4677 S_370_ENGINE_SEL(V_370_PFP));
4678 radeon_emit(cs, va);
4679 radeon_emit(cs, va >> 32);
4680 radeon_emit(cs, value);
4681 } else if (!(stageMask & ~post_index_fetch_flags)) {
4682 /* Sync ME because PFP reads index and indirect buffers. */
4683 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4684 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
4685 S_370_WR_CONFIRM(1) |
4686 S_370_ENGINE_SEL(V_370_ME));
4687 radeon_emit(cs, va);
4688 radeon_emit(cs, va >> 32);
4689 radeon_emit(cs, value);
4690 } else {
4691 /* Otherwise, sync all prior GPU work using an EOP event. */
4692 si_cs_emit_write_event_eop(cs,
4693 cmd_buffer->device->physical_device->rad_info.chip_class,
4694 radv_cmd_buffer_uses_mec(cmd_buffer),
4695 V_028A90_BOTTOM_OF_PIPE_TS, 0,
4696 EOP_DATA_SEL_VALUE_32BIT, va, 2, value,
4697 cmd_buffer->gfx9_eop_bug_va);
4698 }
4699
4700 assert(cmd_buffer->cs->cdw <= cdw_max);
4701 }
4702
4703 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4704 VkEvent _event,
4705 VkPipelineStageFlags stageMask)
4706 {
4707 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4708 RADV_FROM_HANDLE(radv_event, event, _event);
4709
4710 write_event(cmd_buffer, event, stageMask, 1);
4711 }
4712
4713 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4714 VkEvent _event,
4715 VkPipelineStageFlags stageMask)
4716 {
4717 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4718 RADV_FROM_HANDLE(radv_event, event, _event);
4719
4720 write_event(cmd_buffer, event, stageMask, 0);
4721 }
4722
4723 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4724 uint32_t eventCount,
4725 const VkEvent* pEvents,
4726 VkPipelineStageFlags srcStageMask,
4727 VkPipelineStageFlags dstStageMask,
4728 uint32_t memoryBarrierCount,
4729 const VkMemoryBarrier* pMemoryBarriers,
4730 uint32_t bufferMemoryBarrierCount,
4731 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4732 uint32_t imageMemoryBarrierCount,
4733 const VkImageMemoryBarrier* pImageMemoryBarriers)
4734 {
4735 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4736 struct radv_barrier_info info;
4737
4738 info.eventCount = eventCount;
4739 info.pEvents = pEvents;
4740 info.srcStageMask = 0;
4741
4742 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4743 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4744 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4745 }
4746
4747
4748 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4749 uint32_t deviceMask)
4750 {
4751 /* No-op */
4752 }
4753
4754 /* VK_EXT_conditional_rendering */
4755 void radv_CmdBeginConditionalRenderingEXT(
4756 VkCommandBuffer commandBuffer,
4757 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
4758 {
4759 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4760 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
4761 bool draw_visible = true;
4762 uint64_t va;
4763
4764 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
4765
4766 /* By default, if the 32-bit value at offset in buffer memory is zero,
4767 * then the rendering commands are discarded, otherwise they are
4768 * executed as normal. If the inverted flag is set, all commands are
4769 * discarded if the value is non zero.
4770 */
4771 if (pConditionalRenderingBegin->flags &
4772 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
4773 draw_visible = false;
4774 }
4775
4776 si_emit_cache_flush(cmd_buffer);
4777
4778 /* Enable predication for this command buffer. */
4779 si_emit_set_predication_state(cmd_buffer, draw_visible, va);
4780 cmd_buffer->state.predicating = true;
4781
4782 /* Store conditional rendering user info. */
4783 cmd_buffer->state.predication_type = draw_visible;
4784 cmd_buffer->state.predication_va = va;
4785 }
4786
4787 void radv_CmdEndConditionalRenderingEXT(
4788 VkCommandBuffer commandBuffer)
4789 {
4790 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4791
4792 /* Disable predication for this command buffer. */
4793 si_emit_set_predication_state(cmd_buffer, false, 0);
4794 cmd_buffer->state.predicating = false;
4795
4796 /* Reset conditional rendering user info. */
4797 cmd_buffer->state.predication_type = -1;
4798 cmd_buffer->state.predication_va = 0;
4799 }
4800
4801 /* VK_EXT_transform_feedback */
4802 void radv_CmdBindTransformFeedbackBuffersEXT(
4803 VkCommandBuffer commandBuffer,
4804 uint32_t firstBinding,
4805 uint32_t bindingCount,
4806 const VkBuffer* pBuffers,
4807 const VkDeviceSize* pOffsets,
4808 const VkDeviceSize* pSizes)
4809 {
4810 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4811 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
4812 uint8_t enabled_mask = 0;
4813
4814 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
4815 for (uint32_t i = 0; i < bindingCount; i++) {
4816 uint32_t idx = firstBinding + i;
4817
4818 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
4819 sb[idx].offset = pOffsets[i];
4820 sb[idx].size = pSizes[i];
4821
4822 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
4823 sb[idx].buffer->bo);
4824
4825 enabled_mask |= 1 << idx;
4826 }
4827
4828 cmd_buffer->state.streamout.enabled_mask = enabled_mask;
4829
4830 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
4831 }
4832
4833 static void
4834 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
4835 {
4836 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4837 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4838
4839 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
4840 radeon_emit(cs,
4841 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
4842 S_028B94_RAST_STREAM(0) |
4843 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
4844 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
4845 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
4846 radeon_emit(cs, so->hw_enabled_mask &
4847 so->enabled_stream_buffers_mask);
4848 }
4849
4850 static void
4851 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
4852 {
4853 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4854 bool old_streamout_enabled = so->streamout_enabled;
4855 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
4856
4857 so->streamout_enabled = enable;
4858
4859 so->hw_enabled_mask = so->enabled_mask |
4860 (so->enabled_mask << 4) |
4861 (so->enabled_mask << 8) |
4862 (so->enabled_mask << 12);
4863
4864 if ((old_streamout_enabled != so->streamout_enabled) ||
4865 (old_hw_enabled_mask != so->hw_enabled_mask))
4866 radv_emit_streamout_enable(cmd_buffer);
4867 }
4868
4869 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
4870 {
4871 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4872 unsigned reg_strmout_cntl;
4873
4874 /* The register is at different places on different ASICs. */
4875 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
4876 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
4877 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
4878 } else {
4879 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
4880 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
4881 }
4882
4883 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4884 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
4885
4886 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
4887 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
4888 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
4889 radeon_emit(cs, 0);
4890 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
4891 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
4892 radeon_emit(cs, 4); /* poll interval */
4893 }
4894
4895 void radv_CmdBeginTransformFeedbackEXT(
4896 VkCommandBuffer commandBuffer,
4897 uint32_t firstCounterBuffer,
4898 uint32_t counterBufferCount,
4899 const VkBuffer* pCounterBuffers,
4900 const VkDeviceSize* pCounterBufferOffsets)
4901 {
4902 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4903 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
4904 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4905 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4906 uint32_t i;
4907
4908 radv_flush_vgt_streamout(cmd_buffer);
4909
4910 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
4911 for_each_bit(i, so->enabled_mask) {
4912 int32_t counter_buffer_idx = i - firstCounterBuffer;
4913 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
4914 counter_buffer_idx = -1;
4915
4916 /* SI binds streamout buffers as shader resources.
4917 * VGT only counts primitives and tells the shader through
4918 * SGPRs what to do.
4919 */
4920 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
4921 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
4922 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
4923
4924 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
4925 /* The array of counter buffers is optional. */
4926 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
4927 uint64_t va = radv_buffer_get_va(buffer->bo);
4928
4929 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
4930
4931 /* Append */
4932 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
4933 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
4934 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4935 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
4936 radeon_emit(cs, 0); /* unused */
4937 radeon_emit(cs, 0); /* unused */
4938 radeon_emit(cs, va); /* src address lo */
4939 radeon_emit(cs, va >> 32); /* src address hi */
4940
4941 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
4942 } else {
4943 /* Start from the beginning. */
4944 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
4945 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
4946 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4947 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
4948 radeon_emit(cs, 0); /* unused */
4949 radeon_emit(cs, 0); /* unused */
4950 radeon_emit(cs, 0); /* unused */
4951 radeon_emit(cs, 0); /* unused */
4952 }
4953 }
4954
4955 radv_set_streamout_enable(cmd_buffer, true);
4956 }
4957
4958 void radv_CmdEndTransformFeedbackEXT(
4959 VkCommandBuffer commandBuffer,
4960 uint32_t firstCounterBuffer,
4961 uint32_t counterBufferCount,
4962 const VkBuffer* pCounterBuffers,
4963 const VkDeviceSize* pCounterBufferOffsets)
4964 {
4965 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4966 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4967 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4968 uint32_t i;
4969
4970 radv_flush_vgt_streamout(cmd_buffer);
4971
4972 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
4973 for_each_bit(i, so->enabled_mask) {
4974 int32_t counter_buffer_idx = i - firstCounterBuffer;
4975 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
4976 counter_buffer_idx = -1;
4977
4978 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
4979 /* The array of counters buffer is optional. */
4980 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
4981 uint64_t va = radv_buffer_get_va(buffer->bo);
4982
4983 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
4984
4985 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
4986 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
4987 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4988 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
4989 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
4990 radeon_emit(cs, va); /* dst address lo */
4991 radeon_emit(cs, va >> 32); /* dst address hi */
4992 radeon_emit(cs, 0); /* unused */
4993 radeon_emit(cs, 0); /* unused */
4994
4995 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
4996 }
4997
4998 /* Deactivate transform feedback by zeroing the buffer size.
4999 * The counters (primitives generated, primitives emitted) may
5000 * be enabled even if there is not buffer bound. This ensures
5001 * that the primitives-emitted query won't increment.
5002 */
5003 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
5004 }
5005
5006 radv_set_streamout_enable(cmd_buffer, false);
5007 }
5008
5009 void radv_CmdDrawIndirectByteCountEXT(
5010 VkCommandBuffer commandBuffer,
5011 uint32_t instanceCount,
5012 uint32_t firstInstance,
5013 VkBuffer _counterBuffer,
5014 VkDeviceSize counterBufferOffset,
5015 uint32_t counterOffset,
5016 uint32_t vertexStride)
5017 {
5018 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5019 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
5020 struct radv_draw_info info = {};
5021
5022 info.instance_count = instanceCount;
5023 info.first_instance = firstInstance;
5024 info.strmout_buffer = counterBuffer;
5025 info.strmout_buffer_offset = counterBufferOffset;
5026 info.stride = vertexStride;
5027
5028 radv_draw(cmd_buffer, &info);
5029 }