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radv: reduce CB/DB meta flushes in radv_dst_access_flush()
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range,
61 VkImageAspectFlags pending_clears);
62
63 const struct radv_dynamic_state default_dynamic_state = {
64 .viewport = {
65 .count = 0,
66 },
67 .scissor = {
68 .count = 0,
69 },
70 .line_width = 1.0f,
71 .depth_bias = {
72 .bias = 0.0f,
73 .clamp = 0.0f,
74 .slope = 0.0f,
75 },
76 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
77 .depth_bounds = {
78 .min = 0.0f,
79 .max = 1.0f,
80 },
81 .stencil_compare_mask = {
82 .front = ~0u,
83 .back = ~0u,
84 },
85 .stencil_write_mask = {
86 .front = ~0u,
87 .back = ~0u,
88 },
89 .stencil_reference = {
90 .front = 0u,
91 .back = 0u,
92 },
93 };
94
95 static void
96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
97 const struct radv_dynamic_state *src)
98 {
99 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
100 uint32_t copy_mask = src->mask;
101 uint32_t dest_mask = 0;
102
103 /* Make sure to copy the number of viewports/scissors because they can
104 * only be specified at pipeline creation time.
105 */
106 dest->viewport.count = src->viewport.count;
107 dest->scissor.count = src->scissor.count;
108 dest->discard_rectangle.count = src->discard_rectangle.count;
109
110 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
111 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
112 src->viewport.count * sizeof(VkViewport))) {
113 typed_memcpy(dest->viewport.viewports,
114 src->viewport.viewports,
115 src->viewport.count);
116 dest_mask |= RADV_DYNAMIC_VIEWPORT;
117 }
118 }
119
120 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
121 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
122 src->scissor.count * sizeof(VkRect2D))) {
123 typed_memcpy(dest->scissor.scissors,
124 src->scissor.scissors, src->scissor.count);
125 dest_mask |= RADV_DYNAMIC_SCISSOR;
126 }
127 }
128
129 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
130 if (dest->line_width != src->line_width) {
131 dest->line_width = src->line_width;
132 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
133 }
134 }
135
136 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
137 if (memcmp(&dest->depth_bias, &src->depth_bias,
138 sizeof(src->depth_bias))) {
139 dest->depth_bias = src->depth_bias;
140 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
141 }
142 }
143
144 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
145 if (memcmp(&dest->blend_constants, &src->blend_constants,
146 sizeof(src->blend_constants))) {
147 typed_memcpy(dest->blend_constants,
148 src->blend_constants, 4);
149 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
150 }
151 }
152
153 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
154 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
155 sizeof(src->depth_bounds))) {
156 dest->depth_bounds = src->depth_bounds;
157 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
158 }
159 }
160
161 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
162 if (memcmp(&dest->stencil_compare_mask,
163 &src->stencil_compare_mask,
164 sizeof(src->stencil_compare_mask))) {
165 dest->stencil_compare_mask = src->stencil_compare_mask;
166 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
167 }
168 }
169
170 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
171 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
172 sizeof(src->stencil_write_mask))) {
173 dest->stencil_write_mask = src->stencil_write_mask;
174 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
175 }
176 }
177
178 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
179 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
180 sizeof(src->stencil_reference))) {
181 dest->stencil_reference = src->stencil_reference;
182 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
183 }
184 }
185
186 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
187 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
188 src->discard_rectangle.count * sizeof(VkRect2D))) {
189 typed_memcpy(dest->discard_rectangle.rectangles,
190 src->discard_rectangle.rectangles,
191 src->discard_rectangle.count);
192 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
193 }
194 }
195
196 cmd_buffer->state.dirty |= dest_mask;
197 }
198
199 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
200 {
201 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
202 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
203 }
204
205 enum ring_type radv_queue_family_to_ring(int f) {
206 switch (f) {
207 case RADV_QUEUE_GENERAL:
208 return RING_GFX;
209 case RADV_QUEUE_COMPUTE:
210 return RING_COMPUTE;
211 case RADV_QUEUE_TRANSFER:
212 return RING_DMA;
213 default:
214 unreachable("Unknown queue family");
215 }
216 }
217
218 static VkResult radv_create_cmd_buffer(
219 struct radv_device * device,
220 struct radv_cmd_pool * pool,
221 VkCommandBufferLevel level,
222 VkCommandBuffer* pCommandBuffer)
223 {
224 struct radv_cmd_buffer *cmd_buffer;
225 unsigned ring;
226 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
227 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
228 if (cmd_buffer == NULL)
229 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
230
231 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
232 cmd_buffer->device = device;
233 cmd_buffer->pool = pool;
234 cmd_buffer->level = level;
235
236 if (pool) {
237 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
238 cmd_buffer->queue_family_index = pool->queue_family_index;
239
240 } else {
241 /* Init the pool_link so we can safely call list_del when we destroy
242 * the command buffer
243 */
244 list_inithead(&cmd_buffer->pool_link);
245 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
246 }
247
248 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
249
250 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
251 if (!cmd_buffer->cs) {
252 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
253 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
254 }
255
256 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
257
258 list_inithead(&cmd_buffer->upload.list);
259
260 return VK_SUCCESS;
261 }
262
263 static void
264 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
265 {
266 list_del(&cmd_buffer->pool_link);
267
268 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
269 &cmd_buffer->upload.list, list) {
270 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
271 list_del(&up->list);
272 free(up);
273 }
274
275 if (cmd_buffer->upload.upload_bo)
276 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
277 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
278
279 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
280 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
281
282 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
283 }
284
285 static VkResult
286 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
287 {
288
289 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
290
291 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
292 &cmd_buffer->upload.list, list) {
293 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
294 list_del(&up->list);
295 free(up);
296 }
297
298 cmd_buffer->push_constant_stages = 0;
299 cmd_buffer->scratch_size_needed = 0;
300 cmd_buffer->compute_scratch_size_needed = 0;
301 cmd_buffer->esgs_ring_size_needed = 0;
302 cmd_buffer->gsvs_ring_size_needed = 0;
303 cmd_buffer->tess_rings_needed = false;
304 cmd_buffer->sample_positions_needed = false;
305
306 if (cmd_buffer->upload.upload_bo)
307 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
308 cmd_buffer->upload.upload_bo);
309 cmd_buffer->upload.offset = 0;
310
311 cmd_buffer->record_result = VK_SUCCESS;
312
313 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
314 cmd_buffer->descriptors[i].dirty = 0;
315 cmd_buffer->descriptors[i].valid = 0;
316 cmd_buffer->descriptors[i].push_dirty = false;
317 }
318
319 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
320 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
321 unsigned eop_bug_offset;
322 void *fence_ptr;
323
324 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
325 &cmd_buffer->gfx9_fence_offset,
326 &fence_ptr);
327 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
328
329 /* Allocate a buffer for the EOP bug on GFX9. */
330 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 0,
331 &eop_bug_offset, &fence_ptr);
332 cmd_buffer->gfx9_eop_bug_va =
333 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
334 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
335 }
336
337 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
338
339 return cmd_buffer->record_result;
340 }
341
342 static bool
343 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
344 uint64_t min_needed)
345 {
346 uint64_t new_size;
347 struct radeon_winsys_bo *bo;
348 struct radv_cmd_buffer_upload *upload;
349 struct radv_device *device = cmd_buffer->device;
350
351 new_size = MAX2(min_needed, 16 * 1024);
352 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
353
354 bo = device->ws->buffer_create(device->ws,
355 new_size, 4096,
356 RADEON_DOMAIN_GTT,
357 RADEON_FLAG_CPU_ACCESS|
358 RADEON_FLAG_NO_INTERPROCESS_SHARING |
359 RADEON_FLAG_32BIT);
360
361 if (!bo) {
362 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
363 return false;
364 }
365
366 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
367 if (cmd_buffer->upload.upload_bo) {
368 upload = malloc(sizeof(*upload));
369
370 if (!upload) {
371 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
372 device->ws->buffer_destroy(bo);
373 return false;
374 }
375
376 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
377 list_add(&upload->list, &cmd_buffer->upload.list);
378 }
379
380 cmd_buffer->upload.upload_bo = bo;
381 cmd_buffer->upload.size = new_size;
382 cmd_buffer->upload.offset = 0;
383 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
384
385 if (!cmd_buffer->upload.map) {
386 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
387 return false;
388 }
389
390 return true;
391 }
392
393 bool
394 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
395 unsigned size,
396 unsigned alignment,
397 unsigned *out_offset,
398 void **ptr)
399 {
400 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
401 if (offset + size > cmd_buffer->upload.size) {
402 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
403 return false;
404 offset = 0;
405 }
406
407 *out_offset = offset;
408 *ptr = cmd_buffer->upload.map + offset;
409
410 cmd_buffer->upload.offset = offset + size;
411 return true;
412 }
413
414 bool
415 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
416 unsigned size, unsigned alignment,
417 const void *data, unsigned *out_offset)
418 {
419 uint8_t *ptr;
420
421 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
422 out_offset, (void **)&ptr))
423 return false;
424
425 if (ptr)
426 memcpy(ptr, data, size);
427
428 return true;
429 }
430
431 static void
432 radv_emit_write_data_packet(struct radeon_cmdbuf *cs, uint64_t va,
433 unsigned count, const uint32_t *data)
434 {
435 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
436 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
437 S_370_WR_CONFIRM(1) |
438 S_370_ENGINE_SEL(V_370_ME));
439 radeon_emit(cs, va);
440 radeon_emit(cs, va >> 32);
441 radeon_emit_array(cs, data, count);
442 }
443
444 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
445 {
446 struct radv_device *device = cmd_buffer->device;
447 struct radeon_cmdbuf *cs = cmd_buffer->cs;
448 uint64_t va;
449
450 va = radv_buffer_get_va(device->trace_bo);
451 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
452 va += 4;
453
454 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
455
456 ++cmd_buffer->state.trace_id;
457 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
458 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
459 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
460 }
461
462 static void
463 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
464 enum radv_cmd_flush_bits flags)
465 {
466 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
467 uint32_t *ptr = NULL;
468 uint64_t va = 0;
469
470 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
471 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
472
473 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
474 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
475 cmd_buffer->gfx9_fence_offset;
476 ptr = &cmd_buffer->gfx9_fence_idx;
477 }
478
479 /* Force wait for graphics or compute engines to be idle. */
480 si_cs_emit_cache_flush(cmd_buffer->cs,
481 cmd_buffer->device->physical_device->rad_info.chip_class,
482 ptr, va,
483 radv_cmd_buffer_uses_mec(cmd_buffer),
484 flags, cmd_buffer->gfx9_eop_bug_va);
485 }
486
487 if (unlikely(cmd_buffer->device->trace_bo))
488 radv_cmd_buffer_trace_emit(cmd_buffer);
489 }
490
491 static void
492 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
493 struct radv_pipeline *pipeline, enum ring_type ring)
494 {
495 struct radv_device *device = cmd_buffer->device;
496 struct radeon_cmdbuf *cs = cmd_buffer->cs;
497 uint32_t data[2];
498 uint64_t va;
499
500 va = radv_buffer_get_va(device->trace_bo);
501
502 switch (ring) {
503 case RING_GFX:
504 va += 8;
505 break;
506 case RING_COMPUTE:
507 va += 16;
508 break;
509 default:
510 assert(!"invalid ring type");
511 }
512
513 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
514 cmd_buffer->cs, 6);
515
516 data[0] = (uintptr_t)pipeline;
517 data[1] = (uintptr_t)pipeline >> 32;
518
519 radv_emit_write_data_packet(cs, va, 2, data);
520 }
521
522 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
523 VkPipelineBindPoint bind_point,
524 struct radv_descriptor_set *set,
525 unsigned idx)
526 {
527 struct radv_descriptor_state *descriptors_state =
528 radv_get_descriptors_state(cmd_buffer, bind_point);
529
530 descriptors_state->sets[idx] = set;
531
532 descriptors_state->valid |= (1u << idx); /* active descriptors */
533 descriptors_state->dirty |= (1u << idx);
534 }
535
536 static void
537 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
538 VkPipelineBindPoint bind_point)
539 {
540 struct radv_descriptor_state *descriptors_state =
541 radv_get_descriptors_state(cmd_buffer, bind_point);
542 struct radv_device *device = cmd_buffer->device;
543 struct radeon_cmdbuf *cs = cmd_buffer->cs;
544 uint32_t data[MAX_SETS * 2] = {};
545 uint64_t va;
546 unsigned i;
547 va = radv_buffer_get_va(device->trace_bo) + 24;
548
549 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
550 cmd_buffer->cs, 4 + MAX_SETS * 2);
551
552 for_each_bit(i, descriptors_state->valid) {
553 struct radv_descriptor_set *set = descriptors_state->sets[i];
554 data[i * 2] = (uintptr_t)set;
555 data[i * 2 + 1] = (uintptr_t)set >> 32;
556 }
557
558 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
559 }
560
561 struct radv_userdata_info *
562 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
563 gl_shader_stage stage,
564 int idx)
565 {
566 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
567 return &shader->info.user_sgprs_locs.shader_data[idx];
568 }
569
570 static void
571 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
572 struct radv_pipeline *pipeline,
573 gl_shader_stage stage,
574 int idx, uint64_t va)
575 {
576 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
577 uint32_t base_reg = pipeline->user_data_0[stage];
578 if (loc->sgpr_idx == -1)
579 return;
580
581 assert(loc->num_sgprs == (HAVE_32BIT_POINTERS ? 1 : 2));
582 assert(!loc->indirect);
583
584 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
585 base_reg + loc->sgpr_idx * 4, va, false);
586 }
587
588 static void
589 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
590 struct radv_pipeline *pipeline,
591 struct radv_descriptor_state *descriptors_state,
592 gl_shader_stage stage)
593 {
594 struct radv_device *device = cmd_buffer->device;
595 struct radeon_cmdbuf *cs = cmd_buffer->cs;
596 uint32_t sh_base = pipeline->user_data_0[stage];
597 struct radv_userdata_locations *locs =
598 &pipeline->shaders[stage]->info.user_sgprs_locs;
599 unsigned mask = locs->descriptor_sets_enabled;
600
601 mask &= descriptors_state->dirty & descriptors_state->valid;
602
603 while (mask) {
604 int start, count;
605
606 u_bit_scan_consecutive_range(&mask, &start, &count);
607
608 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
609 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
610
611 radv_emit_shader_pointer_head(cs, sh_offset, count,
612 HAVE_32BIT_POINTERS);
613 for (int i = 0; i < count; i++) {
614 struct radv_descriptor_set *set =
615 descriptors_state->sets[start + i];
616
617 radv_emit_shader_pointer_body(device, cs, set->va,
618 HAVE_32BIT_POINTERS);
619 }
620 }
621 }
622
623 static void
624 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
625 struct radv_pipeline *pipeline)
626 {
627 int num_samples = pipeline->graphics.ms.num_samples;
628 struct radv_multisample_state *ms = &pipeline->graphics.ms;
629 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
630
631 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
632 cmd_buffer->sample_positions_needed = true;
633
634 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
635 return;
636
637 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
638 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
639 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
640
641 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
642
643 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
644
645 /* GFX9: Flush DFSM when the AA mode changes. */
646 if (cmd_buffer->device->dfsm_allowed) {
647 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
648 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
649 }
650 }
651
652 static void
653 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
654 struct radv_shader_variant *shader)
655 {
656 uint64_t va;
657
658 if (!shader)
659 return;
660
661 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
662
663 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
664 }
665
666 static void
667 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
668 struct radv_pipeline *pipeline,
669 bool vertex_stage_only)
670 {
671 struct radv_cmd_state *state = &cmd_buffer->state;
672 uint32_t mask = state->prefetch_L2_mask;
673
674 if (vertex_stage_only) {
675 /* Fast prefetch path for starting draws as soon as possible.
676 */
677 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
678 RADV_PREFETCH_VBO_DESCRIPTORS);
679 }
680
681 if (mask & RADV_PREFETCH_VS)
682 radv_emit_shader_prefetch(cmd_buffer,
683 pipeline->shaders[MESA_SHADER_VERTEX]);
684
685 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
686 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
687
688 if (mask & RADV_PREFETCH_TCS)
689 radv_emit_shader_prefetch(cmd_buffer,
690 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
691
692 if (mask & RADV_PREFETCH_TES)
693 radv_emit_shader_prefetch(cmd_buffer,
694 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
695
696 if (mask & RADV_PREFETCH_GS) {
697 radv_emit_shader_prefetch(cmd_buffer,
698 pipeline->shaders[MESA_SHADER_GEOMETRY]);
699 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
700 }
701
702 if (mask & RADV_PREFETCH_PS)
703 radv_emit_shader_prefetch(cmd_buffer,
704 pipeline->shaders[MESA_SHADER_FRAGMENT]);
705
706 state->prefetch_L2_mask &= ~mask;
707 }
708
709 static void
710 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
711 {
712 if (!cmd_buffer->device->physical_device->rbplus_allowed)
713 return;
714
715 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
716 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
717 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
718
719 unsigned sx_ps_downconvert = 0;
720 unsigned sx_blend_opt_epsilon = 0;
721 unsigned sx_blend_opt_control = 0;
722
723 for (unsigned i = 0; i < subpass->color_count; ++i) {
724 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
725 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
726 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
727 continue;
728 }
729
730 int idx = subpass->color_attachments[i].attachment;
731 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
732
733 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
734 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
735 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
736 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
737
738 bool has_alpha, has_rgb;
739
740 /* Set if RGB and A are present. */
741 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
742
743 if (format == V_028C70_COLOR_8 ||
744 format == V_028C70_COLOR_16 ||
745 format == V_028C70_COLOR_32)
746 has_rgb = !has_alpha;
747 else
748 has_rgb = true;
749
750 /* Check the colormask and export format. */
751 if (!(colormask & 0x7))
752 has_rgb = false;
753 if (!(colormask & 0x8))
754 has_alpha = false;
755
756 if (spi_format == V_028714_SPI_SHADER_ZERO) {
757 has_rgb = false;
758 has_alpha = false;
759 }
760
761 /* Disable value checking for disabled channels. */
762 if (!has_rgb)
763 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
764 if (!has_alpha)
765 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
766
767 /* Enable down-conversion for 32bpp and smaller formats. */
768 switch (format) {
769 case V_028C70_COLOR_8:
770 case V_028C70_COLOR_8_8:
771 case V_028C70_COLOR_8_8_8_8:
772 /* For 1 and 2-channel formats, use the superset thereof. */
773 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
774 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
775 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
776 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
777 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
778 }
779 break;
780
781 case V_028C70_COLOR_5_6_5:
782 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
783 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
784 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
785 }
786 break;
787
788 case V_028C70_COLOR_1_5_5_5:
789 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
790 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
791 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
792 }
793 break;
794
795 case V_028C70_COLOR_4_4_4_4:
796 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
797 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
798 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
799 }
800 break;
801
802 case V_028C70_COLOR_32:
803 if (swap == V_028C70_SWAP_STD &&
804 spi_format == V_028714_SPI_SHADER_32_R)
805 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
806 else if (swap == V_028C70_SWAP_ALT_REV &&
807 spi_format == V_028714_SPI_SHADER_32_AR)
808 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
809 break;
810
811 case V_028C70_COLOR_16:
812 case V_028C70_COLOR_16_16:
813 /* For 1-channel formats, use the superset thereof. */
814 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
815 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
816 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
817 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
818 if (swap == V_028C70_SWAP_STD ||
819 swap == V_028C70_SWAP_STD_REV)
820 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
821 else
822 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
823 }
824 break;
825
826 case V_028C70_COLOR_10_11_11:
827 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
828 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
829 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
830 }
831 break;
832
833 case V_028C70_COLOR_2_10_10_10:
834 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
835 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
836 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
837 }
838 break;
839 }
840 }
841
842 for (unsigned i = subpass->color_count; i < 8; ++i) {
843 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
844 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
845 }
846 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
847 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
848 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
849 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
850 }
851
852 static void
853 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
854 {
855 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
856
857 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
858 return;
859
860 radv_update_multisample_state(cmd_buffer, pipeline);
861
862 cmd_buffer->scratch_size_needed =
863 MAX2(cmd_buffer->scratch_size_needed,
864 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
865
866 if (!cmd_buffer->state.emitted_pipeline ||
867 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
868 pipeline->graphics.can_use_guardband)
869 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
870
871 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
872
873 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
874 if (!pipeline->shaders[i])
875 continue;
876
877 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
878 pipeline->shaders[i]->bo);
879 }
880
881 if (radv_pipeline_has_gs(pipeline))
882 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
883 pipeline->gs_copy_shader->bo);
884
885 if (unlikely(cmd_buffer->device->trace_bo))
886 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
887
888 cmd_buffer->state.emitted_pipeline = pipeline;
889
890 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
891 }
892
893 static void
894 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
895 {
896 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
897 cmd_buffer->state.dynamic.viewport.viewports);
898 }
899
900 static void
901 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
902 {
903 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
904
905 si_write_scissors(cmd_buffer->cs, 0, count,
906 cmd_buffer->state.dynamic.scissor.scissors,
907 cmd_buffer->state.dynamic.viewport.viewports,
908 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
909 }
910
911 static void
912 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
913 {
914 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
915 return;
916
917 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
918 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
919 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
920 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
921 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
922 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
923 S_028214_BR_Y(rect.offset.y + rect.extent.height));
924 }
925 }
926
927 static void
928 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
929 {
930 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
931
932 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
933 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
934 }
935
936 static void
937 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
938 {
939 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
940
941 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
942 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
943 }
944
945 static void
946 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
947 {
948 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
949
950 radeon_set_context_reg_seq(cmd_buffer->cs,
951 R_028430_DB_STENCILREFMASK, 2);
952 radeon_emit(cmd_buffer->cs,
953 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
954 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
955 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
956 S_028430_STENCILOPVAL(1));
957 radeon_emit(cmd_buffer->cs,
958 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
959 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
960 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
961 S_028434_STENCILOPVAL_BF(1));
962 }
963
964 static void
965 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
966 {
967 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
968
969 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
970 fui(d->depth_bounds.min));
971 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
972 fui(d->depth_bounds.max));
973 }
974
975 static void
976 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
977 {
978 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
979 unsigned slope = fui(d->depth_bias.slope * 16.0f);
980 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
981
982
983 radeon_set_context_reg_seq(cmd_buffer->cs,
984 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
985 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
986 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
987 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
988 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
989 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
990 }
991
992 static void
993 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
994 int index,
995 struct radv_attachment_info *att,
996 struct radv_image *image,
997 VkImageLayout layout)
998 {
999 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1000 struct radv_color_buffer_info *cb = &att->cb;
1001 uint32_t cb_color_info = cb->cb_color_info;
1002
1003 if (!radv_layout_dcc_compressed(image, layout,
1004 radv_image_queue_family_mask(image,
1005 cmd_buffer->queue_family_index,
1006 cmd_buffer->queue_family_index))) {
1007 cb_color_info &= C_028C70_DCC_ENABLE;
1008 }
1009
1010 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1011 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1012 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1013 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1014 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1015 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1016 radeon_emit(cmd_buffer->cs, cb_color_info);
1017 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1018 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1019 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1020 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1021 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1022 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1023
1024 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1025 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1026 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1027
1028 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1029 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1030 } else {
1031 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1032 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1033 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1034 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1035 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1036 radeon_emit(cmd_buffer->cs, cb_color_info);
1037 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1038 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1039 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1040 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1041 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1042 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1043
1044 if (is_vi) { /* DCC BASE */
1045 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1046 }
1047 }
1048 }
1049
1050 static void
1051 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1052 struct radv_ds_buffer_info *ds,
1053 struct radv_image *image, VkImageLayout layout,
1054 bool requires_cond_write)
1055 {
1056 uint32_t db_z_info = ds->db_z_info;
1057 uint32_t db_z_info_reg;
1058
1059 if (!radv_image_is_tc_compat_htile(image))
1060 return;
1061
1062 if (!radv_layout_has_htile(image, layout,
1063 radv_image_queue_family_mask(image,
1064 cmd_buffer->queue_family_index,
1065 cmd_buffer->queue_family_index))) {
1066 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1067 }
1068
1069 db_z_info &= C_028040_ZRANGE_PRECISION;
1070
1071 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1072 db_z_info_reg = R_028038_DB_Z_INFO;
1073 } else {
1074 db_z_info_reg = R_028040_DB_Z_INFO;
1075 }
1076
1077 /* When we don't know the last fast clear value we need to emit a
1078 * conditional packet, otherwise we can update DB_Z_INFO directly.
1079 */
1080 if (requires_cond_write) {
1081 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_WRITE, 7, 0));
1082
1083 const uint32_t write_space = 0 << 8; /* register */
1084 const uint32_t poll_space = 1 << 4; /* memory */
1085 const uint32_t function = 3 << 0; /* equal to the reference */
1086 const uint32_t options = write_space | poll_space | function;
1087 radeon_emit(cmd_buffer->cs, options);
1088
1089 /* poll address - location of the depth clear value */
1090 uint64_t va = radv_buffer_get_va(image->bo);
1091 va += image->offset + image->clear_value_offset;
1092
1093 /* In presence of stencil format, we have to adjust the base
1094 * address because the first value is the stencil clear value.
1095 */
1096 if (vk_format_is_stencil(image->vk_format))
1097 va += 4;
1098
1099 radeon_emit(cmd_buffer->cs, va);
1100 radeon_emit(cmd_buffer->cs, va >> 32);
1101
1102 radeon_emit(cmd_buffer->cs, fui(0.0f)); /* reference value */
1103 radeon_emit(cmd_buffer->cs, (uint32_t)-1); /* comparison mask */
1104 radeon_emit(cmd_buffer->cs, db_z_info_reg >> 2); /* write address low */
1105 radeon_emit(cmd_buffer->cs, 0u); /* write address high */
1106 radeon_emit(cmd_buffer->cs, db_z_info);
1107 } else {
1108 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1109 }
1110 }
1111
1112 static void
1113 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1114 struct radv_ds_buffer_info *ds,
1115 struct radv_image *image,
1116 VkImageLayout layout)
1117 {
1118 uint32_t db_z_info = ds->db_z_info;
1119 uint32_t db_stencil_info = ds->db_stencil_info;
1120
1121 if (!radv_layout_has_htile(image, layout,
1122 radv_image_queue_family_mask(image,
1123 cmd_buffer->queue_family_index,
1124 cmd_buffer->queue_family_index))) {
1125 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1126 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1127 }
1128
1129 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1130 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1131
1132
1133 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1134 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1135 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1136 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1137 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1138
1139 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1140 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1141 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1142 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1143 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1144 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1145 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1146 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1147 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1148 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1149 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1150
1151 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1152 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1153 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1154 } else {
1155 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1156
1157 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1158 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1159 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1160 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1161 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1162 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1163 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1164 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1165 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1166 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1167
1168 }
1169
1170 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1171 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1172
1173 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1174 ds->pa_su_poly_offset_db_fmt_cntl);
1175 }
1176
1177 /**
1178 * Update the fast clear depth/stencil values if the image is bound as a
1179 * depth/stencil buffer.
1180 */
1181 static void
1182 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1183 struct radv_image *image,
1184 VkClearDepthStencilValue ds_clear_value,
1185 VkImageAspectFlags aspects)
1186 {
1187 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1188 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1189 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1190 struct radv_attachment_info *att;
1191 uint32_t att_idx;
1192
1193 if (!framebuffer || !subpass)
1194 return;
1195
1196 att_idx = subpass->depth_stencil_attachment.attachment;
1197 if (att_idx == VK_ATTACHMENT_UNUSED)
1198 return;
1199
1200 att = &framebuffer->attachments[att_idx];
1201 if (att->attachment->image != image)
1202 return;
1203
1204 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1205 radeon_emit(cs, ds_clear_value.stencil);
1206 radeon_emit(cs, fui(ds_clear_value.depth));
1207
1208 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1209 * only needed when clearing Z to 0.0.
1210 */
1211 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1212 ds_clear_value.depth == 0.0) {
1213 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1214
1215 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1216 layout, false);
1217 }
1218 }
1219
1220 /**
1221 * Set the clear depth/stencil values to the image's metadata.
1222 */
1223 static void
1224 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1225 struct radv_image *image,
1226 VkClearDepthStencilValue ds_clear_value,
1227 VkImageAspectFlags aspects)
1228 {
1229 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1230 uint64_t va = radv_buffer_get_va(image->bo);
1231 unsigned reg_offset = 0, reg_count = 0;
1232
1233 va += image->offset + image->clear_value_offset;
1234
1235 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1236 ++reg_count;
1237 } else {
1238 ++reg_offset;
1239 va += 4;
1240 }
1241 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1242 ++reg_count;
1243
1244 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1245 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1246 S_370_WR_CONFIRM(1) |
1247 S_370_ENGINE_SEL(V_370_PFP));
1248 radeon_emit(cs, va);
1249 radeon_emit(cs, va >> 32);
1250 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1251 radeon_emit(cs, ds_clear_value.stencil);
1252 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1253 radeon_emit(cs, fui(ds_clear_value.depth));
1254 }
1255
1256 /**
1257 * Update the clear depth/stencil values for this image.
1258 */
1259 void
1260 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1261 struct radv_image *image,
1262 VkClearDepthStencilValue ds_clear_value,
1263 VkImageAspectFlags aspects)
1264 {
1265 assert(radv_image_has_htile(image));
1266
1267 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1268
1269 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1270 aspects);
1271 }
1272
1273 /**
1274 * Load the clear depth/stencil values from the image's metadata.
1275 */
1276 static void
1277 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1278 struct radv_image *image)
1279 {
1280 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1281 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1282 uint64_t va = radv_buffer_get_va(image->bo);
1283 unsigned reg_offset = 0, reg_count = 0;
1284
1285 va += image->offset + image->clear_value_offset;
1286
1287 if (!radv_image_has_htile(image))
1288 return;
1289
1290 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1291 ++reg_count;
1292 } else {
1293 ++reg_offset;
1294 va += 4;
1295 }
1296 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1297 ++reg_count;
1298
1299 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1300 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1301 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1302 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1303 radeon_emit(cs, va);
1304 radeon_emit(cs, va >> 32);
1305 radeon_emit(cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
1306 radeon_emit(cs, 0);
1307
1308 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1309 radeon_emit(cs, 0);
1310 }
1311
1312 /*
1313 * With DCC some colors don't require CMASK elimination before being
1314 * used as a texture. This sets a predicate value to determine if the
1315 * cmask eliminate is required.
1316 */
1317 void
1318 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1319 struct radv_image *image,
1320 bool value)
1321 {
1322 uint64_t pred_val = value;
1323 uint64_t va = radv_buffer_get_va(image->bo);
1324 va += image->offset + image->dcc_pred_offset;
1325
1326 assert(radv_image_has_dcc(image));
1327
1328 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1329 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1330 S_370_WR_CONFIRM(1) |
1331 S_370_ENGINE_SEL(V_370_PFP));
1332 radeon_emit(cmd_buffer->cs, va);
1333 radeon_emit(cmd_buffer->cs, va >> 32);
1334 radeon_emit(cmd_buffer->cs, pred_val);
1335 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1336 }
1337
1338 /**
1339 * Update the fast clear color values if the image is bound as a color buffer.
1340 */
1341 static void
1342 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1343 struct radv_image *image,
1344 int cb_idx,
1345 uint32_t color_values[2])
1346 {
1347 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1348 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1349 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1350 struct radv_attachment_info *att;
1351 uint32_t att_idx;
1352
1353 if (!framebuffer || !subpass)
1354 return;
1355
1356 att_idx = subpass->color_attachments[cb_idx].attachment;
1357 if (att_idx == VK_ATTACHMENT_UNUSED)
1358 return;
1359
1360 att = &framebuffer->attachments[att_idx];
1361 if (att->attachment->image != image)
1362 return;
1363
1364 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1365 radeon_emit(cs, color_values[0]);
1366 radeon_emit(cs, color_values[1]);
1367 }
1368
1369 /**
1370 * Set the clear color values to the image's metadata.
1371 */
1372 static void
1373 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1374 struct radv_image *image,
1375 uint32_t color_values[2])
1376 {
1377 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1378 uint64_t va = radv_buffer_get_va(image->bo);
1379
1380 va += image->offset + image->clear_value_offset;
1381
1382 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1383
1384 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1385 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1386 S_370_WR_CONFIRM(1) |
1387 S_370_ENGINE_SEL(V_370_PFP));
1388 radeon_emit(cs, va);
1389 radeon_emit(cs, va >> 32);
1390 radeon_emit(cs, color_values[0]);
1391 radeon_emit(cs, color_values[1]);
1392 }
1393
1394 /**
1395 * Update the clear color values for this image.
1396 */
1397 void
1398 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1399 struct radv_image *image,
1400 int cb_idx,
1401 uint32_t color_values[2])
1402 {
1403 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1404
1405 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
1406
1407 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1408 color_values);
1409 }
1410
1411 /**
1412 * Load the clear color values from the image's metadata.
1413 */
1414 static void
1415 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1416 struct radv_image *image,
1417 int cb_idx)
1418 {
1419 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1420 uint64_t va = radv_buffer_get_va(image->bo);
1421
1422 va += image->offset + image->clear_value_offset;
1423
1424 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1425 return;
1426
1427 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1428
1429 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1430 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1431 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1432 COPY_DATA_COUNT_SEL);
1433 radeon_emit(cs, va);
1434 radeon_emit(cs, va >> 32);
1435 radeon_emit(cs, reg >> 2);
1436 radeon_emit(cs, 0);
1437
1438 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1439 radeon_emit(cs, 0);
1440 }
1441
1442 static void
1443 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1444 {
1445 int i;
1446 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1447 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1448
1449 /* this may happen for inherited secondary recording */
1450 if (!framebuffer)
1451 return;
1452
1453 for (i = 0; i < 8; ++i) {
1454 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1455 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1456 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1457 continue;
1458 }
1459
1460 int idx = subpass->color_attachments[i].attachment;
1461 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1462 struct radv_image *image = att->attachment->image;
1463 VkImageLayout layout = subpass->color_attachments[i].layout;
1464
1465 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1466
1467 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1468 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1469
1470 radv_load_color_clear_metadata(cmd_buffer, image, i);
1471 }
1472
1473 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1474 int idx = subpass->depth_stencil_attachment.attachment;
1475 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1476 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1477 struct radv_image *image = att->attachment->image;
1478 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1479 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1480 cmd_buffer->queue_family_index,
1481 cmd_buffer->queue_family_index);
1482 /* We currently don't support writing decompressed HTILE */
1483 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1484 radv_layout_is_htile_compressed(image, layout, queue_mask));
1485
1486 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1487
1488 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1489 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1490 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1491 }
1492 radv_load_ds_clear_metadata(cmd_buffer, image);
1493 } else {
1494 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1495 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1496 else
1497 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1498
1499 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1500 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1501 }
1502 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1503 S_028208_BR_X(framebuffer->width) |
1504 S_028208_BR_Y(framebuffer->height));
1505
1506 if (cmd_buffer->device->dfsm_allowed) {
1507 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1508 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1509 }
1510
1511 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1512 }
1513
1514 static void
1515 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1516 {
1517 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1518 struct radv_cmd_state *state = &cmd_buffer->state;
1519
1520 if (state->index_type != state->last_index_type) {
1521 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1522 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1523 2, state->index_type);
1524 } else {
1525 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1526 radeon_emit(cs, state->index_type);
1527 }
1528
1529 state->last_index_type = state->index_type;
1530 }
1531
1532 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1533 radeon_emit(cs, state->index_va);
1534 radeon_emit(cs, state->index_va >> 32);
1535
1536 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1537 radeon_emit(cs, state->max_index_count);
1538
1539 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1540 }
1541
1542 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1543 {
1544 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1545 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1546 uint32_t pa_sc_mode_cntl_1 =
1547 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1548 uint32_t db_count_control;
1549
1550 if(!cmd_buffer->state.active_occlusion_queries) {
1551 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1552 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1553 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1554 has_perfect_queries) {
1555 /* Re-enable out-of-order rasterization if the
1556 * bound pipeline supports it and if it's has
1557 * been disabled before starting any perfect
1558 * occlusion queries.
1559 */
1560 radeon_set_context_reg(cmd_buffer->cs,
1561 R_028A4C_PA_SC_MODE_CNTL_1,
1562 pa_sc_mode_cntl_1);
1563 }
1564 }
1565 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1566 } else {
1567 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1568 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1569
1570 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1571 db_count_control =
1572 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1573 S_028004_SAMPLE_RATE(sample_rate) |
1574 S_028004_ZPASS_ENABLE(1) |
1575 S_028004_SLICE_EVEN_ENABLE(1) |
1576 S_028004_SLICE_ODD_ENABLE(1);
1577
1578 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1579 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1580 has_perfect_queries) {
1581 /* If the bound pipeline has enabled
1582 * out-of-order rasterization, we should
1583 * disable it before starting any perfect
1584 * occlusion queries.
1585 */
1586 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1587
1588 radeon_set_context_reg(cmd_buffer->cs,
1589 R_028A4C_PA_SC_MODE_CNTL_1,
1590 pa_sc_mode_cntl_1);
1591 }
1592 } else {
1593 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1594 S_028004_SAMPLE_RATE(sample_rate);
1595 }
1596 }
1597
1598 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1599 }
1600
1601 static void
1602 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1603 {
1604 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1605
1606 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1607 radv_emit_viewport(cmd_buffer);
1608
1609 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1610 !cmd_buffer->device->physical_device->has_scissor_bug)
1611 radv_emit_scissor(cmd_buffer);
1612
1613 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1614 radv_emit_line_width(cmd_buffer);
1615
1616 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1617 radv_emit_blend_constants(cmd_buffer);
1618
1619 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1620 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1621 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1622 radv_emit_stencil(cmd_buffer);
1623
1624 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1625 radv_emit_depth_bounds(cmd_buffer);
1626
1627 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1628 radv_emit_depth_bias(cmd_buffer);
1629
1630 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1631 radv_emit_discard_rectangle(cmd_buffer);
1632
1633 cmd_buffer->state.dirty &= ~states;
1634 }
1635
1636 static void
1637 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1638 VkPipelineBindPoint bind_point)
1639 {
1640 struct radv_descriptor_state *descriptors_state =
1641 radv_get_descriptors_state(cmd_buffer, bind_point);
1642 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1643 unsigned bo_offset;
1644
1645 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1646 set->mapped_ptr,
1647 &bo_offset))
1648 return;
1649
1650 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1651 set->va += bo_offset;
1652 }
1653
1654 static void
1655 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1656 VkPipelineBindPoint bind_point)
1657 {
1658 struct radv_descriptor_state *descriptors_state =
1659 radv_get_descriptors_state(cmd_buffer, bind_point);
1660 uint32_t size = MAX_SETS * 2 * 4;
1661 uint32_t offset;
1662 void *ptr;
1663
1664 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1665 256, &offset, &ptr))
1666 return;
1667
1668 for (unsigned i = 0; i < MAX_SETS; i++) {
1669 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1670 uint64_t set_va = 0;
1671 struct radv_descriptor_set *set = descriptors_state->sets[i];
1672 if (descriptors_state->valid & (1u << i))
1673 set_va = set->va;
1674 uptr[0] = set_va & 0xffffffff;
1675 uptr[1] = set_va >> 32;
1676 }
1677
1678 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1679 va += offset;
1680
1681 if (cmd_buffer->state.pipeline) {
1682 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1683 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1684 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1685
1686 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1687 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1688 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1689
1690 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1691 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1692 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1693
1694 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1695 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1696 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1697
1698 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1699 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1700 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1701 }
1702
1703 if (cmd_buffer->state.compute_pipeline)
1704 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1705 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1706 }
1707
1708 static void
1709 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1710 VkShaderStageFlags stages)
1711 {
1712 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1713 VK_PIPELINE_BIND_POINT_COMPUTE :
1714 VK_PIPELINE_BIND_POINT_GRAPHICS;
1715 struct radv_descriptor_state *descriptors_state =
1716 radv_get_descriptors_state(cmd_buffer, bind_point);
1717
1718 if (!descriptors_state->dirty)
1719 return;
1720
1721 if (descriptors_state->push_dirty)
1722 radv_flush_push_descriptors(cmd_buffer, bind_point);
1723
1724 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1725 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1726 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1727 }
1728
1729 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1730 cmd_buffer->cs,
1731 MAX_SETS * MESA_SHADER_STAGES * 4);
1732
1733 if (cmd_buffer->state.pipeline) {
1734 radv_foreach_stage(stage, stages) {
1735 if (!cmd_buffer->state.pipeline->shaders[stage])
1736 continue;
1737
1738 radv_emit_descriptor_pointers(cmd_buffer,
1739 cmd_buffer->state.pipeline,
1740 descriptors_state, stage);
1741 }
1742 }
1743
1744 if (cmd_buffer->state.compute_pipeline &&
1745 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
1746 radv_emit_descriptor_pointers(cmd_buffer,
1747 cmd_buffer->state.compute_pipeline,
1748 descriptors_state,
1749 MESA_SHADER_COMPUTE);
1750 }
1751
1752 descriptors_state->dirty = 0;
1753 descriptors_state->push_dirty = false;
1754
1755 if (unlikely(cmd_buffer->device->trace_bo))
1756 radv_save_descriptors(cmd_buffer, bind_point);
1757
1758 assert(cmd_buffer->cs->cdw <= cdw_max);
1759 }
1760
1761 static void
1762 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1763 VkShaderStageFlags stages)
1764 {
1765 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1766 ? cmd_buffer->state.compute_pipeline
1767 : cmd_buffer->state.pipeline;
1768 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1769 VK_PIPELINE_BIND_POINT_COMPUTE :
1770 VK_PIPELINE_BIND_POINT_GRAPHICS;
1771 struct radv_descriptor_state *descriptors_state =
1772 radv_get_descriptors_state(cmd_buffer, bind_point);
1773 struct radv_pipeline_layout *layout = pipeline->layout;
1774 struct radv_shader_variant *shader, *prev_shader;
1775 unsigned offset;
1776 void *ptr;
1777 uint64_t va;
1778
1779 stages &= cmd_buffer->push_constant_stages;
1780 if (!stages ||
1781 (!layout->push_constant_size && !layout->dynamic_offset_count))
1782 return;
1783
1784 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1785 16 * layout->dynamic_offset_count,
1786 256, &offset, &ptr))
1787 return;
1788
1789 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1790 memcpy((char*)ptr + layout->push_constant_size,
1791 descriptors_state->dynamic_buffers,
1792 16 * layout->dynamic_offset_count);
1793
1794 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1795 va += offset;
1796
1797 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1798 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1799
1800 prev_shader = NULL;
1801 radv_foreach_stage(stage, stages) {
1802 shader = radv_get_shader(pipeline, stage);
1803
1804 /* Avoid redundantly emitting the address for merged stages. */
1805 if (shader && shader != prev_shader) {
1806 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1807 AC_UD_PUSH_CONSTANTS, va);
1808
1809 prev_shader = shader;
1810 }
1811 }
1812
1813 cmd_buffer->push_constant_stages &= ~stages;
1814 assert(cmd_buffer->cs->cdw <= cdw_max);
1815 }
1816
1817 static void
1818 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1819 bool pipeline_is_dirty)
1820 {
1821 if ((pipeline_is_dirty ||
1822 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1823 cmd_buffer->state.pipeline->vertex_elements.count &&
1824 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
1825 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1826 unsigned vb_offset;
1827 void *vb_ptr;
1828 uint32_t i = 0;
1829 uint32_t count = velems->count;
1830 uint64_t va;
1831
1832 /* allocate some descriptor state for vertex buffers */
1833 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1834 &vb_offset, &vb_ptr))
1835 return;
1836
1837 for (i = 0; i < count; i++) {
1838 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1839 uint32_t offset;
1840 int vb = velems->binding[i];
1841 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1842 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1843
1844 va = radv_buffer_get_va(buffer->bo);
1845
1846 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1847 va += offset + buffer->offset;
1848 desc[0] = va;
1849 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1850 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1851 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1852 else
1853 desc[2] = buffer->size - offset;
1854 desc[3] = velems->rsrc_word3[i];
1855 }
1856
1857 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1858 va += vb_offset;
1859
1860 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1861 AC_UD_VS_VERTEX_BUFFERS, va);
1862
1863 cmd_buffer->state.vb_va = va;
1864 cmd_buffer->state.vb_size = count * 16;
1865 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
1866 }
1867 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1868 }
1869
1870 static void
1871 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1872 {
1873 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
1874 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1875 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1876 }
1877
1878 static void
1879 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1880 bool instanced_draw, bool indirect_draw,
1881 uint32_t draw_vertex_count)
1882 {
1883 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1884 struct radv_cmd_state *state = &cmd_buffer->state;
1885 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1886 uint32_t ia_multi_vgt_param;
1887 int32_t primitive_reset_en;
1888
1889 /* Draw state. */
1890 ia_multi_vgt_param =
1891 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1892 indirect_draw, draw_vertex_count);
1893
1894 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1895 if (info->chip_class >= GFX9) {
1896 radeon_set_uconfig_reg_idx(cs,
1897 R_030960_IA_MULTI_VGT_PARAM,
1898 4, ia_multi_vgt_param);
1899 } else if (info->chip_class >= CIK) {
1900 radeon_set_context_reg_idx(cs,
1901 R_028AA8_IA_MULTI_VGT_PARAM,
1902 1, ia_multi_vgt_param);
1903 } else {
1904 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1905 ia_multi_vgt_param);
1906 }
1907 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1908 }
1909
1910 /* Primitive restart. */
1911 primitive_reset_en =
1912 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1913
1914 if (primitive_reset_en != state->last_primitive_reset_en) {
1915 state->last_primitive_reset_en = primitive_reset_en;
1916 if (info->chip_class >= GFX9) {
1917 radeon_set_uconfig_reg(cs,
1918 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1919 primitive_reset_en);
1920 } else {
1921 radeon_set_context_reg(cs,
1922 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1923 primitive_reset_en);
1924 }
1925 }
1926
1927 if (primitive_reset_en) {
1928 uint32_t primitive_reset_index =
1929 state->index_type ? 0xffffffffu : 0xffffu;
1930
1931 if (primitive_reset_index != state->last_primitive_reset_index) {
1932 radeon_set_context_reg(cs,
1933 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1934 primitive_reset_index);
1935 state->last_primitive_reset_index = primitive_reset_index;
1936 }
1937 }
1938 }
1939
1940 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1941 VkPipelineStageFlags src_stage_mask)
1942 {
1943 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1944 VK_PIPELINE_STAGE_TRANSFER_BIT |
1945 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1946 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1947 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1948 }
1949
1950 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1951 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1952 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1953 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1954 VK_PIPELINE_STAGE_TRANSFER_BIT |
1955 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1956 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1957 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1958 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1959 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1960 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1961 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
1962 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1963 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1964 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT)) {
1965 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1966 }
1967 }
1968
1969 static enum radv_cmd_flush_bits
1970 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1971 VkAccessFlags src_flags,
1972 struct radv_image *image)
1973 {
1974 bool flush_CB_meta = true, flush_DB_meta = true;
1975 enum radv_cmd_flush_bits flush_bits = 0;
1976 uint32_t b;
1977
1978 if (image) {
1979 if (!radv_image_has_CB_metadata(image))
1980 flush_CB_meta = false;
1981 if (!radv_image_has_htile(image))
1982 flush_DB_meta = false;
1983 }
1984
1985 for_each_bit(b, src_flags) {
1986 switch ((VkAccessFlagBits)(1 << b)) {
1987 case VK_ACCESS_SHADER_WRITE_BIT:
1988 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1989 break;
1990 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1991 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
1992 if (flush_CB_meta)
1993 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1994 break;
1995 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1996 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
1997 if (flush_DB_meta)
1998 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1999 break;
2000 case VK_ACCESS_TRANSFER_WRITE_BIT:
2001 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2002 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2003 RADV_CMD_FLAG_INV_GLOBAL_L2;
2004
2005 if (flush_CB_meta)
2006 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2007 if (flush_DB_meta)
2008 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2009 break;
2010 default:
2011 break;
2012 }
2013 }
2014 return flush_bits;
2015 }
2016
2017 static enum radv_cmd_flush_bits
2018 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2019 VkAccessFlags dst_flags,
2020 struct radv_image *image)
2021 {
2022 bool flush_CB_meta = true, flush_DB_meta = true;
2023 enum radv_cmd_flush_bits flush_bits = 0;
2024 bool flush_CB = true, flush_DB = true;
2025 uint32_t b;
2026
2027 if (image) {
2028 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2029 flush_CB = false;
2030 flush_DB = false;
2031 }
2032
2033 if (!radv_image_has_CB_metadata(image))
2034 flush_CB_meta = false;
2035 if (!radv_image_has_htile(image))
2036 flush_DB_meta = false;
2037 }
2038
2039 for_each_bit(b, dst_flags) {
2040 switch ((VkAccessFlagBits)(1 << b)) {
2041 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2042 case VK_ACCESS_INDEX_READ_BIT:
2043 break;
2044 case VK_ACCESS_UNIFORM_READ_BIT:
2045 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2046 break;
2047 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2048 case VK_ACCESS_SHADER_READ_BIT:
2049 case VK_ACCESS_TRANSFER_READ_BIT:
2050 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2051 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2052 RADV_CMD_FLAG_INV_GLOBAL_L2;
2053 break;
2054 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2055 if (flush_CB)
2056 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2057 if (flush_CB_meta)
2058 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2059 break;
2060 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2061 if (flush_DB)
2062 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2063 if (flush_DB_meta)
2064 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2065 break;
2066 default:
2067 break;
2068 }
2069 }
2070 return flush_bits;
2071 }
2072
2073 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2074 const struct radv_subpass_barrier *barrier)
2075 {
2076 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2077 NULL);
2078 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2079 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2080 NULL);
2081 }
2082
2083 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2084 struct radv_subpass_attachment att)
2085 {
2086 unsigned idx = att.attachment;
2087 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2088 VkImageSubresourceRange range;
2089 range.aspectMask = 0;
2090 range.baseMipLevel = view->base_mip;
2091 range.levelCount = 1;
2092 range.baseArrayLayer = view->base_layer;
2093 range.layerCount = cmd_buffer->state.framebuffer->layers;
2094
2095 radv_handle_image_transition(cmd_buffer,
2096 view->image,
2097 cmd_buffer->state.attachments[idx].current_layout,
2098 att.layout, 0, 0, &range,
2099 cmd_buffer->state.attachments[idx].pending_clear_aspects);
2100
2101 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2102
2103
2104 }
2105
2106 void
2107 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2108 const struct radv_subpass *subpass, bool transitions)
2109 {
2110 if (transitions) {
2111 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2112
2113 for (unsigned i = 0; i < subpass->color_count; ++i) {
2114 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2115 radv_handle_subpass_image_transition(cmd_buffer,
2116 subpass->color_attachments[i]);
2117 }
2118
2119 for (unsigned i = 0; i < subpass->input_count; ++i) {
2120 radv_handle_subpass_image_transition(cmd_buffer,
2121 subpass->input_attachments[i]);
2122 }
2123
2124 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2125 radv_handle_subpass_image_transition(cmd_buffer,
2126 subpass->depth_stencil_attachment);
2127 }
2128 }
2129
2130 cmd_buffer->state.subpass = subpass;
2131
2132 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2133 }
2134
2135 static VkResult
2136 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2137 struct radv_render_pass *pass,
2138 const VkRenderPassBeginInfo *info)
2139 {
2140 struct radv_cmd_state *state = &cmd_buffer->state;
2141
2142 if (pass->attachment_count == 0) {
2143 state->attachments = NULL;
2144 return VK_SUCCESS;
2145 }
2146
2147 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2148 pass->attachment_count *
2149 sizeof(state->attachments[0]),
2150 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2151 if (state->attachments == NULL) {
2152 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2153 return cmd_buffer->record_result;
2154 }
2155
2156 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2157 struct radv_render_pass_attachment *att = &pass->attachments[i];
2158 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2159 VkImageAspectFlags clear_aspects = 0;
2160
2161 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2162 /* color attachment */
2163 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2164 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2165 }
2166 } else {
2167 /* depthstencil attachment */
2168 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2169 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2170 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2171 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2172 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2173 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2174 }
2175 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2176 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2177 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2178 }
2179 }
2180
2181 state->attachments[i].pending_clear_aspects = clear_aspects;
2182 state->attachments[i].cleared_views = 0;
2183 if (clear_aspects && info) {
2184 assert(info->clearValueCount > i);
2185 state->attachments[i].clear_value = info->pClearValues[i];
2186 }
2187
2188 state->attachments[i].current_layout = att->initial_layout;
2189 }
2190
2191 return VK_SUCCESS;
2192 }
2193
2194 VkResult radv_AllocateCommandBuffers(
2195 VkDevice _device,
2196 const VkCommandBufferAllocateInfo *pAllocateInfo,
2197 VkCommandBuffer *pCommandBuffers)
2198 {
2199 RADV_FROM_HANDLE(radv_device, device, _device);
2200 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2201
2202 VkResult result = VK_SUCCESS;
2203 uint32_t i;
2204
2205 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2206
2207 if (!list_empty(&pool->free_cmd_buffers)) {
2208 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2209
2210 list_del(&cmd_buffer->pool_link);
2211 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2212
2213 result = radv_reset_cmd_buffer(cmd_buffer);
2214 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2215 cmd_buffer->level = pAllocateInfo->level;
2216
2217 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2218 } else {
2219 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2220 &pCommandBuffers[i]);
2221 }
2222 if (result != VK_SUCCESS)
2223 break;
2224 }
2225
2226 if (result != VK_SUCCESS) {
2227 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2228 i, pCommandBuffers);
2229
2230 /* From the Vulkan 1.0.66 spec:
2231 *
2232 * "vkAllocateCommandBuffers can be used to create multiple
2233 * command buffers. If the creation of any of those command
2234 * buffers fails, the implementation must destroy all
2235 * successfully created command buffer objects from this
2236 * command, set all entries of the pCommandBuffers array to
2237 * NULL and return the error."
2238 */
2239 memset(pCommandBuffers, 0,
2240 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2241 }
2242
2243 return result;
2244 }
2245
2246 void radv_FreeCommandBuffers(
2247 VkDevice device,
2248 VkCommandPool commandPool,
2249 uint32_t commandBufferCount,
2250 const VkCommandBuffer *pCommandBuffers)
2251 {
2252 for (uint32_t i = 0; i < commandBufferCount; i++) {
2253 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2254
2255 if (cmd_buffer) {
2256 if (cmd_buffer->pool) {
2257 list_del(&cmd_buffer->pool_link);
2258 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2259 } else
2260 radv_cmd_buffer_destroy(cmd_buffer);
2261
2262 }
2263 }
2264 }
2265
2266 VkResult radv_ResetCommandBuffer(
2267 VkCommandBuffer commandBuffer,
2268 VkCommandBufferResetFlags flags)
2269 {
2270 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2271 return radv_reset_cmd_buffer(cmd_buffer);
2272 }
2273
2274 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2275 {
2276 struct radv_device *device = cmd_buffer->device;
2277 if (device->gfx_init) {
2278 uint64_t va = radv_buffer_get_va(device->gfx_init);
2279 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init);
2280 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2281 radeon_emit(cmd_buffer->cs, va);
2282 radeon_emit(cmd_buffer->cs, va >> 32);
2283 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2284 } else
2285 si_init_config(cmd_buffer);
2286 }
2287
2288 VkResult radv_BeginCommandBuffer(
2289 VkCommandBuffer commandBuffer,
2290 const VkCommandBufferBeginInfo *pBeginInfo)
2291 {
2292 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2293 VkResult result = VK_SUCCESS;
2294
2295 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2296 /* If the command buffer has already been resetted with
2297 * vkResetCommandBuffer, no need to do it again.
2298 */
2299 result = radv_reset_cmd_buffer(cmd_buffer);
2300 if (result != VK_SUCCESS)
2301 return result;
2302 }
2303
2304 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2305 cmd_buffer->state.last_primitive_reset_en = -1;
2306 cmd_buffer->state.last_index_type = -1;
2307 cmd_buffer->state.last_num_instances = -1;
2308 cmd_buffer->state.last_vertex_offset = -1;
2309 cmd_buffer->state.last_first_instance = -1;
2310 cmd_buffer->usage_flags = pBeginInfo->flags;
2311
2312 /* setup initial configuration into command buffer */
2313 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2314 switch (cmd_buffer->queue_family_index) {
2315 case RADV_QUEUE_GENERAL:
2316 emit_gfx_buffer_state(cmd_buffer);
2317 break;
2318 case RADV_QUEUE_COMPUTE:
2319 si_init_compute(cmd_buffer);
2320 break;
2321 case RADV_QUEUE_TRANSFER:
2322 default:
2323 break;
2324 }
2325 }
2326
2327 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
2328 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
2329 assert(pBeginInfo->pInheritanceInfo);
2330 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2331 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2332
2333 struct radv_subpass *subpass =
2334 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2335
2336 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2337 if (result != VK_SUCCESS)
2338 return result;
2339
2340 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2341 }
2342
2343 if (unlikely(cmd_buffer->device->trace_bo)) {
2344 struct radv_device *device = cmd_buffer->device;
2345
2346 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
2347 device->trace_bo);
2348
2349 radv_cmd_buffer_trace_emit(cmd_buffer);
2350 }
2351
2352 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2353
2354 return result;
2355 }
2356
2357 void radv_CmdBindVertexBuffers(
2358 VkCommandBuffer commandBuffer,
2359 uint32_t firstBinding,
2360 uint32_t bindingCount,
2361 const VkBuffer* pBuffers,
2362 const VkDeviceSize* pOffsets)
2363 {
2364 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2365 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2366 bool changed = false;
2367
2368 /* We have to defer setting up vertex buffer since we need the buffer
2369 * stride from the pipeline. */
2370
2371 assert(firstBinding + bindingCount <= MAX_VBS);
2372 for (uint32_t i = 0; i < bindingCount; i++) {
2373 uint32_t idx = firstBinding + i;
2374
2375 if (!changed &&
2376 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2377 vb[idx].offset != pOffsets[i])) {
2378 changed = true;
2379 }
2380
2381 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2382 vb[idx].offset = pOffsets[i];
2383
2384 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2385 vb[idx].buffer->bo);
2386 }
2387
2388 if (!changed) {
2389 /* No state changes. */
2390 return;
2391 }
2392
2393 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2394 }
2395
2396 void radv_CmdBindIndexBuffer(
2397 VkCommandBuffer commandBuffer,
2398 VkBuffer buffer,
2399 VkDeviceSize offset,
2400 VkIndexType indexType)
2401 {
2402 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2403 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2404
2405 if (cmd_buffer->state.index_buffer == index_buffer &&
2406 cmd_buffer->state.index_offset == offset &&
2407 cmd_buffer->state.index_type == indexType) {
2408 /* No state changes. */
2409 return;
2410 }
2411
2412 cmd_buffer->state.index_buffer = index_buffer;
2413 cmd_buffer->state.index_offset = offset;
2414 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2415 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2416 cmd_buffer->state.index_va += index_buffer->offset + offset;
2417
2418 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2419 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2420 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2421 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
2422 }
2423
2424
2425 static void
2426 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2427 VkPipelineBindPoint bind_point,
2428 struct radv_descriptor_set *set, unsigned idx)
2429 {
2430 struct radeon_winsys *ws = cmd_buffer->device->ws;
2431
2432 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2433
2434 assert(set);
2435 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2436
2437 if (!cmd_buffer->device->use_global_bo_list) {
2438 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2439 if (set->descriptors[j])
2440 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
2441 }
2442
2443 if(set->bo)
2444 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
2445 }
2446
2447 void radv_CmdBindDescriptorSets(
2448 VkCommandBuffer commandBuffer,
2449 VkPipelineBindPoint pipelineBindPoint,
2450 VkPipelineLayout _layout,
2451 uint32_t firstSet,
2452 uint32_t descriptorSetCount,
2453 const VkDescriptorSet* pDescriptorSets,
2454 uint32_t dynamicOffsetCount,
2455 const uint32_t* pDynamicOffsets)
2456 {
2457 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2458 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2459 unsigned dyn_idx = 0;
2460
2461 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2462 struct radv_descriptor_state *descriptors_state =
2463 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2464
2465 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2466 unsigned idx = i + firstSet;
2467 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2468 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2469
2470 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2471 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2472 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
2473 assert(dyn_idx < dynamicOffsetCount);
2474
2475 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2476 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2477 dst[0] = va;
2478 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2479 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2480 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2481 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2482 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2483 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2484 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2485 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2486 cmd_buffer->push_constant_stages |=
2487 set->layout->dynamic_shader_stages;
2488 }
2489 }
2490 }
2491
2492 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2493 struct radv_descriptor_set *set,
2494 struct radv_descriptor_set_layout *layout,
2495 VkPipelineBindPoint bind_point)
2496 {
2497 struct radv_descriptor_state *descriptors_state =
2498 radv_get_descriptors_state(cmd_buffer, bind_point);
2499 set->size = layout->size;
2500 set->layout = layout;
2501
2502 if (descriptors_state->push_set.capacity < set->size) {
2503 size_t new_size = MAX2(set->size, 1024);
2504 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2505 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2506
2507 free(set->mapped_ptr);
2508 set->mapped_ptr = malloc(new_size);
2509
2510 if (!set->mapped_ptr) {
2511 descriptors_state->push_set.capacity = 0;
2512 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2513 return false;
2514 }
2515
2516 descriptors_state->push_set.capacity = new_size;
2517 }
2518
2519 return true;
2520 }
2521
2522 void radv_meta_push_descriptor_set(
2523 struct radv_cmd_buffer* cmd_buffer,
2524 VkPipelineBindPoint pipelineBindPoint,
2525 VkPipelineLayout _layout,
2526 uint32_t set,
2527 uint32_t descriptorWriteCount,
2528 const VkWriteDescriptorSet* pDescriptorWrites)
2529 {
2530 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2531 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2532 unsigned bo_offset;
2533
2534 assert(set == 0);
2535 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2536
2537 push_set->size = layout->set[set].layout->size;
2538 push_set->layout = layout->set[set].layout;
2539
2540 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2541 &bo_offset,
2542 (void**) &push_set->mapped_ptr))
2543 return;
2544
2545 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2546 push_set->va += bo_offset;
2547
2548 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2549 radv_descriptor_set_to_handle(push_set),
2550 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2551
2552 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2553 }
2554
2555 void radv_CmdPushDescriptorSetKHR(
2556 VkCommandBuffer commandBuffer,
2557 VkPipelineBindPoint pipelineBindPoint,
2558 VkPipelineLayout _layout,
2559 uint32_t set,
2560 uint32_t descriptorWriteCount,
2561 const VkWriteDescriptorSet* pDescriptorWrites)
2562 {
2563 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2564 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2565 struct radv_descriptor_state *descriptors_state =
2566 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2567 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2568
2569 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2570
2571 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2572 layout->set[set].layout,
2573 pipelineBindPoint))
2574 return;
2575
2576 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2577 radv_descriptor_set_to_handle(push_set),
2578 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2579
2580 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2581 descriptors_state->push_dirty = true;
2582 }
2583
2584 void radv_CmdPushDescriptorSetWithTemplateKHR(
2585 VkCommandBuffer commandBuffer,
2586 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2587 VkPipelineLayout _layout,
2588 uint32_t set,
2589 const void* pData)
2590 {
2591 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2592 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2593 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2594 struct radv_descriptor_state *descriptors_state =
2595 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2596 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2597
2598 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2599
2600 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2601 layout->set[set].layout,
2602 templ->bind_point))
2603 return;
2604
2605 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2606 descriptorUpdateTemplate, pData);
2607
2608 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2609 descriptors_state->push_dirty = true;
2610 }
2611
2612 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2613 VkPipelineLayout layout,
2614 VkShaderStageFlags stageFlags,
2615 uint32_t offset,
2616 uint32_t size,
2617 const void* pValues)
2618 {
2619 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2620 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2621 cmd_buffer->push_constant_stages |= stageFlags;
2622 }
2623
2624 VkResult radv_EndCommandBuffer(
2625 VkCommandBuffer commandBuffer)
2626 {
2627 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2628
2629 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2630 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2631 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2632 si_emit_cache_flush(cmd_buffer);
2633 }
2634
2635 /* Make sure CP DMA is idle at the end of IBs because the kernel
2636 * doesn't wait for it.
2637 */
2638 si_cp_dma_wait_for_idle(cmd_buffer);
2639
2640 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2641
2642 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2643 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2644
2645 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2646
2647 return cmd_buffer->record_result;
2648 }
2649
2650 static void
2651 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2652 {
2653 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2654
2655 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2656 return;
2657
2658 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2659
2660 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2661 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2662
2663 cmd_buffer->compute_scratch_size_needed =
2664 MAX2(cmd_buffer->compute_scratch_size_needed,
2665 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2666
2667 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2668 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
2669
2670 if (unlikely(cmd_buffer->device->trace_bo))
2671 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2672 }
2673
2674 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2675 VkPipelineBindPoint bind_point)
2676 {
2677 struct radv_descriptor_state *descriptors_state =
2678 radv_get_descriptors_state(cmd_buffer, bind_point);
2679
2680 descriptors_state->dirty |= descriptors_state->valid;
2681 }
2682
2683 void radv_CmdBindPipeline(
2684 VkCommandBuffer commandBuffer,
2685 VkPipelineBindPoint pipelineBindPoint,
2686 VkPipeline _pipeline)
2687 {
2688 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2689 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2690
2691 switch (pipelineBindPoint) {
2692 case VK_PIPELINE_BIND_POINT_COMPUTE:
2693 if (cmd_buffer->state.compute_pipeline == pipeline)
2694 return;
2695 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2696
2697 cmd_buffer->state.compute_pipeline = pipeline;
2698 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2699 break;
2700 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2701 if (cmd_buffer->state.pipeline == pipeline)
2702 return;
2703 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2704
2705 cmd_buffer->state.pipeline = pipeline;
2706 if (!pipeline)
2707 break;
2708
2709 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2710 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2711
2712 /* the new vertex shader might not have the same user regs */
2713 cmd_buffer->state.last_first_instance = -1;
2714 cmd_buffer->state.last_vertex_offset = -1;
2715
2716 /* Prefetch all pipeline shaders at first draw time. */
2717 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
2718
2719 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2720
2721 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2722 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2723 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2724 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2725
2726 if (radv_pipeline_has_tess(pipeline))
2727 cmd_buffer->tess_rings_needed = true;
2728 break;
2729 default:
2730 assert(!"invalid bind point");
2731 break;
2732 }
2733 }
2734
2735 void radv_CmdSetViewport(
2736 VkCommandBuffer commandBuffer,
2737 uint32_t firstViewport,
2738 uint32_t viewportCount,
2739 const VkViewport* pViewports)
2740 {
2741 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2742 struct radv_cmd_state *state = &cmd_buffer->state;
2743 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2744
2745 assert(firstViewport < MAX_VIEWPORTS);
2746 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2747
2748 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2749 viewportCount * sizeof(*pViewports));
2750
2751 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2752 }
2753
2754 void radv_CmdSetScissor(
2755 VkCommandBuffer commandBuffer,
2756 uint32_t firstScissor,
2757 uint32_t scissorCount,
2758 const VkRect2D* pScissors)
2759 {
2760 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2761 struct radv_cmd_state *state = &cmd_buffer->state;
2762 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2763
2764 assert(firstScissor < MAX_SCISSORS);
2765 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2766
2767 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2768 scissorCount * sizeof(*pScissors));
2769
2770 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2771 }
2772
2773 void radv_CmdSetLineWidth(
2774 VkCommandBuffer commandBuffer,
2775 float lineWidth)
2776 {
2777 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2778 cmd_buffer->state.dynamic.line_width = lineWidth;
2779 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2780 }
2781
2782 void radv_CmdSetDepthBias(
2783 VkCommandBuffer commandBuffer,
2784 float depthBiasConstantFactor,
2785 float depthBiasClamp,
2786 float depthBiasSlopeFactor)
2787 {
2788 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2789
2790 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2791 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2792 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2793
2794 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2795 }
2796
2797 void radv_CmdSetBlendConstants(
2798 VkCommandBuffer commandBuffer,
2799 const float blendConstants[4])
2800 {
2801 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2802
2803 memcpy(cmd_buffer->state.dynamic.blend_constants,
2804 blendConstants, sizeof(float) * 4);
2805
2806 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2807 }
2808
2809 void radv_CmdSetDepthBounds(
2810 VkCommandBuffer commandBuffer,
2811 float minDepthBounds,
2812 float maxDepthBounds)
2813 {
2814 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2815
2816 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2817 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2818
2819 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2820 }
2821
2822 void radv_CmdSetStencilCompareMask(
2823 VkCommandBuffer commandBuffer,
2824 VkStencilFaceFlags faceMask,
2825 uint32_t compareMask)
2826 {
2827 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2828
2829 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2830 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2831 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2832 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2833
2834 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2835 }
2836
2837 void radv_CmdSetStencilWriteMask(
2838 VkCommandBuffer commandBuffer,
2839 VkStencilFaceFlags faceMask,
2840 uint32_t writeMask)
2841 {
2842 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2843
2844 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2845 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2846 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2847 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2848
2849 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2850 }
2851
2852 void radv_CmdSetStencilReference(
2853 VkCommandBuffer commandBuffer,
2854 VkStencilFaceFlags faceMask,
2855 uint32_t reference)
2856 {
2857 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2858
2859 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2860 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2861 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2862 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2863
2864 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2865 }
2866
2867 void radv_CmdSetDiscardRectangleEXT(
2868 VkCommandBuffer commandBuffer,
2869 uint32_t firstDiscardRectangle,
2870 uint32_t discardRectangleCount,
2871 const VkRect2D* pDiscardRectangles)
2872 {
2873 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2874 struct radv_cmd_state *state = &cmd_buffer->state;
2875 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
2876
2877 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
2878 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
2879
2880 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
2881 pDiscardRectangles, discardRectangleCount);
2882
2883 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
2884 }
2885
2886 void radv_CmdExecuteCommands(
2887 VkCommandBuffer commandBuffer,
2888 uint32_t commandBufferCount,
2889 const VkCommandBuffer* pCmdBuffers)
2890 {
2891 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2892
2893 assert(commandBufferCount > 0);
2894
2895 /* Emit pending flushes on primary prior to executing secondary */
2896 si_emit_cache_flush(primary);
2897
2898 for (uint32_t i = 0; i < commandBufferCount; i++) {
2899 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2900
2901 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2902 secondary->scratch_size_needed);
2903 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2904 secondary->compute_scratch_size_needed);
2905
2906 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2907 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2908 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2909 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2910 if (secondary->tess_rings_needed)
2911 primary->tess_rings_needed = true;
2912 if (secondary->sample_positions_needed)
2913 primary->sample_positions_needed = true;
2914
2915 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2916
2917
2918 /* When the secondary command buffer is compute only we don't
2919 * need to re-emit the current graphics pipeline.
2920 */
2921 if (secondary->state.emitted_pipeline) {
2922 primary->state.emitted_pipeline =
2923 secondary->state.emitted_pipeline;
2924 }
2925
2926 /* When the secondary command buffer is graphics only we don't
2927 * need to re-emit the current compute pipeline.
2928 */
2929 if (secondary->state.emitted_compute_pipeline) {
2930 primary->state.emitted_compute_pipeline =
2931 secondary->state.emitted_compute_pipeline;
2932 }
2933
2934 /* Only re-emit the draw packets when needed. */
2935 if (secondary->state.last_primitive_reset_en != -1) {
2936 primary->state.last_primitive_reset_en =
2937 secondary->state.last_primitive_reset_en;
2938 }
2939
2940 if (secondary->state.last_primitive_reset_index) {
2941 primary->state.last_primitive_reset_index =
2942 secondary->state.last_primitive_reset_index;
2943 }
2944
2945 if (secondary->state.last_ia_multi_vgt_param) {
2946 primary->state.last_ia_multi_vgt_param =
2947 secondary->state.last_ia_multi_vgt_param;
2948 }
2949
2950 primary->state.last_first_instance = secondary->state.last_first_instance;
2951 primary->state.last_num_instances = secondary->state.last_num_instances;
2952 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
2953
2954 if (secondary->state.last_index_type != -1) {
2955 primary->state.last_index_type =
2956 secondary->state.last_index_type;
2957 }
2958 }
2959
2960 /* After executing commands from secondary buffers we have to dirty
2961 * some states.
2962 */
2963 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2964 RADV_CMD_DIRTY_INDEX_BUFFER |
2965 RADV_CMD_DIRTY_DYNAMIC_ALL;
2966 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
2967 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
2968 }
2969
2970 VkResult radv_CreateCommandPool(
2971 VkDevice _device,
2972 const VkCommandPoolCreateInfo* pCreateInfo,
2973 const VkAllocationCallbacks* pAllocator,
2974 VkCommandPool* pCmdPool)
2975 {
2976 RADV_FROM_HANDLE(radv_device, device, _device);
2977 struct radv_cmd_pool *pool;
2978
2979 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2980 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2981 if (pool == NULL)
2982 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2983
2984 if (pAllocator)
2985 pool->alloc = *pAllocator;
2986 else
2987 pool->alloc = device->alloc;
2988
2989 list_inithead(&pool->cmd_buffers);
2990 list_inithead(&pool->free_cmd_buffers);
2991
2992 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2993
2994 *pCmdPool = radv_cmd_pool_to_handle(pool);
2995
2996 return VK_SUCCESS;
2997
2998 }
2999
3000 void radv_DestroyCommandPool(
3001 VkDevice _device,
3002 VkCommandPool commandPool,
3003 const VkAllocationCallbacks* pAllocator)
3004 {
3005 RADV_FROM_HANDLE(radv_device, device, _device);
3006 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3007
3008 if (!pool)
3009 return;
3010
3011 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3012 &pool->cmd_buffers, pool_link) {
3013 radv_cmd_buffer_destroy(cmd_buffer);
3014 }
3015
3016 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3017 &pool->free_cmd_buffers, pool_link) {
3018 radv_cmd_buffer_destroy(cmd_buffer);
3019 }
3020
3021 vk_free2(&device->alloc, pAllocator, pool);
3022 }
3023
3024 VkResult radv_ResetCommandPool(
3025 VkDevice device,
3026 VkCommandPool commandPool,
3027 VkCommandPoolResetFlags flags)
3028 {
3029 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3030 VkResult result;
3031
3032 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3033 &pool->cmd_buffers, pool_link) {
3034 result = radv_reset_cmd_buffer(cmd_buffer);
3035 if (result != VK_SUCCESS)
3036 return result;
3037 }
3038
3039 return VK_SUCCESS;
3040 }
3041
3042 void radv_TrimCommandPool(
3043 VkDevice device,
3044 VkCommandPool commandPool,
3045 VkCommandPoolTrimFlagsKHR flags)
3046 {
3047 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3048
3049 if (!pool)
3050 return;
3051
3052 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3053 &pool->free_cmd_buffers, pool_link) {
3054 radv_cmd_buffer_destroy(cmd_buffer);
3055 }
3056 }
3057
3058 void radv_CmdBeginRenderPass(
3059 VkCommandBuffer commandBuffer,
3060 const VkRenderPassBeginInfo* pRenderPassBegin,
3061 VkSubpassContents contents)
3062 {
3063 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3064 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3065 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3066
3067 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3068 cmd_buffer->cs, 2048);
3069 MAYBE_UNUSED VkResult result;
3070
3071 cmd_buffer->state.framebuffer = framebuffer;
3072 cmd_buffer->state.pass = pass;
3073 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3074
3075 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3076 if (result != VK_SUCCESS)
3077 return;
3078
3079 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
3080 assert(cmd_buffer->cs->cdw <= cdw_max);
3081
3082 radv_cmd_buffer_clear_subpass(cmd_buffer);
3083 }
3084
3085 void radv_CmdBeginRenderPass2KHR(
3086 VkCommandBuffer commandBuffer,
3087 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
3088 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
3089 {
3090 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
3091 pSubpassBeginInfo->contents);
3092 }
3093
3094 void radv_CmdNextSubpass(
3095 VkCommandBuffer commandBuffer,
3096 VkSubpassContents contents)
3097 {
3098 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3099
3100 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3101
3102 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
3103 2048);
3104
3105 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
3106 radv_cmd_buffer_clear_subpass(cmd_buffer);
3107 }
3108
3109 void radv_CmdNextSubpass2KHR(
3110 VkCommandBuffer commandBuffer,
3111 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
3112 const VkSubpassEndInfoKHR* pSubpassEndInfo)
3113 {
3114 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
3115 }
3116
3117 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3118 {
3119 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3120 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3121 if (!radv_get_shader(pipeline, stage))
3122 continue;
3123
3124 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3125 if (loc->sgpr_idx == -1)
3126 continue;
3127 uint32_t base_reg = pipeline->user_data_0[stage];
3128 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3129
3130 }
3131 if (pipeline->gs_copy_shader) {
3132 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3133 if (loc->sgpr_idx != -1) {
3134 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3135 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3136 }
3137 }
3138 }
3139
3140 static void
3141 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3142 uint32_t vertex_count)
3143 {
3144 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3145 radeon_emit(cmd_buffer->cs, vertex_count);
3146 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3147 S_0287F0_USE_OPAQUE(0));
3148 }
3149
3150 static void
3151 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3152 uint64_t index_va,
3153 uint32_t index_count)
3154 {
3155 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
3156 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3157 radeon_emit(cmd_buffer->cs, index_va);
3158 radeon_emit(cmd_buffer->cs, index_va >> 32);
3159 radeon_emit(cmd_buffer->cs, index_count);
3160 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3161 }
3162
3163 static void
3164 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3165 bool indexed,
3166 uint32_t draw_count,
3167 uint64_t count_va,
3168 uint32_t stride)
3169 {
3170 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3171 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3172 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3173 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
3174 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3175 bool predicating = cmd_buffer->state.predicating;
3176 assert(base_reg);
3177
3178 /* just reset draw state for vertex data */
3179 cmd_buffer->state.last_first_instance = -1;
3180 cmd_buffer->state.last_num_instances = -1;
3181 cmd_buffer->state.last_vertex_offset = -1;
3182
3183 if (draw_count == 1 && !count_va && !draw_id_enable) {
3184 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3185 PKT3_DRAW_INDIRECT, 3, predicating));
3186 radeon_emit(cs, 0);
3187 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3188 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3189 radeon_emit(cs, di_src_sel);
3190 } else {
3191 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3192 PKT3_DRAW_INDIRECT_MULTI,
3193 8, predicating));
3194 radeon_emit(cs, 0);
3195 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3196 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3197 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3198 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3199 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3200 radeon_emit(cs, draw_count); /* count */
3201 radeon_emit(cs, count_va); /* count_addr */
3202 radeon_emit(cs, count_va >> 32);
3203 radeon_emit(cs, stride); /* stride */
3204 radeon_emit(cs, di_src_sel);
3205 }
3206 }
3207
3208 struct radv_draw_info {
3209 /**
3210 * Number of vertices.
3211 */
3212 uint32_t count;
3213
3214 /**
3215 * Index of the first vertex.
3216 */
3217 int32_t vertex_offset;
3218
3219 /**
3220 * First instance id.
3221 */
3222 uint32_t first_instance;
3223
3224 /**
3225 * Number of instances.
3226 */
3227 uint32_t instance_count;
3228
3229 /**
3230 * First index (indexed draws only).
3231 */
3232 uint32_t first_index;
3233
3234 /**
3235 * Whether it's an indexed draw.
3236 */
3237 bool indexed;
3238
3239 /**
3240 * Indirect draw parameters resource.
3241 */
3242 struct radv_buffer *indirect;
3243 uint64_t indirect_offset;
3244 uint32_t stride;
3245
3246 /**
3247 * Draw count parameters resource.
3248 */
3249 struct radv_buffer *count_buffer;
3250 uint64_t count_buffer_offset;
3251 };
3252
3253 static void
3254 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3255 const struct radv_draw_info *info)
3256 {
3257 struct radv_cmd_state *state = &cmd_buffer->state;
3258 struct radeon_winsys *ws = cmd_buffer->device->ws;
3259 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3260
3261 if (info->indirect) {
3262 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3263 uint64_t count_va = 0;
3264
3265 va += info->indirect->offset + info->indirect_offset;
3266
3267 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3268
3269 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3270 radeon_emit(cs, 1);
3271 radeon_emit(cs, va);
3272 radeon_emit(cs, va >> 32);
3273
3274 if (info->count_buffer) {
3275 count_va = radv_buffer_get_va(info->count_buffer->bo);
3276 count_va += info->count_buffer->offset +
3277 info->count_buffer_offset;
3278
3279 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
3280 }
3281
3282 if (!state->subpass->view_mask) {
3283 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3284 info->indexed,
3285 info->count,
3286 count_va,
3287 info->stride);
3288 } else {
3289 unsigned i;
3290 for_each_bit(i, state->subpass->view_mask) {
3291 radv_emit_view_index(cmd_buffer, i);
3292
3293 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3294 info->indexed,
3295 info->count,
3296 count_va,
3297 info->stride);
3298 }
3299 }
3300 } else {
3301 assert(state->pipeline->graphics.vtx_base_sgpr);
3302
3303 if (info->vertex_offset != state->last_vertex_offset ||
3304 info->first_instance != state->last_first_instance) {
3305 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3306 state->pipeline->graphics.vtx_emit_num);
3307
3308 radeon_emit(cs, info->vertex_offset);
3309 radeon_emit(cs, info->first_instance);
3310 if (state->pipeline->graphics.vtx_emit_num == 3)
3311 radeon_emit(cs, 0);
3312 state->last_first_instance = info->first_instance;
3313 state->last_vertex_offset = info->vertex_offset;
3314 }
3315
3316 if (state->last_num_instances != info->instance_count) {
3317 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3318 radeon_emit(cs, info->instance_count);
3319 state->last_num_instances = info->instance_count;
3320 }
3321
3322 if (info->indexed) {
3323 int index_size = state->index_type ? 4 : 2;
3324 uint64_t index_va;
3325
3326 index_va = state->index_va;
3327 index_va += info->first_index * index_size;
3328
3329 if (!state->subpass->view_mask) {
3330 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3331 index_va,
3332 info->count);
3333 } else {
3334 unsigned i;
3335 for_each_bit(i, state->subpass->view_mask) {
3336 radv_emit_view_index(cmd_buffer, i);
3337
3338 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3339 index_va,
3340 info->count);
3341 }
3342 }
3343 } else {
3344 if (!state->subpass->view_mask) {
3345 radv_cs_emit_draw_packet(cmd_buffer, info->count);
3346 } else {
3347 unsigned i;
3348 for_each_bit(i, state->subpass->view_mask) {
3349 radv_emit_view_index(cmd_buffer, i);
3350
3351 radv_cs_emit_draw_packet(cmd_buffer,
3352 info->count);
3353 }
3354 }
3355 }
3356 }
3357 }
3358
3359 /*
3360 * Vega and raven have a bug which triggers if there are multiple context
3361 * register contexts active at the same time with different scissor values.
3362 *
3363 * There are two possible workarounds:
3364 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3365 * there is only ever 1 active set of scissor values at the same time.
3366 *
3367 * 2) Whenever the hardware switches contexts we have to set the scissor
3368 * registers again even if it is a noop. That way the new context gets
3369 * the correct scissor values.
3370 *
3371 * This implements option 2. radv_need_late_scissor_emission needs to
3372 * return true on affected HW if radv_emit_all_graphics_states sets
3373 * any context registers.
3374 */
3375 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
3376 bool indexed_draw)
3377 {
3378 struct radv_cmd_state *state = &cmd_buffer->state;
3379
3380 if (!cmd_buffer->device->physical_device->has_scissor_bug)
3381 return false;
3382
3383 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
3384
3385 /* Index & Vertex buffer don't change context regs, and pipeline is handled later. */
3386 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER | RADV_CMD_DIRTY_VERTEX_BUFFER | RADV_CMD_DIRTY_PIPELINE);
3387
3388 /* Assume all state changes except these two can imply context rolls. */
3389 if (cmd_buffer->state.dirty & used_states)
3390 return true;
3391
3392 if (cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3393 return true;
3394
3395 if (indexed_draw && state->pipeline->graphics.prim_restart_enable &&
3396 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
3397 return true;
3398
3399 return false;
3400 }
3401
3402 static void
3403 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3404 const struct radv_draw_info *info)
3405 {
3406 bool late_scissor_emission = radv_need_late_scissor_emission(cmd_buffer, info->indexed);
3407
3408 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3409 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3410 radv_emit_rbplus_state(cmd_buffer);
3411
3412 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3413 radv_emit_graphics_pipeline(cmd_buffer);
3414
3415 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3416 radv_emit_framebuffer_state(cmd_buffer);
3417
3418 if (info->indexed) {
3419 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3420 radv_emit_index_buffer(cmd_buffer);
3421 } else {
3422 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3423 * so the state must be re-emitted before the next indexed
3424 * draw.
3425 */
3426 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3427 cmd_buffer->state.last_index_type = -1;
3428 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3429 }
3430 }
3431
3432 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3433
3434 radv_emit_draw_registers(cmd_buffer, info->indexed,
3435 info->instance_count > 1, info->indirect,
3436 info->indirect ? 0 : info->count);
3437
3438 if (late_scissor_emission)
3439 radv_emit_scissor(cmd_buffer);
3440 }
3441
3442 static void
3443 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3444 const struct radv_draw_info *info)
3445 {
3446 bool has_prefetch =
3447 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3448 bool pipeline_is_dirty =
3449 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3450 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3451
3452 MAYBE_UNUSED unsigned cdw_max =
3453 radeon_check_space(cmd_buffer->device->ws,
3454 cmd_buffer->cs, 4096);
3455
3456 /* Use optimal packet order based on whether we need to sync the
3457 * pipeline.
3458 */
3459 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3460 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3461 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3462 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3463 /* If we have to wait for idle, set all states first, so that
3464 * all SET packets are processed in parallel with previous draw
3465 * calls. Then upload descriptors, set shader pointers, and
3466 * draw, and prefetch at the end. This ensures that the time
3467 * the CUs are idle is very short. (there are only SET_SH
3468 * packets between the wait and the draw)
3469 */
3470 radv_emit_all_graphics_states(cmd_buffer, info);
3471 si_emit_cache_flush(cmd_buffer);
3472 /* <-- CUs are idle here --> */
3473
3474 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3475
3476 radv_emit_draw_packets(cmd_buffer, info);
3477 /* <-- CUs are busy here --> */
3478
3479 /* Start prefetches after the draw has been started. Both will
3480 * run in parallel, but starting the draw first is more
3481 * important.
3482 */
3483 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3484 radv_emit_prefetch_L2(cmd_buffer,
3485 cmd_buffer->state.pipeline, false);
3486 }
3487 } else {
3488 /* If we don't wait for idle, start prefetches first, then set
3489 * states, and draw at the end.
3490 */
3491 si_emit_cache_flush(cmd_buffer);
3492
3493 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3494 /* Only prefetch the vertex shader and VBO descriptors
3495 * in order to start the draw as soon as possible.
3496 */
3497 radv_emit_prefetch_L2(cmd_buffer,
3498 cmd_buffer->state.pipeline, true);
3499 }
3500
3501 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3502
3503 radv_emit_all_graphics_states(cmd_buffer, info);
3504 radv_emit_draw_packets(cmd_buffer, info);
3505
3506 /* Prefetch the remaining shaders after the draw has been
3507 * started.
3508 */
3509 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3510 radv_emit_prefetch_L2(cmd_buffer,
3511 cmd_buffer->state.pipeline, false);
3512 }
3513 }
3514
3515 assert(cmd_buffer->cs->cdw <= cdw_max);
3516 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3517 }
3518
3519 void radv_CmdDraw(
3520 VkCommandBuffer commandBuffer,
3521 uint32_t vertexCount,
3522 uint32_t instanceCount,
3523 uint32_t firstVertex,
3524 uint32_t firstInstance)
3525 {
3526 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3527 struct radv_draw_info info = {};
3528
3529 info.count = vertexCount;
3530 info.instance_count = instanceCount;
3531 info.first_instance = firstInstance;
3532 info.vertex_offset = firstVertex;
3533
3534 radv_draw(cmd_buffer, &info);
3535 }
3536
3537 void radv_CmdDrawIndexed(
3538 VkCommandBuffer commandBuffer,
3539 uint32_t indexCount,
3540 uint32_t instanceCount,
3541 uint32_t firstIndex,
3542 int32_t vertexOffset,
3543 uint32_t firstInstance)
3544 {
3545 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3546 struct radv_draw_info info = {};
3547
3548 info.indexed = true;
3549 info.count = indexCount;
3550 info.instance_count = instanceCount;
3551 info.first_index = firstIndex;
3552 info.vertex_offset = vertexOffset;
3553 info.first_instance = firstInstance;
3554
3555 radv_draw(cmd_buffer, &info);
3556 }
3557
3558 void radv_CmdDrawIndirect(
3559 VkCommandBuffer commandBuffer,
3560 VkBuffer _buffer,
3561 VkDeviceSize offset,
3562 uint32_t drawCount,
3563 uint32_t stride)
3564 {
3565 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3566 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3567 struct radv_draw_info info = {};
3568
3569 info.count = drawCount;
3570 info.indirect = buffer;
3571 info.indirect_offset = offset;
3572 info.stride = stride;
3573
3574 radv_draw(cmd_buffer, &info);
3575 }
3576
3577 void radv_CmdDrawIndexedIndirect(
3578 VkCommandBuffer commandBuffer,
3579 VkBuffer _buffer,
3580 VkDeviceSize offset,
3581 uint32_t drawCount,
3582 uint32_t stride)
3583 {
3584 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3585 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3586 struct radv_draw_info info = {};
3587
3588 info.indexed = true;
3589 info.count = drawCount;
3590 info.indirect = buffer;
3591 info.indirect_offset = offset;
3592 info.stride = stride;
3593
3594 radv_draw(cmd_buffer, &info);
3595 }
3596
3597 void radv_CmdDrawIndirectCountAMD(
3598 VkCommandBuffer commandBuffer,
3599 VkBuffer _buffer,
3600 VkDeviceSize offset,
3601 VkBuffer _countBuffer,
3602 VkDeviceSize countBufferOffset,
3603 uint32_t maxDrawCount,
3604 uint32_t stride)
3605 {
3606 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3607 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3608 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3609 struct radv_draw_info info = {};
3610
3611 info.count = maxDrawCount;
3612 info.indirect = buffer;
3613 info.indirect_offset = offset;
3614 info.count_buffer = count_buffer;
3615 info.count_buffer_offset = countBufferOffset;
3616 info.stride = stride;
3617
3618 radv_draw(cmd_buffer, &info);
3619 }
3620
3621 void radv_CmdDrawIndexedIndirectCountAMD(
3622 VkCommandBuffer commandBuffer,
3623 VkBuffer _buffer,
3624 VkDeviceSize offset,
3625 VkBuffer _countBuffer,
3626 VkDeviceSize countBufferOffset,
3627 uint32_t maxDrawCount,
3628 uint32_t stride)
3629 {
3630 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3631 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3632 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3633 struct radv_draw_info info = {};
3634
3635 info.indexed = true;
3636 info.count = maxDrawCount;
3637 info.indirect = buffer;
3638 info.indirect_offset = offset;
3639 info.count_buffer = count_buffer;
3640 info.count_buffer_offset = countBufferOffset;
3641 info.stride = stride;
3642
3643 radv_draw(cmd_buffer, &info);
3644 }
3645
3646 void radv_CmdDrawIndirectCountKHR(
3647 VkCommandBuffer commandBuffer,
3648 VkBuffer _buffer,
3649 VkDeviceSize offset,
3650 VkBuffer _countBuffer,
3651 VkDeviceSize countBufferOffset,
3652 uint32_t maxDrawCount,
3653 uint32_t stride)
3654 {
3655 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3656 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3657 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3658 struct radv_draw_info info = {};
3659
3660 info.count = maxDrawCount;
3661 info.indirect = buffer;
3662 info.indirect_offset = offset;
3663 info.count_buffer = count_buffer;
3664 info.count_buffer_offset = countBufferOffset;
3665 info.stride = stride;
3666
3667 radv_draw(cmd_buffer, &info);
3668 }
3669
3670 void radv_CmdDrawIndexedIndirectCountKHR(
3671 VkCommandBuffer commandBuffer,
3672 VkBuffer _buffer,
3673 VkDeviceSize offset,
3674 VkBuffer _countBuffer,
3675 VkDeviceSize countBufferOffset,
3676 uint32_t maxDrawCount,
3677 uint32_t stride)
3678 {
3679 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3680 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3681 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3682 struct radv_draw_info info = {};
3683
3684 info.indexed = true;
3685 info.count = maxDrawCount;
3686 info.indirect = buffer;
3687 info.indirect_offset = offset;
3688 info.count_buffer = count_buffer;
3689 info.count_buffer_offset = countBufferOffset;
3690 info.stride = stride;
3691
3692 radv_draw(cmd_buffer, &info);
3693 }
3694
3695 struct radv_dispatch_info {
3696 /**
3697 * Determine the layout of the grid (in block units) to be used.
3698 */
3699 uint32_t blocks[3];
3700
3701 /**
3702 * A starting offset for the grid. If unaligned is set, the offset
3703 * must still be aligned.
3704 */
3705 uint32_t offsets[3];
3706 /**
3707 * Whether it's an unaligned compute dispatch.
3708 */
3709 bool unaligned;
3710
3711 /**
3712 * Indirect compute parameters resource.
3713 */
3714 struct radv_buffer *indirect;
3715 uint64_t indirect_offset;
3716 };
3717
3718 static void
3719 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3720 const struct radv_dispatch_info *info)
3721 {
3722 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3723 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3724 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3725 struct radeon_winsys *ws = cmd_buffer->device->ws;
3726 bool predicating = cmd_buffer->state.predicating;
3727 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3728 struct radv_userdata_info *loc;
3729
3730 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3731 AC_UD_CS_GRID_SIZE);
3732
3733 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3734
3735 if (info->indirect) {
3736 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3737
3738 va += info->indirect->offset + info->indirect_offset;
3739
3740 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3741
3742 if (loc->sgpr_idx != -1) {
3743 for (unsigned i = 0; i < 3; ++i) {
3744 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3745 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3746 COPY_DATA_DST_SEL(COPY_DATA_REG));
3747 radeon_emit(cs, (va + 4 * i));
3748 radeon_emit(cs, (va + 4 * i) >> 32);
3749 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3750 + loc->sgpr_idx * 4) >> 2) + i);
3751 radeon_emit(cs, 0);
3752 }
3753 }
3754
3755 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3756 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
3757 PKT3_SHADER_TYPE_S(1));
3758 radeon_emit(cs, va);
3759 radeon_emit(cs, va >> 32);
3760 radeon_emit(cs, dispatch_initiator);
3761 } else {
3762 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3763 PKT3_SHADER_TYPE_S(1));
3764 radeon_emit(cs, 1);
3765 radeon_emit(cs, va);
3766 radeon_emit(cs, va >> 32);
3767
3768 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
3769 PKT3_SHADER_TYPE_S(1));
3770 radeon_emit(cs, 0);
3771 radeon_emit(cs, dispatch_initiator);
3772 }
3773 } else {
3774 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3775 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
3776
3777 if (info->unaligned) {
3778 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3779 unsigned remainder[3];
3780
3781 /* If aligned, these should be an entire block size,
3782 * not 0.
3783 */
3784 remainder[0] = blocks[0] + cs_block_size[0] -
3785 align_u32_npot(blocks[0], cs_block_size[0]);
3786 remainder[1] = blocks[1] + cs_block_size[1] -
3787 align_u32_npot(blocks[1], cs_block_size[1]);
3788 remainder[2] = blocks[2] + cs_block_size[2] -
3789 align_u32_npot(blocks[2], cs_block_size[2]);
3790
3791 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3792 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3793 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3794
3795 for(unsigned i = 0; i < 3; ++i) {
3796 assert(offsets[i] % cs_block_size[i] == 0);
3797 offsets[i] /= cs_block_size[i];
3798 }
3799
3800 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3801 radeon_emit(cs,
3802 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3803 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3804 radeon_emit(cs,
3805 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3806 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3807 radeon_emit(cs,
3808 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3809 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3810
3811 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3812 }
3813
3814 if (loc->sgpr_idx != -1) {
3815 assert(!loc->indirect);
3816 assert(loc->num_sgprs == 3);
3817
3818 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3819 loc->sgpr_idx * 4, 3);
3820 radeon_emit(cs, blocks[0]);
3821 radeon_emit(cs, blocks[1]);
3822 radeon_emit(cs, blocks[2]);
3823 }
3824
3825 if (offsets[0] || offsets[1] || offsets[2]) {
3826 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
3827 radeon_emit(cs, offsets[0]);
3828 radeon_emit(cs, offsets[1]);
3829 radeon_emit(cs, offsets[2]);
3830
3831 /* The blocks in the packet are not counts but end values. */
3832 for (unsigned i = 0; i < 3; ++i)
3833 blocks[i] += offsets[i];
3834 } else {
3835 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
3836 }
3837
3838 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
3839 PKT3_SHADER_TYPE_S(1));
3840 radeon_emit(cs, blocks[0]);
3841 radeon_emit(cs, blocks[1]);
3842 radeon_emit(cs, blocks[2]);
3843 radeon_emit(cs, dispatch_initiator);
3844 }
3845
3846 assert(cmd_buffer->cs->cdw <= cdw_max);
3847 }
3848
3849 static void
3850 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3851 {
3852 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3853 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3854 }
3855
3856 static void
3857 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3858 const struct radv_dispatch_info *info)
3859 {
3860 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3861 bool has_prefetch =
3862 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3863 bool pipeline_is_dirty = pipeline &&
3864 pipeline != cmd_buffer->state.emitted_compute_pipeline;
3865
3866 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3867 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3868 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3869 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3870 /* If we have to wait for idle, set all states first, so that
3871 * all SET packets are processed in parallel with previous draw
3872 * calls. Then upload descriptors, set shader pointers, and
3873 * dispatch, and prefetch at the end. This ensures that the
3874 * time the CUs are idle is very short. (there are only SET_SH
3875 * packets between the wait and the draw)
3876 */
3877 radv_emit_compute_pipeline(cmd_buffer);
3878 si_emit_cache_flush(cmd_buffer);
3879 /* <-- CUs are idle here --> */
3880
3881 radv_upload_compute_shader_descriptors(cmd_buffer);
3882
3883 radv_emit_dispatch_packets(cmd_buffer, info);
3884 /* <-- CUs are busy here --> */
3885
3886 /* Start prefetches after the dispatch has been started. Both
3887 * will run in parallel, but starting the dispatch first is
3888 * more important.
3889 */
3890 if (has_prefetch && pipeline_is_dirty) {
3891 radv_emit_shader_prefetch(cmd_buffer,
3892 pipeline->shaders[MESA_SHADER_COMPUTE]);
3893 }
3894 } else {
3895 /* If we don't wait for idle, start prefetches first, then set
3896 * states, and dispatch at the end.
3897 */
3898 si_emit_cache_flush(cmd_buffer);
3899
3900 if (has_prefetch && pipeline_is_dirty) {
3901 radv_emit_shader_prefetch(cmd_buffer,
3902 pipeline->shaders[MESA_SHADER_COMPUTE]);
3903 }
3904
3905 radv_upload_compute_shader_descriptors(cmd_buffer);
3906
3907 radv_emit_compute_pipeline(cmd_buffer);
3908 radv_emit_dispatch_packets(cmd_buffer, info);
3909 }
3910
3911 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
3912 }
3913
3914 void radv_CmdDispatchBase(
3915 VkCommandBuffer commandBuffer,
3916 uint32_t base_x,
3917 uint32_t base_y,
3918 uint32_t base_z,
3919 uint32_t x,
3920 uint32_t y,
3921 uint32_t z)
3922 {
3923 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3924 struct radv_dispatch_info info = {};
3925
3926 info.blocks[0] = x;
3927 info.blocks[1] = y;
3928 info.blocks[2] = z;
3929
3930 info.offsets[0] = base_x;
3931 info.offsets[1] = base_y;
3932 info.offsets[2] = base_z;
3933 radv_dispatch(cmd_buffer, &info);
3934 }
3935
3936 void radv_CmdDispatch(
3937 VkCommandBuffer commandBuffer,
3938 uint32_t x,
3939 uint32_t y,
3940 uint32_t z)
3941 {
3942 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3943 }
3944
3945 void radv_CmdDispatchIndirect(
3946 VkCommandBuffer commandBuffer,
3947 VkBuffer _buffer,
3948 VkDeviceSize offset)
3949 {
3950 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3951 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3952 struct radv_dispatch_info info = {};
3953
3954 info.indirect = buffer;
3955 info.indirect_offset = offset;
3956
3957 radv_dispatch(cmd_buffer, &info);
3958 }
3959
3960 void radv_unaligned_dispatch(
3961 struct radv_cmd_buffer *cmd_buffer,
3962 uint32_t x,
3963 uint32_t y,
3964 uint32_t z)
3965 {
3966 struct radv_dispatch_info info = {};
3967
3968 info.blocks[0] = x;
3969 info.blocks[1] = y;
3970 info.blocks[2] = z;
3971 info.unaligned = 1;
3972
3973 radv_dispatch(cmd_buffer, &info);
3974 }
3975
3976 void radv_CmdEndRenderPass(
3977 VkCommandBuffer commandBuffer)
3978 {
3979 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3980
3981 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3982
3983 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3984
3985 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3986 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3987 radv_handle_subpass_image_transition(cmd_buffer,
3988 (struct radv_subpass_attachment){i, layout});
3989 }
3990
3991 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3992
3993 cmd_buffer->state.pass = NULL;
3994 cmd_buffer->state.subpass = NULL;
3995 cmd_buffer->state.attachments = NULL;
3996 cmd_buffer->state.framebuffer = NULL;
3997 }
3998
3999 void radv_CmdEndRenderPass2KHR(
4000 VkCommandBuffer commandBuffer,
4001 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4002 {
4003 radv_CmdEndRenderPass(commandBuffer);
4004 }
4005
4006 /*
4007 * For HTILE we have the following interesting clear words:
4008 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4009 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4010 * 0xfffffff0: Clear depth to 1.0
4011 * 0x00000000: Clear depth to 0.0
4012 */
4013 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
4014 struct radv_image *image,
4015 const VkImageSubresourceRange *range,
4016 uint32_t clear_word)
4017 {
4018 assert(range->baseMipLevel == 0);
4019 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
4020 unsigned layer_count = radv_get_layerCount(image, range);
4021 uint64_t size = image->surface.htile_slice_size * layer_count;
4022 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
4023 uint64_t offset = image->offset + image->htile_offset +
4024 image->surface.htile_slice_size * range->baseArrayLayer;
4025 struct radv_cmd_state *state = &cmd_buffer->state;
4026 VkClearDepthStencilValue value = {};
4027
4028 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4029 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4030
4031 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
4032 size, clear_word);
4033
4034 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4035
4036 if (vk_format_is_stencil(image->vk_format))
4037 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4038
4039 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4040 }
4041
4042 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4043 struct radv_image *image,
4044 VkImageLayout src_layout,
4045 VkImageLayout dst_layout,
4046 unsigned src_queue_mask,
4047 unsigned dst_queue_mask,
4048 const VkImageSubresourceRange *range,
4049 VkImageAspectFlags pending_clears)
4050 {
4051 if (!radv_image_has_htile(image))
4052 return;
4053
4054 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
4055 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
4056 /* TODO: merge with the clear if applicable */
4057 radv_initialize_htile(cmd_buffer, image, range, 0);
4058 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4059 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4060 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4061 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4062 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4063 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4064 VkImageSubresourceRange local_range = *range;
4065 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4066 local_range.baseMipLevel = 0;
4067 local_range.levelCount = 1;
4068
4069 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4070 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4071
4072 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
4073
4074 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4075 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4076 }
4077 }
4078
4079 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4080 struct radv_image *image, uint32_t value)
4081 {
4082 struct radv_cmd_state *state = &cmd_buffer->state;
4083
4084 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4085 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4086
4087 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
4088
4089 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4090 }
4091
4092 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4093 struct radv_image *image, uint32_t value)
4094 {
4095 struct radv_cmd_state *state = &cmd_buffer->state;
4096
4097 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4098 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4099
4100 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
4101
4102 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4103 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4104 }
4105
4106 /**
4107 * Initialize DCC/FMASK/CMASK metadata for a color image.
4108 */
4109 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4110 struct radv_image *image,
4111 VkImageLayout src_layout,
4112 VkImageLayout dst_layout,
4113 unsigned src_queue_mask,
4114 unsigned dst_queue_mask)
4115 {
4116 if (radv_image_has_cmask(image)) {
4117 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4118
4119 /* TODO: clarify this. */
4120 if (radv_image_has_fmask(image)) {
4121 value = 0xccccccccu;
4122 }
4123
4124 radv_initialise_cmask(cmd_buffer, image, value);
4125 }
4126
4127 if (radv_image_has_dcc(image)) {
4128 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4129
4130 if (radv_layout_dcc_compressed(image, dst_layout,
4131 dst_queue_mask)) {
4132 value = 0x20202020u;
4133 }
4134
4135 radv_initialize_dcc(cmd_buffer, image, value);
4136
4137 radv_set_dcc_need_cmask_elim_pred(cmd_buffer, image, false);
4138 }
4139
4140 if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
4141 uint32_t color_values[2] = {};
4142 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
4143 }
4144 }
4145
4146 /**
4147 * Handle color image transitions for DCC/FMASK/CMASK.
4148 */
4149 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4150 struct radv_image *image,
4151 VkImageLayout src_layout,
4152 VkImageLayout dst_layout,
4153 unsigned src_queue_mask,
4154 unsigned dst_queue_mask,
4155 const VkImageSubresourceRange *range)
4156 {
4157 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4158 radv_init_color_image_metadata(cmd_buffer, image,
4159 src_layout, dst_layout,
4160 src_queue_mask, dst_queue_mask);
4161 return;
4162 }
4163
4164 if (radv_image_has_dcc(image)) {
4165 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4166 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4167 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4168 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4169 radv_decompress_dcc(cmd_buffer, image, range);
4170 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4171 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4172 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4173 }
4174 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
4175 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4176 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4177 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4178 }
4179 }
4180 }
4181
4182 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4183 struct radv_image *image,
4184 VkImageLayout src_layout,
4185 VkImageLayout dst_layout,
4186 uint32_t src_family,
4187 uint32_t dst_family,
4188 const VkImageSubresourceRange *range,
4189 VkImageAspectFlags pending_clears)
4190 {
4191 if (image->exclusive && src_family != dst_family) {
4192 /* This is an acquire or a release operation and there will be
4193 * a corresponding release/acquire. Do the transition in the
4194 * most flexible queue. */
4195
4196 assert(src_family == cmd_buffer->queue_family_index ||
4197 dst_family == cmd_buffer->queue_family_index);
4198
4199 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4200 return;
4201
4202 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4203 (src_family == RADV_QUEUE_GENERAL ||
4204 dst_family == RADV_QUEUE_GENERAL))
4205 return;
4206 }
4207
4208 unsigned src_queue_mask =
4209 radv_image_queue_family_mask(image, src_family,
4210 cmd_buffer->queue_family_index);
4211 unsigned dst_queue_mask =
4212 radv_image_queue_family_mask(image, dst_family,
4213 cmd_buffer->queue_family_index);
4214
4215 if (vk_format_is_depth(image->vk_format)) {
4216 radv_handle_depth_image_transition(cmd_buffer, image,
4217 src_layout, dst_layout,
4218 src_queue_mask, dst_queue_mask,
4219 range, pending_clears);
4220 } else {
4221 radv_handle_color_image_transition(cmd_buffer, image,
4222 src_layout, dst_layout,
4223 src_queue_mask, dst_queue_mask,
4224 range);
4225 }
4226 }
4227
4228 struct radv_barrier_info {
4229 uint32_t eventCount;
4230 const VkEvent *pEvents;
4231 VkPipelineStageFlags srcStageMask;
4232 };
4233
4234 static void
4235 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
4236 uint32_t memoryBarrierCount,
4237 const VkMemoryBarrier *pMemoryBarriers,
4238 uint32_t bufferMemoryBarrierCount,
4239 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4240 uint32_t imageMemoryBarrierCount,
4241 const VkImageMemoryBarrier *pImageMemoryBarriers,
4242 const struct radv_barrier_info *info)
4243 {
4244 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4245 enum radv_cmd_flush_bits src_flush_bits = 0;
4246 enum radv_cmd_flush_bits dst_flush_bits = 0;
4247
4248 for (unsigned i = 0; i < info->eventCount; ++i) {
4249 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
4250 uint64_t va = radv_buffer_get_va(event->bo);
4251
4252 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4253
4254 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4255
4256 si_emit_wait_fence(cs, va, 1, 0xffffffff);
4257 assert(cmd_buffer->cs->cdw <= cdw_max);
4258 }
4259
4260 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4261 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
4262 NULL);
4263 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4264 NULL);
4265 }
4266
4267 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4268 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
4269 NULL);
4270 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4271 NULL);
4272 }
4273
4274 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4275 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4276
4277 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
4278 image);
4279 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4280 image);
4281 }
4282
4283 radv_stage_flush(cmd_buffer, info->srcStageMask);
4284 cmd_buffer->state.flush_bits |= src_flush_bits;
4285
4286 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4287 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4288 radv_handle_image_transition(cmd_buffer, image,
4289 pImageMemoryBarriers[i].oldLayout,
4290 pImageMemoryBarriers[i].newLayout,
4291 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4292 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4293 &pImageMemoryBarriers[i].subresourceRange,
4294 0);
4295 }
4296
4297 /* Make sure CP DMA is idle because the driver might have performed a
4298 * DMA operation for copying or filling buffers/images.
4299 */
4300 si_cp_dma_wait_for_idle(cmd_buffer);
4301
4302 cmd_buffer->state.flush_bits |= dst_flush_bits;
4303 }
4304
4305 void radv_CmdPipelineBarrier(
4306 VkCommandBuffer commandBuffer,
4307 VkPipelineStageFlags srcStageMask,
4308 VkPipelineStageFlags destStageMask,
4309 VkBool32 byRegion,
4310 uint32_t memoryBarrierCount,
4311 const VkMemoryBarrier* pMemoryBarriers,
4312 uint32_t bufferMemoryBarrierCount,
4313 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4314 uint32_t imageMemoryBarrierCount,
4315 const VkImageMemoryBarrier* pImageMemoryBarriers)
4316 {
4317 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4318 struct radv_barrier_info info;
4319
4320 info.eventCount = 0;
4321 info.pEvents = NULL;
4322 info.srcStageMask = srcStageMask;
4323
4324 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4325 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4326 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4327 }
4328
4329
4330 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4331 struct radv_event *event,
4332 VkPipelineStageFlags stageMask,
4333 unsigned value)
4334 {
4335 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4336 uint64_t va = radv_buffer_get_va(event->bo);
4337
4338 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4339
4340 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4341
4342 /* Flags that only require a top-of-pipe event. */
4343 VkPipelineStageFlags top_of_pipe_flags =
4344 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
4345
4346 /* Flags that only require a post-index-fetch event. */
4347 VkPipelineStageFlags post_index_fetch_flags =
4348 top_of_pipe_flags |
4349 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
4350 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
4351
4352 /* Make sure CP DMA is idle because the driver might have performed a
4353 * DMA operation for copying or filling buffers/images.
4354 */
4355 si_cp_dma_wait_for_idle(cmd_buffer);
4356
4357 /* TODO: Emit EOS events for syncing PS/CS stages. */
4358
4359 if (!(stageMask & ~top_of_pipe_flags)) {
4360 /* Just need to sync the PFP engine. */
4361 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4362 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
4363 S_370_WR_CONFIRM(1) |
4364 S_370_ENGINE_SEL(V_370_PFP));
4365 radeon_emit(cs, va);
4366 radeon_emit(cs, va >> 32);
4367 radeon_emit(cs, value);
4368 } else if (!(stageMask & ~post_index_fetch_flags)) {
4369 /* Sync ME because PFP reads index and indirect buffers. */
4370 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4371 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
4372 S_370_WR_CONFIRM(1) |
4373 S_370_ENGINE_SEL(V_370_ME));
4374 radeon_emit(cs, va);
4375 radeon_emit(cs, va >> 32);
4376 radeon_emit(cs, value);
4377 } else {
4378 /* Otherwise, sync all prior GPU work using an EOP event. */
4379 si_cs_emit_write_event_eop(cs,
4380 cmd_buffer->device->physical_device->rad_info.chip_class,
4381 radv_cmd_buffer_uses_mec(cmd_buffer),
4382 V_028A90_BOTTOM_OF_PIPE_TS, 0,
4383 EOP_DATA_SEL_VALUE_32BIT, va, 2, value,
4384 cmd_buffer->gfx9_eop_bug_va);
4385 }
4386
4387 assert(cmd_buffer->cs->cdw <= cdw_max);
4388 }
4389
4390 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4391 VkEvent _event,
4392 VkPipelineStageFlags stageMask)
4393 {
4394 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4395 RADV_FROM_HANDLE(radv_event, event, _event);
4396
4397 write_event(cmd_buffer, event, stageMask, 1);
4398 }
4399
4400 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4401 VkEvent _event,
4402 VkPipelineStageFlags stageMask)
4403 {
4404 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4405 RADV_FROM_HANDLE(radv_event, event, _event);
4406
4407 write_event(cmd_buffer, event, stageMask, 0);
4408 }
4409
4410 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4411 uint32_t eventCount,
4412 const VkEvent* pEvents,
4413 VkPipelineStageFlags srcStageMask,
4414 VkPipelineStageFlags dstStageMask,
4415 uint32_t memoryBarrierCount,
4416 const VkMemoryBarrier* pMemoryBarriers,
4417 uint32_t bufferMemoryBarrierCount,
4418 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4419 uint32_t imageMemoryBarrierCount,
4420 const VkImageMemoryBarrier* pImageMemoryBarriers)
4421 {
4422 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4423 struct radv_barrier_info info;
4424
4425 info.eventCount = eventCount;
4426 info.pEvents = pEvents;
4427 info.srcStageMask = 0;
4428
4429 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4430 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4431 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4432 }
4433
4434
4435 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4436 uint32_t deviceMask)
4437 {
4438 /* No-op */
4439 }
4440
4441 /* VK_EXT_conditional_rendering */
4442 void vkCmdBeginConditionalRenderingEXT(
4443 VkCommandBuffer commandBuffer,
4444 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
4445 {
4446 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4447 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
4448 bool inverted;
4449 uint64_t va;
4450
4451 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
4452
4453 inverted = pConditionalRenderingBegin->flags & VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT;
4454
4455 /* Enable predication for this command buffer. */
4456 si_emit_set_predication_state(cmd_buffer, inverted, va);
4457 cmd_buffer->state.predicating = true;
4458
4459 /* Store conditional rendering user info. */
4460 cmd_buffer->state.predication_type = inverted;
4461 cmd_buffer->state.predication_va = va;
4462 }
4463
4464 void vkCmdEndConditionalRenderingEXT(
4465 VkCommandBuffer commandBuffer)
4466 {
4467 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4468
4469 /* Disable predication for this command buffer. */
4470 si_emit_set_predication_state(cmd_buffer, false, 0);
4471 cmd_buffer->state.predicating = false;
4472
4473 /* Reset conditional rendering user info. */
4474 cmd_buffer->state.predication_type = -1;
4475 cmd_buffer->state.predication_va = 0;
4476 }