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radv: implement VK_KHR_descriptor_update_template
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_cs.h"
31 #include "sid.h"
32 #include "vk_format.h"
33 #include "radv_meta.h"
34
35 #include "ac_debug.h"
36
37 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
38 struct radv_image *image,
39 VkImageLayout src_layout,
40 VkImageLayout dst_layout,
41 uint32_t src_family,
42 uint32_t dst_family,
43 const VkImageSubresourceRange *range,
44 VkImageAspectFlags pending_clears);
45
46 const struct radv_dynamic_state default_dynamic_state = {
47 .viewport = {
48 .count = 0,
49 },
50 .scissor = {
51 .count = 0,
52 },
53 .line_width = 1.0f,
54 .depth_bias = {
55 .bias = 0.0f,
56 .clamp = 0.0f,
57 .slope = 0.0f,
58 },
59 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
60 .depth_bounds = {
61 .min = 0.0f,
62 .max = 1.0f,
63 },
64 .stencil_compare_mask = {
65 .front = ~0u,
66 .back = ~0u,
67 },
68 .stencil_write_mask = {
69 .front = ~0u,
70 .back = ~0u,
71 },
72 .stencil_reference = {
73 .front = 0u,
74 .back = 0u,
75 },
76 };
77
78 void
79 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
80 const struct radv_dynamic_state *src,
81 uint32_t copy_mask)
82 {
83 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
84 dest->viewport.count = src->viewport.count;
85 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
86 src->viewport.count);
87 }
88
89 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
90 dest->scissor.count = src->scissor.count;
91 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
92 src->scissor.count);
93 }
94
95 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
96 dest->line_width = src->line_width;
97
98 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
99 dest->depth_bias = src->depth_bias;
100
101 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
102 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
103
104 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
105 dest->depth_bounds = src->depth_bounds;
106
107 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
108 dest->stencil_compare_mask = src->stencil_compare_mask;
109
110 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
111 dest->stencil_write_mask = src->stencil_write_mask;
112
113 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
114 dest->stencil_reference = src->stencil_reference;
115 }
116
117 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
118 {
119 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
120 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
121 }
122
123 enum ring_type radv_queue_family_to_ring(int f) {
124 switch (f) {
125 case RADV_QUEUE_GENERAL:
126 return RING_GFX;
127 case RADV_QUEUE_COMPUTE:
128 return RING_COMPUTE;
129 case RADV_QUEUE_TRANSFER:
130 return RING_DMA;
131 default:
132 unreachable("Unknown queue family");
133 }
134 }
135
136 static VkResult radv_create_cmd_buffer(
137 struct radv_device * device,
138 struct radv_cmd_pool * pool,
139 VkCommandBufferLevel level,
140 VkCommandBuffer* pCommandBuffer)
141 {
142 struct radv_cmd_buffer *cmd_buffer;
143 VkResult result;
144 unsigned ring;
145 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
146 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
147 if (cmd_buffer == NULL)
148 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
149
150 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
151 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
152 cmd_buffer->device = device;
153 cmd_buffer->pool = pool;
154 cmd_buffer->level = level;
155
156 if (pool) {
157 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
158 cmd_buffer->queue_family_index = pool->queue_family_index;
159
160 } else {
161 /* Init the pool_link so we can safefly call list_del when we destroy
162 * the command buffer
163 */
164 list_inithead(&cmd_buffer->pool_link);
165 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
166 }
167
168 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
169
170 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
171 if (!cmd_buffer->cs) {
172 result = VK_ERROR_OUT_OF_HOST_MEMORY;
173 goto fail;
174 }
175
176 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
177
178 cmd_buffer->upload.offset = 0;
179 cmd_buffer->upload.size = 0;
180 list_inithead(&cmd_buffer->upload.list);
181
182 return VK_SUCCESS;
183
184 fail:
185 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
186
187 return result;
188 }
189
190 static void
191 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
192 {
193 list_del(&cmd_buffer->pool_link);
194
195 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
196 &cmd_buffer->upload.list, list) {
197 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
198 list_del(&up->list);
199 free(up);
200 }
201
202 if (cmd_buffer->upload.upload_bo)
203 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
204 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
205 free(cmd_buffer->push_descriptors.set.mapped_ptr);
206 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
207 }
208
209 static void radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
210 {
211
212 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
213
214 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
215 &cmd_buffer->upload.list, list) {
216 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
217 list_del(&up->list);
218 free(up);
219 }
220
221 cmd_buffer->scratch_size_needed = 0;
222 cmd_buffer->compute_scratch_size_needed = 0;
223 cmd_buffer->esgs_ring_size_needed = 0;
224 cmd_buffer->gsvs_ring_size_needed = 0;
225 cmd_buffer->tess_rings_needed = false;
226 cmd_buffer->sample_positions_needed = false;
227
228 if (cmd_buffer->upload.upload_bo)
229 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
230 cmd_buffer->upload.upload_bo, 8);
231 cmd_buffer->upload.offset = 0;
232
233 cmd_buffer->record_fail = false;
234
235 cmd_buffer->ring_offsets_idx = -1;
236 }
237
238 static bool
239 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
240 uint64_t min_needed)
241 {
242 uint64_t new_size;
243 struct radeon_winsys_bo *bo;
244 struct radv_cmd_buffer_upload *upload;
245 struct radv_device *device = cmd_buffer->device;
246
247 new_size = MAX2(min_needed, 16 * 1024);
248 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
249
250 bo = device->ws->buffer_create(device->ws,
251 new_size, 4096,
252 RADEON_DOMAIN_GTT,
253 RADEON_FLAG_CPU_ACCESS);
254
255 if (!bo) {
256 cmd_buffer->record_fail = true;
257 return false;
258 }
259
260 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
261 if (cmd_buffer->upload.upload_bo) {
262 upload = malloc(sizeof(*upload));
263
264 if (!upload) {
265 cmd_buffer->record_fail = true;
266 device->ws->buffer_destroy(bo);
267 return false;
268 }
269
270 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
271 list_add(&upload->list, &cmd_buffer->upload.list);
272 }
273
274 cmd_buffer->upload.upload_bo = bo;
275 cmd_buffer->upload.size = new_size;
276 cmd_buffer->upload.offset = 0;
277 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
278
279 if (!cmd_buffer->upload.map) {
280 cmd_buffer->record_fail = true;
281 return false;
282 }
283
284 return true;
285 }
286
287 bool
288 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
289 unsigned size,
290 unsigned alignment,
291 unsigned *out_offset,
292 void **ptr)
293 {
294 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
295 if (offset + size > cmd_buffer->upload.size) {
296 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
297 return false;
298 offset = 0;
299 }
300
301 *out_offset = offset;
302 *ptr = cmd_buffer->upload.map + offset;
303
304 cmd_buffer->upload.offset = offset + size;
305 return true;
306 }
307
308 bool
309 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
310 unsigned size, unsigned alignment,
311 const void *data, unsigned *out_offset)
312 {
313 uint8_t *ptr;
314
315 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
316 out_offset, (void **)&ptr))
317 return false;
318
319 if (ptr)
320 memcpy(ptr, data, size);
321
322 return true;
323 }
324
325 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
326 {
327 struct radv_device *device = cmd_buffer->device;
328 struct radeon_winsys_cs *cs = cmd_buffer->cs;
329 uint64_t va;
330
331 if (!device->trace_bo)
332 return;
333
334 va = device->ws->buffer_get_va(device->trace_bo);
335
336 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
337
338 ++cmd_buffer->state.trace_id;
339 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
340 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
341 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
342 S_370_WR_CONFIRM(1) |
343 S_370_ENGINE_SEL(V_370_ME));
344 radeon_emit(cs, va);
345 radeon_emit(cs, va >> 32);
346 radeon_emit(cs, cmd_buffer->state.trace_id);
347 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
348 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
349 }
350
351 static void
352 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
353 struct radv_pipeline *pipeline)
354 {
355 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
356 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
357 8);
358 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
359 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
360 }
361
362 static void
363 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
364 struct radv_pipeline *pipeline)
365 {
366 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
367 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
368 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
369
370 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
371 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
372 }
373
374 /* 12.4 fixed-point */
375 static unsigned radv_pack_float_12p4(float x)
376 {
377 return x <= 0 ? 0 :
378 x >= 4096 ? 0xffff : x * 16;
379 }
380
381 static uint32_t
382 shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs, bool has_tess)
383 {
384 switch (stage) {
385 case MESA_SHADER_FRAGMENT:
386 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
387 case MESA_SHADER_VERTEX:
388 if (has_tess)
389 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
390 else
391 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
392 case MESA_SHADER_GEOMETRY:
393 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
394 case MESA_SHADER_COMPUTE:
395 return R_00B900_COMPUTE_USER_DATA_0;
396 case MESA_SHADER_TESS_CTRL:
397 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
398 case MESA_SHADER_TESS_EVAL:
399 if (has_gs)
400 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
401 else
402 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
403 default:
404 unreachable("unknown shader");
405 }
406 }
407
408 static struct ac_userdata_info *
409 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
410 gl_shader_stage stage,
411 int idx)
412 {
413 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
414 }
415
416 static void
417 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
418 struct radv_pipeline *pipeline,
419 gl_shader_stage stage,
420 int idx, uint64_t va)
421 {
422 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
423 uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
424 if (loc->sgpr_idx == -1)
425 return;
426 assert(loc->num_sgprs == 2);
427 assert(!loc->indirect);
428 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
429 radeon_emit(cmd_buffer->cs, va);
430 radeon_emit(cmd_buffer->cs, va >> 32);
431 }
432
433 static void
434 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
435 struct radv_pipeline *pipeline)
436 {
437 int num_samples = pipeline->graphics.ms.num_samples;
438 struct radv_multisample_state *ms = &pipeline->graphics.ms;
439 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
440
441 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
442 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
443 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
444
445 radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa);
446 radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
447
448 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
449 return;
450
451 radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
452 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
453 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
454
455 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
456
457 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.uses_sample_positions) {
458 uint32_t offset;
459 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
460 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
461 if (loc->sgpr_idx == -1)
462 return;
463 assert(loc->num_sgprs == 1);
464 assert(!loc->indirect);
465 switch (num_samples) {
466 default:
467 offset = 0;
468 break;
469 case 2:
470 offset = 1;
471 break;
472 case 4:
473 offset = 3;
474 break;
475 case 8:
476 offset = 7;
477 break;
478 case 16:
479 offset = 15;
480 break;
481 }
482
483 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
484 cmd_buffer->sample_positions_needed = true;
485 }
486 }
487
488 static void
489 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
490 struct radv_pipeline *pipeline)
491 {
492 struct radv_raster_state *raster = &pipeline->graphics.raster;
493
494 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
495 raster->pa_cl_clip_cntl);
496
497 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
498 raster->spi_interp_control);
499
500 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A00_PA_SU_POINT_SIZE, 2);
501 unsigned tmp = (unsigned)(1.0 * 8.0);
502 radeon_emit(cmd_buffer->cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
503 radeon_emit(cmd_buffer->cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
504 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
505
506 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
507 raster->pa_su_vtx_cntl);
508
509 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
510 raster->pa_su_sc_mode_cntl);
511 }
512
513 static void
514 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
515 struct radv_pipeline *pipeline,
516 struct radv_shader_variant *shader,
517 struct ac_vs_output_info *outinfo)
518 {
519 struct radeon_winsys *ws = cmd_buffer->device->ws;
520 uint64_t va = ws->buffer_get_va(shader->bo);
521 unsigned export_count;
522
523 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
524
525 export_count = MAX2(1, outinfo->param_exports);
526 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
527 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
528
529 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
530 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
531 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
532 V_02870C_SPI_SHADER_4COMP :
533 V_02870C_SPI_SHADER_NONE) |
534 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
535 V_02870C_SPI_SHADER_4COMP :
536 V_02870C_SPI_SHADER_NONE) |
537 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
538 V_02870C_SPI_SHADER_4COMP :
539 V_02870C_SPI_SHADER_NONE));
540
541
542 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
543 radeon_emit(cmd_buffer->cs, va >> 8);
544 radeon_emit(cmd_buffer->cs, va >> 40);
545 radeon_emit(cmd_buffer->cs, shader->rsrc1);
546 radeon_emit(cmd_buffer->cs, shader->rsrc2);
547
548 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
549 S_028818_VTX_W0_FMT(1) |
550 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
551 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
552 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
553
554
555 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
556 pipeline->graphics.pa_cl_vs_out_cntl);
557
558 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
559 S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
560 }
561
562 static void
563 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
564 struct radv_shader_variant *shader,
565 struct ac_es_output_info *outinfo)
566 {
567 struct radeon_winsys *ws = cmd_buffer->device->ws;
568 uint64_t va = ws->buffer_get_va(shader->bo);
569
570 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
571
572 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
573 outinfo->esgs_itemsize / 4);
574 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
575 radeon_emit(cmd_buffer->cs, va >> 8);
576 radeon_emit(cmd_buffer->cs, va >> 40);
577 radeon_emit(cmd_buffer->cs, shader->rsrc1);
578 radeon_emit(cmd_buffer->cs, shader->rsrc2);
579 }
580
581 static void
582 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
583 struct radv_shader_variant *shader)
584 {
585 struct radeon_winsys *ws = cmd_buffer->device->ws;
586 uint64_t va = ws->buffer_get_va(shader->bo);
587 uint32_t rsrc2 = shader->rsrc2;
588
589 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
590
591 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
592 radeon_emit(cmd_buffer->cs, va >> 8);
593 radeon_emit(cmd_buffer->cs, va >> 40);
594
595 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
596 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
597 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
598 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
599
600 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
601 radeon_emit(cmd_buffer->cs, shader->rsrc1);
602 radeon_emit(cmd_buffer->cs, rsrc2);
603 }
604
605 static void
606 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
607 struct radv_shader_variant *shader)
608 {
609 struct radeon_winsys *ws = cmd_buffer->device->ws;
610 uint64_t va = ws->buffer_get_va(shader->bo);
611
612 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
613
614 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
615 radeon_emit(cmd_buffer->cs, va >> 8);
616 radeon_emit(cmd_buffer->cs, va >> 40);
617 radeon_emit(cmd_buffer->cs, shader->rsrc1);
618 radeon_emit(cmd_buffer->cs, shader->rsrc2);
619 }
620
621 static void
622 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
623 struct radv_pipeline *pipeline)
624 {
625 struct radv_shader_variant *vs;
626
627 assert (pipeline->shaders[MESA_SHADER_VERTEX]);
628
629 vs = pipeline->shaders[MESA_SHADER_VERTEX];
630
631 if (vs->info.vs.as_ls)
632 radv_emit_hw_ls(cmd_buffer, vs);
633 else if (vs->info.vs.as_es)
634 radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info);
635 else
636 radv_emit_hw_vs(cmd_buffer, pipeline, vs, &vs->info.vs.outinfo);
637
638 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, 0);
639 }
640
641
642 static void
643 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
644 struct radv_pipeline *pipeline)
645 {
646 if (!radv_pipeline_has_tess(pipeline))
647 return;
648
649 struct radv_shader_variant *tes, *tcs;
650
651 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
652 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
653
654 if (tes->info.tes.as_es)
655 radv_emit_hw_es(cmd_buffer, tes, &tes->info.tes.es_info);
656 else
657 radv_emit_hw_vs(cmd_buffer, pipeline, tes, &tes->info.tes.outinfo);
658
659 radv_emit_hw_hs(cmd_buffer, tcs);
660
661 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
662 pipeline->graphics.tess.tf_param);
663
664 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
665 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
666 pipeline->graphics.tess.ls_hs_config);
667 else
668 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
669 pipeline->graphics.tess.ls_hs_config);
670
671 struct ac_userdata_info *loc;
672
673 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
674 if (loc->sgpr_idx != -1) {
675 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
676 assert(loc->num_sgprs == 4);
677 assert(!loc->indirect);
678 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
679 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
680 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
681 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
682 pipeline->graphics.tess.num_tcs_input_cp << 26);
683 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
684 }
685
686 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
687 if (loc->sgpr_idx != -1) {
688 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
689 assert(loc->num_sgprs == 1);
690 assert(!loc->indirect);
691
692 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
693 pipeline->graphics.tess.offchip_layout);
694 }
695
696 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
697 if (loc->sgpr_idx != -1) {
698 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
699 assert(loc->num_sgprs == 1);
700 assert(!loc->indirect);
701
702 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
703 pipeline->graphics.tess.tcs_in_layout);
704 }
705 }
706
707 static void
708 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
709 struct radv_pipeline *pipeline)
710 {
711 struct radeon_winsys *ws = cmd_buffer->device->ws;
712 struct radv_shader_variant *gs;
713 uint64_t va;
714
715 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
716
717 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
718 if (!gs)
719 return;
720
721 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
722
723 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
724 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
725 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
726 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
727
728 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
729
730 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
731
732 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
733 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
734 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
735 radeon_emit(cmd_buffer->cs, 0);
736 radeon_emit(cmd_buffer->cs, 0);
737 radeon_emit(cmd_buffer->cs, 0);
738
739 uint32_t gs_num_invocations = gs->info.gs.invocations;
740 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
741 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
742 S_028B90_ENABLE(gs_num_invocations > 0));
743
744 va = ws->buffer_get_va(gs->bo);
745 ws->cs_add_buffer(cmd_buffer->cs, gs->bo, 8);
746 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
747 radeon_emit(cmd_buffer->cs, va >> 8);
748 radeon_emit(cmd_buffer->cs, va >> 40);
749 radeon_emit(cmd_buffer->cs, gs->rsrc1);
750 radeon_emit(cmd_buffer->cs, gs->rsrc2);
751
752 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader, &pipeline->gs_copy_shader->info.vs.outinfo);
753
754 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
755 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
756 if (loc->sgpr_idx != -1) {
757 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
758 uint32_t num_entries = 64;
759 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
760
761 if (is_vi)
762 num_entries *= stride;
763
764 stride = S_008F04_STRIDE(stride);
765 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
766 radeon_emit(cmd_buffer->cs, stride);
767 radeon_emit(cmd_buffer->cs, num_entries);
768 }
769 }
770
771 static void
772 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
773 struct radv_pipeline *pipeline)
774 {
775 struct radeon_winsys *ws = cmd_buffer->device->ws;
776 struct radv_shader_variant *ps;
777 uint64_t va;
778 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
779 struct radv_blend_state *blend = &pipeline->graphics.blend;
780 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
781
782 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
783
784 va = ws->buffer_get_va(ps->bo);
785 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
786
787 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
788 radeon_emit(cmd_buffer->cs, va >> 8);
789 radeon_emit(cmd_buffer->cs, va >> 40);
790 radeon_emit(cmd_buffer->cs, ps->rsrc1);
791 radeon_emit(cmd_buffer->cs, ps->rsrc2);
792
793 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
794 pipeline->graphics.db_shader_control);
795
796 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
797 ps->config.spi_ps_input_ena);
798
799 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
800 ps->config.spi_ps_input_addr);
801
802 if (ps->info.fs.force_persample)
803 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
804
805 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
806 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
807
808 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
809
810 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
811 pipeline->graphics.shader_z_format);
812
813 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
814
815 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
816 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
817
818 if (pipeline->graphics.ps_input_cntl_num) {
819 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
820 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
821 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
822 }
823 }
824 }
825
826 static void polaris_set_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
827 struct radv_pipeline *pipeline)
828 {
829 uint32_t vtx_reuse_depth = 30;
830 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
831 return;
832
833 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
834 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD)
835 vtx_reuse_depth = 14;
836 }
837 radeon_set_context_reg(cmd_buffer->cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
838 vtx_reuse_depth);
839 }
840
841 static void
842 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer,
843 struct radv_pipeline *pipeline)
844 {
845 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
846 return;
847
848 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
849 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
850 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
851 radv_update_multisample_state(cmd_buffer, pipeline);
852 radv_emit_vertex_shader(cmd_buffer, pipeline);
853 radv_emit_tess_shaders(cmd_buffer, pipeline);
854 radv_emit_geometry_shader(cmd_buffer, pipeline);
855 radv_emit_fragment_shader(cmd_buffer, pipeline);
856 polaris_set_vgt_vertex_reuse(cmd_buffer, pipeline);
857
858 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
859 pipeline->graphics.prim_restart_enable);
860
861 cmd_buffer->scratch_size_needed =
862 MAX2(cmd_buffer->scratch_size_needed,
863 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
864
865 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
866 S_0286E8_WAVES(pipeline->max_waves) |
867 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
868
869 if (!cmd_buffer->state.emitted_pipeline ||
870 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
871 pipeline->graphics.can_use_guardband)
872 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
873 cmd_buffer->state.emitted_pipeline = pipeline;
874 }
875
876 static void
877 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
878 {
879 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
880 cmd_buffer->state.dynamic.viewport.viewports);
881 }
882
883 static void
884 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
885 {
886 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
887 si_write_scissors(cmd_buffer->cs, 0, count,
888 cmd_buffer->state.dynamic.scissor.scissors,
889 cmd_buffer->state.dynamic.viewport.viewports,
890 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
891 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
892 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
893 }
894
895 static void
896 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
897 int index,
898 struct radv_color_buffer_info *cb)
899 {
900 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
901 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
902 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
903 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
904 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
905 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
906 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
907 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
908 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
909 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
910 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
911 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
912 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
913
914 if (is_vi) { /* DCC BASE */
915 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
916 }
917 }
918
919 static void
920 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
921 struct radv_ds_buffer_info *ds,
922 struct radv_image *image,
923 VkImageLayout layout)
924 {
925 uint32_t db_z_info = ds->db_z_info;
926
927 if (!radv_layout_has_htile(image, layout))
928 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
929
930 if (!radv_layout_can_expclear(image, layout))
931 db_z_info &= C_028040_ALLOW_EXPCLEAR & C_028044_ALLOW_EXPCLEAR;
932
933 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
934 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
935
936 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
937 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
938 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
939 radeon_emit(cmd_buffer->cs, ds->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
940 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
941 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
942 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
943 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
944 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
945 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
946
947 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
948 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
949 ds->pa_su_poly_offset_db_fmt_cntl);
950 }
951
952 /*
953 * To hw resolve multisample images both src and dst need to have the same
954 * micro tiling mode. However we don't always know in advance when creating
955 * the images. This function gets called if we have a resolve attachment,
956 * and tests if the attachment image has the same tiling mode, then it
957 * checks if the generated framebuffer data has the same tiling mode, and
958 * updates it if not.
959 */
960 static void radv_set_optimal_micro_tile_mode(struct radv_device *device,
961 struct radv_attachment_info *att,
962 uint32_t micro_tile_mode)
963 {
964 struct radv_image *image = att->attachment->image;
965 uint32_t tile_mode_index;
966 if (image->surface.nsamples <= 1)
967 return;
968
969 if (image->surface.micro_tile_mode != micro_tile_mode) {
970 radv_image_set_optimal_micro_tile_mode(device, image, micro_tile_mode);
971 }
972
973 if (att->cb.micro_tile_mode != micro_tile_mode) {
974 tile_mode_index = image->surface.tiling_index[0];
975
976 att->cb.cb_color_attrib &= C_028C74_TILE_MODE_INDEX;
977 att->cb.cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
978 att->cb.micro_tile_mode = micro_tile_mode;
979 }
980 }
981
982 void
983 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
984 struct radv_image *image,
985 VkClearDepthStencilValue ds_clear_value,
986 VkImageAspectFlags aspects)
987 {
988 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
989 va += image->offset + image->clear_value_offset;
990 unsigned reg_offset = 0, reg_count = 0;
991
992 if (!image->surface.htile_size || !aspects)
993 return;
994
995 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
996 ++reg_count;
997 } else {
998 ++reg_offset;
999 va += 4;
1000 }
1001 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1002 ++reg_count;
1003
1004 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1005
1006 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1007 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1008 S_370_WR_CONFIRM(1) |
1009 S_370_ENGINE_SEL(V_370_PFP));
1010 radeon_emit(cmd_buffer->cs, va);
1011 radeon_emit(cmd_buffer->cs, va >> 32);
1012 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1013 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1014 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1015 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1016
1017 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1018 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1019 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1020 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1021 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1022 }
1023
1024 static void
1025 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1026 struct radv_image *image)
1027 {
1028 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1029 va += image->offset + image->clear_value_offset;
1030
1031 if (!image->surface.htile_size)
1032 return;
1033
1034 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1035
1036 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1037 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1038 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1039 COPY_DATA_COUNT_SEL);
1040 radeon_emit(cmd_buffer->cs, va);
1041 radeon_emit(cmd_buffer->cs, va >> 32);
1042 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
1043 radeon_emit(cmd_buffer->cs, 0);
1044
1045 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1046 radeon_emit(cmd_buffer->cs, 0);
1047 }
1048
1049 void
1050 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1051 struct radv_image *image,
1052 int idx,
1053 uint32_t color_values[2])
1054 {
1055 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1056 va += image->offset + image->clear_value_offset;
1057
1058 if (!image->cmask.size && !image->surface.dcc_size)
1059 return;
1060
1061 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1062
1063 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1064 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1065 S_370_WR_CONFIRM(1) |
1066 S_370_ENGINE_SEL(V_370_PFP));
1067 radeon_emit(cmd_buffer->cs, va);
1068 radeon_emit(cmd_buffer->cs, va >> 32);
1069 radeon_emit(cmd_buffer->cs, color_values[0]);
1070 radeon_emit(cmd_buffer->cs, color_values[1]);
1071
1072 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1073 radeon_emit(cmd_buffer->cs, color_values[0]);
1074 radeon_emit(cmd_buffer->cs, color_values[1]);
1075 }
1076
1077 static void
1078 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1079 struct radv_image *image,
1080 int idx)
1081 {
1082 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1083 va += image->offset + image->clear_value_offset;
1084
1085 if (!image->cmask.size && !image->surface.dcc_size)
1086 return;
1087
1088 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1089 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1090
1091 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1092 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1093 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1094 COPY_DATA_COUNT_SEL);
1095 radeon_emit(cmd_buffer->cs, va);
1096 radeon_emit(cmd_buffer->cs, va >> 32);
1097 radeon_emit(cmd_buffer->cs, reg >> 2);
1098 radeon_emit(cmd_buffer->cs, 0);
1099
1100 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1101 radeon_emit(cmd_buffer->cs, 0);
1102 }
1103
1104 void
1105 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1106 {
1107 int i;
1108 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1109 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1110 int dst_resolve_micro_tile_mode = -1;
1111
1112 if (subpass->has_resolve) {
1113 uint32_t a = subpass->resolve_attachments[0].attachment;
1114 const struct radv_image *image = framebuffer->attachments[a].attachment->image;
1115 dst_resolve_micro_tile_mode = image->surface.micro_tile_mode;
1116 }
1117 for (i = 0; i < subpass->color_count; ++i) {
1118 int idx = subpass->color_attachments[i].attachment;
1119 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1120
1121 if (dst_resolve_micro_tile_mode != -1) {
1122 radv_set_optimal_micro_tile_mode(cmd_buffer->device,
1123 att, dst_resolve_micro_tile_mode);
1124 }
1125 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1126
1127 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1128 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1129
1130 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1131 }
1132
1133 for (i = subpass->color_count; i < 8; i++)
1134 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1135 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1136
1137 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1138 int idx = subpass->depth_stencil_attachment.attachment;
1139 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1140 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1141 struct radv_image *image = att->attachment->image;
1142 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1143
1144 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1145
1146 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1147 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1148 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1149 }
1150 radv_load_depth_clear_regs(cmd_buffer, image);
1151 } else {
1152 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1153 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1154 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1155 }
1156 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1157 S_028208_BR_X(framebuffer->width) |
1158 S_028208_BR_Y(framebuffer->height));
1159 }
1160
1161 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1162 {
1163 uint32_t db_count_control;
1164
1165 if(!cmd_buffer->state.active_occlusion_queries) {
1166 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1167 db_count_control = 0;
1168 } else {
1169 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1170 }
1171 } else {
1172 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1173 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1174 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1175 S_028004_ZPASS_ENABLE(1) |
1176 S_028004_SLICE_EVEN_ENABLE(1) |
1177 S_028004_SLICE_ODD_ENABLE(1);
1178 } else {
1179 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1180 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1181 }
1182 }
1183
1184 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1185 }
1186
1187 static void
1188 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1189 {
1190 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1191
1192 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH) {
1193 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1194 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1195 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1196 }
1197
1198 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
1199 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1200 radeon_emit_array(cmd_buffer->cs, (uint32_t*)d->blend_constants, 4);
1201 }
1202
1203 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1204 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1205 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK)) {
1206 radeon_set_context_reg_seq(cmd_buffer->cs, R_028430_DB_STENCILREFMASK, 2);
1207 radeon_emit(cmd_buffer->cs, S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1208 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1209 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1210 S_028430_STENCILOPVAL(1));
1211 radeon_emit(cmd_buffer->cs, S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1212 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1213 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1214 S_028434_STENCILOPVAL_BF(1));
1215 }
1216
1217 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1218 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) {
1219 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, fui(d->depth_bounds.min));
1220 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX, fui(d->depth_bounds.max));
1221 }
1222
1223 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1224 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
1225 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1226 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1227 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1228
1229 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1230 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1231 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1232 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1233 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1234 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1235 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1236 }
1237 }
1238
1239 cmd_buffer->state.dirty = 0;
1240 }
1241
1242 static void
1243 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1244 struct radv_pipeline *pipeline,
1245 int idx,
1246 uint64_t va,
1247 gl_shader_stage stage)
1248 {
1249 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1250 uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
1251
1252 if (desc_set_loc->sgpr_idx == -1)
1253 return;
1254
1255 assert(!desc_set_loc->indirect);
1256 assert(desc_set_loc->num_sgprs == 2);
1257 radeon_set_sh_reg_seq(cmd_buffer->cs,
1258 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1259 radeon_emit(cmd_buffer->cs, va);
1260 radeon_emit(cmd_buffer->cs, va >> 32);
1261 }
1262
1263 static void
1264 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1265 struct radv_pipeline *pipeline,
1266 VkShaderStageFlags stages,
1267 struct radv_descriptor_set *set,
1268 unsigned idx)
1269 {
1270 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1271 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1272 idx, set->va,
1273 MESA_SHADER_FRAGMENT);
1274
1275 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1276 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1277 idx, set->va,
1278 MESA_SHADER_VERTEX);
1279
1280 if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(pipeline))
1281 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1282 idx, set->va,
1283 MESA_SHADER_GEOMETRY);
1284
1285 if ((stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT) && radv_pipeline_has_tess(pipeline))
1286 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1287 idx, set->va,
1288 MESA_SHADER_TESS_CTRL);
1289
1290 if ((stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) && radv_pipeline_has_tess(pipeline))
1291 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1292 idx, set->va,
1293 MESA_SHADER_TESS_EVAL);
1294
1295 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1296 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1297 idx, set->va,
1298 MESA_SHADER_COMPUTE);
1299 }
1300
1301 static void
1302 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1303 {
1304 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1305 uint32_t *ptr = NULL;
1306 unsigned bo_offset;
1307
1308 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, set->size, 32,
1309 &bo_offset,
1310 (void**) &ptr))
1311 return;
1312
1313 set->va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1314 set->va += bo_offset;
1315
1316 memcpy(ptr, set->mapped_ptr, set->size);
1317 }
1318
1319 static void
1320 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1321 struct radv_pipeline *pipeline,
1322 VkShaderStageFlags stages)
1323 {
1324 unsigned i;
1325 if (!cmd_buffer->state.descriptors_dirty)
1326 return;
1327
1328 if (cmd_buffer->state.push_descriptors_dirty)
1329 radv_flush_push_descriptors(cmd_buffer);
1330
1331 for (i = 0; i < MAX_SETS; i++) {
1332 if (!(cmd_buffer->state.descriptors_dirty & (1 << i)))
1333 continue;
1334 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1335 if (!set)
1336 continue;
1337
1338 radv_emit_descriptor_set_userdata(cmd_buffer, pipeline, stages, set, i);
1339 }
1340 cmd_buffer->state.descriptors_dirty = 0;
1341 cmd_buffer->state.push_descriptors_dirty = false;
1342 }
1343
1344 static void
1345 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1346 struct radv_pipeline *pipeline,
1347 VkShaderStageFlags stages)
1348 {
1349 struct radv_pipeline_layout *layout = pipeline->layout;
1350 unsigned offset;
1351 void *ptr;
1352 uint64_t va;
1353
1354 stages &= cmd_buffer->push_constant_stages;
1355 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1356 return;
1357
1358 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1359 16 * layout->dynamic_offset_count,
1360 256, &offset, &ptr))
1361 return;
1362
1363 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1364 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1365 16 * layout->dynamic_offset_count);
1366
1367 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1368 va += offset;
1369
1370 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1371 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1372 AC_UD_PUSH_CONSTANTS, va);
1373
1374 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1375 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
1376 AC_UD_PUSH_CONSTANTS, va);
1377
1378 if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(pipeline))
1379 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_GEOMETRY,
1380 AC_UD_PUSH_CONSTANTS, va);
1381
1382 if ((stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT) && radv_pipeline_has_tess(pipeline))
1383 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_TESS_CTRL,
1384 AC_UD_PUSH_CONSTANTS, va);
1385
1386 if ((stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) && radv_pipeline_has_tess(pipeline))
1387 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_TESS_EVAL,
1388 AC_UD_PUSH_CONSTANTS, va);
1389
1390 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1391 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_COMPUTE,
1392 AC_UD_PUSH_CONSTANTS, va);
1393
1394 cmd_buffer->push_constant_stages &= ~stages;
1395 }
1396
1397 static void
1398 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer,
1399 bool instanced_draw, bool indirect_draw,
1400 uint32_t draw_vertex_count)
1401 {
1402 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1403 struct radv_device *device = cmd_buffer->device;
1404 uint32_t ia_multi_vgt_param;
1405
1406 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1407 cmd_buffer->cs, 4096);
1408
1409 if ((cmd_buffer->state.vertex_descriptors_dirty || cmd_buffer->state.vb_dirty) &&
1410 cmd_buffer->state.pipeline->num_vertex_attribs) {
1411 unsigned vb_offset;
1412 void *vb_ptr;
1413 uint32_t i = 0;
1414 uint32_t num_attribs = cmd_buffer->state.pipeline->num_vertex_attribs;
1415 uint64_t va;
1416
1417 /* allocate some descriptor state for vertex buffers */
1418 radv_cmd_buffer_upload_alloc(cmd_buffer, num_attribs * 16, 256,
1419 &vb_offset, &vb_ptr);
1420
1421 for (i = 0; i < num_attribs; i++) {
1422 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1423 uint32_t offset;
1424 int vb = cmd_buffer->state.pipeline->va_binding[i];
1425 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1426 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1427
1428 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1429 va = device->ws->buffer_get_va(buffer->bo);
1430
1431 offset = cmd_buffer->state.vertex_bindings[vb].offset + cmd_buffer->state.pipeline->va_offset[i];
1432 va += offset + buffer->offset;
1433 desc[0] = va;
1434 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1435 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1436 desc[2] = (buffer->size - offset - cmd_buffer->state.pipeline->va_format_size[i]) / stride + 1;
1437 else
1438 desc[2] = buffer->size - offset;
1439 desc[3] = cmd_buffer->state.pipeline->va_rsrc_word3[i];
1440 }
1441
1442 va = device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1443 va += vb_offset;
1444
1445 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1446 AC_UD_VS_VERTEX_BUFFERS, va);
1447 }
1448
1449 cmd_buffer->state.vertex_descriptors_dirty = false;
1450 cmd_buffer->state.vb_dirty = 0;
1451 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1452 radv_emit_graphics_pipeline(cmd_buffer, pipeline);
1453
1454 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1455 radv_emit_framebuffer_state(cmd_buffer);
1456
1457 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1458 radv_emit_viewport(cmd_buffer);
1459
1460 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1461 radv_emit_scissor(cmd_buffer);
1462
1463 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, draw_vertex_count);
1464 if (cmd_buffer->state.last_ia_multi_vgt_param != ia_multi_vgt_param) {
1465 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
1466 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1467 else
1468 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1469 cmd_buffer->state.last_ia_multi_vgt_param = ia_multi_vgt_param;
1470 }
1471
1472 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) {
1473 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
1474
1475 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1476 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, cmd_buffer->state.pipeline->graphics.prim);
1477 } else {
1478 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, cmd_buffer->state.pipeline->graphics.prim);
1479 }
1480 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, cmd_buffer->state.pipeline->graphics.gs_out);
1481 }
1482
1483 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1484
1485 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.pipeline,
1486 VK_SHADER_STAGE_ALL_GRAPHICS);
1487 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1488 VK_SHADER_STAGE_ALL_GRAPHICS);
1489
1490 assert(cmd_buffer->cs->cdw <= cdw_max);
1491
1492 si_emit_cache_flush(cmd_buffer);
1493 }
1494
1495 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1496 VkPipelineStageFlags src_stage_mask)
1497 {
1498 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1499 VK_PIPELINE_STAGE_TRANSFER_BIT |
1500 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1501 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1502 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1503 }
1504
1505 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1506 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1507 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1508 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1509 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1510 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1511 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1512 VK_PIPELINE_STAGE_TRANSFER_BIT |
1513 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1514 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1515 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1516 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1517 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1518 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1519 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1520 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1521 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1522 }
1523 }
1524
1525 static enum radv_cmd_flush_bits
1526 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1527 VkAccessFlags src_flags)
1528 {
1529 enum radv_cmd_flush_bits flush_bits = 0;
1530 uint32_t b;
1531 for_each_bit(b, src_flags) {
1532 switch ((VkAccessFlagBits)(1 << b)) {
1533 case VK_ACCESS_SHADER_WRITE_BIT:
1534 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1535 break;
1536 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1537 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1538 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1539 break;
1540 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1541 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1542 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1543 break;
1544 case VK_ACCESS_TRANSFER_WRITE_BIT:
1545 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1546 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1547 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1548 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1549 RADV_CMD_FLAG_INV_GLOBAL_L2;
1550 break;
1551 default:
1552 break;
1553 }
1554 }
1555 return flush_bits;
1556 }
1557
1558 static enum radv_cmd_flush_bits
1559 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1560 VkAccessFlags dst_flags,
1561 struct radv_image *image)
1562 {
1563 enum radv_cmd_flush_bits flush_bits = 0;
1564 uint32_t b;
1565 for_each_bit(b, dst_flags) {
1566 switch ((VkAccessFlagBits)(1 << b)) {
1567 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1568 case VK_ACCESS_INDEX_READ_BIT:
1569 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1570 break;
1571 case VK_ACCESS_UNIFORM_READ_BIT:
1572 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1573 break;
1574 case VK_ACCESS_SHADER_READ_BIT:
1575 case VK_ACCESS_TRANSFER_READ_BIT:
1576 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1577 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1578 RADV_CMD_FLAG_INV_GLOBAL_L2;
1579 break;
1580 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1581 /* TODO: change to image && when the image gets passed
1582 * through from the subpass. */
1583 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1584 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1585 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1586 break;
1587 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1588 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1589 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1590 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1591 break;
1592 default:
1593 break;
1594 }
1595 }
1596 return flush_bits;
1597 }
1598
1599 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1600 {
1601 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1602 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1603 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1604 NULL);
1605 }
1606
1607 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1608 VkAttachmentReference att)
1609 {
1610 unsigned idx = att.attachment;
1611 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1612 VkImageSubresourceRange range;
1613 range.aspectMask = 0;
1614 range.baseMipLevel = view->base_mip;
1615 range.levelCount = 1;
1616 range.baseArrayLayer = view->base_layer;
1617 range.layerCount = cmd_buffer->state.framebuffer->layers;
1618
1619 radv_handle_image_transition(cmd_buffer,
1620 view->image,
1621 cmd_buffer->state.attachments[idx].current_layout,
1622 att.layout, 0, 0, &range,
1623 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1624
1625 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1626
1627
1628 }
1629
1630 void
1631 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1632 const struct radv_subpass *subpass, bool transitions)
1633 {
1634 if (transitions) {
1635 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1636
1637 for (unsigned i = 0; i < subpass->color_count; ++i) {
1638 radv_handle_subpass_image_transition(cmd_buffer,
1639 subpass->color_attachments[i]);
1640 }
1641
1642 for (unsigned i = 0; i < subpass->input_count; ++i) {
1643 radv_handle_subpass_image_transition(cmd_buffer,
1644 subpass->input_attachments[i]);
1645 }
1646
1647 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1648 radv_handle_subpass_image_transition(cmd_buffer,
1649 subpass->depth_stencil_attachment);
1650 }
1651 }
1652
1653 cmd_buffer->state.subpass = subpass;
1654
1655 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1656 }
1657
1658 static void
1659 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1660 struct radv_render_pass *pass,
1661 const VkRenderPassBeginInfo *info)
1662 {
1663 struct radv_cmd_state *state = &cmd_buffer->state;
1664
1665 if (pass->attachment_count == 0) {
1666 state->attachments = NULL;
1667 return;
1668 }
1669
1670 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1671 pass->attachment_count *
1672 sizeof(state->attachments[0]),
1673 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1674 if (state->attachments == NULL) {
1675 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1676 abort();
1677 }
1678
1679 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1680 struct radv_render_pass_attachment *att = &pass->attachments[i];
1681 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1682 VkImageAspectFlags clear_aspects = 0;
1683
1684 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1685 /* color attachment */
1686 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1687 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1688 }
1689 } else {
1690 /* depthstencil attachment */
1691 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1692 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1693 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1694 }
1695 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1696 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1697 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1698 }
1699 }
1700
1701 state->attachments[i].pending_clear_aspects = clear_aspects;
1702 if (clear_aspects && info) {
1703 assert(info->clearValueCount > i);
1704 state->attachments[i].clear_value = info->pClearValues[i];
1705 }
1706
1707 state->attachments[i].current_layout = att->initial_layout;
1708 }
1709 }
1710
1711 VkResult radv_AllocateCommandBuffers(
1712 VkDevice _device,
1713 const VkCommandBufferAllocateInfo *pAllocateInfo,
1714 VkCommandBuffer *pCommandBuffers)
1715 {
1716 RADV_FROM_HANDLE(radv_device, device, _device);
1717 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1718
1719 VkResult result = VK_SUCCESS;
1720 uint32_t i;
1721
1722 memset(pCommandBuffers, 0,
1723 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
1724
1725 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1726
1727 if (!list_empty(&pool->free_cmd_buffers)) {
1728 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1729
1730 list_del(&cmd_buffer->pool_link);
1731 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1732
1733 radv_reset_cmd_buffer(cmd_buffer);
1734 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1735 cmd_buffer->level = pAllocateInfo->level;
1736
1737 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
1738 result = VK_SUCCESS;
1739 } else {
1740 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1741 &pCommandBuffers[i]);
1742 }
1743 if (result != VK_SUCCESS)
1744 break;
1745 }
1746
1747 if (result != VK_SUCCESS)
1748 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1749 i, pCommandBuffers);
1750
1751 return result;
1752 }
1753
1754 void radv_FreeCommandBuffers(
1755 VkDevice device,
1756 VkCommandPool commandPool,
1757 uint32_t commandBufferCount,
1758 const VkCommandBuffer *pCommandBuffers)
1759 {
1760 for (uint32_t i = 0; i < commandBufferCount; i++) {
1761 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1762
1763 if (cmd_buffer) {
1764 if (cmd_buffer->pool) {
1765 list_del(&cmd_buffer->pool_link);
1766 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
1767 } else
1768 radv_cmd_buffer_destroy(cmd_buffer);
1769
1770 }
1771 }
1772 }
1773
1774 VkResult radv_ResetCommandBuffer(
1775 VkCommandBuffer commandBuffer,
1776 VkCommandBufferResetFlags flags)
1777 {
1778 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1779 radv_reset_cmd_buffer(cmd_buffer);
1780 return VK_SUCCESS;
1781 }
1782
1783 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
1784 {
1785 struct radv_device *device = cmd_buffer->device;
1786 if (device->gfx_init) {
1787 uint64_t va = device->ws->buffer_get_va(device->gfx_init);
1788 device->ws->cs_add_buffer(cmd_buffer->cs, device->gfx_init, 8);
1789 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
1790 radeon_emit(cmd_buffer->cs, va);
1791 radeon_emit(cmd_buffer->cs, (va >> 32) & 0xffff);
1792 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
1793 } else
1794 si_init_config(cmd_buffer);
1795 }
1796
1797 VkResult radv_BeginCommandBuffer(
1798 VkCommandBuffer commandBuffer,
1799 const VkCommandBufferBeginInfo *pBeginInfo)
1800 {
1801 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1802 radv_reset_cmd_buffer(cmd_buffer);
1803
1804 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1805
1806 /* setup initial configuration into command buffer */
1807 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1808 switch (cmd_buffer->queue_family_index) {
1809 case RADV_QUEUE_GENERAL:
1810 emit_gfx_buffer_state(cmd_buffer);
1811 radv_set_db_count_control(cmd_buffer);
1812 break;
1813 case RADV_QUEUE_COMPUTE:
1814 si_init_compute(cmd_buffer);
1815 break;
1816 case RADV_QUEUE_TRANSFER:
1817 default:
1818 break;
1819 }
1820 }
1821
1822 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1823 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1824 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1825
1826 struct radv_subpass *subpass =
1827 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1828
1829 radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1830 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
1831 }
1832
1833 return VK_SUCCESS;
1834 }
1835
1836 void radv_CmdBindVertexBuffers(
1837 VkCommandBuffer commandBuffer,
1838 uint32_t firstBinding,
1839 uint32_t bindingCount,
1840 const VkBuffer* pBuffers,
1841 const VkDeviceSize* pOffsets)
1842 {
1843 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1844 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
1845
1846 /* We have to defer setting up vertex buffer since we need the buffer
1847 * stride from the pipeline. */
1848
1849 assert(firstBinding + bindingCount < MAX_VBS);
1850 for (uint32_t i = 0; i < bindingCount; i++) {
1851 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
1852 vb[firstBinding + i].offset = pOffsets[i];
1853 cmd_buffer->state.vb_dirty |= 1 << (firstBinding + i);
1854 }
1855 }
1856
1857 void radv_CmdBindIndexBuffer(
1858 VkCommandBuffer commandBuffer,
1859 VkBuffer buffer,
1860 VkDeviceSize offset,
1861 VkIndexType indexType)
1862 {
1863 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1864
1865 cmd_buffer->state.index_buffer = radv_buffer_from_handle(buffer);
1866 cmd_buffer->state.index_offset = offset;
1867 cmd_buffer->state.index_type = indexType; /* vk matches hw */
1868 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
1869 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, cmd_buffer->state.index_buffer->bo, 8);
1870 }
1871
1872
1873 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1874 struct radv_descriptor_set *set,
1875 unsigned idx)
1876 {
1877 struct radeon_winsys *ws = cmd_buffer->device->ws;
1878
1879 cmd_buffer->state.descriptors[idx] = set;
1880 cmd_buffer->state.descriptors_dirty |= (1 << idx);
1881 if (!set)
1882 return;
1883
1884 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
1885 if (set->descriptors[j])
1886 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
1887
1888 if(set->bo)
1889 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
1890 }
1891
1892 void radv_CmdBindDescriptorSets(
1893 VkCommandBuffer commandBuffer,
1894 VkPipelineBindPoint pipelineBindPoint,
1895 VkPipelineLayout _layout,
1896 uint32_t firstSet,
1897 uint32_t descriptorSetCount,
1898 const VkDescriptorSet* pDescriptorSets,
1899 uint32_t dynamicOffsetCount,
1900 const uint32_t* pDynamicOffsets)
1901 {
1902 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1903 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
1904 unsigned dyn_idx = 0;
1905
1906 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1907 cmd_buffer->cs, MAX_SETS * 4 * 6);
1908
1909 for (unsigned i = 0; i < descriptorSetCount; ++i) {
1910 unsigned idx = i + firstSet;
1911 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
1912 radv_bind_descriptor_set(cmd_buffer, set, idx);
1913
1914 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1915 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
1916 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
1917 assert(dyn_idx < dynamicOffsetCount);
1918
1919 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
1920 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
1921 dst[0] = va;
1922 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
1923 dst[2] = range->size;
1924 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1925 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1926 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1927 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1928 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1929 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1930 cmd_buffer->push_constant_stages |=
1931 set->layout->dynamic_shader_stages;
1932 }
1933 }
1934
1935 assert(cmd_buffer->cs->cdw <= cdw_max);
1936 }
1937
1938 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1939 struct radv_descriptor_set *set,
1940 struct radv_descriptor_set_layout *layout)
1941 {
1942 set->size = layout->size;
1943 set->layout = layout;
1944
1945 if (cmd_buffer->push_descriptors.capacity < set->size) {
1946 size_t new_size = MAX2(set->size, 1024);
1947 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
1948 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
1949
1950 free(set->mapped_ptr);
1951 set->mapped_ptr = malloc(new_size);
1952
1953 if (!set->mapped_ptr) {
1954 cmd_buffer->push_descriptors.capacity = 0;
1955 cmd_buffer->record_fail = true;
1956 return false;
1957 }
1958
1959 cmd_buffer->push_descriptors.capacity = new_size;
1960 }
1961
1962 return true;
1963 }
1964
1965 void radv_CmdPushDescriptorSetKHR(
1966 VkCommandBuffer commandBuffer,
1967 VkPipelineBindPoint pipelineBindPoint,
1968 VkPipelineLayout _layout,
1969 uint32_t set,
1970 uint32_t descriptorWriteCount,
1971 const VkWriteDescriptorSet* pDescriptorWrites)
1972 {
1973 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1974 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
1975 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
1976
1977 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
1978
1979 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
1980 return;
1981
1982 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
1983 radv_descriptor_set_to_handle(push_set),
1984 descriptorWriteCount, pDescriptorWrites, 0, NULL);
1985
1986 cmd_buffer->state.descriptors[set] = push_set;
1987 cmd_buffer->state.descriptors_dirty |= (1 << set);
1988 cmd_buffer->state.push_descriptors_dirty = true;
1989 }
1990
1991 void radv_CmdPushDescriptorSetWithTemplateKHR(
1992 VkCommandBuffer commandBuffer,
1993 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1994 VkPipelineLayout _layout,
1995 uint32_t set,
1996 const void* pData)
1997 {
1998 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1999 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2000 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2001
2002 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2003
2004 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2005 return;
2006
2007 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2008 descriptorUpdateTemplate, pData);
2009
2010 cmd_buffer->state.descriptors[set] = push_set;
2011 cmd_buffer->state.descriptors_dirty |= (1 << set);
2012 cmd_buffer->state.push_descriptors_dirty = true;
2013 }
2014
2015 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2016 VkPipelineLayout layout,
2017 VkShaderStageFlags stageFlags,
2018 uint32_t offset,
2019 uint32_t size,
2020 const void* pValues)
2021 {
2022 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2023 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2024 cmd_buffer->push_constant_stages |= stageFlags;
2025 }
2026
2027 VkResult radv_EndCommandBuffer(
2028 VkCommandBuffer commandBuffer)
2029 {
2030 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2031
2032 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER)
2033 si_emit_cache_flush(cmd_buffer);
2034
2035 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs) ||
2036 cmd_buffer->record_fail)
2037 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2038 return VK_SUCCESS;
2039 }
2040
2041 static void
2042 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2043 {
2044 struct radeon_winsys *ws = cmd_buffer->device->ws;
2045 struct radv_shader_variant *compute_shader;
2046 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2047 uint64_t va;
2048
2049 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2050 return;
2051
2052 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2053
2054 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2055 va = ws->buffer_get_va(compute_shader->bo);
2056
2057 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
2058
2059 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2060 cmd_buffer->cs, 16);
2061
2062 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2063 radeon_emit(cmd_buffer->cs, va >> 8);
2064 radeon_emit(cmd_buffer->cs, va >> 40);
2065
2066 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2067 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2068 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2069
2070
2071 cmd_buffer->compute_scratch_size_needed =
2072 MAX2(cmd_buffer->compute_scratch_size_needed,
2073 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2074
2075 /* change these once we have scratch support */
2076 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2077 S_00B860_WAVES(pipeline->max_waves) |
2078 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2079
2080 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2081 radeon_emit(cmd_buffer->cs,
2082 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2083 radeon_emit(cmd_buffer->cs,
2084 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2085 radeon_emit(cmd_buffer->cs,
2086 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2087
2088 assert(cmd_buffer->cs->cdw <= cdw_max);
2089 }
2090
2091
2092 void radv_CmdBindPipeline(
2093 VkCommandBuffer commandBuffer,
2094 VkPipelineBindPoint pipelineBindPoint,
2095 VkPipeline _pipeline)
2096 {
2097 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2098 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2099
2100 for (unsigned i = 0; i < MAX_SETS; i++) {
2101 if (cmd_buffer->state.descriptors[i])
2102 cmd_buffer->state.descriptors_dirty |= (1 << i);
2103 }
2104
2105 switch (pipelineBindPoint) {
2106 case VK_PIPELINE_BIND_POINT_COMPUTE:
2107 cmd_buffer->state.compute_pipeline = pipeline;
2108 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2109 break;
2110 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2111 cmd_buffer->state.pipeline = pipeline;
2112 cmd_buffer->state.vertex_descriptors_dirty = true;
2113 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2114 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2115
2116 /* Apply the dynamic state from the pipeline */
2117 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
2118 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
2119 &pipeline->dynamic_state,
2120 pipeline->dynamic_state_mask);
2121
2122 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2123 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2124 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2125 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2126
2127 if (radv_pipeline_has_tess(pipeline))
2128 cmd_buffer->tess_rings_needed = true;
2129
2130 if (radv_pipeline_has_gs(pipeline)) {
2131 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2132 AC_UD_SCRATCH_RING_OFFSETS);
2133 if (cmd_buffer->ring_offsets_idx == -1)
2134 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2135 else if (loc->sgpr_idx != -1)
2136 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2137 }
2138 break;
2139 default:
2140 assert(!"invalid bind point");
2141 break;
2142 }
2143 }
2144
2145 void radv_CmdSetViewport(
2146 VkCommandBuffer commandBuffer,
2147 uint32_t firstViewport,
2148 uint32_t viewportCount,
2149 const VkViewport* pViewports)
2150 {
2151 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2152
2153 const uint32_t total_count = firstViewport + viewportCount;
2154 if (cmd_buffer->state.dynamic.viewport.count < total_count)
2155 cmd_buffer->state.dynamic.viewport.count = total_count;
2156
2157 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2158 pViewports, viewportCount * sizeof(*pViewports));
2159
2160 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2161 }
2162
2163 void radv_CmdSetScissor(
2164 VkCommandBuffer commandBuffer,
2165 uint32_t firstScissor,
2166 uint32_t scissorCount,
2167 const VkRect2D* pScissors)
2168 {
2169 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2170
2171 const uint32_t total_count = firstScissor + scissorCount;
2172 if (cmd_buffer->state.dynamic.scissor.count < total_count)
2173 cmd_buffer->state.dynamic.scissor.count = total_count;
2174
2175 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2176 pScissors, scissorCount * sizeof(*pScissors));
2177 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2178 }
2179
2180 void radv_CmdSetLineWidth(
2181 VkCommandBuffer commandBuffer,
2182 float lineWidth)
2183 {
2184 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2185 cmd_buffer->state.dynamic.line_width = lineWidth;
2186 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2187 }
2188
2189 void radv_CmdSetDepthBias(
2190 VkCommandBuffer commandBuffer,
2191 float depthBiasConstantFactor,
2192 float depthBiasClamp,
2193 float depthBiasSlopeFactor)
2194 {
2195 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2196
2197 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2198 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2199 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2200
2201 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2202 }
2203
2204 void radv_CmdSetBlendConstants(
2205 VkCommandBuffer commandBuffer,
2206 const float blendConstants[4])
2207 {
2208 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2209
2210 memcpy(cmd_buffer->state.dynamic.blend_constants,
2211 blendConstants, sizeof(float) * 4);
2212
2213 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2214 }
2215
2216 void radv_CmdSetDepthBounds(
2217 VkCommandBuffer commandBuffer,
2218 float minDepthBounds,
2219 float maxDepthBounds)
2220 {
2221 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2222
2223 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2224 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2225
2226 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2227 }
2228
2229 void radv_CmdSetStencilCompareMask(
2230 VkCommandBuffer commandBuffer,
2231 VkStencilFaceFlags faceMask,
2232 uint32_t compareMask)
2233 {
2234 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2235
2236 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2237 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2238 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2239 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2240
2241 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2242 }
2243
2244 void radv_CmdSetStencilWriteMask(
2245 VkCommandBuffer commandBuffer,
2246 VkStencilFaceFlags faceMask,
2247 uint32_t writeMask)
2248 {
2249 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2250
2251 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2252 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2253 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2254 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2255
2256 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2257 }
2258
2259 void radv_CmdSetStencilReference(
2260 VkCommandBuffer commandBuffer,
2261 VkStencilFaceFlags faceMask,
2262 uint32_t reference)
2263 {
2264 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2265
2266 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2267 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2268 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2269 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2270
2271 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2272 }
2273
2274
2275 void radv_CmdExecuteCommands(
2276 VkCommandBuffer commandBuffer,
2277 uint32_t commandBufferCount,
2278 const VkCommandBuffer* pCmdBuffers)
2279 {
2280 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2281
2282 /* Emit pending flushes on primary prior to executing secondary */
2283 si_emit_cache_flush(primary);
2284
2285 for (uint32_t i = 0; i < commandBufferCount; i++) {
2286 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2287
2288 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2289 secondary->scratch_size_needed);
2290 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2291 secondary->compute_scratch_size_needed);
2292
2293 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2294 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2295 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2296 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2297 if (secondary->tess_rings_needed)
2298 primary->tess_rings_needed = true;
2299 if (secondary->sample_positions_needed)
2300 primary->sample_positions_needed = true;
2301
2302 if (secondary->ring_offsets_idx != -1) {
2303 if (primary->ring_offsets_idx == -1)
2304 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2305 else
2306 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2307 }
2308 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2309 }
2310
2311 /* if we execute secondary we need to re-emit out pipelines */
2312 if (commandBufferCount) {
2313 primary->state.emitted_pipeline = NULL;
2314 primary->state.emitted_compute_pipeline = NULL;
2315 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2316 primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
2317 }
2318 }
2319
2320 VkResult radv_CreateCommandPool(
2321 VkDevice _device,
2322 const VkCommandPoolCreateInfo* pCreateInfo,
2323 const VkAllocationCallbacks* pAllocator,
2324 VkCommandPool* pCmdPool)
2325 {
2326 RADV_FROM_HANDLE(radv_device, device, _device);
2327 struct radv_cmd_pool *pool;
2328
2329 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2330 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2331 if (pool == NULL)
2332 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2333
2334 if (pAllocator)
2335 pool->alloc = *pAllocator;
2336 else
2337 pool->alloc = device->alloc;
2338
2339 list_inithead(&pool->cmd_buffers);
2340 list_inithead(&pool->free_cmd_buffers);
2341
2342 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2343
2344 *pCmdPool = radv_cmd_pool_to_handle(pool);
2345
2346 return VK_SUCCESS;
2347
2348 }
2349
2350 void radv_DestroyCommandPool(
2351 VkDevice _device,
2352 VkCommandPool commandPool,
2353 const VkAllocationCallbacks* pAllocator)
2354 {
2355 RADV_FROM_HANDLE(radv_device, device, _device);
2356 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2357
2358 if (!pool)
2359 return;
2360
2361 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2362 &pool->cmd_buffers, pool_link) {
2363 radv_cmd_buffer_destroy(cmd_buffer);
2364 }
2365
2366 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2367 &pool->free_cmd_buffers, pool_link) {
2368 radv_cmd_buffer_destroy(cmd_buffer);
2369 }
2370
2371 vk_free2(&device->alloc, pAllocator, pool);
2372 }
2373
2374 VkResult radv_ResetCommandPool(
2375 VkDevice device,
2376 VkCommandPool commandPool,
2377 VkCommandPoolResetFlags flags)
2378 {
2379 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2380
2381 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2382 &pool->cmd_buffers, pool_link) {
2383 radv_reset_cmd_buffer(cmd_buffer);
2384 }
2385
2386 return VK_SUCCESS;
2387 }
2388
2389 void radv_TrimCommandPoolKHR(
2390 VkDevice device,
2391 VkCommandPool commandPool,
2392 VkCommandPoolTrimFlagsKHR flags)
2393 {
2394 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2395
2396 if (!pool)
2397 return;
2398
2399 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2400 &pool->free_cmd_buffers, pool_link) {
2401 radv_cmd_buffer_destroy(cmd_buffer);
2402 }
2403 }
2404
2405 void radv_CmdBeginRenderPass(
2406 VkCommandBuffer commandBuffer,
2407 const VkRenderPassBeginInfo* pRenderPassBegin,
2408 VkSubpassContents contents)
2409 {
2410 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2411 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2412 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2413
2414 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2415 cmd_buffer->cs, 2048);
2416
2417 cmd_buffer->state.framebuffer = framebuffer;
2418 cmd_buffer->state.pass = pass;
2419 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2420 radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2421
2422 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2423 assert(cmd_buffer->cs->cdw <= cdw_max);
2424
2425 radv_cmd_buffer_clear_subpass(cmd_buffer);
2426 }
2427
2428 void radv_CmdNextSubpass(
2429 VkCommandBuffer commandBuffer,
2430 VkSubpassContents contents)
2431 {
2432 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2433
2434 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2435
2436 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2437 2048);
2438
2439 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2440 radv_cmd_buffer_clear_subpass(cmd_buffer);
2441 }
2442
2443 void radv_CmdDraw(
2444 VkCommandBuffer commandBuffer,
2445 uint32_t vertexCount,
2446 uint32_t instanceCount,
2447 uint32_t firstVertex,
2448 uint32_t firstInstance)
2449 {
2450 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2451
2452 radv_cmd_buffer_flush_state(cmd_buffer, (instanceCount > 1), false, vertexCount);
2453
2454 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2455
2456 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2457 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2458 if (loc->sgpr_idx != -1) {
2459 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
2460 radv_pipeline_has_tess(cmd_buffer->state.pipeline));
2461 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 3);
2462 radeon_emit(cmd_buffer->cs, firstVertex);
2463 radeon_emit(cmd_buffer->cs, firstInstance);
2464 radeon_emit(cmd_buffer->cs, 0);
2465 }
2466 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2467 radeon_emit(cmd_buffer->cs, instanceCount);
2468
2469 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, 0));
2470 radeon_emit(cmd_buffer->cs, vertexCount);
2471 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2472 S_0287F0_USE_OPAQUE(0));
2473
2474 assert(cmd_buffer->cs->cdw <= cdw_max);
2475
2476 radv_cmd_buffer_trace_emit(cmd_buffer);
2477 }
2478
2479 static void radv_emit_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2480 {
2481 uint32_t primitive_reset_index = cmd_buffer->state.index_type ? 0xffffffffu : 0xffffu;
2482
2483 if (cmd_buffer->state.pipeline->graphics.prim_restart_enable &&
2484 primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
2485 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
2486 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2487 primitive_reset_index);
2488 }
2489 }
2490
2491 void radv_CmdDrawIndexed(
2492 VkCommandBuffer commandBuffer,
2493 uint32_t indexCount,
2494 uint32_t instanceCount,
2495 uint32_t firstIndex,
2496 int32_t vertexOffset,
2497 uint32_t firstInstance)
2498 {
2499 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2500 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2501 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2502 uint64_t index_va;
2503
2504 radv_cmd_buffer_flush_state(cmd_buffer, (instanceCount > 1), false, indexCount);
2505 radv_emit_primitive_reset_index(cmd_buffer);
2506
2507 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2508
2509 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2510 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2511
2512 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2513 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2514 if (loc->sgpr_idx != -1) {
2515 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
2516 radv_pipeline_has_tess(cmd_buffer->state.pipeline));
2517 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 3);
2518 radeon_emit(cmd_buffer->cs, vertexOffset);
2519 radeon_emit(cmd_buffer->cs, firstInstance);
2520 radeon_emit(cmd_buffer->cs, 0);
2521 }
2522 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2523 radeon_emit(cmd_buffer->cs, instanceCount);
2524
2525 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2526 index_va += firstIndex * index_size + cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2527 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2528 radeon_emit(cmd_buffer->cs, index_max_size);
2529 radeon_emit(cmd_buffer->cs, index_va);
2530 radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
2531 radeon_emit(cmd_buffer->cs, indexCount);
2532 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2533
2534 assert(cmd_buffer->cs->cdw <= cdw_max);
2535 radv_cmd_buffer_trace_emit(cmd_buffer);
2536 }
2537
2538 static void
2539 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
2540 VkBuffer _buffer,
2541 VkDeviceSize offset,
2542 VkBuffer _count_buffer,
2543 VkDeviceSize count_offset,
2544 uint32_t draw_count,
2545 uint32_t stride,
2546 bool indexed)
2547 {
2548 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2549 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
2550 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2551 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2552 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2553 uint64_t indirect_va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2554 indirect_va += offset + buffer->offset;
2555 uint64_t count_va = 0;
2556
2557 if (count_buffer) {
2558 count_va = cmd_buffer->device->ws->buffer_get_va(count_buffer->bo);
2559 count_va += count_offset + count_buffer->offset;
2560 }
2561
2562 if (!draw_count)
2563 return;
2564
2565 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
2566
2567 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2568 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2569 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
2570 radv_pipeline_has_tess(cmd_buffer->state.pipeline));
2571 assert(loc->sgpr_idx != -1);
2572 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2573 radeon_emit(cs, 1);
2574 radeon_emit(cs, indirect_va);
2575 radeon_emit(cs, indirect_va >> 32);
2576
2577 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2578 PKT3_DRAW_INDIRECT_MULTI,
2579 8, false));
2580 radeon_emit(cs, 0);
2581 radeon_emit(cs, ((base_reg + loc->sgpr_idx * 4) - SI_SH_REG_OFFSET) >> 2);
2582 radeon_emit(cs, ((base_reg + (loc->sgpr_idx + 1) * 4) - SI_SH_REG_OFFSET) >> 2);
2583 radeon_emit(cs, (((base_reg + (loc->sgpr_idx + 2) * 4) - SI_SH_REG_OFFSET) >> 2) |
2584 S_2C3_DRAW_INDEX_ENABLE(1) |
2585 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2586 radeon_emit(cs, draw_count); /* count */
2587 radeon_emit(cs, count_va); /* count_addr */
2588 radeon_emit(cs, count_va >> 32);
2589 radeon_emit(cs, stride); /* stride */
2590 radeon_emit(cs, di_src_sel);
2591 radv_cmd_buffer_trace_emit(cmd_buffer);
2592 }
2593
2594 static void
2595 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
2596 VkBuffer buffer,
2597 VkDeviceSize offset,
2598 VkBuffer countBuffer,
2599 VkDeviceSize countBufferOffset,
2600 uint32_t maxDrawCount,
2601 uint32_t stride)
2602 {
2603 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2604 radv_cmd_buffer_flush_state(cmd_buffer, false, true, 0);
2605
2606 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2607 cmd_buffer->cs, 14);
2608
2609 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2610 countBuffer, countBufferOffset, maxDrawCount, stride, false);
2611
2612 assert(cmd_buffer->cs->cdw <= cdw_max);
2613 }
2614
2615 static void
2616 radv_cmd_draw_indexed_indirect_count(
2617 VkCommandBuffer commandBuffer,
2618 VkBuffer buffer,
2619 VkDeviceSize offset,
2620 VkBuffer countBuffer,
2621 VkDeviceSize countBufferOffset,
2622 uint32_t maxDrawCount,
2623 uint32_t stride)
2624 {
2625 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2626 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2627 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2628 uint64_t index_va;
2629 radv_cmd_buffer_flush_state(cmd_buffer, false, true, 0);
2630 radv_emit_primitive_reset_index(cmd_buffer);
2631
2632 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2633 index_va += cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2634
2635 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 21);
2636
2637 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2638 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2639
2640 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2641 radeon_emit(cmd_buffer->cs, index_va);
2642 radeon_emit(cmd_buffer->cs, index_va >> 32);
2643
2644 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2645 radeon_emit(cmd_buffer->cs, index_max_size);
2646
2647 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2648 countBuffer, countBufferOffset, maxDrawCount, stride, true);
2649
2650 assert(cmd_buffer->cs->cdw <= cdw_max);
2651 }
2652
2653 void radv_CmdDrawIndirect(
2654 VkCommandBuffer commandBuffer,
2655 VkBuffer buffer,
2656 VkDeviceSize offset,
2657 uint32_t drawCount,
2658 uint32_t stride)
2659 {
2660 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2661 VK_NULL_HANDLE, 0, drawCount, stride);
2662 }
2663
2664 void radv_CmdDrawIndexedIndirect(
2665 VkCommandBuffer commandBuffer,
2666 VkBuffer buffer,
2667 VkDeviceSize offset,
2668 uint32_t drawCount,
2669 uint32_t stride)
2670 {
2671 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2672 VK_NULL_HANDLE, 0, drawCount, stride);
2673 }
2674
2675 void radv_CmdDrawIndirectCountAMD(
2676 VkCommandBuffer commandBuffer,
2677 VkBuffer buffer,
2678 VkDeviceSize offset,
2679 VkBuffer countBuffer,
2680 VkDeviceSize countBufferOffset,
2681 uint32_t maxDrawCount,
2682 uint32_t stride)
2683 {
2684 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2685 countBuffer, countBufferOffset,
2686 maxDrawCount, stride);
2687 }
2688
2689 void radv_CmdDrawIndexedIndirectCountAMD(
2690 VkCommandBuffer commandBuffer,
2691 VkBuffer buffer,
2692 VkDeviceSize offset,
2693 VkBuffer countBuffer,
2694 VkDeviceSize countBufferOffset,
2695 uint32_t maxDrawCount,
2696 uint32_t stride)
2697 {
2698 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2699 countBuffer, countBufferOffset,
2700 maxDrawCount, stride);
2701 }
2702
2703 static void
2704 radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
2705 {
2706 radv_emit_compute_pipeline(cmd_buffer);
2707 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.compute_pipeline,
2708 VK_SHADER_STAGE_COMPUTE_BIT);
2709 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
2710 VK_SHADER_STAGE_COMPUTE_BIT);
2711 si_emit_cache_flush(cmd_buffer);
2712 }
2713
2714 void radv_CmdDispatch(
2715 VkCommandBuffer commandBuffer,
2716 uint32_t x,
2717 uint32_t y,
2718 uint32_t z)
2719 {
2720 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2721
2722 radv_flush_compute_state(cmd_buffer);
2723
2724 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2725
2726 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2727 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2728 if (loc->sgpr_idx != -1) {
2729 assert(!loc->indirect);
2730 assert(loc->num_sgprs == 3);
2731 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3);
2732 radeon_emit(cmd_buffer->cs, x);
2733 radeon_emit(cmd_buffer->cs, y);
2734 radeon_emit(cmd_buffer->cs, z);
2735 }
2736
2737 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2738 PKT3_SHADER_TYPE_S(1));
2739 radeon_emit(cmd_buffer->cs, x);
2740 radeon_emit(cmd_buffer->cs, y);
2741 radeon_emit(cmd_buffer->cs, z);
2742 radeon_emit(cmd_buffer->cs, 1);
2743
2744 assert(cmd_buffer->cs->cdw <= cdw_max);
2745 radv_cmd_buffer_trace_emit(cmd_buffer);
2746 }
2747
2748 void radv_CmdDispatchIndirect(
2749 VkCommandBuffer commandBuffer,
2750 VkBuffer _buffer,
2751 VkDeviceSize offset)
2752 {
2753 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2754 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2755 uint64_t va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2756 va += buffer->offset + offset;
2757
2758 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
2759
2760 radv_flush_compute_state(cmd_buffer);
2761
2762 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 25);
2763 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2764 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2765 if (loc->sgpr_idx != -1) {
2766 for (unsigned i = 0; i < 3; ++i) {
2767 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
2768 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
2769 COPY_DATA_DST_SEL(COPY_DATA_REG));
2770 radeon_emit(cmd_buffer->cs, (va + 4 * i));
2771 radeon_emit(cmd_buffer->cs, (va + 4 * i) >> 32);
2772 radeon_emit(cmd_buffer->cs, ((R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4) >> 2) + i);
2773 radeon_emit(cmd_buffer->cs, 0);
2774 }
2775 }
2776
2777 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
2778 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
2779 PKT3_SHADER_TYPE_S(1));
2780 radeon_emit(cmd_buffer->cs, va);
2781 radeon_emit(cmd_buffer->cs, va >> 32);
2782 radeon_emit(cmd_buffer->cs, 1);
2783 } else {
2784 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_BASE, 2, 0) |
2785 PKT3_SHADER_TYPE_S(1));
2786 radeon_emit(cmd_buffer->cs, 1);
2787 radeon_emit(cmd_buffer->cs, va);
2788 radeon_emit(cmd_buffer->cs, va >> 32);
2789
2790 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
2791 PKT3_SHADER_TYPE_S(1));
2792 radeon_emit(cmd_buffer->cs, 0);
2793 radeon_emit(cmd_buffer->cs, 1);
2794 }
2795
2796 assert(cmd_buffer->cs->cdw <= cdw_max);
2797 radv_cmd_buffer_trace_emit(cmd_buffer);
2798 }
2799
2800 void radv_unaligned_dispatch(
2801 struct radv_cmd_buffer *cmd_buffer,
2802 uint32_t x,
2803 uint32_t y,
2804 uint32_t z)
2805 {
2806 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2807 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2808 uint32_t blocks[3], remainder[3];
2809
2810 blocks[0] = round_up_u32(x, compute_shader->info.cs.block_size[0]);
2811 blocks[1] = round_up_u32(y, compute_shader->info.cs.block_size[1]);
2812 blocks[2] = round_up_u32(z, compute_shader->info.cs.block_size[2]);
2813
2814 /* If aligned, these should be an entire block size, not 0 */
2815 remainder[0] = x + compute_shader->info.cs.block_size[0] - align_u32_npot(x, compute_shader->info.cs.block_size[0]);
2816 remainder[1] = y + compute_shader->info.cs.block_size[1] - align_u32_npot(y, compute_shader->info.cs.block_size[1]);
2817 remainder[2] = z + compute_shader->info.cs.block_size[2] - align_u32_npot(z, compute_shader->info.cs.block_size[2]);
2818
2819 radv_flush_compute_state(cmd_buffer);
2820
2821 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2822
2823 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2824 radeon_emit(cmd_buffer->cs,
2825 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]) |
2826 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
2827 radeon_emit(cmd_buffer->cs,
2828 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]) |
2829 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
2830 radeon_emit(cmd_buffer->cs,
2831 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]) |
2832 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
2833
2834 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2835 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2836 if (loc->sgpr_idx != -1) {
2837 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3);
2838 radeon_emit(cmd_buffer->cs, blocks[0]);
2839 radeon_emit(cmd_buffer->cs, blocks[1]);
2840 radeon_emit(cmd_buffer->cs, blocks[2]);
2841 }
2842 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2843 PKT3_SHADER_TYPE_S(1));
2844 radeon_emit(cmd_buffer->cs, blocks[0]);
2845 radeon_emit(cmd_buffer->cs, blocks[1]);
2846 radeon_emit(cmd_buffer->cs, blocks[2]);
2847 radeon_emit(cmd_buffer->cs, S_00B800_COMPUTE_SHADER_EN(1) |
2848 S_00B800_PARTIAL_TG_EN(1));
2849
2850 assert(cmd_buffer->cs->cdw <= cdw_max);
2851 radv_cmd_buffer_trace_emit(cmd_buffer);
2852 }
2853
2854 void radv_CmdEndRenderPass(
2855 VkCommandBuffer commandBuffer)
2856 {
2857 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2858
2859 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
2860
2861 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2862
2863 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
2864 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
2865 radv_handle_subpass_image_transition(cmd_buffer,
2866 (VkAttachmentReference){i, layout});
2867 }
2868
2869 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2870
2871 cmd_buffer->state.pass = NULL;
2872 cmd_buffer->state.subpass = NULL;
2873 cmd_buffer->state.attachments = NULL;
2874 cmd_buffer->state.framebuffer = NULL;
2875 }
2876
2877
2878 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
2879 struct radv_image *image,
2880 const VkImageSubresourceRange *range)
2881 {
2882 assert(range->baseMipLevel == 0);
2883 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
2884 unsigned layer_count = radv_get_layerCount(image, range);
2885 uint64_t size = image->surface.htile_slice_size * layer_count;
2886 uint64_t offset = image->offset + image->htile_offset +
2887 image->surface.htile_slice_size * range->baseArrayLayer;
2888
2889 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2890 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2891
2892 radv_fill_buffer(cmd_buffer, image->bo, offset, size, 0xffffffff);
2893
2894 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
2895 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2896 RADV_CMD_FLAG_INV_VMEM_L1 |
2897 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2898 }
2899
2900 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
2901 struct radv_image *image,
2902 VkImageLayout src_layout,
2903 VkImageLayout dst_layout,
2904 const VkImageSubresourceRange *range,
2905 VkImageAspectFlags pending_clears)
2906 {
2907 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
2908 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
2909 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
2910 cmd_buffer->state.render_area.extent.width == image->extent.width &&
2911 cmd_buffer->state.render_area.extent.height == image->extent.height) {
2912 /* The clear will initialize htile. */
2913 return;
2914 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
2915 radv_layout_has_htile(image, dst_layout)) {
2916 /* TODO: merge with the clear if applicable */
2917 radv_initialize_htile(cmd_buffer, image, range);
2918 } else if (!radv_layout_has_htile(image, src_layout) &&
2919 radv_layout_has_htile(image, dst_layout)) {
2920 radv_initialize_htile(cmd_buffer, image, range);
2921 } else if ((radv_layout_has_htile(image, src_layout) &&
2922 !radv_layout_has_htile(image, dst_layout)) ||
2923 (radv_layout_is_htile_compressed(image, src_layout) &&
2924 !radv_layout_is_htile_compressed(image, dst_layout))) {
2925 VkImageSubresourceRange local_range = *range;
2926 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
2927 local_range.baseMipLevel = 0;
2928 local_range.levelCount = 1;
2929
2930 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2931 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2932
2933 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
2934
2935 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2936 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2937 }
2938 }
2939
2940 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
2941 struct radv_image *image, uint32_t value)
2942 {
2943 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2944 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2945
2946 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
2947 image->cmask.size, value);
2948
2949 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2950 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2951 RADV_CMD_FLAG_INV_VMEM_L1 |
2952 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2953 }
2954
2955 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
2956 struct radv_image *image,
2957 VkImageLayout src_layout,
2958 VkImageLayout dst_layout,
2959 unsigned src_queue_mask,
2960 unsigned dst_queue_mask,
2961 const VkImageSubresourceRange *range,
2962 VkImageAspectFlags pending_clears)
2963 {
2964 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
2965 if (image->fmask.size)
2966 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
2967 else
2968 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
2969 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
2970 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
2971 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
2972 }
2973 }
2974
2975 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
2976 struct radv_image *image, uint32_t value)
2977 {
2978
2979 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2980 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2981
2982 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
2983 image->surface.dcc_size, value);
2984
2985 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2986 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2987 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2988 RADV_CMD_FLAG_INV_VMEM_L1 |
2989 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2990 }
2991
2992 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
2993 struct radv_image *image,
2994 VkImageLayout src_layout,
2995 VkImageLayout dst_layout,
2996 unsigned src_queue_mask,
2997 unsigned dst_queue_mask,
2998 const VkImageSubresourceRange *range,
2999 VkImageAspectFlags pending_clears)
3000 {
3001 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3002 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
3003 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3004 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3005 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3006 }
3007 }
3008
3009 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3010 struct radv_image *image,
3011 VkImageLayout src_layout,
3012 VkImageLayout dst_layout,
3013 uint32_t src_family,
3014 uint32_t dst_family,
3015 const VkImageSubresourceRange *range,
3016 VkImageAspectFlags pending_clears)
3017 {
3018 if (image->exclusive && src_family != dst_family) {
3019 /* This is an acquire or a release operation and there will be
3020 * a corresponding release/acquire. Do the transition in the
3021 * most flexible queue. */
3022
3023 assert(src_family == cmd_buffer->queue_family_index ||
3024 dst_family == cmd_buffer->queue_family_index);
3025
3026 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3027 return;
3028
3029 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3030 (src_family == RADV_QUEUE_GENERAL ||
3031 dst_family == RADV_QUEUE_GENERAL))
3032 return;
3033 }
3034
3035 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3036 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3037
3038 if (image->surface.htile_size)
3039 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3040 dst_layout, range, pending_clears);
3041
3042 if (image->cmask.size)
3043 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3044 dst_layout, src_queue_mask,
3045 dst_queue_mask, range,
3046 pending_clears);
3047
3048 if (image->surface.dcc_size)
3049 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3050 dst_layout, src_queue_mask,
3051 dst_queue_mask, range,
3052 pending_clears);
3053 }
3054
3055 void radv_CmdPipelineBarrier(
3056 VkCommandBuffer commandBuffer,
3057 VkPipelineStageFlags srcStageMask,
3058 VkPipelineStageFlags destStageMask,
3059 VkBool32 byRegion,
3060 uint32_t memoryBarrierCount,
3061 const VkMemoryBarrier* pMemoryBarriers,
3062 uint32_t bufferMemoryBarrierCount,
3063 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3064 uint32_t imageMemoryBarrierCount,
3065 const VkImageMemoryBarrier* pImageMemoryBarriers)
3066 {
3067 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3068 enum radv_cmd_flush_bits src_flush_bits = 0;
3069 enum radv_cmd_flush_bits dst_flush_bits = 0;
3070
3071 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3072 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3073 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3074 NULL);
3075 }
3076
3077 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3078 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3079 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3080 NULL);
3081 }
3082
3083 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3084 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3085 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3086 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3087 image);
3088 }
3089
3090 radv_stage_flush(cmd_buffer, srcStageMask);
3091 cmd_buffer->state.flush_bits |= src_flush_bits;
3092
3093 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3094 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3095 radv_handle_image_transition(cmd_buffer, image,
3096 pImageMemoryBarriers[i].oldLayout,
3097 pImageMemoryBarriers[i].newLayout,
3098 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3099 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3100 &pImageMemoryBarriers[i].subresourceRange,
3101 0);
3102 }
3103
3104 cmd_buffer->state.flush_bits |= dst_flush_bits;
3105 }
3106
3107
3108 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3109 struct radv_event *event,
3110 VkPipelineStageFlags stageMask,
3111 unsigned value)
3112 {
3113 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3114 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3115
3116 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3117
3118 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 12);
3119
3120 /* TODO: this is overkill. Probably should figure something out from
3121 * the stage mask. */
3122
3123 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK) {
3124 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
3125 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
3126 EVENT_INDEX(5));
3127 radeon_emit(cs, va);
3128 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
3129 radeon_emit(cs, 2);
3130 radeon_emit(cs, 0);
3131 }
3132
3133 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
3134 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
3135 EVENT_INDEX(5));
3136 radeon_emit(cs, va);
3137 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
3138 radeon_emit(cs, value);
3139 radeon_emit(cs, 0);
3140
3141 assert(cmd_buffer->cs->cdw <= cdw_max);
3142 }
3143
3144 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3145 VkEvent _event,
3146 VkPipelineStageFlags stageMask)
3147 {
3148 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3149 RADV_FROM_HANDLE(radv_event, event, _event);
3150
3151 write_event(cmd_buffer, event, stageMask, 1);
3152 }
3153
3154 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3155 VkEvent _event,
3156 VkPipelineStageFlags stageMask)
3157 {
3158 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3159 RADV_FROM_HANDLE(radv_event, event, _event);
3160
3161 write_event(cmd_buffer, event, stageMask, 0);
3162 }
3163
3164 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3165 uint32_t eventCount,
3166 const VkEvent* pEvents,
3167 VkPipelineStageFlags srcStageMask,
3168 VkPipelineStageFlags dstStageMask,
3169 uint32_t memoryBarrierCount,
3170 const VkMemoryBarrier* pMemoryBarriers,
3171 uint32_t bufferMemoryBarrierCount,
3172 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3173 uint32_t imageMemoryBarrierCount,
3174 const VkImageMemoryBarrier* pImageMemoryBarriers)
3175 {
3176 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3177 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3178
3179 for (unsigned i = 0; i < eventCount; ++i) {
3180 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3181 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3182
3183 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3184
3185 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3186
3187 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
3188 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
3189 radeon_emit(cs, va);
3190 radeon_emit(cs, va >> 32);
3191 radeon_emit(cs, 1); /* reference value */
3192 radeon_emit(cs, 0xffffffff); /* mask */
3193 radeon_emit(cs, 4); /* poll interval */
3194
3195 assert(cmd_buffer->cs->cdw <= cdw_max);
3196 }
3197
3198
3199 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3200 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3201
3202 radv_handle_image_transition(cmd_buffer, image,
3203 pImageMemoryBarriers[i].oldLayout,
3204 pImageMemoryBarriers[i].newLayout,
3205 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3206 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3207 &pImageMemoryBarriers[i].subresourceRange,
3208 0);
3209 }
3210
3211 /* TODO: figure out how to do memory barriers without waiting */
3212 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3213 RADV_CMD_FLAG_INV_GLOBAL_L2 |
3214 RADV_CMD_FLAG_INV_VMEM_L1 |
3215 RADV_CMD_FLAG_INV_SMEM_L1;
3216 }