projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: emit the initial config only once in the preambles
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range,
61 VkImageAspectFlags pending_clears);
62
63 const struct radv_dynamic_state default_dynamic_state = {
64 .viewport = {
65 .count = 0,
66 },
67 .scissor = {
68 .count = 0,
69 },
70 .line_width = 1.0f,
71 .depth_bias = {
72 .bias = 0.0f,
73 .clamp = 0.0f,
74 .slope = 0.0f,
75 },
76 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
77 .depth_bounds = {
78 .min = 0.0f,
79 .max = 1.0f,
80 },
81 .stencil_compare_mask = {
82 .front = ~0u,
83 .back = ~0u,
84 },
85 .stencil_write_mask = {
86 .front = ~0u,
87 .back = ~0u,
88 },
89 .stencil_reference = {
90 .front = 0u,
91 .back = 0u,
92 },
93 };
94
95 static void
96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
97 const struct radv_dynamic_state *src)
98 {
99 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
100 uint32_t copy_mask = src->mask;
101 uint32_t dest_mask = 0;
102
103 /* Make sure to copy the number of viewports/scissors because they can
104 * only be specified at pipeline creation time.
105 */
106 dest->viewport.count = src->viewport.count;
107 dest->scissor.count = src->scissor.count;
108 dest->discard_rectangle.count = src->discard_rectangle.count;
109
110 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
111 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
112 src->viewport.count * sizeof(VkViewport))) {
113 typed_memcpy(dest->viewport.viewports,
114 src->viewport.viewports,
115 src->viewport.count);
116 dest_mask |= RADV_DYNAMIC_VIEWPORT;
117 }
118 }
119
120 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
121 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
122 src->scissor.count * sizeof(VkRect2D))) {
123 typed_memcpy(dest->scissor.scissors,
124 src->scissor.scissors, src->scissor.count);
125 dest_mask |= RADV_DYNAMIC_SCISSOR;
126 }
127 }
128
129 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
130 if (dest->line_width != src->line_width) {
131 dest->line_width = src->line_width;
132 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
133 }
134 }
135
136 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
137 if (memcmp(&dest->depth_bias, &src->depth_bias,
138 sizeof(src->depth_bias))) {
139 dest->depth_bias = src->depth_bias;
140 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
141 }
142 }
143
144 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
145 if (memcmp(&dest->blend_constants, &src->blend_constants,
146 sizeof(src->blend_constants))) {
147 typed_memcpy(dest->blend_constants,
148 src->blend_constants, 4);
149 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
150 }
151 }
152
153 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
154 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
155 sizeof(src->depth_bounds))) {
156 dest->depth_bounds = src->depth_bounds;
157 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
158 }
159 }
160
161 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
162 if (memcmp(&dest->stencil_compare_mask,
163 &src->stencil_compare_mask,
164 sizeof(src->stencil_compare_mask))) {
165 dest->stencil_compare_mask = src->stencil_compare_mask;
166 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
167 }
168 }
169
170 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
171 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
172 sizeof(src->stencil_write_mask))) {
173 dest->stencil_write_mask = src->stencil_write_mask;
174 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
175 }
176 }
177
178 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
179 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
180 sizeof(src->stencil_reference))) {
181 dest->stencil_reference = src->stencil_reference;
182 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
183 }
184 }
185
186 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
187 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
188 src->discard_rectangle.count * sizeof(VkRect2D))) {
189 typed_memcpy(dest->discard_rectangle.rectangles,
190 src->discard_rectangle.rectangles,
191 src->discard_rectangle.count);
192 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
193 }
194 }
195
196 cmd_buffer->state.dirty |= dest_mask;
197 }
198
199 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
200 {
201 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
202 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
203 }
204
205 enum ring_type radv_queue_family_to_ring(int f) {
206 switch (f) {
207 case RADV_QUEUE_GENERAL:
208 return RING_GFX;
209 case RADV_QUEUE_COMPUTE:
210 return RING_COMPUTE;
211 case RADV_QUEUE_TRANSFER:
212 return RING_DMA;
213 default:
214 unreachable("Unknown queue family");
215 }
216 }
217
218 static VkResult radv_create_cmd_buffer(
219 struct radv_device * device,
220 struct radv_cmd_pool * pool,
221 VkCommandBufferLevel level,
222 VkCommandBuffer* pCommandBuffer)
223 {
224 struct radv_cmd_buffer *cmd_buffer;
225 unsigned ring;
226 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
227 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
228 if (cmd_buffer == NULL)
229 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
230
231 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
232 cmd_buffer->device = device;
233 cmd_buffer->pool = pool;
234 cmd_buffer->level = level;
235
236 if (pool) {
237 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
238 cmd_buffer->queue_family_index = pool->queue_family_index;
239
240 } else {
241 /* Init the pool_link so we can safely call list_del when we destroy
242 * the command buffer
243 */
244 list_inithead(&cmd_buffer->pool_link);
245 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
246 }
247
248 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
249
250 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
251 if (!cmd_buffer->cs) {
252 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
253 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
254 }
255
256 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
257
258 list_inithead(&cmd_buffer->upload.list);
259
260 return VK_SUCCESS;
261 }
262
263 static void
264 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
265 {
266 list_del(&cmd_buffer->pool_link);
267
268 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
269 &cmd_buffer->upload.list, list) {
270 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
271 list_del(&up->list);
272 free(up);
273 }
274
275 if (cmd_buffer->upload.upload_bo)
276 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
277 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
278
279 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
280 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
281
282 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
283 }
284
285 static VkResult
286 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
287 {
288
289 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
290
291 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
292 &cmd_buffer->upload.list, list) {
293 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
294 list_del(&up->list);
295 free(up);
296 }
297
298 cmd_buffer->push_constant_stages = 0;
299 cmd_buffer->scratch_size_needed = 0;
300 cmd_buffer->compute_scratch_size_needed = 0;
301 cmd_buffer->esgs_ring_size_needed = 0;
302 cmd_buffer->gsvs_ring_size_needed = 0;
303 cmd_buffer->tess_rings_needed = false;
304 cmd_buffer->sample_positions_needed = false;
305
306 if (cmd_buffer->upload.upload_bo)
307 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
308 cmd_buffer->upload.upload_bo);
309 cmd_buffer->upload.offset = 0;
310
311 cmd_buffer->record_result = VK_SUCCESS;
312
313 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
314 cmd_buffer->descriptors[i].dirty = 0;
315 cmd_buffer->descriptors[i].valid = 0;
316 cmd_buffer->descriptors[i].push_dirty = false;
317 }
318
319 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
320 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
321 unsigned eop_bug_offset;
322 void *fence_ptr;
323
324 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
325 &cmd_buffer->gfx9_fence_offset,
326 &fence_ptr);
327 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
328
329 /* Allocate a buffer for the EOP bug on GFX9. */
330 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 0,
331 &eop_bug_offset, &fence_ptr);
332 cmd_buffer->gfx9_eop_bug_va =
333 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
334 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
335 }
336
337 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
338
339 return cmd_buffer->record_result;
340 }
341
342 static bool
343 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
344 uint64_t min_needed)
345 {
346 uint64_t new_size;
347 struct radeon_winsys_bo *bo;
348 struct radv_cmd_buffer_upload *upload;
349 struct radv_device *device = cmd_buffer->device;
350
351 new_size = MAX2(min_needed, 16 * 1024);
352 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
353
354 bo = device->ws->buffer_create(device->ws,
355 new_size, 4096,
356 RADEON_DOMAIN_GTT,
357 RADEON_FLAG_CPU_ACCESS|
358 RADEON_FLAG_NO_INTERPROCESS_SHARING |
359 RADEON_FLAG_32BIT);
360
361 if (!bo) {
362 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
363 return false;
364 }
365
366 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
367 if (cmd_buffer->upload.upload_bo) {
368 upload = malloc(sizeof(*upload));
369
370 if (!upload) {
371 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
372 device->ws->buffer_destroy(bo);
373 return false;
374 }
375
376 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
377 list_add(&upload->list, &cmd_buffer->upload.list);
378 }
379
380 cmd_buffer->upload.upload_bo = bo;
381 cmd_buffer->upload.size = new_size;
382 cmd_buffer->upload.offset = 0;
383 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
384
385 if (!cmd_buffer->upload.map) {
386 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
387 return false;
388 }
389
390 return true;
391 }
392
393 bool
394 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
395 unsigned size,
396 unsigned alignment,
397 unsigned *out_offset,
398 void **ptr)
399 {
400 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
401 if (offset + size > cmd_buffer->upload.size) {
402 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
403 return false;
404 offset = 0;
405 }
406
407 *out_offset = offset;
408 *ptr = cmd_buffer->upload.map + offset;
409
410 cmd_buffer->upload.offset = offset + size;
411 return true;
412 }
413
414 bool
415 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
416 unsigned size, unsigned alignment,
417 const void *data, unsigned *out_offset)
418 {
419 uint8_t *ptr;
420
421 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
422 out_offset, (void **)&ptr))
423 return false;
424
425 if (ptr)
426 memcpy(ptr, data, size);
427
428 return true;
429 }
430
431 static void
432 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
433 unsigned count, const uint32_t *data)
434 {
435 struct radeon_cmdbuf *cs = cmd_buffer->cs;
436
437 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
438
439 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
440 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
441 S_370_WR_CONFIRM(1) |
442 S_370_ENGINE_SEL(V_370_ME));
443 radeon_emit(cs, va);
444 radeon_emit(cs, va >> 32);
445 radeon_emit_array(cs, data, count);
446 }
447
448 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
449 {
450 struct radv_device *device = cmd_buffer->device;
451 struct radeon_cmdbuf *cs = cmd_buffer->cs;
452 uint64_t va;
453
454 va = radv_buffer_get_va(device->trace_bo);
455 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
456 va += 4;
457
458 ++cmd_buffer->state.trace_id;
459 radv_emit_write_data_packet(cmd_buffer, va, 1,
460 &cmd_buffer->state.trace_id);
461
462 radeon_check_space(cmd_buffer->device->ws, cs, 2);
463
464 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
465 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
466 }
467
468 static void
469 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
470 enum radv_cmd_flush_bits flags)
471 {
472 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
473 uint32_t *ptr = NULL;
474 uint64_t va = 0;
475
476 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
477 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
478
479 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
480 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
481 cmd_buffer->gfx9_fence_offset;
482 ptr = &cmd_buffer->gfx9_fence_idx;
483 }
484
485 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
486
487 /* Force wait for graphics or compute engines to be idle. */
488 si_cs_emit_cache_flush(cmd_buffer->cs,
489 cmd_buffer->device->physical_device->rad_info.chip_class,
490 ptr, va,
491 radv_cmd_buffer_uses_mec(cmd_buffer),
492 flags, cmd_buffer->gfx9_eop_bug_va);
493 }
494
495 if (unlikely(cmd_buffer->device->trace_bo))
496 radv_cmd_buffer_trace_emit(cmd_buffer);
497 }
498
499 static void
500 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
501 struct radv_pipeline *pipeline, enum ring_type ring)
502 {
503 struct radv_device *device = cmd_buffer->device;
504 uint32_t data[2];
505 uint64_t va;
506
507 va = radv_buffer_get_va(device->trace_bo);
508
509 switch (ring) {
510 case RING_GFX:
511 va += 8;
512 break;
513 case RING_COMPUTE:
514 va += 16;
515 break;
516 default:
517 assert(!"invalid ring type");
518 }
519
520 data[0] = (uintptr_t)pipeline;
521 data[1] = (uintptr_t)pipeline >> 32;
522
523 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
524 }
525
526 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
527 VkPipelineBindPoint bind_point,
528 struct radv_descriptor_set *set,
529 unsigned idx)
530 {
531 struct radv_descriptor_state *descriptors_state =
532 radv_get_descriptors_state(cmd_buffer, bind_point);
533
534 descriptors_state->sets[idx] = set;
535
536 descriptors_state->valid |= (1u << idx); /* active descriptors */
537 descriptors_state->dirty |= (1u << idx);
538 }
539
540 static void
541 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
542 VkPipelineBindPoint bind_point)
543 {
544 struct radv_descriptor_state *descriptors_state =
545 radv_get_descriptors_state(cmd_buffer, bind_point);
546 struct radv_device *device = cmd_buffer->device;
547 uint32_t data[MAX_SETS * 2] = {};
548 uint64_t va;
549 unsigned i;
550 va = radv_buffer_get_va(device->trace_bo) + 24;
551
552 for_each_bit(i, descriptors_state->valid) {
553 struct radv_descriptor_set *set = descriptors_state->sets[i];
554 data[i * 2] = (uintptr_t)set;
555 data[i * 2 + 1] = (uintptr_t)set >> 32;
556 }
557
558 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
559 }
560
561 struct radv_userdata_info *
562 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
563 gl_shader_stage stage,
564 int idx)
565 {
566 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
567 return &shader->info.user_sgprs_locs.shader_data[idx];
568 }
569
570 static void
571 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
572 struct radv_pipeline *pipeline,
573 gl_shader_stage stage,
574 int idx, uint64_t va)
575 {
576 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
577 uint32_t base_reg = pipeline->user_data_0[stage];
578 if (loc->sgpr_idx == -1)
579 return;
580
581 assert(loc->num_sgprs == (HAVE_32BIT_POINTERS ? 1 : 2));
582 assert(!loc->indirect);
583
584 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
585 base_reg + loc->sgpr_idx * 4, va, false);
586 }
587
588 static void
589 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
590 struct radv_pipeline *pipeline,
591 struct radv_descriptor_state *descriptors_state,
592 gl_shader_stage stage)
593 {
594 struct radv_device *device = cmd_buffer->device;
595 struct radeon_cmdbuf *cs = cmd_buffer->cs;
596 uint32_t sh_base = pipeline->user_data_0[stage];
597 struct radv_userdata_locations *locs =
598 &pipeline->shaders[stage]->info.user_sgprs_locs;
599 unsigned mask = locs->descriptor_sets_enabled;
600
601 mask &= descriptors_state->dirty & descriptors_state->valid;
602
603 while (mask) {
604 int start, count;
605
606 u_bit_scan_consecutive_range(&mask, &start, &count);
607
608 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
609 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
610
611 radv_emit_shader_pointer_head(cs, sh_offset, count,
612 HAVE_32BIT_POINTERS);
613 for (int i = 0; i < count; i++) {
614 struct radv_descriptor_set *set =
615 descriptors_state->sets[start + i];
616
617 radv_emit_shader_pointer_body(device, cs, set->va,
618 HAVE_32BIT_POINTERS);
619 }
620 }
621 }
622
623 static void
624 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
625 struct radv_pipeline *pipeline)
626 {
627 int num_samples = pipeline->graphics.ms.num_samples;
628 struct radv_multisample_state *ms = &pipeline->graphics.ms;
629 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
630
631 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
632 cmd_buffer->sample_positions_needed = true;
633
634 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
635 return;
636
637 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
638 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
639 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
640
641 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
642
643 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
644
645 /* GFX9: Flush DFSM when the AA mode changes. */
646 if (cmd_buffer->device->dfsm_allowed) {
647 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
648 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
649 }
650 }
651
652 static void
653 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
654 struct radv_shader_variant *shader)
655 {
656 uint64_t va;
657
658 if (!shader)
659 return;
660
661 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
662
663 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
664 }
665
666 static void
667 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
668 struct radv_pipeline *pipeline,
669 bool vertex_stage_only)
670 {
671 struct radv_cmd_state *state = &cmd_buffer->state;
672 uint32_t mask = state->prefetch_L2_mask;
673
674 if (vertex_stage_only) {
675 /* Fast prefetch path for starting draws as soon as possible.
676 */
677 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
678 RADV_PREFETCH_VBO_DESCRIPTORS);
679 }
680
681 if (mask & RADV_PREFETCH_VS)
682 radv_emit_shader_prefetch(cmd_buffer,
683 pipeline->shaders[MESA_SHADER_VERTEX]);
684
685 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
686 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
687
688 if (mask & RADV_PREFETCH_TCS)
689 radv_emit_shader_prefetch(cmd_buffer,
690 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
691
692 if (mask & RADV_PREFETCH_TES)
693 radv_emit_shader_prefetch(cmd_buffer,
694 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
695
696 if (mask & RADV_PREFETCH_GS) {
697 radv_emit_shader_prefetch(cmd_buffer,
698 pipeline->shaders[MESA_SHADER_GEOMETRY]);
699 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
700 }
701
702 if (mask & RADV_PREFETCH_PS)
703 radv_emit_shader_prefetch(cmd_buffer,
704 pipeline->shaders[MESA_SHADER_FRAGMENT]);
705
706 state->prefetch_L2_mask &= ~mask;
707 }
708
709 static void
710 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
711 {
712 if (!cmd_buffer->device->physical_device->rbplus_allowed)
713 return;
714
715 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
716 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
717 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
718
719 unsigned sx_ps_downconvert = 0;
720 unsigned sx_blend_opt_epsilon = 0;
721 unsigned sx_blend_opt_control = 0;
722
723 for (unsigned i = 0; i < subpass->color_count; ++i) {
724 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
725 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
726 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
727 continue;
728 }
729
730 int idx = subpass->color_attachments[i].attachment;
731 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
732
733 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
734 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
735 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
736 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
737
738 bool has_alpha, has_rgb;
739
740 /* Set if RGB and A are present. */
741 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
742
743 if (format == V_028C70_COLOR_8 ||
744 format == V_028C70_COLOR_16 ||
745 format == V_028C70_COLOR_32)
746 has_rgb = !has_alpha;
747 else
748 has_rgb = true;
749
750 /* Check the colormask and export format. */
751 if (!(colormask & 0x7))
752 has_rgb = false;
753 if (!(colormask & 0x8))
754 has_alpha = false;
755
756 if (spi_format == V_028714_SPI_SHADER_ZERO) {
757 has_rgb = false;
758 has_alpha = false;
759 }
760
761 /* Disable value checking for disabled channels. */
762 if (!has_rgb)
763 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
764 if (!has_alpha)
765 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
766
767 /* Enable down-conversion for 32bpp and smaller formats. */
768 switch (format) {
769 case V_028C70_COLOR_8:
770 case V_028C70_COLOR_8_8:
771 case V_028C70_COLOR_8_8_8_8:
772 /* For 1 and 2-channel formats, use the superset thereof. */
773 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
774 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
775 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
776 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
777 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
778 }
779 break;
780
781 case V_028C70_COLOR_5_6_5:
782 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
783 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
784 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
785 }
786 break;
787
788 case V_028C70_COLOR_1_5_5_5:
789 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
790 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
791 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
792 }
793 break;
794
795 case V_028C70_COLOR_4_4_4_4:
796 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
797 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
798 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
799 }
800 break;
801
802 case V_028C70_COLOR_32:
803 if (swap == V_028C70_SWAP_STD &&
804 spi_format == V_028714_SPI_SHADER_32_R)
805 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
806 else if (swap == V_028C70_SWAP_ALT_REV &&
807 spi_format == V_028714_SPI_SHADER_32_AR)
808 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
809 break;
810
811 case V_028C70_COLOR_16:
812 case V_028C70_COLOR_16_16:
813 /* For 1-channel formats, use the superset thereof. */
814 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
815 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
816 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
817 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
818 if (swap == V_028C70_SWAP_STD ||
819 swap == V_028C70_SWAP_STD_REV)
820 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
821 else
822 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
823 }
824 break;
825
826 case V_028C70_COLOR_10_11_11:
827 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
828 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
829 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
830 }
831 break;
832
833 case V_028C70_COLOR_2_10_10_10:
834 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
835 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
836 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
837 }
838 break;
839 }
840 }
841
842 for (unsigned i = subpass->color_count; i < 8; ++i) {
843 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
844 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
845 }
846 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
847 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
848 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
849 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
850 }
851
852 static void
853 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
854 {
855 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
856
857 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
858 return;
859
860 radv_update_multisample_state(cmd_buffer, pipeline);
861
862 cmd_buffer->scratch_size_needed =
863 MAX2(cmd_buffer->scratch_size_needed,
864 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
865
866 if (!cmd_buffer->state.emitted_pipeline ||
867 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
868 pipeline->graphics.can_use_guardband)
869 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
870
871 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
872
873 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
874 if (!pipeline->shaders[i])
875 continue;
876
877 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
878 pipeline->shaders[i]->bo);
879 }
880
881 if (radv_pipeline_has_gs(pipeline))
882 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
883 pipeline->gs_copy_shader->bo);
884
885 if (unlikely(cmd_buffer->device->trace_bo))
886 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
887
888 cmd_buffer->state.emitted_pipeline = pipeline;
889
890 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
891 }
892
893 static void
894 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
895 {
896 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
897 cmd_buffer->state.dynamic.viewport.viewports);
898 }
899
900 static void
901 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
902 {
903 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
904
905 si_write_scissors(cmd_buffer->cs, 0, count,
906 cmd_buffer->state.dynamic.scissor.scissors,
907 cmd_buffer->state.dynamic.viewport.viewports,
908 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
909 }
910
911 static void
912 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
913 {
914 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
915 return;
916
917 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
918 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
919 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
920 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
921 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
922 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
923 S_028214_BR_Y(rect.offset.y + rect.extent.height));
924 }
925 }
926
927 static void
928 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
929 {
930 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
931
932 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
933 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
934 }
935
936 static void
937 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
938 {
939 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
940
941 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
942 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
943 }
944
945 static void
946 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
947 {
948 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
949
950 radeon_set_context_reg_seq(cmd_buffer->cs,
951 R_028430_DB_STENCILREFMASK, 2);
952 radeon_emit(cmd_buffer->cs,
953 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
954 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
955 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
956 S_028430_STENCILOPVAL(1));
957 radeon_emit(cmd_buffer->cs,
958 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
959 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
960 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
961 S_028434_STENCILOPVAL_BF(1));
962 }
963
964 static void
965 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
966 {
967 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
968
969 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
970 fui(d->depth_bounds.min));
971 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
972 fui(d->depth_bounds.max));
973 }
974
975 static void
976 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
977 {
978 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
979 unsigned slope = fui(d->depth_bias.slope * 16.0f);
980 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
981
982
983 radeon_set_context_reg_seq(cmd_buffer->cs,
984 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
985 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
986 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
987 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
988 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
989 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
990 }
991
992 static void
993 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
994 int index,
995 struct radv_attachment_info *att,
996 struct radv_image *image,
997 VkImageLayout layout)
998 {
999 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1000 struct radv_color_buffer_info *cb = &att->cb;
1001 uint32_t cb_color_info = cb->cb_color_info;
1002
1003 if (!radv_layout_dcc_compressed(image, layout,
1004 radv_image_queue_family_mask(image,
1005 cmd_buffer->queue_family_index,
1006 cmd_buffer->queue_family_index))) {
1007 cb_color_info &= C_028C70_DCC_ENABLE;
1008 }
1009
1010 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1011 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1012 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1013 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1014 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1015 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1016 radeon_emit(cmd_buffer->cs, cb_color_info);
1017 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1018 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1019 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1020 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1021 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1022 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1023
1024 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1025 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1026 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1027
1028 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1029 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1030 } else {
1031 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1032 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1033 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1034 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1035 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1036 radeon_emit(cmd_buffer->cs, cb_color_info);
1037 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1038 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1039 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1040 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1041 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1042 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1043
1044 if (is_vi) { /* DCC BASE */
1045 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1046 }
1047 }
1048 }
1049
1050 static void
1051 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1052 struct radv_ds_buffer_info *ds,
1053 struct radv_image *image, VkImageLayout layout,
1054 bool requires_cond_write)
1055 {
1056 uint32_t db_z_info = ds->db_z_info;
1057 uint32_t db_z_info_reg;
1058
1059 if (!radv_image_is_tc_compat_htile(image))
1060 return;
1061
1062 if (!radv_layout_has_htile(image, layout,
1063 radv_image_queue_family_mask(image,
1064 cmd_buffer->queue_family_index,
1065 cmd_buffer->queue_family_index))) {
1066 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1067 }
1068
1069 db_z_info &= C_028040_ZRANGE_PRECISION;
1070
1071 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1072 db_z_info_reg = R_028038_DB_Z_INFO;
1073 } else {
1074 db_z_info_reg = R_028040_DB_Z_INFO;
1075 }
1076
1077 /* When we don't know the last fast clear value we need to emit a
1078 * conditional packet, otherwise we can update DB_Z_INFO directly.
1079 */
1080 if (requires_cond_write) {
1081 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_WRITE, 7, 0));
1082
1083 const uint32_t write_space = 0 << 8; /* register */
1084 const uint32_t poll_space = 1 << 4; /* memory */
1085 const uint32_t function = 3 << 0; /* equal to the reference */
1086 const uint32_t options = write_space | poll_space | function;
1087 radeon_emit(cmd_buffer->cs, options);
1088
1089 /* poll address - location of the depth clear value */
1090 uint64_t va = radv_buffer_get_va(image->bo);
1091 va += image->offset + image->clear_value_offset;
1092
1093 /* In presence of stencil format, we have to adjust the base
1094 * address because the first value is the stencil clear value.
1095 */
1096 if (vk_format_is_stencil(image->vk_format))
1097 va += 4;
1098
1099 radeon_emit(cmd_buffer->cs, va);
1100 radeon_emit(cmd_buffer->cs, va >> 32);
1101
1102 radeon_emit(cmd_buffer->cs, fui(0.0f)); /* reference value */
1103 radeon_emit(cmd_buffer->cs, (uint32_t)-1); /* comparison mask */
1104 radeon_emit(cmd_buffer->cs, db_z_info_reg >> 2); /* write address low */
1105 radeon_emit(cmd_buffer->cs, 0u); /* write address high */
1106 radeon_emit(cmd_buffer->cs, db_z_info);
1107 } else {
1108 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1109 }
1110 }
1111
1112 static void
1113 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1114 struct radv_ds_buffer_info *ds,
1115 struct radv_image *image,
1116 VkImageLayout layout)
1117 {
1118 uint32_t db_z_info = ds->db_z_info;
1119 uint32_t db_stencil_info = ds->db_stencil_info;
1120
1121 if (!radv_layout_has_htile(image, layout,
1122 radv_image_queue_family_mask(image,
1123 cmd_buffer->queue_family_index,
1124 cmd_buffer->queue_family_index))) {
1125 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1126 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1127 }
1128
1129 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1130 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1131
1132
1133 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1134 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1135 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1136 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1137 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1138
1139 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1140 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1141 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1142 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1143 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1144 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1145 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1146 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1147 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1148 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1149 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1150
1151 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1152 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1153 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1154 } else {
1155 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1156
1157 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1158 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1159 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1160 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1161 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1162 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1163 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1164 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1165 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1166 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1167
1168 }
1169
1170 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1171 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1172
1173 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1174 ds->pa_su_poly_offset_db_fmt_cntl);
1175 }
1176
1177 /**
1178 * Update the fast clear depth/stencil values if the image is bound as a
1179 * depth/stencil buffer.
1180 */
1181 static void
1182 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1183 struct radv_image *image,
1184 VkClearDepthStencilValue ds_clear_value,
1185 VkImageAspectFlags aspects)
1186 {
1187 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1188 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1189 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1190 struct radv_attachment_info *att;
1191 uint32_t att_idx;
1192
1193 if (!framebuffer || !subpass)
1194 return;
1195
1196 att_idx = subpass->depth_stencil_attachment.attachment;
1197 if (att_idx == VK_ATTACHMENT_UNUSED)
1198 return;
1199
1200 att = &framebuffer->attachments[att_idx];
1201 if (att->attachment->image != image)
1202 return;
1203
1204 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1205 radeon_emit(cs, ds_clear_value.stencil);
1206 radeon_emit(cs, fui(ds_clear_value.depth));
1207
1208 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1209 * only needed when clearing Z to 0.0.
1210 */
1211 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1212 ds_clear_value.depth == 0.0) {
1213 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1214
1215 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1216 layout, false);
1217 }
1218 }
1219
1220 /**
1221 * Set the clear depth/stencil values to the image's metadata.
1222 */
1223 static void
1224 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1225 struct radv_image *image,
1226 VkClearDepthStencilValue ds_clear_value,
1227 VkImageAspectFlags aspects)
1228 {
1229 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1230 uint64_t va = radv_buffer_get_va(image->bo);
1231 unsigned reg_offset = 0, reg_count = 0;
1232
1233 va += image->offset + image->clear_value_offset;
1234
1235 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1236 ++reg_count;
1237 } else {
1238 ++reg_offset;
1239 va += 4;
1240 }
1241 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1242 ++reg_count;
1243
1244 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1245 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1246 S_370_WR_CONFIRM(1) |
1247 S_370_ENGINE_SEL(V_370_PFP));
1248 radeon_emit(cs, va);
1249 radeon_emit(cs, va >> 32);
1250 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1251 radeon_emit(cs, ds_clear_value.stencil);
1252 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1253 radeon_emit(cs, fui(ds_clear_value.depth));
1254 }
1255
1256 /**
1257 * Update the clear depth/stencil values for this image.
1258 */
1259 void
1260 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1261 struct radv_image *image,
1262 VkClearDepthStencilValue ds_clear_value,
1263 VkImageAspectFlags aspects)
1264 {
1265 assert(radv_image_has_htile(image));
1266
1267 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1268
1269 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1270 aspects);
1271 }
1272
1273 /**
1274 * Load the clear depth/stencil values from the image's metadata.
1275 */
1276 static void
1277 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1278 struct radv_image *image)
1279 {
1280 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1281 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1282 uint64_t va = radv_buffer_get_va(image->bo);
1283 unsigned reg_offset = 0, reg_count = 0;
1284
1285 va += image->offset + image->clear_value_offset;
1286
1287 if (!radv_image_has_htile(image))
1288 return;
1289
1290 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1291 ++reg_count;
1292 } else {
1293 ++reg_offset;
1294 va += 4;
1295 }
1296 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1297 ++reg_count;
1298
1299 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1300 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1301 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1302 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1303 radeon_emit(cs, va);
1304 radeon_emit(cs, va >> 32);
1305 radeon_emit(cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
1306 radeon_emit(cs, 0);
1307
1308 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1309 radeon_emit(cs, 0);
1310 }
1311
1312 /*
1313 * With DCC some colors don't require CMASK elimination before being
1314 * used as a texture. This sets a predicate value to determine if the
1315 * cmask eliminate is required.
1316 */
1317 void
1318 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1319 struct radv_image *image,
1320 bool value)
1321 {
1322 uint64_t pred_val = value;
1323 uint64_t va = radv_buffer_get_va(image->bo);
1324 va += image->offset + image->dcc_pred_offset;
1325
1326 assert(radv_image_has_dcc(image));
1327
1328 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1329 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1330 S_370_WR_CONFIRM(1) |
1331 S_370_ENGINE_SEL(V_370_PFP));
1332 radeon_emit(cmd_buffer->cs, va);
1333 radeon_emit(cmd_buffer->cs, va >> 32);
1334 radeon_emit(cmd_buffer->cs, pred_val);
1335 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1336 }
1337
1338 /**
1339 * Update the fast clear color values if the image is bound as a color buffer.
1340 */
1341 static void
1342 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1343 struct radv_image *image,
1344 int cb_idx,
1345 uint32_t color_values[2])
1346 {
1347 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1348 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1349 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1350 struct radv_attachment_info *att;
1351 uint32_t att_idx;
1352
1353 if (!framebuffer || !subpass)
1354 return;
1355
1356 att_idx = subpass->color_attachments[cb_idx].attachment;
1357 if (att_idx == VK_ATTACHMENT_UNUSED)
1358 return;
1359
1360 att = &framebuffer->attachments[att_idx];
1361 if (att->attachment->image != image)
1362 return;
1363
1364 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1365 radeon_emit(cs, color_values[0]);
1366 radeon_emit(cs, color_values[1]);
1367 }
1368
1369 /**
1370 * Set the clear color values to the image's metadata.
1371 */
1372 static void
1373 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1374 struct radv_image *image,
1375 uint32_t color_values[2])
1376 {
1377 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1378 uint64_t va = radv_buffer_get_va(image->bo);
1379
1380 va += image->offset + image->clear_value_offset;
1381
1382 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1383
1384 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1385 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1386 S_370_WR_CONFIRM(1) |
1387 S_370_ENGINE_SEL(V_370_PFP));
1388 radeon_emit(cs, va);
1389 radeon_emit(cs, va >> 32);
1390 radeon_emit(cs, color_values[0]);
1391 radeon_emit(cs, color_values[1]);
1392 }
1393
1394 /**
1395 * Update the clear color values for this image.
1396 */
1397 void
1398 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1399 struct radv_image *image,
1400 int cb_idx,
1401 uint32_t color_values[2])
1402 {
1403 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1404
1405 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
1406
1407 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1408 color_values);
1409 }
1410
1411 /**
1412 * Load the clear color values from the image's metadata.
1413 */
1414 static void
1415 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1416 struct radv_image *image,
1417 int cb_idx)
1418 {
1419 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1420 uint64_t va = radv_buffer_get_va(image->bo);
1421
1422 va += image->offset + image->clear_value_offset;
1423
1424 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1425 return;
1426
1427 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1428
1429 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1430 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1431 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1432 COPY_DATA_COUNT_SEL);
1433 radeon_emit(cs, va);
1434 radeon_emit(cs, va >> 32);
1435 radeon_emit(cs, reg >> 2);
1436 radeon_emit(cs, 0);
1437
1438 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1439 radeon_emit(cs, 0);
1440 }
1441
1442 static void
1443 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1444 {
1445 int i;
1446 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1447 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1448
1449 /* this may happen for inherited secondary recording */
1450 if (!framebuffer)
1451 return;
1452
1453 for (i = 0; i < 8; ++i) {
1454 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1455 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1456 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1457 continue;
1458 }
1459
1460 int idx = subpass->color_attachments[i].attachment;
1461 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1462 struct radv_image *image = att->attachment->image;
1463 VkImageLayout layout = subpass->color_attachments[i].layout;
1464
1465 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1466
1467 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1468 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1469
1470 radv_load_color_clear_metadata(cmd_buffer, image, i);
1471 }
1472
1473 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1474 int idx = subpass->depth_stencil_attachment.attachment;
1475 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1476 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1477 struct radv_image *image = att->attachment->image;
1478 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1479 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1480 cmd_buffer->queue_family_index,
1481 cmd_buffer->queue_family_index);
1482 /* We currently don't support writing decompressed HTILE */
1483 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1484 radv_layout_is_htile_compressed(image, layout, queue_mask));
1485
1486 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1487
1488 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1489 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1490 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1491 }
1492 radv_load_ds_clear_metadata(cmd_buffer, image);
1493 } else {
1494 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1495 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1496 else
1497 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1498
1499 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1500 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1501 }
1502 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1503 S_028208_BR_X(framebuffer->width) |
1504 S_028208_BR_Y(framebuffer->height));
1505
1506 if (cmd_buffer->device->dfsm_allowed) {
1507 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1508 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1509 }
1510
1511 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1512 }
1513
1514 static void
1515 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1516 {
1517 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1518 struct radv_cmd_state *state = &cmd_buffer->state;
1519
1520 if (state->index_type != state->last_index_type) {
1521 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1522 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1523 2, state->index_type);
1524 } else {
1525 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1526 radeon_emit(cs, state->index_type);
1527 }
1528
1529 state->last_index_type = state->index_type;
1530 }
1531
1532 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1533 radeon_emit(cs, state->index_va);
1534 radeon_emit(cs, state->index_va >> 32);
1535
1536 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1537 radeon_emit(cs, state->max_index_count);
1538
1539 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1540 }
1541
1542 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1543 {
1544 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1545 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1546 uint32_t pa_sc_mode_cntl_1 =
1547 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1548 uint32_t db_count_control;
1549
1550 if(!cmd_buffer->state.active_occlusion_queries) {
1551 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1552 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1553 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1554 has_perfect_queries) {
1555 /* Re-enable out-of-order rasterization if the
1556 * bound pipeline supports it and if it's has
1557 * been disabled before starting any perfect
1558 * occlusion queries.
1559 */
1560 radeon_set_context_reg(cmd_buffer->cs,
1561 R_028A4C_PA_SC_MODE_CNTL_1,
1562 pa_sc_mode_cntl_1);
1563 }
1564 }
1565 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1566 } else {
1567 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1568 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1569
1570 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1571 db_count_control =
1572 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1573 S_028004_SAMPLE_RATE(sample_rate) |
1574 S_028004_ZPASS_ENABLE(1) |
1575 S_028004_SLICE_EVEN_ENABLE(1) |
1576 S_028004_SLICE_ODD_ENABLE(1);
1577
1578 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1579 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1580 has_perfect_queries) {
1581 /* If the bound pipeline has enabled
1582 * out-of-order rasterization, we should
1583 * disable it before starting any perfect
1584 * occlusion queries.
1585 */
1586 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1587
1588 radeon_set_context_reg(cmd_buffer->cs,
1589 R_028A4C_PA_SC_MODE_CNTL_1,
1590 pa_sc_mode_cntl_1);
1591 }
1592 } else {
1593 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1594 S_028004_SAMPLE_RATE(sample_rate);
1595 }
1596 }
1597
1598 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1599 }
1600
1601 static void
1602 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1603 {
1604 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1605
1606 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1607 radv_emit_viewport(cmd_buffer);
1608
1609 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1610 !cmd_buffer->device->physical_device->has_scissor_bug)
1611 radv_emit_scissor(cmd_buffer);
1612
1613 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1614 radv_emit_line_width(cmd_buffer);
1615
1616 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1617 radv_emit_blend_constants(cmd_buffer);
1618
1619 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1620 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1621 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1622 radv_emit_stencil(cmd_buffer);
1623
1624 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1625 radv_emit_depth_bounds(cmd_buffer);
1626
1627 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1628 radv_emit_depth_bias(cmd_buffer);
1629
1630 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1631 radv_emit_discard_rectangle(cmd_buffer);
1632
1633 cmd_buffer->state.dirty &= ~states;
1634 }
1635
1636 static void
1637 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1638 VkPipelineBindPoint bind_point)
1639 {
1640 struct radv_descriptor_state *descriptors_state =
1641 radv_get_descriptors_state(cmd_buffer, bind_point);
1642 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1643 unsigned bo_offset;
1644
1645 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1646 set->mapped_ptr,
1647 &bo_offset))
1648 return;
1649
1650 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1651 set->va += bo_offset;
1652 }
1653
1654 static void
1655 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1656 VkPipelineBindPoint bind_point)
1657 {
1658 struct radv_descriptor_state *descriptors_state =
1659 radv_get_descriptors_state(cmd_buffer, bind_point);
1660 uint8_t ptr_size = HAVE_32BIT_POINTERS ? 1 : 2;
1661 uint32_t size = MAX_SETS * 4 * ptr_size;
1662 uint32_t offset;
1663 void *ptr;
1664
1665 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1666 256, &offset, &ptr))
1667 return;
1668
1669 for (unsigned i = 0; i < MAX_SETS; i++) {
1670 uint32_t *uptr = ((uint32_t *)ptr) + i * ptr_size;
1671 uint64_t set_va = 0;
1672 struct radv_descriptor_set *set = descriptors_state->sets[i];
1673 if (descriptors_state->valid & (1u << i))
1674 set_va = set->va;
1675 uptr[0] = set_va & 0xffffffff;
1676 if (ptr_size == 2)
1677 uptr[1] = set_va >> 32;
1678 }
1679
1680 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1681 va += offset;
1682
1683 if (cmd_buffer->state.pipeline) {
1684 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1685 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1686 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1687
1688 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1689 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1690 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1691
1692 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1693 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1694 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1695
1696 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1697 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1698 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1699
1700 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1701 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1702 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1703 }
1704
1705 if (cmd_buffer->state.compute_pipeline)
1706 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1707 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1708 }
1709
1710 static void
1711 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1712 VkShaderStageFlags stages)
1713 {
1714 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1715 VK_PIPELINE_BIND_POINT_COMPUTE :
1716 VK_PIPELINE_BIND_POINT_GRAPHICS;
1717 struct radv_descriptor_state *descriptors_state =
1718 radv_get_descriptors_state(cmd_buffer, bind_point);
1719 struct radv_cmd_state *state = &cmd_buffer->state;
1720 bool flush_indirect_descriptors;
1721
1722 if (!descriptors_state->dirty)
1723 return;
1724
1725 if (descriptors_state->push_dirty)
1726 radv_flush_push_descriptors(cmd_buffer, bind_point);
1727
1728 flush_indirect_descriptors =
1729 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
1730 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
1731 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
1732 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
1733
1734 if (flush_indirect_descriptors)
1735 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1736
1737 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1738 cmd_buffer->cs,
1739 MAX_SETS * MESA_SHADER_STAGES * 4);
1740
1741 if (cmd_buffer->state.pipeline) {
1742 radv_foreach_stage(stage, stages) {
1743 if (!cmd_buffer->state.pipeline->shaders[stage])
1744 continue;
1745
1746 radv_emit_descriptor_pointers(cmd_buffer,
1747 cmd_buffer->state.pipeline,
1748 descriptors_state, stage);
1749 }
1750 }
1751
1752 if (cmd_buffer->state.compute_pipeline &&
1753 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
1754 radv_emit_descriptor_pointers(cmd_buffer,
1755 cmd_buffer->state.compute_pipeline,
1756 descriptors_state,
1757 MESA_SHADER_COMPUTE);
1758 }
1759
1760 descriptors_state->dirty = 0;
1761 descriptors_state->push_dirty = false;
1762
1763 assert(cmd_buffer->cs->cdw <= cdw_max);
1764
1765 if (unlikely(cmd_buffer->device->trace_bo))
1766 radv_save_descriptors(cmd_buffer, bind_point);
1767 }
1768
1769 static void
1770 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1771 VkShaderStageFlags stages)
1772 {
1773 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1774 ? cmd_buffer->state.compute_pipeline
1775 : cmd_buffer->state.pipeline;
1776 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1777 VK_PIPELINE_BIND_POINT_COMPUTE :
1778 VK_PIPELINE_BIND_POINT_GRAPHICS;
1779 struct radv_descriptor_state *descriptors_state =
1780 radv_get_descriptors_state(cmd_buffer, bind_point);
1781 struct radv_pipeline_layout *layout = pipeline->layout;
1782 struct radv_shader_variant *shader, *prev_shader;
1783 unsigned offset;
1784 void *ptr;
1785 uint64_t va;
1786
1787 stages &= cmd_buffer->push_constant_stages;
1788 if (!stages ||
1789 (!layout->push_constant_size && !layout->dynamic_offset_count))
1790 return;
1791
1792 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1793 16 * layout->dynamic_offset_count,
1794 256, &offset, &ptr))
1795 return;
1796
1797 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1798 memcpy((char*)ptr + layout->push_constant_size,
1799 descriptors_state->dynamic_buffers,
1800 16 * layout->dynamic_offset_count);
1801
1802 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1803 va += offset;
1804
1805 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1806 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1807
1808 prev_shader = NULL;
1809 radv_foreach_stage(stage, stages) {
1810 shader = radv_get_shader(pipeline, stage);
1811
1812 /* Avoid redundantly emitting the address for merged stages. */
1813 if (shader && shader != prev_shader) {
1814 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1815 AC_UD_PUSH_CONSTANTS, va);
1816
1817 prev_shader = shader;
1818 }
1819 }
1820
1821 cmd_buffer->push_constant_stages &= ~stages;
1822 assert(cmd_buffer->cs->cdw <= cdw_max);
1823 }
1824
1825 static void
1826 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1827 bool pipeline_is_dirty)
1828 {
1829 if ((pipeline_is_dirty ||
1830 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1831 cmd_buffer->state.pipeline->vertex_elements.count &&
1832 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
1833 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1834 unsigned vb_offset;
1835 void *vb_ptr;
1836 uint32_t i = 0;
1837 uint32_t count = velems->count;
1838 uint64_t va;
1839
1840 /* allocate some descriptor state for vertex buffers */
1841 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1842 &vb_offset, &vb_ptr))
1843 return;
1844
1845 for (i = 0; i < count; i++) {
1846 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1847 uint32_t offset;
1848 int vb = velems->binding[i];
1849 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1850 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1851
1852 va = radv_buffer_get_va(buffer->bo);
1853
1854 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1855 va += offset + buffer->offset;
1856 desc[0] = va;
1857 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1858 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1859 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1860 else
1861 desc[2] = buffer->size - offset;
1862 desc[3] = velems->rsrc_word3[i];
1863 }
1864
1865 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1866 va += vb_offset;
1867
1868 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1869 AC_UD_VS_VERTEX_BUFFERS, va);
1870
1871 cmd_buffer->state.vb_va = va;
1872 cmd_buffer->state.vb_size = count * 16;
1873 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
1874 }
1875 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1876 }
1877
1878 static void
1879 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1880 {
1881 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
1882 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1883 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1884 }
1885
1886 static void
1887 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1888 bool instanced_draw, bool indirect_draw,
1889 uint32_t draw_vertex_count)
1890 {
1891 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1892 struct radv_cmd_state *state = &cmd_buffer->state;
1893 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1894 uint32_t ia_multi_vgt_param;
1895 int32_t primitive_reset_en;
1896
1897 /* Draw state. */
1898 ia_multi_vgt_param =
1899 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1900 indirect_draw, draw_vertex_count);
1901
1902 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1903 if (info->chip_class >= GFX9) {
1904 radeon_set_uconfig_reg_idx(cs,
1905 R_030960_IA_MULTI_VGT_PARAM,
1906 4, ia_multi_vgt_param);
1907 } else if (info->chip_class >= CIK) {
1908 radeon_set_context_reg_idx(cs,
1909 R_028AA8_IA_MULTI_VGT_PARAM,
1910 1, ia_multi_vgt_param);
1911 } else {
1912 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1913 ia_multi_vgt_param);
1914 }
1915 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1916 }
1917
1918 /* Primitive restart. */
1919 primitive_reset_en =
1920 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1921
1922 if (primitive_reset_en != state->last_primitive_reset_en) {
1923 state->last_primitive_reset_en = primitive_reset_en;
1924 if (info->chip_class >= GFX9) {
1925 radeon_set_uconfig_reg(cs,
1926 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1927 primitive_reset_en);
1928 } else {
1929 radeon_set_context_reg(cs,
1930 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1931 primitive_reset_en);
1932 }
1933 }
1934
1935 if (primitive_reset_en) {
1936 uint32_t primitive_reset_index =
1937 state->index_type ? 0xffffffffu : 0xffffu;
1938
1939 if (primitive_reset_index != state->last_primitive_reset_index) {
1940 radeon_set_context_reg(cs,
1941 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1942 primitive_reset_index);
1943 state->last_primitive_reset_index = primitive_reset_index;
1944 }
1945 }
1946 }
1947
1948 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1949 VkPipelineStageFlags src_stage_mask)
1950 {
1951 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1952 VK_PIPELINE_STAGE_TRANSFER_BIT |
1953 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1954 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1955 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1956 }
1957
1958 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1959 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1960 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1961 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1962 VK_PIPELINE_STAGE_TRANSFER_BIT |
1963 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1964 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1965 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1966 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1967 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1968 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1969 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
1970 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1971 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1972 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT)) {
1973 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1974 }
1975 }
1976
1977 static enum radv_cmd_flush_bits
1978 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1979 VkAccessFlags src_flags,
1980 struct radv_image *image)
1981 {
1982 bool flush_CB_meta = true, flush_DB_meta = true;
1983 enum radv_cmd_flush_bits flush_bits = 0;
1984 uint32_t b;
1985
1986 if (image) {
1987 if (!radv_image_has_CB_metadata(image))
1988 flush_CB_meta = false;
1989 if (!radv_image_has_htile(image))
1990 flush_DB_meta = false;
1991 }
1992
1993 for_each_bit(b, src_flags) {
1994 switch ((VkAccessFlagBits)(1 << b)) {
1995 case VK_ACCESS_SHADER_WRITE_BIT:
1996 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1997 break;
1998 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1999 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2000 if (flush_CB_meta)
2001 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2002 break;
2003 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2004 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2005 if (flush_DB_meta)
2006 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2007 break;
2008 case VK_ACCESS_TRANSFER_WRITE_BIT:
2009 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2010 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2011 RADV_CMD_FLAG_INV_GLOBAL_L2;
2012
2013 if (flush_CB_meta)
2014 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2015 if (flush_DB_meta)
2016 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2017 break;
2018 default:
2019 break;
2020 }
2021 }
2022 return flush_bits;
2023 }
2024
2025 static enum radv_cmd_flush_bits
2026 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2027 VkAccessFlags dst_flags,
2028 struct radv_image *image)
2029 {
2030 bool flush_CB_meta = true, flush_DB_meta = true;
2031 enum radv_cmd_flush_bits flush_bits = 0;
2032 bool flush_CB = true, flush_DB = true;
2033 bool image_is_coherent = false;
2034 uint32_t b;
2035
2036 if (image) {
2037 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2038 flush_CB = false;
2039 flush_DB = false;
2040 }
2041
2042 if (!radv_image_has_CB_metadata(image))
2043 flush_CB_meta = false;
2044 if (!radv_image_has_htile(image))
2045 flush_DB_meta = false;
2046
2047 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2048 if (image->info.samples == 1 &&
2049 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2050 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2051 !vk_format_is_stencil(image->vk_format)) {
2052 /* Single-sample color and single-sample depth
2053 * (not stencil) are coherent with shaders on
2054 * GFX9.
2055 */
2056 image_is_coherent = true;
2057 }
2058 }
2059 }
2060
2061 for_each_bit(b, dst_flags) {
2062 switch ((VkAccessFlagBits)(1 << b)) {
2063 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2064 case VK_ACCESS_INDEX_READ_BIT:
2065 break;
2066 case VK_ACCESS_UNIFORM_READ_BIT:
2067 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2068 break;
2069 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2070 case VK_ACCESS_TRANSFER_READ_BIT:
2071 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2072 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2073 RADV_CMD_FLAG_INV_GLOBAL_L2;
2074 break;
2075 case VK_ACCESS_SHADER_READ_BIT:
2076 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2077
2078 if (!image_is_coherent)
2079 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2080 break;
2081 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2082 if (flush_CB)
2083 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2084 if (flush_CB_meta)
2085 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2086 break;
2087 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2088 if (flush_DB)
2089 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2090 if (flush_DB_meta)
2091 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2092 break;
2093 default:
2094 break;
2095 }
2096 }
2097 return flush_bits;
2098 }
2099
2100 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2101 const struct radv_subpass_barrier *barrier)
2102 {
2103 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2104 NULL);
2105 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2106 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2107 NULL);
2108 }
2109
2110 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2111 struct radv_subpass_attachment att)
2112 {
2113 unsigned idx = att.attachment;
2114 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2115 VkImageSubresourceRange range;
2116 range.aspectMask = 0;
2117 range.baseMipLevel = view->base_mip;
2118 range.levelCount = 1;
2119 range.baseArrayLayer = view->base_layer;
2120 range.layerCount = cmd_buffer->state.framebuffer->layers;
2121
2122 radv_handle_image_transition(cmd_buffer,
2123 view->image,
2124 cmd_buffer->state.attachments[idx].current_layout,
2125 att.layout, 0, 0, &range,
2126 cmd_buffer->state.attachments[idx].pending_clear_aspects);
2127
2128 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2129
2130
2131 }
2132
2133 void
2134 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2135 const struct radv_subpass *subpass, bool transitions)
2136 {
2137 if (transitions) {
2138 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2139
2140 for (unsigned i = 0; i < subpass->color_count; ++i) {
2141 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2142 radv_handle_subpass_image_transition(cmd_buffer,
2143 subpass->color_attachments[i]);
2144 }
2145
2146 for (unsigned i = 0; i < subpass->input_count; ++i) {
2147 radv_handle_subpass_image_transition(cmd_buffer,
2148 subpass->input_attachments[i]);
2149 }
2150
2151 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2152 radv_handle_subpass_image_transition(cmd_buffer,
2153 subpass->depth_stencil_attachment);
2154 }
2155 }
2156
2157 cmd_buffer->state.subpass = subpass;
2158
2159 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2160 }
2161
2162 static VkResult
2163 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2164 struct radv_render_pass *pass,
2165 const VkRenderPassBeginInfo *info)
2166 {
2167 struct radv_cmd_state *state = &cmd_buffer->state;
2168
2169 if (pass->attachment_count == 0) {
2170 state->attachments = NULL;
2171 return VK_SUCCESS;
2172 }
2173
2174 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2175 pass->attachment_count *
2176 sizeof(state->attachments[0]),
2177 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2178 if (state->attachments == NULL) {
2179 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2180 return cmd_buffer->record_result;
2181 }
2182
2183 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2184 struct radv_render_pass_attachment *att = &pass->attachments[i];
2185 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2186 VkImageAspectFlags clear_aspects = 0;
2187
2188 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2189 /* color attachment */
2190 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2191 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2192 }
2193 } else {
2194 /* depthstencil attachment */
2195 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2196 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2197 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2198 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2199 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2200 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2201 }
2202 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2203 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2204 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2205 }
2206 }
2207
2208 state->attachments[i].pending_clear_aspects = clear_aspects;
2209 state->attachments[i].cleared_views = 0;
2210 if (clear_aspects && info) {
2211 assert(info->clearValueCount > i);
2212 state->attachments[i].clear_value = info->pClearValues[i];
2213 }
2214
2215 state->attachments[i].current_layout = att->initial_layout;
2216 }
2217
2218 return VK_SUCCESS;
2219 }
2220
2221 VkResult radv_AllocateCommandBuffers(
2222 VkDevice _device,
2223 const VkCommandBufferAllocateInfo *pAllocateInfo,
2224 VkCommandBuffer *pCommandBuffers)
2225 {
2226 RADV_FROM_HANDLE(radv_device, device, _device);
2227 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2228
2229 VkResult result = VK_SUCCESS;
2230 uint32_t i;
2231
2232 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2233
2234 if (!list_empty(&pool->free_cmd_buffers)) {
2235 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2236
2237 list_del(&cmd_buffer->pool_link);
2238 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2239
2240 result = radv_reset_cmd_buffer(cmd_buffer);
2241 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2242 cmd_buffer->level = pAllocateInfo->level;
2243
2244 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2245 } else {
2246 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2247 &pCommandBuffers[i]);
2248 }
2249 if (result != VK_SUCCESS)
2250 break;
2251 }
2252
2253 if (result != VK_SUCCESS) {
2254 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2255 i, pCommandBuffers);
2256
2257 /* From the Vulkan 1.0.66 spec:
2258 *
2259 * "vkAllocateCommandBuffers can be used to create multiple
2260 * command buffers. If the creation of any of those command
2261 * buffers fails, the implementation must destroy all
2262 * successfully created command buffer objects from this
2263 * command, set all entries of the pCommandBuffers array to
2264 * NULL and return the error."
2265 */
2266 memset(pCommandBuffers, 0,
2267 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2268 }
2269
2270 return result;
2271 }
2272
2273 void radv_FreeCommandBuffers(
2274 VkDevice device,
2275 VkCommandPool commandPool,
2276 uint32_t commandBufferCount,
2277 const VkCommandBuffer *pCommandBuffers)
2278 {
2279 for (uint32_t i = 0; i < commandBufferCount; i++) {
2280 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2281
2282 if (cmd_buffer) {
2283 if (cmd_buffer->pool) {
2284 list_del(&cmd_buffer->pool_link);
2285 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2286 } else
2287 radv_cmd_buffer_destroy(cmd_buffer);
2288
2289 }
2290 }
2291 }
2292
2293 VkResult radv_ResetCommandBuffer(
2294 VkCommandBuffer commandBuffer,
2295 VkCommandBufferResetFlags flags)
2296 {
2297 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2298 return radv_reset_cmd_buffer(cmd_buffer);
2299 }
2300
2301 VkResult radv_BeginCommandBuffer(
2302 VkCommandBuffer commandBuffer,
2303 const VkCommandBufferBeginInfo *pBeginInfo)
2304 {
2305 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2306 VkResult result = VK_SUCCESS;
2307
2308 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2309 /* If the command buffer has already been resetted with
2310 * vkResetCommandBuffer, no need to do it again.
2311 */
2312 result = radv_reset_cmd_buffer(cmd_buffer);
2313 if (result != VK_SUCCESS)
2314 return result;
2315 }
2316
2317 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2318 cmd_buffer->state.last_primitive_reset_en = -1;
2319 cmd_buffer->state.last_index_type = -1;
2320 cmd_buffer->state.last_num_instances = -1;
2321 cmd_buffer->state.last_vertex_offset = -1;
2322 cmd_buffer->state.last_first_instance = -1;
2323 cmd_buffer->state.predication_type = -1;
2324 cmd_buffer->usage_flags = pBeginInfo->flags;
2325
2326 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
2327 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
2328 assert(pBeginInfo->pInheritanceInfo);
2329 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2330 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2331
2332 struct radv_subpass *subpass =
2333 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2334
2335 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2336 if (result != VK_SUCCESS)
2337 return result;
2338
2339 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2340 }
2341
2342 if (unlikely(cmd_buffer->device->trace_bo)) {
2343 struct radv_device *device = cmd_buffer->device;
2344
2345 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
2346 device->trace_bo);
2347
2348 radv_cmd_buffer_trace_emit(cmd_buffer);
2349 }
2350
2351 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2352
2353 return result;
2354 }
2355
2356 void radv_CmdBindVertexBuffers(
2357 VkCommandBuffer commandBuffer,
2358 uint32_t firstBinding,
2359 uint32_t bindingCount,
2360 const VkBuffer* pBuffers,
2361 const VkDeviceSize* pOffsets)
2362 {
2363 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2364 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2365 bool changed = false;
2366
2367 /* We have to defer setting up vertex buffer since we need the buffer
2368 * stride from the pipeline. */
2369
2370 assert(firstBinding + bindingCount <= MAX_VBS);
2371 for (uint32_t i = 0; i < bindingCount; i++) {
2372 uint32_t idx = firstBinding + i;
2373
2374 if (!changed &&
2375 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2376 vb[idx].offset != pOffsets[i])) {
2377 changed = true;
2378 }
2379
2380 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2381 vb[idx].offset = pOffsets[i];
2382
2383 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2384 vb[idx].buffer->bo);
2385 }
2386
2387 if (!changed) {
2388 /* No state changes. */
2389 return;
2390 }
2391
2392 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2393 }
2394
2395 void radv_CmdBindIndexBuffer(
2396 VkCommandBuffer commandBuffer,
2397 VkBuffer buffer,
2398 VkDeviceSize offset,
2399 VkIndexType indexType)
2400 {
2401 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2402 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2403
2404 if (cmd_buffer->state.index_buffer == index_buffer &&
2405 cmd_buffer->state.index_offset == offset &&
2406 cmd_buffer->state.index_type == indexType) {
2407 /* No state changes. */
2408 return;
2409 }
2410
2411 cmd_buffer->state.index_buffer = index_buffer;
2412 cmd_buffer->state.index_offset = offset;
2413 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2414 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2415 cmd_buffer->state.index_va += index_buffer->offset + offset;
2416
2417 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2418 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2419 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2420 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
2421 }
2422
2423
2424 static void
2425 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2426 VkPipelineBindPoint bind_point,
2427 struct radv_descriptor_set *set, unsigned idx)
2428 {
2429 struct radeon_winsys *ws = cmd_buffer->device->ws;
2430
2431 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2432
2433 assert(set);
2434 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2435
2436 if (!cmd_buffer->device->use_global_bo_list) {
2437 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2438 if (set->descriptors[j])
2439 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
2440 }
2441
2442 if(set->bo)
2443 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
2444 }
2445
2446 void radv_CmdBindDescriptorSets(
2447 VkCommandBuffer commandBuffer,
2448 VkPipelineBindPoint pipelineBindPoint,
2449 VkPipelineLayout _layout,
2450 uint32_t firstSet,
2451 uint32_t descriptorSetCount,
2452 const VkDescriptorSet* pDescriptorSets,
2453 uint32_t dynamicOffsetCount,
2454 const uint32_t* pDynamicOffsets)
2455 {
2456 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2457 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2458 unsigned dyn_idx = 0;
2459
2460 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2461 struct radv_descriptor_state *descriptors_state =
2462 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2463
2464 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2465 unsigned idx = i + firstSet;
2466 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2467 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2468
2469 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2470 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2471 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
2472 assert(dyn_idx < dynamicOffsetCount);
2473
2474 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2475 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2476 dst[0] = va;
2477 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2478 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2479 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2480 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2481 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2482 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2483 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2484 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2485 cmd_buffer->push_constant_stages |=
2486 set->layout->dynamic_shader_stages;
2487 }
2488 }
2489 }
2490
2491 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2492 struct radv_descriptor_set *set,
2493 struct radv_descriptor_set_layout *layout,
2494 VkPipelineBindPoint bind_point)
2495 {
2496 struct radv_descriptor_state *descriptors_state =
2497 radv_get_descriptors_state(cmd_buffer, bind_point);
2498 set->size = layout->size;
2499 set->layout = layout;
2500
2501 if (descriptors_state->push_set.capacity < set->size) {
2502 size_t new_size = MAX2(set->size, 1024);
2503 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2504 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2505
2506 free(set->mapped_ptr);
2507 set->mapped_ptr = malloc(new_size);
2508
2509 if (!set->mapped_ptr) {
2510 descriptors_state->push_set.capacity = 0;
2511 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2512 return false;
2513 }
2514
2515 descriptors_state->push_set.capacity = new_size;
2516 }
2517
2518 return true;
2519 }
2520
2521 void radv_meta_push_descriptor_set(
2522 struct radv_cmd_buffer* cmd_buffer,
2523 VkPipelineBindPoint pipelineBindPoint,
2524 VkPipelineLayout _layout,
2525 uint32_t set,
2526 uint32_t descriptorWriteCount,
2527 const VkWriteDescriptorSet* pDescriptorWrites)
2528 {
2529 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2530 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2531 unsigned bo_offset;
2532
2533 assert(set == 0);
2534 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2535
2536 push_set->size = layout->set[set].layout->size;
2537 push_set->layout = layout->set[set].layout;
2538
2539 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2540 &bo_offset,
2541 (void**) &push_set->mapped_ptr))
2542 return;
2543
2544 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2545 push_set->va += bo_offset;
2546
2547 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2548 radv_descriptor_set_to_handle(push_set),
2549 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2550
2551 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2552 }
2553
2554 void radv_CmdPushDescriptorSetKHR(
2555 VkCommandBuffer commandBuffer,
2556 VkPipelineBindPoint pipelineBindPoint,
2557 VkPipelineLayout _layout,
2558 uint32_t set,
2559 uint32_t descriptorWriteCount,
2560 const VkWriteDescriptorSet* pDescriptorWrites)
2561 {
2562 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2563 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2564 struct radv_descriptor_state *descriptors_state =
2565 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2566 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2567
2568 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2569
2570 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2571 layout->set[set].layout,
2572 pipelineBindPoint))
2573 return;
2574
2575 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2576 radv_descriptor_set_to_handle(push_set),
2577 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2578
2579 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2580 descriptors_state->push_dirty = true;
2581 }
2582
2583 void radv_CmdPushDescriptorSetWithTemplateKHR(
2584 VkCommandBuffer commandBuffer,
2585 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2586 VkPipelineLayout _layout,
2587 uint32_t set,
2588 const void* pData)
2589 {
2590 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2591 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2592 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2593 struct radv_descriptor_state *descriptors_state =
2594 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2595 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2596
2597 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2598
2599 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2600 layout->set[set].layout,
2601 templ->bind_point))
2602 return;
2603
2604 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2605 descriptorUpdateTemplate, pData);
2606
2607 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2608 descriptors_state->push_dirty = true;
2609 }
2610
2611 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2612 VkPipelineLayout layout,
2613 VkShaderStageFlags stageFlags,
2614 uint32_t offset,
2615 uint32_t size,
2616 const void* pValues)
2617 {
2618 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2619 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2620 cmd_buffer->push_constant_stages |= stageFlags;
2621 }
2622
2623 VkResult radv_EndCommandBuffer(
2624 VkCommandBuffer commandBuffer)
2625 {
2626 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2627
2628 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2629 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2630 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2631 si_emit_cache_flush(cmd_buffer);
2632 }
2633
2634 /* Make sure CP DMA is idle at the end of IBs because the kernel
2635 * doesn't wait for it.
2636 */
2637 si_cp_dma_wait_for_idle(cmd_buffer);
2638
2639 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2640
2641 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2642 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2643
2644 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2645
2646 return cmd_buffer->record_result;
2647 }
2648
2649 static void
2650 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2651 {
2652 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2653
2654 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2655 return;
2656
2657 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2658
2659 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2660 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2661
2662 cmd_buffer->compute_scratch_size_needed =
2663 MAX2(cmd_buffer->compute_scratch_size_needed,
2664 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2665
2666 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2667 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
2668
2669 if (unlikely(cmd_buffer->device->trace_bo))
2670 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2671 }
2672
2673 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2674 VkPipelineBindPoint bind_point)
2675 {
2676 struct radv_descriptor_state *descriptors_state =
2677 radv_get_descriptors_state(cmd_buffer, bind_point);
2678
2679 descriptors_state->dirty |= descriptors_state->valid;
2680 }
2681
2682 void radv_CmdBindPipeline(
2683 VkCommandBuffer commandBuffer,
2684 VkPipelineBindPoint pipelineBindPoint,
2685 VkPipeline _pipeline)
2686 {
2687 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2688 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2689
2690 switch (pipelineBindPoint) {
2691 case VK_PIPELINE_BIND_POINT_COMPUTE:
2692 if (cmd_buffer->state.compute_pipeline == pipeline)
2693 return;
2694 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2695
2696 cmd_buffer->state.compute_pipeline = pipeline;
2697 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2698 break;
2699 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2700 if (cmd_buffer->state.pipeline == pipeline)
2701 return;
2702 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2703
2704 cmd_buffer->state.pipeline = pipeline;
2705 if (!pipeline)
2706 break;
2707
2708 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2709 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2710
2711 /* the new vertex shader might not have the same user regs */
2712 cmd_buffer->state.last_first_instance = -1;
2713 cmd_buffer->state.last_vertex_offset = -1;
2714
2715 /* Prefetch all pipeline shaders at first draw time. */
2716 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
2717
2718 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2719
2720 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2721 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2722 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2723 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2724
2725 if (radv_pipeline_has_tess(pipeline))
2726 cmd_buffer->tess_rings_needed = true;
2727 break;
2728 default:
2729 assert(!"invalid bind point");
2730 break;
2731 }
2732 }
2733
2734 void radv_CmdSetViewport(
2735 VkCommandBuffer commandBuffer,
2736 uint32_t firstViewport,
2737 uint32_t viewportCount,
2738 const VkViewport* pViewports)
2739 {
2740 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2741 struct radv_cmd_state *state = &cmd_buffer->state;
2742 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2743
2744 assert(firstViewport < MAX_VIEWPORTS);
2745 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2746
2747 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2748 viewportCount * sizeof(*pViewports));
2749
2750 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2751 }
2752
2753 void radv_CmdSetScissor(
2754 VkCommandBuffer commandBuffer,
2755 uint32_t firstScissor,
2756 uint32_t scissorCount,
2757 const VkRect2D* pScissors)
2758 {
2759 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2760 struct radv_cmd_state *state = &cmd_buffer->state;
2761 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2762
2763 assert(firstScissor < MAX_SCISSORS);
2764 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2765
2766 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2767 scissorCount * sizeof(*pScissors));
2768
2769 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2770 }
2771
2772 void radv_CmdSetLineWidth(
2773 VkCommandBuffer commandBuffer,
2774 float lineWidth)
2775 {
2776 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2777 cmd_buffer->state.dynamic.line_width = lineWidth;
2778 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2779 }
2780
2781 void radv_CmdSetDepthBias(
2782 VkCommandBuffer commandBuffer,
2783 float depthBiasConstantFactor,
2784 float depthBiasClamp,
2785 float depthBiasSlopeFactor)
2786 {
2787 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2788
2789 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2790 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2791 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2792
2793 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2794 }
2795
2796 void radv_CmdSetBlendConstants(
2797 VkCommandBuffer commandBuffer,
2798 const float blendConstants[4])
2799 {
2800 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2801
2802 memcpy(cmd_buffer->state.dynamic.blend_constants,
2803 blendConstants, sizeof(float) * 4);
2804
2805 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2806 }
2807
2808 void radv_CmdSetDepthBounds(
2809 VkCommandBuffer commandBuffer,
2810 float minDepthBounds,
2811 float maxDepthBounds)
2812 {
2813 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2814
2815 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2816 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2817
2818 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2819 }
2820
2821 void radv_CmdSetStencilCompareMask(
2822 VkCommandBuffer commandBuffer,
2823 VkStencilFaceFlags faceMask,
2824 uint32_t compareMask)
2825 {
2826 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2827
2828 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2829 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2830 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2831 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2832
2833 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2834 }
2835
2836 void radv_CmdSetStencilWriteMask(
2837 VkCommandBuffer commandBuffer,
2838 VkStencilFaceFlags faceMask,
2839 uint32_t writeMask)
2840 {
2841 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2842
2843 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2844 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2845 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2846 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2847
2848 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2849 }
2850
2851 void radv_CmdSetStencilReference(
2852 VkCommandBuffer commandBuffer,
2853 VkStencilFaceFlags faceMask,
2854 uint32_t reference)
2855 {
2856 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2857
2858 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2859 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2860 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2861 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2862
2863 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2864 }
2865
2866 void radv_CmdSetDiscardRectangleEXT(
2867 VkCommandBuffer commandBuffer,
2868 uint32_t firstDiscardRectangle,
2869 uint32_t discardRectangleCount,
2870 const VkRect2D* pDiscardRectangles)
2871 {
2872 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2873 struct radv_cmd_state *state = &cmd_buffer->state;
2874 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
2875
2876 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
2877 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
2878
2879 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
2880 pDiscardRectangles, discardRectangleCount);
2881
2882 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
2883 }
2884
2885 void radv_CmdExecuteCommands(
2886 VkCommandBuffer commandBuffer,
2887 uint32_t commandBufferCount,
2888 const VkCommandBuffer* pCmdBuffers)
2889 {
2890 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2891
2892 assert(commandBufferCount > 0);
2893
2894 /* Emit pending flushes on primary prior to executing secondary */
2895 si_emit_cache_flush(primary);
2896
2897 for (uint32_t i = 0; i < commandBufferCount; i++) {
2898 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2899
2900 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2901 secondary->scratch_size_needed);
2902 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2903 secondary->compute_scratch_size_needed);
2904
2905 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2906 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2907 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2908 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2909 if (secondary->tess_rings_needed)
2910 primary->tess_rings_needed = true;
2911 if (secondary->sample_positions_needed)
2912 primary->sample_positions_needed = true;
2913
2914 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2915
2916
2917 /* When the secondary command buffer is compute only we don't
2918 * need to re-emit the current graphics pipeline.
2919 */
2920 if (secondary->state.emitted_pipeline) {
2921 primary->state.emitted_pipeline =
2922 secondary->state.emitted_pipeline;
2923 }
2924
2925 /* When the secondary command buffer is graphics only we don't
2926 * need to re-emit the current compute pipeline.
2927 */
2928 if (secondary->state.emitted_compute_pipeline) {
2929 primary->state.emitted_compute_pipeline =
2930 secondary->state.emitted_compute_pipeline;
2931 }
2932
2933 /* Only re-emit the draw packets when needed. */
2934 if (secondary->state.last_primitive_reset_en != -1) {
2935 primary->state.last_primitive_reset_en =
2936 secondary->state.last_primitive_reset_en;
2937 }
2938
2939 if (secondary->state.last_primitive_reset_index) {
2940 primary->state.last_primitive_reset_index =
2941 secondary->state.last_primitive_reset_index;
2942 }
2943
2944 if (secondary->state.last_ia_multi_vgt_param) {
2945 primary->state.last_ia_multi_vgt_param =
2946 secondary->state.last_ia_multi_vgt_param;
2947 }
2948
2949 primary->state.last_first_instance = secondary->state.last_first_instance;
2950 primary->state.last_num_instances = secondary->state.last_num_instances;
2951 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
2952
2953 if (secondary->state.last_index_type != -1) {
2954 primary->state.last_index_type =
2955 secondary->state.last_index_type;
2956 }
2957 }
2958
2959 /* After executing commands from secondary buffers we have to dirty
2960 * some states.
2961 */
2962 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2963 RADV_CMD_DIRTY_INDEX_BUFFER |
2964 RADV_CMD_DIRTY_DYNAMIC_ALL;
2965 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
2966 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
2967 }
2968
2969 VkResult radv_CreateCommandPool(
2970 VkDevice _device,
2971 const VkCommandPoolCreateInfo* pCreateInfo,
2972 const VkAllocationCallbacks* pAllocator,
2973 VkCommandPool* pCmdPool)
2974 {
2975 RADV_FROM_HANDLE(radv_device, device, _device);
2976 struct radv_cmd_pool *pool;
2977
2978 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2979 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2980 if (pool == NULL)
2981 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2982
2983 if (pAllocator)
2984 pool->alloc = *pAllocator;
2985 else
2986 pool->alloc = device->alloc;
2987
2988 list_inithead(&pool->cmd_buffers);
2989 list_inithead(&pool->free_cmd_buffers);
2990
2991 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2992
2993 *pCmdPool = radv_cmd_pool_to_handle(pool);
2994
2995 return VK_SUCCESS;
2996
2997 }
2998
2999 void radv_DestroyCommandPool(
3000 VkDevice _device,
3001 VkCommandPool commandPool,
3002 const VkAllocationCallbacks* pAllocator)
3003 {
3004 RADV_FROM_HANDLE(radv_device, device, _device);
3005 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3006
3007 if (!pool)
3008 return;
3009
3010 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3011 &pool->cmd_buffers, pool_link) {
3012 radv_cmd_buffer_destroy(cmd_buffer);
3013 }
3014
3015 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3016 &pool->free_cmd_buffers, pool_link) {
3017 radv_cmd_buffer_destroy(cmd_buffer);
3018 }
3019
3020 vk_free2(&device->alloc, pAllocator, pool);
3021 }
3022
3023 VkResult radv_ResetCommandPool(
3024 VkDevice device,
3025 VkCommandPool commandPool,
3026 VkCommandPoolResetFlags flags)
3027 {
3028 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3029 VkResult result;
3030
3031 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3032 &pool->cmd_buffers, pool_link) {
3033 result = radv_reset_cmd_buffer(cmd_buffer);
3034 if (result != VK_SUCCESS)
3035 return result;
3036 }
3037
3038 return VK_SUCCESS;
3039 }
3040
3041 void radv_TrimCommandPool(
3042 VkDevice device,
3043 VkCommandPool commandPool,
3044 VkCommandPoolTrimFlagsKHR flags)
3045 {
3046 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3047
3048 if (!pool)
3049 return;
3050
3051 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3052 &pool->free_cmd_buffers, pool_link) {
3053 radv_cmd_buffer_destroy(cmd_buffer);
3054 }
3055 }
3056
3057 void radv_CmdBeginRenderPass(
3058 VkCommandBuffer commandBuffer,
3059 const VkRenderPassBeginInfo* pRenderPassBegin,
3060 VkSubpassContents contents)
3061 {
3062 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3063 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3064 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3065
3066 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3067 cmd_buffer->cs, 2048);
3068 MAYBE_UNUSED VkResult result;
3069
3070 cmd_buffer->state.framebuffer = framebuffer;
3071 cmd_buffer->state.pass = pass;
3072 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3073
3074 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3075 if (result != VK_SUCCESS)
3076 return;
3077
3078 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
3079 assert(cmd_buffer->cs->cdw <= cdw_max);
3080
3081 radv_cmd_buffer_clear_subpass(cmd_buffer);
3082 }
3083
3084 void radv_CmdBeginRenderPass2KHR(
3085 VkCommandBuffer commandBuffer,
3086 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
3087 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
3088 {
3089 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
3090 pSubpassBeginInfo->contents);
3091 }
3092
3093 void radv_CmdNextSubpass(
3094 VkCommandBuffer commandBuffer,
3095 VkSubpassContents contents)
3096 {
3097 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3098
3099 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3100
3101 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
3102 2048);
3103
3104 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
3105 radv_cmd_buffer_clear_subpass(cmd_buffer);
3106 }
3107
3108 void radv_CmdNextSubpass2KHR(
3109 VkCommandBuffer commandBuffer,
3110 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
3111 const VkSubpassEndInfoKHR* pSubpassEndInfo)
3112 {
3113 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
3114 }
3115
3116 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3117 {
3118 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3119 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3120 if (!radv_get_shader(pipeline, stage))
3121 continue;
3122
3123 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3124 if (loc->sgpr_idx == -1)
3125 continue;
3126 uint32_t base_reg = pipeline->user_data_0[stage];
3127 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3128
3129 }
3130 if (pipeline->gs_copy_shader) {
3131 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3132 if (loc->sgpr_idx != -1) {
3133 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3134 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3135 }
3136 }
3137 }
3138
3139 static void
3140 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3141 uint32_t vertex_count)
3142 {
3143 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3144 radeon_emit(cmd_buffer->cs, vertex_count);
3145 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3146 S_0287F0_USE_OPAQUE(0));
3147 }
3148
3149 static void
3150 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3151 uint64_t index_va,
3152 uint32_t index_count)
3153 {
3154 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
3155 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3156 radeon_emit(cmd_buffer->cs, index_va);
3157 radeon_emit(cmd_buffer->cs, index_va >> 32);
3158 radeon_emit(cmd_buffer->cs, index_count);
3159 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3160 }
3161
3162 static void
3163 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3164 bool indexed,
3165 uint32_t draw_count,
3166 uint64_t count_va,
3167 uint32_t stride)
3168 {
3169 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3170 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3171 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3172 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
3173 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3174 bool predicating = cmd_buffer->state.predicating;
3175 assert(base_reg);
3176
3177 /* just reset draw state for vertex data */
3178 cmd_buffer->state.last_first_instance = -1;
3179 cmd_buffer->state.last_num_instances = -1;
3180 cmd_buffer->state.last_vertex_offset = -1;
3181
3182 if (draw_count == 1 && !count_va && !draw_id_enable) {
3183 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3184 PKT3_DRAW_INDIRECT, 3, predicating));
3185 radeon_emit(cs, 0);
3186 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3187 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3188 radeon_emit(cs, di_src_sel);
3189 } else {
3190 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3191 PKT3_DRAW_INDIRECT_MULTI,
3192 8, predicating));
3193 radeon_emit(cs, 0);
3194 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3195 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3196 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3197 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3198 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3199 radeon_emit(cs, draw_count); /* count */
3200 radeon_emit(cs, count_va); /* count_addr */
3201 radeon_emit(cs, count_va >> 32);
3202 radeon_emit(cs, stride); /* stride */
3203 radeon_emit(cs, di_src_sel);
3204 }
3205 }
3206
3207 struct radv_draw_info {
3208 /**
3209 * Number of vertices.
3210 */
3211 uint32_t count;
3212
3213 /**
3214 * Index of the first vertex.
3215 */
3216 int32_t vertex_offset;
3217
3218 /**
3219 * First instance id.
3220 */
3221 uint32_t first_instance;
3222
3223 /**
3224 * Number of instances.
3225 */
3226 uint32_t instance_count;
3227
3228 /**
3229 * First index (indexed draws only).
3230 */
3231 uint32_t first_index;
3232
3233 /**
3234 * Whether it's an indexed draw.
3235 */
3236 bool indexed;
3237
3238 /**
3239 * Indirect draw parameters resource.
3240 */
3241 struct radv_buffer *indirect;
3242 uint64_t indirect_offset;
3243 uint32_t stride;
3244
3245 /**
3246 * Draw count parameters resource.
3247 */
3248 struct radv_buffer *count_buffer;
3249 uint64_t count_buffer_offset;
3250 };
3251
3252 static void
3253 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3254 const struct radv_draw_info *info)
3255 {
3256 struct radv_cmd_state *state = &cmd_buffer->state;
3257 struct radeon_winsys *ws = cmd_buffer->device->ws;
3258 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3259
3260 if (info->indirect) {
3261 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3262 uint64_t count_va = 0;
3263
3264 va += info->indirect->offset + info->indirect_offset;
3265
3266 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3267
3268 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3269 radeon_emit(cs, 1);
3270 radeon_emit(cs, va);
3271 radeon_emit(cs, va >> 32);
3272
3273 if (info->count_buffer) {
3274 count_va = radv_buffer_get_va(info->count_buffer->bo);
3275 count_va += info->count_buffer->offset +
3276 info->count_buffer_offset;
3277
3278 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
3279 }
3280
3281 if (!state->subpass->view_mask) {
3282 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3283 info->indexed,
3284 info->count,
3285 count_va,
3286 info->stride);
3287 } else {
3288 unsigned i;
3289 for_each_bit(i, state->subpass->view_mask) {
3290 radv_emit_view_index(cmd_buffer, i);
3291
3292 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3293 info->indexed,
3294 info->count,
3295 count_va,
3296 info->stride);
3297 }
3298 }
3299 } else {
3300 assert(state->pipeline->graphics.vtx_base_sgpr);
3301
3302 if (info->vertex_offset != state->last_vertex_offset ||
3303 info->first_instance != state->last_first_instance) {
3304 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3305 state->pipeline->graphics.vtx_emit_num);
3306
3307 radeon_emit(cs, info->vertex_offset);
3308 radeon_emit(cs, info->first_instance);
3309 if (state->pipeline->graphics.vtx_emit_num == 3)
3310 radeon_emit(cs, 0);
3311 state->last_first_instance = info->first_instance;
3312 state->last_vertex_offset = info->vertex_offset;
3313 }
3314
3315 if (state->last_num_instances != info->instance_count) {
3316 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3317 radeon_emit(cs, info->instance_count);
3318 state->last_num_instances = info->instance_count;
3319 }
3320
3321 if (info->indexed) {
3322 int index_size = state->index_type ? 4 : 2;
3323 uint64_t index_va;
3324
3325 index_va = state->index_va;
3326 index_va += info->first_index * index_size;
3327
3328 if (!state->subpass->view_mask) {
3329 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3330 index_va,
3331 info->count);
3332 } else {
3333 unsigned i;
3334 for_each_bit(i, state->subpass->view_mask) {
3335 radv_emit_view_index(cmd_buffer, i);
3336
3337 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3338 index_va,
3339 info->count);
3340 }
3341 }
3342 } else {
3343 if (!state->subpass->view_mask) {
3344 radv_cs_emit_draw_packet(cmd_buffer, info->count);
3345 } else {
3346 unsigned i;
3347 for_each_bit(i, state->subpass->view_mask) {
3348 radv_emit_view_index(cmd_buffer, i);
3349
3350 radv_cs_emit_draw_packet(cmd_buffer,
3351 info->count);
3352 }
3353 }
3354 }
3355 }
3356 }
3357
3358 /*
3359 * Vega and raven have a bug which triggers if there are multiple context
3360 * register contexts active at the same time with different scissor values.
3361 *
3362 * There are two possible workarounds:
3363 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3364 * there is only ever 1 active set of scissor values at the same time.
3365 *
3366 * 2) Whenever the hardware switches contexts we have to set the scissor
3367 * registers again even if it is a noop. That way the new context gets
3368 * the correct scissor values.
3369 *
3370 * This implements option 2. radv_need_late_scissor_emission needs to
3371 * return true on affected HW if radv_emit_all_graphics_states sets
3372 * any context registers.
3373 */
3374 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
3375 bool indexed_draw)
3376 {
3377 struct radv_cmd_state *state = &cmd_buffer->state;
3378
3379 if (!cmd_buffer->device->physical_device->has_scissor_bug)
3380 return false;
3381
3382 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
3383
3384 /* Index & Vertex buffer don't change context regs, and pipeline is handled later. */
3385 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER | RADV_CMD_DIRTY_VERTEX_BUFFER | RADV_CMD_DIRTY_PIPELINE);
3386
3387 /* Assume all state changes except these two can imply context rolls. */
3388 if (cmd_buffer->state.dirty & used_states)
3389 return true;
3390
3391 if (cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3392 return true;
3393
3394 if (indexed_draw && state->pipeline->graphics.prim_restart_enable &&
3395 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
3396 return true;
3397
3398 return false;
3399 }
3400
3401 static void
3402 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3403 const struct radv_draw_info *info)
3404 {
3405 bool late_scissor_emission = radv_need_late_scissor_emission(cmd_buffer, info->indexed);
3406
3407 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3408 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3409 radv_emit_rbplus_state(cmd_buffer);
3410
3411 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3412 radv_emit_graphics_pipeline(cmd_buffer);
3413
3414 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3415 radv_emit_framebuffer_state(cmd_buffer);
3416
3417 if (info->indexed) {
3418 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3419 radv_emit_index_buffer(cmd_buffer);
3420 } else {
3421 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3422 * so the state must be re-emitted before the next indexed
3423 * draw.
3424 */
3425 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3426 cmd_buffer->state.last_index_type = -1;
3427 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3428 }
3429 }
3430
3431 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3432
3433 radv_emit_draw_registers(cmd_buffer, info->indexed,
3434 info->instance_count > 1, info->indirect,
3435 info->indirect ? 0 : info->count);
3436
3437 if (late_scissor_emission)
3438 radv_emit_scissor(cmd_buffer);
3439 }
3440
3441 static void
3442 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3443 const struct radv_draw_info *info)
3444 {
3445 bool has_prefetch =
3446 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3447 bool pipeline_is_dirty =
3448 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3449 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3450
3451 MAYBE_UNUSED unsigned cdw_max =
3452 radeon_check_space(cmd_buffer->device->ws,
3453 cmd_buffer->cs, 4096);
3454
3455 /* Use optimal packet order based on whether we need to sync the
3456 * pipeline.
3457 */
3458 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3459 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3460 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3461 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3462 /* If we have to wait for idle, set all states first, so that
3463 * all SET packets are processed in parallel with previous draw
3464 * calls. Then upload descriptors, set shader pointers, and
3465 * draw, and prefetch at the end. This ensures that the time
3466 * the CUs are idle is very short. (there are only SET_SH
3467 * packets between the wait and the draw)
3468 */
3469 radv_emit_all_graphics_states(cmd_buffer, info);
3470 si_emit_cache_flush(cmd_buffer);
3471 /* <-- CUs are idle here --> */
3472
3473 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3474
3475 radv_emit_draw_packets(cmd_buffer, info);
3476 /* <-- CUs are busy here --> */
3477
3478 /* Start prefetches after the draw has been started. Both will
3479 * run in parallel, but starting the draw first is more
3480 * important.
3481 */
3482 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3483 radv_emit_prefetch_L2(cmd_buffer,
3484 cmd_buffer->state.pipeline, false);
3485 }
3486 } else {
3487 /* If we don't wait for idle, start prefetches first, then set
3488 * states, and draw at the end.
3489 */
3490 si_emit_cache_flush(cmd_buffer);
3491
3492 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3493 /* Only prefetch the vertex shader and VBO descriptors
3494 * in order to start the draw as soon as possible.
3495 */
3496 radv_emit_prefetch_L2(cmd_buffer,
3497 cmd_buffer->state.pipeline, true);
3498 }
3499
3500 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3501
3502 radv_emit_all_graphics_states(cmd_buffer, info);
3503 radv_emit_draw_packets(cmd_buffer, info);
3504
3505 /* Prefetch the remaining shaders after the draw has been
3506 * started.
3507 */
3508 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3509 radv_emit_prefetch_L2(cmd_buffer,
3510 cmd_buffer->state.pipeline, false);
3511 }
3512 }
3513
3514 assert(cmd_buffer->cs->cdw <= cdw_max);
3515 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3516 }
3517
3518 void radv_CmdDraw(
3519 VkCommandBuffer commandBuffer,
3520 uint32_t vertexCount,
3521 uint32_t instanceCount,
3522 uint32_t firstVertex,
3523 uint32_t firstInstance)
3524 {
3525 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3526 struct radv_draw_info info = {};
3527
3528 info.count = vertexCount;
3529 info.instance_count = instanceCount;
3530 info.first_instance = firstInstance;
3531 info.vertex_offset = firstVertex;
3532
3533 radv_draw(cmd_buffer, &info);
3534 }
3535
3536 void radv_CmdDrawIndexed(
3537 VkCommandBuffer commandBuffer,
3538 uint32_t indexCount,
3539 uint32_t instanceCount,
3540 uint32_t firstIndex,
3541 int32_t vertexOffset,
3542 uint32_t firstInstance)
3543 {
3544 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3545 struct radv_draw_info info = {};
3546
3547 info.indexed = true;
3548 info.count = indexCount;
3549 info.instance_count = instanceCount;
3550 info.first_index = firstIndex;
3551 info.vertex_offset = vertexOffset;
3552 info.first_instance = firstInstance;
3553
3554 radv_draw(cmd_buffer, &info);
3555 }
3556
3557 void radv_CmdDrawIndirect(
3558 VkCommandBuffer commandBuffer,
3559 VkBuffer _buffer,
3560 VkDeviceSize offset,
3561 uint32_t drawCount,
3562 uint32_t stride)
3563 {
3564 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3565 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3566 struct radv_draw_info info = {};
3567
3568 info.count = drawCount;
3569 info.indirect = buffer;
3570 info.indirect_offset = offset;
3571 info.stride = stride;
3572
3573 radv_draw(cmd_buffer, &info);
3574 }
3575
3576 void radv_CmdDrawIndexedIndirect(
3577 VkCommandBuffer commandBuffer,
3578 VkBuffer _buffer,
3579 VkDeviceSize offset,
3580 uint32_t drawCount,
3581 uint32_t stride)
3582 {
3583 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3584 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3585 struct radv_draw_info info = {};
3586
3587 info.indexed = true;
3588 info.count = drawCount;
3589 info.indirect = buffer;
3590 info.indirect_offset = offset;
3591 info.stride = stride;
3592
3593 radv_draw(cmd_buffer, &info);
3594 }
3595
3596 void radv_CmdDrawIndirectCountAMD(
3597 VkCommandBuffer commandBuffer,
3598 VkBuffer _buffer,
3599 VkDeviceSize offset,
3600 VkBuffer _countBuffer,
3601 VkDeviceSize countBufferOffset,
3602 uint32_t maxDrawCount,
3603 uint32_t stride)
3604 {
3605 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3606 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3607 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3608 struct radv_draw_info info = {};
3609
3610 info.count = maxDrawCount;
3611 info.indirect = buffer;
3612 info.indirect_offset = offset;
3613 info.count_buffer = count_buffer;
3614 info.count_buffer_offset = countBufferOffset;
3615 info.stride = stride;
3616
3617 radv_draw(cmd_buffer, &info);
3618 }
3619
3620 void radv_CmdDrawIndexedIndirectCountAMD(
3621 VkCommandBuffer commandBuffer,
3622 VkBuffer _buffer,
3623 VkDeviceSize offset,
3624 VkBuffer _countBuffer,
3625 VkDeviceSize countBufferOffset,
3626 uint32_t maxDrawCount,
3627 uint32_t stride)
3628 {
3629 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3630 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3631 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3632 struct radv_draw_info info = {};
3633
3634 info.indexed = true;
3635 info.count = maxDrawCount;
3636 info.indirect = buffer;
3637 info.indirect_offset = offset;
3638 info.count_buffer = count_buffer;
3639 info.count_buffer_offset = countBufferOffset;
3640 info.stride = stride;
3641
3642 radv_draw(cmd_buffer, &info);
3643 }
3644
3645 void radv_CmdDrawIndirectCountKHR(
3646 VkCommandBuffer commandBuffer,
3647 VkBuffer _buffer,
3648 VkDeviceSize offset,
3649 VkBuffer _countBuffer,
3650 VkDeviceSize countBufferOffset,
3651 uint32_t maxDrawCount,
3652 uint32_t stride)
3653 {
3654 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3655 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3656 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3657 struct radv_draw_info info = {};
3658
3659 info.count = maxDrawCount;
3660 info.indirect = buffer;
3661 info.indirect_offset = offset;
3662 info.count_buffer = count_buffer;
3663 info.count_buffer_offset = countBufferOffset;
3664 info.stride = stride;
3665
3666 radv_draw(cmd_buffer, &info);
3667 }
3668
3669 void radv_CmdDrawIndexedIndirectCountKHR(
3670 VkCommandBuffer commandBuffer,
3671 VkBuffer _buffer,
3672 VkDeviceSize offset,
3673 VkBuffer _countBuffer,
3674 VkDeviceSize countBufferOffset,
3675 uint32_t maxDrawCount,
3676 uint32_t stride)
3677 {
3678 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3679 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3680 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3681 struct radv_draw_info info = {};
3682
3683 info.indexed = true;
3684 info.count = maxDrawCount;
3685 info.indirect = buffer;
3686 info.indirect_offset = offset;
3687 info.count_buffer = count_buffer;
3688 info.count_buffer_offset = countBufferOffset;
3689 info.stride = stride;
3690
3691 radv_draw(cmd_buffer, &info);
3692 }
3693
3694 struct radv_dispatch_info {
3695 /**
3696 * Determine the layout of the grid (in block units) to be used.
3697 */
3698 uint32_t blocks[3];
3699
3700 /**
3701 * A starting offset for the grid. If unaligned is set, the offset
3702 * must still be aligned.
3703 */
3704 uint32_t offsets[3];
3705 /**
3706 * Whether it's an unaligned compute dispatch.
3707 */
3708 bool unaligned;
3709
3710 /**
3711 * Indirect compute parameters resource.
3712 */
3713 struct radv_buffer *indirect;
3714 uint64_t indirect_offset;
3715 };
3716
3717 static void
3718 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3719 const struct radv_dispatch_info *info)
3720 {
3721 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3722 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3723 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3724 struct radeon_winsys *ws = cmd_buffer->device->ws;
3725 bool predicating = cmd_buffer->state.predicating;
3726 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3727 struct radv_userdata_info *loc;
3728
3729 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3730 AC_UD_CS_GRID_SIZE);
3731
3732 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3733
3734 if (info->indirect) {
3735 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3736
3737 va += info->indirect->offset + info->indirect_offset;
3738
3739 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3740
3741 if (loc->sgpr_idx != -1) {
3742 for (unsigned i = 0; i < 3; ++i) {
3743 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3744 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3745 COPY_DATA_DST_SEL(COPY_DATA_REG));
3746 radeon_emit(cs, (va + 4 * i));
3747 radeon_emit(cs, (va + 4 * i) >> 32);
3748 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3749 + loc->sgpr_idx * 4) >> 2) + i);
3750 radeon_emit(cs, 0);
3751 }
3752 }
3753
3754 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3755 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
3756 PKT3_SHADER_TYPE_S(1));
3757 radeon_emit(cs, va);
3758 radeon_emit(cs, va >> 32);
3759 radeon_emit(cs, dispatch_initiator);
3760 } else {
3761 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3762 PKT3_SHADER_TYPE_S(1));
3763 radeon_emit(cs, 1);
3764 radeon_emit(cs, va);
3765 radeon_emit(cs, va >> 32);
3766
3767 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
3768 PKT3_SHADER_TYPE_S(1));
3769 radeon_emit(cs, 0);
3770 radeon_emit(cs, dispatch_initiator);
3771 }
3772 } else {
3773 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3774 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
3775
3776 if (info->unaligned) {
3777 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3778 unsigned remainder[3];
3779
3780 /* If aligned, these should be an entire block size,
3781 * not 0.
3782 */
3783 remainder[0] = blocks[0] + cs_block_size[0] -
3784 align_u32_npot(blocks[0], cs_block_size[0]);
3785 remainder[1] = blocks[1] + cs_block_size[1] -
3786 align_u32_npot(blocks[1], cs_block_size[1]);
3787 remainder[2] = blocks[2] + cs_block_size[2] -
3788 align_u32_npot(blocks[2], cs_block_size[2]);
3789
3790 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3791 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3792 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3793
3794 for(unsigned i = 0; i < 3; ++i) {
3795 assert(offsets[i] % cs_block_size[i] == 0);
3796 offsets[i] /= cs_block_size[i];
3797 }
3798
3799 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3800 radeon_emit(cs,
3801 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3802 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3803 radeon_emit(cs,
3804 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3805 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3806 radeon_emit(cs,
3807 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3808 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3809
3810 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3811 }
3812
3813 if (loc->sgpr_idx != -1) {
3814 assert(!loc->indirect);
3815 assert(loc->num_sgprs == 3);
3816
3817 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3818 loc->sgpr_idx * 4, 3);
3819 radeon_emit(cs, blocks[0]);
3820 radeon_emit(cs, blocks[1]);
3821 radeon_emit(cs, blocks[2]);
3822 }
3823
3824 if (offsets[0] || offsets[1] || offsets[2]) {
3825 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
3826 radeon_emit(cs, offsets[0]);
3827 radeon_emit(cs, offsets[1]);
3828 radeon_emit(cs, offsets[2]);
3829
3830 /* The blocks in the packet are not counts but end values. */
3831 for (unsigned i = 0; i < 3; ++i)
3832 blocks[i] += offsets[i];
3833 } else {
3834 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
3835 }
3836
3837 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
3838 PKT3_SHADER_TYPE_S(1));
3839 radeon_emit(cs, blocks[0]);
3840 radeon_emit(cs, blocks[1]);
3841 radeon_emit(cs, blocks[2]);
3842 radeon_emit(cs, dispatch_initiator);
3843 }
3844
3845 assert(cmd_buffer->cs->cdw <= cdw_max);
3846 }
3847
3848 static void
3849 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3850 {
3851 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3852 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3853 }
3854
3855 static void
3856 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3857 const struct radv_dispatch_info *info)
3858 {
3859 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3860 bool has_prefetch =
3861 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3862 bool pipeline_is_dirty = pipeline &&
3863 pipeline != cmd_buffer->state.emitted_compute_pipeline;
3864
3865 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3866 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3867 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3868 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3869 /* If we have to wait for idle, set all states first, so that
3870 * all SET packets are processed in parallel with previous draw
3871 * calls. Then upload descriptors, set shader pointers, and
3872 * dispatch, and prefetch at the end. This ensures that the
3873 * time the CUs are idle is very short. (there are only SET_SH
3874 * packets between the wait and the draw)
3875 */
3876 radv_emit_compute_pipeline(cmd_buffer);
3877 si_emit_cache_flush(cmd_buffer);
3878 /* <-- CUs are idle here --> */
3879
3880 radv_upload_compute_shader_descriptors(cmd_buffer);
3881
3882 radv_emit_dispatch_packets(cmd_buffer, info);
3883 /* <-- CUs are busy here --> */
3884
3885 /* Start prefetches after the dispatch has been started. Both
3886 * will run in parallel, but starting the dispatch first is
3887 * more important.
3888 */
3889 if (has_prefetch && pipeline_is_dirty) {
3890 radv_emit_shader_prefetch(cmd_buffer,
3891 pipeline->shaders[MESA_SHADER_COMPUTE]);
3892 }
3893 } else {
3894 /* If we don't wait for idle, start prefetches first, then set
3895 * states, and dispatch at the end.
3896 */
3897 si_emit_cache_flush(cmd_buffer);
3898
3899 if (has_prefetch && pipeline_is_dirty) {
3900 radv_emit_shader_prefetch(cmd_buffer,
3901 pipeline->shaders[MESA_SHADER_COMPUTE]);
3902 }
3903
3904 radv_upload_compute_shader_descriptors(cmd_buffer);
3905
3906 radv_emit_compute_pipeline(cmd_buffer);
3907 radv_emit_dispatch_packets(cmd_buffer, info);
3908 }
3909
3910 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
3911 }
3912
3913 void radv_CmdDispatchBase(
3914 VkCommandBuffer commandBuffer,
3915 uint32_t base_x,
3916 uint32_t base_y,
3917 uint32_t base_z,
3918 uint32_t x,
3919 uint32_t y,
3920 uint32_t z)
3921 {
3922 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3923 struct radv_dispatch_info info = {};
3924
3925 info.blocks[0] = x;
3926 info.blocks[1] = y;
3927 info.blocks[2] = z;
3928
3929 info.offsets[0] = base_x;
3930 info.offsets[1] = base_y;
3931 info.offsets[2] = base_z;
3932 radv_dispatch(cmd_buffer, &info);
3933 }
3934
3935 void radv_CmdDispatch(
3936 VkCommandBuffer commandBuffer,
3937 uint32_t x,
3938 uint32_t y,
3939 uint32_t z)
3940 {
3941 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3942 }
3943
3944 void radv_CmdDispatchIndirect(
3945 VkCommandBuffer commandBuffer,
3946 VkBuffer _buffer,
3947 VkDeviceSize offset)
3948 {
3949 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3950 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3951 struct radv_dispatch_info info = {};
3952
3953 info.indirect = buffer;
3954 info.indirect_offset = offset;
3955
3956 radv_dispatch(cmd_buffer, &info);
3957 }
3958
3959 void radv_unaligned_dispatch(
3960 struct radv_cmd_buffer *cmd_buffer,
3961 uint32_t x,
3962 uint32_t y,
3963 uint32_t z)
3964 {
3965 struct radv_dispatch_info info = {};
3966
3967 info.blocks[0] = x;
3968 info.blocks[1] = y;
3969 info.blocks[2] = z;
3970 info.unaligned = 1;
3971
3972 radv_dispatch(cmd_buffer, &info);
3973 }
3974
3975 void radv_CmdEndRenderPass(
3976 VkCommandBuffer commandBuffer)
3977 {
3978 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3979
3980 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3981
3982 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3983
3984 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3985 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3986 radv_handle_subpass_image_transition(cmd_buffer,
3987 (struct radv_subpass_attachment){i, layout});
3988 }
3989
3990 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3991
3992 cmd_buffer->state.pass = NULL;
3993 cmd_buffer->state.subpass = NULL;
3994 cmd_buffer->state.attachments = NULL;
3995 cmd_buffer->state.framebuffer = NULL;
3996 }
3997
3998 void radv_CmdEndRenderPass2KHR(
3999 VkCommandBuffer commandBuffer,
4000 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4001 {
4002 radv_CmdEndRenderPass(commandBuffer);
4003 }
4004
4005 /*
4006 * For HTILE we have the following interesting clear words:
4007 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4008 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4009 * 0xfffffff0: Clear depth to 1.0
4010 * 0x00000000: Clear depth to 0.0
4011 */
4012 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
4013 struct radv_image *image,
4014 const VkImageSubresourceRange *range,
4015 uint32_t clear_word)
4016 {
4017 assert(range->baseMipLevel == 0);
4018 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
4019 unsigned layer_count = radv_get_layerCount(image, range);
4020 uint64_t size = image->surface.htile_slice_size * layer_count;
4021 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
4022 uint64_t offset = image->offset + image->htile_offset +
4023 image->surface.htile_slice_size * range->baseArrayLayer;
4024 struct radv_cmd_state *state = &cmd_buffer->state;
4025 VkClearDepthStencilValue value = {};
4026
4027 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4028 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4029
4030 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
4031 size, clear_word);
4032
4033 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4034
4035 if (vk_format_is_stencil(image->vk_format))
4036 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4037
4038 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4039 }
4040
4041 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4042 struct radv_image *image,
4043 VkImageLayout src_layout,
4044 VkImageLayout dst_layout,
4045 unsigned src_queue_mask,
4046 unsigned dst_queue_mask,
4047 const VkImageSubresourceRange *range,
4048 VkImageAspectFlags pending_clears)
4049 {
4050 if (!radv_image_has_htile(image))
4051 return;
4052
4053 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
4054 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
4055 /* TODO: merge with the clear if applicable */
4056 radv_initialize_htile(cmd_buffer, image, range, 0);
4057 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4058 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4059 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4060 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4061 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4062 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4063 VkImageSubresourceRange local_range = *range;
4064 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4065 local_range.baseMipLevel = 0;
4066 local_range.levelCount = 1;
4067
4068 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4069 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4070
4071 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
4072
4073 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4074 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4075 }
4076 }
4077
4078 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4079 struct radv_image *image, uint32_t value)
4080 {
4081 struct radv_cmd_state *state = &cmd_buffer->state;
4082
4083 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4084 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4085
4086 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
4087
4088 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4089 }
4090
4091 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4092 struct radv_image *image, uint32_t value)
4093 {
4094 struct radv_cmd_state *state = &cmd_buffer->state;
4095
4096 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4097 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4098
4099 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
4100
4101 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4102 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4103 }
4104
4105 /**
4106 * Initialize DCC/FMASK/CMASK metadata for a color image.
4107 */
4108 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4109 struct radv_image *image,
4110 VkImageLayout src_layout,
4111 VkImageLayout dst_layout,
4112 unsigned src_queue_mask,
4113 unsigned dst_queue_mask)
4114 {
4115 if (radv_image_has_cmask(image)) {
4116 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4117
4118 /* TODO: clarify this. */
4119 if (radv_image_has_fmask(image)) {
4120 value = 0xccccccccu;
4121 }
4122
4123 radv_initialise_cmask(cmd_buffer, image, value);
4124 }
4125
4126 if (radv_image_has_dcc(image)) {
4127 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4128 bool need_decompress_pass = false;
4129
4130 if (radv_layout_dcc_compressed(image, dst_layout,
4131 dst_queue_mask)) {
4132 value = 0x20202020u;
4133 need_decompress_pass = true;
4134 }
4135
4136 radv_initialize_dcc(cmd_buffer, image, value);
4137
4138 radv_set_dcc_need_cmask_elim_pred(cmd_buffer, image,
4139 need_decompress_pass);
4140 }
4141
4142 if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
4143 uint32_t color_values[2] = {};
4144 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
4145 }
4146 }
4147
4148 /**
4149 * Handle color image transitions for DCC/FMASK/CMASK.
4150 */
4151 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4152 struct radv_image *image,
4153 VkImageLayout src_layout,
4154 VkImageLayout dst_layout,
4155 unsigned src_queue_mask,
4156 unsigned dst_queue_mask,
4157 const VkImageSubresourceRange *range)
4158 {
4159 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4160 radv_init_color_image_metadata(cmd_buffer, image,
4161 src_layout, dst_layout,
4162 src_queue_mask, dst_queue_mask);
4163 return;
4164 }
4165
4166 if (radv_image_has_dcc(image)) {
4167 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4168 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4169 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4170 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4171 radv_decompress_dcc(cmd_buffer, image, range);
4172 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4173 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4174 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4175 }
4176 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
4177 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4178 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4179 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4180 }
4181 }
4182 }
4183
4184 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4185 struct radv_image *image,
4186 VkImageLayout src_layout,
4187 VkImageLayout dst_layout,
4188 uint32_t src_family,
4189 uint32_t dst_family,
4190 const VkImageSubresourceRange *range,
4191 VkImageAspectFlags pending_clears)
4192 {
4193 if (image->exclusive && src_family != dst_family) {
4194 /* This is an acquire or a release operation and there will be
4195 * a corresponding release/acquire. Do the transition in the
4196 * most flexible queue. */
4197
4198 assert(src_family == cmd_buffer->queue_family_index ||
4199 dst_family == cmd_buffer->queue_family_index);
4200
4201 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4202 return;
4203
4204 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4205 (src_family == RADV_QUEUE_GENERAL ||
4206 dst_family == RADV_QUEUE_GENERAL))
4207 return;
4208 }
4209
4210 unsigned src_queue_mask =
4211 radv_image_queue_family_mask(image, src_family,
4212 cmd_buffer->queue_family_index);
4213 unsigned dst_queue_mask =
4214 radv_image_queue_family_mask(image, dst_family,
4215 cmd_buffer->queue_family_index);
4216
4217 if (vk_format_is_depth(image->vk_format)) {
4218 radv_handle_depth_image_transition(cmd_buffer, image,
4219 src_layout, dst_layout,
4220 src_queue_mask, dst_queue_mask,
4221 range, pending_clears);
4222 } else {
4223 radv_handle_color_image_transition(cmd_buffer, image,
4224 src_layout, dst_layout,
4225 src_queue_mask, dst_queue_mask,
4226 range);
4227 }
4228 }
4229
4230 struct radv_barrier_info {
4231 uint32_t eventCount;
4232 const VkEvent *pEvents;
4233 VkPipelineStageFlags srcStageMask;
4234 };
4235
4236 static void
4237 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
4238 uint32_t memoryBarrierCount,
4239 const VkMemoryBarrier *pMemoryBarriers,
4240 uint32_t bufferMemoryBarrierCount,
4241 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4242 uint32_t imageMemoryBarrierCount,
4243 const VkImageMemoryBarrier *pImageMemoryBarriers,
4244 const struct radv_barrier_info *info)
4245 {
4246 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4247 enum radv_cmd_flush_bits src_flush_bits = 0;
4248 enum radv_cmd_flush_bits dst_flush_bits = 0;
4249
4250 for (unsigned i = 0; i < info->eventCount; ++i) {
4251 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
4252 uint64_t va = radv_buffer_get_va(event->bo);
4253
4254 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4255
4256 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4257
4258 si_emit_wait_fence(cs, va, 1, 0xffffffff);
4259 assert(cmd_buffer->cs->cdw <= cdw_max);
4260 }
4261
4262 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4263 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
4264 NULL);
4265 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4266 NULL);
4267 }
4268
4269 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4270 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
4271 NULL);
4272 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4273 NULL);
4274 }
4275
4276 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4277 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4278
4279 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
4280 image);
4281 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4282 image);
4283 }
4284
4285 radv_stage_flush(cmd_buffer, info->srcStageMask);
4286 cmd_buffer->state.flush_bits |= src_flush_bits;
4287
4288 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4289 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4290 radv_handle_image_transition(cmd_buffer, image,
4291 pImageMemoryBarriers[i].oldLayout,
4292 pImageMemoryBarriers[i].newLayout,
4293 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4294 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4295 &pImageMemoryBarriers[i].subresourceRange,
4296 0);
4297 }
4298
4299 /* Make sure CP DMA is idle because the driver might have performed a
4300 * DMA operation for copying or filling buffers/images.
4301 */
4302 si_cp_dma_wait_for_idle(cmd_buffer);
4303
4304 cmd_buffer->state.flush_bits |= dst_flush_bits;
4305 }
4306
4307 void radv_CmdPipelineBarrier(
4308 VkCommandBuffer commandBuffer,
4309 VkPipelineStageFlags srcStageMask,
4310 VkPipelineStageFlags destStageMask,
4311 VkBool32 byRegion,
4312 uint32_t memoryBarrierCount,
4313 const VkMemoryBarrier* pMemoryBarriers,
4314 uint32_t bufferMemoryBarrierCount,
4315 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4316 uint32_t imageMemoryBarrierCount,
4317 const VkImageMemoryBarrier* pImageMemoryBarriers)
4318 {
4319 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4320 struct radv_barrier_info info;
4321
4322 info.eventCount = 0;
4323 info.pEvents = NULL;
4324 info.srcStageMask = srcStageMask;
4325
4326 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4327 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4328 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4329 }
4330
4331
4332 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4333 struct radv_event *event,
4334 VkPipelineStageFlags stageMask,
4335 unsigned value)
4336 {
4337 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4338 uint64_t va = radv_buffer_get_va(event->bo);
4339
4340 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4341
4342 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4343
4344 /* Flags that only require a top-of-pipe event. */
4345 VkPipelineStageFlags top_of_pipe_flags =
4346 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
4347
4348 /* Flags that only require a post-index-fetch event. */
4349 VkPipelineStageFlags post_index_fetch_flags =
4350 top_of_pipe_flags |
4351 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
4352 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
4353
4354 /* Make sure CP DMA is idle because the driver might have performed a
4355 * DMA operation for copying or filling buffers/images.
4356 */
4357 si_cp_dma_wait_for_idle(cmd_buffer);
4358
4359 /* TODO: Emit EOS events for syncing PS/CS stages. */
4360
4361 if (!(stageMask & ~top_of_pipe_flags)) {
4362 /* Just need to sync the PFP engine. */
4363 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4364 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
4365 S_370_WR_CONFIRM(1) |
4366 S_370_ENGINE_SEL(V_370_PFP));
4367 radeon_emit(cs, va);
4368 radeon_emit(cs, va >> 32);
4369 radeon_emit(cs, value);
4370 } else if (!(stageMask & ~post_index_fetch_flags)) {
4371 /* Sync ME because PFP reads index and indirect buffers. */
4372 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4373 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
4374 S_370_WR_CONFIRM(1) |
4375 S_370_ENGINE_SEL(V_370_ME));
4376 radeon_emit(cs, va);
4377 radeon_emit(cs, va >> 32);
4378 radeon_emit(cs, value);
4379 } else {
4380 /* Otherwise, sync all prior GPU work using an EOP event. */
4381 si_cs_emit_write_event_eop(cs,
4382 cmd_buffer->device->physical_device->rad_info.chip_class,
4383 radv_cmd_buffer_uses_mec(cmd_buffer),
4384 V_028A90_BOTTOM_OF_PIPE_TS, 0,
4385 EOP_DATA_SEL_VALUE_32BIT, va, 2, value,
4386 cmd_buffer->gfx9_eop_bug_va);
4387 }
4388
4389 assert(cmd_buffer->cs->cdw <= cdw_max);
4390 }
4391
4392 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4393 VkEvent _event,
4394 VkPipelineStageFlags stageMask)
4395 {
4396 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4397 RADV_FROM_HANDLE(radv_event, event, _event);
4398
4399 write_event(cmd_buffer, event, stageMask, 1);
4400 }
4401
4402 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4403 VkEvent _event,
4404 VkPipelineStageFlags stageMask)
4405 {
4406 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4407 RADV_FROM_HANDLE(radv_event, event, _event);
4408
4409 write_event(cmd_buffer, event, stageMask, 0);
4410 }
4411
4412 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4413 uint32_t eventCount,
4414 const VkEvent* pEvents,
4415 VkPipelineStageFlags srcStageMask,
4416 VkPipelineStageFlags dstStageMask,
4417 uint32_t memoryBarrierCount,
4418 const VkMemoryBarrier* pMemoryBarriers,
4419 uint32_t bufferMemoryBarrierCount,
4420 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4421 uint32_t imageMemoryBarrierCount,
4422 const VkImageMemoryBarrier* pImageMemoryBarriers)
4423 {
4424 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4425 struct radv_barrier_info info;
4426
4427 info.eventCount = eventCount;
4428 info.pEvents = pEvents;
4429 info.srcStageMask = 0;
4430
4431 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4432 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4433 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4434 }
4435
4436
4437 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4438 uint32_t deviceMask)
4439 {
4440 /* No-op */
4441 }
4442
4443 /* VK_EXT_conditional_rendering */
4444 void radv_CmdBeginConditionalRenderingEXT(
4445 VkCommandBuffer commandBuffer,
4446 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
4447 {
4448 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4449 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
4450 bool draw_visible = true;
4451 uint64_t va;
4452
4453 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
4454
4455 /* By default, if the 32-bit value at offset in buffer memory is zero,
4456 * then the rendering commands are discarded, otherwise they are
4457 * executed as normal. If the inverted flag is set, all commands are
4458 * discarded if the value is non zero.
4459 */
4460 if (pConditionalRenderingBegin->flags &
4461 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
4462 draw_visible = false;
4463 }
4464
4465 /* Enable predication for this command buffer. */
4466 si_emit_set_predication_state(cmd_buffer, draw_visible, va);
4467 cmd_buffer->state.predicating = true;
4468
4469 /* Store conditional rendering user info. */
4470 cmd_buffer->state.predication_type = draw_visible;
4471 cmd_buffer->state.predication_va = va;
4472 }
4473
4474 void radv_CmdEndConditionalRenderingEXT(
4475 VkCommandBuffer commandBuffer)
4476 {
4477 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4478
4479 /* Disable predication for this command buffer. */
4480 si_emit_set_predication_state(cmd_buffer, false, 0);
4481 cmd_buffer->state.predicating = false;
4482
4483 /* Reset conditional rendering user info. */
4484 cmd_buffer->state.predication_type = -1;
4485 cmd_buffer->state.predication_va = 0;
4486 }