projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: remove radv_layout_has_htile() helper
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 bool src_render_loop,
58 VkImageLayout dst_layout,
59 bool dst_render_loop,
60 uint32_t src_family,
61 uint32_t dst_family,
62 const VkImageSubresourceRange *range,
63 struct radv_sample_locations_state *sample_locs);
64
65 const struct radv_dynamic_state default_dynamic_state = {
66 .viewport = {
67 .count = 0,
68 },
69 .scissor = {
70 .count = 0,
71 },
72 .line_width = 1.0f,
73 .depth_bias = {
74 .bias = 0.0f,
75 .clamp = 0.0f,
76 .slope = 0.0f,
77 },
78 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
79 .depth_bounds = {
80 .min = 0.0f,
81 .max = 1.0f,
82 },
83 .stencil_compare_mask = {
84 .front = ~0u,
85 .back = ~0u,
86 },
87 .stencil_write_mask = {
88 .front = ~0u,
89 .back = ~0u,
90 },
91 .stencil_reference = {
92 .front = 0u,
93 .back = 0u,
94 },
95 .line_stipple = {
96 .factor = 0u,
97 .pattern = 0u,
98 },
99 };
100
101 static void
102 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
103 const struct radv_dynamic_state *src)
104 {
105 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
106 uint32_t copy_mask = src->mask;
107 uint32_t dest_mask = 0;
108
109 /* Make sure to copy the number of viewports/scissors because they can
110 * only be specified at pipeline creation time.
111 */
112 dest->viewport.count = src->viewport.count;
113 dest->scissor.count = src->scissor.count;
114 dest->discard_rectangle.count = src->discard_rectangle.count;
115 dest->sample_location.count = src->sample_location.count;
116
117 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
118 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
119 src->viewport.count * sizeof(VkViewport))) {
120 typed_memcpy(dest->viewport.viewports,
121 src->viewport.viewports,
122 src->viewport.count);
123 dest_mask |= RADV_DYNAMIC_VIEWPORT;
124 }
125 }
126
127 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
128 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
129 src->scissor.count * sizeof(VkRect2D))) {
130 typed_memcpy(dest->scissor.scissors,
131 src->scissor.scissors, src->scissor.count);
132 dest_mask |= RADV_DYNAMIC_SCISSOR;
133 }
134 }
135
136 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
137 if (dest->line_width != src->line_width) {
138 dest->line_width = src->line_width;
139 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
140 }
141 }
142
143 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
144 if (memcmp(&dest->depth_bias, &src->depth_bias,
145 sizeof(src->depth_bias))) {
146 dest->depth_bias = src->depth_bias;
147 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
148 }
149 }
150
151 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
152 if (memcmp(&dest->blend_constants, &src->blend_constants,
153 sizeof(src->blend_constants))) {
154 typed_memcpy(dest->blend_constants,
155 src->blend_constants, 4);
156 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
157 }
158 }
159
160 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
161 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
162 sizeof(src->depth_bounds))) {
163 dest->depth_bounds = src->depth_bounds;
164 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
165 }
166 }
167
168 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
169 if (memcmp(&dest->stencil_compare_mask,
170 &src->stencil_compare_mask,
171 sizeof(src->stencil_compare_mask))) {
172 dest->stencil_compare_mask = src->stencil_compare_mask;
173 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
174 }
175 }
176
177 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
178 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
179 sizeof(src->stencil_write_mask))) {
180 dest->stencil_write_mask = src->stencil_write_mask;
181 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
182 }
183 }
184
185 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
186 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
187 sizeof(src->stencil_reference))) {
188 dest->stencil_reference = src->stencil_reference;
189 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
190 }
191 }
192
193 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
194 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
195 src->discard_rectangle.count * sizeof(VkRect2D))) {
196 typed_memcpy(dest->discard_rectangle.rectangles,
197 src->discard_rectangle.rectangles,
198 src->discard_rectangle.count);
199 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
200 }
201 }
202
203 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
204 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
205 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
206 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
207 memcmp(&dest->sample_location.locations,
208 &src->sample_location.locations,
209 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
210 dest->sample_location.per_pixel = src->sample_location.per_pixel;
211 dest->sample_location.grid_size = src->sample_location.grid_size;
212 typed_memcpy(dest->sample_location.locations,
213 src->sample_location.locations,
214 src->sample_location.count);
215 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
216 }
217 }
218
219 if (copy_mask & RADV_DYNAMIC_LINE_STIPPLE) {
220 if (memcmp(&dest->line_stipple, &src->line_stipple,
221 sizeof(src->line_stipple))) {
222 dest->line_stipple = src->line_stipple;
223 dest_mask |= RADV_DYNAMIC_LINE_STIPPLE;
224 }
225 }
226
227 cmd_buffer->state.dirty |= dest_mask;
228 }
229
230 static void
231 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
232 struct radv_pipeline *pipeline)
233 {
234 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
235 struct radv_shader_info *info;
236
237 if (!pipeline->streamout_shader ||
238 cmd_buffer->device->physical_device->use_ngg_streamout)
239 return;
240
241 info = &pipeline->streamout_shader->info;
242 for (int i = 0; i < MAX_SO_BUFFERS; i++)
243 so->stride_in_dw[i] = info->so.strides[i];
244
245 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
246 }
247
248 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
249 {
250 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
251 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
252 }
253
254 enum ring_type radv_queue_family_to_ring(int f) {
255 switch (f) {
256 case RADV_QUEUE_GENERAL:
257 return RING_GFX;
258 case RADV_QUEUE_COMPUTE:
259 return RING_COMPUTE;
260 case RADV_QUEUE_TRANSFER:
261 return RING_DMA;
262 default:
263 unreachable("Unknown queue family");
264 }
265 }
266
267 static VkResult radv_create_cmd_buffer(
268 struct radv_device * device,
269 struct radv_cmd_pool * pool,
270 VkCommandBufferLevel level,
271 VkCommandBuffer* pCommandBuffer)
272 {
273 struct radv_cmd_buffer *cmd_buffer;
274 unsigned ring;
275 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
276 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
277 if (cmd_buffer == NULL)
278 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
279
280 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
281 cmd_buffer->device = device;
282 cmd_buffer->pool = pool;
283 cmd_buffer->level = level;
284
285 if (pool) {
286 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
287 cmd_buffer->queue_family_index = pool->queue_family_index;
288
289 } else {
290 /* Init the pool_link so we can safely call list_del when we destroy
291 * the command buffer
292 */
293 list_inithead(&cmd_buffer->pool_link);
294 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
295 }
296
297 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
298
299 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
300 if (!cmd_buffer->cs) {
301 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
302 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
303 }
304
305 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
306
307 list_inithead(&cmd_buffer->upload.list);
308
309 return VK_SUCCESS;
310 }
311
312 static void
313 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
314 {
315 list_del(&cmd_buffer->pool_link);
316
317 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
318 &cmd_buffer->upload.list, list) {
319 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
320 list_del(&up->list);
321 free(up);
322 }
323
324 if (cmd_buffer->upload.upload_bo)
325 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
326 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
327
328 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
329 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
330
331 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
332 }
333
334 static VkResult
335 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
336 {
337 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
338
339 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
340 &cmd_buffer->upload.list, list) {
341 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
342 list_del(&up->list);
343 free(up);
344 }
345
346 cmd_buffer->push_constant_stages = 0;
347 cmd_buffer->scratch_size_per_wave_needed = 0;
348 cmd_buffer->scratch_waves_wanted = 0;
349 cmd_buffer->compute_scratch_size_per_wave_needed = 0;
350 cmd_buffer->compute_scratch_waves_wanted = 0;
351 cmd_buffer->esgs_ring_size_needed = 0;
352 cmd_buffer->gsvs_ring_size_needed = 0;
353 cmd_buffer->tess_rings_needed = false;
354 cmd_buffer->gds_needed = false;
355 cmd_buffer->gds_oa_needed = false;
356 cmd_buffer->sample_positions_needed = false;
357
358 if (cmd_buffer->upload.upload_bo)
359 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
360 cmd_buffer->upload.upload_bo);
361 cmd_buffer->upload.offset = 0;
362
363 cmd_buffer->record_result = VK_SUCCESS;
364
365 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
366
367 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
368 cmd_buffer->descriptors[i].dirty = 0;
369 cmd_buffer->descriptors[i].valid = 0;
370 cmd_buffer->descriptors[i].push_dirty = false;
371 }
372
373 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
374 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
375 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
376 unsigned fence_offset, eop_bug_offset;
377 void *fence_ptr;
378
379 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
380 &fence_ptr);
381
382 cmd_buffer->gfx9_fence_va =
383 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
384 cmd_buffer->gfx9_fence_va += fence_offset;
385
386 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
387 /* Allocate a buffer for the EOP bug on GFX9. */
388 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
389 &eop_bug_offset, &fence_ptr);
390 cmd_buffer->gfx9_eop_bug_va =
391 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
392 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
393 }
394 }
395
396 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
397
398 return cmd_buffer->record_result;
399 }
400
401 static bool
402 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
403 uint64_t min_needed)
404 {
405 uint64_t new_size;
406 struct radeon_winsys_bo *bo;
407 struct radv_cmd_buffer_upload *upload;
408 struct radv_device *device = cmd_buffer->device;
409
410 new_size = MAX2(min_needed, 16 * 1024);
411 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
412
413 bo = device->ws->buffer_create(device->ws,
414 new_size, 4096,
415 RADEON_DOMAIN_GTT,
416 RADEON_FLAG_CPU_ACCESS|
417 RADEON_FLAG_NO_INTERPROCESS_SHARING |
418 RADEON_FLAG_32BIT,
419 RADV_BO_PRIORITY_UPLOAD_BUFFER);
420
421 if (!bo) {
422 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
423 return false;
424 }
425
426 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
427 if (cmd_buffer->upload.upload_bo) {
428 upload = malloc(sizeof(*upload));
429
430 if (!upload) {
431 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
432 device->ws->buffer_destroy(bo);
433 return false;
434 }
435
436 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
437 list_add(&upload->list, &cmd_buffer->upload.list);
438 }
439
440 cmd_buffer->upload.upload_bo = bo;
441 cmd_buffer->upload.size = new_size;
442 cmd_buffer->upload.offset = 0;
443 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
444
445 if (!cmd_buffer->upload.map) {
446 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
447 return false;
448 }
449
450 return true;
451 }
452
453 bool
454 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
455 unsigned size,
456 unsigned alignment,
457 unsigned *out_offset,
458 void **ptr)
459 {
460 assert(util_is_power_of_two_nonzero(alignment));
461
462 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
463 if (offset + size > cmd_buffer->upload.size) {
464 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
465 return false;
466 offset = 0;
467 }
468
469 *out_offset = offset;
470 *ptr = cmd_buffer->upload.map + offset;
471
472 cmd_buffer->upload.offset = offset + size;
473 return true;
474 }
475
476 bool
477 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
478 unsigned size, unsigned alignment,
479 const void *data, unsigned *out_offset)
480 {
481 uint8_t *ptr;
482
483 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
484 out_offset, (void **)&ptr))
485 return false;
486
487 if (ptr)
488 memcpy(ptr, data, size);
489
490 return true;
491 }
492
493 static void
494 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
495 unsigned count, const uint32_t *data)
496 {
497 struct radeon_cmdbuf *cs = cmd_buffer->cs;
498
499 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
500
501 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
502 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
503 S_370_WR_CONFIRM(1) |
504 S_370_ENGINE_SEL(V_370_ME));
505 radeon_emit(cs, va);
506 radeon_emit(cs, va >> 32);
507 radeon_emit_array(cs, data, count);
508 }
509
510 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
511 {
512 struct radv_device *device = cmd_buffer->device;
513 struct radeon_cmdbuf *cs = cmd_buffer->cs;
514 uint64_t va;
515
516 va = radv_buffer_get_va(device->trace_bo);
517 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
518 va += 4;
519
520 ++cmd_buffer->state.trace_id;
521 radv_emit_write_data_packet(cmd_buffer, va, 1,
522 &cmd_buffer->state.trace_id);
523
524 radeon_check_space(cmd_buffer->device->ws, cs, 2);
525
526 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
527 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
528 }
529
530 static void
531 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
532 enum radv_cmd_flush_bits flags)
533 {
534 if (unlikely(cmd_buffer->device->thread_trace_bo)) {
535 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
536 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_THREAD_TRACE_MARKER) | EVENT_INDEX(0));
537 }
538
539 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
540 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
541 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
542
543 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
544
545 /* Force wait for graphics or compute engines to be idle. */
546 si_cs_emit_cache_flush(cmd_buffer->cs,
547 cmd_buffer->device->physical_device->rad_info.chip_class,
548 &cmd_buffer->gfx9_fence_idx,
549 cmd_buffer->gfx9_fence_va,
550 radv_cmd_buffer_uses_mec(cmd_buffer),
551 flags, cmd_buffer->gfx9_eop_bug_va);
552 }
553
554 if (unlikely(cmd_buffer->device->trace_bo))
555 radv_cmd_buffer_trace_emit(cmd_buffer);
556 }
557
558 static void
559 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
560 struct radv_pipeline *pipeline, enum ring_type ring)
561 {
562 struct radv_device *device = cmd_buffer->device;
563 uint32_t data[2];
564 uint64_t va;
565
566 va = radv_buffer_get_va(device->trace_bo);
567
568 switch (ring) {
569 case RING_GFX:
570 va += 8;
571 break;
572 case RING_COMPUTE:
573 va += 16;
574 break;
575 default:
576 assert(!"invalid ring type");
577 }
578
579 uint64_t pipeline_address = (uintptr_t)pipeline;
580 data[0] = pipeline_address;
581 data[1] = pipeline_address >> 32;
582
583 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
584 }
585
586 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
587 VkPipelineBindPoint bind_point,
588 struct radv_descriptor_set *set,
589 unsigned idx)
590 {
591 struct radv_descriptor_state *descriptors_state =
592 radv_get_descriptors_state(cmd_buffer, bind_point);
593
594 descriptors_state->sets[idx] = set;
595
596 descriptors_state->valid |= (1u << idx); /* active descriptors */
597 descriptors_state->dirty |= (1u << idx);
598 }
599
600 static void
601 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
602 VkPipelineBindPoint bind_point)
603 {
604 struct radv_descriptor_state *descriptors_state =
605 radv_get_descriptors_state(cmd_buffer, bind_point);
606 struct radv_device *device = cmd_buffer->device;
607 uint32_t data[MAX_SETS * 2] = {};
608 uint64_t va;
609 unsigned i;
610 va = radv_buffer_get_va(device->trace_bo) + 24;
611
612 for_each_bit(i, descriptors_state->valid) {
613 struct radv_descriptor_set *set = descriptors_state->sets[i];
614 data[i * 2] = (uint64_t)(uintptr_t)set;
615 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
616 }
617
618 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
619 }
620
621 struct radv_userdata_info *
622 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
623 gl_shader_stage stage,
624 int idx)
625 {
626 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
627 return &shader->info.user_sgprs_locs.shader_data[idx];
628 }
629
630 static void
631 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
632 struct radv_pipeline *pipeline,
633 gl_shader_stage stage,
634 int idx, uint64_t va)
635 {
636 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
637 uint32_t base_reg = pipeline->user_data_0[stage];
638 if (loc->sgpr_idx == -1)
639 return;
640
641 assert(loc->num_sgprs == 1);
642
643 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
644 base_reg + loc->sgpr_idx * 4, va, false);
645 }
646
647 static void
648 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
649 struct radv_pipeline *pipeline,
650 struct radv_descriptor_state *descriptors_state,
651 gl_shader_stage stage)
652 {
653 struct radv_device *device = cmd_buffer->device;
654 struct radeon_cmdbuf *cs = cmd_buffer->cs;
655 uint32_t sh_base = pipeline->user_data_0[stage];
656 struct radv_userdata_locations *locs =
657 &pipeline->shaders[stage]->info.user_sgprs_locs;
658 unsigned mask = locs->descriptor_sets_enabled;
659
660 mask &= descriptors_state->dirty & descriptors_state->valid;
661
662 while (mask) {
663 int start, count;
664
665 u_bit_scan_consecutive_range(&mask, &start, &count);
666
667 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
668 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
669
670 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
671 for (int i = 0; i < count; i++) {
672 struct radv_descriptor_set *set =
673 descriptors_state->sets[start + i];
674
675 radv_emit_shader_pointer_body(device, cs, set->va, true);
676 }
677 }
678 }
679
680 /**
681 * Convert the user sample locations to hardware sample locations (the values
682 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
683 */
684 static void
685 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
686 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
687 {
688 uint32_t x_offset = x % state->grid_size.width;
689 uint32_t y_offset = y % state->grid_size.height;
690 uint32_t num_samples = (uint32_t)state->per_pixel;
691 VkSampleLocationEXT *user_locs;
692 uint32_t pixel_offset;
693
694 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
695
696 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
697 user_locs = &state->locations[pixel_offset];
698
699 for (uint32_t i = 0; i < num_samples; i++) {
700 float shifted_pos_x = user_locs[i].x - 0.5;
701 float shifted_pos_y = user_locs[i].y - 0.5;
702
703 int32_t scaled_pos_x = floor(shifted_pos_x * 16);
704 int32_t scaled_pos_y = floor(shifted_pos_y * 16);
705
706 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
707 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
708 }
709 }
710
711 /**
712 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
713 * locations.
714 */
715 static void
716 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
717 uint32_t *sample_locs_pixel)
718 {
719 for (uint32_t i = 0; i < num_samples; i++) {
720 uint32_t sample_reg_idx = i / 4;
721 uint32_t sample_loc_idx = i % 4;
722 int32_t pos_x = sample_locs[i].x;
723 int32_t pos_y = sample_locs[i].y;
724
725 uint32_t shift_x = 8 * sample_loc_idx;
726 uint32_t shift_y = shift_x + 4;
727
728 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
729 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
730 }
731 }
732
733 /**
734 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
735 * sample locations.
736 */
737 static uint64_t
738 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
739 VkOffset2D *sample_locs,
740 uint32_t num_samples)
741 {
742 uint32_t centroid_priorities[num_samples];
743 uint32_t sample_mask = num_samples - 1;
744 uint32_t distances[num_samples];
745 uint64_t centroid_priority = 0;
746
747 /* Compute the distances from center for each sample. */
748 for (int i = 0; i < num_samples; i++) {
749 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
750 (sample_locs[i].y * sample_locs[i].y);
751 }
752
753 /* Compute the centroid priorities by looking at the distances array. */
754 for (int i = 0; i < num_samples; i++) {
755 uint32_t min_idx = 0;
756
757 for (int j = 1; j < num_samples; j++) {
758 if (distances[j] < distances[min_idx])
759 min_idx = j;
760 }
761
762 centroid_priorities[i] = min_idx;
763 distances[min_idx] = 0xffffffff;
764 }
765
766 /* Compute the final centroid priority. */
767 for (int i = 0; i < 8; i++) {
768 centroid_priority |=
769 centroid_priorities[i & sample_mask] << (i * 4);
770 }
771
772 return centroid_priority << 32 | centroid_priority;
773 }
774
775 /**
776 * Emit the sample locations that are specified with VK_EXT_sample_locations.
777 */
778 static void
779 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
780 {
781 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
782 struct radv_multisample_state *ms = &pipeline->graphics.ms;
783 struct radv_sample_locations_state *sample_location =
784 &cmd_buffer->state.dynamic.sample_location;
785 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
786 struct radeon_cmdbuf *cs = cmd_buffer->cs;
787 uint32_t sample_locs_pixel[4][2] = {};
788 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
789 uint32_t max_sample_dist = 0;
790 uint64_t centroid_priority;
791
792 if (!cmd_buffer->state.dynamic.sample_location.count)
793 return;
794
795 /* Convert the user sample locations to hardware sample locations. */
796 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
797 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
798 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
799 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
800
801 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
802 for (uint32_t i = 0; i < 4; i++) {
803 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
804 sample_locs_pixel[i]);
805 }
806
807 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
808 centroid_priority =
809 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
810 num_samples);
811
812 /* Compute the maximum sample distance from the specified locations. */
813 for (uint32_t i = 0; i < num_samples; i++) {
814 VkOffset2D offset = sample_locs[0][i];
815 max_sample_dist = MAX2(max_sample_dist,
816 MAX2(abs(offset.x), abs(offset.y)));
817 }
818
819 /* Emit the specified user sample locations. */
820 switch (num_samples) {
821 case 2:
822 case 4:
823 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
824 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
825 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
826 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
827 break;
828 case 8:
829 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
830 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
831 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
832 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
833 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
834 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
835 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
836 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
837 break;
838 default:
839 unreachable("invalid number of samples");
840 }
841
842 /* Emit the maximum sample distance and the centroid priority. */
843 uint32_t pa_sc_aa_config = ms->pa_sc_aa_config;
844
845 pa_sc_aa_config &= C_028BE0_MAX_SAMPLE_DIST;
846 pa_sc_aa_config |= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist);
847
848 radeon_set_context_reg_seq(cs, R_028BE0_PA_SC_AA_CONFIG, 1);
849 radeon_emit(cs, pa_sc_aa_config);
850
851 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
852 radeon_emit(cs, centroid_priority);
853 radeon_emit(cs, centroid_priority >> 32);
854
855 /* GFX9: Flush DFSM when the AA mode changes. */
856 if (cmd_buffer->device->dfsm_allowed) {
857 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
858 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
859 }
860
861 cmd_buffer->state.context_roll_without_scissor_emitted = true;
862 }
863
864 static void
865 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
866 struct radv_pipeline *pipeline,
867 gl_shader_stage stage,
868 int idx, int count, uint32_t *values)
869 {
870 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
871 uint32_t base_reg = pipeline->user_data_0[stage];
872 if (loc->sgpr_idx == -1)
873 return;
874
875 assert(loc->num_sgprs == count);
876
877 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
878 radeon_emit_array(cmd_buffer->cs, values, count);
879 }
880
881 static void
882 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
883 struct radv_pipeline *pipeline)
884 {
885 int num_samples = pipeline->graphics.ms.num_samples;
886 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
887
888 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.needs_sample_positions)
889 cmd_buffer->sample_positions_needed = true;
890
891 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
892 return;
893
894 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
895
896 cmd_buffer->state.context_roll_without_scissor_emitted = true;
897 }
898
899 static void
900 radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer,
901 struct radv_pipeline *pipeline)
902 {
903 const struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
904
905
906 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
907 return;
908
909 if (old_pipeline &&
910 old_pipeline->graphics.binning.pa_sc_binner_cntl_0 == pipeline->graphics.binning.pa_sc_binner_cntl_0 &&
911 old_pipeline->graphics.binning.db_dfsm_control == pipeline->graphics.binning.db_dfsm_control)
912 return;
913
914 bool binning_flush = false;
915 if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 ||
916 cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 ||
917 cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 ||
918 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
919 binning_flush = !old_pipeline ||
920 G_028C44_BINNING_MODE(old_pipeline->graphics.binning.pa_sc_binner_cntl_0) !=
921 G_028C44_BINNING_MODE(pipeline->graphics.binning.pa_sc_binner_cntl_0);
922 }
923
924 radeon_set_context_reg(cmd_buffer->cs, R_028C44_PA_SC_BINNER_CNTL_0,
925 pipeline->graphics.binning.pa_sc_binner_cntl_0 |
926 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush));
927
928 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
929 radeon_set_context_reg(cmd_buffer->cs, R_028038_DB_DFSM_CONTROL,
930 pipeline->graphics.binning.db_dfsm_control);
931 } else {
932 radeon_set_context_reg(cmd_buffer->cs, R_028060_DB_DFSM_CONTROL,
933 pipeline->graphics.binning.db_dfsm_control);
934 }
935
936 cmd_buffer->state.context_roll_without_scissor_emitted = true;
937 }
938
939
940 static void
941 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
942 struct radv_shader_variant *shader)
943 {
944 uint64_t va;
945
946 if (!shader)
947 return;
948
949 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
950
951 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
952 }
953
954 static void
955 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
956 struct radv_pipeline *pipeline,
957 bool vertex_stage_only)
958 {
959 struct radv_cmd_state *state = &cmd_buffer->state;
960 uint32_t mask = state->prefetch_L2_mask;
961
962 if (vertex_stage_only) {
963 /* Fast prefetch path for starting draws as soon as possible.
964 */
965 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
966 RADV_PREFETCH_VBO_DESCRIPTORS);
967 }
968
969 if (mask & RADV_PREFETCH_VS)
970 radv_emit_shader_prefetch(cmd_buffer,
971 pipeline->shaders[MESA_SHADER_VERTEX]);
972
973 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
974 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
975
976 if (mask & RADV_PREFETCH_TCS)
977 radv_emit_shader_prefetch(cmd_buffer,
978 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
979
980 if (mask & RADV_PREFETCH_TES)
981 radv_emit_shader_prefetch(cmd_buffer,
982 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
983
984 if (mask & RADV_PREFETCH_GS) {
985 radv_emit_shader_prefetch(cmd_buffer,
986 pipeline->shaders[MESA_SHADER_GEOMETRY]);
987 if (radv_pipeline_has_gs_copy_shader(pipeline))
988 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
989 }
990
991 if (mask & RADV_PREFETCH_PS)
992 radv_emit_shader_prefetch(cmd_buffer,
993 pipeline->shaders[MESA_SHADER_FRAGMENT]);
994
995 state->prefetch_L2_mask &= ~mask;
996 }
997
998 static void
999 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
1000 {
1001 if (!cmd_buffer->device->physical_device->rad_info.rbplus_allowed)
1002 return;
1003
1004 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1005 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1006
1007 unsigned sx_ps_downconvert = 0;
1008 unsigned sx_blend_opt_epsilon = 0;
1009 unsigned sx_blend_opt_control = 0;
1010
1011 if (!cmd_buffer->state.attachments || !subpass)
1012 return;
1013
1014 for (unsigned i = 0; i < subpass->color_count; ++i) {
1015 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1016 /* We don't set the DISABLE bits, because the HW can't have holes,
1017 * so the SPI color format is set to 32-bit 1-component. */
1018 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1019 continue;
1020 }
1021
1022 int idx = subpass->color_attachments[i].attachment;
1023 struct radv_color_buffer_info *cb = &cmd_buffer->state.attachments[idx].cb;
1024
1025 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
1026 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
1027 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
1028 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
1029
1030 bool has_alpha, has_rgb;
1031
1032 /* Set if RGB and A are present. */
1033 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
1034
1035 if (format == V_028C70_COLOR_8 ||
1036 format == V_028C70_COLOR_16 ||
1037 format == V_028C70_COLOR_32)
1038 has_rgb = !has_alpha;
1039 else
1040 has_rgb = true;
1041
1042 /* Check the colormask and export format. */
1043 if (!(colormask & 0x7))
1044 has_rgb = false;
1045 if (!(colormask & 0x8))
1046 has_alpha = false;
1047
1048 if (spi_format == V_028714_SPI_SHADER_ZERO) {
1049 has_rgb = false;
1050 has_alpha = false;
1051 }
1052
1053 /* Disable value checking for disabled channels. */
1054 if (!has_rgb)
1055 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1056 if (!has_alpha)
1057 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1058
1059 /* Enable down-conversion for 32bpp and smaller formats. */
1060 switch (format) {
1061 case V_028C70_COLOR_8:
1062 case V_028C70_COLOR_8_8:
1063 case V_028C70_COLOR_8_8_8_8:
1064 /* For 1 and 2-channel formats, use the superset thereof. */
1065 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1066 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1067 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1068 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1069 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1070 }
1071 break;
1072
1073 case V_028C70_COLOR_5_6_5:
1074 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1075 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1076 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1077 }
1078 break;
1079
1080 case V_028C70_COLOR_1_5_5_5:
1081 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1082 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1083 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1084 }
1085 break;
1086
1087 case V_028C70_COLOR_4_4_4_4:
1088 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1089 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1090 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1091 }
1092 break;
1093
1094 case V_028C70_COLOR_32:
1095 if (swap == V_028C70_SWAP_STD &&
1096 spi_format == V_028714_SPI_SHADER_32_R)
1097 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1098 else if (swap == V_028C70_SWAP_ALT_REV &&
1099 spi_format == V_028714_SPI_SHADER_32_AR)
1100 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1101 break;
1102
1103 case V_028C70_COLOR_16:
1104 case V_028C70_COLOR_16_16:
1105 /* For 1-channel formats, use the superset thereof. */
1106 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1107 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1108 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1109 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1110 if (swap == V_028C70_SWAP_STD ||
1111 swap == V_028C70_SWAP_STD_REV)
1112 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1113 else
1114 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1115 }
1116 break;
1117
1118 case V_028C70_COLOR_10_11_11:
1119 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1120 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1121 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1122 }
1123 break;
1124
1125 case V_028C70_COLOR_2_10_10_10:
1126 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1127 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1128 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1129 }
1130 break;
1131 }
1132 }
1133
1134 /* Do not set the DISABLE bits for the unused attachments, as that
1135 * breaks dual source blending in SkQP and does not seem to improve
1136 * performance. */
1137
1138 if (sx_ps_downconvert == cmd_buffer->state.last_sx_ps_downconvert &&
1139 sx_blend_opt_epsilon == cmd_buffer->state.last_sx_blend_opt_epsilon &&
1140 sx_blend_opt_control == cmd_buffer->state.last_sx_blend_opt_control)
1141 return;
1142
1143 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1144 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1145 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1146 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1147
1148 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1149
1150 cmd_buffer->state.last_sx_ps_downconvert = sx_ps_downconvert;
1151 cmd_buffer->state.last_sx_blend_opt_epsilon = sx_blend_opt_epsilon;
1152 cmd_buffer->state.last_sx_blend_opt_control = sx_blend_opt_control;
1153 }
1154
1155 static void
1156 radv_emit_batch_break_on_new_ps(struct radv_cmd_buffer *cmd_buffer)
1157 {
1158 if (!cmd_buffer->device->pbb_allowed)
1159 return;
1160
1161 struct radv_binning_settings settings =
1162 radv_get_binning_settings(cmd_buffer->device->physical_device);
1163 bool break_for_new_ps =
1164 (!cmd_buffer->state.emitted_pipeline ||
1165 cmd_buffer->state.emitted_pipeline->shaders[MESA_SHADER_FRAGMENT] !=
1166 cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT]) &&
1167 (settings.context_states_per_bin > 1 ||
1168 settings.persistent_states_per_bin > 1);
1169 bool break_for_new_cb_target_mask =
1170 (!cmd_buffer->state.emitted_pipeline ||
1171 cmd_buffer->state.emitted_pipeline->graphics.cb_target_mask !=
1172 cmd_buffer->state.pipeline->graphics.cb_target_mask) &&
1173 settings.context_states_per_bin > 1;
1174
1175 if (!break_for_new_ps && !break_for_new_cb_target_mask)
1176 return;
1177
1178 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1179 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1180 }
1181
1182 static void
1183 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1184 {
1185 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1186
1187 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1188 return;
1189
1190 radv_update_multisample_state(cmd_buffer, pipeline);
1191 radv_update_binning_state(cmd_buffer, pipeline);
1192
1193 cmd_buffer->scratch_size_per_wave_needed = MAX2(cmd_buffer->scratch_size_per_wave_needed,
1194 pipeline->scratch_bytes_per_wave);
1195 cmd_buffer->scratch_waves_wanted = MAX2(cmd_buffer->scratch_waves_wanted,
1196 pipeline->max_waves);
1197
1198 if (!cmd_buffer->state.emitted_pipeline ||
1199 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1200 pipeline->graphics.can_use_guardband)
1201 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1202
1203 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1204
1205 if (!cmd_buffer->state.emitted_pipeline ||
1206 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1207 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1208 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1209 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1210 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1211 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1212 }
1213
1214 radv_emit_batch_break_on_new_ps(cmd_buffer);
1215
1216 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1217 if (!pipeline->shaders[i])
1218 continue;
1219
1220 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1221 pipeline->shaders[i]->bo);
1222 }
1223
1224 if (radv_pipeline_has_gs_copy_shader(pipeline))
1225 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1226 pipeline->gs_copy_shader->bo);
1227
1228 if (unlikely(cmd_buffer->device->trace_bo))
1229 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1230
1231 cmd_buffer->state.emitted_pipeline = pipeline;
1232
1233 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1234 }
1235
1236 static void
1237 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1238 {
1239 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1240 cmd_buffer->state.dynamic.viewport.viewports);
1241 }
1242
1243 static void
1244 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1245 {
1246 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1247
1248 si_write_scissors(cmd_buffer->cs, 0, count,
1249 cmd_buffer->state.dynamic.scissor.scissors,
1250 cmd_buffer->state.dynamic.viewport.viewports,
1251 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1252
1253 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1254 }
1255
1256 static void
1257 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1258 {
1259 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1260 return;
1261
1262 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1263 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1264 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1265 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1266 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1267 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1268 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1269 }
1270 }
1271
1272 static void
1273 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1274 {
1275 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1276
1277 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1278 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1279 }
1280
1281 static void
1282 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1283 {
1284 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1285
1286 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1287 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1288 }
1289
1290 static void
1291 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1292 {
1293 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1294
1295 radeon_set_context_reg_seq(cmd_buffer->cs,
1296 R_028430_DB_STENCILREFMASK, 2);
1297 radeon_emit(cmd_buffer->cs,
1298 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1299 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1300 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1301 S_028430_STENCILOPVAL(1));
1302 radeon_emit(cmd_buffer->cs,
1303 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1304 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1305 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1306 S_028434_STENCILOPVAL_BF(1));
1307 }
1308
1309 static void
1310 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1311 {
1312 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1313
1314 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1315 fui(d->depth_bounds.min));
1316 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1317 fui(d->depth_bounds.max));
1318 }
1319
1320 static void
1321 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1322 {
1323 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1324 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1325 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1326
1327
1328 radeon_set_context_reg_seq(cmd_buffer->cs,
1329 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1330 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1331 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1332 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1333 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1334 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1335 }
1336
1337 static void
1338 radv_emit_line_stipple(struct radv_cmd_buffer *cmd_buffer)
1339 {
1340 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1341 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1342 uint32_t auto_reset_cntl = 1;
1343
1344 if (pipeline->graphics.topology == VK_PRIMITIVE_TOPOLOGY_LINE_STRIP)
1345 auto_reset_cntl = 2;
1346
1347 radeon_set_context_reg(cmd_buffer->cs, R_028A0C_PA_SC_LINE_STIPPLE,
1348 S_028A0C_LINE_PATTERN(d->line_stipple.pattern) |
1349 S_028A0C_REPEAT_COUNT(d->line_stipple.factor - 1) |
1350 S_028A0C_AUTO_RESET_CNTL(auto_reset_cntl));
1351 }
1352
1353 static void
1354 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1355 int index,
1356 struct radv_color_buffer_info *cb,
1357 struct radv_image_view *iview,
1358 VkImageLayout layout,
1359 bool in_render_loop)
1360 {
1361 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1362 uint32_t cb_color_info = cb->cb_color_info;
1363 struct radv_image *image = iview->image;
1364
1365 if (!radv_layout_dcc_compressed(cmd_buffer->device, image, layout, in_render_loop,
1366 radv_image_queue_family_mask(image,
1367 cmd_buffer->queue_family_index,
1368 cmd_buffer->queue_family_index))) {
1369 cb_color_info &= C_028C70_DCC_ENABLE;
1370 }
1371
1372 if (radv_image_is_tc_compat_cmask(image) &&
1373 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1374 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1375 /* If this bit is set, the FMASK decompression operation
1376 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1377 */
1378 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1379 }
1380
1381 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1382 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1383 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1384 radeon_emit(cmd_buffer->cs, 0);
1385 radeon_emit(cmd_buffer->cs, 0);
1386 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1387 radeon_emit(cmd_buffer->cs, cb_color_info);
1388 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1389 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1390 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1391 radeon_emit(cmd_buffer->cs, 0);
1392 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1393 radeon_emit(cmd_buffer->cs, 0);
1394
1395 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1396 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1397
1398 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1399 cb->cb_color_base >> 32);
1400 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1401 cb->cb_color_cmask >> 32);
1402 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1403 cb->cb_color_fmask >> 32);
1404 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1405 cb->cb_dcc_base >> 32);
1406 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1407 cb->cb_color_attrib2);
1408 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1409 cb->cb_color_attrib3);
1410 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1411 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1412 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1413 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1414 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1415 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1416 radeon_emit(cmd_buffer->cs, cb_color_info);
1417 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1418 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1419 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1420 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1421 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1422 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1423
1424 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1425 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1426 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1427
1428 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1429 cb->cb_mrt_epitch);
1430 } else {
1431 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1432 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1433 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1434 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1435 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1436 radeon_emit(cmd_buffer->cs, cb_color_info);
1437 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1438 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1439 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1440 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1441 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1442 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1443
1444 if (is_vi) { /* DCC BASE */
1445 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1446 }
1447 }
1448
1449 if (radv_dcc_enabled(image, iview->base_mip)) {
1450 /* Drawing with DCC enabled also compresses colorbuffers. */
1451 VkImageSubresourceRange range = {
1452 .aspectMask = iview->aspect_mask,
1453 .baseMipLevel = iview->base_mip,
1454 .levelCount = iview->level_count,
1455 .baseArrayLayer = iview->base_layer,
1456 .layerCount = iview->layer_count,
1457 };
1458
1459 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1460 }
1461 }
1462
1463 static void
1464 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1465 struct radv_ds_buffer_info *ds,
1466 const struct radv_image_view *iview,
1467 VkImageLayout layout,
1468 bool in_render_loop, bool requires_cond_exec)
1469 {
1470 const struct radv_image *image = iview->image;
1471 uint32_t db_z_info = ds->db_z_info;
1472 uint32_t db_z_info_reg;
1473
1474 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug ||
1475 !radv_image_is_tc_compat_htile(image))
1476 return;
1477
1478 if (!radv_layout_is_htile_compressed(image, layout, in_render_loop,
1479 radv_image_queue_family_mask(image,
1480 cmd_buffer->queue_family_index,
1481 cmd_buffer->queue_family_index))) {
1482 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1483 }
1484
1485 db_z_info &= C_028040_ZRANGE_PRECISION;
1486
1487 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1488 db_z_info_reg = R_028038_DB_Z_INFO;
1489 } else {
1490 db_z_info_reg = R_028040_DB_Z_INFO;
1491 }
1492
1493 /* When we don't know the last fast clear value we need to emit a
1494 * conditional packet that will eventually skip the following
1495 * SET_CONTEXT_REG packet.
1496 */
1497 if (requires_cond_exec) {
1498 uint64_t va = radv_get_tc_compat_zrange_va(image, iview->base_mip);
1499
1500 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1501 radeon_emit(cmd_buffer->cs, va);
1502 radeon_emit(cmd_buffer->cs, va >> 32);
1503 radeon_emit(cmd_buffer->cs, 0);
1504 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1505 }
1506
1507 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1508 }
1509
1510 static void
1511 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1512 struct radv_ds_buffer_info *ds,
1513 struct radv_image_view *iview,
1514 VkImageLayout layout,
1515 bool in_render_loop)
1516 {
1517 const struct radv_image *image = iview->image;
1518 uint32_t db_z_info = ds->db_z_info;
1519 uint32_t db_stencil_info = ds->db_stencil_info;
1520
1521 if (!radv_layout_is_htile_compressed(image, layout, in_render_loop,
1522 radv_image_queue_family_mask(image,
1523 cmd_buffer->queue_family_index,
1524 cmd_buffer->queue_family_index))) {
1525 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1526 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1527 }
1528
1529 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1530 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1531
1532 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1533 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1534 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1535
1536 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1537 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1538 radeon_emit(cmd_buffer->cs, db_z_info);
1539 radeon_emit(cmd_buffer->cs, db_stencil_info);
1540 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1541 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1542 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1543 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1544
1545 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 5);
1546 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1547 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1548 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1549 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1550 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1551 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1552 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1553 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1554 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1555 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1556
1557 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1558 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1559 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1560 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1561 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1562 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1563 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1564 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1565 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1566 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1567 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1568
1569 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1570 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1571 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1572 } else {
1573 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1574
1575 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1576 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1577 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1578 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1579 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1580 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1581 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1582 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1583 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1584 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1585
1586 }
1587
1588 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1589 radv_update_zrange_precision(cmd_buffer, ds, iview, layout,
1590 in_render_loop, true);
1591
1592 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1593 ds->pa_su_poly_offset_db_fmt_cntl);
1594 }
1595
1596 /**
1597 * Update the fast clear depth/stencil values if the image is bound as a
1598 * depth/stencil buffer.
1599 */
1600 static void
1601 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1602 const struct radv_image_view *iview,
1603 VkClearDepthStencilValue ds_clear_value,
1604 VkImageAspectFlags aspects)
1605 {
1606 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1607 const struct radv_image *image = iview->image;
1608 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1609 uint32_t att_idx;
1610
1611 if (!cmd_buffer->state.attachments || !subpass)
1612 return;
1613
1614 if (!subpass->depth_stencil_attachment)
1615 return;
1616
1617 att_idx = subpass->depth_stencil_attachment->attachment;
1618 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1619 return;
1620
1621 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1622 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1623 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1624 radeon_emit(cs, ds_clear_value.stencil);
1625 radeon_emit(cs, fui(ds_clear_value.depth));
1626 } else if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1627 radeon_set_context_reg_seq(cs, R_02802C_DB_DEPTH_CLEAR, 1);
1628 radeon_emit(cs, fui(ds_clear_value.depth));
1629 } else {
1630 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1631 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 1);
1632 radeon_emit(cs, ds_clear_value.stencil);
1633 }
1634
1635 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1636 * only needed when clearing Z to 0.0.
1637 */
1638 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1639 ds_clear_value.depth == 0.0) {
1640 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1641 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1642
1643 radv_update_zrange_precision(cmd_buffer, &cmd_buffer->state.attachments[att_idx].ds,
1644 iview, layout, in_render_loop, false);
1645 }
1646
1647 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1648 }
1649
1650 /**
1651 * Set the clear depth/stencil values to the image's metadata.
1652 */
1653 static void
1654 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1655 struct radv_image *image,
1656 const VkImageSubresourceRange *range,
1657 VkClearDepthStencilValue ds_clear_value,
1658 VkImageAspectFlags aspects)
1659 {
1660 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1661 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel);
1662 uint32_t level_count = radv_get_levelCount(image, range);
1663
1664 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1665 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1666 /* Use the fastest way when both aspects are used. */
1667 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + 2 * level_count, cmd_buffer->state.predicating));
1668 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1669 S_370_WR_CONFIRM(1) |
1670 S_370_ENGINE_SEL(V_370_PFP));
1671 radeon_emit(cs, va);
1672 radeon_emit(cs, va >> 32);
1673
1674 for (uint32_t l = 0; l < level_count; l++) {
1675 radeon_emit(cs, ds_clear_value.stencil);
1676 radeon_emit(cs, fui(ds_clear_value.depth));
1677 }
1678 } else {
1679 /* Otherwise we need one WRITE_DATA packet per level. */
1680 for (uint32_t l = 0; l < level_count; l++) {
1681 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel + l);
1682 unsigned value;
1683
1684 if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1685 value = fui(ds_clear_value.depth);
1686 va += 4;
1687 } else {
1688 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1689 value = ds_clear_value.stencil;
1690 }
1691
1692 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1693 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1694 S_370_WR_CONFIRM(1) |
1695 S_370_ENGINE_SEL(V_370_PFP));
1696 radeon_emit(cs, va);
1697 radeon_emit(cs, va >> 32);
1698 radeon_emit(cs, value);
1699 }
1700 }
1701 }
1702
1703 /**
1704 * Update the TC-compat metadata value for this image.
1705 */
1706 static void
1707 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1708 struct radv_image *image,
1709 const VkImageSubresourceRange *range,
1710 uint32_t value)
1711 {
1712 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1713
1714 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug)
1715 return;
1716
1717 uint64_t va = radv_get_tc_compat_zrange_va(image, range->baseMipLevel);
1718 uint32_t level_count = radv_get_levelCount(image, range);
1719
1720 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + level_count, cmd_buffer->state.predicating));
1721 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1722 S_370_WR_CONFIRM(1) |
1723 S_370_ENGINE_SEL(V_370_PFP));
1724 radeon_emit(cs, va);
1725 radeon_emit(cs, va >> 32);
1726
1727 for (uint32_t l = 0; l < level_count; l++)
1728 radeon_emit(cs, value);
1729 }
1730
1731 static void
1732 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1733 const struct radv_image_view *iview,
1734 VkClearDepthStencilValue ds_clear_value)
1735 {
1736 VkImageSubresourceRange range = {
1737 .aspectMask = iview->aspect_mask,
1738 .baseMipLevel = iview->base_mip,
1739 .levelCount = iview->level_count,
1740 .baseArrayLayer = iview->base_layer,
1741 .layerCount = iview->layer_count,
1742 };
1743 uint32_t cond_val;
1744
1745 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1746 * depth clear value is 0.0f.
1747 */
1748 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1749
1750 radv_set_tc_compat_zrange_metadata(cmd_buffer, iview->image, &range,
1751 cond_val);
1752 }
1753
1754 /**
1755 * Update the clear depth/stencil values for this image.
1756 */
1757 void
1758 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1759 const struct radv_image_view *iview,
1760 VkClearDepthStencilValue ds_clear_value,
1761 VkImageAspectFlags aspects)
1762 {
1763 VkImageSubresourceRange range = {
1764 .aspectMask = iview->aspect_mask,
1765 .baseMipLevel = iview->base_mip,
1766 .levelCount = iview->level_count,
1767 .baseArrayLayer = iview->base_layer,
1768 .layerCount = iview->layer_count,
1769 };
1770 struct radv_image *image = iview->image;
1771
1772 assert(radv_image_has_htile(image));
1773
1774 radv_set_ds_clear_metadata(cmd_buffer, iview->image, &range,
1775 ds_clear_value, aspects);
1776
1777 if (radv_image_is_tc_compat_htile(image) &&
1778 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1779 radv_update_tc_compat_zrange_metadata(cmd_buffer, iview,
1780 ds_clear_value);
1781 }
1782
1783 radv_update_bound_fast_clear_ds(cmd_buffer, iview, ds_clear_value,
1784 aspects);
1785 }
1786
1787 /**
1788 * Load the clear depth/stencil values from the image's metadata.
1789 */
1790 static void
1791 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1792 const struct radv_image_view *iview)
1793 {
1794 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1795 const struct radv_image *image = iview->image;
1796 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1797 uint64_t va = radv_get_ds_clear_value_va(image, iview->base_mip);
1798 unsigned reg_offset = 0, reg_count = 0;
1799
1800 if (!radv_image_has_htile(image))
1801 return;
1802
1803 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1804 ++reg_count;
1805 } else {
1806 ++reg_offset;
1807 va += 4;
1808 }
1809 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1810 ++reg_count;
1811
1812 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1813
1814 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1815 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1816 radeon_emit(cs, va);
1817 radeon_emit(cs, va >> 32);
1818 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1819 radeon_emit(cs, reg_count);
1820 } else {
1821 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1822 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1823 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1824 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1825 radeon_emit(cs, va);
1826 radeon_emit(cs, va >> 32);
1827 radeon_emit(cs, reg >> 2);
1828 radeon_emit(cs, 0);
1829
1830 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1831 radeon_emit(cs, 0);
1832 }
1833 }
1834
1835 /*
1836 * With DCC some colors don't require CMASK elimination before being
1837 * used as a texture. This sets a predicate value to determine if the
1838 * cmask eliminate is required.
1839 */
1840 void
1841 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1842 struct radv_image *image,
1843 const VkImageSubresourceRange *range, bool value)
1844 {
1845 uint64_t pred_val = value;
1846 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
1847 uint32_t level_count = radv_get_levelCount(image, range);
1848 uint32_t count = 2 * level_count;
1849
1850 assert(radv_dcc_enabled(image, range->baseMipLevel));
1851
1852 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1853 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1854 S_370_WR_CONFIRM(1) |
1855 S_370_ENGINE_SEL(V_370_PFP));
1856 radeon_emit(cmd_buffer->cs, va);
1857 radeon_emit(cmd_buffer->cs, va >> 32);
1858
1859 for (uint32_t l = 0; l < level_count; l++) {
1860 radeon_emit(cmd_buffer->cs, pred_val);
1861 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1862 }
1863 }
1864
1865 /**
1866 * Update the DCC predicate to reflect the compression state.
1867 */
1868 void
1869 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1870 struct radv_image *image,
1871 const VkImageSubresourceRange *range, bool value)
1872 {
1873 uint64_t pred_val = value;
1874 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
1875 uint32_t level_count = radv_get_levelCount(image, range);
1876 uint32_t count = 2 * level_count;
1877
1878 assert(radv_dcc_enabled(image, range->baseMipLevel));
1879
1880 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1881 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1882 S_370_WR_CONFIRM(1) |
1883 S_370_ENGINE_SEL(V_370_PFP));
1884 radeon_emit(cmd_buffer->cs, va);
1885 radeon_emit(cmd_buffer->cs, va >> 32);
1886
1887 for (uint32_t l = 0; l < level_count; l++) {
1888 radeon_emit(cmd_buffer->cs, pred_val);
1889 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1890 }
1891 }
1892
1893 /**
1894 * Update the fast clear color values if the image is bound as a color buffer.
1895 */
1896 static void
1897 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1898 struct radv_image *image,
1899 int cb_idx,
1900 uint32_t color_values[2])
1901 {
1902 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1903 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1904 uint32_t att_idx;
1905
1906 if (!cmd_buffer->state.attachments || !subpass)
1907 return;
1908
1909 att_idx = subpass->color_attachments[cb_idx].attachment;
1910 if (att_idx == VK_ATTACHMENT_UNUSED)
1911 return;
1912
1913 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1914 return;
1915
1916 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1917 radeon_emit(cs, color_values[0]);
1918 radeon_emit(cs, color_values[1]);
1919
1920 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1921 }
1922
1923 /**
1924 * Set the clear color values to the image's metadata.
1925 */
1926 static void
1927 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1928 struct radv_image *image,
1929 const VkImageSubresourceRange *range,
1930 uint32_t color_values[2])
1931 {
1932 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1933 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
1934 uint32_t level_count = radv_get_levelCount(image, range);
1935 uint32_t count = 2 * level_count;
1936
1937 assert(radv_image_has_cmask(image) ||
1938 radv_dcc_enabled(image, range->baseMipLevel));
1939
1940 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
1941 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1942 S_370_WR_CONFIRM(1) |
1943 S_370_ENGINE_SEL(V_370_PFP));
1944 radeon_emit(cs, va);
1945 radeon_emit(cs, va >> 32);
1946
1947 for (uint32_t l = 0; l < level_count; l++) {
1948 radeon_emit(cs, color_values[0]);
1949 radeon_emit(cs, color_values[1]);
1950 }
1951 }
1952
1953 /**
1954 * Update the clear color values for this image.
1955 */
1956 void
1957 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1958 const struct radv_image_view *iview,
1959 int cb_idx,
1960 uint32_t color_values[2])
1961 {
1962 struct radv_image *image = iview->image;
1963 VkImageSubresourceRange range = {
1964 .aspectMask = iview->aspect_mask,
1965 .baseMipLevel = iview->base_mip,
1966 .levelCount = iview->level_count,
1967 .baseArrayLayer = iview->base_layer,
1968 .layerCount = iview->layer_count,
1969 };
1970
1971 assert(radv_image_has_cmask(image) ||
1972 radv_dcc_enabled(image, iview->base_mip));
1973
1974 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
1975
1976 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1977 color_values);
1978 }
1979
1980 /**
1981 * Load the clear color values from the image's metadata.
1982 */
1983 static void
1984 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1985 struct radv_image_view *iview,
1986 int cb_idx)
1987 {
1988 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1989 struct radv_image *image = iview->image;
1990 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
1991
1992 if (!radv_image_has_cmask(image) &&
1993 !radv_dcc_enabled(image, iview->base_mip))
1994 return;
1995
1996 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1997
1998 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1999 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
2000 radeon_emit(cs, va);
2001 radeon_emit(cs, va >> 32);
2002 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
2003 radeon_emit(cs, 2);
2004 } else {
2005 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
2006 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2007 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2008 COPY_DATA_COUNT_SEL);
2009 radeon_emit(cs, va);
2010 radeon_emit(cs, va >> 32);
2011 radeon_emit(cs, reg >> 2);
2012 radeon_emit(cs, 0);
2013
2014 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
2015 radeon_emit(cs, 0);
2016 }
2017 }
2018
2019 static void
2020 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
2021 {
2022 int i;
2023 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
2024 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2025
2026 /* this may happen for inherited secondary recording */
2027 if (!framebuffer)
2028 return;
2029
2030 for (i = 0; i < 8; ++i) {
2031 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
2032 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2033 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2034 continue;
2035 }
2036
2037 int idx = subpass->color_attachments[i].attachment;
2038 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2039 VkImageLayout layout = subpass->color_attachments[i].layout;
2040 bool in_render_loop = subpass->color_attachments[i].in_render_loop;
2041
2042 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->bo);
2043
2044 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
2045 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
2046 radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout, in_render_loop);
2047
2048 radv_load_color_clear_metadata(cmd_buffer, iview, i);
2049 }
2050
2051 if (subpass->depth_stencil_attachment) {
2052 int idx = subpass->depth_stencil_attachment->attachment;
2053 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
2054 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
2055 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2056 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->state.attachments[idx].iview->bo);
2057
2058 radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, iview, layout, in_render_loop);
2059
2060 if (cmd_buffer->state.attachments[idx].ds.offset_scale != cmd_buffer->state.offset_scale) {
2061 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2062 cmd_buffer->state.offset_scale = cmd_buffer->state.attachments[idx].ds.offset_scale;
2063 }
2064 radv_load_ds_clear_metadata(cmd_buffer, iview);
2065 } else {
2066 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
2067 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
2068 else
2069 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
2070
2071 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2072 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2073 }
2074 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2075 S_028208_BR_X(framebuffer->width) |
2076 S_028208_BR_Y(framebuffer->height));
2077
2078 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
2079 bool disable_constant_encode =
2080 cmd_buffer->device->physical_device->rad_info.has_dcc_constant_encode;
2081 enum chip_class chip_class =
2082 cmd_buffer->device->physical_device->rad_info.chip_class;
2083 uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
2084
2085 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
2086 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
2087 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
2088 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
2089 }
2090
2091 if (cmd_buffer->device->dfsm_allowed) {
2092 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2093 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2094 }
2095
2096 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
2097 }
2098
2099 static void
2100 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer, bool indirect)
2101 {
2102 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2103 struct radv_cmd_state *state = &cmd_buffer->state;
2104
2105 if (state->index_type != state->last_index_type) {
2106 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2107 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2108 cs, R_03090C_VGT_INDEX_TYPE,
2109 2, state->index_type);
2110 } else {
2111 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2112 radeon_emit(cs, state->index_type);
2113 }
2114
2115 state->last_index_type = state->index_type;
2116 }
2117
2118 /* For the direct indexed draws we use DRAW_INDEX_2, which includes
2119 * the index_va and max_index_count already. */
2120 if (!indirect)
2121 return;
2122
2123 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2124 radeon_emit(cs, state->index_va);
2125 radeon_emit(cs, state->index_va >> 32);
2126
2127 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2128 radeon_emit(cs, state->max_index_count);
2129
2130 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
2131 }
2132
2133 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
2134 {
2135 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
2136 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2137 uint32_t pa_sc_mode_cntl_1 =
2138 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
2139 uint32_t db_count_control;
2140
2141 if(!cmd_buffer->state.active_occlusion_queries) {
2142 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2143 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2144 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2145 has_perfect_queries) {
2146 /* Re-enable out-of-order rasterization if the
2147 * bound pipeline supports it and if it's has
2148 * been disabled before starting any perfect
2149 * occlusion queries.
2150 */
2151 radeon_set_context_reg(cmd_buffer->cs,
2152 R_028A4C_PA_SC_MODE_CNTL_1,
2153 pa_sc_mode_cntl_1);
2154 }
2155 }
2156 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
2157 } else {
2158 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2159 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
2160 bool gfx10_perfect = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries;
2161
2162 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2163 db_count_control =
2164 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
2165 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
2166 S_028004_SAMPLE_RATE(sample_rate) |
2167 S_028004_ZPASS_ENABLE(1) |
2168 S_028004_SLICE_EVEN_ENABLE(1) |
2169 S_028004_SLICE_ODD_ENABLE(1);
2170
2171 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2172 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2173 has_perfect_queries) {
2174 /* If the bound pipeline has enabled
2175 * out-of-order rasterization, we should
2176 * disable it before starting any perfect
2177 * occlusion queries.
2178 */
2179 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2180
2181 radeon_set_context_reg(cmd_buffer->cs,
2182 R_028A4C_PA_SC_MODE_CNTL_1,
2183 pa_sc_mode_cntl_1);
2184 }
2185 } else {
2186 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2187 S_028004_SAMPLE_RATE(sample_rate);
2188 }
2189 }
2190
2191 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2192
2193 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2194 }
2195
2196 static void
2197 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2198 {
2199 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2200
2201 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2202 radv_emit_viewport(cmd_buffer);
2203
2204 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2205 !cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
2206 radv_emit_scissor(cmd_buffer);
2207
2208 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2209 radv_emit_line_width(cmd_buffer);
2210
2211 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2212 radv_emit_blend_constants(cmd_buffer);
2213
2214 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2215 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2216 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2217 radv_emit_stencil(cmd_buffer);
2218
2219 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2220 radv_emit_depth_bounds(cmd_buffer);
2221
2222 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2223 radv_emit_depth_bias(cmd_buffer);
2224
2225 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2226 radv_emit_discard_rectangle(cmd_buffer);
2227
2228 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2229 radv_emit_sample_locations(cmd_buffer);
2230
2231 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2232 radv_emit_line_stipple(cmd_buffer);
2233
2234 cmd_buffer->state.dirty &= ~states;
2235 }
2236
2237 static void
2238 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2239 VkPipelineBindPoint bind_point)
2240 {
2241 struct radv_descriptor_state *descriptors_state =
2242 radv_get_descriptors_state(cmd_buffer, bind_point);
2243 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2244 unsigned bo_offset;
2245
2246 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2247 set->mapped_ptr,
2248 &bo_offset))
2249 return;
2250
2251 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2252 set->va += bo_offset;
2253 }
2254
2255 static void
2256 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2257 VkPipelineBindPoint bind_point)
2258 {
2259 struct radv_descriptor_state *descriptors_state =
2260 radv_get_descriptors_state(cmd_buffer, bind_point);
2261 uint32_t size = MAX_SETS * 4;
2262 uint32_t offset;
2263 void *ptr;
2264
2265 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2266 256, &offset, &ptr))
2267 return;
2268
2269 for (unsigned i = 0; i < MAX_SETS; i++) {
2270 uint32_t *uptr = ((uint32_t *)ptr) + i;
2271 uint64_t set_va = 0;
2272 struct radv_descriptor_set *set = descriptors_state->sets[i];
2273 if (descriptors_state->valid & (1u << i))
2274 set_va = set->va;
2275 uptr[0] = set_va & 0xffffffff;
2276 }
2277
2278 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2279 va += offset;
2280
2281 if (cmd_buffer->state.pipeline) {
2282 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2283 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2284 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2285
2286 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2287 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2288 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2289
2290 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2291 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2292 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2293
2294 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2295 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2296 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2297
2298 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2299 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2300 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2301 }
2302
2303 if (cmd_buffer->state.compute_pipeline)
2304 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2305 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2306 }
2307
2308 static void
2309 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2310 VkShaderStageFlags stages)
2311 {
2312 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2313 VK_PIPELINE_BIND_POINT_COMPUTE :
2314 VK_PIPELINE_BIND_POINT_GRAPHICS;
2315 struct radv_descriptor_state *descriptors_state =
2316 radv_get_descriptors_state(cmd_buffer, bind_point);
2317 struct radv_cmd_state *state = &cmd_buffer->state;
2318 bool flush_indirect_descriptors;
2319
2320 if (!descriptors_state->dirty)
2321 return;
2322
2323 if (descriptors_state->push_dirty)
2324 radv_flush_push_descriptors(cmd_buffer, bind_point);
2325
2326 flush_indirect_descriptors =
2327 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2328 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2329 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2330 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2331
2332 if (flush_indirect_descriptors)
2333 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2334
2335 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2336 cmd_buffer->cs,
2337 MAX_SETS * MESA_SHADER_STAGES * 4);
2338
2339 if (cmd_buffer->state.pipeline) {
2340 radv_foreach_stage(stage, stages) {
2341 if (!cmd_buffer->state.pipeline->shaders[stage])
2342 continue;
2343
2344 radv_emit_descriptor_pointers(cmd_buffer,
2345 cmd_buffer->state.pipeline,
2346 descriptors_state, stage);
2347 }
2348 }
2349
2350 if (cmd_buffer->state.compute_pipeline &&
2351 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2352 radv_emit_descriptor_pointers(cmd_buffer,
2353 cmd_buffer->state.compute_pipeline,
2354 descriptors_state,
2355 MESA_SHADER_COMPUTE);
2356 }
2357
2358 descriptors_state->dirty = 0;
2359 descriptors_state->push_dirty = false;
2360
2361 assert(cmd_buffer->cs->cdw <= cdw_max);
2362
2363 if (unlikely(cmd_buffer->device->trace_bo))
2364 radv_save_descriptors(cmd_buffer, bind_point);
2365 }
2366
2367 static void
2368 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2369 VkShaderStageFlags stages)
2370 {
2371 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2372 ? cmd_buffer->state.compute_pipeline
2373 : cmd_buffer->state.pipeline;
2374 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2375 VK_PIPELINE_BIND_POINT_COMPUTE :
2376 VK_PIPELINE_BIND_POINT_GRAPHICS;
2377 struct radv_descriptor_state *descriptors_state =
2378 radv_get_descriptors_state(cmd_buffer, bind_point);
2379 struct radv_pipeline_layout *layout = pipeline->layout;
2380 struct radv_shader_variant *shader, *prev_shader;
2381 bool need_push_constants = false;
2382 unsigned offset;
2383 void *ptr;
2384 uint64_t va;
2385
2386 stages &= cmd_buffer->push_constant_stages;
2387 if (!stages ||
2388 (!layout->push_constant_size && !layout->dynamic_offset_count))
2389 return;
2390
2391 radv_foreach_stage(stage, stages) {
2392 shader = radv_get_shader(pipeline, stage);
2393 if (!shader)
2394 continue;
2395
2396 need_push_constants |= shader->info.loads_push_constants;
2397 need_push_constants |= shader->info.loads_dynamic_offsets;
2398
2399 uint8_t base = shader->info.base_inline_push_consts;
2400 uint8_t count = shader->info.num_inline_push_consts;
2401
2402 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2403 AC_UD_INLINE_PUSH_CONSTANTS,
2404 count,
2405 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2406 }
2407
2408 if (need_push_constants) {
2409 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2410 16 * layout->dynamic_offset_count,
2411 256, &offset, &ptr))
2412 return;
2413
2414 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2415 memcpy((char*)ptr + layout->push_constant_size,
2416 descriptors_state->dynamic_buffers,
2417 16 * layout->dynamic_offset_count);
2418
2419 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2420 va += offset;
2421
2422 ASSERTED unsigned cdw_max =
2423 radeon_check_space(cmd_buffer->device->ws,
2424 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2425
2426 prev_shader = NULL;
2427 radv_foreach_stage(stage, stages) {
2428 shader = radv_get_shader(pipeline, stage);
2429
2430 /* Avoid redundantly emitting the address for merged stages. */
2431 if (shader && shader != prev_shader) {
2432 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2433 AC_UD_PUSH_CONSTANTS, va);
2434
2435 prev_shader = shader;
2436 }
2437 }
2438 assert(cmd_buffer->cs->cdw <= cdw_max);
2439 }
2440
2441 cmd_buffer->push_constant_stages &= ~stages;
2442 }
2443
2444 static void
2445 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2446 bool pipeline_is_dirty)
2447 {
2448 if ((pipeline_is_dirty ||
2449 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2450 cmd_buffer->state.pipeline->num_vertex_bindings &&
2451 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.has_vertex_buffers) {
2452 unsigned vb_offset;
2453 void *vb_ptr;
2454 uint32_t i = 0;
2455 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2456 uint64_t va;
2457
2458 /* allocate some descriptor state for vertex buffers */
2459 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2460 &vb_offset, &vb_ptr))
2461 return;
2462
2463 for (i = 0; i < count; i++) {
2464 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2465 uint32_t offset;
2466 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2467 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2468 unsigned num_records;
2469
2470 if (!buffer)
2471 continue;
2472
2473 va = radv_buffer_get_va(buffer->bo);
2474
2475 offset = cmd_buffer->vertex_bindings[i].offset;
2476 va += offset + buffer->offset;
2477
2478 num_records = buffer->size - offset;
2479 if (cmd_buffer->device->physical_device->rad_info.chip_class != GFX8 && stride)
2480 num_records /= stride;
2481
2482 desc[0] = va;
2483 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2484 desc[2] = num_records;
2485 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2486 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2487 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2488 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2489
2490 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2491 /* OOB_SELECT chooses the out-of-bounds check:
2492 * - 1: index >= NUM_RECORDS (Structured)
2493 * - 3: offset >= NUM_RECORDS (Raw)
2494 */
2495 int oob_select = stride ? V_008F0C_OOB_SELECT_STRUCTURED : V_008F0C_OOB_SELECT_RAW;
2496
2497 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
2498 S_008F0C_OOB_SELECT(oob_select) |
2499 S_008F0C_RESOURCE_LEVEL(1);
2500 } else {
2501 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2502 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2503 }
2504 }
2505
2506 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2507 va += vb_offset;
2508
2509 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2510 AC_UD_VS_VERTEX_BUFFERS, va);
2511
2512 cmd_buffer->state.vb_va = va;
2513 cmd_buffer->state.vb_size = count * 16;
2514 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2515 }
2516 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2517 }
2518
2519 static void
2520 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2521 {
2522 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2523 struct radv_userdata_info *loc;
2524 uint32_t base_reg;
2525
2526 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2527 if (!radv_get_shader(pipeline, stage))
2528 continue;
2529
2530 loc = radv_lookup_user_sgpr(pipeline, stage,
2531 AC_UD_STREAMOUT_BUFFERS);
2532 if (loc->sgpr_idx == -1)
2533 continue;
2534
2535 base_reg = pipeline->user_data_0[stage];
2536
2537 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2538 base_reg + loc->sgpr_idx * 4, va, false);
2539 }
2540
2541 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
2542 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2543 if (loc->sgpr_idx != -1) {
2544 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2545
2546 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2547 base_reg + loc->sgpr_idx * 4, va, false);
2548 }
2549 }
2550 }
2551
2552 static void
2553 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2554 {
2555 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2556 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2557 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2558 unsigned so_offset;
2559 void *so_ptr;
2560 uint64_t va;
2561
2562 /* Allocate some descriptor state for streamout buffers. */
2563 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2564 MAX_SO_BUFFERS * 16, 256,
2565 &so_offset, &so_ptr))
2566 return;
2567
2568 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2569 struct radv_buffer *buffer = sb[i].buffer;
2570 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2571
2572 if (!(so->enabled_mask & (1 << i)))
2573 continue;
2574
2575 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2576
2577 va += sb[i].offset;
2578
2579 /* Set the descriptor.
2580 *
2581 * On GFX8, the format must be non-INVALID, otherwise
2582 * the buffer will be considered not bound and store
2583 * instructions will be no-ops.
2584 */
2585 uint32_t size = 0xffffffff;
2586
2587 /* Compute the correct buffer size for NGG streamout
2588 * because it's used to determine the max emit per
2589 * buffer.
2590 */
2591 if (cmd_buffer->device->physical_device->use_ngg_streamout)
2592 size = buffer->size - sb[i].offset;
2593
2594 desc[0] = va;
2595 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2596 desc[2] = size;
2597 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2598 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2599 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2600 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2601
2602 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2603 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2604 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
2605 S_008F0C_RESOURCE_LEVEL(1);
2606 } else {
2607 desc[3] |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2608 }
2609 }
2610
2611 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2612 va += so_offset;
2613
2614 radv_emit_streamout_buffers(cmd_buffer, va);
2615 }
2616
2617 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2618 }
2619
2620 static void
2621 radv_flush_ngg_gs_state(struct radv_cmd_buffer *cmd_buffer)
2622 {
2623 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2624 struct radv_userdata_info *loc;
2625 uint32_t ngg_gs_state = 0;
2626 uint32_t base_reg;
2627
2628 if (!radv_pipeline_has_gs(pipeline) ||
2629 !radv_pipeline_has_ngg(pipeline))
2630 return;
2631
2632 /* By default NGG GS queries are disabled but they are enabled if the
2633 * command buffer has active GDS queries or if it's a secondary command
2634 * buffer that inherits the number of generated primitives.
2635 */
2636 if (cmd_buffer->state.active_pipeline_gds_queries ||
2637 (cmd_buffer->state.inherited_pipeline_statistics & VK_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_PRIMITIVES_BIT))
2638 ngg_gs_state = 1;
2639
2640 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_GEOMETRY,
2641 AC_UD_NGG_GS_STATE);
2642 base_reg = pipeline->user_data_0[MESA_SHADER_GEOMETRY];
2643 assert(loc->sgpr_idx != -1);
2644
2645 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
2646 ngg_gs_state);
2647 }
2648
2649 static void
2650 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2651 {
2652 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2653 radv_flush_streamout_descriptors(cmd_buffer);
2654 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2655 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2656 radv_flush_ngg_gs_state(cmd_buffer);
2657 }
2658
2659 struct radv_draw_info {
2660 /**
2661 * Number of vertices.
2662 */
2663 uint32_t count;
2664
2665 /**
2666 * Index of the first vertex.
2667 */
2668 int32_t vertex_offset;
2669
2670 /**
2671 * First instance id.
2672 */
2673 uint32_t first_instance;
2674
2675 /**
2676 * Number of instances.
2677 */
2678 uint32_t instance_count;
2679
2680 /**
2681 * First index (indexed draws only).
2682 */
2683 uint32_t first_index;
2684
2685 /**
2686 * Whether it's an indexed draw.
2687 */
2688 bool indexed;
2689
2690 /**
2691 * Indirect draw parameters resource.
2692 */
2693 struct radv_buffer *indirect;
2694 uint64_t indirect_offset;
2695 uint32_t stride;
2696
2697 /**
2698 * Draw count parameters resource.
2699 */
2700 struct radv_buffer *count_buffer;
2701 uint64_t count_buffer_offset;
2702
2703 /**
2704 * Stream output parameters resource.
2705 */
2706 struct radv_buffer *strmout_buffer;
2707 uint64_t strmout_buffer_offset;
2708 };
2709
2710 static uint32_t
2711 radv_get_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2712 {
2713 switch (cmd_buffer->state.index_type) {
2714 case V_028A7C_VGT_INDEX_8:
2715 return 0xffu;
2716 case V_028A7C_VGT_INDEX_16:
2717 return 0xffffu;
2718 case V_028A7C_VGT_INDEX_32:
2719 return 0xffffffffu;
2720 default:
2721 unreachable("invalid index type");
2722 }
2723 }
2724
2725 static void
2726 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
2727 bool instanced_draw, bool indirect_draw,
2728 bool count_from_stream_output,
2729 uint32_t draw_vertex_count)
2730 {
2731 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2732 struct radv_cmd_state *state = &cmd_buffer->state;
2733 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2734 unsigned ia_multi_vgt_param;
2735
2736 ia_multi_vgt_param =
2737 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2738 indirect_draw,
2739 count_from_stream_output,
2740 draw_vertex_count);
2741
2742 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2743 if (info->chip_class == GFX9) {
2744 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2745 cs,
2746 R_030960_IA_MULTI_VGT_PARAM,
2747 4, ia_multi_vgt_param);
2748 } else if (info->chip_class >= GFX7) {
2749 radeon_set_context_reg_idx(cs,
2750 R_028AA8_IA_MULTI_VGT_PARAM,
2751 1, ia_multi_vgt_param);
2752 } else {
2753 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2754 ia_multi_vgt_param);
2755 }
2756 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2757 }
2758 }
2759
2760 static void
2761 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2762 const struct radv_draw_info *draw_info)
2763 {
2764 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2765 struct radv_cmd_state *state = &cmd_buffer->state;
2766 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2767 int32_t primitive_reset_en;
2768
2769 /* Draw state. */
2770 if (info->chip_class < GFX10) {
2771 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2772 draw_info->indirect,
2773 !!draw_info->strmout_buffer,
2774 draw_info->indirect ? 0 : draw_info->count);
2775 }
2776
2777 /* Primitive restart. */
2778 primitive_reset_en =
2779 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2780
2781 if (primitive_reset_en != state->last_primitive_reset_en) {
2782 state->last_primitive_reset_en = primitive_reset_en;
2783 if (info->chip_class >= GFX9) {
2784 radeon_set_uconfig_reg(cs,
2785 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2786 primitive_reset_en);
2787 } else {
2788 radeon_set_context_reg(cs,
2789 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2790 primitive_reset_en);
2791 }
2792 }
2793
2794 if (primitive_reset_en) {
2795 uint32_t primitive_reset_index =
2796 radv_get_primitive_reset_index(cmd_buffer);
2797
2798 if (primitive_reset_index != state->last_primitive_reset_index) {
2799 radeon_set_context_reg(cs,
2800 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2801 primitive_reset_index);
2802 state->last_primitive_reset_index = primitive_reset_index;
2803 }
2804 }
2805
2806 if (draw_info->strmout_buffer) {
2807 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2808
2809 va += draw_info->strmout_buffer->offset +
2810 draw_info->strmout_buffer_offset;
2811
2812 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2813 draw_info->stride);
2814
2815 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2816 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2817 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2818 COPY_DATA_WR_CONFIRM);
2819 radeon_emit(cs, va);
2820 radeon_emit(cs, va >> 32);
2821 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2822 radeon_emit(cs, 0); /* unused */
2823
2824 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2825 }
2826 }
2827
2828 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2829 VkPipelineStageFlags src_stage_mask)
2830 {
2831 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2832 VK_PIPELINE_STAGE_TRANSFER_BIT |
2833 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2834 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2835 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2836 }
2837
2838 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2839 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2840 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2841 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2842 VK_PIPELINE_STAGE_TRANSFER_BIT |
2843 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2844 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2845 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2846 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2847 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2848 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2849 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2850 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2851 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2852 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2853 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2854 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2855 }
2856 }
2857
2858 static enum radv_cmd_flush_bits
2859 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2860 VkAccessFlags src_flags,
2861 struct radv_image *image)
2862 {
2863 bool flush_CB_meta = true, flush_DB_meta = true;
2864 enum radv_cmd_flush_bits flush_bits = 0;
2865 uint32_t b;
2866
2867 if (image) {
2868 if (!radv_image_has_CB_metadata(image))
2869 flush_CB_meta = false;
2870 if (!radv_image_has_htile(image))
2871 flush_DB_meta = false;
2872 }
2873
2874 for_each_bit(b, src_flags) {
2875 switch ((VkAccessFlagBits)(1 << b)) {
2876 case VK_ACCESS_SHADER_WRITE_BIT:
2877 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2878 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2879 flush_bits |= RADV_CMD_FLAG_WB_L2;
2880 break;
2881 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2882 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2883 if (flush_CB_meta)
2884 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2885 break;
2886 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2887 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2888 if (flush_DB_meta)
2889 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2890 break;
2891 case VK_ACCESS_TRANSFER_WRITE_BIT:
2892 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2893 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2894 RADV_CMD_FLAG_INV_L2;
2895
2896 if (flush_CB_meta)
2897 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2898 if (flush_DB_meta)
2899 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2900 break;
2901 default:
2902 break;
2903 }
2904 }
2905 return flush_bits;
2906 }
2907
2908 static enum radv_cmd_flush_bits
2909 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2910 VkAccessFlags dst_flags,
2911 struct radv_image *image)
2912 {
2913 bool flush_CB_meta = true, flush_DB_meta = true;
2914 enum radv_cmd_flush_bits flush_bits = 0;
2915 bool flush_CB = true, flush_DB = true;
2916 bool image_is_coherent = false;
2917 uint32_t b;
2918
2919 if (image) {
2920 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2921 flush_CB = false;
2922 flush_DB = false;
2923 }
2924
2925 if (!radv_image_has_CB_metadata(image))
2926 flush_CB_meta = false;
2927 if (!radv_image_has_htile(image))
2928 flush_DB_meta = false;
2929
2930 /* TODO: implement shader coherent for GFX10 */
2931
2932 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
2933 if (image->info.samples == 1 &&
2934 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2935 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2936 !vk_format_is_stencil(image->vk_format)) {
2937 /* Single-sample color and single-sample depth
2938 * (not stencil) are coherent with shaders on
2939 * GFX9.
2940 */
2941 image_is_coherent = true;
2942 }
2943 }
2944 }
2945
2946 for_each_bit(b, dst_flags) {
2947 switch ((VkAccessFlagBits)(1 << b)) {
2948 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2949 case VK_ACCESS_INDEX_READ_BIT:
2950 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2951 break;
2952 case VK_ACCESS_UNIFORM_READ_BIT:
2953 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
2954 break;
2955 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2956 case VK_ACCESS_TRANSFER_READ_BIT:
2957 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2958 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
2959 RADV_CMD_FLAG_INV_L2;
2960 break;
2961 case VK_ACCESS_SHADER_READ_BIT:
2962 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
2963 /* Unlike LLVM, ACO uses SMEM for SSBOs and we have to
2964 * invalidate the scalar cache. */
2965 if (cmd_buffer->device->physical_device->use_aco &&
2966 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8)
2967 flush_bits |= RADV_CMD_FLAG_INV_SCACHE;
2968
2969 if (!image_is_coherent)
2970 flush_bits |= RADV_CMD_FLAG_INV_L2;
2971 break;
2972 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2973 if (flush_CB)
2974 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2975 if (flush_CB_meta)
2976 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2977 break;
2978 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2979 if (flush_DB)
2980 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2981 if (flush_DB_meta)
2982 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2983 break;
2984 default:
2985 break;
2986 }
2987 }
2988 return flush_bits;
2989 }
2990
2991 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2992 const struct radv_subpass_barrier *barrier)
2993 {
2994 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2995 NULL);
2996 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2997 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2998 NULL);
2999 }
3000
3001 uint32_t
3002 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
3003 {
3004 struct radv_cmd_state *state = &cmd_buffer->state;
3005 uint32_t subpass_id = state->subpass - state->pass->subpasses;
3006
3007 /* The id of this subpass shouldn't exceed the number of subpasses in
3008 * this render pass minus 1.
3009 */
3010 assert(subpass_id < state->pass->subpass_count);
3011 return subpass_id;
3012 }
3013
3014 static struct radv_sample_locations_state *
3015 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3016 uint32_t att_idx,
3017 bool begin_subpass)
3018 {
3019 struct radv_cmd_state *state = &cmd_buffer->state;
3020 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
3021 struct radv_image_view *view = state->attachments[att_idx].iview;
3022
3023 if (view->image->info.samples == 1)
3024 return NULL;
3025
3026 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
3027 /* Return the initial sample locations if this is the initial
3028 * layout transition of the given subpass attachemnt.
3029 */
3030 if (state->attachments[att_idx].sample_location.count > 0)
3031 return &state->attachments[att_idx].sample_location;
3032 } else {
3033 /* Otherwise return the subpass sample locations if defined. */
3034 if (state->subpass_sample_locs) {
3035 /* Because the driver sets the current subpass before
3036 * initial layout transitions, we should use the sample
3037 * locations from the previous subpass to avoid an
3038 * off-by-one problem. Otherwise, use the sample
3039 * locations for the current subpass for final layout
3040 * transitions.
3041 */
3042 if (begin_subpass)
3043 subpass_id--;
3044
3045 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
3046 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
3047 return &state->subpass_sample_locs[i].sample_location;
3048 }
3049 }
3050 }
3051
3052 return NULL;
3053 }
3054
3055 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
3056 struct radv_subpass_attachment att,
3057 bool begin_subpass)
3058 {
3059 unsigned idx = att.attachment;
3060 struct radv_image_view *view = cmd_buffer->state.attachments[idx].iview;
3061 struct radv_sample_locations_state *sample_locs;
3062 VkImageSubresourceRange range;
3063 range.aspectMask = view->aspect_mask;
3064 range.baseMipLevel = view->base_mip;
3065 range.levelCount = 1;
3066 range.baseArrayLayer = view->base_layer;
3067 range.layerCount = cmd_buffer->state.framebuffer->layers;
3068
3069 if (cmd_buffer->state.subpass->view_mask) {
3070 /* If the current subpass uses multiview, the driver might have
3071 * performed a fast color/depth clear to the whole image
3072 * (including all layers). To make sure the driver will
3073 * decompress the image correctly (if needed), we have to
3074 * account for the "real" number of layers. If the view mask is
3075 * sparse, this will decompress more layers than needed.
3076 */
3077 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
3078 }
3079
3080 /* Get the subpass sample locations for the given attachment, if NULL
3081 * is returned the driver will use the default HW locations.
3082 */
3083 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
3084 begin_subpass);
3085
3086 /* Determine if the subpass uses separate depth/stencil layouts. */
3087 bool uses_separate_depth_stencil_layouts = false;
3088 if ((cmd_buffer->state.attachments[idx].current_layout !=
3089 cmd_buffer->state.attachments[idx].current_stencil_layout) ||
3090 (att.layout != att.stencil_layout)) {
3091 uses_separate_depth_stencil_layouts = true;
3092 }
3093
3094 /* For separate layouts, perform depth and stencil transitions
3095 * separately.
3096 */
3097 if (uses_separate_depth_stencil_layouts &&
3098 (range.aspectMask == (VK_IMAGE_ASPECT_DEPTH_BIT |
3099 VK_IMAGE_ASPECT_STENCIL_BIT))) {
3100 /* Depth-only transitions. */
3101 range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3102 radv_handle_image_transition(cmd_buffer,
3103 view->image,
3104 cmd_buffer->state.attachments[idx].current_layout,
3105 cmd_buffer->state.attachments[idx].current_in_render_loop,
3106 att.layout, att.in_render_loop,
3107 0, 0, &range, sample_locs);
3108
3109 /* Stencil-only transitions. */
3110 range.aspectMask = VK_IMAGE_ASPECT_STENCIL_BIT;
3111 radv_handle_image_transition(cmd_buffer,
3112 view->image,
3113 cmd_buffer->state.attachments[idx].current_stencil_layout,
3114 cmd_buffer->state.attachments[idx].current_in_render_loop,
3115 att.stencil_layout, att.in_render_loop,
3116 0, 0, &range, sample_locs);
3117 } else {
3118 radv_handle_image_transition(cmd_buffer,
3119 view->image,
3120 cmd_buffer->state.attachments[idx].current_layout,
3121 cmd_buffer->state.attachments[idx].current_in_render_loop,
3122 att.layout, att.in_render_loop,
3123 0, 0, &range, sample_locs);
3124 }
3125
3126 cmd_buffer->state.attachments[idx].current_layout = att.layout;
3127 cmd_buffer->state.attachments[idx].current_stencil_layout = att.stencil_layout;
3128 cmd_buffer->state.attachments[idx].current_in_render_loop = att.in_render_loop;
3129
3130
3131 }
3132
3133 void
3134 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
3135 const struct radv_subpass *subpass)
3136 {
3137 cmd_buffer->state.subpass = subpass;
3138
3139 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
3140 }
3141
3142 static VkResult
3143 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3144 struct radv_render_pass *pass,
3145 const VkRenderPassBeginInfo *info)
3146 {
3147 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
3148 vk_find_struct_const(info->pNext,
3149 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
3150 struct radv_cmd_state *state = &cmd_buffer->state;
3151
3152 if (!sample_locs) {
3153 state->subpass_sample_locs = NULL;
3154 return VK_SUCCESS;
3155 }
3156
3157 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
3158 const VkAttachmentSampleLocationsEXT *att_sample_locs =
3159 &sample_locs->pAttachmentInitialSampleLocations[i];
3160 uint32_t att_idx = att_sample_locs->attachmentIndex;
3161 struct radv_image *image = cmd_buffer->state.attachments[att_idx].iview->image;
3162
3163 assert(vk_format_is_depth_or_stencil(image->vk_format));
3164
3165 /* From the Vulkan spec 1.1.108:
3166 *
3167 * "If the image referenced by the framebuffer attachment at
3168 * index attachmentIndex was not created with
3169 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
3170 * then the values specified in sampleLocationsInfo are
3171 * ignored."
3172 */
3173 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
3174 continue;
3175
3176 const VkSampleLocationsInfoEXT *sample_locs_info =
3177 &att_sample_locs->sampleLocationsInfo;
3178
3179 state->attachments[att_idx].sample_location.per_pixel =
3180 sample_locs_info->sampleLocationsPerPixel;
3181 state->attachments[att_idx].sample_location.grid_size =
3182 sample_locs_info->sampleLocationGridSize;
3183 state->attachments[att_idx].sample_location.count =
3184 sample_locs_info->sampleLocationsCount;
3185 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
3186 sample_locs_info->pSampleLocations,
3187 sample_locs_info->sampleLocationsCount);
3188 }
3189
3190 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
3191 sample_locs->postSubpassSampleLocationsCount *
3192 sizeof(state->subpass_sample_locs[0]),
3193 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3194 if (state->subpass_sample_locs == NULL) {
3195 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3196 return cmd_buffer->record_result;
3197 }
3198
3199 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
3200
3201 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
3202 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
3203 &sample_locs->pPostSubpassSampleLocations[i];
3204 const VkSampleLocationsInfoEXT *sample_locs_info =
3205 &subpass_sample_locs_info->sampleLocationsInfo;
3206
3207 state->subpass_sample_locs[i].subpass_idx =
3208 subpass_sample_locs_info->subpassIndex;
3209 state->subpass_sample_locs[i].sample_location.per_pixel =
3210 sample_locs_info->sampleLocationsPerPixel;
3211 state->subpass_sample_locs[i].sample_location.grid_size =
3212 sample_locs_info->sampleLocationGridSize;
3213 state->subpass_sample_locs[i].sample_location.count =
3214 sample_locs_info->sampleLocationsCount;
3215 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
3216 sample_locs_info->pSampleLocations,
3217 sample_locs_info->sampleLocationsCount);
3218 }
3219
3220 return VK_SUCCESS;
3221 }
3222
3223 static VkResult
3224 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
3225 struct radv_render_pass *pass,
3226 const VkRenderPassBeginInfo *info)
3227 {
3228 struct radv_cmd_state *state = &cmd_buffer->state;
3229 const struct VkRenderPassAttachmentBeginInfo *attachment_info = NULL;
3230
3231 if (info) {
3232 attachment_info = vk_find_struct_const(info->pNext,
3233 RENDER_PASS_ATTACHMENT_BEGIN_INFO);
3234 }
3235
3236
3237 if (pass->attachment_count == 0) {
3238 state->attachments = NULL;
3239 return VK_SUCCESS;
3240 }
3241
3242 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
3243 pass->attachment_count *
3244 sizeof(state->attachments[0]),
3245 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3246 if (state->attachments == NULL) {
3247 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3248 return cmd_buffer->record_result;
3249 }
3250
3251 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
3252 struct radv_render_pass_attachment *att = &pass->attachments[i];
3253 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
3254 VkImageAspectFlags clear_aspects = 0;
3255
3256 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
3257 /* color attachment */
3258 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3259 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
3260 }
3261 } else {
3262 /* depthstencil attachment */
3263 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
3264 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3265 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
3266 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3267 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
3268 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3269 }
3270 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3271 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3272 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3273 }
3274 }
3275
3276 state->attachments[i].pending_clear_aspects = clear_aspects;
3277 state->attachments[i].cleared_views = 0;
3278 if (clear_aspects && info) {
3279 assert(info->clearValueCount > i);
3280 state->attachments[i].clear_value = info->pClearValues[i];
3281 }
3282
3283 state->attachments[i].current_layout = att->initial_layout;
3284 state->attachments[i].current_stencil_layout = att->stencil_initial_layout;
3285 state->attachments[i].sample_location.count = 0;
3286
3287 struct radv_image_view *iview;
3288 if (attachment_info && attachment_info->attachmentCount > i) {
3289 iview = radv_image_view_from_handle(attachment_info->pAttachments[i]);
3290 } else {
3291 iview = state->framebuffer->attachments[i];
3292 }
3293
3294 state->attachments[i].iview = iview;
3295 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3296 radv_initialise_ds_surface(cmd_buffer->device, &state->attachments[i].ds, iview);
3297 } else {
3298 radv_initialise_color_surface(cmd_buffer->device, &state->attachments[i].cb, iview);
3299 }
3300 }
3301
3302 return VK_SUCCESS;
3303 }
3304
3305 VkResult radv_AllocateCommandBuffers(
3306 VkDevice _device,
3307 const VkCommandBufferAllocateInfo *pAllocateInfo,
3308 VkCommandBuffer *pCommandBuffers)
3309 {
3310 RADV_FROM_HANDLE(radv_device, device, _device);
3311 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
3312
3313 VkResult result = VK_SUCCESS;
3314 uint32_t i;
3315
3316 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
3317
3318 if (!list_is_empty(&pool->free_cmd_buffers)) {
3319 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
3320
3321 list_del(&cmd_buffer->pool_link);
3322 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
3323
3324 result = radv_reset_cmd_buffer(cmd_buffer);
3325 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
3326 cmd_buffer->level = pAllocateInfo->level;
3327
3328 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
3329 } else {
3330 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
3331 &pCommandBuffers[i]);
3332 }
3333 if (result != VK_SUCCESS)
3334 break;
3335 }
3336
3337 if (result != VK_SUCCESS) {
3338 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
3339 i, pCommandBuffers);
3340
3341 /* From the Vulkan 1.0.66 spec:
3342 *
3343 * "vkAllocateCommandBuffers can be used to create multiple
3344 * command buffers. If the creation of any of those command
3345 * buffers fails, the implementation must destroy all
3346 * successfully created command buffer objects from this
3347 * command, set all entries of the pCommandBuffers array to
3348 * NULL and return the error."
3349 */
3350 memset(pCommandBuffers, 0,
3351 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
3352 }
3353
3354 return result;
3355 }
3356
3357 void radv_FreeCommandBuffers(
3358 VkDevice device,
3359 VkCommandPool commandPool,
3360 uint32_t commandBufferCount,
3361 const VkCommandBuffer *pCommandBuffers)
3362 {
3363 for (uint32_t i = 0; i < commandBufferCount; i++) {
3364 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
3365
3366 if (cmd_buffer) {
3367 if (cmd_buffer->pool) {
3368 list_del(&cmd_buffer->pool_link);
3369 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3370 } else
3371 radv_cmd_buffer_destroy(cmd_buffer);
3372
3373 }
3374 }
3375 }
3376
3377 VkResult radv_ResetCommandBuffer(
3378 VkCommandBuffer commandBuffer,
3379 VkCommandBufferResetFlags flags)
3380 {
3381 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3382 return radv_reset_cmd_buffer(cmd_buffer);
3383 }
3384
3385 VkResult radv_BeginCommandBuffer(
3386 VkCommandBuffer commandBuffer,
3387 const VkCommandBufferBeginInfo *pBeginInfo)
3388 {
3389 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3390 VkResult result = VK_SUCCESS;
3391
3392 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3393 /* If the command buffer has already been resetted with
3394 * vkResetCommandBuffer, no need to do it again.
3395 */
3396 result = radv_reset_cmd_buffer(cmd_buffer);
3397 if (result != VK_SUCCESS)
3398 return result;
3399 }
3400
3401 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3402 cmd_buffer->state.last_primitive_reset_en = -1;
3403 cmd_buffer->state.last_index_type = -1;
3404 cmd_buffer->state.last_num_instances = -1;
3405 cmd_buffer->state.last_vertex_offset = -1;
3406 cmd_buffer->state.last_first_instance = -1;
3407 cmd_buffer->state.predication_type = -1;
3408 cmd_buffer->state.last_sx_ps_downconvert = -1;
3409 cmd_buffer->state.last_sx_blend_opt_epsilon = -1;
3410 cmd_buffer->state.last_sx_blend_opt_control = -1;
3411 cmd_buffer->usage_flags = pBeginInfo->flags;
3412
3413 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3414 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3415 assert(pBeginInfo->pInheritanceInfo);
3416 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3417 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3418
3419 struct radv_subpass *subpass =
3420 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3421
3422 if (cmd_buffer->state.framebuffer) {
3423 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3424 if (result != VK_SUCCESS)
3425 return result;
3426 }
3427
3428 cmd_buffer->state.inherited_pipeline_statistics =
3429 pBeginInfo->pInheritanceInfo->pipelineStatistics;
3430
3431 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3432 }
3433
3434 if (unlikely(cmd_buffer->device->trace_bo))
3435 radv_cmd_buffer_trace_emit(cmd_buffer);
3436
3437 radv_describe_begin_cmd_buffer(cmd_buffer);
3438
3439 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3440
3441 return result;
3442 }
3443
3444 void radv_CmdBindVertexBuffers(
3445 VkCommandBuffer commandBuffer,
3446 uint32_t firstBinding,
3447 uint32_t bindingCount,
3448 const VkBuffer* pBuffers,
3449 const VkDeviceSize* pOffsets)
3450 {
3451 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3452 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3453 bool changed = false;
3454
3455 /* We have to defer setting up vertex buffer since we need the buffer
3456 * stride from the pipeline. */
3457
3458 assert(firstBinding + bindingCount <= MAX_VBS);
3459 for (uint32_t i = 0; i < bindingCount; i++) {
3460 uint32_t idx = firstBinding + i;
3461
3462 if (!changed &&
3463 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
3464 vb[idx].offset != pOffsets[i])) {
3465 changed = true;
3466 }
3467
3468 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
3469 vb[idx].offset = pOffsets[i];
3470
3471 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3472 vb[idx].buffer->bo);
3473 }
3474
3475 if (!changed) {
3476 /* No state changes. */
3477 return;
3478 }
3479
3480 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3481 }
3482
3483 static uint32_t
3484 vk_to_index_type(VkIndexType type)
3485 {
3486 switch (type) {
3487 case VK_INDEX_TYPE_UINT8_EXT:
3488 return V_028A7C_VGT_INDEX_8;
3489 case VK_INDEX_TYPE_UINT16:
3490 return V_028A7C_VGT_INDEX_16;
3491 case VK_INDEX_TYPE_UINT32:
3492 return V_028A7C_VGT_INDEX_32;
3493 default:
3494 unreachable("invalid index type");
3495 }
3496 }
3497
3498 static uint32_t
3499 radv_get_vgt_index_size(uint32_t type)
3500 {
3501 switch (type) {
3502 case V_028A7C_VGT_INDEX_8:
3503 return 1;
3504 case V_028A7C_VGT_INDEX_16:
3505 return 2;
3506 case V_028A7C_VGT_INDEX_32:
3507 return 4;
3508 default:
3509 unreachable("invalid index type");
3510 }
3511 }
3512
3513 void radv_CmdBindIndexBuffer(
3514 VkCommandBuffer commandBuffer,
3515 VkBuffer buffer,
3516 VkDeviceSize offset,
3517 VkIndexType indexType)
3518 {
3519 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3520 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3521
3522 if (cmd_buffer->state.index_buffer == index_buffer &&
3523 cmd_buffer->state.index_offset == offset &&
3524 cmd_buffer->state.index_type == indexType) {
3525 /* No state changes. */
3526 return;
3527 }
3528
3529 cmd_buffer->state.index_buffer = index_buffer;
3530 cmd_buffer->state.index_offset = offset;
3531 cmd_buffer->state.index_type = vk_to_index_type(indexType);
3532 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3533 cmd_buffer->state.index_va += index_buffer->offset + offset;
3534
3535 int index_size = radv_get_vgt_index_size(vk_to_index_type(indexType));
3536 cmd_buffer->state.max_index_count = (index_buffer->size - offset) / index_size;
3537 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3538 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3539 }
3540
3541
3542 static void
3543 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3544 VkPipelineBindPoint bind_point,
3545 struct radv_descriptor_set *set, unsigned idx)
3546 {
3547 struct radeon_winsys *ws = cmd_buffer->device->ws;
3548
3549 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3550
3551 assert(set);
3552 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3553
3554 if (!cmd_buffer->device->use_global_bo_list) {
3555 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3556 if (set->descriptors[j])
3557 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3558 }
3559
3560 if(set->bo)
3561 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3562 }
3563
3564 void radv_CmdBindDescriptorSets(
3565 VkCommandBuffer commandBuffer,
3566 VkPipelineBindPoint pipelineBindPoint,
3567 VkPipelineLayout _layout,
3568 uint32_t firstSet,
3569 uint32_t descriptorSetCount,
3570 const VkDescriptorSet* pDescriptorSets,
3571 uint32_t dynamicOffsetCount,
3572 const uint32_t* pDynamicOffsets)
3573 {
3574 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3575 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3576 unsigned dyn_idx = 0;
3577
3578 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3579 struct radv_descriptor_state *descriptors_state =
3580 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3581
3582 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3583 unsigned idx = i + firstSet;
3584 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3585
3586 /* If the set is already bound we only need to update the
3587 * (potentially changed) dynamic offsets. */
3588 if (descriptors_state->sets[idx] != set ||
3589 !(descriptors_state->valid & (1u << idx))) {
3590 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3591 }
3592
3593 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3594 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3595 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3596 assert(dyn_idx < dynamicOffsetCount);
3597
3598 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3599 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3600 dst[0] = va;
3601 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3602 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3603 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3604 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3605 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3606 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3607
3608 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
3609 dst[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3610 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3611 S_008F0C_RESOURCE_LEVEL(1);
3612 } else {
3613 dst[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3614 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3615 }
3616
3617 cmd_buffer->push_constant_stages |=
3618 set->layout->dynamic_shader_stages;
3619 }
3620 }
3621 }
3622
3623 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3624 struct radv_descriptor_set *set,
3625 struct radv_descriptor_set_layout *layout,
3626 VkPipelineBindPoint bind_point)
3627 {
3628 struct radv_descriptor_state *descriptors_state =
3629 radv_get_descriptors_state(cmd_buffer, bind_point);
3630 set->size = layout->size;
3631 set->layout = layout;
3632
3633 if (descriptors_state->push_set.capacity < set->size) {
3634 size_t new_size = MAX2(set->size, 1024);
3635 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3636 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3637
3638 free(set->mapped_ptr);
3639 set->mapped_ptr = malloc(new_size);
3640
3641 if (!set->mapped_ptr) {
3642 descriptors_state->push_set.capacity = 0;
3643 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3644 return false;
3645 }
3646
3647 descriptors_state->push_set.capacity = new_size;
3648 }
3649
3650 return true;
3651 }
3652
3653 void radv_meta_push_descriptor_set(
3654 struct radv_cmd_buffer* cmd_buffer,
3655 VkPipelineBindPoint pipelineBindPoint,
3656 VkPipelineLayout _layout,
3657 uint32_t set,
3658 uint32_t descriptorWriteCount,
3659 const VkWriteDescriptorSet* pDescriptorWrites)
3660 {
3661 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3662 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3663 unsigned bo_offset;
3664
3665 assert(set == 0);
3666 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3667
3668 push_set->size = layout->set[set].layout->size;
3669 push_set->layout = layout->set[set].layout;
3670
3671 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3672 &bo_offset,
3673 (void**) &push_set->mapped_ptr))
3674 return;
3675
3676 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3677 push_set->va += bo_offset;
3678
3679 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3680 radv_descriptor_set_to_handle(push_set),
3681 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3682
3683 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3684 }
3685
3686 void radv_CmdPushDescriptorSetKHR(
3687 VkCommandBuffer commandBuffer,
3688 VkPipelineBindPoint pipelineBindPoint,
3689 VkPipelineLayout _layout,
3690 uint32_t set,
3691 uint32_t descriptorWriteCount,
3692 const VkWriteDescriptorSet* pDescriptorWrites)
3693 {
3694 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3695 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3696 struct radv_descriptor_state *descriptors_state =
3697 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3698 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3699
3700 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3701
3702 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3703 layout->set[set].layout,
3704 pipelineBindPoint))
3705 return;
3706
3707 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3708 * because it is invalid, according to Vulkan spec.
3709 */
3710 for (int i = 0; i < descriptorWriteCount; i++) {
3711 ASSERTED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
3712 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
3713 }
3714
3715 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3716 radv_descriptor_set_to_handle(push_set),
3717 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3718
3719 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3720 descriptors_state->push_dirty = true;
3721 }
3722
3723 void radv_CmdPushDescriptorSetWithTemplateKHR(
3724 VkCommandBuffer commandBuffer,
3725 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
3726 VkPipelineLayout _layout,
3727 uint32_t set,
3728 const void* pData)
3729 {
3730 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3731 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3732 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
3733 struct radv_descriptor_state *descriptors_state =
3734 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
3735 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3736
3737 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3738
3739 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3740 layout->set[set].layout,
3741 templ->bind_point))
3742 return;
3743
3744 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
3745 descriptorUpdateTemplate, pData);
3746
3747 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
3748 descriptors_state->push_dirty = true;
3749 }
3750
3751 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
3752 VkPipelineLayout layout,
3753 VkShaderStageFlags stageFlags,
3754 uint32_t offset,
3755 uint32_t size,
3756 const void* pValues)
3757 {
3758 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3759 memcpy(cmd_buffer->push_constants + offset, pValues, size);
3760 cmd_buffer->push_constant_stages |= stageFlags;
3761 }
3762
3763 VkResult radv_EndCommandBuffer(
3764 VkCommandBuffer commandBuffer)
3765 {
3766 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3767
3768 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
3769 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
3770 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
3771
3772 /* Make sure to sync all pending active queries at the end of
3773 * command buffer.
3774 */
3775 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
3776
3777 /* Since NGG streamout uses GDS, we need to make GDS idle when
3778 * we leave the IB, otherwise another process might overwrite
3779 * it while our shaders are busy.
3780 */
3781 if (cmd_buffer->gds_needed)
3782 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
3783
3784 si_emit_cache_flush(cmd_buffer);
3785 }
3786
3787 /* Make sure CP DMA is idle at the end of IBs because the kernel
3788 * doesn't wait for it.
3789 */
3790 si_cp_dma_wait_for_idle(cmd_buffer);
3791
3792 radv_describe_end_cmd_buffer(cmd_buffer);
3793
3794 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3795 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
3796
3797 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
3798 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3799
3800 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
3801
3802 return cmd_buffer->record_result;
3803 }
3804
3805 static void
3806 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
3807 {
3808 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3809
3810 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
3811 return;
3812
3813 assert(!pipeline->ctx_cs.cdw);
3814
3815 cmd_buffer->state.emitted_compute_pipeline = pipeline;
3816
3817 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
3818 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
3819
3820 cmd_buffer->compute_scratch_size_per_wave_needed = MAX2(cmd_buffer->compute_scratch_size_per_wave_needed,
3821 pipeline->scratch_bytes_per_wave);
3822 cmd_buffer->compute_scratch_waves_wanted = MAX2(cmd_buffer->compute_scratch_waves_wanted,
3823 pipeline->max_waves);
3824
3825 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3826 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
3827
3828 if (unlikely(cmd_buffer->device->trace_bo))
3829 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
3830 }
3831
3832 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
3833 VkPipelineBindPoint bind_point)
3834 {
3835 struct radv_descriptor_state *descriptors_state =
3836 radv_get_descriptors_state(cmd_buffer, bind_point);
3837
3838 descriptors_state->dirty |= descriptors_state->valid;
3839 }
3840
3841 void radv_CmdBindPipeline(
3842 VkCommandBuffer commandBuffer,
3843 VkPipelineBindPoint pipelineBindPoint,
3844 VkPipeline _pipeline)
3845 {
3846 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3847 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3848
3849 switch (pipelineBindPoint) {
3850 case VK_PIPELINE_BIND_POINT_COMPUTE:
3851 if (cmd_buffer->state.compute_pipeline == pipeline)
3852 return;
3853 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3854
3855 cmd_buffer->state.compute_pipeline = pipeline;
3856 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3857 break;
3858 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3859 if (cmd_buffer->state.pipeline == pipeline)
3860 return;
3861 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3862
3863 cmd_buffer->state.pipeline = pipeline;
3864 if (!pipeline)
3865 break;
3866
3867 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3868 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3869
3870 /* the new vertex shader might not have the same user regs */
3871 cmd_buffer->state.last_first_instance = -1;
3872 cmd_buffer->state.last_vertex_offset = -1;
3873
3874 /* Prefetch all pipeline shaders at first draw time. */
3875 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3876
3877 if ((cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI10 ||
3878 cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI12 ||
3879 cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI14) &&
3880 cmd_buffer->state.emitted_pipeline &&
3881 radv_pipeline_has_ngg(cmd_buffer->state.emitted_pipeline) &&
3882 !radv_pipeline_has_ngg(cmd_buffer->state.pipeline)) {
3883 /* Transitioning from NGG to legacy GS requires
3884 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
3885 * at the beginning of IBs when legacy GS ring pointers
3886 * are set.
3887 */
3888 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
3889 }
3890
3891 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3892 radv_bind_streamout_state(cmd_buffer, pipeline);
3893
3894 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3895 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3896 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3897 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3898
3899 if (radv_pipeline_has_tess(pipeline))
3900 cmd_buffer->tess_rings_needed = true;
3901 break;
3902 default:
3903 assert(!"invalid bind point");
3904 break;
3905 }
3906 }
3907
3908 void radv_CmdSetViewport(
3909 VkCommandBuffer commandBuffer,
3910 uint32_t firstViewport,
3911 uint32_t viewportCount,
3912 const VkViewport* pViewports)
3913 {
3914 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3915 struct radv_cmd_state *state = &cmd_buffer->state;
3916 ASSERTED const uint32_t total_count = firstViewport + viewportCount;
3917
3918 assert(firstViewport < MAX_VIEWPORTS);
3919 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3920
3921 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3922 pViewports, viewportCount * sizeof(*pViewports))) {
3923 return;
3924 }
3925
3926 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3927 viewportCount * sizeof(*pViewports));
3928
3929 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3930 }
3931
3932 void radv_CmdSetScissor(
3933 VkCommandBuffer commandBuffer,
3934 uint32_t firstScissor,
3935 uint32_t scissorCount,
3936 const VkRect2D* pScissors)
3937 {
3938 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3939 struct radv_cmd_state *state = &cmd_buffer->state;
3940 ASSERTED const uint32_t total_count = firstScissor + scissorCount;
3941
3942 assert(firstScissor < MAX_SCISSORS);
3943 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3944
3945 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3946 scissorCount * sizeof(*pScissors))) {
3947 return;
3948 }
3949
3950 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3951 scissorCount * sizeof(*pScissors));
3952
3953 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3954 }
3955
3956 void radv_CmdSetLineWidth(
3957 VkCommandBuffer commandBuffer,
3958 float lineWidth)
3959 {
3960 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3961
3962 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3963 return;
3964
3965 cmd_buffer->state.dynamic.line_width = lineWidth;
3966 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3967 }
3968
3969 void radv_CmdSetDepthBias(
3970 VkCommandBuffer commandBuffer,
3971 float depthBiasConstantFactor,
3972 float depthBiasClamp,
3973 float depthBiasSlopeFactor)
3974 {
3975 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3976 struct radv_cmd_state *state = &cmd_buffer->state;
3977
3978 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3979 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3980 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3981 return;
3982 }
3983
3984 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3985 state->dynamic.depth_bias.clamp = depthBiasClamp;
3986 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3987
3988 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3989 }
3990
3991 void radv_CmdSetBlendConstants(
3992 VkCommandBuffer commandBuffer,
3993 const float blendConstants[4])
3994 {
3995 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3996 struct radv_cmd_state *state = &cmd_buffer->state;
3997
3998 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3999 return;
4000
4001 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
4002
4003 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
4004 }
4005
4006 void radv_CmdSetDepthBounds(
4007 VkCommandBuffer commandBuffer,
4008 float minDepthBounds,
4009 float maxDepthBounds)
4010 {
4011 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4012 struct radv_cmd_state *state = &cmd_buffer->state;
4013
4014 if (state->dynamic.depth_bounds.min == minDepthBounds &&
4015 state->dynamic.depth_bounds.max == maxDepthBounds) {
4016 return;
4017 }
4018
4019 state->dynamic.depth_bounds.min = minDepthBounds;
4020 state->dynamic.depth_bounds.max = maxDepthBounds;
4021
4022 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
4023 }
4024
4025 void radv_CmdSetStencilCompareMask(
4026 VkCommandBuffer commandBuffer,
4027 VkStencilFaceFlags faceMask,
4028 uint32_t compareMask)
4029 {
4030 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4031 struct radv_cmd_state *state = &cmd_buffer->state;
4032 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
4033 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
4034
4035 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4036 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4037 return;
4038 }
4039
4040 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4041 state->dynamic.stencil_compare_mask.front = compareMask;
4042 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4043 state->dynamic.stencil_compare_mask.back = compareMask;
4044
4045 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
4046 }
4047
4048 void radv_CmdSetStencilWriteMask(
4049 VkCommandBuffer commandBuffer,
4050 VkStencilFaceFlags faceMask,
4051 uint32_t writeMask)
4052 {
4053 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4054 struct radv_cmd_state *state = &cmd_buffer->state;
4055 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
4056 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
4057
4058 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4059 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4060 return;
4061 }
4062
4063 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4064 state->dynamic.stencil_write_mask.front = writeMask;
4065 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4066 state->dynamic.stencil_write_mask.back = writeMask;
4067
4068 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
4069 }
4070
4071 void radv_CmdSetStencilReference(
4072 VkCommandBuffer commandBuffer,
4073 VkStencilFaceFlags faceMask,
4074 uint32_t reference)
4075 {
4076 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4077 struct radv_cmd_state *state = &cmd_buffer->state;
4078 bool front_same = state->dynamic.stencil_reference.front == reference;
4079 bool back_same = state->dynamic.stencil_reference.back == reference;
4080
4081 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4082 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4083 return;
4084 }
4085
4086 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4087 cmd_buffer->state.dynamic.stencil_reference.front = reference;
4088 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4089 cmd_buffer->state.dynamic.stencil_reference.back = reference;
4090
4091 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
4092 }
4093
4094 void radv_CmdSetDiscardRectangleEXT(
4095 VkCommandBuffer commandBuffer,
4096 uint32_t firstDiscardRectangle,
4097 uint32_t discardRectangleCount,
4098 const VkRect2D* pDiscardRectangles)
4099 {
4100 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4101 struct radv_cmd_state *state = &cmd_buffer->state;
4102 ASSERTED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
4103
4104 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
4105 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
4106
4107 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
4108 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
4109 return;
4110 }
4111
4112 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
4113 pDiscardRectangles, discardRectangleCount);
4114
4115 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
4116 }
4117
4118 void radv_CmdSetSampleLocationsEXT(
4119 VkCommandBuffer commandBuffer,
4120 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
4121 {
4122 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4123 struct radv_cmd_state *state = &cmd_buffer->state;
4124
4125 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
4126
4127 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
4128 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
4129 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
4130 typed_memcpy(&state->dynamic.sample_location.locations[0],
4131 pSampleLocationsInfo->pSampleLocations,
4132 pSampleLocationsInfo->sampleLocationsCount);
4133
4134 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
4135 }
4136
4137 void radv_CmdSetLineStippleEXT(
4138 VkCommandBuffer commandBuffer,
4139 uint32_t lineStippleFactor,
4140 uint16_t lineStipplePattern)
4141 {
4142 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4143 struct radv_cmd_state *state = &cmd_buffer->state;
4144
4145 state->dynamic.line_stipple.factor = lineStippleFactor;
4146 state->dynamic.line_stipple.pattern = lineStipplePattern;
4147
4148 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE;
4149 }
4150
4151 void radv_CmdExecuteCommands(
4152 VkCommandBuffer commandBuffer,
4153 uint32_t commandBufferCount,
4154 const VkCommandBuffer* pCmdBuffers)
4155 {
4156 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
4157
4158 assert(commandBufferCount > 0);
4159
4160 /* Emit pending flushes on primary prior to executing secondary */
4161 si_emit_cache_flush(primary);
4162
4163 for (uint32_t i = 0; i < commandBufferCount; i++) {
4164 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
4165
4166 primary->scratch_size_per_wave_needed = MAX2(primary->scratch_size_per_wave_needed,
4167 secondary->scratch_size_per_wave_needed);
4168 primary->scratch_waves_wanted = MAX2(primary->scratch_waves_wanted,
4169 secondary->scratch_waves_wanted);
4170 primary->compute_scratch_size_per_wave_needed = MAX2(primary->compute_scratch_size_per_wave_needed,
4171 secondary->compute_scratch_size_per_wave_needed);
4172 primary->compute_scratch_waves_wanted = MAX2(primary->compute_scratch_waves_wanted,
4173 secondary->compute_scratch_waves_wanted);
4174
4175 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
4176 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
4177 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
4178 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
4179 if (secondary->tess_rings_needed)
4180 primary->tess_rings_needed = true;
4181 if (secondary->sample_positions_needed)
4182 primary->sample_positions_needed = true;
4183 if (secondary->gds_needed)
4184 primary->gds_needed = true;
4185
4186 if (!secondary->state.framebuffer &&
4187 (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
4188 /* Emit the framebuffer state from primary if secondary
4189 * has been recorded without a framebuffer, otherwise
4190 * fast color/depth clears can't work.
4191 */
4192 radv_emit_framebuffer_state(primary);
4193 }
4194
4195 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
4196
4197
4198 /* When the secondary command buffer is compute only we don't
4199 * need to re-emit the current graphics pipeline.
4200 */
4201 if (secondary->state.emitted_pipeline) {
4202 primary->state.emitted_pipeline =
4203 secondary->state.emitted_pipeline;
4204 }
4205
4206 /* When the secondary command buffer is graphics only we don't
4207 * need to re-emit the current compute pipeline.
4208 */
4209 if (secondary->state.emitted_compute_pipeline) {
4210 primary->state.emitted_compute_pipeline =
4211 secondary->state.emitted_compute_pipeline;
4212 }
4213
4214 /* Only re-emit the draw packets when needed. */
4215 if (secondary->state.last_primitive_reset_en != -1) {
4216 primary->state.last_primitive_reset_en =
4217 secondary->state.last_primitive_reset_en;
4218 }
4219
4220 if (secondary->state.last_primitive_reset_index) {
4221 primary->state.last_primitive_reset_index =
4222 secondary->state.last_primitive_reset_index;
4223 }
4224
4225 if (secondary->state.last_ia_multi_vgt_param) {
4226 primary->state.last_ia_multi_vgt_param =
4227 secondary->state.last_ia_multi_vgt_param;
4228 }
4229
4230 primary->state.last_first_instance = secondary->state.last_first_instance;
4231 primary->state.last_num_instances = secondary->state.last_num_instances;
4232 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
4233 primary->state.last_sx_ps_downconvert = secondary->state.last_sx_ps_downconvert;
4234 primary->state.last_sx_blend_opt_epsilon = secondary->state.last_sx_blend_opt_epsilon;
4235 primary->state.last_sx_blend_opt_control = secondary->state.last_sx_blend_opt_control;
4236
4237 if (secondary->state.last_index_type != -1) {
4238 primary->state.last_index_type =
4239 secondary->state.last_index_type;
4240 }
4241 }
4242
4243 /* After executing commands from secondary buffers we have to dirty
4244 * some states.
4245 */
4246 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
4247 RADV_CMD_DIRTY_INDEX_BUFFER |
4248 RADV_CMD_DIRTY_DYNAMIC_ALL;
4249 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
4250 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
4251 }
4252
4253 VkResult radv_CreateCommandPool(
4254 VkDevice _device,
4255 const VkCommandPoolCreateInfo* pCreateInfo,
4256 const VkAllocationCallbacks* pAllocator,
4257 VkCommandPool* pCmdPool)
4258 {
4259 RADV_FROM_HANDLE(radv_device, device, _device);
4260 struct radv_cmd_pool *pool;
4261
4262 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
4263 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4264 if (pool == NULL)
4265 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4266
4267 if (pAllocator)
4268 pool->alloc = *pAllocator;
4269 else
4270 pool->alloc = device->alloc;
4271
4272 list_inithead(&pool->cmd_buffers);
4273 list_inithead(&pool->free_cmd_buffers);
4274
4275 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
4276
4277 *pCmdPool = radv_cmd_pool_to_handle(pool);
4278
4279 return VK_SUCCESS;
4280
4281 }
4282
4283 void radv_DestroyCommandPool(
4284 VkDevice _device,
4285 VkCommandPool commandPool,
4286 const VkAllocationCallbacks* pAllocator)
4287 {
4288 RADV_FROM_HANDLE(radv_device, device, _device);
4289 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4290
4291 if (!pool)
4292 return;
4293
4294 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4295 &pool->cmd_buffers, pool_link) {
4296 radv_cmd_buffer_destroy(cmd_buffer);
4297 }
4298
4299 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4300 &pool->free_cmd_buffers, pool_link) {
4301 radv_cmd_buffer_destroy(cmd_buffer);
4302 }
4303
4304 vk_free2(&device->alloc, pAllocator, pool);
4305 }
4306
4307 VkResult radv_ResetCommandPool(
4308 VkDevice device,
4309 VkCommandPool commandPool,
4310 VkCommandPoolResetFlags flags)
4311 {
4312 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4313 VkResult result;
4314
4315 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
4316 &pool->cmd_buffers, pool_link) {
4317 result = radv_reset_cmd_buffer(cmd_buffer);
4318 if (result != VK_SUCCESS)
4319 return result;
4320 }
4321
4322 return VK_SUCCESS;
4323 }
4324
4325 void radv_TrimCommandPool(
4326 VkDevice device,
4327 VkCommandPool commandPool,
4328 VkCommandPoolTrimFlags flags)
4329 {
4330 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4331
4332 if (!pool)
4333 return;
4334
4335 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4336 &pool->free_cmd_buffers, pool_link) {
4337 radv_cmd_buffer_destroy(cmd_buffer);
4338 }
4339 }
4340
4341 static void
4342 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
4343 uint32_t subpass_id)
4344 {
4345 struct radv_cmd_state *state = &cmd_buffer->state;
4346 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
4347
4348 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
4349 cmd_buffer->cs, 4096);
4350
4351 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
4352
4353 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
4354
4355 radv_describe_barrier_start(cmd_buffer, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC);
4356
4357 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4358 const uint32_t a = subpass->attachments[i].attachment;
4359 if (a == VK_ATTACHMENT_UNUSED)
4360 continue;
4361
4362 radv_handle_subpass_image_transition(cmd_buffer,
4363 subpass->attachments[i],
4364 true);
4365 }
4366
4367 radv_describe_barrier_end(cmd_buffer);
4368
4369 radv_cmd_buffer_clear_subpass(cmd_buffer);
4370
4371 assert(cmd_buffer->cs->cdw <= cdw_max);
4372 }
4373
4374 static void
4375 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
4376 {
4377 struct radv_cmd_state *state = &cmd_buffer->state;
4378 const struct radv_subpass *subpass = state->subpass;
4379 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
4380
4381 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4382
4383 radv_describe_barrier_start(cmd_buffer, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC);
4384
4385 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4386 const uint32_t a = subpass->attachments[i].attachment;
4387 if (a == VK_ATTACHMENT_UNUSED)
4388 continue;
4389
4390 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
4391 continue;
4392
4393 VkImageLayout layout = state->pass->attachments[a].final_layout;
4394 VkImageLayout stencil_layout = state->pass->attachments[a].stencil_final_layout;
4395 struct radv_subpass_attachment att = { a, layout, stencil_layout };
4396 radv_handle_subpass_image_transition(cmd_buffer, att, false);
4397 }
4398
4399 radv_describe_barrier_end(cmd_buffer);
4400 }
4401
4402 void
4403 radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer *cmd_buffer,
4404 const VkRenderPassBeginInfo *pRenderPassBegin)
4405 {
4406 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
4407 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
4408 VkResult result;
4409
4410 cmd_buffer->state.framebuffer = framebuffer;
4411 cmd_buffer->state.pass = pass;
4412 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
4413
4414 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
4415 if (result != VK_SUCCESS)
4416 return;
4417
4418 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
4419 if (result != VK_SUCCESS)
4420 return;
4421 }
4422
4423 void radv_CmdBeginRenderPass(
4424 VkCommandBuffer commandBuffer,
4425 const VkRenderPassBeginInfo* pRenderPassBegin,
4426 VkSubpassContents contents)
4427 {
4428 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4429
4430 radv_cmd_buffer_begin_render_pass(cmd_buffer, pRenderPassBegin);
4431
4432 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
4433 }
4434
4435 void radv_CmdBeginRenderPass2(
4436 VkCommandBuffer commandBuffer,
4437 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
4438 const VkSubpassBeginInfo* pSubpassBeginInfo)
4439 {
4440 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
4441 pSubpassBeginInfo->contents);
4442 }
4443
4444 void radv_CmdNextSubpass(
4445 VkCommandBuffer commandBuffer,
4446 VkSubpassContents contents)
4447 {
4448 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4449
4450 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
4451 radv_cmd_buffer_end_subpass(cmd_buffer);
4452 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
4453 }
4454
4455 void radv_CmdNextSubpass2(
4456 VkCommandBuffer commandBuffer,
4457 const VkSubpassBeginInfo* pSubpassBeginInfo,
4458 const VkSubpassEndInfo* pSubpassEndInfo)
4459 {
4460 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
4461 }
4462
4463 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
4464 {
4465 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
4466 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
4467 if (!radv_get_shader(pipeline, stage))
4468 continue;
4469
4470 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
4471 if (loc->sgpr_idx == -1)
4472 continue;
4473 uint32_t base_reg = pipeline->user_data_0[stage];
4474 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4475
4476 }
4477 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
4478 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
4479 if (loc->sgpr_idx != -1) {
4480 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
4481 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4482 }
4483 }
4484 }
4485
4486 static void
4487 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4488 uint32_t vertex_count,
4489 bool use_opaque)
4490 {
4491 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
4492 radeon_emit(cmd_buffer->cs, vertex_count);
4493 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
4494 S_0287F0_USE_OPAQUE(use_opaque));
4495 }
4496
4497 static void
4498 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
4499 uint64_t index_va,
4500 uint32_t index_count)
4501 {
4502 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
4503 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
4504 radeon_emit(cmd_buffer->cs, index_va);
4505 radeon_emit(cmd_buffer->cs, index_va >> 32);
4506 radeon_emit(cmd_buffer->cs, index_count);
4507 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
4508 }
4509
4510 static void
4511 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4512 bool indexed,
4513 uint32_t draw_count,
4514 uint64_t count_va,
4515 uint32_t stride)
4516 {
4517 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4518 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
4519 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
4520 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id;
4521 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
4522 bool predicating = cmd_buffer->state.predicating;
4523 assert(base_reg);
4524
4525 /* just reset draw state for vertex data */
4526 cmd_buffer->state.last_first_instance = -1;
4527 cmd_buffer->state.last_num_instances = -1;
4528 cmd_buffer->state.last_vertex_offset = -1;
4529
4530 if (draw_count == 1 && !count_va && !draw_id_enable) {
4531 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
4532 PKT3_DRAW_INDIRECT, 3, predicating));
4533 radeon_emit(cs, 0);
4534 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4535 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4536 radeon_emit(cs, di_src_sel);
4537 } else {
4538 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
4539 PKT3_DRAW_INDIRECT_MULTI,
4540 8, predicating));
4541 radeon_emit(cs, 0);
4542 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4543 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4544 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
4545 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
4546 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
4547 radeon_emit(cs, draw_count); /* count */
4548 radeon_emit(cs, count_va); /* count_addr */
4549 radeon_emit(cs, count_va >> 32);
4550 radeon_emit(cs, stride); /* stride */
4551 radeon_emit(cs, di_src_sel);
4552 }
4553 }
4554
4555 static void
4556 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
4557 const struct radv_draw_info *info)
4558 {
4559 struct radv_cmd_state *state = &cmd_buffer->state;
4560 struct radeon_winsys *ws = cmd_buffer->device->ws;
4561 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4562
4563 if (info->indirect) {
4564 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4565 uint64_t count_va = 0;
4566
4567 va += info->indirect->offset + info->indirect_offset;
4568
4569 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4570
4571 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
4572 radeon_emit(cs, 1);
4573 radeon_emit(cs, va);
4574 radeon_emit(cs, va >> 32);
4575
4576 if (info->count_buffer) {
4577 count_va = radv_buffer_get_va(info->count_buffer->bo);
4578 count_va += info->count_buffer->offset +
4579 info->count_buffer_offset;
4580
4581 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
4582 }
4583
4584 if (!state->subpass->view_mask) {
4585 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4586 info->indexed,
4587 info->count,
4588 count_va,
4589 info->stride);
4590 } else {
4591 unsigned i;
4592 for_each_bit(i, state->subpass->view_mask) {
4593 radv_emit_view_index(cmd_buffer, i);
4594
4595 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4596 info->indexed,
4597 info->count,
4598 count_va,
4599 info->stride);
4600 }
4601 }
4602 } else {
4603 assert(state->pipeline->graphics.vtx_base_sgpr);
4604
4605 if (info->vertex_offset != state->last_vertex_offset ||
4606 info->first_instance != state->last_first_instance) {
4607 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
4608 state->pipeline->graphics.vtx_emit_num);
4609
4610 radeon_emit(cs, info->vertex_offset);
4611 radeon_emit(cs, info->first_instance);
4612 if (state->pipeline->graphics.vtx_emit_num == 3)
4613 radeon_emit(cs, 0);
4614 state->last_first_instance = info->first_instance;
4615 state->last_vertex_offset = info->vertex_offset;
4616 }
4617
4618 if (state->last_num_instances != info->instance_count) {
4619 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
4620 radeon_emit(cs, info->instance_count);
4621 state->last_num_instances = info->instance_count;
4622 }
4623
4624 if (info->indexed) {
4625 int index_size = radv_get_vgt_index_size(state->index_type);
4626 uint64_t index_va;
4627
4628 /* Skip draw calls with 0-sized index buffers. They
4629 * cause a hang on some chips, like Navi10-14.
4630 */
4631 if (!cmd_buffer->state.max_index_count)
4632 return;
4633
4634 index_va = state->index_va;
4635 index_va += info->first_index * index_size;
4636
4637 if (!state->subpass->view_mask) {
4638 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4639 index_va,
4640 info->count);
4641 } else {
4642 unsigned i;
4643 for_each_bit(i, state->subpass->view_mask) {
4644 radv_emit_view_index(cmd_buffer, i);
4645
4646 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4647 index_va,
4648 info->count);
4649 }
4650 }
4651 } else {
4652 if (!state->subpass->view_mask) {
4653 radv_cs_emit_draw_packet(cmd_buffer,
4654 info->count,
4655 !!info->strmout_buffer);
4656 } else {
4657 unsigned i;
4658 for_each_bit(i, state->subpass->view_mask) {
4659 radv_emit_view_index(cmd_buffer, i);
4660
4661 radv_cs_emit_draw_packet(cmd_buffer,
4662 info->count,
4663 !!info->strmout_buffer);
4664 }
4665 }
4666 }
4667 }
4668 }
4669
4670 /*
4671 * Vega and raven have a bug which triggers if there are multiple context
4672 * register contexts active at the same time with different scissor values.
4673 *
4674 * There are two possible workarounds:
4675 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4676 * there is only ever 1 active set of scissor values at the same time.
4677 *
4678 * 2) Whenever the hardware switches contexts we have to set the scissor
4679 * registers again even if it is a noop. That way the new context gets
4680 * the correct scissor values.
4681 *
4682 * This implements option 2. radv_need_late_scissor_emission needs to
4683 * return true on affected HW if radv_emit_all_graphics_states sets
4684 * any context registers.
4685 */
4686 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
4687 const struct radv_draw_info *info)
4688 {
4689 struct radv_cmd_state *state = &cmd_buffer->state;
4690
4691 if (!cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
4692 return false;
4693
4694 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
4695 return true;
4696
4697 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
4698
4699 /* Index, vertex and streamout buffers don't change context regs, and
4700 * pipeline is already handled.
4701 */
4702 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
4703 RADV_CMD_DIRTY_VERTEX_BUFFER |
4704 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
4705 RADV_CMD_DIRTY_PIPELINE);
4706
4707 if (cmd_buffer->state.dirty & used_states)
4708 return true;
4709
4710 uint32_t primitive_reset_index =
4711 radv_get_primitive_reset_index(cmd_buffer);
4712
4713 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
4714 primitive_reset_index != state->last_primitive_reset_index)
4715 return true;
4716
4717 return false;
4718 }
4719
4720 static void
4721 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
4722 const struct radv_draw_info *info)
4723 {
4724 bool late_scissor_emission;
4725
4726 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
4727 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
4728 radv_emit_rbplus_state(cmd_buffer);
4729
4730 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
4731 radv_emit_graphics_pipeline(cmd_buffer);
4732
4733 /* This should be before the cmd_buffer->state.dirty is cleared
4734 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4735 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4736 late_scissor_emission =
4737 radv_need_late_scissor_emission(cmd_buffer, info);
4738
4739 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
4740 radv_emit_framebuffer_state(cmd_buffer);
4741
4742 if (info->indexed) {
4743 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
4744 radv_emit_index_buffer(cmd_buffer, info->indirect);
4745 } else {
4746 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4747 * so the state must be re-emitted before the next indexed
4748 * draw.
4749 */
4750 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
4751 cmd_buffer->state.last_index_type = -1;
4752 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
4753 }
4754 }
4755
4756 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
4757
4758 radv_emit_draw_registers(cmd_buffer, info);
4759
4760 if (late_scissor_emission)
4761 radv_emit_scissor(cmd_buffer);
4762 }
4763
4764 static void
4765 radv_draw(struct radv_cmd_buffer *cmd_buffer,
4766 const struct radv_draw_info *info)
4767 {
4768 struct radeon_info *rad_info =
4769 &cmd_buffer->device->physical_device->rad_info;
4770 bool has_prefetch =
4771 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4772 bool pipeline_is_dirty =
4773 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
4774 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
4775
4776 ASSERTED unsigned cdw_max =
4777 radeon_check_space(cmd_buffer->device->ws,
4778 cmd_buffer->cs, 4096);
4779
4780 if (likely(!info->indirect)) {
4781 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4782 * no workaround for indirect draws, but we can at least skip
4783 * direct draws.
4784 */
4785 if (unlikely(!info->instance_count))
4786 return;
4787
4788 /* Handle count == 0. */
4789 if (unlikely(!info->count && !info->strmout_buffer))
4790 return;
4791 }
4792
4793 radv_describe_draw(cmd_buffer);
4794
4795 /* Use optimal packet order based on whether we need to sync the
4796 * pipeline.
4797 */
4798 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4799 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4800 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4801 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4802 /* If we have to wait for idle, set all states first, so that
4803 * all SET packets are processed in parallel with previous draw
4804 * calls. Then upload descriptors, set shader pointers, and
4805 * draw, and prefetch at the end. This ensures that the time
4806 * the CUs are idle is very short. (there are only SET_SH
4807 * packets between the wait and the draw)
4808 */
4809 radv_emit_all_graphics_states(cmd_buffer, info);
4810 si_emit_cache_flush(cmd_buffer);
4811 /* <-- CUs are idle here --> */
4812
4813 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4814
4815 radv_emit_draw_packets(cmd_buffer, info);
4816 /* <-- CUs are busy here --> */
4817
4818 /* Start prefetches after the draw has been started. Both will
4819 * run in parallel, but starting the draw first is more
4820 * important.
4821 */
4822 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4823 radv_emit_prefetch_L2(cmd_buffer,
4824 cmd_buffer->state.pipeline, false);
4825 }
4826 } else {
4827 /* If we don't wait for idle, start prefetches first, then set
4828 * states, and draw at the end.
4829 */
4830 si_emit_cache_flush(cmd_buffer);
4831
4832 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4833 /* Only prefetch the vertex shader and VBO descriptors
4834 * in order to start the draw as soon as possible.
4835 */
4836 radv_emit_prefetch_L2(cmd_buffer,
4837 cmd_buffer->state.pipeline, true);
4838 }
4839
4840 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4841
4842 radv_emit_all_graphics_states(cmd_buffer, info);
4843 radv_emit_draw_packets(cmd_buffer, info);
4844
4845 /* Prefetch the remaining shaders after the draw has been
4846 * started.
4847 */
4848 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4849 radv_emit_prefetch_L2(cmd_buffer,
4850 cmd_buffer->state.pipeline, false);
4851 }
4852 }
4853
4854 /* Workaround for a VGT hang when streamout is enabled.
4855 * It must be done after drawing.
4856 */
4857 if (cmd_buffer->state.streamout.streamout_enabled &&
4858 (rad_info->family == CHIP_HAWAII ||
4859 rad_info->family == CHIP_TONGA ||
4860 rad_info->family == CHIP_FIJI)) {
4861 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
4862 }
4863
4864 assert(cmd_buffer->cs->cdw <= cdw_max);
4865 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
4866 }
4867
4868 void radv_CmdDraw(
4869 VkCommandBuffer commandBuffer,
4870 uint32_t vertexCount,
4871 uint32_t instanceCount,
4872 uint32_t firstVertex,
4873 uint32_t firstInstance)
4874 {
4875 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4876 struct radv_draw_info info = {};
4877
4878 info.count = vertexCount;
4879 info.instance_count = instanceCount;
4880 info.first_instance = firstInstance;
4881 info.vertex_offset = firstVertex;
4882
4883 radv_draw(cmd_buffer, &info);
4884 }
4885
4886 void radv_CmdDrawIndexed(
4887 VkCommandBuffer commandBuffer,
4888 uint32_t indexCount,
4889 uint32_t instanceCount,
4890 uint32_t firstIndex,
4891 int32_t vertexOffset,
4892 uint32_t firstInstance)
4893 {
4894 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4895 struct radv_draw_info info = {};
4896
4897 info.indexed = true;
4898 info.count = indexCount;
4899 info.instance_count = instanceCount;
4900 info.first_index = firstIndex;
4901 info.vertex_offset = vertexOffset;
4902 info.first_instance = firstInstance;
4903
4904 radv_draw(cmd_buffer, &info);
4905 }
4906
4907 void radv_CmdDrawIndirect(
4908 VkCommandBuffer commandBuffer,
4909 VkBuffer _buffer,
4910 VkDeviceSize offset,
4911 uint32_t drawCount,
4912 uint32_t stride)
4913 {
4914 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4915 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4916 struct radv_draw_info info = {};
4917
4918 info.count = drawCount;
4919 info.indirect = buffer;
4920 info.indirect_offset = offset;
4921 info.stride = stride;
4922
4923 radv_draw(cmd_buffer, &info);
4924 }
4925
4926 void radv_CmdDrawIndexedIndirect(
4927 VkCommandBuffer commandBuffer,
4928 VkBuffer _buffer,
4929 VkDeviceSize offset,
4930 uint32_t drawCount,
4931 uint32_t stride)
4932 {
4933 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4934 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4935 struct radv_draw_info info = {};
4936
4937 info.indexed = true;
4938 info.count = drawCount;
4939 info.indirect = buffer;
4940 info.indirect_offset = offset;
4941 info.stride = stride;
4942
4943 radv_draw(cmd_buffer, &info);
4944 }
4945
4946 void radv_CmdDrawIndirectCount(
4947 VkCommandBuffer commandBuffer,
4948 VkBuffer _buffer,
4949 VkDeviceSize offset,
4950 VkBuffer _countBuffer,
4951 VkDeviceSize countBufferOffset,
4952 uint32_t maxDrawCount,
4953 uint32_t stride)
4954 {
4955 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4956 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4957 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4958 struct radv_draw_info info = {};
4959
4960 info.count = maxDrawCount;
4961 info.indirect = buffer;
4962 info.indirect_offset = offset;
4963 info.count_buffer = count_buffer;
4964 info.count_buffer_offset = countBufferOffset;
4965 info.stride = stride;
4966
4967 radv_draw(cmd_buffer, &info);
4968 }
4969
4970 void radv_CmdDrawIndexedIndirectCount(
4971 VkCommandBuffer commandBuffer,
4972 VkBuffer _buffer,
4973 VkDeviceSize offset,
4974 VkBuffer _countBuffer,
4975 VkDeviceSize countBufferOffset,
4976 uint32_t maxDrawCount,
4977 uint32_t stride)
4978 {
4979 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4980 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4981 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4982 struct radv_draw_info info = {};
4983
4984 info.indexed = true;
4985 info.count = maxDrawCount;
4986 info.indirect = buffer;
4987 info.indirect_offset = offset;
4988 info.count_buffer = count_buffer;
4989 info.count_buffer_offset = countBufferOffset;
4990 info.stride = stride;
4991
4992 radv_draw(cmd_buffer, &info);
4993 }
4994
4995 struct radv_dispatch_info {
4996 /**
4997 * Determine the layout of the grid (in block units) to be used.
4998 */
4999 uint32_t blocks[3];
5000
5001 /**
5002 * A starting offset for the grid. If unaligned is set, the offset
5003 * must still be aligned.
5004 */
5005 uint32_t offsets[3];
5006 /**
5007 * Whether it's an unaligned compute dispatch.
5008 */
5009 bool unaligned;
5010
5011 /**
5012 * Indirect compute parameters resource.
5013 */
5014 struct radv_buffer *indirect;
5015 uint64_t indirect_offset;
5016 };
5017
5018 static void
5019 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
5020 const struct radv_dispatch_info *info)
5021 {
5022 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
5023 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5024 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
5025 struct radeon_winsys *ws = cmd_buffer->device->ws;
5026 bool predicating = cmd_buffer->state.predicating;
5027 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5028 struct radv_userdata_info *loc;
5029
5030 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
5031 AC_UD_CS_GRID_SIZE);
5032
5033 ASSERTED unsigned cdw_max = radeon_check_space(ws, cs, 25);
5034
5035 if (compute_shader->info.wave_size == 32) {
5036 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
5037 dispatch_initiator |= S_00B800_CS_W32_EN(1);
5038 }
5039
5040 if (info->indirect) {
5041 uint64_t va = radv_buffer_get_va(info->indirect->bo);
5042
5043 va += info->indirect->offset + info->indirect_offset;
5044
5045 radv_cs_add_buffer(ws, cs, info->indirect->bo);
5046
5047 if (loc->sgpr_idx != -1) {
5048 for (unsigned i = 0; i < 3; ++i) {
5049 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5050 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5051 COPY_DATA_DST_SEL(COPY_DATA_REG));
5052 radeon_emit(cs, (va + 4 * i));
5053 radeon_emit(cs, (va + 4 * i) >> 32);
5054 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
5055 + loc->sgpr_idx * 4) >> 2) + i);
5056 radeon_emit(cs, 0);
5057 }
5058 }
5059
5060 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
5061 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
5062 PKT3_SHADER_TYPE_S(1));
5063 radeon_emit(cs, va);
5064 radeon_emit(cs, va >> 32);
5065 radeon_emit(cs, dispatch_initiator);
5066 } else {
5067 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
5068 PKT3_SHADER_TYPE_S(1));
5069 radeon_emit(cs, 1);
5070 radeon_emit(cs, va);
5071 radeon_emit(cs, va >> 32);
5072
5073 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
5074 PKT3_SHADER_TYPE_S(1));
5075 radeon_emit(cs, 0);
5076 radeon_emit(cs, dispatch_initiator);
5077 }
5078 } else {
5079 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
5080 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
5081
5082 if (info->unaligned) {
5083 unsigned *cs_block_size = compute_shader->info.cs.block_size;
5084 unsigned remainder[3];
5085
5086 /* If aligned, these should be an entire block size,
5087 * not 0.
5088 */
5089 remainder[0] = blocks[0] + cs_block_size[0] -
5090 align_u32_npot(blocks[0], cs_block_size[0]);
5091 remainder[1] = blocks[1] + cs_block_size[1] -
5092 align_u32_npot(blocks[1], cs_block_size[1]);
5093 remainder[2] = blocks[2] + cs_block_size[2] -
5094 align_u32_npot(blocks[2], cs_block_size[2]);
5095
5096 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
5097 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
5098 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
5099
5100 for(unsigned i = 0; i < 3; ++i) {
5101 assert(offsets[i] % cs_block_size[i] == 0);
5102 offsets[i] /= cs_block_size[i];
5103 }
5104
5105 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5106 radeon_emit(cs,
5107 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
5108 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
5109 radeon_emit(cs,
5110 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
5111 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
5112 radeon_emit(cs,
5113 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
5114 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
5115
5116 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
5117 }
5118
5119 if (loc->sgpr_idx != -1) {
5120 assert(loc->num_sgprs == 3);
5121
5122 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
5123 loc->sgpr_idx * 4, 3);
5124 radeon_emit(cs, blocks[0]);
5125 radeon_emit(cs, blocks[1]);
5126 radeon_emit(cs, blocks[2]);
5127 }
5128
5129 if (offsets[0] || offsets[1] || offsets[2]) {
5130 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
5131 radeon_emit(cs, offsets[0]);
5132 radeon_emit(cs, offsets[1]);
5133 radeon_emit(cs, offsets[2]);
5134
5135 /* The blocks in the packet are not counts but end values. */
5136 for (unsigned i = 0; i < 3; ++i)
5137 blocks[i] += offsets[i];
5138 } else {
5139 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
5140 }
5141
5142 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
5143 PKT3_SHADER_TYPE_S(1));
5144 radeon_emit(cs, blocks[0]);
5145 radeon_emit(cs, blocks[1]);
5146 radeon_emit(cs, blocks[2]);
5147 radeon_emit(cs, dispatch_initiator);
5148 }
5149
5150 assert(cmd_buffer->cs->cdw <= cdw_max);
5151 }
5152
5153 static void
5154 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
5155 {
5156 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5157 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5158 }
5159
5160 static void
5161 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
5162 const struct radv_dispatch_info *info)
5163 {
5164 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
5165 bool has_prefetch =
5166 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
5167 bool pipeline_is_dirty = pipeline &&
5168 pipeline != cmd_buffer->state.emitted_compute_pipeline;
5169
5170 radv_describe_dispatch(cmd_buffer, 8, 8, 8);
5171
5172 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5173 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5174 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
5175 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
5176 /* If we have to wait for idle, set all states first, so that
5177 * all SET packets are processed in parallel with previous draw
5178 * calls. Then upload descriptors, set shader pointers, and
5179 * dispatch, and prefetch at the end. This ensures that the
5180 * time the CUs are idle is very short. (there are only SET_SH
5181 * packets between the wait and the draw)
5182 */
5183 radv_emit_compute_pipeline(cmd_buffer);
5184 si_emit_cache_flush(cmd_buffer);
5185 /* <-- CUs are idle here --> */
5186
5187 radv_upload_compute_shader_descriptors(cmd_buffer);
5188
5189 radv_emit_dispatch_packets(cmd_buffer, info);
5190 /* <-- CUs are busy here --> */
5191
5192 /* Start prefetches after the dispatch has been started. Both
5193 * will run in parallel, but starting the dispatch first is
5194 * more important.
5195 */
5196 if (has_prefetch && pipeline_is_dirty) {
5197 radv_emit_shader_prefetch(cmd_buffer,
5198 pipeline->shaders[MESA_SHADER_COMPUTE]);
5199 }
5200 } else {
5201 /* If we don't wait for idle, start prefetches first, then set
5202 * states, and dispatch at the end.
5203 */
5204 si_emit_cache_flush(cmd_buffer);
5205
5206 if (has_prefetch && pipeline_is_dirty) {
5207 radv_emit_shader_prefetch(cmd_buffer,
5208 pipeline->shaders[MESA_SHADER_COMPUTE]);
5209 }
5210
5211 radv_upload_compute_shader_descriptors(cmd_buffer);
5212
5213 radv_emit_compute_pipeline(cmd_buffer);
5214 radv_emit_dispatch_packets(cmd_buffer, info);
5215 }
5216
5217 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
5218 }
5219
5220 void radv_CmdDispatchBase(
5221 VkCommandBuffer commandBuffer,
5222 uint32_t base_x,
5223 uint32_t base_y,
5224 uint32_t base_z,
5225 uint32_t x,
5226 uint32_t y,
5227 uint32_t z)
5228 {
5229 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5230 struct radv_dispatch_info info = {};
5231
5232 info.blocks[0] = x;
5233 info.blocks[1] = y;
5234 info.blocks[2] = z;
5235
5236 info.offsets[0] = base_x;
5237 info.offsets[1] = base_y;
5238 info.offsets[2] = base_z;
5239 radv_dispatch(cmd_buffer, &info);
5240 }
5241
5242 void radv_CmdDispatch(
5243 VkCommandBuffer commandBuffer,
5244 uint32_t x,
5245 uint32_t y,
5246 uint32_t z)
5247 {
5248 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
5249 }
5250
5251 void radv_CmdDispatchIndirect(
5252 VkCommandBuffer commandBuffer,
5253 VkBuffer _buffer,
5254 VkDeviceSize offset)
5255 {
5256 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5257 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5258 struct radv_dispatch_info info = {};
5259
5260 info.indirect = buffer;
5261 info.indirect_offset = offset;
5262
5263 radv_dispatch(cmd_buffer, &info);
5264 }
5265
5266 void radv_unaligned_dispatch(
5267 struct radv_cmd_buffer *cmd_buffer,
5268 uint32_t x,
5269 uint32_t y,
5270 uint32_t z)
5271 {
5272 struct radv_dispatch_info info = {};
5273
5274 info.blocks[0] = x;
5275 info.blocks[1] = y;
5276 info.blocks[2] = z;
5277 info.unaligned = 1;
5278
5279 radv_dispatch(cmd_buffer, &info);
5280 }
5281
5282 void
5283 radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer *cmd_buffer)
5284 {
5285 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
5286 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
5287
5288 cmd_buffer->state.pass = NULL;
5289 cmd_buffer->state.subpass = NULL;
5290 cmd_buffer->state.attachments = NULL;
5291 cmd_buffer->state.framebuffer = NULL;
5292 cmd_buffer->state.subpass_sample_locs = NULL;
5293 }
5294
5295 void radv_CmdEndRenderPass(
5296 VkCommandBuffer commandBuffer)
5297 {
5298 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5299
5300 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
5301
5302 radv_cmd_buffer_end_subpass(cmd_buffer);
5303
5304 radv_cmd_buffer_end_render_pass(cmd_buffer);
5305 }
5306
5307 void radv_CmdEndRenderPass2(
5308 VkCommandBuffer commandBuffer,
5309 const VkSubpassEndInfo* pSubpassEndInfo)
5310 {
5311 radv_CmdEndRenderPass(commandBuffer);
5312 }
5313
5314 /*
5315 * For HTILE we have the following interesting clear words:
5316 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5317 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5318 * 0xfffffff0: Clear depth to 1.0
5319 * 0x00000000: Clear depth to 0.0
5320 */
5321 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
5322 struct radv_image *image,
5323 const VkImageSubresourceRange *range)
5324 {
5325 assert(range->baseMipLevel == 0);
5326 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
5327 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
5328 struct radv_cmd_state *state = &cmd_buffer->state;
5329 uint32_t htile_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5330 VkClearDepthStencilValue value = {};
5331 struct radv_barrier_data barrier = {};
5332
5333 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5334 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5335
5336 barrier.layout_transitions.init_mask_ram = 1;
5337 radv_describe_layout_transition(cmd_buffer, &barrier);
5338
5339 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, htile_value);
5340
5341 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5342
5343 if (vk_format_is_stencil(image->vk_format))
5344 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
5345
5346 radv_set_ds_clear_metadata(cmd_buffer, image, range, value, aspects);
5347
5348 if (radv_image_is_tc_compat_htile(image)) {
5349 /* Initialize the TC-compat metada value to 0 because by
5350 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5351 * need have to conditionally update its value when performing
5352 * a fast depth clear.
5353 */
5354 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, range, 0);
5355 }
5356 }
5357
5358 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
5359 struct radv_image *image,
5360 VkImageLayout src_layout,
5361 bool src_render_loop,
5362 VkImageLayout dst_layout,
5363 bool dst_render_loop,
5364 unsigned src_queue_mask,
5365 unsigned dst_queue_mask,
5366 const VkImageSubresourceRange *range,
5367 struct radv_sample_locations_state *sample_locs)
5368 {
5369 if (!radv_image_has_htile(image))
5370 return;
5371
5372 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5373 radv_initialize_htile(cmd_buffer, image, range);
5374 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5375 radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5376 radv_initialize_htile(cmd_buffer, image, range);
5377 } else if (radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5378 !radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5379 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5380 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5381
5382 radv_decompress_depth_stencil(cmd_buffer, image, range,
5383 sample_locs);
5384
5385 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5386 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5387 }
5388 }
5389
5390 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
5391 struct radv_image *image,
5392 const VkImageSubresourceRange *range,
5393 uint32_t value)
5394 {
5395 struct radv_cmd_state *state = &cmd_buffer->state;
5396 struct radv_barrier_data barrier = {};
5397
5398 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5399 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5400
5401 barrier.layout_transitions.init_mask_ram = 1;
5402 radv_describe_layout_transition(cmd_buffer, &barrier);
5403
5404 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
5405
5406 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5407 }
5408
5409 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
5410 struct radv_image *image,
5411 const VkImageSubresourceRange *range)
5412 {
5413 struct radv_cmd_state *state = &cmd_buffer->state;
5414 static const uint32_t fmask_clear_values[4] = {
5415 0x00000000,
5416 0x02020202,
5417 0xE4E4E4E4,
5418 0x76543210
5419 };
5420 uint32_t log2_samples = util_logbase2(image->info.samples);
5421 uint32_t value = fmask_clear_values[log2_samples];
5422 struct radv_barrier_data barrier = {};
5423
5424 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5425 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5426
5427 barrier.layout_transitions.init_mask_ram = 1;
5428 radv_describe_layout_transition(cmd_buffer, &barrier);
5429
5430 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
5431
5432 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5433 }
5434
5435 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
5436 struct radv_image *image,
5437 const VkImageSubresourceRange *range, uint32_t value)
5438 {
5439 struct radv_cmd_state *state = &cmd_buffer->state;
5440 struct radv_barrier_data barrier = {};
5441 unsigned size = 0;
5442
5443 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5444 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5445
5446 barrier.layout_transitions.init_mask_ram = 1;
5447 radv_describe_layout_transition(cmd_buffer, &barrier);
5448
5449 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
5450
5451 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
5452 /* When DCC is enabled with mipmaps, some levels might not
5453 * support fast clears and we have to initialize them as "fully
5454 * expanded".
5455 */
5456 /* Compute the size of all fast clearable DCC levels. */
5457 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
5458 struct legacy_surf_level *surf_level =
5459 &image->planes[0].surface.u.legacy.level[i];
5460 unsigned dcc_fast_clear_size =
5461 surf_level->dcc_slice_fast_clear_size * image->info.array_size;
5462
5463 if (!dcc_fast_clear_size)
5464 break;
5465
5466 size = surf_level->dcc_offset + dcc_fast_clear_size;
5467 }
5468
5469 /* Initialize the mipmap levels without DCC. */
5470 if (size != image->planes[0].surface.dcc_size) {
5471 state->flush_bits |=
5472 radv_fill_buffer(cmd_buffer, image->bo,
5473 image->offset + image->dcc_offset + size,
5474 image->planes[0].surface.dcc_size - size,
5475 0xffffffff);
5476 }
5477 }
5478
5479 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5480 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5481 }
5482
5483 /**
5484 * Initialize DCC/FMASK/CMASK metadata for a color image.
5485 */
5486 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
5487 struct radv_image *image,
5488 VkImageLayout src_layout,
5489 bool src_render_loop,
5490 VkImageLayout dst_layout,
5491 bool dst_render_loop,
5492 unsigned src_queue_mask,
5493 unsigned dst_queue_mask,
5494 const VkImageSubresourceRange *range)
5495 {
5496 if (radv_image_has_cmask(image)) {
5497 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5498
5499 /* TODO: clarify this. */
5500 if (radv_image_has_fmask(image)) {
5501 value = 0xccccccccu;
5502 }
5503
5504 radv_initialise_cmask(cmd_buffer, image, range, value);
5505 }
5506
5507 if (radv_image_has_fmask(image)) {
5508 radv_initialize_fmask(cmd_buffer, image, range);
5509 }
5510
5511 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5512 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5513 bool need_decompress_pass = false;
5514
5515 if (radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout,
5516 dst_render_loop,
5517 dst_queue_mask)) {
5518 value = 0x20202020u;
5519 need_decompress_pass = true;
5520 }
5521
5522 radv_initialize_dcc(cmd_buffer, image, range, value);
5523
5524 radv_update_fce_metadata(cmd_buffer, image, range,
5525 need_decompress_pass);
5526 }
5527
5528 if (radv_image_has_cmask(image) ||
5529 radv_dcc_enabled(image, range->baseMipLevel)) {
5530 uint32_t color_values[2] = {};
5531 radv_set_color_clear_metadata(cmd_buffer, image, range,
5532 color_values);
5533 }
5534 }
5535
5536 /**
5537 * Handle color image transitions for DCC/FMASK/CMASK.
5538 */
5539 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
5540 struct radv_image *image,
5541 VkImageLayout src_layout,
5542 bool src_render_loop,
5543 VkImageLayout dst_layout,
5544 bool dst_render_loop,
5545 unsigned src_queue_mask,
5546 unsigned dst_queue_mask,
5547 const VkImageSubresourceRange *range)
5548 {
5549 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5550 radv_init_color_image_metadata(cmd_buffer, image,
5551 src_layout, src_render_loop,
5552 dst_layout, dst_render_loop,
5553 src_queue_mask, dst_queue_mask,
5554 range);
5555 return;
5556 }
5557
5558 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5559 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
5560 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
5561 } else if (radv_layout_dcc_compressed(cmd_buffer->device, image, src_layout, src_render_loop, src_queue_mask) &&
5562 !radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout, dst_render_loop, dst_queue_mask)) {
5563 radv_decompress_dcc(cmd_buffer, image, range);
5564 } else if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5565 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5566 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5567 }
5568 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
5569 bool fce_eliminate = false, fmask_expand = false;
5570
5571 if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5572 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5573 fce_eliminate = true;
5574 }
5575
5576 if (radv_image_has_fmask(image)) {
5577 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
5578 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
5579 /* A FMASK decompress is required before doing
5580 * a MSAA decompress using FMASK.
5581 */
5582 fmask_expand = true;
5583 }
5584 }
5585
5586 if (fce_eliminate || fmask_expand)
5587 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5588
5589 if (fmask_expand) {
5590 struct radv_barrier_data barrier = {};
5591 barrier.layout_transitions.fmask_color_expand = 1;
5592 radv_describe_layout_transition(cmd_buffer, &barrier);
5593
5594 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
5595 }
5596 }
5597 }
5598
5599 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
5600 struct radv_image *image,
5601 VkImageLayout src_layout,
5602 bool src_render_loop,
5603 VkImageLayout dst_layout,
5604 bool dst_render_loop,
5605 uint32_t src_family,
5606 uint32_t dst_family,
5607 const VkImageSubresourceRange *range,
5608 struct radv_sample_locations_state *sample_locs)
5609 {
5610 if (image->exclusive && src_family != dst_family) {
5611 /* This is an acquire or a release operation and there will be
5612 * a corresponding release/acquire. Do the transition in the
5613 * most flexible queue. */
5614
5615 assert(src_family == cmd_buffer->queue_family_index ||
5616 dst_family == cmd_buffer->queue_family_index);
5617
5618 if (src_family == VK_QUEUE_FAMILY_EXTERNAL ||
5619 src_family == VK_QUEUE_FAMILY_FOREIGN_EXT)
5620 return;
5621
5622 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
5623 return;
5624
5625 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
5626 (src_family == RADV_QUEUE_GENERAL ||
5627 dst_family == RADV_QUEUE_GENERAL))
5628 return;
5629 }
5630
5631 if (src_layout == dst_layout)
5632 return;
5633
5634 unsigned src_queue_mask =
5635 radv_image_queue_family_mask(image, src_family,
5636 cmd_buffer->queue_family_index);
5637 unsigned dst_queue_mask =
5638 radv_image_queue_family_mask(image, dst_family,
5639 cmd_buffer->queue_family_index);
5640
5641 if (vk_format_is_depth(image->vk_format)) {
5642 radv_handle_depth_image_transition(cmd_buffer, image,
5643 src_layout, src_render_loop,
5644 dst_layout, dst_render_loop,
5645 src_queue_mask, dst_queue_mask,
5646 range, sample_locs);
5647 } else {
5648 radv_handle_color_image_transition(cmd_buffer, image,
5649 src_layout, src_render_loop,
5650 dst_layout, dst_render_loop,
5651 src_queue_mask, dst_queue_mask,
5652 range);
5653 }
5654 }
5655
5656 struct radv_barrier_info {
5657 enum rgp_barrier_reason reason;
5658 uint32_t eventCount;
5659 const VkEvent *pEvents;
5660 VkPipelineStageFlags srcStageMask;
5661 VkPipelineStageFlags dstStageMask;
5662 };
5663
5664 static void
5665 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
5666 uint32_t memoryBarrierCount,
5667 const VkMemoryBarrier *pMemoryBarriers,
5668 uint32_t bufferMemoryBarrierCount,
5669 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
5670 uint32_t imageMemoryBarrierCount,
5671 const VkImageMemoryBarrier *pImageMemoryBarriers,
5672 const struct radv_barrier_info *info)
5673 {
5674 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5675 enum radv_cmd_flush_bits src_flush_bits = 0;
5676 enum radv_cmd_flush_bits dst_flush_bits = 0;
5677
5678 radv_describe_barrier_start(cmd_buffer, info->reason);
5679
5680 for (unsigned i = 0; i < info->eventCount; ++i) {
5681 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
5682 uint64_t va = radv_buffer_get_va(event->bo);
5683
5684 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5685
5686 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
5687
5688 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
5689 assert(cmd_buffer->cs->cdw <= cdw_max);
5690 }
5691
5692 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
5693 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
5694 NULL);
5695 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
5696 NULL);
5697 }
5698
5699 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
5700 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
5701 NULL);
5702 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
5703 NULL);
5704 }
5705
5706 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5707 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5708
5709 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
5710 image);
5711 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
5712 image);
5713 }
5714
5715 /* The Vulkan spec 1.1.98 says:
5716 *
5717 * "An execution dependency with only
5718 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5719 * will only prevent that stage from executing in subsequently
5720 * submitted commands. As this stage does not perform any actual
5721 * execution, this is not observable - in effect, it does not delay
5722 * processing of subsequent commands. Similarly an execution dependency
5723 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5724 * will effectively not wait for any prior commands to complete."
5725 */
5726 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
5727 radv_stage_flush(cmd_buffer, info->srcStageMask);
5728 cmd_buffer->state.flush_bits |= src_flush_bits;
5729
5730 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5731 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5732
5733 const struct VkSampleLocationsInfoEXT *sample_locs_info =
5734 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
5735 SAMPLE_LOCATIONS_INFO_EXT);
5736 struct radv_sample_locations_state sample_locations = {};
5737
5738 if (sample_locs_info) {
5739 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
5740 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
5741 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
5742 sample_locations.count = sample_locs_info->sampleLocationsCount;
5743 typed_memcpy(&sample_locations.locations[0],
5744 sample_locs_info->pSampleLocations,
5745 sample_locs_info->sampleLocationsCount);
5746 }
5747
5748 radv_handle_image_transition(cmd_buffer, image,
5749 pImageMemoryBarriers[i].oldLayout,
5750 false, /* Outside of a renderpass we are never in a renderloop */
5751 pImageMemoryBarriers[i].newLayout,
5752 false, /* Outside of a renderpass we are never in a renderloop */
5753 pImageMemoryBarriers[i].srcQueueFamilyIndex,
5754 pImageMemoryBarriers[i].dstQueueFamilyIndex,
5755 &pImageMemoryBarriers[i].subresourceRange,
5756 sample_locs_info ? &sample_locations : NULL);
5757 }
5758
5759 /* Make sure CP DMA is idle because the driver might have performed a
5760 * DMA operation for copying or filling buffers/images.
5761 */
5762 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5763 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5764 si_cp_dma_wait_for_idle(cmd_buffer);
5765
5766 cmd_buffer->state.flush_bits |= dst_flush_bits;
5767
5768 radv_describe_barrier_end(cmd_buffer);
5769 }
5770
5771 void radv_CmdPipelineBarrier(
5772 VkCommandBuffer commandBuffer,
5773 VkPipelineStageFlags srcStageMask,
5774 VkPipelineStageFlags destStageMask,
5775 VkBool32 byRegion,
5776 uint32_t memoryBarrierCount,
5777 const VkMemoryBarrier* pMemoryBarriers,
5778 uint32_t bufferMemoryBarrierCount,
5779 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5780 uint32_t imageMemoryBarrierCount,
5781 const VkImageMemoryBarrier* pImageMemoryBarriers)
5782 {
5783 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5784 struct radv_barrier_info info;
5785
5786 info.reason = RGP_BARRIER_EXTERNAL_CMD_PIPELINE_BARRIER;
5787 info.eventCount = 0;
5788 info.pEvents = NULL;
5789 info.srcStageMask = srcStageMask;
5790 info.dstStageMask = destStageMask;
5791
5792 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5793 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5794 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5795 }
5796
5797
5798 static void write_event(struct radv_cmd_buffer *cmd_buffer,
5799 struct radv_event *event,
5800 VkPipelineStageFlags stageMask,
5801 unsigned value)
5802 {
5803 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5804 uint64_t va = radv_buffer_get_va(event->bo);
5805
5806 si_emit_cache_flush(cmd_buffer);
5807
5808 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5809
5810 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
5811
5812 /* Flags that only require a top-of-pipe event. */
5813 VkPipelineStageFlags top_of_pipe_flags =
5814 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
5815
5816 /* Flags that only require a post-index-fetch event. */
5817 VkPipelineStageFlags post_index_fetch_flags =
5818 top_of_pipe_flags |
5819 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
5820 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
5821
5822 /* Make sure CP DMA is idle because the driver might have performed a
5823 * DMA operation for copying or filling buffers/images.
5824 */
5825 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5826 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5827 si_cp_dma_wait_for_idle(cmd_buffer);
5828
5829 /* TODO: Emit EOS events for syncing PS/CS stages. */
5830
5831 if (!(stageMask & ~top_of_pipe_flags)) {
5832 /* Just need to sync the PFP engine. */
5833 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5834 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5835 S_370_WR_CONFIRM(1) |
5836 S_370_ENGINE_SEL(V_370_PFP));
5837 radeon_emit(cs, va);
5838 radeon_emit(cs, va >> 32);
5839 radeon_emit(cs, value);
5840 } else if (!(stageMask & ~post_index_fetch_flags)) {
5841 /* Sync ME because PFP reads index and indirect buffers. */
5842 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5843 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5844 S_370_WR_CONFIRM(1) |
5845 S_370_ENGINE_SEL(V_370_ME));
5846 radeon_emit(cs, va);
5847 radeon_emit(cs, va >> 32);
5848 radeon_emit(cs, value);
5849 } else {
5850 /* Otherwise, sync all prior GPU work using an EOP event. */
5851 si_cs_emit_write_event_eop(cs,
5852 cmd_buffer->device->physical_device->rad_info.chip_class,
5853 radv_cmd_buffer_uses_mec(cmd_buffer),
5854 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5855 EOP_DST_SEL_MEM,
5856 EOP_DATA_SEL_VALUE_32BIT, va, value,
5857 cmd_buffer->gfx9_eop_bug_va);
5858 }
5859
5860 assert(cmd_buffer->cs->cdw <= cdw_max);
5861 }
5862
5863 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
5864 VkEvent _event,
5865 VkPipelineStageFlags stageMask)
5866 {
5867 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5868 RADV_FROM_HANDLE(radv_event, event, _event);
5869
5870 write_event(cmd_buffer, event, stageMask, 1);
5871 }
5872
5873 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
5874 VkEvent _event,
5875 VkPipelineStageFlags stageMask)
5876 {
5877 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5878 RADV_FROM_HANDLE(radv_event, event, _event);
5879
5880 write_event(cmd_buffer, event, stageMask, 0);
5881 }
5882
5883 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
5884 uint32_t eventCount,
5885 const VkEvent* pEvents,
5886 VkPipelineStageFlags srcStageMask,
5887 VkPipelineStageFlags dstStageMask,
5888 uint32_t memoryBarrierCount,
5889 const VkMemoryBarrier* pMemoryBarriers,
5890 uint32_t bufferMemoryBarrierCount,
5891 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5892 uint32_t imageMemoryBarrierCount,
5893 const VkImageMemoryBarrier* pImageMemoryBarriers)
5894 {
5895 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5896 struct radv_barrier_info info;
5897
5898 info.reason = RGP_BARRIER_EXTERNAL_CMD_WAIT_EVENTS;
5899 info.eventCount = eventCount;
5900 info.pEvents = pEvents;
5901 info.srcStageMask = 0;
5902
5903 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5904 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5905 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5906 }
5907
5908
5909 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
5910 uint32_t deviceMask)
5911 {
5912 /* No-op */
5913 }
5914
5915 /* VK_EXT_conditional_rendering */
5916 void radv_CmdBeginConditionalRenderingEXT(
5917 VkCommandBuffer commandBuffer,
5918 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
5919 {
5920 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5921 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
5922 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5923 bool draw_visible = true;
5924 uint64_t pred_value = 0;
5925 uint64_t va, new_va;
5926 unsigned pred_offset;
5927
5928 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
5929
5930 /* By default, if the 32-bit value at offset in buffer memory is zero,
5931 * then the rendering commands are discarded, otherwise they are
5932 * executed as normal. If the inverted flag is set, all commands are
5933 * discarded if the value is non zero.
5934 */
5935 if (pConditionalRenderingBegin->flags &
5936 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
5937 draw_visible = false;
5938 }
5939
5940 si_emit_cache_flush(cmd_buffer);
5941
5942 /* From the Vulkan spec 1.1.107:
5943 *
5944 * "If the 32-bit value at offset in buffer memory is zero, then the
5945 * rendering commands are discarded, otherwise they are executed as
5946 * normal. If the value of the predicate in buffer memory changes while
5947 * conditional rendering is active, the rendering commands may be
5948 * discarded in an implementation-dependent way. Some implementations
5949 * may latch the value of the predicate upon beginning conditional
5950 * rendering while others may read it before every rendering command."
5951 *
5952 * But, the AMD hardware treats the predicate as a 64-bit value which
5953 * means we need a workaround in the driver. Luckily, it's not required
5954 * to support if the value changes when predication is active.
5955 *
5956 * The workaround is as follows:
5957 * 1) allocate a 64-value in the upload BO and initialize it to 0
5958 * 2) copy the 32-bit predicate value to the upload BO
5959 * 3) use the new allocated VA address for predication
5960 *
5961 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5962 * in ME (+ sync PFP) instead of PFP.
5963 */
5964 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
5965
5966 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
5967
5968 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5969 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5970 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5971 COPY_DATA_WR_CONFIRM);
5972 radeon_emit(cs, va);
5973 radeon_emit(cs, va >> 32);
5974 radeon_emit(cs, new_va);
5975 radeon_emit(cs, new_va >> 32);
5976
5977 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
5978 radeon_emit(cs, 0);
5979
5980 /* Enable predication for this command buffer. */
5981 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
5982 cmd_buffer->state.predicating = true;
5983
5984 /* Store conditional rendering user info. */
5985 cmd_buffer->state.predication_type = draw_visible;
5986 cmd_buffer->state.predication_va = new_va;
5987 }
5988
5989 void radv_CmdEndConditionalRenderingEXT(
5990 VkCommandBuffer commandBuffer)
5991 {
5992 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5993
5994 /* Disable predication for this command buffer. */
5995 si_emit_set_predication_state(cmd_buffer, false, 0);
5996 cmd_buffer->state.predicating = false;
5997
5998 /* Reset conditional rendering user info. */
5999 cmd_buffer->state.predication_type = -1;
6000 cmd_buffer->state.predication_va = 0;
6001 }
6002
6003 /* VK_EXT_transform_feedback */
6004 void radv_CmdBindTransformFeedbackBuffersEXT(
6005 VkCommandBuffer commandBuffer,
6006 uint32_t firstBinding,
6007 uint32_t bindingCount,
6008 const VkBuffer* pBuffers,
6009 const VkDeviceSize* pOffsets,
6010 const VkDeviceSize* pSizes)
6011 {
6012 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6013 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
6014 uint8_t enabled_mask = 0;
6015
6016 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
6017 for (uint32_t i = 0; i < bindingCount; i++) {
6018 uint32_t idx = firstBinding + i;
6019
6020 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
6021 sb[idx].offset = pOffsets[i];
6022
6023 if (!pSizes || pSizes[i] == VK_WHOLE_SIZE) {
6024 sb[idx].size = sb[idx].buffer->size - sb[idx].offset;
6025 } else {
6026 sb[idx].size = pSizes[i];
6027 }
6028
6029 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
6030 sb[idx].buffer->bo);
6031
6032 enabled_mask |= 1 << idx;
6033 }
6034
6035 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
6036
6037 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
6038 }
6039
6040 static void
6041 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
6042 {
6043 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6044 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6045
6046 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
6047 radeon_emit(cs,
6048 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
6049 S_028B94_RAST_STREAM(0) |
6050 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
6051 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
6052 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
6053 radeon_emit(cs, so->hw_enabled_mask &
6054 so->enabled_stream_buffers_mask);
6055
6056 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6057 }
6058
6059 static void
6060 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
6061 {
6062 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6063 bool old_streamout_enabled = so->streamout_enabled;
6064 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
6065
6066 so->streamout_enabled = enable;
6067
6068 so->hw_enabled_mask = so->enabled_mask |
6069 (so->enabled_mask << 4) |
6070 (so->enabled_mask << 8) |
6071 (so->enabled_mask << 12);
6072
6073 if (!cmd_buffer->device->physical_device->use_ngg_streamout &&
6074 ((old_streamout_enabled != so->streamout_enabled) ||
6075 (old_hw_enabled_mask != so->hw_enabled_mask)))
6076 radv_emit_streamout_enable(cmd_buffer);
6077
6078 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6079 cmd_buffer->gds_needed = true;
6080 cmd_buffer->gds_oa_needed = true;
6081 }
6082 }
6083
6084 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
6085 {
6086 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6087 unsigned reg_strmout_cntl;
6088
6089 /* The register is at different places on different ASICs. */
6090 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
6091 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
6092 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
6093 } else {
6094 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
6095 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
6096 }
6097
6098 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
6099 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
6100
6101 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
6102 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
6103 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
6104 radeon_emit(cs, 0);
6105 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
6106 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
6107 radeon_emit(cs, 4); /* poll interval */
6108 }
6109
6110 static void
6111 radv_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6112 uint32_t firstCounterBuffer,
6113 uint32_t counterBufferCount,
6114 const VkBuffer *pCounterBuffers,
6115 const VkDeviceSize *pCounterBufferOffsets)
6116
6117 {
6118 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
6119 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6120 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6121 uint32_t i;
6122
6123 radv_flush_vgt_streamout(cmd_buffer);
6124
6125 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6126 for_each_bit(i, so->enabled_mask) {
6127 int32_t counter_buffer_idx = i - firstCounterBuffer;
6128 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6129 counter_buffer_idx = -1;
6130
6131 /* AMD GCN binds streamout buffers as shader resources.
6132 * VGT only counts primitives and tells the shader through
6133 * SGPRs what to do.
6134 */
6135 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
6136 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
6137 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
6138
6139 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6140
6141 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6142 /* The array of counter buffers is optional. */
6143 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6144 uint64_t va = radv_buffer_get_va(buffer->bo);
6145
6146 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6147
6148 /* Append */
6149 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6150 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6151 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6152 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
6153 radeon_emit(cs, 0); /* unused */
6154 radeon_emit(cs, 0); /* unused */
6155 radeon_emit(cs, va); /* src address lo */
6156 radeon_emit(cs, va >> 32); /* src address hi */
6157
6158 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6159 } else {
6160 /* Start from the beginning. */
6161 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6162 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6163 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6164 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
6165 radeon_emit(cs, 0); /* unused */
6166 radeon_emit(cs, 0); /* unused */
6167 radeon_emit(cs, 0); /* unused */
6168 radeon_emit(cs, 0); /* unused */
6169 }
6170 }
6171
6172 radv_set_streamout_enable(cmd_buffer, true);
6173 }
6174
6175 static void
6176 gfx10_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6177 uint32_t firstCounterBuffer,
6178 uint32_t counterBufferCount,
6179 const VkBuffer *pCounterBuffers,
6180 const VkDeviceSize *pCounterBufferOffsets)
6181 {
6182 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6183 unsigned last_target = util_last_bit(so->enabled_mask) - 1;
6184 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6185 uint32_t i;
6186
6187 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6188 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6189
6190 /* Sync because the next streamout operation will overwrite GDS and we
6191 * have to make sure it's idle.
6192 * TODO: Improve by tracking if there is a streamout operation in
6193 * flight.
6194 */
6195 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
6196 si_emit_cache_flush(cmd_buffer);
6197
6198 for_each_bit(i, so->enabled_mask) {
6199 int32_t counter_buffer_idx = i - firstCounterBuffer;
6200 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6201 counter_buffer_idx = -1;
6202
6203 bool append = counter_buffer_idx >= 0 &&
6204 pCounterBuffers && pCounterBuffers[counter_buffer_idx];
6205 uint64_t va = 0;
6206
6207 if (append) {
6208 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6209
6210 va += radv_buffer_get_va(buffer->bo);
6211 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6212
6213 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6214 }
6215
6216 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
6217 radeon_emit(cs, S_411_SRC_SEL(append ? V_411_SRC_ADDR_TC_L2 : V_411_DATA) |
6218 S_411_DST_SEL(V_411_GDS) |
6219 S_411_CP_SYNC(i == last_target));
6220 radeon_emit(cs, va);
6221 radeon_emit(cs, va >> 32);
6222 radeon_emit(cs, 4 * i); /* destination in GDS */
6223 radeon_emit(cs, 0);
6224 radeon_emit(cs, S_414_BYTE_COUNT_GFX9(4) |
6225 S_414_DISABLE_WR_CONFIRM_GFX9(i != last_target));
6226 }
6227
6228 radv_set_streamout_enable(cmd_buffer, true);
6229 }
6230
6231 void radv_CmdBeginTransformFeedbackEXT(
6232 VkCommandBuffer commandBuffer,
6233 uint32_t firstCounterBuffer,
6234 uint32_t counterBufferCount,
6235 const VkBuffer* pCounterBuffers,
6236 const VkDeviceSize* pCounterBufferOffsets)
6237 {
6238 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6239
6240 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6241 gfx10_emit_streamout_begin(cmd_buffer,
6242 firstCounterBuffer, counterBufferCount,
6243 pCounterBuffers, pCounterBufferOffsets);
6244 } else {
6245 radv_emit_streamout_begin(cmd_buffer,
6246 firstCounterBuffer, counterBufferCount,
6247 pCounterBuffers, pCounterBufferOffsets);
6248 }
6249 }
6250
6251 static void
6252 radv_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6253 uint32_t firstCounterBuffer,
6254 uint32_t counterBufferCount,
6255 const VkBuffer *pCounterBuffers,
6256 const VkDeviceSize *pCounterBufferOffsets)
6257 {
6258 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6259 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6260 uint32_t i;
6261
6262 radv_flush_vgt_streamout(cmd_buffer);
6263
6264 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6265 for_each_bit(i, so->enabled_mask) {
6266 int32_t counter_buffer_idx = i - firstCounterBuffer;
6267 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6268 counter_buffer_idx = -1;
6269
6270 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6271 /* The array of counters buffer is optional. */
6272 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6273 uint64_t va = radv_buffer_get_va(buffer->bo);
6274
6275 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6276
6277 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6278 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6279 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6280 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
6281 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
6282 radeon_emit(cs, va); /* dst address lo */
6283 radeon_emit(cs, va >> 32); /* dst address hi */
6284 radeon_emit(cs, 0); /* unused */
6285 radeon_emit(cs, 0); /* unused */
6286
6287 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6288 }
6289
6290 /* Deactivate transform feedback by zeroing the buffer size.
6291 * The counters (primitives generated, primitives emitted) may
6292 * be enabled even if there is not buffer bound. This ensures
6293 * that the primitives-emitted query won't increment.
6294 */
6295 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
6296
6297 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6298 }
6299
6300 radv_set_streamout_enable(cmd_buffer, false);
6301 }
6302
6303 static void
6304 gfx10_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6305 uint32_t firstCounterBuffer,
6306 uint32_t counterBufferCount,
6307 const VkBuffer *pCounterBuffers,
6308 const VkDeviceSize *pCounterBufferOffsets)
6309 {
6310 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6311 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6312 uint32_t i;
6313
6314 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6315 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6316
6317 for_each_bit(i, so->enabled_mask) {
6318 int32_t counter_buffer_idx = i - firstCounterBuffer;
6319 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6320 counter_buffer_idx = -1;
6321
6322 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6323 /* The array of counters buffer is optional. */
6324 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6325 uint64_t va = radv_buffer_get_va(buffer->bo);
6326
6327 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6328
6329 si_cs_emit_write_event_eop(cs,
6330 cmd_buffer->device->physical_device->rad_info.chip_class,
6331 radv_cmd_buffer_uses_mec(cmd_buffer),
6332 V_028A90_PS_DONE, 0,
6333 EOP_DST_SEL_TC_L2,
6334 EOP_DATA_SEL_GDS,
6335 va, EOP_DATA_GDS(i, 1), 0);
6336
6337 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6338 }
6339 }
6340
6341 radv_set_streamout_enable(cmd_buffer, false);
6342 }
6343
6344 void radv_CmdEndTransformFeedbackEXT(
6345 VkCommandBuffer commandBuffer,
6346 uint32_t firstCounterBuffer,
6347 uint32_t counterBufferCount,
6348 const VkBuffer* pCounterBuffers,
6349 const VkDeviceSize* pCounterBufferOffsets)
6350 {
6351 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6352
6353 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6354 gfx10_emit_streamout_end(cmd_buffer,
6355 firstCounterBuffer, counterBufferCount,
6356 pCounterBuffers, pCounterBufferOffsets);
6357 } else {
6358 radv_emit_streamout_end(cmd_buffer,
6359 firstCounterBuffer, counterBufferCount,
6360 pCounterBuffers, pCounterBufferOffsets);
6361 }
6362 }
6363
6364 void radv_CmdDrawIndirectByteCountEXT(
6365 VkCommandBuffer commandBuffer,
6366 uint32_t instanceCount,
6367 uint32_t firstInstance,
6368 VkBuffer _counterBuffer,
6369 VkDeviceSize counterBufferOffset,
6370 uint32_t counterOffset,
6371 uint32_t vertexStride)
6372 {
6373 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6374 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
6375 struct radv_draw_info info = {};
6376
6377 info.instance_count = instanceCount;
6378 info.first_instance = firstInstance;
6379 info.strmout_buffer = counterBuffer;
6380 info.strmout_buffer_offset = counterBufferOffset;
6381 info.stride = vertexStride;
6382
6383 radv_draw(cmd_buffer, &info);
6384 }
6385
6386 /* VK_AMD_buffer_marker */
6387 void radv_CmdWriteBufferMarkerAMD(
6388 VkCommandBuffer commandBuffer,
6389 VkPipelineStageFlagBits pipelineStage,
6390 VkBuffer dstBuffer,
6391 VkDeviceSize dstOffset,
6392 uint32_t marker)
6393 {
6394 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6395 RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
6396 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6397 uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
6398
6399 si_emit_cache_flush(cmd_buffer);
6400
6401 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 12);
6402
6403 if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
6404 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
6405 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
6406 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
6407 COPY_DATA_WR_CONFIRM);
6408 radeon_emit(cs, marker);
6409 radeon_emit(cs, 0);
6410 radeon_emit(cs, va);
6411 radeon_emit(cs, va >> 32);
6412 } else {
6413 si_cs_emit_write_event_eop(cs,
6414 cmd_buffer->device->physical_device->rad_info.chip_class,
6415 radv_cmd_buffer_uses_mec(cmd_buffer),
6416 V_028A90_BOTTOM_OF_PIPE_TS, 0,
6417 EOP_DST_SEL_MEM,
6418 EOP_DATA_SEL_VALUE_32BIT,
6419 va, marker,
6420 cmd_buffer->gfx9_eop_bug_va);
6421 }
6422
6423 assert(cmd_buffer->cs->cdw <= cdw_max);
6424 }