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radv: remove radv_userdata_info::indirect field
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range);
61
62 const struct radv_dynamic_state default_dynamic_state = {
63 .viewport = {
64 .count = 0,
65 },
66 .scissor = {
67 .count = 0,
68 },
69 .line_width = 1.0f,
70 .depth_bias = {
71 .bias = 0.0f,
72 .clamp = 0.0f,
73 .slope = 0.0f,
74 },
75 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
76 .depth_bounds = {
77 .min = 0.0f,
78 .max = 1.0f,
79 },
80 .stencil_compare_mask = {
81 .front = ~0u,
82 .back = ~0u,
83 },
84 .stencil_write_mask = {
85 .front = ~0u,
86 .back = ~0u,
87 },
88 .stencil_reference = {
89 .front = 0u,
90 .back = 0u,
91 },
92 };
93
94 static void
95 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
96 const struct radv_dynamic_state *src)
97 {
98 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
99 uint32_t copy_mask = src->mask;
100 uint32_t dest_mask = 0;
101
102 /* Make sure to copy the number of viewports/scissors because they can
103 * only be specified at pipeline creation time.
104 */
105 dest->viewport.count = src->viewport.count;
106 dest->scissor.count = src->scissor.count;
107 dest->discard_rectangle.count = src->discard_rectangle.count;
108
109 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
110 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
111 src->viewport.count * sizeof(VkViewport))) {
112 typed_memcpy(dest->viewport.viewports,
113 src->viewport.viewports,
114 src->viewport.count);
115 dest_mask |= RADV_DYNAMIC_VIEWPORT;
116 }
117 }
118
119 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
120 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
121 src->scissor.count * sizeof(VkRect2D))) {
122 typed_memcpy(dest->scissor.scissors,
123 src->scissor.scissors, src->scissor.count);
124 dest_mask |= RADV_DYNAMIC_SCISSOR;
125 }
126 }
127
128 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
129 if (dest->line_width != src->line_width) {
130 dest->line_width = src->line_width;
131 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
132 }
133 }
134
135 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
136 if (memcmp(&dest->depth_bias, &src->depth_bias,
137 sizeof(src->depth_bias))) {
138 dest->depth_bias = src->depth_bias;
139 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
140 }
141 }
142
143 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
144 if (memcmp(&dest->blend_constants, &src->blend_constants,
145 sizeof(src->blend_constants))) {
146 typed_memcpy(dest->blend_constants,
147 src->blend_constants, 4);
148 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
149 }
150 }
151
152 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
153 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
154 sizeof(src->depth_bounds))) {
155 dest->depth_bounds = src->depth_bounds;
156 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
157 }
158 }
159
160 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
161 if (memcmp(&dest->stencil_compare_mask,
162 &src->stencil_compare_mask,
163 sizeof(src->stencil_compare_mask))) {
164 dest->stencil_compare_mask = src->stencil_compare_mask;
165 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
166 }
167 }
168
169 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
170 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
171 sizeof(src->stencil_write_mask))) {
172 dest->stencil_write_mask = src->stencil_write_mask;
173 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
174 }
175 }
176
177 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
178 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
179 sizeof(src->stencil_reference))) {
180 dest->stencil_reference = src->stencil_reference;
181 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
182 }
183 }
184
185 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
186 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
187 src->discard_rectangle.count * sizeof(VkRect2D))) {
188 typed_memcpy(dest->discard_rectangle.rectangles,
189 src->discard_rectangle.rectangles,
190 src->discard_rectangle.count);
191 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
192 }
193 }
194
195 cmd_buffer->state.dirty |= dest_mask;
196 }
197
198 static void
199 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
200 struct radv_pipeline *pipeline)
201 {
202 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
203 struct radv_shader_info *info;
204
205 if (!pipeline->streamout_shader)
206 return;
207
208 info = &pipeline->streamout_shader->info.info;
209 for (int i = 0; i < MAX_SO_BUFFERS; i++)
210 so->stride_in_dw[i] = info->so.strides[i];
211
212 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
213 }
214
215 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
216 {
217 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
218 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
219 }
220
221 enum ring_type radv_queue_family_to_ring(int f) {
222 switch (f) {
223 case RADV_QUEUE_GENERAL:
224 return RING_GFX;
225 case RADV_QUEUE_COMPUTE:
226 return RING_COMPUTE;
227 case RADV_QUEUE_TRANSFER:
228 return RING_DMA;
229 default:
230 unreachable("Unknown queue family");
231 }
232 }
233
234 static VkResult radv_create_cmd_buffer(
235 struct radv_device * device,
236 struct radv_cmd_pool * pool,
237 VkCommandBufferLevel level,
238 VkCommandBuffer* pCommandBuffer)
239 {
240 struct radv_cmd_buffer *cmd_buffer;
241 unsigned ring;
242 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
243 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
244 if (cmd_buffer == NULL)
245 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
246
247 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
248 cmd_buffer->device = device;
249 cmd_buffer->pool = pool;
250 cmd_buffer->level = level;
251
252 if (pool) {
253 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
254 cmd_buffer->queue_family_index = pool->queue_family_index;
255
256 } else {
257 /* Init the pool_link so we can safely call list_del when we destroy
258 * the command buffer
259 */
260 list_inithead(&cmd_buffer->pool_link);
261 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
262 }
263
264 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
265
266 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
267 if (!cmd_buffer->cs) {
268 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
269 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
270 }
271
272 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
273
274 list_inithead(&cmd_buffer->upload.list);
275
276 return VK_SUCCESS;
277 }
278
279 static void
280 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
281 {
282 list_del(&cmd_buffer->pool_link);
283
284 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
285 &cmd_buffer->upload.list, list) {
286 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
287 list_del(&up->list);
288 free(up);
289 }
290
291 if (cmd_buffer->upload.upload_bo)
292 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
293 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
294
295 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
296 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
297
298 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
299 }
300
301 static VkResult
302 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
303 {
304
305 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
306
307 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
308 &cmd_buffer->upload.list, list) {
309 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
310 list_del(&up->list);
311 free(up);
312 }
313
314 cmd_buffer->push_constant_stages = 0;
315 cmd_buffer->scratch_size_needed = 0;
316 cmd_buffer->compute_scratch_size_needed = 0;
317 cmd_buffer->esgs_ring_size_needed = 0;
318 cmd_buffer->gsvs_ring_size_needed = 0;
319 cmd_buffer->tess_rings_needed = false;
320 cmd_buffer->sample_positions_needed = false;
321
322 if (cmd_buffer->upload.upload_bo)
323 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
324 cmd_buffer->upload.upload_bo);
325 cmd_buffer->upload.offset = 0;
326
327 cmd_buffer->record_result = VK_SUCCESS;
328
329 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
330 cmd_buffer->descriptors[i].dirty = 0;
331 cmd_buffer->descriptors[i].valid = 0;
332 cmd_buffer->descriptors[i].push_dirty = false;
333 }
334
335 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
336 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
337 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
338 unsigned fence_offset, eop_bug_offset;
339 void *fence_ptr;
340
341 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0, &fence_offset,
342 &fence_ptr);
343 cmd_buffer->gfx9_fence_va =
344 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
345 cmd_buffer->gfx9_fence_va += fence_offset;
346
347 /* Allocate a buffer for the EOP bug on GFX9. */
348 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 0,
349 &eop_bug_offset, &fence_ptr);
350 cmd_buffer->gfx9_eop_bug_va =
351 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
352 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
353 }
354
355 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
356
357 return cmd_buffer->record_result;
358 }
359
360 static bool
361 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
362 uint64_t min_needed)
363 {
364 uint64_t new_size;
365 struct radeon_winsys_bo *bo;
366 struct radv_cmd_buffer_upload *upload;
367 struct radv_device *device = cmd_buffer->device;
368
369 new_size = MAX2(min_needed, 16 * 1024);
370 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
371
372 bo = device->ws->buffer_create(device->ws,
373 new_size, 4096,
374 RADEON_DOMAIN_GTT,
375 RADEON_FLAG_CPU_ACCESS|
376 RADEON_FLAG_NO_INTERPROCESS_SHARING |
377 RADEON_FLAG_32BIT);
378
379 if (!bo) {
380 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
381 return false;
382 }
383
384 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
385 if (cmd_buffer->upload.upload_bo) {
386 upload = malloc(sizeof(*upload));
387
388 if (!upload) {
389 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
390 device->ws->buffer_destroy(bo);
391 return false;
392 }
393
394 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
395 list_add(&upload->list, &cmd_buffer->upload.list);
396 }
397
398 cmd_buffer->upload.upload_bo = bo;
399 cmd_buffer->upload.size = new_size;
400 cmd_buffer->upload.offset = 0;
401 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
402
403 if (!cmd_buffer->upload.map) {
404 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
405 return false;
406 }
407
408 return true;
409 }
410
411 bool
412 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
413 unsigned size,
414 unsigned alignment,
415 unsigned *out_offset,
416 void **ptr)
417 {
418 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
419 if (offset + size > cmd_buffer->upload.size) {
420 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
421 return false;
422 offset = 0;
423 }
424
425 *out_offset = offset;
426 *ptr = cmd_buffer->upload.map + offset;
427
428 cmd_buffer->upload.offset = offset + size;
429 return true;
430 }
431
432 bool
433 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
434 unsigned size, unsigned alignment,
435 const void *data, unsigned *out_offset)
436 {
437 uint8_t *ptr;
438
439 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
440 out_offset, (void **)&ptr))
441 return false;
442
443 if (ptr)
444 memcpy(ptr, data, size);
445
446 return true;
447 }
448
449 static void
450 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
451 unsigned count, const uint32_t *data)
452 {
453 struct radeon_cmdbuf *cs = cmd_buffer->cs;
454
455 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
456
457 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
458 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
459 S_370_WR_CONFIRM(1) |
460 S_370_ENGINE_SEL(V_370_ME));
461 radeon_emit(cs, va);
462 radeon_emit(cs, va >> 32);
463 radeon_emit_array(cs, data, count);
464 }
465
466 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
467 {
468 struct radv_device *device = cmd_buffer->device;
469 struct radeon_cmdbuf *cs = cmd_buffer->cs;
470 uint64_t va;
471
472 va = radv_buffer_get_va(device->trace_bo);
473 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
474 va += 4;
475
476 ++cmd_buffer->state.trace_id;
477 radv_emit_write_data_packet(cmd_buffer, va, 1,
478 &cmd_buffer->state.trace_id);
479
480 radeon_check_space(cmd_buffer->device->ws, cs, 2);
481
482 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
483 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
484 }
485
486 static void
487 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
488 enum radv_cmd_flush_bits flags)
489 {
490 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
491 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
492 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
493
494 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
495
496 /* Force wait for graphics or compute engines to be idle. */
497 si_cs_emit_cache_flush(cmd_buffer->cs,
498 cmd_buffer->device->physical_device->rad_info.chip_class,
499 &cmd_buffer->gfx9_fence_idx,
500 cmd_buffer->gfx9_fence_va,
501 radv_cmd_buffer_uses_mec(cmd_buffer),
502 flags, cmd_buffer->gfx9_eop_bug_va);
503 }
504
505 if (unlikely(cmd_buffer->device->trace_bo))
506 radv_cmd_buffer_trace_emit(cmd_buffer);
507 }
508
509 static void
510 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
511 struct radv_pipeline *pipeline, enum ring_type ring)
512 {
513 struct radv_device *device = cmd_buffer->device;
514 uint32_t data[2];
515 uint64_t va;
516
517 va = radv_buffer_get_va(device->trace_bo);
518
519 switch (ring) {
520 case RING_GFX:
521 va += 8;
522 break;
523 case RING_COMPUTE:
524 va += 16;
525 break;
526 default:
527 assert(!"invalid ring type");
528 }
529
530 data[0] = (uintptr_t)pipeline;
531 data[1] = (uintptr_t)pipeline >> 32;
532
533 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
534 }
535
536 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
537 VkPipelineBindPoint bind_point,
538 struct radv_descriptor_set *set,
539 unsigned idx)
540 {
541 struct radv_descriptor_state *descriptors_state =
542 radv_get_descriptors_state(cmd_buffer, bind_point);
543
544 descriptors_state->sets[idx] = set;
545
546 descriptors_state->valid |= (1u << idx); /* active descriptors */
547 descriptors_state->dirty |= (1u << idx);
548 }
549
550 static void
551 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
552 VkPipelineBindPoint bind_point)
553 {
554 struct radv_descriptor_state *descriptors_state =
555 radv_get_descriptors_state(cmd_buffer, bind_point);
556 struct radv_device *device = cmd_buffer->device;
557 uint32_t data[MAX_SETS * 2] = {};
558 uint64_t va;
559 unsigned i;
560 va = radv_buffer_get_va(device->trace_bo) + 24;
561
562 for_each_bit(i, descriptors_state->valid) {
563 struct radv_descriptor_set *set = descriptors_state->sets[i];
564 data[i * 2] = (uintptr_t)set;
565 data[i * 2 + 1] = (uintptr_t)set >> 32;
566 }
567
568 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
569 }
570
571 struct radv_userdata_info *
572 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
573 gl_shader_stage stage,
574 int idx)
575 {
576 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
577 return &shader->info.user_sgprs_locs.shader_data[idx];
578 }
579
580 static void
581 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
582 struct radv_pipeline *pipeline,
583 gl_shader_stage stage,
584 int idx, uint64_t va)
585 {
586 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
587 uint32_t base_reg = pipeline->user_data_0[stage];
588 if (loc->sgpr_idx == -1)
589 return;
590
591 assert(loc->num_sgprs == 1);
592
593 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
594 base_reg + loc->sgpr_idx * 4, va, false);
595 }
596
597 static void
598 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
599 struct radv_pipeline *pipeline,
600 struct radv_descriptor_state *descriptors_state,
601 gl_shader_stage stage)
602 {
603 struct radv_device *device = cmd_buffer->device;
604 struct radeon_cmdbuf *cs = cmd_buffer->cs;
605 uint32_t sh_base = pipeline->user_data_0[stage];
606 struct radv_userdata_locations *locs =
607 &pipeline->shaders[stage]->info.user_sgprs_locs;
608 unsigned mask = locs->descriptor_sets_enabled;
609
610 mask &= descriptors_state->dirty & descriptors_state->valid;
611
612 while (mask) {
613 int start, count;
614
615 u_bit_scan_consecutive_range(&mask, &start, &count);
616
617 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
618 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
619
620 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
621 for (int i = 0; i < count; i++) {
622 struct radv_descriptor_set *set =
623 descriptors_state->sets[start + i];
624
625 radv_emit_shader_pointer_body(device, cs, set->va, true);
626 }
627 }
628 }
629
630 static void
631 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
632 struct radv_pipeline *pipeline)
633 {
634 int num_samples = pipeline->graphics.ms.num_samples;
635 struct radv_multisample_state *ms = &pipeline->graphics.ms;
636 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
637
638 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
639 cmd_buffer->sample_positions_needed = true;
640
641 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
642 return;
643
644 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
645 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
646 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
647
648 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
649
650 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
651
652 /* GFX9: Flush DFSM when the AA mode changes. */
653 if (cmd_buffer->device->dfsm_allowed) {
654 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
655 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
656 }
657
658 cmd_buffer->state.context_roll_without_scissor_emitted = true;
659 }
660
661 static void
662 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
663 struct radv_shader_variant *shader)
664 {
665 uint64_t va;
666
667 if (!shader)
668 return;
669
670 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
671
672 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
673 }
674
675 static void
676 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
677 struct radv_pipeline *pipeline,
678 bool vertex_stage_only)
679 {
680 struct radv_cmd_state *state = &cmd_buffer->state;
681 uint32_t mask = state->prefetch_L2_mask;
682
683 if (vertex_stage_only) {
684 /* Fast prefetch path for starting draws as soon as possible.
685 */
686 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
687 RADV_PREFETCH_VBO_DESCRIPTORS);
688 }
689
690 if (mask & RADV_PREFETCH_VS)
691 radv_emit_shader_prefetch(cmd_buffer,
692 pipeline->shaders[MESA_SHADER_VERTEX]);
693
694 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
695 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
696
697 if (mask & RADV_PREFETCH_TCS)
698 radv_emit_shader_prefetch(cmd_buffer,
699 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
700
701 if (mask & RADV_PREFETCH_TES)
702 radv_emit_shader_prefetch(cmd_buffer,
703 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
704
705 if (mask & RADV_PREFETCH_GS) {
706 radv_emit_shader_prefetch(cmd_buffer,
707 pipeline->shaders[MESA_SHADER_GEOMETRY]);
708 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
709 }
710
711 if (mask & RADV_PREFETCH_PS)
712 radv_emit_shader_prefetch(cmd_buffer,
713 pipeline->shaders[MESA_SHADER_FRAGMENT]);
714
715 state->prefetch_L2_mask &= ~mask;
716 }
717
718 static void
719 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
720 {
721 if (!cmd_buffer->device->physical_device->rbplus_allowed)
722 return;
723
724 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
725 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
726 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
727
728 unsigned sx_ps_downconvert = 0;
729 unsigned sx_blend_opt_epsilon = 0;
730 unsigned sx_blend_opt_control = 0;
731
732 for (unsigned i = 0; i < subpass->color_count; ++i) {
733 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
734 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
735 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
736 continue;
737 }
738
739 int idx = subpass->color_attachments[i].attachment;
740 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
741
742 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
743 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
744 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
745 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
746
747 bool has_alpha, has_rgb;
748
749 /* Set if RGB and A are present. */
750 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
751
752 if (format == V_028C70_COLOR_8 ||
753 format == V_028C70_COLOR_16 ||
754 format == V_028C70_COLOR_32)
755 has_rgb = !has_alpha;
756 else
757 has_rgb = true;
758
759 /* Check the colormask and export format. */
760 if (!(colormask & 0x7))
761 has_rgb = false;
762 if (!(colormask & 0x8))
763 has_alpha = false;
764
765 if (spi_format == V_028714_SPI_SHADER_ZERO) {
766 has_rgb = false;
767 has_alpha = false;
768 }
769
770 /* Disable value checking for disabled channels. */
771 if (!has_rgb)
772 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
773 if (!has_alpha)
774 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
775
776 /* Enable down-conversion for 32bpp and smaller formats. */
777 switch (format) {
778 case V_028C70_COLOR_8:
779 case V_028C70_COLOR_8_8:
780 case V_028C70_COLOR_8_8_8_8:
781 /* For 1 and 2-channel formats, use the superset thereof. */
782 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
783 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
784 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
785 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
786 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
787 }
788 break;
789
790 case V_028C70_COLOR_5_6_5:
791 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
792 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
793 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
794 }
795 break;
796
797 case V_028C70_COLOR_1_5_5_5:
798 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
799 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
800 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
801 }
802 break;
803
804 case V_028C70_COLOR_4_4_4_4:
805 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
806 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
807 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
808 }
809 break;
810
811 case V_028C70_COLOR_32:
812 if (swap == V_028C70_SWAP_STD &&
813 spi_format == V_028714_SPI_SHADER_32_R)
814 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
815 else if (swap == V_028C70_SWAP_ALT_REV &&
816 spi_format == V_028714_SPI_SHADER_32_AR)
817 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
818 break;
819
820 case V_028C70_COLOR_16:
821 case V_028C70_COLOR_16_16:
822 /* For 1-channel formats, use the superset thereof. */
823 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
824 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
825 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
826 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
827 if (swap == V_028C70_SWAP_STD ||
828 swap == V_028C70_SWAP_STD_REV)
829 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
830 else
831 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
832 }
833 break;
834
835 case V_028C70_COLOR_10_11_11:
836 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
837 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
838 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
839 }
840 break;
841
842 case V_028C70_COLOR_2_10_10_10:
843 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
844 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
845 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
846 }
847 break;
848 }
849 }
850
851 for (unsigned i = subpass->color_count; i < 8; ++i) {
852 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
853 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
854 }
855 /* TODO: avoid redundantly setting context registers */
856 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
857 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
858 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
859 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
860
861 cmd_buffer->state.context_roll_without_scissor_emitted = true;
862 }
863
864 static void
865 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
866 {
867 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
868
869 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
870 return;
871
872 radv_update_multisample_state(cmd_buffer, pipeline);
873
874 cmd_buffer->scratch_size_needed =
875 MAX2(cmd_buffer->scratch_size_needed,
876 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
877
878 if (!cmd_buffer->state.emitted_pipeline ||
879 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
880 pipeline->graphics.can_use_guardband)
881 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
882
883 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
884
885 if (!cmd_buffer->state.emitted_pipeline ||
886 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
887 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
888 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
889 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
890 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
891 cmd_buffer->state.context_roll_without_scissor_emitted = true;
892 }
893
894 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
895 if (!pipeline->shaders[i])
896 continue;
897
898 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
899 pipeline->shaders[i]->bo);
900 }
901
902 if (radv_pipeline_has_gs(pipeline))
903 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
904 pipeline->gs_copy_shader->bo);
905
906 if (unlikely(cmd_buffer->device->trace_bo))
907 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
908
909 cmd_buffer->state.emitted_pipeline = pipeline;
910
911 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
912 }
913
914 static void
915 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
916 {
917 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
918 cmd_buffer->state.dynamic.viewport.viewports);
919 }
920
921 static void
922 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
923 {
924 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
925
926 si_write_scissors(cmd_buffer->cs, 0, count,
927 cmd_buffer->state.dynamic.scissor.scissors,
928 cmd_buffer->state.dynamic.viewport.viewports,
929 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
930
931 cmd_buffer->state.context_roll_without_scissor_emitted = false;
932 }
933
934 static void
935 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
936 {
937 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
938 return;
939
940 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
941 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
942 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
943 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
944 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
945 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
946 S_028214_BR_Y(rect.offset.y + rect.extent.height));
947 }
948 }
949
950 static void
951 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
952 {
953 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
954
955 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
956 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
957 }
958
959 static void
960 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
961 {
962 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
963
964 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
965 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
966 }
967
968 static void
969 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
970 {
971 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
972
973 radeon_set_context_reg_seq(cmd_buffer->cs,
974 R_028430_DB_STENCILREFMASK, 2);
975 radeon_emit(cmd_buffer->cs,
976 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
977 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
978 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
979 S_028430_STENCILOPVAL(1));
980 radeon_emit(cmd_buffer->cs,
981 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
982 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
983 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
984 S_028434_STENCILOPVAL_BF(1));
985 }
986
987 static void
988 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
989 {
990 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
991
992 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
993 fui(d->depth_bounds.min));
994 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
995 fui(d->depth_bounds.max));
996 }
997
998 static void
999 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1000 {
1001 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1002 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1003 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1004
1005
1006 radeon_set_context_reg_seq(cmd_buffer->cs,
1007 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1008 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1009 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1010 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1011 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1012 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1013 }
1014
1015 static void
1016 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1017 int index,
1018 struct radv_attachment_info *att,
1019 struct radv_image *image,
1020 VkImageLayout layout)
1021 {
1022 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1023 struct radv_color_buffer_info *cb = &att->cb;
1024 uint32_t cb_color_info = cb->cb_color_info;
1025
1026 if (!radv_layout_dcc_compressed(image, layout,
1027 radv_image_queue_family_mask(image,
1028 cmd_buffer->queue_family_index,
1029 cmd_buffer->queue_family_index))) {
1030 cb_color_info &= C_028C70_DCC_ENABLE;
1031 }
1032
1033 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1034 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1035 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1036 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1037 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1038 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1039 radeon_emit(cmd_buffer->cs, cb_color_info);
1040 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1041 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1042 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1043 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1044 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1045 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1046
1047 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1048 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1049 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1050
1051 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1052 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1053 } else {
1054 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1055 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1056 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1057 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1058 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1059 radeon_emit(cmd_buffer->cs, cb_color_info);
1060 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1061 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1062 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1063 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1064 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1065 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1066
1067 if (is_vi) { /* DCC BASE */
1068 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1069 }
1070 }
1071
1072 if (radv_image_has_dcc(image)) {
1073 /* Drawing with DCC enabled also compresses colorbuffers. */
1074 radv_update_dcc_metadata(cmd_buffer, image, true);
1075 }
1076 }
1077
1078 static void
1079 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1080 struct radv_ds_buffer_info *ds,
1081 struct radv_image *image, VkImageLayout layout,
1082 bool requires_cond_exec)
1083 {
1084 uint32_t db_z_info = ds->db_z_info;
1085 uint32_t db_z_info_reg;
1086
1087 if (!radv_image_is_tc_compat_htile(image))
1088 return;
1089
1090 if (!radv_layout_has_htile(image, layout,
1091 radv_image_queue_family_mask(image,
1092 cmd_buffer->queue_family_index,
1093 cmd_buffer->queue_family_index))) {
1094 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1095 }
1096
1097 db_z_info &= C_028040_ZRANGE_PRECISION;
1098
1099 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1100 db_z_info_reg = R_028038_DB_Z_INFO;
1101 } else {
1102 db_z_info_reg = R_028040_DB_Z_INFO;
1103 }
1104
1105 /* When we don't know the last fast clear value we need to emit a
1106 * conditional packet that will eventually skip the following
1107 * SET_CONTEXT_REG packet.
1108 */
1109 if (requires_cond_exec) {
1110 uint64_t va = radv_buffer_get_va(image->bo);
1111 va += image->offset + image->tc_compat_zrange_offset;
1112
1113 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1114 radeon_emit(cmd_buffer->cs, va);
1115 radeon_emit(cmd_buffer->cs, va >> 32);
1116 radeon_emit(cmd_buffer->cs, 0);
1117 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1118 }
1119
1120 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1121 }
1122
1123 static void
1124 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1125 struct radv_ds_buffer_info *ds,
1126 struct radv_image *image,
1127 VkImageLayout layout)
1128 {
1129 uint32_t db_z_info = ds->db_z_info;
1130 uint32_t db_stencil_info = ds->db_stencil_info;
1131
1132 if (!radv_layout_has_htile(image, layout,
1133 radv_image_queue_family_mask(image,
1134 cmd_buffer->queue_family_index,
1135 cmd_buffer->queue_family_index))) {
1136 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1137 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1138 }
1139
1140 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1141 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1142
1143
1144 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1145 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1146 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1147 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1148 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1149
1150 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1151 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1152 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1153 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1154 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1155 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1156 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1157 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1158 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1159 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1160 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1161
1162 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1163 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1164 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1165 } else {
1166 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1167
1168 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1169 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1170 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1171 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1172 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1173 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1174 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1175 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1176 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1177 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1178
1179 }
1180
1181 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1182 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1183
1184 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1185 ds->pa_su_poly_offset_db_fmt_cntl);
1186 }
1187
1188 /**
1189 * Update the fast clear depth/stencil values if the image is bound as a
1190 * depth/stencil buffer.
1191 */
1192 static void
1193 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1194 struct radv_image *image,
1195 VkClearDepthStencilValue ds_clear_value,
1196 VkImageAspectFlags aspects)
1197 {
1198 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1199 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1200 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1201 struct radv_attachment_info *att;
1202 uint32_t att_idx;
1203
1204 if (!framebuffer || !subpass)
1205 return;
1206
1207 att_idx = subpass->depth_stencil_attachment.attachment;
1208 if (att_idx == VK_ATTACHMENT_UNUSED)
1209 return;
1210
1211 att = &framebuffer->attachments[att_idx];
1212 if (att->attachment->image != image)
1213 return;
1214
1215 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1216 radeon_emit(cs, ds_clear_value.stencil);
1217 radeon_emit(cs, fui(ds_clear_value.depth));
1218
1219 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1220 * only needed when clearing Z to 0.0.
1221 */
1222 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1223 ds_clear_value.depth == 0.0) {
1224 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1225
1226 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1227 layout, false);
1228 }
1229
1230 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1231 }
1232
1233 /**
1234 * Set the clear depth/stencil values to the image's metadata.
1235 */
1236 static void
1237 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1238 struct radv_image *image,
1239 VkClearDepthStencilValue ds_clear_value,
1240 VkImageAspectFlags aspects)
1241 {
1242 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1243 uint64_t va = radv_buffer_get_va(image->bo);
1244 unsigned reg_offset = 0, reg_count = 0;
1245
1246 va += image->offset + image->clear_value_offset;
1247
1248 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1249 ++reg_count;
1250 } else {
1251 ++reg_offset;
1252 va += 4;
1253 }
1254 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1255 ++reg_count;
1256
1257 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1258 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1259 S_370_WR_CONFIRM(1) |
1260 S_370_ENGINE_SEL(V_370_PFP));
1261 radeon_emit(cs, va);
1262 radeon_emit(cs, va >> 32);
1263 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1264 radeon_emit(cs, ds_clear_value.stencil);
1265 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1266 radeon_emit(cs, fui(ds_clear_value.depth));
1267 }
1268
1269 /**
1270 * Update the TC-compat metadata value for this image.
1271 */
1272 static void
1273 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1274 struct radv_image *image,
1275 uint32_t value)
1276 {
1277 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1278 uint64_t va = radv_buffer_get_va(image->bo);
1279 va += image->offset + image->tc_compat_zrange_offset;
1280
1281 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1282 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1283 S_370_WR_CONFIRM(1) |
1284 S_370_ENGINE_SEL(V_370_PFP));
1285 radeon_emit(cs, va);
1286 radeon_emit(cs, va >> 32);
1287 radeon_emit(cs, value);
1288 }
1289
1290 static void
1291 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1292 struct radv_image *image,
1293 VkClearDepthStencilValue ds_clear_value)
1294 {
1295 uint64_t va = radv_buffer_get_va(image->bo);
1296 va += image->offset + image->tc_compat_zrange_offset;
1297 uint32_t cond_val;
1298
1299 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1300 * depth clear value is 0.0f.
1301 */
1302 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1303
1304 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, cond_val);
1305 }
1306
1307 /**
1308 * Update the clear depth/stencil values for this image.
1309 */
1310 void
1311 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1312 struct radv_image *image,
1313 VkClearDepthStencilValue ds_clear_value,
1314 VkImageAspectFlags aspects)
1315 {
1316 assert(radv_image_has_htile(image));
1317
1318 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1319
1320 if (radv_image_is_tc_compat_htile(image) &&
1321 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1322 radv_update_tc_compat_zrange_metadata(cmd_buffer, image,
1323 ds_clear_value);
1324 }
1325
1326 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1327 aspects);
1328 }
1329
1330 /**
1331 * Load the clear depth/stencil values from the image's metadata.
1332 */
1333 static void
1334 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1335 struct radv_image *image)
1336 {
1337 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1338 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1339 uint64_t va = radv_buffer_get_va(image->bo);
1340 unsigned reg_offset = 0, reg_count = 0;
1341
1342 va += image->offset + image->clear_value_offset;
1343
1344 if (!radv_image_has_htile(image))
1345 return;
1346
1347 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1348 ++reg_count;
1349 } else {
1350 ++reg_offset;
1351 va += 4;
1352 }
1353 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1354 ++reg_count;
1355
1356 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1357
1358 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1359 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1360 radeon_emit(cs, va);
1361 radeon_emit(cs, va >> 32);
1362 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1363 radeon_emit(cs, reg_count);
1364 } else {
1365 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1366 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1367 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1368 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1369 radeon_emit(cs, va);
1370 radeon_emit(cs, va >> 32);
1371 radeon_emit(cs, reg >> 2);
1372 radeon_emit(cs, 0);
1373
1374 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1375 radeon_emit(cs, 0);
1376 }
1377 }
1378
1379 /*
1380 * With DCC some colors don't require CMASK elimination before being
1381 * used as a texture. This sets a predicate value to determine if the
1382 * cmask eliminate is required.
1383 */
1384 void
1385 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1386 struct radv_image *image, bool value)
1387 {
1388 uint64_t pred_val = value;
1389 uint64_t va = radv_buffer_get_va(image->bo);
1390 va += image->offset + image->fce_pred_offset;
1391
1392 assert(radv_image_has_dcc(image));
1393
1394 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1395 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1396 S_370_WR_CONFIRM(1) |
1397 S_370_ENGINE_SEL(V_370_PFP));
1398 radeon_emit(cmd_buffer->cs, va);
1399 radeon_emit(cmd_buffer->cs, va >> 32);
1400 radeon_emit(cmd_buffer->cs, pred_val);
1401 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1402 }
1403
1404 /**
1405 * Update the DCC predicate to reflect the compression state.
1406 */
1407 void
1408 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1409 struct radv_image *image, bool value)
1410 {
1411 uint64_t pred_val = value;
1412 uint64_t va = radv_buffer_get_va(image->bo);
1413 va += image->offset + image->dcc_pred_offset;
1414
1415 assert(radv_image_has_dcc(image));
1416
1417 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1418 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1419 S_370_WR_CONFIRM(1) |
1420 S_370_ENGINE_SEL(V_370_PFP));
1421 radeon_emit(cmd_buffer->cs, va);
1422 radeon_emit(cmd_buffer->cs, va >> 32);
1423 radeon_emit(cmd_buffer->cs, pred_val);
1424 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1425 }
1426
1427 /**
1428 * Update the fast clear color values if the image is bound as a color buffer.
1429 */
1430 static void
1431 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1432 struct radv_image *image,
1433 int cb_idx,
1434 uint32_t color_values[2])
1435 {
1436 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1437 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1438 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1439 struct radv_attachment_info *att;
1440 uint32_t att_idx;
1441
1442 if (!framebuffer || !subpass)
1443 return;
1444
1445 att_idx = subpass->color_attachments[cb_idx].attachment;
1446 if (att_idx == VK_ATTACHMENT_UNUSED)
1447 return;
1448
1449 att = &framebuffer->attachments[att_idx];
1450 if (att->attachment->image != image)
1451 return;
1452
1453 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1454 radeon_emit(cs, color_values[0]);
1455 radeon_emit(cs, color_values[1]);
1456
1457 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1458 }
1459
1460 /**
1461 * Set the clear color values to the image's metadata.
1462 */
1463 static void
1464 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1465 struct radv_image *image,
1466 uint32_t color_values[2])
1467 {
1468 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1469 uint64_t va = radv_buffer_get_va(image->bo);
1470
1471 va += image->offset + image->clear_value_offset;
1472
1473 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1474
1475 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1476 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1477 S_370_WR_CONFIRM(1) |
1478 S_370_ENGINE_SEL(V_370_PFP));
1479 radeon_emit(cs, va);
1480 radeon_emit(cs, va >> 32);
1481 radeon_emit(cs, color_values[0]);
1482 radeon_emit(cs, color_values[1]);
1483 }
1484
1485 /**
1486 * Update the clear color values for this image.
1487 */
1488 void
1489 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1490 struct radv_image *image,
1491 int cb_idx,
1492 uint32_t color_values[2])
1493 {
1494 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1495
1496 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
1497
1498 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1499 color_values);
1500 }
1501
1502 /**
1503 * Load the clear color values from the image's metadata.
1504 */
1505 static void
1506 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1507 struct radv_image *image,
1508 int cb_idx)
1509 {
1510 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1511 uint64_t va = radv_buffer_get_va(image->bo);
1512
1513 va += image->offset + image->clear_value_offset;
1514
1515 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1516 return;
1517
1518 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1519
1520 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1521 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1522 radeon_emit(cs, va);
1523 radeon_emit(cs, va >> 32);
1524 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1525 radeon_emit(cs, 2);
1526 } else {
1527 /* TODO: Figure out how to use LOAD_CONTEXT_REG on SI/CIK. */
1528 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1529 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1530 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1531 COPY_DATA_COUNT_SEL);
1532 radeon_emit(cs, va);
1533 radeon_emit(cs, va >> 32);
1534 radeon_emit(cs, reg >> 2);
1535 radeon_emit(cs, 0);
1536
1537 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1538 radeon_emit(cs, 0);
1539 }
1540 }
1541
1542 static void
1543 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1544 {
1545 int i;
1546 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1547 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1548 unsigned num_bpp64_colorbufs = 0;
1549
1550 /* this may happen for inherited secondary recording */
1551 if (!framebuffer)
1552 return;
1553
1554 for (i = 0; i < 8; ++i) {
1555 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1556 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1557 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1558 continue;
1559 }
1560
1561 int idx = subpass->color_attachments[i].attachment;
1562 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1563 struct radv_image *image = att->attachment->image;
1564 VkImageLayout layout = subpass->color_attachments[i].layout;
1565
1566 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1567
1568 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1569 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1570
1571 radv_load_color_clear_metadata(cmd_buffer, image, i);
1572
1573 if (image->surface.bpe >= 8)
1574 num_bpp64_colorbufs++;
1575 }
1576
1577 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1578 int idx = subpass->depth_stencil_attachment.attachment;
1579 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1580 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1581 struct radv_image *image = att->attachment->image;
1582 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1583 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1584 cmd_buffer->queue_family_index,
1585 cmd_buffer->queue_family_index);
1586 /* We currently don't support writing decompressed HTILE */
1587 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1588 radv_layout_is_htile_compressed(image, layout, queue_mask));
1589
1590 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1591
1592 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1593 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1594 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1595 }
1596 radv_load_ds_clear_metadata(cmd_buffer, image);
1597 } else {
1598 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1599 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1600 else
1601 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1602
1603 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1604 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1605 }
1606 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1607 S_028208_BR_X(framebuffer->width) |
1608 S_028208_BR_Y(framebuffer->height));
1609
1610 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1611 uint8_t watermark = 4; /* Default value for VI. */
1612
1613 /* For optimal DCC performance. */
1614 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1615 if (num_bpp64_colorbufs >= 5) {
1616 watermark = 8;
1617 } else {
1618 watermark = 6;
1619 }
1620 }
1621
1622 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
1623 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
1624 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark));
1625 }
1626
1627 if (cmd_buffer->device->dfsm_allowed) {
1628 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1629 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1630 }
1631
1632 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1633 }
1634
1635 static void
1636 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1637 {
1638 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1639 struct radv_cmd_state *state = &cmd_buffer->state;
1640
1641 if (state->index_type != state->last_index_type) {
1642 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1643 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1644 2, state->index_type);
1645 } else {
1646 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1647 radeon_emit(cs, state->index_type);
1648 }
1649
1650 state->last_index_type = state->index_type;
1651 }
1652
1653 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1654 radeon_emit(cs, state->index_va);
1655 radeon_emit(cs, state->index_va >> 32);
1656
1657 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1658 radeon_emit(cs, state->max_index_count);
1659
1660 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1661 }
1662
1663 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1664 {
1665 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1666 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1667 uint32_t pa_sc_mode_cntl_1 =
1668 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1669 uint32_t db_count_control;
1670
1671 if(!cmd_buffer->state.active_occlusion_queries) {
1672 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1673 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1674 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1675 has_perfect_queries) {
1676 /* Re-enable out-of-order rasterization if the
1677 * bound pipeline supports it and if it's has
1678 * been disabled before starting any perfect
1679 * occlusion queries.
1680 */
1681 radeon_set_context_reg(cmd_buffer->cs,
1682 R_028A4C_PA_SC_MODE_CNTL_1,
1683 pa_sc_mode_cntl_1);
1684 }
1685 }
1686 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1687 } else {
1688 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1689 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1690
1691 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1692 db_count_control =
1693 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1694 S_028004_SAMPLE_RATE(sample_rate) |
1695 S_028004_ZPASS_ENABLE(1) |
1696 S_028004_SLICE_EVEN_ENABLE(1) |
1697 S_028004_SLICE_ODD_ENABLE(1);
1698
1699 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1700 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1701 has_perfect_queries) {
1702 /* If the bound pipeline has enabled
1703 * out-of-order rasterization, we should
1704 * disable it before starting any perfect
1705 * occlusion queries.
1706 */
1707 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1708
1709 radeon_set_context_reg(cmd_buffer->cs,
1710 R_028A4C_PA_SC_MODE_CNTL_1,
1711 pa_sc_mode_cntl_1);
1712 }
1713 } else {
1714 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1715 S_028004_SAMPLE_RATE(sample_rate);
1716 }
1717 }
1718
1719 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1720
1721 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1722 }
1723
1724 static void
1725 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1726 {
1727 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1728
1729 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1730 radv_emit_viewport(cmd_buffer);
1731
1732 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1733 !cmd_buffer->device->physical_device->has_scissor_bug)
1734 radv_emit_scissor(cmd_buffer);
1735
1736 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1737 radv_emit_line_width(cmd_buffer);
1738
1739 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1740 radv_emit_blend_constants(cmd_buffer);
1741
1742 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1743 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1744 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1745 radv_emit_stencil(cmd_buffer);
1746
1747 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1748 radv_emit_depth_bounds(cmd_buffer);
1749
1750 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1751 radv_emit_depth_bias(cmd_buffer);
1752
1753 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1754 radv_emit_discard_rectangle(cmd_buffer);
1755
1756 cmd_buffer->state.dirty &= ~states;
1757 }
1758
1759 static void
1760 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1761 VkPipelineBindPoint bind_point)
1762 {
1763 struct radv_descriptor_state *descriptors_state =
1764 radv_get_descriptors_state(cmd_buffer, bind_point);
1765 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1766 unsigned bo_offset;
1767
1768 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1769 set->mapped_ptr,
1770 &bo_offset))
1771 return;
1772
1773 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1774 set->va += bo_offset;
1775 }
1776
1777 static void
1778 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1779 VkPipelineBindPoint bind_point)
1780 {
1781 struct radv_descriptor_state *descriptors_state =
1782 radv_get_descriptors_state(cmd_buffer, bind_point);
1783 uint32_t size = MAX_SETS * 4;
1784 uint32_t offset;
1785 void *ptr;
1786
1787 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1788 256, &offset, &ptr))
1789 return;
1790
1791 for (unsigned i = 0; i < MAX_SETS; i++) {
1792 uint32_t *uptr = ((uint32_t *)ptr) + i;
1793 uint64_t set_va = 0;
1794 struct radv_descriptor_set *set = descriptors_state->sets[i];
1795 if (descriptors_state->valid & (1u << i))
1796 set_va = set->va;
1797 uptr[0] = set_va & 0xffffffff;
1798 }
1799
1800 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1801 va += offset;
1802
1803 if (cmd_buffer->state.pipeline) {
1804 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1805 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1806 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1807
1808 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1809 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1810 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1811
1812 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1813 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1814 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1815
1816 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1817 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1818 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1819
1820 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1821 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1822 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1823 }
1824
1825 if (cmd_buffer->state.compute_pipeline)
1826 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1827 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1828 }
1829
1830 static void
1831 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1832 VkShaderStageFlags stages)
1833 {
1834 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1835 VK_PIPELINE_BIND_POINT_COMPUTE :
1836 VK_PIPELINE_BIND_POINT_GRAPHICS;
1837 struct radv_descriptor_state *descriptors_state =
1838 radv_get_descriptors_state(cmd_buffer, bind_point);
1839 struct radv_cmd_state *state = &cmd_buffer->state;
1840 bool flush_indirect_descriptors;
1841
1842 if (!descriptors_state->dirty)
1843 return;
1844
1845 if (descriptors_state->push_dirty)
1846 radv_flush_push_descriptors(cmd_buffer, bind_point);
1847
1848 flush_indirect_descriptors =
1849 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
1850 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
1851 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
1852 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
1853
1854 if (flush_indirect_descriptors)
1855 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1856
1857 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1858 cmd_buffer->cs,
1859 MAX_SETS * MESA_SHADER_STAGES * 4);
1860
1861 if (cmd_buffer->state.pipeline) {
1862 radv_foreach_stage(stage, stages) {
1863 if (!cmd_buffer->state.pipeline->shaders[stage])
1864 continue;
1865
1866 radv_emit_descriptor_pointers(cmd_buffer,
1867 cmd_buffer->state.pipeline,
1868 descriptors_state, stage);
1869 }
1870 }
1871
1872 if (cmd_buffer->state.compute_pipeline &&
1873 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
1874 radv_emit_descriptor_pointers(cmd_buffer,
1875 cmd_buffer->state.compute_pipeline,
1876 descriptors_state,
1877 MESA_SHADER_COMPUTE);
1878 }
1879
1880 descriptors_state->dirty = 0;
1881 descriptors_state->push_dirty = false;
1882
1883 assert(cmd_buffer->cs->cdw <= cdw_max);
1884
1885 if (unlikely(cmd_buffer->device->trace_bo))
1886 radv_save_descriptors(cmd_buffer, bind_point);
1887 }
1888
1889 static void
1890 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1891 VkShaderStageFlags stages)
1892 {
1893 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1894 ? cmd_buffer->state.compute_pipeline
1895 : cmd_buffer->state.pipeline;
1896 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1897 VK_PIPELINE_BIND_POINT_COMPUTE :
1898 VK_PIPELINE_BIND_POINT_GRAPHICS;
1899 struct radv_descriptor_state *descriptors_state =
1900 radv_get_descriptors_state(cmd_buffer, bind_point);
1901 struct radv_pipeline_layout *layout = pipeline->layout;
1902 struct radv_shader_variant *shader, *prev_shader;
1903 unsigned offset;
1904 void *ptr;
1905 uint64_t va;
1906
1907 stages &= cmd_buffer->push_constant_stages;
1908 if (!stages ||
1909 (!layout->push_constant_size && !layout->dynamic_offset_count))
1910 return;
1911
1912 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1913 16 * layout->dynamic_offset_count,
1914 256, &offset, &ptr))
1915 return;
1916
1917 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1918 memcpy((char*)ptr + layout->push_constant_size,
1919 descriptors_state->dynamic_buffers,
1920 16 * layout->dynamic_offset_count);
1921
1922 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1923 va += offset;
1924
1925 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1926 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1927
1928 prev_shader = NULL;
1929 radv_foreach_stage(stage, stages) {
1930 shader = radv_get_shader(pipeline, stage);
1931
1932 /* Avoid redundantly emitting the address for merged stages. */
1933 if (shader && shader != prev_shader) {
1934 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1935 AC_UD_PUSH_CONSTANTS, va);
1936
1937 prev_shader = shader;
1938 }
1939 }
1940
1941 cmd_buffer->push_constant_stages &= ~stages;
1942 assert(cmd_buffer->cs->cdw <= cdw_max);
1943 }
1944
1945 static void
1946 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1947 bool pipeline_is_dirty)
1948 {
1949 if ((pipeline_is_dirty ||
1950 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1951 cmd_buffer->state.pipeline->vertex_elements.count &&
1952 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
1953 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1954 unsigned vb_offset;
1955 void *vb_ptr;
1956 uint32_t i = 0;
1957 uint32_t count = velems->count;
1958 uint64_t va;
1959
1960 /* allocate some descriptor state for vertex buffers */
1961 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1962 &vb_offset, &vb_ptr))
1963 return;
1964
1965 for (i = 0; i < count; i++) {
1966 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1967 uint32_t offset;
1968 int vb = velems->binding[i];
1969 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1970 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1971
1972 va = radv_buffer_get_va(buffer->bo);
1973
1974 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1975 va += offset + buffer->offset;
1976 desc[0] = va;
1977 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1978 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1979 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1980 else
1981 desc[2] = buffer->size - offset;
1982 desc[3] = velems->rsrc_word3[i];
1983 }
1984
1985 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1986 va += vb_offset;
1987
1988 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1989 AC_UD_VS_VERTEX_BUFFERS, va);
1990
1991 cmd_buffer->state.vb_va = va;
1992 cmd_buffer->state.vb_size = count * 16;
1993 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
1994 }
1995 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1996 }
1997
1998 static void
1999 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2000 {
2001 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2002 struct radv_userdata_info *loc;
2003 uint32_t base_reg;
2004
2005 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2006 if (!radv_get_shader(pipeline, stage))
2007 continue;
2008
2009 loc = radv_lookup_user_sgpr(pipeline, stage,
2010 AC_UD_STREAMOUT_BUFFERS);
2011 if (loc->sgpr_idx == -1)
2012 continue;
2013
2014 base_reg = pipeline->user_data_0[stage];
2015
2016 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2017 base_reg + loc->sgpr_idx * 4, va, false);
2018 }
2019
2020 if (pipeline->gs_copy_shader) {
2021 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2022 if (loc->sgpr_idx != -1) {
2023 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2024
2025 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2026 base_reg + loc->sgpr_idx * 4, va, false);
2027 }
2028 }
2029 }
2030
2031 static void
2032 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2033 {
2034 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2035 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2036 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2037 unsigned so_offset;
2038 void *so_ptr;
2039 uint64_t va;
2040
2041 /* Allocate some descriptor state for streamout buffers. */
2042 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2043 MAX_SO_BUFFERS * 16, 256,
2044 &so_offset, &so_ptr))
2045 return;
2046
2047 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2048 struct radv_buffer *buffer = sb[i].buffer;
2049 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2050
2051 if (!(so->enabled_mask & (1 << i)))
2052 continue;
2053
2054 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2055
2056 va += sb[i].offset;
2057
2058 /* Set the descriptor.
2059 *
2060 * On VI, the format must be non-INVALID, otherwise
2061 * the buffer will be considered not bound and store
2062 * instructions will be no-ops.
2063 */
2064 desc[0] = va;
2065 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2066 desc[2] = 0xffffffff;
2067 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2068 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2069 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2070 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2071 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2072 }
2073
2074 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2075 va += so_offset;
2076
2077 radv_emit_streamout_buffers(cmd_buffer, va);
2078 }
2079
2080 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2081 }
2082
2083 static void
2084 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2085 {
2086 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2087 radv_flush_streamout_descriptors(cmd_buffer);
2088 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2089 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2090 }
2091
2092 struct radv_draw_info {
2093 /**
2094 * Number of vertices.
2095 */
2096 uint32_t count;
2097
2098 /**
2099 * Index of the first vertex.
2100 */
2101 int32_t vertex_offset;
2102
2103 /**
2104 * First instance id.
2105 */
2106 uint32_t first_instance;
2107
2108 /**
2109 * Number of instances.
2110 */
2111 uint32_t instance_count;
2112
2113 /**
2114 * First index (indexed draws only).
2115 */
2116 uint32_t first_index;
2117
2118 /**
2119 * Whether it's an indexed draw.
2120 */
2121 bool indexed;
2122
2123 /**
2124 * Indirect draw parameters resource.
2125 */
2126 struct radv_buffer *indirect;
2127 uint64_t indirect_offset;
2128 uint32_t stride;
2129
2130 /**
2131 * Draw count parameters resource.
2132 */
2133 struct radv_buffer *count_buffer;
2134 uint64_t count_buffer_offset;
2135
2136 /**
2137 * Stream output parameters resource.
2138 */
2139 struct radv_buffer *strmout_buffer;
2140 uint64_t strmout_buffer_offset;
2141 };
2142
2143 static void
2144 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2145 const struct radv_draw_info *draw_info)
2146 {
2147 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2148 struct radv_cmd_state *state = &cmd_buffer->state;
2149 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2150 uint32_t ia_multi_vgt_param;
2151 int32_t primitive_reset_en;
2152
2153 /* Draw state. */
2154 ia_multi_vgt_param =
2155 si_get_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2156 draw_info->indirect,
2157 draw_info->indirect ? 0 : draw_info->count);
2158
2159 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2160 if (info->chip_class >= GFX9) {
2161 radeon_set_uconfig_reg_idx(cs,
2162 R_030960_IA_MULTI_VGT_PARAM,
2163 4, ia_multi_vgt_param);
2164 } else if (info->chip_class >= CIK) {
2165 radeon_set_context_reg_idx(cs,
2166 R_028AA8_IA_MULTI_VGT_PARAM,
2167 1, ia_multi_vgt_param);
2168 } else {
2169 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2170 ia_multi_vgt_param);
2171 }
2172 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2173 }
2174
2175 /* Primitive restart. */
2176 primitive_reset_en =
2177 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2178
2179 if (primitive_reset_en != state->last_primitive_reset_en) {
2180 state->last_primitive_reset_en = primitive_reset_en;
2181 if (info->chip_class >= GFX9) {
2182 radeon_set_uconfig_reg(cs,
2183 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2184 primitive_reset_en);
2185 } else {
2186 radeon_set_context_reg(cs,
2187 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2188 primitive_reset_en);
2189 }
2190 }
2191
2192 if (primitive_reset_en) {
2193 uint32_t primitive_reset_index =
2194 state->index_type ? 0xffffffffu : 0xffffu;
2195
2196 if (primitive_reset_index != state->last_primitive_reset_index) {
2197 radeon_set_context_reg(cs,
2198 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2199 primitive_reset_index);
2200 state->last_primitive_reset_index = primitive_reset_index;
2201 }
2202 }
2203
2204 if (draw_info->strmout_buffer) {
2205 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2206
2207 va += draw_info->strmout_buffer->offset +
2208 draw_info->strmout_buffer_offset;
2209
2210 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2211 draw_info->stride);
2212
2213 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2214 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2215 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2216 COPY_DATA_WR_CONFIRM);
2217 radeon_emit(cs, va);
2218 radeon_emit(cs, va >> 32);
2219 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2220 radeon_emit(cs, 0); /* unused */
2221
2222 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2223 }
2224 }
2225
2226 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2227 VkPipelineStageFlags src_stage_mask)
2228 {
2229 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2230 VK_PIPELINE_STAGE_TRANSFER_BIT |
2231 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2232 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2233 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2234 }
2235
2236 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2237 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2238 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2239 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2240 VK_PIPELINE_STAGE_TRANSFER_BIT |
2241 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2242 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2243 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2244 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2245 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2246 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2247 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2248 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2249 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2250 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2251 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2252 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2253 }
2254 }
2255
2256 static enum radv_cmd_flush_bits
2257 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2258 VkAccessFlags src_flags,
2259 struct radv_image *image)
2260 {
2261 bool flush_CB_meta = true, flush_DB_meta = true;
2262 enum radv_cmd_flush_bits flush_bits = 0;
2263 uint32_t b;
2264
2265 if (image) {
2266 if (!radv_image_has_CB_metadata(image))
2267 flush_CB_meta = false;
2268 if (!radv_image_has_htile(image))
2269 flush_DB_meta = false;
2270 }
2271
2272 for_each_bit(b, src_flags) {
2273 switch ((VkAccessFlagBits)(1 << b)) {
2274 case VK_ACCESS_SHADER_WRITE_BIT:
2275 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2276 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2277 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2278 break;
2279 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2280 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2281 if (flush_CB_meta)
2282 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2283 break;
2284 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2285 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2286 if (flush_DB_meta)
2287 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2288 break;
2289 case VK_ACCESS_TRANSFER_WRITE_BIT:
2290 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2291 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2292 RADV_CMD_FLAG_INV_GLOBAL_L2;
2293
2294 if (flush_CB_meta)
2295 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2296 if (flush_DB_meta)
2297 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2298 break;
2299 default:
2300 break;
2301 }
2302 }
2303 return flush_bits;
2304 }
2305
2306 static enum radv_cmd_flush_bits
2307 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2308 VkAccessFlags dst_flags,
2309 struct radv_image *image)
2310 {
2311 bool flush_CB_meta = true, flush_DB_meta = true;
2312 enum radv_cmd_flush_bits flush_bits = 0;
2313 bool flush_CB = true, flush_DB = true;
2314 bool image_is_coherent = false;
2315 uint32_t b;
2316
2317 if (image) {
2318 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2319 flush_CB = false;
2320 flush_DB = false;
2321 }
2322
2323 if (!radv_image_has_CB_metadata(image))
2324 flush_CB_meta = false;
2325 if (!radv_image_has_htile(image))
2326 flush_DB_meta = false;
2327
2328 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2329 if (image->info.samples == 1 &&
2330 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2331 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2332 !vk_format_is_stencil(image->vk_format)) {
2333 /* Single-sample color and single-sample depth
2334 * (not stencil) are coherent with shaders on
2335 * GFX9.
2336 */
2337 image_is_coherent = true;
2338 }
2339 }
2340 }
2341
2342 for_each_bit(b, dst_flags) {
2343 switch ((VkAccessFlagBits)(1 << b)) {
2344 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2345 case VK_ACCESS_INDEX_READ_BIT:
2346 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2347 break;
2348 case VK_ACCESS_UNIFORM_READ_BIT:
2349 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2350 break;
2351 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2352 case VK_ACCESS_TRANSFER_READ_BIT:
2353 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2354 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2355 RADV_CMD_FLAG_INV_GLOBAL_L2;
2356 break;
2357 case VK_ACCESS_SHADER_READ_BIT:
2358 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2359
2360 if (!image_is_coherent)
2361 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2362 break;
2363 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2364 if (flush_CB)
2365 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2366 if (flush_CB_meta)
2367 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2368 break;
2369 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2370 if (flush_DB)
2371 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2372 if (flush_DB_meta)
2373 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2374 break;
2375 default:
2376 break;
2377 }
2378 }
2379 return flush_bits;
2380 }
2381
2382 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2383 const struct radv_subpass_barrier *barrier)
2384 {
2385 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2386 NULL);
2387 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2388 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2389 NULL);
2390 }
2391
2392 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2393 struct radv_subpass_attachment att)
2394 {
2395 unsigned idx = att.attachment;
2396 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2397 VkImageSubresourceRange range;
2398 range.aspectMask = 0;
2399 range.baseMipLevel = view->base_mip;
2400 range.levelCount = 1;
2401 range.baseArrayLayer = view->base_layer;
2402 range.layerCount = cmd_buffer->state.framebuffer->layers;
2403
2404 if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask) {
2405 /* If the current subpass uses multiview, the driver might have
2406 * performed a fast color/depth clear to the whole image
2407 * (including all layers). To make sure the driver will
2408 * decompress the image correctly (if needed), we have to
2409 * account for the "real" number of layers. If the view mask is
2410 * sparse, this will decompress more layers than needed.
2411 */
2412 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
2413 }
2414
2415 radv_handle_image_transition(cmd_buffer,
2416 view->image,
2417 cmd_buffer->state.attachments[idx].current_layout,
2418 att.layout, 0, 0, &range);
2419
2420 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2421
2422
2423 }
2424
2425 void
2426 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2427 const struct radv_subpass *subpass, bool transitions)
2428 {
2429 if (transitions) {
2430 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2431
2432 for (unsigned i = 0; i < subpass->color_count; ++i) {
2433 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2434 radv_handle_subpass_image_transition(cmd_buffer,
2435 subpass->color_attachments[i]);
2436 }
2437
2438 for (unsigned i = 0; i < subpass->input_count; ++i) {
2439 radv_handle_subpass_image_transition(cmd_buffer,
2440 subpass->input_attachments[i]);
2441 }
2442
2443 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2444 radv_handle_subpass_image_transition(cmd_buffer,
2445 subpass->depth_stencil_attachment);
2446 }
2447 }
2448
2449 cmd_buffer->state.subpass = subpass;
2450
2451 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2452 }
2453
2454 static VkResult
2455 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2456 struct radv_render_pass *pass,
2457 const VkRenderPassBeginInfo *info)
2458 {
2459 struct radv_cmd_state *state = &cmd_buffer->state;
2460
2461 if (pass->attachment_count == 0) {
2462 state->attachments = NULL;
2463 return VK_SUCCESS;
2464 }
2465
2466 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2467 pass->attachment_count *
2468 sizeof(state->attachments[0]),
2469 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2470 if (state->attachments == NULL) {
2471 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2472 return cmd_buffer->record_result;
2473 }
2474
2475 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2476 struct radv_render_pass_attachment *att = &pass->attachments[i];
2477 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2478 VkImageAspectFlags clear_aspects = 0;
2479
2480 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2481 /* color attachment */
2482 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2483 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2484 }
2485 } else {
2486 /* depthstencil attachment */
2487 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2488 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2489 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2490 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2491 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2492 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2493 }
2494 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2495 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2496 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2497 }
2498 }
2499
2500 state->attachments[i].pending_clear_aspects = clear_aspects;
2501 state->attachments[i].cleared_views = 0;
2502 if (clear_aspects && info) {
2503 assert(info->clearValueCount > i);
2504 state->attachments[i].clear_value = info->pClearValues[i];
2505 }
2506
2507 state->attachments[i].current_layout = att->initial_layout;
2508 }
2509
2510 return VK_SUCCESS;
2511 }
2512
2513 VkResult radv_AllocateCommandBuffers(
2514 VkDevice _device,
2515 const VkCommandBufferAllocateInfo *pAllocateInfo,
2516 VkCommandBuffer *pCommandBuffers)
2517 {
2518 RADV_FROM_HANDLE(radv_device, device, _device);
2519 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2520
2521 VkResult result = VK_SUCCESS;
2522 uint32_t i;
2523
2524 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2525
2526 if (!list_empty(&pool->free_cmd_buffers)) {
2527 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2528
2529 list_del(&cmd_buffer->pool_link);
2530 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2531
2532 result = radv_reset_cmd_buffer(cmd_buffer);
2533 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2534 cmd_buffer->level = pAllocateInfo->level;
2535
2536 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2537 } else {
2538 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2539 &pCommandBuffers[i]);
2540 }
2541 if (result != VK_SUCCESS)
2542 break;
2543 }
2544
2545 if (result != VK_SUCCESS) {
2546 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2547 i, pCommandBuffers);
2548
2549 /* From the Vulkan 1.0.66 spec:
2550 *
2551 * "vkAllocateCommandBuffers can be used to create multiple
2552 * command buffers. If the creation of any of those command
2553 * buffers fails, the implementation must destroy all
2554 * successfully created command buffer objects from this
2555 * command, set all entries of the pCommandBuffers array to
2556 * NULL and return the error."
2557 */
2558 memset(pCommandBuffers, 0,
2559 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2560 }
2561
2562 return result;
2563 }
2564
2565 void radv_FreeCommandBuffers(
2566 VkDevice device,
2567 VkCommandPool commandPool,
2568 uint32_t commandBufferCount,
2569 const VkCommandBuffer *pCommandBuffers)
2570 {
2571 for (uint32_t i = 0; i < commandBufferCount; i++) {
2572 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2573
2574 if (cmd_buffer) {
2575 if (cmd_buffer->pool) {
2576 list_del(&cmd_buffer->pool_link);
2577 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2578 } else
2579 radv_cmd_buffer_destroy(cmd_buffer);
2580
2581 }
2582 }
2583 }
2584
2585 VkResult radv_ResetCommandBuffer(
2586 VkCommandBuffer commandBuffer,
2587 VkCommandBufferResetFlags flags)
2588 {
2589 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2590 return radv_reset_cmd_buffer(cmd_buffer);
2591 }
2592
2593 VkResult radv_BeginCommandBuffer(
2594 VkCommandBuffer commandBuffer,
2595 const VkCommandBufferBeginInfo *pBeginInfo)
2596 {
2597 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2598 VkResult result = VK_SUCCESS;
2599
2600 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2601 /* If the command buffer has already been resetted with
2602 * vkResetCommandBuffer, no need to do it again.
2603 */
2604 result = radv_reset_cmd_buffer(cmd_buffer);
2605 if (result != VK_SUCCESS)
2606 return result;
2607 }
2608
2609 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2610 cmd_buffer->state.last_primitive_reset_en = -1;
2611 cmd_buffer->state.last_index_type = -1;
2612 cmd_buffer->state.last_num_instances = -1;
2613 cmd_buffer->state.last_vertex_offset = -1;
2614 cmd_buffer->state.last_first_instance = -1;
2615 cmd_buffer->state.predication_type = -1;
2616 cmd_buffer->usage_flags = pBeginInfo->flags;
2617
2618 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
2619 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
2620 assert(pBeginInfo->pInheritanceInfo);
2621 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2622 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2623
2624 struct radv_subpass *subpass =
2625 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2626
2627 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2628 if (result != VK_SUCCESS)
2629 return result;
2630
2631 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2632 }
2633
2634 if (unlikely(cmd_buffer->device->trace_bo)) {
2635 struct radv_device *device = cmd_buffer->device;
2636
2637 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
2638 device->trace_bo);
2639
2640 radv_cmd_buffer_trace_emit(cmd_buffer);
2641 }
2642
2643 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2644
2645 return result;
2646 }
2647
2648 void radv_CmdBindVertexBuffers(
2649 VkCommandBuffer commandBuffer,
2650 uint32_t firstBinding,
2651 uint32_t bindingCount,
2652 const VkBuffer* pBuffers,
2653 const VkDeviceSize* pOffsets)
2654 {
2655 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2656 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2657 bool changed = false;
2658
2659 /* We have to defer setting up vertex buffer since we need the buffer
2660 * stride from the pipeline. */
2661
2662 assert(firstBinding + bindingCount <= MAX_VBS);
2663 for (uint32_t i = 0; i < bindingCount; i++) {
2664 uint32_t idx = firstBinding + i;
2665
2666 if (!changed &&
2667 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2668 vb[idx].offset != pOffsets[i])) {
2669 changed = true;
2670 }
2671
2672 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2673 vb[idx].offset = pOffsets[i];
2674
2675 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2676 vb[idx].buffer->bo);
2677 }
2678
2679 if (!changed) {
2680 /* No state changes. */
2681 return;
2682 }
2683
2684 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2685 }
2686
2687 void radv_CmdBindIndexBuffer(
2688 VkCommandBuffer commandBuffer,
2689 VkBuffer buffer,
2690 VkDeviceSize offset,
2691 VkIndexType indexType)
2692 {
2693 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2694 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2695
2696 if (cmd_buffer->state.index_buffer == index_buffer &&
2697 cmd_buffer->state.index_offset == offset &&
2698 cmd_buffer->state.index_type == indexType) {
2699 /* No state changes. */
2700 return;
2701 }
2702
2703 cmd_buffer->state.index_buffer = index_buffer;
2704 cmd_buffer->state.index_offset = offset;
2705 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2706 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2707 cmd_buffer->state.index_va += index_buffer->offset + offset;
2708
2709 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2710 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2711 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2712 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
2713 }
2714
2715
2716 static void
2717 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2718 VkPipelineBindPoint bind_point,
2719 struct radv_descriptor_set *set, unsigned idx)
2720 {
2721 struct radeon_winsys *ws = cmd_buffer->device->ws;
2722
2723 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2724
2725 assert(set);
2726 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2727
2728 if (!cmd_buffer->device->use_global_bo_list) {
2729 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2730 if (set->descriptors[j])
2731 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
2732 }
2733
2734 if(set->bo)
2735 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
2736 }
2737
2738 void radv_CmdBindDescriptorSets(
2739 VkCommandBuffer commandBuffer,
2740 VkPipelineBindPoint pipelineBindPoint,
2741 VkPipelineLayout _layout,
2742 uint32_t firstSet,
2743 uint32_t descriptorSetCount,
2744 const VkDescriptorSet* pDescriptorSets,
2745 uint32_t dynamicOffsetCount,
2746 const uint32_t* pDynamicOffsets)
2747 {
2748 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2749 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2750 unsigned dyn_idx = 0;
2751
2752 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2753 struct radv_descriptor_state *descriptors_state =
2754 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2755
2756 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2757 unsigned idx = i + firstSet;
2758 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2759 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2760
2761 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2762 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2763 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
2764 assert(dyn_idx < dynamicOffsetCount);
2765
2766 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2767 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2768 dst[0] = va;
2769 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2770 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2771 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2772 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2773 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2774 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2775 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2776 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2777 cmd_buffer->push_constant_stages |=
2778 set->layout->dynamic_shader_stages;
2779 }
2780 }
2781 }
2782
2783 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2784 struct radv_descriptor_set *set,
2785 struct radv_descriptor_set_layout *layout,
2786 VkPipelineBindPoint bind_point)
2787 {
2788 struct radv_descriptor_state *descriptors_state =
2789 radv_get_descriptors_state(cmd_buffer, bind_point);
2790 set->size = layout->size;
2791 set->layout = layout;
2792
2793 if (descriptors_state->push_set.capacity < set->size) {
2794 size_t new_size = MAX2(set->size, 1024);
2795 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2796 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2797
2798 free(set->mapped_ptr);
2799 set->mapped_ptr = malloc(new_size);
2800
2801 if (!set->mapped_ptr) {
2802 descriptors_state->push_set.capacity = 0;
2803 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2804 return false;
2805 }
2806
2807 descriptors_state->push_set.capacity = new_size;
2808 }
2809
2810 return true;
2811 }
2812
2813 void radv_meta_push_descriptor_set(
2814 struct radv_cmd_buffer* cmd_buffer,
2815 VkPipelineBindPoint pipelineBindPoint,
2816 VkPipelineLayout _layout,
2817 uint32_t set,
2818 uint32_t descriptorWriteCount,
2819 const VkWriteDescriptorSet* pDescriptorWrites)
2820 {
2821 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2822 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2823 unsigned bo_offset;
2824
2825 assert(set == 0);
2826 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2827
2828 push_set->size = layout->set[set].layout->size;
2829 push_set->layout = layout->set[set].layout;
2830
2831 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2832 &bo_offset,
2833 (void**) &push_set->mapped_ptr))
2834 return;
2835
2836 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2837 push_set->va += bo_offset;
2838
2839 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2840 radv_descriptor_set_to_handle(push_set),
2841 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2842
2843 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2844 }
2845
2846 void radv_CmdPushDescriptorSetKHR(
2847 VkCommandBuffer commandBuffer,
2848 VkPipelineBindPoint pipelineBindPoint,
2849 VkPipelineLayout _layout,
2850 uint32_t set,
2851 uint32_t descriptorWriteCount,
2852 const VkWriteDescriptorSet* pDescriptorWrites)
2853 {
2854 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2855 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2856 struct radv_descriptor_state *descriptors_state =
2857 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2858 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2859
2860 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2861
2862 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2863 layout->set[set].layout,
2864 pipelineBindPoint))
2865 return;
2866
2867 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2868 radv_descriptor_set_to_handle(push_set),
2869 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2870
2871 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2872 descriptors_state->push_dirty = true;
2873 }
2874
2875 void radv_CmdPushDescriptorSetWithTemplateKHR(
2876 VkCommandBuffer commandBuffer,
2877 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
2878 VkPipelineLayout _layout,
2879 uint32_t set,
2880 const void* pData)
2881 {
2882 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2883 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2884 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2885 struct radv_descriptor_state *descriptors_state =
2886 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2887 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2888
2889 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2890
2891 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2892 layout->set[set].layout,
2893 templ->bind_point))
2894 return;
2895
2896 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2897 descriptorUpdateTemplate, pData);
2898
2899 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2900 descriptors_state->push_dirty = true;
2901 }
2902
2903 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2904 VkPipelineLayout layout,
2905 VkShaderStageFlags stageFlags,
2906 uint32_t offset,
2907 uint32_t size,
2908 const void* pValues)
2909 {
2910 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2911 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2912 cmd_buffer->push_constant_stages |= stageFlags;
2913 }
2914
2915 VkResult radv_EndCommandBuffer(
2916 VkCommandBuffer commandBuffer)
2917 {
2918 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2919
2920 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2921 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2922 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2923 si_emit_cache_flush(cmd_buffer);
2924 }
2925
2926 /* Make sure CP DMA is idle at the end of IBs because the kernel
2927 * doesn't wait for it.
2928 */
2929 si_cp_dma_wait_for_idle(cmd_buffer);
2930
2931 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2932
2933 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2934 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2935
2936 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2937
2938 return cmd_buffer->record_result;
2939 }
2940
2941 static void
2942 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2943 {
2944 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2945
2946 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2947 return;
2948
2949 assert(!pipeline->ctx_cs.cdw);
2950
2951 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2952
2953 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2954 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2955
2956 cmd_buffer->compute_scratch_size_needed =
2957 MAX2(cmd_buffer->compute_scratch_size_needed,
2958 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2959
2960 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2961 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
2962
2963 if (unlikely(cmd_buffer->device->trace_bo))
2964 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2965 }
2966
2967 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2968 VkPipelineBindPoint bind_point)
2969 {
2970 struct radv_descriptor_state *descriptors_state =
2971 radv_get_descriptors_state(cmd_buffer, bind_point);
2972
2973 descriptors_state->dirty |= descriptors_state->valid;
2974 }
2975
2976 void radv_CmdBindPipeline(
2977 VkCommandBuffer commandBuffer,
2978 VkPipelineBindPoint pipelineBindPoint,
2979 VkPipeline _pipeline)
2980 {
2981 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2982 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2983
2984 switch (pipelineBindPoint) {
2985 case VK_PIPELINE_BIND_POINT_COMPUTE:
2986 if (cmd_buffer->state.compute_pipeline == pipeline)
2987 return;
2988 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2989
2990 cmd_buffer->state.compute_pipeline = pipeline;
2991 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2992 break;
2993 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2994 if (cmd_buffer->state.pipeline == pipeline)
2995 return;
2996 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2997
2998 cmd_buffer->state.pipeline = pipeline;
2999 if (!pipeline)
3000 break;
3001
3002 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3003 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3004
3005 /* the new vertex shader might not have the same user regs */
3006 cmd_buffer->state.last_first_instance = -1;
3007 cmd_buffer->state.last_vertex_offset = -1;
3008
3009 /* Prefetch all pipeline shaders at first draw time. */
3010 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3011
3012 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3013 radv_bind_streamout_state(cmd_buffer, pipeline);
3014
3015 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3016 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3017 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3018 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3019
3020 if (radv_pipeline_has_tess(pipeline))
3021 cmd_buffer->tess_rings_needed = true;
3022 break;
3023 default:
3024 assert(!"invalid bind point");
3025 break;
3026 }
3027 }
3028
3029 void radv_CmdSetViewport(
3030 VkCommandBuffer commandBuffer,
3031 uint32_t firstViewport,
3032 uint32_t viewportCount,
3033 const VkViewport* pViewports)
3034 {
3035 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3036 struct radv_cmd_state *state = &cmd_buffer->state;
3037 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
3038
3039 assert(firstViewport < MAX_VIEWPORTS);
3040 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3041
3042 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3043 pViewports, viewportCount * sizeof(*pViewports))) {
3044 return;
3045 }
3046
3047 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3048 viewportCount * sizeof(*pViewports));
3049
3050 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3051 }
3052
3053 void radv_CmdSetScissor(
3054 VkCommandBuffer commandBuffer,
3055 uint32_t firstScissor,
3056 uint32_t scissorCount,
3057 const VkRect2D* pScissors)
3058 {
3059 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3060 struct radv_cmd_state *state = &cmd_buffer->state;
3061 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
3062
3063 assert(firstScissor < MAX_SCISSORS);
3064 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3065
3066 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3067 scissorCount * sizeof(*pScissors))) {
3068 return;
3069 }
3070
3071 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3072 scissorCount * sizeof(*pScissors));
3073
3074 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3075 }
3076
3077 void radv_CmdSetLineWidth(
3078 VkCommandBuffer commandBuffer,
3079 float lineWidth)
3080 {
3081 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3082
3083 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3084 return;
3085
3086 cmd_buffer->state.dynamic.line_width = lineWidth;
3087 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3088 }
3089
3090 void radv_CmdSetDepthBias(
3091 VkCommandBuffer commandBuffer,
3092 float depthBiasConstantFactor,
3093 float depthBiasClamp,
3094 float depthBiasSlopeFactor)
3095 {
3096 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3097 struct radv_cmd_state *state = &cmd_buffer->state;
3098
3099 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3100 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3101 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3102 return;
3103 }
3104
3105 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3106 state->dynamic.depth_bias.clamp = depthBiasClamp;
3107 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3108
3109 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3110 }
3111
3112 void radv_CmdSetBlendConstants(
3113 VkCommandBuffer commandBuffer,
3114 const float blendConstants[4])
3115 {
3116 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3117 struct radv_cmd_state *state = &cmd_buffer->state;
3118
3119 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3120 return;
3121
3122 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
3123
3124 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3125 }
3126
3127 void radv_CmdSetDepthBounds(
3128 VkCommandBuffer commandBuffer,
3129 float minDepthBounds,
3130 float maxDepthBounds)
3131 {
3132 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3133 struct radv_cmd_state *state = &cmd_buffer->state;
3134
3135 if (state->dynamic.depth_bounds.min == minDepthBounds &&
3136 state->dynamic.depth_bounds.max == maxDepthBounds) {
3137 return;
3138 }
3139
3140 state->dynamic.depth_bounds.min = minDepthBounds;
3141 state->dynamic.depth_bounds.max = maxDepthBounds;
3142
3143 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
3144 }
3145
3146 void radv_CmdSetStencilCompareMask(
3147 VkCommandBuffer commandBuffer,
3148 VkStencilFaceFlags faceMask,
3149 uint32_t compareMask)
3150 {
3151 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3152 struct radv_cmd_state *state = &cmd_buffer->state;
3153 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
3154 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
3155
3156 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3157 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3158 return;
3159 }
3160
3161 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3162 state->dynamic.stencil_compare_mask.front = compareMask;
3163 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3164 state->dynamic.stencil_compare_mask.back = compareMask;
3165
3166 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
3167 }
3168
3169 void radv_CmdSetStencilWriteMask(
3170 VkCommandBuffer commandBuffer,
3171 VkStencilFaceFlags faceMask,
3172 uint32_t writeMask)
3173 {
3174 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3175 struct radv_cmd_state *state = &cmd_buffer->state;
3176 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
3177 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
3178
3179 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3180 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3181 return;
3182 }
3183
3184 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3185 state->dynamic.stencil_write_mask.front = writeMask;
3186 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3187 state->dynamic.stencil_write_mask.back = writeMask;
3188
3189 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
3190 }
3191
3192 void radv_CmdSetStencilReference(
3193 VkCommandBuffer commandBuffer,
3194 VkStencilFaceFlags faceMask,
3195 uint32_t reference)
3196 {
3197 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3198 struct radv_cmd_state *state = &cmd_buffer->state;
3199 bool front_same = state->dynamic.stencil_reference.front == reference;
3200 bool back_same = state->dynamic.stencil_reference.back == reference;
3201
3202 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3203 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3204 return;
3205 }
3206
3207 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3208 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3209 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3210 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3211
3212 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3213 }
3214
3215 void radv_CmdSetDiscardRectangleEXT(
3216 VkCommandBuffer commandBuffer,
3217 uint32_t firstDiscardRectangle,
3218 uint32_t discardRectangleCount,
3219 const VkRect2D* pDiscardRectangles)
3220 {
3221 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3222 struct radv_cmd_state *state = &cmd_buffer->state;
3223 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3224
3225 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3226 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3227
3228 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
3229 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
3230 return;
3231 }
3232
3233 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3234 pDiscardRectangles, discardRectangleCount);
3235
3236 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3237 }
3238
3239 void radv_CmdExecuteCommands(
3240 VkCommandBuffer commandBuffer,
3241 uint32_t commandBufferCount,
3242 const VkCommandBuffer* pCmdBuffers)
3243 {
3244 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3245
3246 assert(commandBufferCount > 0);
3247
3248 /* Emit pending flushes on primary prior to executing secondary */
3249 si_emit_cache_flush(primary);
3250
3251 for (uint32_t i = 0; i < commandBufferCount; i++) {
3252 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3253
3254 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3255 secondary->scratch_size_needed);
3256 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3257 secondary->compute_scratch_size_needed);
3258
3259 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
3260 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
3261 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
3262 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
3263 if (secondary->tess_rings_needed)
3264 primary->tess_rings_needed = true;
3265 if (secondary->sample_positions_needed)
3266 primary->sample_positions_needed = true;
3267
3268 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
3269
3270
3271 /* When the secondary command buffer is compute only we don't
3272 * need to re-emit the current graphics pipeline.
3273 */
3274 if (secondary->state.emitted_pipeline) {
3275 primary->state.emitted_pipeline =
3276 secondary->state.emitted_pipeline;
3277 }
3278
3279 /* When the secondary command buffer is graphics only we don't
3280 * need to re-emit the current compute pipeline.
3281 */
3282 if (secondary->state.emitted_compute_pipeline) {
3283 primary->state.emitted_compute_pipeline =
3284 secondary->state.emitted_compute_pipeline;
3285 }
3286
3287 /* Only re-emit the draw packets when needed. */
3288 if (secondary->state.last_primitive_reset_en != -1) {
3289 primary->state.last_primitive_reset_en =
3290 secondary->state.last_primitive_reset_en;
3291 }
3292
3293 if (secondary->state.last_primitive_reset_index) {
3294 primary->state.last_primitive_reset_index =
3295 secondary->state.last_primitive_reset_index;
3296 }
3297
3298 if (secondary->state.last_ia_multi_vgt_param) {
3299 primary->state.last_ia_multi_vgt_param =
3300 secondary->state.last_ia_multi_vgt_param;
3301 }
3302
3303 primary->state.last_first_instance = secondary->state.last_first_instance;
3304 primary->state.last_num_instances = secondary->state.last_num_instances;
3305 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
3306
3307 if (secondary->state.last_index_type != -1) {
3308 primary->state.last_index_type =
3309 secondary->state.last_index_type;
3310 }
3311 }
3312
3313 /* After executing commands from secondary buffers we have to dirty
3314 * some states.
3315 */
3316 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
3317 RADV_CMD_DIRTY_INDEX_BUFFER |
3318 RADV_CMD_DIRTY_DYNAMIC_ALL;
3319 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
3320 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
3321 }
3322
3323 VkResult radv_CreateCommandPool(
3324 VkDevice _device,
3325 const VkCommandPoolCreateInfo* pCreateInfo,
3326 const VkAllocationCallbacks* pAllocator,
3327 VkCommandPool* pCmdPool)
3328 {
3329 RADV_FROM_HANDLE(radv_device, device, _device);
3330 struct radv_cmd_pool *pool;
3331
3332 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3333 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3334 if (pool == NULL)
3335 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3336
3337 if (pAllocator)
3338 pool->alloc = *pAllocator;
3339 else
3340 pool->alloc = device->alloc;
3341
3342 list_inithead(&pool->cmd_buffers);
3343 list_inithead(&pool->free_cmd_buffers);
3344
3345 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3346
3347 *pCmdPool = radv_cmd_pool_to_handle(pool);
3348
3349 return VK_SUCCESS;
3350
3351 }
3352
3353 void radv_DestroyCommandPool(
3354 VkDevice _device,
3355 VkCommandPool commandPool,
3356 const VkAllocationCallbacks* pAllocator)
3357 {
3358 RADV_FROM_HANDLE(radv_device, device, _device);
3359 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3360
3361 if (!pool)
3362 return;
3363
3364 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3365 &pool->cmd_buffers, pool_link) {
3366 radv_cmd_buffer_destroy(cmd_buffer);
3367 }
3368
3369 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3370 &pool->free_cmd_buffers, pool_link) {
3371 radv_cmd_buffer_destroy(cmd_buffer);
3372 }
3373
3374 vk_free2(&device->alloc, pAllocator, pool);
3375 }
3376
3377 VkResult radv_ResetCommandPool(
3378 VkDevice device,
3379 VkCommandPool commandPool,
3380 VkCommandPoolResetFlags flags)
3381 {
3382 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3383 VkResult result;
3384
3385 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3386 &pool->cmd_buffers, pool_link) {
3387 result = radv_reset_cmd_buffer(cmd_buffer);
3388 if (result != VK_SUCCESS)
3389 return result;
3390 }
3391
3392 return VK_SUCCESS;
3393 }
3394
3395 void radv_TrimCommandPool(
3396 VkDevice device,
3397 VkCommandPool commandPool,
3398 VkCommandPoolTrimFlags flags)
3399 {
3400 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3401
3402 if (!pool)
3403 return;
3404
3405 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3406 &pool->free_cmd_buffers, pool_link) {
3407 radv_cmd_buffer_destroy(cmd_buffer);
3408 }
3409 }
3410
3411 void radv_CmdBeginRenderPass(
3412 VkCommandBuffer commandBuffer,
3413 const VkRenderPassBeginInfo* pRenderPassBegin,
3414 VkSubpassContents contents)
3415 {
3416 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3417 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3418 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3419
3420 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3421 cmd_buffer->cs, 2048);
3422 MAYBE_UNUSED VkResult result;
3423
3424 cmd_buffer->state.framebuffer = framebuffer;
3425 cmd_buffer->state.pass = pass;
3426 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3427
3428 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3429 if (result != VK_SUCCESS)
3430 return;
3431
3432 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
3433 assert(cmd_buffer->cs->cdw <= cdw_max);
3434
3435 radv_cmd_buffer_clear_subpass(cmd_buffer);
3436 }
3437
3438 void radv_CmdBeginRenderPass2KHR(
3439 VkCommandBuffer commandBuffer,
3440 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
3441 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
3442 {
3443 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
3444 pSubpassBeginInfo->contents);
3445 }
3446
3447 void radv_CmdNextSubpass(
3448 VkCommandBuffer commandBuffer,
3449 VkSubpassContents contents)
3450 {
3451 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3452
3453 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3454
3455 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
3456 2048);
3457
3458 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
3459 radv_cmd_buffer_clear_subpass(cmd_buffer);
3460 }
3461
3462 void radv_CmdNextSubpass2KHR(
3463 VkCommandBuffer commandBuffer,
3464 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
3465 const VkSubpassEndInfoKHR* pSubpassEndInfo)
3466 {
3467 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
3468 }
3469
3470 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3471 {
3472 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3473 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3474 if (!radv_get_shader(pipeline, stage))
3475 continue;
3476
3477 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3478 if (loc->sgpr_idx == -1)
3479 continue;
3480 uint32_t base_reg = pipeline->user_data_0[stage];
3481 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3482
3483 }
3484 if (pipeline->gs_copy_shader) {
3485 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3486 if (loc->sgpr_idx != -1) {
3487 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3488 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3489 }
3490 }
3491 }
3492
3493 static void
3494 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3495 uint32_t vertex_count,
3496 bool use_opaque)
3497 {
3498 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3499 radeon_emit(cmd_buffer->cs, vertex_count);
3500 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3501 S_0287F0_USE_OPAQUE(use_opaque));
3502 }
3503
3504 static void
3505 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3506 uint64_t index_va,
3507 uint32_t index_count)
3508 {
3509 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
3510 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3511 radeon_emit(cmd_buffer->cs, index_va);
3512 radeon_emit(cmd_buffer->cs, index_va >> 32);
3513 radeon_emit(cmd_buffer->cs, index_count);
3514 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3515 }
3516
3517 static void
3518 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3519 bool indexed,
3520 uint32_t draw_count,
3521 uint64_t count_va,
3522 uint32_t stride)
3523 {
3524 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3525 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3526 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3527 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
3528 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3529 bool predicating = cmd_buffer->state.predicating;
3530 assert(base_reg);
3531
3532 /* just reset draw state for vertex data */
3533 cmd_buffer->state.last_first_instance = -1;
3534 cmd_buffer->state.last_num_instances = -1;
3535 cmd_buffer->state.last_vertex_offset = -1;
3536
3537 if (draw_count == 1 && !count_va && !draw_id_enable) {
3538 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3539 PKT3_DRAW_INDIRECT, 3, predicating));
3540 radeon_emit(cs, 0);
3541 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3542 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3543 radeon_emit(cs, di_src_sel);
3544 } else {
3545 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3546 PKT3_DRAW_INDIRECT_MULTI,
3547 8, predicating));
3548 radeon_emit(cs, 0);
3549 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3550 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3551 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3552 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3553 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3554 radeon_emit(cs, draw_count); /* count */
3555 radeon_emit(cs, count_va); /* count_addr */
3556 radeon_emit(cs, count_va >> 32);
3557 radeon_emit(cs, stride); /* stride */
3558 radeon_emit(cs, di_src_sel);
3559 }
3560 }
3561
3562 static void
3563 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3564 const struct radv_draw_info *info)
3565 {
3566 struct radv_cmd_state *state = &cmd_buffer->state;
3567 struct radeon_winsys *ws = cmd_buffer->device->ws;
3568 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3569
3570 if (info->indirect) {
3571 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3572 uint64_t count_va = 0;
3573
3574 va += info->indirect->offset + info->indirect_offset;
3575
3576 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3577
3578 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3579 radeon_emit(cs, 1);
3580 radeon_emit(cs, va);
3581 radeon_emit(cs, va >> 32);
3582
3583 if (info->count_buffer) {
3584 count_va = radv_buffer_get_va(info->count_buffer->bo);
3585 count_va += info->count_buffer->offset +
3586 info->count_buffer_offset;
3587
3588 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
3589 }
3590
3591 if (!state->subpass->view_mask) {
3592 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3593 info->indexed,
3594 info->count,
3595 count_va,
3596 info->stride);
3597 } else {
3598 unsigned i;
3599 for_each_bit(i, state->subpass->view_mask) {
3600 radv_emit_view_index(cmd_buffer, i);
3601
3602 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3603 info->indexed,
3604 info->count,
3605 count_va,
3606 info->stride);
3607 }
3608 }
3609 } else {
3610 assert(state->pipeline->graphics.vtx_base_sgpr);
3611
3612 if (info->vertex_offset != state->last_vertex_offset ||
3613 info->first_instance != state->last_first_instance) {
3614 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3615 state->pipeline->graphics.vtx_emit_num);
3616
3617 radeon_emit(cs, info->vertex_offset);
3618 radeon_emit(cs, info->first_instance);
3619 if (state->pipeline->graphics.vtx_emit_num == 3)
3620 radeon_emit(cs, 0);
3621 state->last_first_instance = info->first_instance;
3622 state->last_vertex_offset = info->vertex_offset;
3623 }
3624
3625 if (state->last_num_instances != info->instance_count) {
3626 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3627 radeon_emit(cs, info->instance_count);
3628 state->last_num_instances = info->instance_count;
3629 }
3630
3631 if (info->indexed) {
3632 int index_size = state->index_type ? 4 : 2;
3633 uint64_t index_va;
3634
3635 index_va = state->index_va;
3636 index_va += info->first_index * index_size;
3637
3638 if (!state->subpass->view_mask) {
3639 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3640 index_va,
3641 info->count);
3642 } else {
3643 unsigned i;
3644 for_each_bit(i, state->subpass->view_mask) {
3645 radv_emit_view_index(cmd_buffer, i);
3646
3647 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3648 index_va,
3649 info->count);
3650 }
3651 }
3652 } else {
3653 if (!state->subpass->view_mask) {
3654 radv_cs_emit_draw_packet(cmd_buffer,
3655 info->count,
3656 !!info->strmout_buffer);
3657 } else {
3658 unsigned i;
3659 for_each_bit(i, state->subpass->view_mask) {
3660 radv_emit_view_index(cmd_buffer, i);
3661
3662 radv_cs_emit_draw_packet(cmd_buffer,
3663 info->count,
3664 !!info->strmout_buffer);
3665 }
3666 }
3667 }
3668 }
3669 }
3670
3671 /*
3672 * Vega and raven have a bug which triggers if there are multiple context
3673 * register contexts active at the same time with different scissor values.
3674 *
3675 * There are two possible workarounds:
3676 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3677 * there is only ever 1 active set of scissor values at the same time.
3678 *
3679 * 2) Whenever the hardware switches contexts we have to set the scissor
3680 * registers again even if it is a noop. That way the new context gets
3681 * the correct scissor values.
3682 *
3683 * This implements option 2. radv_need_late_scissor_emission needs to
3684 * return true on affected HW if radv_emit_all_graphics_states sets
3685 * any context registers.
3686 */
3687 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
3688 const struct radv_draw_info *info)
3689 {
3690 struct radv_cmd_state *state = &cmd_buffer->state;
3691
3692 if (!cmd_buffer->device->physical_device->has_scissor_bug)
3693 return false;
3694
3695 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
3696 return true;
3697
3698 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
3699
3700 /* Index, vertex and streamout buffers don't change context regs, and
3701 * pipeline is already handled.
3702 */
3703 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
3704 RADV_CMD_DIRTY_VERTEX_BUFFER |
3705 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
3706 RADV_CMD_DIRTY_PIPELINE);
3707
3708 if (cmd_buffer->state.dirty & used_states)
3709 return true;
3710
3711 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
3712 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
3713 return true;
3714
3715 return false;
3716 }
3717
3718 static void
3719 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3720 const struct radv_draw_info *info)
3721 {
3722 bool late_scissor_emission;
3723
3724 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3725 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3726 radv_emit_rbplus_state(cmd_buffer);
3727
3728 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3729 radv_emit_graphics_pipeline(cmd_buffer);
3730
3731 /* This should be before the cmd_buffer->state.dirty is cleared
3732 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
3733 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
3734 late_scissor_emission =
3735 radv_need_late_scissor_emission(cmd_buffer, info);
3736
3737 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3738 radv_emit_framebuffer_state(cmd_buffer);
3739
3740 if (info->indexed) {
3741 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3742 radv_emit_index_buffer(cmd_buffer);
3743 } else {
3744 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3745 * so the state must be re-emitted before the next indexed
3746 * draw.
3747 */
3748 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3749 cmd_buffer->state.last_index_type = -1;
3750 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3751 }
3752 }
3753
3754 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3755
3756 radv_emit_draw_registers(cmd_buffer, info);
3757
3758 if (late_scissor_emission)
3759 radv_emit_scissor(cmd_buffer);
3760 }
3761
3762 static void
3763 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3764 const struct radv_draw_info *info)
3765 {
3766 struct radeon_info *rad_info =
3767 &cmd_buffer->device->physical_device->rad_info;
3768 bool has_prefetch =
3769 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3770 bool pipeline_is_dirty =
3771 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3772 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3773
3774 MAYBE_UNUSED unsigned cdw_max =
3775 radeon_check_space(cmd_buffer->device->ws,
3776 cmd_buffer->cs, 4096);
3777
3778 if (likely(!info->indirect)) {
3779 /* SI-CI treat instance_count==0 as instance_count==1. There is
3780 * no workaround for indirect draws, but we can at least skip
3781 * direct draws.
3782 */
3783 if (unlikely(!info->instance_count))
3784 return;
3785
3786 /* Handle count == 0. */
3787 if (unlikely(!info->count && !info->strmout_buffer))
3788 return;
3789 }
3790
3791 /* Use optimal packet order based on whether we need to sync the
3792 * pipeline.
3793 */
3794 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3795 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3796 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3797 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3798 /* If we have to wait for idle, set all states first, so that
3799 * all SET packets are processed in parallel with previous draw
3800 * calls. Then upload descriptors, set shader pointers, and
3801 * draw, and prefetch at the end. This ensures that the time
3802 * the CUs are idle is very short. (there are only SET_SH
3803 * packets between the wait and the draw)
3804 */
3805 radv_emit_all_graphics_states(cmd_buffer, info);
3806 si_emit_cache_flush(cmd_buffer);
3807 /* <-- CUs are idle here --> */
3808
3809 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3810
3811 radv_emit_draw_packets(cmd_buffer, info);
3812 /* <-- CUs are busy here --> */
3813
3814 /* Start prefetches after the draw has been started. Both will
3815 * run in parallel, but starting the draw first is more
3816 * important.
3817 */
3818 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3819 radv_emit_prefetch_L2(cmd_buffer,
3820 cmd_buffer->state.pipeline, false);
3821 }
3822 } else {
3823 /* If we don't wait for idle, start prefetches first, then set
3824 * states, and draw at the end.
3825 */
3826 si_emit_cache_flush(cmd_buffer);
3827
3828 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3829 /* Only prefetch the vertex shader and VBO descriptors
3830 * in order to start the draw as soon as possible.
3831 */
3832 radv_emit_prefetch_L2(cmd_buffer,
3833 cmd_buffer->state.pipeline, true);
3834 }
3835
3836 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3837
3838 radv_emit_all_graphics_states(cmd_buffer, info);
3839 radv_emit_draw_packets(cmd_buffer, info);
3840
3841 /* Prefetch the remaining shaders after the draw has been
3842 * started.
3843 */
3844 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3845 radv_emit_prefetch_L2(cmd_buffer,
3846 cmd_buffer->state.pipeline, false);
3847 }
3848 }
3849
3850 /* Workaround for a VGT hang when streamout is enabled.
3851 * It must be done after drawing.
3852 */
3853 if (cmd_buffer->state.streamout.streamout_enabled &&
3854 (rad_info->family == CHIP_HAWAII ||
3855 rad_info->family == CHIP_TONGA ||
3856 rad_info->family == CHIP_FIJI)) {
3857 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
3858 }
3859
3860 assert(cmd_buffer->cs->cdw <= cdw_max);
3861 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3862 }
3863
3864 void radv_CmdDraw(
3865 VkCommandBuffer commandBuffer,
3866 uint32_t vertexCount,
3867 uint32_t instanceCount,
3868 uint32_t firstVertex,
3869 uint32_t firstInstance)
3870 {
3871 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3872 struct radv_draw_info info = {};
3873
3874 info.count = vertexCount;
3875 info.instance_count = instanceCount;
3876 info.first_instance = firstInstance;
3877 info.vertex_offset = firstVertex;
3878
3879 radv_draw(cmd_buffer, &info);
3880 }
3881
3882 void radv_CmdDrawIndexed(
3883 VkCommandBuffer commandBuffer,
3884 uint32_t indexCount,
3885 uint32_t instanceCount,
3886 uint32_t firstIndex,
3887 int32_t vertexOffset,
3888 uint32_t firstInstance)
3889 {
3890 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3891 struct radv_draw_info info = {};
3892
3893 info.indexed = true;
3894 info.count = indexCount;
3895 info.instance_count = instanceCount;
3896 info.first_index = firstIndex;
3897 info.vertex_offset = vertexOffset;
3898 info.first_instance = firstInstance;
3899
3900 radv_draw(cmd_buffer, &info);
3901 }
3902
3903 void radv_CmdDrawIndirect(
3904 VkCommandBuffer commandBuffer,
3905 VkBuffer _buffer,
3906 VkDeviceSize offset,
3907 uint32_t drawCount,
3908 uint32_t stride)
3909 {
3910 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3911 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3912 struct radv_draw_info info = {};
3913
3914 info.count = drawCount;
3915 info.indirect = buffer;
3916 info.indirect_offset = offset;
3917 info.stride = stride;
3918
3919 radv_draw(cmd_buffer, &info);
3920 }
3921
3922 void radv_CmdDrawIndexedIndirect(
3923 VkCommandBuffer commandBuffer,
3924 VkBuffer _buffer,
3925 VkDeviceSize offset,
3926 uint32_t drawCount,
3927 uint32_t stride)
3928 {
3929 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3930 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3931 struct radv_draw_info info = {};
3932
3933 info.indexed = true;
3934 info.count = drawCount;
3935 info.indirect = buffer;
3936 info.indirect_offset = offset;
3937 info.stride = stride;
3938
3939 radv_draw(cmd_buffer, &info);
3940 }
3941
3942 void radv_CmdDrawIndirectCountAMD(
3943 VkCommandBuffer commandBuffer,
3944 VkBuffer _buffer,
3945 VkDeviceSize offset,
3946 VkBuffer _countBuffer,
3947 VkDeviceSize countBufferOffset,
3948 uint32_t maxDrawCount,
3949 uint32_t stride)
3950 {
3951 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3952 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3953 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3954 struct radv_draw_info info = {};
3955
3956 info.count = maxDrawCount;
3957 info.indirect = buffer;
3958 info.indirect_offset = offset;
3959 info.count_buffer = count_buffer;
3960 info.count_buffer_offset = countBufferOffset;
3961 info.stride = stride;
3962
3963 radv_draw(cmd_buffer, &info);
3964 }
3965
3966 void radv_CmdDrawIndexedIndirectCountAMD(
3967 VkCommandBuffer commandBuffer,
3968 VkBuffer _buffer,
3969 VkDeviceSize offset,
3970 VkBuffer _countBuffer,
3971 VkDeviceSize countBufferOffset,
3972 uint32_t maxDrawCount,
3973 uint32_t stride)
3974 {
3975 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3976 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3977 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3978 struct radv_draw_info info = {};
3979
3980 info.indexed = true;
3981 info.count = maxDrawCount;
3982 info.indirect = buffer;
3983 info.indirect_offset = offset;
3984 info.count_buffer = count_buffer;
3985 info.count_buffer_offset = countBufferOffset;
3986 info.stride = stride;
3987
3988 radv_draw(cmd_buffer, &info);
3989 }
3990
3991 void radv_CmdDrawIndirectCountKHR(
3992 VkCommandBuffer commandBuffer,
3993 VkBuffer _buffer,
3994 VkDeviceSize offset,
3995 VkBuffer _countBuffer,
3996 VkDeviceSize countBufferOffset,
3997 uint32_t maxDrawCount,
3998 uint32_t stride)
3999 {
4000 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4001 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4002 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4003 struct radv_draw_info info = {};
4004
4005 info.count = maxDrawCount;
4006 info.indirect = buffer;
4007 info.indirect_offset = offset;
4008 info.count_buffer = count_buffer;
4009 info.count_buffer_offset = countBufferOffset;
4010 info.stride = stride;
4011
4012 radv_draw(cmd_buffer, &info);
4013 }
4014
4015 void radv_CmdDrawIndexedIndirectCountKHR(
4016 VkCommandBuffer commandBuffer,
4017 VkBuffer _buffer,
4018 VkDeviceSize offset,
4019 VkBuffer _countBuffer,
4020 VkDeviceSize countBufferOffset,
4021 uint32_t maxDrawCount,
4022 uint32_t stride)
4023 {
4024 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4025 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4026 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4027 struct radv_draw_info info = {};
4028
4029 info.indexed = true;
4030 info.count = maxDrawCount;
4031 info.indirect = buffer;
4032 info.indirect_offset = offset;
4033 info.count_buffer = count_buffer;
4034 info.count_buffer_offset = countBufferOffset;
4035 info.stride = stride;
4036
4037 radv_draw(cmd_buffer, &info);
4038 }
4039
4040 struct radv_dispatch_info {
4041 /**
4042 * Determine the layout of the grid (in block units) to be used.
4043 */
4044 uint32_t blocks[3];
4045
4046 /**
4047 * A starting offset for the grid. If unaligned is set, the offset
4048 * must still be aligned.
4049 */
4050 uint32_t offsets[3];
4051 /**
4052 * Whether it's an unaligned compute dispatch.
4053 */
4054 bool unaligned;
4055
4056 /**
4057 * Indirect compute parameters resource.
4058 */
4059 struct radv_buffer *indirect;
4060 uint64_t indirect_offset;
4061 };
4062
4063 static void
4064 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
4065 const struct radv_dispatch_info *info)
4066 {
4067 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4068 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4069 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
4070 struct radeon_winsys *ws = cmd_buffer->device->ws;
4071 bool predicating = cmd_buffer->state.predicating;
4072 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4073 struct radv_userdata_info *loc;
4074
4075 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
4076 AC_UD_CS_GRID_SIZE);
4077
4078 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
4079
4080 if (info->indirect) {
4081 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4082
4083 va += info->indirect->offset + info->indirect_offset;
4084
4085 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4086
4087 if (loc->sgpr_idx != -1) {
4088 for (unsigned i = 0; i < 3; ++i) {
4089 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4090 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4091 COPY_DATA_DST_SEL(COPY_DATA_REG));
4092 radeon_emit(cs, (va + 4 * i));
4093 radeon_emit(cs, (va + 4 * i) >> 32);
4094 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
4095 + loc->sgpr_idx * 4) >> 2) + i);
4096 radeon_emit(cs, 0);
4097 }
4098 }
4099
4100 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
4101 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
4102 PKT3_SHADER_TYPE_S(1));
4103 radeon_emit(cs, va);
4104 radeon_emit(cs, va >> 32);
4105 radeon_emit(cs, dispatch_initiator);
4106 } else {
4107 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
4108 PKT3_SHADER_TYPE_S(1));
4109 radeon_emit(cs, 1);
4110 radeon_emit(cs, va);
4111 radeon_emit(cs, va >> 32);
4112
4113 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
4114 PKT3_SHADER_TYPE_S(1));
4115 radeon_emit(cs, 0);
4116 radeon_emit(cs, dispatch_initiator);
4117 }
4118 } else {
4119 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
4120 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
4121
4122 if (info->unaligned) {
4123 unsigned *cs_block_size = compute_shader->info.cs.block_size;
4124 unsigned remainder[3];
4125
4126 /* If aligned, these should be an entire block size,
4127 * not 0.
4128 */
4129 remainder[0] = blocks[0] + cs_block_size[0] -
4130 align_u32_npot(blocks[0], cs_block_size[0]);
4131 remainder[1] = blocks[1] + cs_block_size[1] -
4132 align_u32_npot(blocks[1], cs_block_size[1]);
4133 remainder[2] = blocks[2] + cs_block_size[2] -
4134 align_u32_npot(blocks[2], cs_block_size[2]);
4135
4136 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
4137 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
4138 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
4139
4140 for(unsigned i = 0; i < 3; ++i) {
4141 assert(offsets[i] % cs_block_size[i] == 0);
4142 offsets[i] /= cs_block_size[i];
4143 }
4144
4145 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4146 radeon_emit(cs,
4147 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
4148 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4149 radeon_emit(cs,
4150 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4151 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4152 radeon_emit(cs,
4153 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4154 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4155
4156 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4157 }
4158
4159 if (loc->sgpr_idx != -1) {
4160 assert(loc->num_sgprs == 3);
4161
4162 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4163 loc->sgpr_idx * 4, 3);
4164 radeon_emit(cs, blocks[0]);
4165 radeon_emit(cs, blocks[1]);
4166 radeon_emit(cs, blocks[2]);
4167 }
4168
4169 if (offsets[0] || offsets[1] || offsets[2]) {
4170 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4171 radeon_emit(cs, offsets[0]);
4172 radeon_emit(cs, offsets[1]);
4173 radeon_emit(cs, offsets[2]);
4174
4175 /* The blocks in the packet are not counts but end values. */
4176 for (unsigned i = 0; i < 3; ++i)
4177 blocks[i] += offsets[i];
4178 } else {
4179 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4180 }
4181
4182 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4183 PKT3_SHADER_TYPE_S(1));
4184 radeon_emit(cs, blocks[0]);
4185 radeon_emit(cs, blocks[1]);
4186 radeon_emit(cs, blocks[2]);
4187 radeon_emit(cs, dispatch_initiator);
4188 }
4189
4190 assert(cmd_buffer->cs->cdw <= cdw_max);
4191 }
4192
4193 static void
4194 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4195 {
4196 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4197 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4198 }
4199
4200 static void
4201 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4202 const struct radv_dispatch_info *info)
4203 {
4204 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4205 bool has_prefetch =
4206 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
4207 bool pipeline_is_dirty = pipeline &&
4208 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4209
4210 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4211 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4212 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4213 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4214 /* If we have to wait for idle, set all states first, so that
4215 * all SET packets are processed in parallel with previous draw
4216 * calls. Then upload descriptors, set shader pointers, and
4217 * dispatch, and prefetch at the end. This ensures that the
4218 * time the CUs are idle is very short. (there are only SET_SH
4219 * packets between the wait and the draw)
4220 */
4221 radv_emit_compute_pipeline(cmd_buffer);
4222 si_emit_cache_flush(cmd_buffer);
4223 /* <-- CUs are idle here --> */
4224
4225 radv_upload_compute_shader_descriptors(cmd_buffer);
4226
4227 radv_emit_dispatch_packets(cmd_buffer, info);
4228 /* <-- CUs are busy here --> */
4229
4230 /* Start prefetches after the dispatch has been started. Both
4231 * will run in parallel, but starting the dispatch first is
4232 * more important.
4233 */
4234 if (has_prefetch && pipeline_is_dirty) {
4235 radv_emit_shader_prefetch(cmd_buffer,
4236 pipeline->shaders[MESA_SHADER_COMPUTE]);
4237 }
4238 } else {
4239 /* If we don't wait for idle, start prefetches first, then set
4240 * states, and dispatch at the end.
4241 */
4242 si_emit_cache_flush(cmd_buffer);
4243
4244 if (has_prefetch && pipeline_is_dirty) {
4245 radv_emit_shader_prefetch(cmd_buffer,
4246 pipeline->shaders[MESA_SHADER_COMPUTE]);
4247 }
4248
4249 radv_upload_compute_shader_descriptors(cmd_buffer);
4250
4251 radv_emit_compute_pipeline(cmd_buffer);
4252 radv_emit_dispatch_packets(cmd_buffer, info);
4253 }
4254
4255 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
4256 }
4257
4258 void radv_CmdDispatchBase(
4259 VkCommandBuffer commandBuffer,
4260 uint32_t base_x,
4261 uint32_t base_y,
4262 uint32_t base_z,
4263 uint32_t x,
4264 uint32_t y,
4265 uint32_t z)
4266 {
4267 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4268 struct radv_dispatch_info info = {};
4269
4270 info.blocks[0] = x;
4271 info.blocks[1] = y;
4272 info.blocks[2] = z;
4273
4274 info.offsets[0] = base_x;
4275 info.offsets[1] = base_y;
4276 info.offsets[2] = base_z;
4277 radv_dispatch(cmd_buffer, &info);
4278 }
4279
4280 void radv_CmdDispatch(
4281 VkCommandBuffer commandBuffer,
4282 uint32_t x,
4283 uint32_t y,
4284 uint32_t z)
4285 {
4286 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4287 }
4288
4289 void radv_CmdDispatchIndirect(
4290 VkCommandBuffer commandBuffer,
4291 VkBuffer _buffer,
4292 VkDeviceSize offset)
4293 {
4294 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4295 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4296 struct radv_dispatch_info info = {};
4297
4298 info.indirect = buffer;
4299 info.indirect_offset = offset;
4300
4301 radv_dispatch(cmd_buffer, &info);
4302 }
4303
4304 void radv_unaligned_dispatch(
4305 struct radv_cmd_buffer *cmd_buffer,
4306 uint32_t x,
4307 uint32_t y,
4308 uint32_t z)
4309 {
4310 struct radv_dispatch_info info = {};
4311
4312 info.blocks[0] = x;
4313 info.blocks[1] = y;
4314 info.blocks[2] = z;
4315 info.unaligned = 1;
4316
4317 radv_dispatch(cmd_buffer, &info);
4318 }
4319
4320 void radv_CmdEndRenderPass(
4321 VkCommandBuffer commandBuffer)
4322 {
4323 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4324
4325 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
4326
4327 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4328
4329 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
4330 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
4331 radv_handle_subpass_image_transition(cmd_buffer,
4332 (struct radv_subpass_attachment){i, layout});
4333 }
4334
4335 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4336
4337 cmd_buffer->state.pass = NULL;
4338 cmd_buffer->state.subpass = NULL;
4339 cmd_buffer->state.attachments = NULL;
4340 cmd_buffer->state.framebuffer = NULL;
4341 }
4342
4343 void radv_CmdEndRenderPass2KHR(
4344 VkCommandBuffer commandBuffer,
4345 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4346 {
4347 radv_CmdEndRenderPass(commandBuffer);
4348 }
4349
4350 /*
4351 * For HTILE we have the following interesting clear words:
4352 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4353 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4354 * 0xfffffff0: Clear depth to 1.0
4355 * 0x00000000: Clear depth to 0.0
4356 */
4357 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
4358 struct radv_image *image,
4359 const VkImageSubresourceRange *range,
4360 uint32_t clear_word)
4361 {
4362 assert(range->baseMipLevel == 0);
4363 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
4364 unsigned layer_count = radv_get_layerCount(image, range);
4365 uint64_t size = image->surface.htile_slice_size * layer_count;
4366 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
4367 uint64_t offset = image->offset + image->htile_offset +
4368 image->surface.htile_slice_size * range->baseArrayLayer;
4369 struct radv_cmd_state *state = &cmd_buffer->state;
4370 VkClearDepthStencilValue value = {};
4371
4372 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4373 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4374
4375 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
4376 size, clear_word);
4377
4378 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4379
4380 if (vk_format_is_stencil(image->vk_format))
4381 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4382
4383 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4384
4385 if (radv_image_is_tc_compat_htile(image)) {
4386 /* Initialize the TC-compat metada value to 0 because by
4387 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
4388 * need have to conditionally update its value when performing
4389 * a fast depth clear.
4390 */
4391 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, 0);
4392 }
4393 }
4394
4395 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4396 struct radv_image *image,
4397 VkImageLayout src_layout,
4398 VkImageLayout dst_layout,
4399 unsigned src_queue_mask,
4400 unsigned dst_queue_mask,
4401 const VkImageSubresourceRange *range)
4402 {
4403 if (!radv_image_has_htile(image))
4404 return;
4405
4406 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
4407 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
4408 /* TODO: merge with the clear if applicable */
4409 radv_initialize_htile(cmd_buffer, image, range, 0);
4410 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4411 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4412 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4413 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4414 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4415 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4416 VkImageSubresourceRange local_range = *range;
4417 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4418 local_range.baseMipLevel = 0;
4419 local_range.levelCount = 1;
4420
4421 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4422 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4423
4424 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
4425
4426 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4427 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4428 }
4429 }
4430
4431 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4432 struct radv_image *image, uint32_t value)
4433 {
4434 struct radv_cmd_state *state = &cmd_buffer->state;
4435
4436 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4437 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4438
4439 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
4440
4441 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4442 }
4443
4444 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
4445 struct radv_image *image)
4446 {
4447 struct radv_cmd_state *state = &cmd_buffer->state;
4448 static const uint32_t fmask_clear_values[4] = {
4449 0x00000000,
4450 0x02020202,
4451 0xE4E4E4E4,
4452 0x76543210
4453 };
4454 uint32_t log2_samples = util_logbase2(image->info.samples);
4455 uint32_t value = fmask_clear_values[log2_samples];
4456
4457 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4458 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4459
4460 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, value);
4461
4462 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4463 }
4464
4465 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4466 struct radv_image *image, uint32_t value)
4467 {
4468 struct radv_cmd_state *state = &cmd_buffer->state;
4469
4470 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4471 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4472
4473 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
4474
4475 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4476 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4477 }
4478
4479 /**
4480 * Initialize DCC/FMASK/CMASK metadata for a color image.
4481 */
4482 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4483 struct radv_image *image,
4484 VkImageLayout src_layout,
4485 VkImageLayout dst_layout,
4486 unsigned src_queue_mask,
4487 unsigned dst_queue_mask)
4488 {
4489 if (radv_image_has_cmask(image)) {
4490 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4491
4492 /* TODO: clarify this. */
4493 if (radv_image_has_fmask(image)) {
4494 value = 0xccccccccu;
4495 }
4496
4497 radv_initialise_cmask(cmd_buffer, image, value);
4498 }
4499
4500 if (radv_image_has_fmask(image)) {
4501 radv_initialize_fmask(cmd_buffer, image);
4502 }
4503
4504 if (radv_image_has_dcc(image)) {
4505 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4506 bool need_decompress_pass = false;
4507
4508 if (radv_layout_dcc_compressed(image, dst_layout,
4509 dst_queue_mask)) {
4510 value = 0x20202020u;
4511 need_decompress_pass = true;
4512 }
4513
4514 radv_initialize_dcc(cmd_buffer, image, value);
4515
4516 radv_update_fce_metadata(cmd_buffer, image,
4517 need_decompress_pass);
4518 }
4519
4520 if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
4521 uint32_t color_values[2] = {};
4522 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
4523 }
4524 }
4525
4526 /**
4527 * Handle color image transitions for DCC/FMASK/CMASK.
4528 */
4529 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4530 struct radv_image *image,
4531 VkImageLayout src_layout,
4532 VkImageLayout dst_layout,
4533 unsigned src_queue_mask,
4534 unsigned dst_queue_mask,
4535 const VkImageSubresourceRange *range)
4536 {
4537 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4538 radv_init_color_image_metadata(cmd_buffer, image,
4539 src_layout, dst_layout,
4540 src_queue_mask, dst_queue_mask);
4541 return;
4542 }
4543
4544 if (radv_image_has_dcc(image)) {
4545 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4546 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4547 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4548 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4549 radv_decompress_dcc(cmd_buffer, image, range);
4550 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4551 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4552 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4553 }
4554 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
4555 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4556 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4557 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4558 }
4559
4560 if (radv_image_has_fmask(image)) {
4561 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
4562 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
4563 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
4564 }
4565 }
4566 }
4567 }
4568
4569 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4570 struct radv_image *image,
4571 VkImageLayout src_layout,
4572 VkImageLayout dst_layout,
4573 uint32_t src_family,
4574 uint32_t dst_family,
4575 const VkImageSubresourceRange *range)
4576 {
4577 if (image->exclusive && src_family != dst_family) {
4578 /* This is an acquire or a release operation and there will be
4579 * a corresponding release/acquire. Do the transition in the
4580 * most flexible queue. */
4581
4582 assert(src_family == cmd_buffer->queue_family_index ||
4583 dst_family == cmd_buffer->queue_family_index);
4584
4585 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4586 return;
4587
4588 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4589 (src_family == RADV_QUEUE_GENERAL ||
4590 dst_family == RADV_QUEUE_GENERAL))
4591 return;
4592 }
4593
4594 unsigned src_queue_mask =
4595 radv_image_queue_family_mask(image, src_family,
4596 cmd_buffer->queue_family_index);
4597 unsigned dst_queue_mask =
4598 radv_image_queue_family_mask(image, dst_family,
4599 cmd_buffer->queue_family_index);
4600
4601 if (vk_format_is_depth(image->vk_format)) {
4602 radv_handle_depth_image_transition(cmd_buffer, image,
4603 src_layout, dst_layout,
4604 src_queue_mask, dst_queue_mask,
4605 range);
4606 } else {
4607 radv_handle_color_image_transition(cmd_buffer, image,
4608 src_layout, dst_layout,
4609 src_queue_mask, dst_queue_mask,
4610 range);
4611 }
4612 }
4613
4614 struct radv_barrier_info {
4615 uint32_t eventCount;
4616 const VkEvent *pEvents;
4617 VkPipelineStageFlags srcStageMask;
4618 };
4619
4620 static void
4621 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
4622 uint32_t memoryBarrierCount,
4623 const VkMemoryBarrier *pMemoryBarriers,
4624 uint32_t bufferMemoryBarrierCount,
4625 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4626 uint32_t imageMemoryBarrierCount,
4627 const VkImageMemoryBarrier *pImageMemoryBarriers,
4628 const struct radv_barrier_info *info)
4629 {
4630 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4631 enum radv_cmd_flush_bits src_flush_bits = 0;
4632 enum radv_cmd_flush_bits dst_flush_bits = 0;
4633
4634 for (unsigned i = 0; i < info->eventCount; ++i) {
4635 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
4636 uint64_t va = radv_buffer_get_va(event->bo);
4637
4638 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4639
4640 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4641
4642 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
4643 assert(cmd_buffer->cs->cdw <= cdw_max);
4644 }
4645
4646 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4647 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
4648 NULL);
4649 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4650 NULL);
4651 }
4652
4653 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4654 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
4655 NULL);
4656 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4657 NULL);
4658 }
4659
4660 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4661 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4662
4663 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
4664 image);
4665 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4666 image);
4667 }
4668
4669 radv_stage_flush(cmd_buffer, info->srcStageMask);
4670 cmd_buffer->state.flush_bits |= src_flush_bits;
4671
4672 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4673 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4674 radv_handle_image_transition(cmd_buffer, image,
4675 pImageMemoryBarriers[i].oldLayout,
4676 pImageMemoryBarriers[i].newLayout,
4677 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4678 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4679 &pImageMemoryBarriers[i].subresourceRange);
4680 }
4681
4682 /* Make sure CP DMA is idle because the driver might have performed a
4683 * DMA operation for copying or filling buffers/images.
4684 */
4685 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
4686 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
4687 si_cp_dma_wait_for_idle(cmd_buffer);
4688
4689 cmd_buffer->state.flush_bits |= dst_flush_bits;
4690 }
4691
4692 void radv_CmdPipelineBarrier(
4693 VkCommandBuffer commandBuffer,
4694 VkPipelineStageFlags srcStageMask,
4695 VkPipelineStageFlags destStageMask,
4696 VkBool32 byRegion,
4697 uint32_t memoryBarrierCount,
4698 const VkMemoryBarrier* pMemoryBarriers,
4699 uint32_t bufferMemoryBarrierCount,
4700 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4701 uint32_t imageMemoryBarrierCount,
4702 const VkImageMemoryBarrier* pImageMemoryBarriers)
4703 {
4704 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4705 struct radv_barrier_info info;
4706
4707 info.eventCount = 0;
4708 info.pEvents = NULL;
4709 info.srcStageMask = srcStageMask;
4710
4711 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4712 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4713 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4714 }
4715
4716
4717 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4718 struct radv_event *event,
4719 VkPipelineStageFlags stageMask,
4720 unsigned value)
4721 {
4722 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4723 uint64_t va = radv_buffer_get_va(event->bo);
4724
4725 si_emit_cache_flush(cmd_buffer);
4726
4727 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4728
4729 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4730
4731 /* Flags that only require a top-of-pipe event. */
4732 VkPipelineStageFlags top_of_pipe_flags =
4733 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
4734
4735 /* Flags that only require a post-index-fetch event. */
4736 VkPipelineStageFlags post_index_fetch_flags =
4737 top_of_pipe_flags |
4738 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
4739 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
4740
4741 /* Make sure CP DMA is idle because the driver might have performed a
4742 * DMA operation for copying or filling buffers/images.
4743 */
4744 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
4745 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
4746 si_cp_dma_wait_for_idle(cmd_buffer);
4747
4748 /* TODO: Emit EOS events for syncing PS/CS stages. */
4749
4750 if (!(stageMask & ~top_of_pipe_flags)) {
4751 /* Just need to sync the PFP engine. */
4752 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4753 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
4754 S_370_WR_CONFIRM(1) |
4755 S_370_ENGINE_SEL(V_370_PFP));
4756 radeon_emit(cs, va);
4757 radeon_emit(cs, va >> 32);
4758 radeon_emit(cs, value);
4759 } else if (!(stageMask & ~post_index_fetch_flags)) {
4760 /* Sync ME because PFP reads index and indirect buffers. */
4761 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4762 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
4763 S_370_WR_CONFIRM(1) |
4764 S_370_ENGINE_SEL(V_370_ME));
4765 radeon_emit(cs, va);
4766 radeon_emit(cs, va >> 32);
4767 radeon_emit(cs, value);
4768 } else {
4769 /* Otherwise, sync all prior GPU work using an EOP event. */
4770 si_cs_emit_write_event_eop(cs,
4771 cmd_buffer->device->physical_device->rad_info.chip_class,
4772 radv_cmd_buffer_uses_mec(cmd_buffer),
4773 V_028A90_BOTTOM_OF_PIPE_TS, 0,
4774 EOP_DATA_SEL_VALUE_32BIT, va, value,
4775 cmd_buffer->gfx9_eop_bug_va);
4776 }
4777
4778 assert(cmd_buffer->cs->cdw <= cdw_max);
4779 }
4780
4781 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4782 VkEvent _event,
4783 VkPipelineStageFlags stageMask)
4784 {
4785 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4786 RADV_FROM_HANDLE(radv_event, event, _event);
4787
4788 write_event(cmd_buffer, event, stageMask, 1);
4789 }
4790
4791 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4792 VkEvent _event,
4793 VkPipelineStageFlags stageMask)
4794 {
4795 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4796 RADV_FROM_HANDLE(radv_event, event, _event);
4797
4798 write_event(cmd_buffer, event, stageMask, 0);
4799 }
4800
4801 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4802 uint32_t eventCount,
4803 const VkEvent* pEvents,
4804 VkPipelineStageFlags srcStageMask,
4805 VkPipelineStageFlags dstStageMask,
4806 uint32_t memoryBarrierCount,
4807 const VkMemoryBarrier* pMemoryBarriers,
4808 uint32_t bufferMemoryBarrierCount,
4809 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4810 uint32_t imageMemoryBarrierCount,
4811 const VkImageMemoryBarrier* pImageMemoryBarriers)
4812 {
4813 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4814 struct radv_barrier_info info;
4815
4816 info.eventCount = eventCount;
4817 info.pEvents = pEvents;
4818 info.srcStageMask = 0;
4819
4820 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4821 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4822 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4823 }
4824
4825
4826 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4827 uint32_t deviceMask)
4828 {
4829 /* No-op */
4830 }
4831
4832 /* VK_EXT_conditional_rendering */
4833 void radv_CmdBeginConditionalRenderingEXT(
4834 VkCommandBuffer commandBuffer,
4835 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
4836 {
4837 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4838 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
4839 bool draw_visible = true;
4840 uint64_t va;
4841
4842 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
4843
4844 /* By default, if the 32-bit value at offset in buffer memory is zero,
4845 * then the rendering commands are discarded, otherwise they are
4846 * executed as normal. If the inverted flag is set, all commands are
4847 * discarded if the value is non zero.
4848 */
4849 if (pConditionalRenderingBegin->flags &
4850 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
4851 draw_visible = false;
4852 }
4853
4854 si_emit_cache_flush(cmd_buffer);
4855
4856 /* Enable predication for this command buffer. */
4857 si_emit_set_predication_state(cmd_buffer, draw_visible, va);
4858 cmd_buffer->state.predicating = true;
4859
4860 /* Store conditional rendering user info. */
4861 cmd_buffer->state.predication_type = draw_visible;
4862 cmd_buffer->state.predication_va = va;
4863 }
4864
4865 void radv_CmdEndConditionalRenderingEXT(
4866 VkCommandBuffer commandBuffer)
4867 {
4868 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4869
4870 /* Disable predication for this command buffer. */
4871 si_emit_set_predication_state(cmd_buffer, false, 0);
4872 cmd_buffer->state.predicating = false;
4873
4874 /* Reset conditional rendering user info. */
4875 cmd_buffer->state.predication_type = -1;
4876 cmd_buffer->state.predication_va = 0;
4877 }
4878
4879 /* VK_EXT_transform_feedback */
4880 void radv_CmdBindTransformFeedbackBuffersEXT(
4881 VkCommandBuffer commandBuffer,
4882 uint32_t firstBinding,
4883 uint32_t bindingCount,
4884 const VkBuffer* pBuffers,
4885 const VkDeviceSize* pOffsets,
4886 const VkDeviceSize* pSizes)
4887 {
4888 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4889 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
4890 uint8_t enabled_mask = 0;
4891
4892 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
4893 for (uint32_t i = 0; i < bindingCount; i++) {
4894 uint32_t idx = firstBinding + i;
4895
4896 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
4897 sb[idx].offset = pOffsets[i];
4898 sb[idx].size = pSizes[i];
4899
4900 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
4901 sb[idx].buffer->bo);
4902
4903 enabled_mask |= 1 << idx;
4904 }
4905
4906 cmd_buffer->state.streamout.enabled_mask = enabled_mask;
4907
4908 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
4909 }
4910
4911 static void
4912 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
4913 {
4914 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4915 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4916
4917 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
4918 radeon_emit(cs,
4919 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
4920 S_028B94_RAST_STREAM(0) |
4921 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
4922 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
4923 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
4924 radeon_emit(cs, so->hw_enabled_mask &
4925 so->enabled_stream_buffers_mask);
4926
4927 cmd_buffer->state.context_roll_without_scissor_emitted = true;
4928 }
4929
4930 static void
4931 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
4932 {
4933 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4934 bool old_streamout_enabled = so->streamout_enabled;
4935 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
4936
4937 so->streamout_enabled = enable;
4938
4939 so->hw_enabled_mask = so->enabled_mask |
4940 (so->enabled_mask << 4) |
4941 (so->enabled_mask << 8) |
4942 (so->enabled_mask << 12);
4943
4944 if ((old_streamout_enabled != so->streamout_enabled) ||
4945 (old_hw_enabled_mask != so->hw_enabled_mask))
4946 radv_emit_streamout_enable(cmd_buffer);
4947 }
4948
4949 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
4950 {
4951 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4952 unsigned reg_strmout_cntl;
4953
4954 /* The register is at different places on different ASICs. */
4955 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
4956 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
4957 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
4958 } else {
4959 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
4960 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
4961 }
4962
4963 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4964 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
4965
4966 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
4967 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
4968 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
4969 radeon_emit(cs, 0);
4970 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
4971 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
4972 radeon_emit(cs, 4); /* poll interval */
4973 }
4974
4975 void radv_CmdBeginTransformFeedbackEXT(
4976 VkCommandBuffer commandBuffer,
4977 uint32_t firstCounterBuffer,
4978 uint32_t counterBufferCount,
4979 const VkBuffer* pCounterBuffers,
4980 const VkDeviceSize* pCounterBufferOffsets)
4981 {
4982 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4983 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
4984 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4985 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4986 uint32_t i;
4987
4988 radv_flush_vgt_streamout(cmd_buffer);
4989
4990 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
4991 for_each_bit(i, so->enabled_mask) {
4992 int32_t counter_buffer_idx = i - firstCounterBuffer;
4993 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
4994 counter_buffer_idx = -1;
4995
4996 /* SI binds streamout buffers as shader resources.
4997 * VGT only counts primitives and tells the shader through
4998 * SGPRs what to do.
4999 */
5000 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
5001 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
5002 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
5003
5004 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5005
5006 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5007 /* The array of counter buffers is optional. */
5008 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5009 uint64_t va = radv_buffer_get_va(buffer->bo);
5010
5011 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5012
5013 /* Append */
5014 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5015 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5016 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5017 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
5018 radeon_emit(cs, 0); /* unused */
5019 radeon_emit(cs, 0); /* unused */
5020 radeon_emit(cs, va); /* src address lo */
5021 radeon_emit(cs, va >> 32); /* src address hi */
5022
5023 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5024 } else {
5025 /* Start from the beginning. */
5026 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5027 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5028 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5029 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
5030 radeon_emit(cs, 0); /* unused */
5031 radeon_emit(cs, 0); /* unused */
5032 radeon_emit(cs, 0); /* unused */
5033 radeon_emit(cs, 0); /* unused */
5034 }
5035 }
5036
5037 radv_set_streamout_enable(cmd_buffer, true);
5038 }
5039
5040 void radv_CmdEndTransformFeedbackEXT(
5041 VkCommandBuffer commandBuffer,
5042 uint32_t firstCounterBuffer,
5043 uint32_t counterBufferCount,
5044 const VkBuffer* pCounterBuffers,
5045 const VkDeviceSize* pCounterBufferOffsets)
5046 {
5047 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5048 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5049 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5050 uint32_t i;
5051
5052 radv_flush_vgt_streamout(cmd_buffer);
5053
5054 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5055 for_each_bit(i, so->enabled_mask) {
5056 int32_t counter_buffer_idx = i - firstCounterBuffer;
5057 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5058 counter_buffer_idx = -1;
5059
5060 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5061 /* The array of counters buffer is optional. */
5062 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5063 uint64_t va = radv_buffer_get_va(buffer->bo);
5064
5065 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5066
5067 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5068 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5069 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5070 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
5071 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
5072 radeon_emit(cs, va); /* dst address lo */
5073 radeon_emit(cs, va >> 32); /* dst address hi */
5074 radeon_emit(cs, 0); /* unused */
5075 radeon_emit(cs, 0); /* unused */
5076
5077 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5078 }
5079
5080 /* Deactivate transform feedback by zeroing the buffer size.
5081 * The counters (primitives generated, primitives emitted) may
5082 * be enabled even if there is not buffer bound. This ensures
5083 * that the primitives-emitted query won't increment.
5084 */
5085 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
5086
5087 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5088 }
5089
5090 radv_set_streamout_enable(cmd_buffer, false);
5091 }
5092
5093 void radv_CmdDrawIndirectByteCountEXT(
5094 VkCommandBuffer commandBuffer,
5095 uint32_t instanceCount,
5096 uint32_t firstInstance,
5097 VkBuffer _counterBuffer,
5098 VkDeviceSize counterBufferOffset,
5099 uint32_t counterOffset,
5100 uint32_t vertexStride)
5101 {
5102 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5103 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
5104 struct radv_draw_info info = {};
5105
5106 info.instance_count = instanceCount;
5107 info.first_instance = firstInstance;
5108 info.strmout_buffer = counterBuffer;
5109 info.strmout_buffer_offset = counterBufferOffset;
5110 info.stride = vertexStride;
5111
5112 radv_draw(cmd_buffer, &info);
5113 }