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radv: move shaders related code to radv_shader.c
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_meta.h"
36
37 #include "ac_debug.h"
38
39 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
40 struct radv_image *image,
41 VkImageLayout src_layout,
42 VkImageLayout dst_layout,
43 uint32_t src_family,
44 uint32_t dst_family,
45 const VkImageSubresourceRange *range,
46 VkImageAspectFlags pending_clears);
47
48 const struct radv_dynamic_state default_dynamic_state = {
49 .viewport = {
50 .count = 0,
51 },
52 .scissor = {
53 .count = 0,
54 },
55 .line_width = 1.0f,
56 .depth_bias = {
57 .bias = 0.0f,
58 .clamp = 0.0f,
59 .slope = 0.0f,
60 },
61 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
62 .depth_bounds = {
63 .min = 0.0f,
64 .max = 1.0f,
65 },
66 .stencil_compare_mask = {
67 .front = ~0u,
68 .back = ~0u,
69 },
70 .stencil_write_mask = {
71 .front = ~0u,
72 .back = ~0u,
73 },
74 .stencil_reference = {
75 .front = 0u,
76 .back = 0u,
77 },
78 };
79
80 void
81 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
82 const struct radv_dynamic_state *src,
83 uint32_t copy_mask)
84 {
85 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
86 dest->viewport.count = src->viewport.count;
87 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
88 src->viewport.count);
89 }
90
91 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
92 dest->scissor.count = src->scissor.count;
93 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
94 src->scissor.count);
95 }
96
97 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
98 dest->line_width = src->line_width;
99
100 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
101 dest->depth_bias = src->depth_bias;
102
103 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
104 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
105
106 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
107 dest->depth_bounds = src->depth_bounds;
108
109 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
110 dest->stencil_compare_mask = src->stencil_compare_mask;
111
112 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
113 dest->stencil_write_mask = src->stencil_write_mask;
114
115 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
116 dest->stencil_reference = src->stencil_reference;
117 }
118
119 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
120 {
121 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
122 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
123 }
124
125 enum ring_type radv_queue_family_to_ring(int f) {
126 switch (f) {
127 case RADV_QUEUE_GENERAL:
128 return RING_GFX;
129 case RADV_QUEUE_COMPUTE:
130 return RING_COMPUTE;
131 case RADV_QUEUE_TRANSFER:
132 return RING_DMA;
133 default:
134 unreachable("Unknown queue family");
135 }
136 }
137
138 static VkResult radv_create_cmd_buffer(
139 struct radv_device * device,
140 struct radv_cmd_pool * pool,
141 VkCommandBufferLevel level,
142 VkCommandBuffer* pCommandBuffer)
143 {
144 struct radv_cmd_buffer *cmd_buffer;
145 VkResult result;
146 unsigned ring;
147 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
148 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
149 if (cmd_buffer == NULL)
150 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
151
152 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
153 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
154 cmd_buffer->device = device;
155 cmd_buffer->pool = pool;
156 cmd_buffer->level = level;
157
158 if (pool) {
159 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
160 cmd_buffer->queue_family_index = pool->queue_family_index;
161
162 } else {
163 /* Init the pool_link so we can safefly call list_del when we destroy
164 * the command buffer
165 */
166 list_inithead(&cmd_buffer->pool_link);
167 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
168 }
169
170 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
171
172 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
173 if (!cmd_buffer->cs) {
174 result = VK_ERROR_OUT_OF_HOST_MEMORY;
175 goto fail;
176 }
177
178 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
179
180 cmd_buffer->upload.offset = 0;
181 cmd_buffer->upload.size = 0;
182 list_inithead(&cmd_buffer->upload.list);
183
184 return VK_SUCCESS;
185
186 fail:
187 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
188
189 return result;
190 }
191
192 static void
193 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
194 {
195 list_del(&cmd_buffer->pool_link);
196
197 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
198 &cmd_buffer->upload.list, list) {
199 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
200 list_del(&up->list);
201 free(up);
202 }
203
204 if (cmd_buffer->upload.upload_bo)
205 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
206 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
207 free(cmd_buffer->push_descriptors.set.mapped_ptr);
208 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
209 }
210
211 static void radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
212 {
213
214 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
215
216 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
217 &cmd_buffer->upload.list, list) {
218 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
219 list_del(&up->list);
220 free(up);
221 }
222
223 cmd_buffer->scratch_size_needed = 0;
224 cmd_buffer->compute_scratch_size_needed = 0;
225 cmd_buffer->esgs_ring_size_needed = 0;
226 cmd_buffer->gsvs_ring_size_needed = 0;
227 cmd_buffer->tess_rings_needed = false;
228 cmd_buffer->sample_positions_needed = false;
229
230 if (cmd_buffer->upload.upload_bo)
231 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
232 cmd_buffer->upload.upload_bo, 8);
233 cmd_buffer->upload.offset = 0;
234
235 cmd_buffer->record_result = VK_SUCCESS;
236
237 cmd_buffer->ring_offsets_idx = -1;
238
239 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
240 void *fence_ptr;
241 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
242 &cmd_buffer->gfx9_fence_offset,
243 &fence_ptr);
244 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
245 }
246 }
247
248 static bool
249 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
250 uint64_t min_needed)
251 {
252 uint64_t new_size;
253 struct radeon_winsys_bo *bo;
254 struct radv_cmd_buffer_upload *upload;
255 struct radv_device *device = cmd_buffer->device;
256
257 new_size = MAX2(min_needed, 16 * 1024);
258 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
259
260 bo = device->ws->buffer_create(device->ws,
261 new_size, 4096,
262 RADEON_DOMAIN_GTT,
263 RADEON_FLAG_CPU_ACCESS);
264
265 if (!bo) {
266 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
267 return false;
268 }
269
270 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
271 if (cmd_buffer->upload.upload_bo) {
272 upload = malloc(sizeof(*upload));
273
274 if (!upload) {
275 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
276 device->ws->buffer_destroy(bo);
277 return false;
278 }
279
280 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
281 list_add(&upload->list, &cmd_buffer->upload.list);
282 }
283
284 cmd_buffer->upload.upload_bo = bo;
285 cmd_buffer->upload.size = new_size;
286 cmd_buffer->upload.offset = 0;
287 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
288
289 if (!cmd_buffer->upload.map) {
290 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
291 return false;
292 }
293
294 return true;
295 }
296
297 bool
298 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
299 unsigned size,
300 unsigned alignment,
301 unsigned *out_offset,
302 void **ptr)
303 {
304 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
305 if (offset + size > cmd_buffer->upload.size) {
306 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
307 return false;
308 offset = 0;
309 }
310
311 *out_offset = offset;
312 *ptr = cmd_buffer->upload.map + offset;
313
314 cmd_buffer->upload.offset = offset + size;
315 return true;
316 }
317
318 bool
319 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
320 unsigned size, unsigned alignment,
321 const void *data, unsigned *out_offset)
322 {
323 uint8_t *ptr;
324
325 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
326 out_offset, (void **)&ptr))
327 return false;
328
329 if (ptr)
330 memcpy(ptr, data, size);
331
332 return true;
333 }
334
335 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
336 {
337 struct radv_device *device = cmd_buffer->device;
338 struct radeon_winsys_cs *cs = cmd_buffer->cs;
339 uint64_t va;
340
341 if (!device->trace_bo)
342 return;
343
344 va = device->ws->buffer_get_va(device->trace_bo);
345 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
346 va += 4;
347
348 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
349
350 ++cmd_buffer->state.trace_id;
351 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
352 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
353 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
354 S_370_WR_CONFIRM(1) |
355 S_370_ENGINE_SEL(V_370_ME));
356 radeon_emit(cs, va);
357 radeon_emit(cs, va >> 32);
358 radeon_emit(cs, cmd_buffer->state.trace_id);
359 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
360 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
361 }
362
363 static void
364 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
365 struct radv_pipeline *pipeline)
366 {
367 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
368 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
369 8);
370 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
371 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
372
373 if (cmd_buffer->device->physical_device->has_rbplus) {
374
375 radeon_set_context_reg_seq(cmd_buffer->cs, R_028760_SX_MRT0_BLEND_OPT, 8);
376 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.sx_mrt_blend_opt, 8);
377
378 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
379 radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
380 radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
381 radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
382 }
383 }
384
385 static void
386 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
387 struct radv_pipeline *pipeline)
388 {
389 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
390 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
391 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
392
393 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
394 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
395 }
396
397 /* 12.4 fixed-point */
398 static unsigned radv_pack_float_12p4(float x)
399 {
400 return x <= 0 ? 0 :
401 x >= 4096 ? 0xffff : x * 16;
402 }
403
404 struct ac_userdata_info *
405 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
406 gl_shader_stage stage,
407 int idx)
408 {
409 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
410 }
411
412 static void
413 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
414 struct radv_pipeline *pipeline,
415 gl_shader_stage stage,
416 int idx, uint64_t va)
417 {
418 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
419 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
420 if (loc->sgpr_idx == -1)
421 return;
422 assert(loc->num_sgprs == 2);
423 assert(!loc->indirect);
424 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
425 radeon_emit(cmd_buffer->cs, va);
426 radeon_emit(cmd_buffer->cs, va >> 32);
427 }
428
429 static void
430 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
431 struct radv_pipeline *pipeline)
432 {
433 int num_samples = pipeline->graphics.ms.num_samples;
434 struct radv_multisample_state *ms = &pipeline->graphics.ms;
435 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
436
437 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
438 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
439 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
440
441 radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa);
442 radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
443
444 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
445 return;
446
447 radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
448 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
449 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
450
451 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
452
453 /* GFX9: Flush DFSM when the AA mode changes. */
454 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
455 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
456 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
457 }
458 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
459 uint32_t offset;
460 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
461 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
462 if (loc->sgpr_idx == -1)
463 return;
464 assert(loc->num_sgprs == 1);
465 assert(!loc->indirect);
466 switch (num_samples) {
467 default:
468 offset = 0;
469 break;
470 case 2:
471 offset = 1;
472 break;
473 case 4:
474 offset = 3;
475 break;
476 case 8:
477 offset = 7;
478 break;
479 case 16:
480 offset = 15;
481 break;
482 }
483
484 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
485 cmd_buffer->sample_positions_needed = true;
486 }
487 }
488
489 static void
490 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
491 struct radv_pipeline *pipeline)
492 {
493 struct radv_raster_state *raster = &pipeline->graphics.raster;
494
495 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
496 raster->pa_cl_clip_cntl);
497
498 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
499 raster->spi_interp_control);
500
501 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A00_PA_SU_POINT_SIZE, 2);
502 unsigned tmp = (unsigned)(1.0 * 8.0);
503 radeon_emit(cmd_buffer->cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
504 radeon_emit(cmd_buffer->cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
505 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
506
507 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
508 raster->pa_su_vtx_cntl);
509
510 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
511 raster->pa_su_sc_mode_cntl);
512 }
513
514 static inline void
515 radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
516 unsigned size)
517 {
518 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
519 si_cp_dma_prefetch(cmd_buffer, va, size);
520 }
521
522 static void
523 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
524 struct radv_pipeline *pipeline,
525 struct radv_shader_variant *shader,
526 struct ac_vs_output_info *outinfo)
527 {
528 struct radeon_winsys *ws = cmd_buffer->device->ws;
529 uint64_t va = ws->buffer_get_va(shader->bo) + shader->bo_offset;
530 unsigned export_count;
531
532 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
533 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
534
535 export_count = MAX2(1, outinfo->param_exports);
536 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
537 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
538
539 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
540 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
541 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
542 V_02870C_SPI_SHADER_4COMP :
543 V_02870C_SPI_SHADER_NONE) |
544 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
545 V_02870C_SPI_SHADER_4COMP :
546 V_02870C_SPI_SHADER_NONE) |
547 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
548 V_02870C_SPI_SHADER_4COMP :
549 V_02870C_SPI_SHADER_NONE));
550
551
552 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
553 radeon_emit(cmd_buffer->cs, va >> 8);
554 radeon_emit(cmd_buffer->cs, va >> 40);
555 radeon_emit(cmd_buffer->cs, shader->rsrc1);
556 radeon_emit(cmd_buffer->cs, shader->rsrc2);
557
558 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
559 S_028818_VTX_W0_FMT(1) |
560 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
561 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
562 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
563
564
565 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
566 pipeline->graphics.pa_cl_vs_out_cntl);
567
568 if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
569 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
570 S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
571 }
572
573 static void
574 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
575 struct radv_shader_variant *shader,
576 struct ac_es_output_info *outinfo)
577 {
578 struct radeon_winsys *ws = cmd_buffer->device->ws;
579 uint64_t va = ws->buffer_get_va(shader->bo) + shader->bo_offset;
580
581 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
582 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
583
584 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
585 outinfo->esgs_itemsize / 4);
586 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
587 radeon_emit(cmd_buffer->cs, va >> 8);
588 radeon_emit(cmd_buffer->cs, va >> 40);
589 radeon_emit(cmd_buffer->cs, shader->rsrc1);
590 radeon_emit(cmd_buffer->cs, shader->rsrc2);
591 }
592
593 static void
594 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
595 struct radv_shader_variant *shader)
596 {
597 struct radeon_winsys *ws = cmd_buffer->device->ws;
598 uint64_t va = ws->buffer_get_va(shader->bo) + shader->bo_offset;
599 uint32_t rsrc2 = shader->rsrc2;
600
601 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
602 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
603
604 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
605 radeon_emit(cmd_buffer->cs, va >> 8);
606 radeon_emit(cmd_buffer->cs, va >> 40);
607
608 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
609 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
610 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
611 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
612
613 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
614 radeon_emit(cmd_buffer->cs, shader->rsrc1);
615 radeon_emit(cmd_buffer->cs, rsrc2);
616 }
617
618 static void
619 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
620 struct radv_shader_variant *shader)
621 {
622 struct radeon_winsys *ws = cmd_buffer->device->ws;
623 uint64_t va = ws->buffer_get_va(shader->bo) + shader->bo_offset;
624
625 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
626 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
627
628 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
629 radeon_emit(cmd_buffer->cs, va >> 8);
630 radeon_emit(cmd_buffer->cs, va >> 40);
631 radeon_emit(cmd_buffer->cs, shader->rsrc1);
632 radeon_emit(cmd_buffer->cs, shader->rsrc2);
633 }
634
635 static void
636 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
637 struct radv_pipeline *pipeline)
638 {
639 struct radv_shader_variant *vs;
640
641 assert (pipeline->shaders[MESA_SHADER_VERTEX]);
642
643 vs = pipeline->shaders[MESA_SHADER_VERTEX];
644
645 if (vs->info.vs.as_ls)
646 radv_emit_hw_ls(cmd_buffer, vs);
647 else if (vs->info.vs.as_es)
648 radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info);
649 else
650 radv_emit_hw_vs(cmd_buffer, pipeline, vs, &vs->info.vs.outinfo);
651
652 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en);
653 }
654
655
656 static void
657 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
658 struct radv_pipeline *pipeline)
659 {
660 if (!radv_pipeline_has_tess(pipeline))
661 return;
662
663 struct radv_shader_variant *tes, *tcs;
664
665 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
666 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
667
668 if (tes->info.tes.as_es)
669 radv_emit_hw_es(cmd_buffer, tes, &tes->info.tes.es_info);
670 else
671 radv_emit_hw_vs(cmd_buffer, pipeline, tes, &tes->info.tes.outinfo);
672
673 radv_emit_hw_hs(cmd_buffer, tcs);
674
675 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
676 pipeline->graphics.tess.tf_param);
677
678 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
679 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
680 pipeline->graphics.tess.ls_hs_config);
681 else
682 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
683 pipeline->graphics.tess.ls_hs_config);
684
685 struct ac_userdata_info *loc;
686
687 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
688 if (loc->sgpr_idx != -1) {
689 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
690 assert(loc->num_sgprs == 4);
691 assert(!loc->indirect);
692 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
693 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
694 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
695 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
696 pipeline->graphics.tess.num_tcs_input_cp << 26);
697 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
698 }
699
700 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
701 if (loc->sgpr_idx != -1) {
702 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
703 assert(loc->num_sgprs == 1);
704 assert(!loc->indirect);
705
706 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
707 pipeline->graphics.tess.offchip_layout);
708 }
709
710 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
711 if (loc->sgpr_idx != -1) {
712 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
713 assert(loc->num_sgprs == 1);
714 assert(!loc->indirect);
715
716 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
717 pipeline->graphics.tess.tcs_in_layout);
718 }
719 }
720
721 static void
722 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
723 struct radv_pipeline *pipeline)
724 {
725 struct radeon_winsys *ws = cmd_buffer->device->ws;
726 struct radv_shader_variant *gs;
727 uint64_t va;
728
729 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
730
731 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
732 if (!gs)
733 return;
734
735 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
736
737 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
738 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
739 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
740 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
741
742 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
743
744 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
745
746 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
747 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
748 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
749 radeon_emit(cmd_buffer->cs, 0);
750 radeon_emit(cmd_buffer->cs, 0);
751 radeon_emit(cmd_buffer->cs, 0);
752
753 uint32_t gs_num_invocations = gs->info.gs.invocations;
754 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
755 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
756 S_028B90_ENABLE(gs_num_invocations > 0));
757
758 va = ws->buffer_get_va(gs->bo) + gs->bo_offset;
759 ws->cs_add_buffer(cmd_buffer->cs, gs->bo, 8);
760 radv_emit_prefetch(cmd_buffer, va, gs->code_size);
761
762 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
763 radeon_emit(cmd_buffer->cs, va >> 8);
764 radeon_emit(cmd_buffer->cs, va >> 40);
765 radeon_emit(cmd_buffer->cs, gs->rsrc1);
766 radeon_emit(cmd_buffer->cs, gs->rsrc2);
767
768 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader, &pipeline->gs_copy_shader->info.vs.outinfo);
769
770 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
771 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
772 if (loc->sgpr_idx != -1) {
773 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
774 uint32_t num_entries = 64;
775 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
776
777 if (is_vi)
778 num_entries *= stride;
779
780 stride = S_008F04_STRIDE(stride);
781 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
782 radeon_emit(cmd_buffer->cs, stride);
783 radeon_emit(cmd_buffer->cs, num_entries);
784 }
785 }
786
787 static void
788 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
789 struct radv_pipeline *pipeline)
790 {
791 struct radeon_winsys *ws = cmd_buffer->device->ws;
792 struct radv_shader_variant *ps;
793 uint64_t va;
794 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
795 struct radv_blend_state *blend = &pipeline->graphics.blend;
796 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
797
798 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
799 va = ws->buffer_get_va(ps->bo) + ps->bo_offset;
800 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
801 radv_emit_prefetch(cmd_buffer, va, ps->code_size);
802
803 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
804 radeon_emit(cmd_buffer->cs, va >> 8);
805 radeon_emit(cmd_buffer->cs, va >> 40);
806 radeon_emit(cmd_buffer->cs, ps->rsrc1);
807 radeon_emit(cmd_buffer->cs, ps->rsrc2);
808
809 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
810 pipeline->graphics.db_shader_control);
811
812 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
813 ps->config.spi_ps_input_ena);
814
815 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
816 ps->config.spi_ps_input_addr);
817
818 if (ps->info.info.ps.force_persample)
819 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
820
821 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
822 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
823
824 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
825
826 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
827 pipeline->graphics.shader_z_format);
828
829 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
830
831 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
832 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
833
834 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
835 /* optimise this? */
836 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
837 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
838 }
839
840 if (pipeline->graphics.ps_input_cntl_num) {
841 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
842 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
843 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
844 }
845 }
846 }
847
848 static void polaris_set_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
849 struct radv_pipeline *pipeline)
850 {
851 uint32_t vtx_reuse_depth = 30;
852 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
853 return;
854
855 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
856 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD)
857 vtx_reuse_depth = 14;
858 }
859 radeon_set_context_reg(cmd_buffer->cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
860 vtx_reuse_depth);
861 }
862
863 static void
864 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer,
865 struct radv_pipeline *pipeline)
866 {
867 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
868 return;
869
870 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
871 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
872 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
873 radv_update_multisample_state(cmd_buffer, pipeline);
874 radv_emit_vertex_shader(cmd_buffer, pipeline);
875 radv_emit_tess_shaders(cmd_buffer, pipeline);
876 radv_emit_geometry_shader(cmd_buffer, pipeline);
877 radv_emit_fragment_shader(cmd_buffer, pipeline);
878 polaris_set_vgt_vertex_reuse(cmd_buffer, pipeline);
879
880 cmd_buffer->scratch_size_needed =
881 MAX2(cmd_buffer->scratch_size_needed,
882 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
883
884 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
885 S_0286E8_WAVES(pipeline->max_waves) |
886 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
887
888 if (!cmd_buffer->state.emitted_pipeline ||
889 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
890 pipeline->graphics.can_use_guardband)
891 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
892
893 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
894
895 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
896 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
897 } else {
898 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
899 }
900 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
901
902 cmd_buffer->state.emitted_pipeline = pipeline;
903 }
904
905 static void
906 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
907 {
908 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
909 cmd_buffer->state.dynamic.viewport.viewports);
910 }
911
912 static void
913 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
914 {
915 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
916 si_write_scissors(cmd_buffer->cs, 0, count,
917 cmd_buffer->state.dynamic.scissor.scissors,
918 cmd_buffer->state.dynamic.viewport.viewports,
919 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
920 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
921 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
922 }
923
924 static void
925 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
926 int index,
927 struct radv_color_buffer_info *cb)
928 {
929 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
930
931 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
932 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
933 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
934 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
935 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
936 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
937 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
938 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
939 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
940 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
941 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
942 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
943 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
944
945 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
946 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
947 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
948
949 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
950 cb->gfx9_epitch);
951 } else {
952 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
953 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
954 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
955 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
956 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
957 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
958 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
959 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
960 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
961 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
962 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
963 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
964
965 if (is_vi) { /* DCC BASE */
966 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
967 }
968 }
969 }
970
971 static void
972 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
973 struct radv_ds_buffer_info *ds,
974 struct radv_image *image,
975 VkImageLayout layout)
976 {
977 uint32_t db_z_info = ds->db_z_info;
978 uint32_t db_stencil_info = ds->db_stencil_info;
979
980 if (!radv_layout_has_htile(image, layout,
981 radv_image_queue_family_mask(image,
982 cmd_buffer->queue_family_index,
983 cmd_buffer->queue_family_index))) {
984 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
985 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
986 }
987
988 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
989 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
990
991
992 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
993 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
994 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
995 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
996 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
997
998 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
999 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1000 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1001 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1002 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); /* DB_Z_READ_BASE_HI */
1003 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1004 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
1005 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1006 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
1007 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1008 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
1009
1010 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1011 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1012 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1013 } else {
1014 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1015
1016 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1017 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1018 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1019 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1020 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1021 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1022 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1023 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1024 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1025 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1026
1027 }
1028
1029 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1030 ds->pa_su_poly_offset_db_fmt_cntl);
1031 }
1032
1033 void
1034 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1035 struct radv_image *image,
1036 VkClearDepthStencilValue ds_clear_value,
1037 VkImageAspectFlags aspects)
1038 {
1039 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1040 va += image->offset + image->clear_value_offset;
1041 unsigned reg_offset = 0, reg_count = 0;
1042
1043 if (!image->surface.htile_size || !aspects)
1044 return;
1045
1046 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1047 ++reg_count;
1048 } else {
1049 ++reg_offset;
1050 va += 4;
1051 }
1052 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1053 ++reg_count;
1054
1055 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1056
1057 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1058 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1059 S_370_WR_CONFIRM(1) |
1060 S_370_ENGINE_SEL(V_370_PFP));
1061 radeon_emit(cmd_buffer->cs, va);
1062 radeon_emit(cmd_buffer->cs, va >> 32);
1063 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1064 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1065 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1066 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1067
1068 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1069 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1070 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1071 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1072 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1073 }
1074
1075 static void
1076 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1077 struct radv_image *image)
1078 {
1079 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1080 va += image->offset + image->clear_value_offset;
1081
1082 if (!image->surface.htile_size)
1083 return;
1084
1085 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1086
1087 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1088 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1089 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1090 COPY_DATA_COUNT_SEL);
1091 radeon_emit(cmd_buffer->cs, va);
1092 radeon_emit(cmd_buffer->cs, va >> 32);
1093 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
1094 radeon_emit(cmd_buffer->cs, 0);
1095
1096 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1097 radeon_emit(cmd_buffer->cs, 0);
1098 }
1099
1100 /*
1101 *with DCC some colors don't require CMASK elimiation before being
1102 * used as a texture. This sets a predicate value to determine if the
1103 * cmask eliminate is required.
1104 */
1105 void
1106 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1107 struct radv_image *image,
1108 bool value)
1109 {
1110 uint64_t pred_val = value;
1111 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1112 va += image->offset + image->dcc_pred_offset;
1113
1114 if (!image->surface.dcc_size)
1115 return;
1116
1117 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1118
1119 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1120 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1121 S_370_WR_CONFIRM(1) |
1122 S_370_ENGINE_SEL(V_370_PFP));
1123 radeon_emit(cmd_buffer->cs, va);
1124 radeon_emit(cmd_buffer->cs, va >> 32);
1125 radeon_emit(cmd_buffer->cs, pred_val);
1126 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1127 }
1128
1129 void
1130 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1131 struct radv_image *image,
1132 int idx,
1133 uint32_t color_values[2])
1134 {
1135 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1136 va += image->offset + image->clear_value_offset;
1137
1138 if (!image->cmask.size && !image->surface.dcc_size)
1139 return;
1140
1141 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1142
1143 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1144 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1145 S_370_WR_CONFIRM(1) |
1146 S_370_ENGINE_SEL(V_370_PFP));
1147 radeon_emit(cmd_buffer->cs, va);
1148 radeon_emit(cmd_buffer->cs, va >> 32);
1149 radeon_emit(cmd_buffer->cs, color_values[0]);
1150 radeon_emit(cmd_buffer->cs, color_values[1]);
1151
1152 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1153 radeon_emit(cmd_buffer->cs, color_values[0]);
1154 radeon_emit(cmd_buffer->cs, color_values[1]);
1155 }
1156
1157 static void
1158 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1159 struct radv_image *image,
1160 int idx)
1161 {
1162 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1163 va += image->offset + image->clear_value_offset;
1164
1165 if (!image->cmask.size && !image->surface.dcc_size)
1166 return;
1167
1168 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1169 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1170
1171 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1172 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1173 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1174 COPY_DATA_COUNT_SEL);
1175 radeon_emit(cmd_buffer->cs, va);
1176 radeon_emit(cmd_buffer->cs, va >> 32);
1177 radeon_emit(cmd_buffer->cs, reg >> 2);
1178 radeon_emit(cmd_buffer->cs, 0);
1179
1180 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1181 radeon_emit(cmd_buffer->cs, 0);
1182 }
1183
1184 void
1185 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1186 {
1187 int i;
1188 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1189 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1190
1191 /* this may happen for inherited secondary recording */
1192 if (!framebuffer)
1193 return;
1194
1195 for (i = 0; i < 8; ++i) {
1196 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1197 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1198 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1199 continue;
1200 }
1201
1202 int idx = subpass->color_attachments[i].attachment;
1203 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1204
1205 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1206
1207 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1208 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1209
1210 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1211 }
1212
1213 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1214 int idx = subpass->depth_stencil_attachment.attachment;
1215 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1216 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1217 struct radv_image *image = att->attachment->image;
1218 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1219 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1220 cmd_buffer->queue_family_index,
1221 cmd_buffer->queue_family_index);
1222 /* We currently don't support writing decompressed HTILE */
1223 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1224 radv_layout_is_htile_compressed(image, layout, queue_mask));
1225
1226 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1227
1228 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1229 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1230 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1231 }
1232 radv_load_depth_clear_regs(cmd_buffer, image);
1233 } else {
1234 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1235 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1236 else
1237 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1238
1239 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1240 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1241 }
1242 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1243 S_028208_BR_X(framebuffer->width) |
1244 S_028208_BR_Y(framebuffer->height));
1245
1246 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1247 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1248 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1249 }
1250 }
1251
1252 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1253 {
1254 uint32_t db_count_control;
1255
1256 if(!cmd_buffer->state.active_occlusion_queries) {
1257 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1258 db_count_control = 0;
1259 } else {
1260 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1261 }
1262 } else {
1263 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1264 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1265 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1266 S_028004_ZPASS_ENABLE(1) |
1267 S_028004_SLICE_EVEN_ENABLE(1) |
1268 S_028004_SLICE_ODD_ENABLE(1);
1269 } else {
1270 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1271 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1272 }
1273 }
1274
1275 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1276 }
1277
1278 static void
1279 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1280 {
1281 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1282
1283 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1284 return;
1285
1286 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1287 radv_emit_viewport(cmd_buffer);
1288
1289 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1290 radv_emit_scissor(cmd_buffer);
1291
1292 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH) {
1293 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1294 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1295 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1296 }
1297
1298 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
1299 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1300 radeon_emit_array(cmd_buffer->cs, (uint32_t*)d->blend_constants, 4);
1301 }
1302
1303 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1304 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1305 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK)) {
1306 radeon_set_context_reg_seq(cmd_buffer->cs, R_028430_DB_STENCILREFMASK, 2);
1307 radeon_emit(cmd_buffer->cs, S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1308 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1309 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1310 S_028430_STENCILOPVAL(1));
1311 radeon_emit(cmd_buffer->cs, S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1312 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1313 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1314 S_028434_STENCILOPVAL_BF(1));
1315 }
1316
1317 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1318 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) {
1319 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, fui(d->depth_bounds.min));
1320 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX, fui(d->depth_bounds.max));
1321 }
1322
1323 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1324 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
1325 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1326 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1327 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1328
1329 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1330 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1331 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1332 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1333 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1334 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1335 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1336 }
1337 }
1338
1339 cmd_buffer->state.dirty = 0;
1340 }
1341
1342 static void
1343 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1344 struct radv_pipeline *pipeline,
1345 int idx,
1346 uint64_t va,
1347 gl_shader_stage stage)
1348 {
1349 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1350 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
1351
1352 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1353 return;
1354
1355 assert(!desc_set_loc->indirect);
1356 assert(desc_set_loc->num_sgprs == 2);
1357 radeon_set_sh_reg_seq(cmd_buffer->cs,
1358 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1359 radeon_emit(cmd_buffer->cs, va);
1360 radeon_emit(cmd_buffer->cs, va >> 32);
1361 }
1362
1363 static void
1364 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1365 VkShaderStageFlags stages,
1366 struct radv_descriptor_set *set,
1367 unsigned idx)
1368 {
1369 if (cmd_buffer->state.pipeline) {
1370 radv_foreach_stage(stage, stages) {
1371 if (cmd_buffer->state.pipeline->shaders[stage])
1372 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1373 idx, set->va,
1374 stage);
1375 }
1376 }
1377
1378 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1379 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1380 idx, set->va,
1381 MESA_SHADER_COMPUTE);
1382 }
1383
1384 static void
1385 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1386 {
1387 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1388 uint32_t *ptr = NULL;
1389 unsigned bo_offset;
1390
1391 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, set->size, 32,
1392 &bo_offset,
1393 (void**) &ptr))
1394 return;
1395
1396 set->va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1397 set->va += bo_offset;
1398
1399 memcpy(ptr, set->mapped_ptr, set->size);
1400 }
1401
1402 static void
1403 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1404 {
1405 uint32_t size = MAX_SETS * 2 * 4;
1406 uint32_t offset;
1407 void *ptr;
1408
1409 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1410 256, &offset, &ptr))
1411 return;
1412
1413 for (unsigned i = 0; i < MAX_SETS; i++) {
1414 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1415 uint64_t set_va = 0;
1416 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1417 if (set)
1418 set_va = set->va;
1419 uptr[0] = set_va & 0xffffffff;
1420 uptr[1] = set_va >> 32;
1421 }
1422
1423 uint64_t va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1424 va += offset;
1425
1426 if (cmd_buffer->state.pipeline) {
1427 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1428 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1429 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1430
1431 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1432 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1433 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1434
1435 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1436 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1437 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1438
1439 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1440 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1441 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1442
1443 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1444 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1445 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1446 }
1447
1448 if (cmd_buffer->state.compute_pipeline)
1449 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1450 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1451 }
1452
1453 static void
1454 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1455 VkShaderStageFlags stages)
1456 {
1457 unsigned i;
1458
1459 if (!cmd_buffer->state.descriptors_dirty)
1460 return;
1461
1462 if (cmd_buffer->state.push_descriptors_dirty)
1463 radv_flush_push_descriptors(cmd_buffer);
1464
1465 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1466 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1467 radv_flush_indirect_descriptor_sets(cmd_buffer);
1468 }
1469
1470 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1471 cmd_buffer->cs,
1472 MAX_SETS * MESA_SHADER_STAGES * 4);
1473
1474 for (i = 0; i < MAX_SETS; i++) {
1475 if (!(cmd_buffer->state.descriptors_dirty & (1u << i)))
1476 continue;
1477 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1478 if (!set)
1479 continue;
1480
1481 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1482 }
1483 cmd_buffer->state.descriptors_dirty = 0;
1484 cmd_buffer->state.push_descriptors_dirty = false;
1485 assert(cmd_buffer->cs->cdw <= cdw_max);
1486 }
1487
1488 static void
1489 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1490 struct radv_pipeline *pipeline,
1491 VkShaderStageFlags stages)
1492 {
1493 struct radv_pipeline_layout *layout = pipeline->layout;
1494 unsigned offset;
1495 void *ptr;
1496 uint64_t va;
1497
1498 stages &= cmd_buffer->push_constant_stages;
1499 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1500 return;
1501
1502 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1503 16 * layout->dynamic_offset_count,
1504 256, &offset, &ptr))
1505 return;
1506
1507 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1508 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1509 16 * layout->dynamic_offset_count);
1510
1511 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1512 va += offset;
1513
1514 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1515 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1516
1517 radv_foreach_stage(stage, stages) {
1518 if (pipeline->shaders[stage]) {
1519 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1520 AC_UD_PUSH_CONSTANTS, va);
1521 }
1522 }
1523
1524 cmd_buffer->push_constant_stages &= ~stages;
1525 assert(cmd_buffer->cs->cdw <= cdw_max);
1526 }
1527
1528 static void radv_emit_primitive_reset_state(struct radv_cmd_buffer *cmd_buffer,
1529 bool indexed_draw)
1530 {
1531 int32_t primitive_reset_en = indexed_draw && cmd_buffer->state.pipeline->graphics.prim_restart_enable;
1532
1533 if (primitive_reset_en != cmd_buffer->state.last_primitive_reset_en) {
1534 cmd_buffer->state.last_primitive_reset_en = primitive_reset_en;
1535 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1536 radeon_set_uconfig_reg(cmd_buffer->cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1537 primitive_reset_en);
1538 } else {
1539 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1540 primitive_reset_en);
1541 }
1542 }
1543
1544 if (primitive_reset_en) {
1545 uint32_t primitive_reset_index = cmd_buffer->state.index_type ? 0xffffffffu : 0xffffu;
1546
1547 if (primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
1548 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
1549 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1550 primitive_reset_index);
1551 }
1552 }
1553 }
1554
1555 static bool
1556 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer)
1557 {
1558 struct radv_device *device = cmd_buffer->device;
1559
1560 if ((cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline || cmd_buffer->state.vb_dirty) &&
1561 cmd_buffer->state.pipeline->vertex_elements.count &&
1562 cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.has_vertex_buffers) {
1563 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1564 unsigned vb_offset;
1565 void *vb_ptr;
1566 uint32_t i = 0;
1567 uint32_t count = velems->count;
1568 uint64_t va;
1569
1570 /* allocate some descriptor state for vertex buffers */
1571 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1572 &vb_offset, &vb_ptr))
1573 return false;
1574
1575 for (i = 0; i < count; i++) {
1576 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1577 uint32_t offset;
1578 int vb = velems->binding[i];
1579 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1580 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1581
1582 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1583 va = device->ws->buffer_get_va(buffer->bo);
1584
1585 offset = cmd_buffer->state.vertex_bindings[vb].offset + velems->offset[i];
1586 va += offset + buffer->offset;
1587 desc[0] = va;
1588 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1589 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1590 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1591 else
1592 desc[2] = buffer->size - offset;
1593 desc[3] = velems->rsrc_word3[i];
1594 }
1595
1596 va = device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1597 va += vb_offset;
1598
1599 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1600 AC_UD_VS_VERTEX_BUFFERS, va);
1601 }
1602 cmd_buffer->state.vb_dirty = false;
1603
1604 return true;
1605 }
1606
1607 static void
1608 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer,
1609 bool indexed_draw, bool instanced_draw,
1610 bool indirect_draw,
1611 uint32_t draw_vertex_count)
1612 {
1613 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1614 uint32_t ia_multi_vgt_param;
1615
1616 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1617 cmd_buffer->cs, 4096);
1618
1619 if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer))
1620 return;
1621
1622 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1623 radv_emit_graphics_pipeline(cmd_buffer, pipeline);
1624
1625 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1626 radv_emit_framebuffer_state(cmd_buffer);
1627
1628 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, draw_vertex_count);
1629 if (cmd_buffer->state.last_ia_multi_vgt_param != ia_multi_vgt_param) {
1630 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1631 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
1632 else if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
1633 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1634 else
1635 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1636 cmd_buffer->state.last_ia_multi_vgt_param = ia_multi_vgt_param;
1637 }
1638
1639 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1640
1641 radv_emit_primitive_reset_state(cmd_buffer, indexed_draw);
1642
1643 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1644 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1645 VK_SHADER_STAGE_ALL_GRAPHICS);
1646
1647 assert(cmd_buffer->cs->cdw <= cdw_max);
1648
1649 si_emit_cache_flush(cmd_buffer);
1650 }
1651
1652 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1653 VkPipelineStageFlags src_stage_mask)
1654 {
1655 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1656 VK_PIPELINE_STAGE_TRANSFER_BIT |
1657 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1658 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1659 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1660 }
1661
1662 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1663 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1664 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1665 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1666 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1667 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1668 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1669 VK_PIPELINE_STAGE_TRANSFER_BIT |
1670 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1671 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1672 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1673 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1674 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1675 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1676 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1677 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1678 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1679 }
1680 }
1681
1682 static enum radv_cmd_flush_bits
1683 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1684 VkAccessFlags src_flags)
1685 {
1686 enum radv_cmd_flush_bits flush_bits = 0;
1687 uint32_t b;
1688 for_each_bit(b, src_flags) {
1689 switch ((VkAccessFlagBits)(1 << b)) {
1690 case VK_ACCESS_SHADER_WRITE_BIT:
1691 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1692 break;
1693 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1694 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1695 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1696 break;
1697 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1698 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1699 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1700 break;
1701 case VK_ACCESS_TRANSFER_WRITE_BIT:
1702 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1703 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1704 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1705 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1706 RADV_CMD_FLAG_INV_GLOBAL_L2;
1707 break;
1708 default:
1709 break;
1710 }
1711 }
1712 return flush_bits;
1713 }
1714
1715 static enum radv_cmd_flush_bits
1716 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1717 VkAccessFlags dst_flags,
1718 struct radv_image *image)
1719 {
1720 enum radv_cmd_flush_bits flush_bits = 0;
1721 uint32_t b;
1722 for_each_bit(b, dst_flags) {
1723 switch ((VkAccessFlagBits)(1 << b)) {
1724 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1725 case VK_ACCESS_INDEX_READ_BIT:
1726 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1727 break;
1728 case VK_ACCESS_UNIFORM_READ_BIT:
1729 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1730 break;
1731 case VK_ACCESS_SHADER_READ_BIT:
1732 case VK_ACCESS_TRANSFER_READ_BIT:
1733 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1734 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1735 RADV_CMD_FLAG_INV_GLOBAL_L2;
1736 break;
1737 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1738 /* TODO: change to image && when the image gets passed
1739 * through from the subpass. */
1740 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1741 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1742 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1743 break;
1744 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1745 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1746 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1747 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1748 break;
1749 default:
1750 break;
1751 }
1752 }
1753 return flush_bits;
1754 }
1755
1756 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1757 {
1758 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1759 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1760 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1761 NULL);
1762 }
1763
1764 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1765 VkAttachmentReference att)
1766 {
1767 unsigned idx = att.attachment;
1768 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1769 VkImageSubresourceRange range;
1770 range.aspectMask = 0;
1771 range.baseMipLevel = view->base_mip;
1772 range.levelCount = 1;
1773 range.baseArrayLayer = view->base_layer;
1774 range.layerCount = cmd_buffer->state.framebuffer->layers;
1775
1776 radv_handle_image_transition(cmd_buffer,
1777 view->image,
1778 cmd_buffer->state.attachments[idx].current_layout,
1779 att.layout, 0, 0, &range,
1780 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1781
1782 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1783
1784
1785 }
1786
1787 void
1788 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1789 const struct radv_subpass *subpass, bool transitions)
1790 {
1791 if (transitions) {
1792 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1793
1794 for (unsigned i = 0; i < subpass->color_count; ++i) {
1795 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
1796 radv_handle_subpass_image_transition(cmd_buffer,
1797 subpass->color_attachments[i]);
1798 }
1799
1800 for (unsigned i = 0; i < subpass->input_count; ++i) {
1801 radv_handle_subpass_image_transition(cmd_buffer,
1802 subpass->input_attachments[i]);
1803 }
1804
1805 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1806 radv_handle_subpass_image_transition(cmd_buffer,
1807 subpass->depth_stencil_attachment);
1808 }
1809 }
1810
1811 cmd_buffer->state.subpass = subpass;
1812
1813 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1814 }
1815
1816 static VkResult
1817 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1818 struct radv_render_pass *pass,
1819 const VkRenderPassBeginInfo *info)
1820 {
1821 struct radv_cmd_state *state = &cmd_buffer->state;
1822
1823 if (pass->attachment_count == 0) {
1824 state->attachments = NULL;
1825 return VK_SUCCESS;
1826 }
1827
1828 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1829 pass->attachment_count *
1830 sizeof(state->attachments[0]),
1831 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1832 if (state->attachments == NULL) {
1833 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
1834 return cmd_buffer->record_result;
1835 }
1836
1837 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1838 struct radv_render_pass_attachment *att = &pass->attachments[i];
1839 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1840 VkImageAspectFlags clear_aspects = 0;
1841
1842 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1843 /* color attachment */
1844 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1845 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1846 }
1847 } else {
1848 /* depthstencil attachment */
1849 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1850 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1851 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1852 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1853 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
1854 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1855 }
1856 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1857 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1858 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1859 }
1860 }
1861
1862 state->attachments[i].pending_clear_aspects = clear_aspects;
1863 state->attachments[i].cleared_views = 0;
1864 if (clear_aspects && info) {
1865 assert(info->clearValueCount > i);
1866 state->attachments[i].clear_value = info->pClearValues[i];
1867 }
1868
1869 state->attachments[i].current_layout = att->initial_layout;
1870 }
1871
1872 return VK_SUCCESS;
1873 }
1874
1875 VkResult radv_AllocateCommandBuffers(
1876 VkDevice _device,
1877 const VkCommandBufferAllocateInfo *pAllocateInfo,
1878 VkCommandBuffer *pCommandBuffers)
1879 {
1880 RADV_FROM_HANDLE(radv_device, device, _device);
1881 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1882
1883 VkResult result = VK_SUCCESS;
1884 uint32_t i;
1885
1886 memset(pCommandBuffers, 0,
1887 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
1888
1889 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1890
1891 if (!list_empty(&pool->free_cmd_buffers)) {
1892 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1893
1894 list_del(&cmd_buffer->pool_link);
1895 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1896
1897 radv_reset_cmd_buffer(cmd_buffer);
1898 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1899 cmd_buffer->level = pAllocateInfo->level;
1900
1901 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
1902 result = VK_SUCCESS;
1903 } else {
1904 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1905 &pCommandBuffers[i]);
1906 }
1907 if (result != VK_SUCCESS)
1908 break;
1909 }
1910
1911 if (result != VK_SUCCESS)
1912 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1913 i, pCommandBuffers);
1914
1915 return result;
1916 }
1917
1918 void radv_FreeCommandBuffers(
1919 VkDevice device,
1920 VkCommandPool commandPool,
1921 uint32_t commandBufferCount,
1922 const VkCommandBuffer *pCommandBuffers)
1923 {
1924 for (uint32_t i = 0; i < commandBufferCount; i++) {
1925 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1926
1927 if (cmd_buffer) {
1928 if (cmd_buffer->pool) {
1929 list_del(&cmd_buffer->pool_link);
1930 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
1931 } else
1932 radv_cmd_buffer_destroy(cmd_buffer);
1933
1934 }
1935 }
1936 }
1937
1938 VkResult radv_ResetCommandBuffer(
1939 VkCommandBuffer commandBuffer,
1940 VkCommandBufferResetFlags flags)
1941 {
1942 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1943 radv_reset_cmd_buffer(cmd_buffer);
1944 return VK_SUCCESS;
1945 }
1946
1947 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
1948 {
1949 struct radv_device *device = cmd_buffer->device;
1950 if (device->gfx_init) {
1951 uint64_t va = device->ws->buffer_get_va(device->gfx_init);
1952 device->ws->cs_add_buffer(cmd_buffer->cs, device->gfx_init, 8);
1953 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
1954 radeon_emit(cmd_buffer->cs, va);
1955 radeon_emit(cmd_buffer->cs, va >> 32);
1956 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
1957 } else
1958 si_init_config(cmd_buffer);
1959 }
1960
1961 VkResult radv_BeginCommandBuffer(
1962 VkCommandBuffer commandBuffer,
1963 const VkCommandBufferBeginInfo *pBeginInfo)
1964 {
1965 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1966 VkResult result = VK_SUCCESS;
1967
1968 radv_reset_cmd_buffer(cmd_buffer);
1969
1970 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1971 cmd_buffer->state.last_primitive_reset_en = -1;
1972 cmd_buffer->usage_flags = pBeginInfo->flags;
1973
1974 /* setup initial configuration into command buffer */
1975 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1976 switch (cmd_buffer->queue_family_index) {
1977 case RADV_QUEUE_GENERAL:
1978 emit_gfx_buffer_state(cmd_buffer);
1979 radv_set_db_count_control(cmd_buffer);
1980 break;
1981 case RADV_QUEUE_COMPUTE:
1982 si_init_compute(cmd_buffer);
1983 break;
1984 case RADV_QUEUE_TRANSFER:
1985 default:
1986 break;
1987 }
1988 }
1989
1990 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1991 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1992 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1993
1994 struct radv_subpass *subpass =
1995 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1996
1997 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1998 if (result != VK_SUCCESS)
1999 return result;
2000
2001 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2002 }
2003
2004 radv_cmd_buffer_trace_emit(cmd_buffer);
2005 return result;
2006 }
2007
2008 void radv_CmdBindVertexBuffers(
2009 VkCommandBuffer commandBuffer,
2010 uint32_t firstBinding,
2011 uint32_t bindingCount,
2012 const VkBuffer* pBuffers,
2013 const VkDeviceSize* pOffsets)
2014 {
2015 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2016 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
2017
2018 /* We have to defer setting up vertex buffer since we need the buffer
2019 * stride from the pipeline. */
2020
2021 assert(firstBinding + bindingCount <= MAX_VBS);
2022 for (uint32_t i = 0; i < bindingCount; i++) {
2023 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
2024 vb[firstBinding + i].offset = pOffsets[i];
2025 }
2026
2027 cmd_buffer->state.vb_dirty = true;
2028 }
2029
2030 void radv_CmdBindIndexBuffer(
2031 VkCommandBuffer commandBuffer,
2032 VkBuffer buffer,
2033 VkDeviceSize offset,
2034 VkIndexType indexType)
2035 {
2036 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2037 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2038
2039 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2040 cmd_buffer->state.index_va = cmd_buffer->device->ws->buffer_get_va(index_buffer->bo);
2041 cmd_buffer->state.index_va += index_buffer->offset + offset;
2042
2043 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2044 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2045 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2046 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, index_buffer->bo, 8);
2047 }
2048
2049
2050 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2051 struct radv_descriptor_set *set,
2052 unsigned idx)
2053 {
2054 struct radeon_winsys *ws = cmd_buffer->device->ws;
2055
2056 cmd_buffer->state.descriptors[idx] = set;
2057 cmd_buffer->state.descriptors_dirty |= (1u << idx);
2058 if (!set)
2059 return;
2060
2061 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2062
2063 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2064 if (set->descriptors[j])
2065 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
2066
2067 if(set->bo)
2068 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
2069 }
2070
2071 void radv_CmdBindDescriptorSets(
2072 VkCommandBuffer commandBuffer,
2073 VkPipelineBindPoint pipelineBindPoint,
2074 VkPipelineLayout _layout,
2075 uint32_t firstSet,
2076 uint32_t descriptorSetCount,
2077 const VkDescriptorSet* pDescriptorSets,
2078 uint32_t dynamicOffsetCount,
2079 const uint32_t* pDynamicOffsets)
2080 {
2081 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2082 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2083 unsigned dyn_idx = 0;
2084
2085 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2086 unsigned idx = i + firstSet;
2087 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2088 radv_bind_descriptor_set(cmd_buffer, set, idx);
2089
2090 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2091 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2092 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2093 assert(dyn_idx < dynamicOffsetCount);
2094
2095 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2096 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2097 dst[0] = va;
2098 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2099 dst[2] = range->size;
2100 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2101 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2102 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2103 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2104 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2105 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2106 cmd_buffer->push_constant_stages |=
2107 set->layout->dynamic_shader_stages;
2108 }
2109 }
2110 }
2111
2112 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2113 struct radv_descriptor_set *set,
2114 struct radv_descriptor_set_layout *layout)
2115 {
2116 set->size = layout->size;
2117 set->layout = layout;
2118
2119 if (cmd_buffer->push_descriptors.capacity < set->size) {
2120 size_t new_size = MAX2(set->size, 1024);
2121 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2122 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2123
2124 free(set->mapped_ptr);
2125 set->mapped_ptr = malloc(new_size);
2126
2127 if (!set->mapped_ptr) {
2128 cmd_buffer->push_descriptors.capacity = 0;
2129 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2130 return false;
2131 }
2132
2133 cmd_buffer->push_descriptors.capacity = new_size;
2134 }
2135
2136 return true;
2137 }
2138
2139 void radv_meta_push_descriptor_set(
2140 struct radv_cmd_buffer* cmd_buffer,
2141 VkPipelineBindPoint pipelineBindPoint,
2142 VkPipelineLayout _layout,
2143 uint32_t set,
2144 uint32_t descriptorWriteCount,
2145 const VkWriteDescriptorSet* pDescriptorWrites)
2146 {
2147 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2148 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2149 unsigned bo_offset;
2150
2151 assert(set == 0);
2152 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2153
2154 push_set->size = layout->set[set].layout->size;
2155 push_set->layout = layout->set[set].layout;
2156
2157 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2158 &bo_offset,
2159 (void**) &push_set->mapped_ptr))
2160 return;
2161
2162 push_set->va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
2163 push_set->va += bo_offset;
2164
2165 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2166 radv_descriptor_set_to_handle(push_set),
2167 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2168
2169 cmd_buffer->state.descriptors[set] = push_set;
2170 cmd_buffer->state.descriptors_dirty |= (1u << set);
2171 }
2172
2173 void radv_CmdPushDescriptorSetKHR(
2174 VkCommandBuffer commandBuffer,
2175 VkPipelineBindPoint pipelineBindPoint,
2176 VkPipelineLayout _layout,
2177 uint32_t set,
2178 uint32_t descriptorWriteCount,
2179 const VkWriteDescriptorSet* pDescriptorWrites)
2180 {
2181 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2182 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2183 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2184
2185 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2186
2187 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2188 return;
2189
2190 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2191 radv_descriptor_set_to_handle(push_set),
2192 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2193
2194 cmd_buffer->state.descriptors[set] = push_set;
2195 cmd_buffer->state.descriptors_dirty |= (1u << set);
2196 cmd_buffer->state.push_descriptors_dirty = true;
2197 }
2198
2199 void radv_CmdPushDescriptorSetWithTemplateKHR(
2200 VkCommandBuffer commandBuffer,
2201 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2202 VkPipelineLayout _layout,
2203 uint32_t set,
2204 const void* pData)
2205 {
2206 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2207 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2208 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2209
2210 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2211
2212 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2213 return;
2214
2215 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2216 descriptorUpdateTemplate, pData);
2217
2218 cmd_buffer->state.descriptors[set] = push_set;
2219 cmd_buffer->state.descriptors_dirty |= (1u << set);
2220 cmd_buffer->state.push_descriptors_dirty = true;
2221 }
2222
2223 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2224 VkPipelineLayout layout,
2225 VkShaderStageFlags stageFlags,
2226 uint32_t offset,
2227 uint32_t size,
2228 const void* pValues)
2229 {
2230 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2231 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2232 cmd_buffer->push_constant_stages |= stageFlags;
2233 }
2234
2235 VkResult radv_EndCommandBuffer(
2236 VkCommandBuffer commandBuffer)
2237 {
2238 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2239
2240 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2241 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2242 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2243 si_emit_cache_flush(cmd_buffer);
2244 }
2245
2246 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2247 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2248
2249 return cmd_buffer->record_result;
2250 }
2251
2252 static void
2253 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2254 {
2255 struct radeon_winsys *ws = cmd_buffer->device->ws;
2256 struct radv_shader_variant *compute_shader;
2257 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2258 uint64_t va;
2259
2260 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2261 return;
2262
2263 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2264
2265 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2266 va = ws->buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
2267
2268 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
2269 radv_emit_prefetch(cmd_buffer, va, compute_shader->code_size);
2270
2271 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2272 cmd_buffer->cs, 16);
2273
2274 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2275 radeon_emit(cmd_buffer->cs, va >> 8);
2276 radeon_emit(cmd_buffer->cs, va >> 40);
2277
2278 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2279 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2280 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2281
2282
2283 cmd_buffer->compute_scratch_size_needed =
2284 MAX2(cmd_buffer->compute_scratch_size_needed,
2285 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2286
2287 /* change these once we have scratch support */
2288 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2289 S_00B860_WAVES(pipeline->max_waves) |
2290 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2291
2292 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2293 radeon_emit(cmd_buffer->cs,
2294 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2295 radeon_emit(cmd_buffer->cs,
2296 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2297 radeon_emit(cmd_buffer->cs,
2298 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2299
2300 assert(cmd_buffer->cs->cdw <= cdw_max);
2301 }
2302
2303 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2304 {
2305 for (unsigned i = 0; i < MAX_SETS; i++) {
2306 if (cmd_buffer->state.descriptors[i])
2307 cmd_buffer->state.descriptors_dirty |= (1u << i);
2308 }
2309 }
2310
2311 void radv_CmdBindPipeline(
2312 VkCommandBuffer commandBuffer,
2313 VkPipelineBindPoint pipelineBindPoint,
2314 VkPipeline _pipeline)
2315 {
2316 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2317 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2318
2319 radv_mark_descriptor_sets_dirty(cmd_buffer);
2320
2321 switch (pipelineBindPoint) {
2322 case VK_PIPELINE_BIND_POINT_COMPUTE:
2323 cmd_buffer->state.compute_pipeline = pipeline;
2324 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2325 break;
2326 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2327 cmd_buffer->state.pipeline = pipeline;
2328 if (!pipeline)
2329 break;
2330
2331 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2332 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2333
2334 /* Apply the dynamic state from the pipeline */
2335 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
2336 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
2337 &pipeline->dynamic_state,
2338 pipeline->dynamic_state_mask);
2339
2340 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2341 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2342 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2343 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2344
2345 if (radv_pipeline_has_tess(pipeline))
2346 cmd_buffer->tess_rings_needed = true;
2347
2348 if (radv_pipeline_has_gs(pipeline)) {
2349 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2350 AC_UD_SCRATCH_RING_OFFSETS);
2351 if (cmd_buffer->ring_offsets_idx == -1)
2352 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2353 else if (loc->sgpr_idx != -1)
2354 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2355 }
2356 break;
2357 default:
2358 assert(!"invalid bind point");
2359 break;
2360 }
2361 }
2362
2363 void radv_CmdSetViewport(
2364 VkCommandBuffer commandBuffer,
2365 uint32_t firstViewport,
2366 uint32_t viewportCount,
2367 const VkViewport* pViewports)
2368 {
2369 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2370
2371 const uint32_t total_count = firstViewport + viewportCount;
2372 if (cmd_buffer->state.dynamic.viewport.count < total_count)
2373 cmd_buffer->state.dynamic.viewport.count = total_count;
2374
2375 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2376 pViewports, viewportCount * sizeof(*pViewports));
2377
2378 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2379 }
2380
2381 void radv_CmdSetScissor(
2382 VkCommandBuffer commandBuffer,
2383 uint32_t firstScissor,
2384 uint32_t scissorCount,
2385 const VkRect2D* pScissors)
2386 {
2387 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2388
2389 const uint32_t total_count = firstScissor + scissorCount;
2390 if (cmd_buffer->state.dynamic.scissor.count < total_count)
2391 cmd_buffer->state.dynamic.scissor.count = total_count;
2392
2393 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2394 pScissors, scissorCount * sizeof(*pScissors));
2395 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2396 }
2397
2398 void radv_CmdSetLineWidth(
2399 VkCommandBuffer commandBuffer,
2400 float lineWidth)
2401 {
2402 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2403 cmd_buffer->state.dynamic.line_width = lineWidth;
2404 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2405 }
2406
2407 void radv_CmdSetDepthBias(
2408 VkCommandBuffer commandBuffer,
2409 float depthBiasConstantFactor,
2410 float depthBiasClamp,
2411 float depthBiasSlopeFactor)
2412 {
2413 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2414
2415 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2416 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2417 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2418
2419 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2420 }
2421
2422 void radv_CmdSetBlendConstants(
2423 VkCommandBuffer commandBuffer,
2424 const float blendConstants[4])
2425 {
2426 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2427
2428 memcpy(cmd_buffer->state.dynamic.blend_constants,
2429 blendConstants, sizeof(float) * 4);
2430
2431 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2432 }
2433
2434 void radv_CmdSetDepthBounds(
2435 VkCommandBuffer commandBuffer,
2436 float minDepthBounds,
2437 float maxDepthBounds)
2438 {
2439 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2440
2441 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2442 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2443
2444 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2445 }
2446
2447 void radv_CmdSetStencilCompareMask(
2448 VkCommandBuffer commandBuffer,
2449 VkStencilFaceFlags faceMask,
2450 uint32_t compareMask)
2451 {
2452 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2453
2454 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2455 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2456 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2457 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2458
2459 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2460 }
2461
2462 void radv_CmdSetStencilWriteMask(
2463 VkCommandBuffer commandBuffer,
2464 VkStencilFaceFlags faceMask,
2465 uint32_t writeMask)
2466 {
2467 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2468
2469 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2470 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2471 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2472 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2473
2474 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2475 }
2476
2477 void radv_CmdSetStencilReference(
2478 VkCommandBuffer commandBuffer,
2479 VkStencilFaceFlags faceMask,
2480 uint32_t reference)
2481 {
2482 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2483
2484 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2485 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2486 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2487 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2488
2489 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2490 }
2491
2492 void radv_CmdExecuteCommands(
2493 VkCommandBuffer commandBuffer,
2494 uint32_t commandBufferCount,
2495 const VkCommandBuffer* pCmdBuffers)
2496 {
2497 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2498
2499 /* Emit pending flushes on primary prior to executing secondary */
2500 si_emit_cache_flush(primary);
2501
2502 for (uint32_t i = 0; i < commandBufferCount; i++) {
2503 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2504
2505 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2506 secondary->scratch_size_needed);
2507 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2508 secondary->compute_scratch_size_needed);
2509
2510 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2511 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2512 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2513 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2514 if (secondary->tess_rings_needed)
2515 primary->tess_rings_needed = true;
2516 if (secondary->sample_positions_needed)
2517 primary->sample_positions_needed = true;
2518
2519 if (secondary->ring_offsets_idx != -1) {
2520 if (primary->ring_offsets_idx == -1)
2521 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2522 else
2523 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2524 }
2525 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2526 }
2527
2528 /* if we execute secondary we need to re-emit out pipelines */
2529 if (commandBufferCount) {
2530 primary->state.emitted_pipeline = NULL;
2531 primary->state.emitted_compute_pipeline = NULL;
2532 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2533 primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
2534 primary->state.last_primitive_reset_en = -1;
2535 primary->state.last_primitive_reset_index = 0;
2536 radv_mark_descriptor_sets_dirty(primary);
2537 }
2538 }
2539
2540 VkResult radv_CreateCommandPool(
2541 VkDevice _device,
2542 const VkCommandPoolCreateInfo* pCreateInfo,
2543 const VkAllocationCallbacks* pAllocator,
2544 VkCommandPool* pCmdPool)
2545 {
2546 RADV_FROM_HANDLE(radv_device, device, _device);
2547 struct radv_cmd_pool *pool;
2548
2549 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2550 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2551 if (pool == NULL)
2552 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2553
2554 if (pAllocator)
2555 pool->alloc = *pAllocator;
2556 else
2557 pool->alloc = device->alloc;
2558
2559 list_inithead(&pool->cmd_buffers);
2560 list_inithead(&pool->free_cmd_buffers);
2561
2562 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2563
2564 *pCmdPool = radv_cmd_pool_to_handle(pool);
2565
2566 return VK_SUCCESS;
2567
2568 }
2569
2570 void radv_DestroyCommandPool(
2571 VkDevice _device,
2572 VkCommandPool commandPool,
2573 const VkAllocationCallbacks* pAllocator)
2574 {
2575 RADV_FROM_HANDLE(radv_device, device, _device);
2576 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2577
2578 if (!pool)
2579 return;
2580
2581 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2582 &pool->cmd_buffers, pool_link) {
2583 radv_cmd_buffer_destroy(cmd_buffer);
2584 }
2585
2586 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2587 &pool->free_cmd_buffers, pool_link) {
2588 radv_cmd_buffer_destroy(cmd_buffer);
2589 }
2590
2591 vk_free2(&device->alloc, pAllocator, pool);
2592 }
2593
2594 VkResult radv_ResetCommandPool(
2595 VkDevice device,
2596 VkCommandPool commandPool,
2597 VkCommandPoolResetFlags flags)
2598 {
2599 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2600
2601 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2602 &pool->cmd_buffers, pool_link) {
2603 radv_reset_cmd_buffer(cmd_buffer);
2604 }
2605
2606 return VK_SUCCESS;
2607 }
2608
2609 void radv_TrimCommandPoolKHR(
2610 VkDevice device,
2611 VkCommandPool commandPool,
2612 VkCommandPoolTrimFlagsKHR flags)
2613 {
2614 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2615
2616 if (!pool)
2617 return;
2618
2619 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2620 &pool->free_cmd_buffers, pool_link) {
2621 radv_cmd_buffer_destroy(cmd_buffer);
2622 }
2623 }
2624
2625 void radv_CmdBeginRenderPass(
2626 VkCommandBuffer commandBuffer,
2627 const VkRenderPassBeginInfo* pRenderPassBegin,
2628 VkSubpassContents contents)
2629 {
2630 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2631 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2632 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2633
2634 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2635 cmd_buffer->cs, 2048);
2636 MAYBE_UNUSED VkResult result;
2637
2638 cmd_buffer->state.framebuffer = framebuffer;
2639 cmd_buffer->state.pass = pass;
2640 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2641 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2642 if (result != VK_SUCCESS)
2643 cmd_buffer->record_result = result;
2644
2645 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2646 assert(cmd_buffer->cs->cdw <= cdw_max);
2647
2648 radv_cmd_buffer_clear_subpass(cmd_buffer);
2649 }
2650
2651 void radv_CmdNextSubpass(
2652 VkCommandBuffer commandBuffer,
2653 VkSubpassContents contents)
2654 {
2655 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2656
2657 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2658
2659 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2660 2048);
2661
2662 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2663 radv_cmd_buffer_clear_subpass(cmd_buffer);
2664 }
2665
2666 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
2667 {
2668 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2669 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2670 if (!pipeline->shaders[stage])
2671 continue;
2672 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
2673 if (loc->sgpr_idx == -1)
2674 continue;
2675 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
2676 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2677
2678 }
2679 if (pipeline->gs_copy_shader) {
2680 struct ac_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
2681 if (loc->sgpr_idx != -1) {
2682 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2683 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2684 }
2685 }
2686 }
2687
2688 static void
2689 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2690 uint32_t vertex_count)
2691 {
2692 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
2693 radeon_emit(cmd_buffer->cs, vertex_count);
2694 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2695 S_0287F0_USE_OPAQUE(0));
2696 }
2697
2698 void radv_CmdDraw(
2699 VkCommandBuffer commandBuffer,
2700 uint32_t vertexCount,
2701 uint32_t instanceCount,
2702 uint32_t firstVertex,
2703 uint32_t firstInstance)
2704 {
2705 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2706
2707 radv_cmd_buffer_flush_state(cmd_buffer, false, (instanceCount > 1), false, vertexCount);
2708
2709 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 20 * MAX_VIEWS);
2710
2711 assert(cmd_buffer->state.pipeline->graphics.vtx_base_sgpr);
2712 radeon_set_sh_reg_seq(cmd_buffer->cs, cmd_buffer->state.pipeline->graphics.vtx_base_sgpr,
2713 cmd_buffer->state.pipeline->graphics.vtx_emit_num);
2714 radeon_emit(cmd_buffer->cs, firstVertex);
2715 radeon_emit(cmd_buffer->cs, firstInstance);
2716 if (cmd_buffer->state.pipeline->graphics.vtx_emit_num == 3)
2717 radeon_emit(cmd_buffer->cs, 0);
2718
2719 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, cmd_buffer->state.predicating));
2720 radeon_emit(cmd_buffer->cs, instanceCount);
2721
2722 if (!cmd_buffer->state.subpass->view_mask) {
2723 radv_cs_emit_draw_packet(cmd_buffer, vertexCount);
2724 } else {
2725 unsigned i;
2726 for_each_bit(i, cmd_buffer->state.subpass->view_mask) {
2727 radv_emit_view_index(cmd_buffer, i);
2728
2729 radv_cs_emit_draw_packet(cmd_buffer, vertexCount);
2730 }
2731 }
2732
2733 assert(cmd_buffer->cs->cdw <= cdw_max);
2734
2735 radv_cmd_buffer_trace_emit(cmd_buffer);
2736 }
2737
2738
2739 static void
2740 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
2741 uint64_t index_va,
2742 uint32_t index_count)
2743 {
2744 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2745 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2746 radeon_emit(cmd_buffer->cs, index_va);
2747 radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
2748 radeon_emit(cmd_buffer->cs, index_count);
2749 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2750 }
2751
2752 void radv_CmdDrawIndexed(
2753 VkCommandBuffer commandBuffer,
2754 uint32_t indexCount,
2755 uint32_t instanceCount,
2756 uint32_t firstIndex,
2757 int32_t vertexOffset,
2758 uint32_t firstInstance)
2759 {
2760 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2761 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2762 uint64_t index_va;
2763
2764 radv_cmd_buffer_flush_state(cmd_buffer, true, (instanceCount > 1), false, indexCount);
2765
2766 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 26 * MAX_VIEWS);
2767
2768 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2769 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_03090C_VGT_INDEX_TYPE,
2770 2, cmd_buffer->state.index_type);
2771 } else {
2772 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2773 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2774 }
2775
2776 assert(cmd_buffer->state.pipeline->graphics.vtx_base_sgpr);
2777 radeon_set_sh_reg_seq(cmd_buffer->cs, cmd_buffer->state.pipeline->graphics.vtx_base_sgpr,
2778 cmd_buffer->state.pipeline->graphics.vtx_emit_num);
2779 radeon_emit(cmd_buffer->cs, vertexOffset);
2780 radeon_emit(cmd_buffer->cs, firstInstance);
2781 if (cmd_buffer->state.pipeline->graphics.vtx_emit_num == 3)
2782 radeon_emit(cmd_buffer->cs, 0);
2783
2784 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2785 radeon_emit(cmd_buffer->cs, instanceCount);
2786
2787 index_va = cmd_buffer->state.index_va;
2788 index_va += firstIndex * index_size;
2789 if (!cmd_buffer->state.subpass->view_mask) {
2790 radv_cs_emit_draw_indexed_packet(cmd_buffer, index_va, indexCount);
2791 } else {
2792 unsigned i;
2793 for_each_bit(i, cmd_buffer->state.subpass->view_mask) {
2794 radv_emit_view_index(cmd_buffer, i);
2795
2796 radv_cs_emit_draw_indexed_packet(cmd_buffer, index_va, indexCount);
2797 }
2798 }
2799
2800 assert(cmd_buffer->cs->cdw <= cdw_max);
2801 radv_cmd_buffer_trace_emit(cmd_buffer);
2802 }
2803
2804 static void
2805 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2806 bool indexed,
2807 uint32_t draw_count,
2808 uint64_t count_va,
2809 uint32_t stride)
2810 {
2811 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2812 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2813 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2814 bool draw_id_enable = cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id;
2815 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
2816 assert(base_reg);
2817
2818 if (draw_count == 1 && !count_va && !draw_id_enable) {
2819 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
2820 PKT3_DRAW_INDIRECT, 3, false));
2821 radeon_emit(cs, 0);
2822 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2823 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2824 radeon_emit(cs, di_src_sel);
2825 } else {
2826 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2827 PKT3_DRAW_INDIRECT_MULTI,
2828 8, false));
2829 radeon_emit(cs, 0);
2830 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2831 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2832 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
2833 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
2834 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2835 radeon_emit(cs, draw_count); /* count */
2836 radeon_emit(cs, count_va); /* count_addr */
2837 radeon_emit(cs, count_va >> 32);
2838 radeon_emit(cs, stride); /* stride */
2839 radeon_emit(cs, di_src_sel);
2840 }
2841 }
2842
2843 static void
2844 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
2845 VkBuffer _buffer,
2846 VkDeviceSize offset,
2847 VkBuffer _count_buffer,
2848 VkDeviceSize count_offset,
2849 uint32_t draw_count,
2850 uint32_t stride,
2851 bool indexed)
2852 {
2853 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2854 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
2855 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2856
2857 uint64_t indirect_va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2858 indirect_va += offset + buffer->offset;
2859 uint64_t count_va = 0;
2860
2861 if (count_buffer) {
2862 count_va = cmd_buffer->device->ws->buffer_get_va(count_buffer->bo);
2863 count_va += count_offset + count_buffer->offset;
2864 }
2865
2866 if (!draw_count)
2867 return;
2868
2869 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
2870
2871 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2872 radeon_emit(cs, 1);
2873 radeon_emit(cs, indirect_va);
2874 radeon_emit(cs, indirect_va >> 32);
2875
2876 if (!cmd_buffer->state.subpass->view_mask) {
2877 radv_cs_emit_indirect_draw_packet(cmd_buffer, indexed, draw_count, count_va, stride);
2878 } else {
2879 unsigned i;
2880 for_each_bit(i, cmd_buffer->state.subpass->view_mask) {
2881 radv_emit_view_index(cmd_buffer, i);
2882
2883 radv_cs_emit_indirect_draw_packet(cmd_buffer, indexed, draw_count, count_va, stride);
2884 }
2885 }
2886 radv_cmd_buffer_trace_emit(cmd_buffer);
2887 }
2888
2889 static void
2890 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
2891 VkBuffer buffer,
2892 VkDeviceSize offset,
2893 VkBuffer countBuffer,
2894 VkDeviceSize countBufferOffset,
2895 uint32_t maxDrawCount,
2896 uint32_t stride)
2897 {
2898 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2899 radv_cmd_buffer_flush_state(cmd_buffer, false, false, true, 0);
2900
2901 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2902 cmd_buffer->cs, 24 * MAX_VIEWS);
2903
2904 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2905 countBuffer, countBufferOffset, maxDrawCount, stride, false);
2906
2907 assert(cmd_buffer->cs->cdw <= cdw_max);
2908 }
2909
2910 static void
2911 radv_cmd_draw_indexed_indirect_count(
2912 VkCommandBuffer commandBuffer,
2913 VkBuffer buffer,
2914 VkDeviceSize offset,
2915 VkBuffer countBuffer,
2916 VkDeviceSize countBufferOffset,
2917 uint32_t maxDrawCount,
2918 uint32_t stride)
2919 {
2920 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2921 uint64_t index_va;
2922 radv_cmd_buffer_flush_state(cmd_buffer, true, false, true, 0);
2923
2924 index_va = cmd_buffer->state.index_va;
2925
2926 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 31 * MAX_VIEWS);
2927
2928 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2929 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2930
2931 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2932 radeon_emit(cmd_buffer->cs, index_va);
2933 radeon_emit(cmd_buffer->cs, index_va >> 32);
2934
2935 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2936 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2937
2938 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2939 countBuffer, countBufferOffset, maxDrawCount, stride, true);
2940
2941 assert(cmd_buffer->cs->cdw <= cdw_max);
2942 }
2943
2944 void radv_CmdDrawIndirect(
2945 VkCommandBuffer commandBuffer,
2946 VkBuffer buffer,
2947 VkDeviceSize offset,
2948 uint32_t drawCount,
2949 uint32_t stride)
2950 {
2951 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2952 VK_NULL_HANDLE, 0, drawCount, stride);
2953 }
2954
2955 void radv_CmdDrawIndexedIndirect(
2956 VkCommandBuffer commandBuffer,
2957 VkBuffer buffer,
2958 VkDeviceSize offset,
2959 uint32_t drawCount,
2960 uint32_t stride)
2961 {
2962 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2963 VK_NULL_HANDLE, 0, drawCount, stride);
2964 }
2965
2966 void radv_CmdDrawIndirectCountAMD(
2967 VkCommandBuffer commandBuffer,
2968 VkBuffer buffer,
2969 VkDeviceSize offset,
2970 VkBuffer countBuffer,
2971 VkDeviceSize countBufferOffset,
2972 uint32_t maxDrawCount,
2973 uint32_t stride)
2974 {
2975 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2976 countBuffer, countBufferOffset,
2977 maxDrawCount, stride);
2978 }
2979
2980 void radv_CmdDrawIndexedIndirectCountAMD(
2981 VkCommandBuffer commandBuffer,
2982 VkBuffer buffer,
2983 VkDeviceSize offset,
2984 VkBuffer countBuffer,
2985 VkDeviceSize countBufferOffset,
2986 uint32_t maxDrawCount,
2987 uint32_t stride)
2988 {
2989 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2990 countBuffer, countBufferOffset,
2991 maxDrawCount, stride);
2992 }
2993
2994 static void
2995 radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
2996 {
2997 radv_emit_compute_pipeline(cmd_buffer);
2998 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
2999 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
3000 VK_SHADER_STAGE_COMPUTE_BIT);
3001 si_emit_cache_flush(cmd_buffer);
3002 }
3003
3004 void radv_CmdDispatch(
3005 VkCommandBuffer commandBuffer,
3006 uint32_t x,
3007 uint32_t y,
3008 uint32_t z)
3009 {
3010 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3011
3012 radv_flush_compute_state(cmd_buffer);
3013
3014 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
3015
3016 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
3017 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
3018 if (loc->sgpr_idx != -1) {
3019 assert(!loc->indirect);
3020 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
3021 assert(loc->num_sgprs == grid_used);
3022 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used);
3023 radeon_emit(cmd_buffer->cs, x);
3024 if (grid_used > 1)
3025 radeon_emit(cmd_buffer->cs, y);
3026 if (grid_used > 2)
3027 radeon_emit(cmd_buffer->cs, z);
3028 }
3029
3030 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3031 PKT3_SHADER_TYPE_S(1));
3032 radeon_emit(cmd_buffer->cs, x);
3033 radeon_emit(cmd_buffer->cs, y);
3034 radeon_emit(cmd_buffer->cs, z);
3035 radeon_emit(cmd_buffer->cs, 1);
3036
3037 assert(cmd_buffer->cs->cdw <= cdw_max);
3038 radv_cmd_buffer_trace_emit(cmd_buffer);
3039 }
3040
3041 void radv_CmdDispatchIndirect(
3042 VkCommandBuffer commandBuffer,
3043 VkBuffer _buffer,
3044 VkDeviceSize offset)
3045 {
3046 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3047 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3048 uint64_t va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
3049 va += buffer->offset + offset;
3050
3051 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
3052
3053 radv_flush_compute_state(cmd_buffer);
3054
3055 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 25);
3056 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
3057 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
3058 if (loc->sgpr_idx != -1) {
3059 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
3060 for (unsigned i = 0; i < grid_used; ++i) {
3061 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
3062 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3063 COPY_DATA_DST_SEL(COPY_DATA_REG));
3064 radeon_emit(cmd_buffer->cs, (va + 4 * i));
3065 radeon_emit(cmd_buffer->cs, (va + 4 * i) >> 32);
3066 radeon_emit(cmd_buffer->cs, ((R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4) >> 2) + i);
3067 radeon_emit(cmd_buffer->cs, 0);
3068 }
3069 }
3070
3071 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3072 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3073 PKT3_SHADER_TYPE_S(1));
3074 radeon_emit(cmd_buffer->cs, va);
3075 radeon_emit(cmd_buffer->cs, va >> 32);
3076 radeon_emit(cmd_buffer->cs, 1);
3077 } else {
3078 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_BASE, 2, 0) |
3079 PKT3_SHADER_TYPE_S(1));
3080 radeon_emit(cmd_buffer->cs, 1);
3081 radeon_emit(cmd_buffer->cs, va);
3082 radeon_emit(cmd_buffer->cs, va >> 32);
3083
3084 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3085 PKT3_SHADER_TYPE_S(1));
3086 radeon_emit(cmd_buffer->cs, 0);
3087 radeon_emit(cmd_buffer->cs, 1);
3088 }
3089
3090 assert(cmd_buffer->cs->cdw <= cdw_max);
3091 radv_cmd_buffer_trace_emit(cmd_buffer);
3092 }
3093
3094 void radv_unaligned_dispatch(
3095 struct radv_cmd_buffer *cmd_buffer,
3096 uint32_t x,
3097 uint32_t y,
3098 uint32_t z)
3099 {
3100 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3101 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3102 uint32_t blocks[3], remainder[3];
3103
3104 blocks[0] = round_up_u32(x, compute_shader->info.cs.block_size[0]);
3105 blocks[1] = round_up_u32(y, compute_shader->info.cs.block_size[1]);
3106 blocks[2] = round_up_u32(z, compute_shader->info.cs.block_size[2]);
3107
3108 /* If aligned, these should be an entire block size, not 0 */
3109 remainder[0] = x + compute_shader->info.cs.block_size[0] - align_u32_npot(x, compute_shader->info.cs.block_size[0]);
3110 remainder[1] = y + compute_shader->info.cs.block_size[1] - align_u32_npot(y, compute_shader->info.cs.block_size[1]);
3111 remainder[2] = z + compute_shader->info.cs.block_size[2] - align_u32_npot(z, compute_shader->info.cs.block_size[2]);
3112
3113 radv_flush_compute_state(cmd_buffer);
3114
3115 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
3116
3117 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3118 radeon_emit(cmd_buffer->cs,
3119 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]) |
3120 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3121 radeon_emit(cmd_buffer->cs,
3122 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]) |
3123 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3124 radeon_emit(cmd_buffer->cs,
3125 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]) |
3126 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3127
3128 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
3129 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
3130 if (loc->sgpr_idx != -1) {
3131 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
3132 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used);
3133 radeon_emit(cmd_buffer->cs, blocks[0]);
3134 if (grid_used > 1)
3135 radeon_emit(cmd_buffer->cs, blocks[1]);
3136 if (grid_used > 2)
3137 radeon_emit(cmd_buffer->cs, blocks[2]);
3138 }
3139 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3140 PKT3_SHADER_TYPE_S(1));
3141 radeon_emit(cmd_buffer->cs, blocks[0]);
3142 radeon_emit(cmd_buffer->cs, blocks[1]);
3143 radeon_emit(cmd_buffer->cs, blocks[2]);
3144 radeon_emit(cmd_buffer->cs, S_00B800_COMPUTE_SHADER_EN(1) |
3145 S_00B800_PARTIAL_TG_EN(1));
3146
3147 assert(cmd_buffer->cs->cdw <= cdw_max);
3148 radv_cmd_buffer_trace_emit(cmd_buffer);
3149 }
3150
3151 void radv_CmdEndRenderPass(
3152 VkCommandBuffer commandBuffer)
3153 {
3154 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3155
3156 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3157
3158 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3159
3160 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3161 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3162 radv_handle_subpass_image_transition(cmd_buffer,
3163 (VkAttachmentReference){i, layout});
3164 }
3165
3166 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3167
3168 cmd_buffer->state.pass = NULL;
3169 cmd_buffer->state.subpass = NULL;
3170 cmd_buffer->state.attachments = NULL;
3171 cmd_buffer->state.framebuffer = NULL;
3172 }
3173
3174 /*
3175 * For HTILE we have the following interesting clear words:
3176 * 0x0000030f: Uncompressed.
3177 * 0xfffffff0: Clear depth to 1.0
3178 * 0x00000000: Clear depth to 0.0
3179 */
3180 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3181 struct radv_image *image,
3182 const VkImageSubresourceRange *range,
3183 uint32_t clear_word)
3184 {
3185 assert(range->baseMipLevel == 0);
3186 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3187 unsigned layer_count = radv_get_layerCount(image, range);
3188 uint64_t size = image->surface.htile_slice_size * layer_count;
3189 uint64_t offset = image->offset + image->htile_offset +
3190 image->surface.htile_slice_size * range->baseArrayLayer;
3191
3192 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3193 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3194
3195 radv_fill_buffer(cmd_buffer, image->bo, offset, size, clear_word);
3196
3197 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
3198 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3199 RADV_CMD_FLAG_INV_VMEM_L1 |
3200 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3201 }
3202
3203 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3204 struct radv_image *image,
3205 VkImageLayout src_layout,
3206 VkImageLayout dst_layout,
3207 unsigned src_queue_mask,
3208 unsigned dst_queue_mask,
3209 const VkImageSubresourceRange *range,
3210 VkImageAspectFlags pending_clears)
3211 {
3212 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3213 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3214 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3215 cmd_buffer->state.render_area.extent.width == image->info.width &&
3216 cmd_buffer->state.render_area.extent.height == image->info.height) {
3217 /* The clear will initialize htile. */
3218 return;
3219 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3220 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3221 /* TODO: merge with the clear if applicable */
3222 radv_initialize_htile(cmd_buffer, image, range, 0);
3223 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3224 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3225 radv_initialize_htile(cmd_buffer, image, range, 0xffffffff);
3226 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3227 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3228 VkImageSubresourceRange local_range = *range;
3229 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3230 local_range.baseMipLevel = 0;
3231 local_range.levelCount = 1;
3232
3233 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3234 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3235
3236 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3237
3238 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3239 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3240 }
3241 }
3242
3243 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3244 struct radv_image *image, uint32_t value)
3245 {
3246 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3247 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3248
3249 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
3250 image->cmask.size, value);
3251
3252 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3253 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3254 RADV_CMD_FLAG_INV_VMEM_L1 |
3255 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3256 }
3257
3258 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3259 struct radv_image *image,
3260 VkImageLayout src_layout,
3261 VkImageLayout dst_layout,
3262 unsigned src_queue_mask,
3263 unsigned dst_queue_mask,
3264 const VkImageSubresourceRange *range,
3265 VkImageAspectFlags pending_clears)
3266 {
3267 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3268 if (image->fmask.size)
3269 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3270 else
3271 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3272 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3273 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3274 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3275 }
3276 }
3277
3278 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3279 struct radv_image *image, uint32_t value)
3280 {
3281
3282 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3283 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3284
3285 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
3286 image->surface.dcc_size, value);
3287
3288 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3289 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3290 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3291 RADV_CMD_FLAG_INV_VMEM_L1 |
3292 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3293 }
3294
3295 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3296 struct radv_image *image,
3297 VkImageLayout src_layout,
3298 VkImageLayout dst_layout,
3299 unsigned src_queue_mask,
3300 unsigned dst_queue_mask,
3301 const VkImageSubresourceRange *range,
3302 VkImageAspectFlags pending_clears)
3303 {
3304 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3305 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
3306 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3307 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3308 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3309 }
3310 }
3311
3312 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3313 struct radv_image *image,
3314 VkImageLayout src_layout,
3315 VkImageLayout dst_layout,
3316 uint32_t src_family,
3317 uint32_t dst_family,
3318 const VkImageSubresourceRange *range,
3319 VkImageAspectFlags pending_clears)
3320 {
3321 if (image->exclusive && src_family != dst_family) {
3322 /* This is an acquire or a release operation and there will be
3323 * a corresponding release/acquire. Do the transition in the
3324 * most flexible queue. */
3325
3326 assert(src_family == cmd_buffer->queue_family_index ||
3327 dst_family == cmd_buffer->queue_family_index);
3328
3329 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3330 return;
3331
3332 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3333 (src_family == RADV_QUEUE_GENERAL ||
3334 dst_family == RADV_QUEUE_GENERAL))
3335 return;
3336 }
3337
3338 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3339 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3340
3341 if (image->surface.htile_size)
3342 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3343 dst_layout, src_queue_mask,
3344 dst_queue_mask, range,
3345 pending_clears);
3346
3347 if (image->cmask.size)
3348 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3349 dst_layout, src_queue_mask,
3350 dst_queue_mask, range,
3351 pending_clears);
3352
3353 if (image->surface.dcc_size)
3354 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3355 dst_layout, src_queue_mask,
3356 dst_queue_mask, range,
3357 pending_clears);
3358 }
3359
3360 void radv_CmdPipelineBarrier(
3361 VkCommandBuffer commandBuffer,
3362 VkPipelineStageFlags srcStageMask,
3363 VkPipelineStageFlags destStageMask,
3364 VkBool32 byRegion,
3365 uint32_t memoryBarrierCount,
3366 const VkMemoryBarrier* pMemoryBarriers,
3367 uint32_t bufferMemoryBarrierCount,
3368 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3369 uint32_t imageMemoryBarrierCount,
3370 const VkImageMemoryBarrier* pImageMemoryBarriers)
3371 {
3372 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3373 enum radv_cmd_flush_bits src_flush_bits = 0;
3374 enum radv_cmd_flush_bits dst_flush_bits = 0;
3375
3376 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3377 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3378 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3379 NULL);
3380 }
3381
3382 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3383 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3384 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3385 NULL);
3386 }
3387
3388 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3389 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3390 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3391 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3392 image);
3393 }
3394
3395 radv_stage_flush(cmd_buffer, srcStageMask);
3396 cmd_buffer->state.flush_bits |= src_flush_bits;
3397
3398 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3399 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3400 radv_handle_image_transition(cmd_buffer, image,
3401 pImageMemoryBarriers[i].oldLayout,
3402 pImageMemoryBarriers[i].newLayout,
3403 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3404 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3405 &pImageMemoryBarriers[i].subresourceRange,
3406 0);
3407 }
3408
3409 cmd_buffer->state.flush_bits |= dst_flush_bits;
3410 }
3411
3412
3413 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3414 struct radv_event *event,
3415 VkPipelineStageFlags stageMask,
3416 unsigned value)
3417 {
3418 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3419 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3420
3421 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3422
3423 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3424
3425 /* TODO: this is overkill. Probably should figure something out from
3426 * the stage mask. */
3427
3428 si_cs_emit_write_event_eop(cs,
3429 cmd_buffer->state.predicating,
3430 cmd_buffer->device->physical_device->rad_info.chip_class,
3431 false,
3432 EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0,
3433 1, va, 2, value);
3434
3435 assert(cmd_buffer->cs->cdw <= cdw_max);
3436 }
3437
3438 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3439 VkEvent _event,
3440 VkPipelineStageFlags stageMask)
3441 {
3442 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3443 RADV_FROM_HANDLE(radv_event, event, _event);
3444
3445 write_event(cmd_buffer, event, stageMask, 1);
3446 }
3447
3448 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3449 VkEvent _event,
3450 VkPipelineStageFlags stageMask)
3451 {
3452 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3453 RADV_FROM_HANDLE(radv_event, event, _event);
3454
3455 write_event(cmd_buffer, event, stageMask, 0);
3456 }
3457
3458 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3459 uint32_t eventCount,
3460 const VkEvent* pEvents,
3461 VkPipelineStageFlags srcStageMask,
3462 VkPipelineStageFlags dstStageMask,
3463 uint32_t memoryBarrierCount,
3464 const VkMemoryBarrier* pMemoryBarriers,
3465 uint32_t bufferMemoryBarrierCount,
3466 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3467 uint32_t imageMemoryBarrierCount,
3468 const VkImageMemoryBarrier* pImageMemoryBarriers)
3469 {
3470 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3471 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3472
3473 for (unsigned i = 0; i < eventCount; ++i) {
3474 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3475 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3476
3477 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3478
3479 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3480
3481 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
3482 assert(cmd_buffer->cs->cdw <= cdw_max);
3483 }
3484
3485
3486 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3487 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3488
3489 radv_handle_image_transition(cmd_buffer, image,
3490 pImageMemoryBarriers[i].oldLayout,
3491 pImageMemoryBarriers[i].newLayout,
3492 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3493 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3494 &pImageMemoryBarriers[i].subresourceRange,
3495 0);
3496 }
3497
3498 /* TODO: figure out how to do memory barriers without waiting */
3499 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3500 RADV_CMD_FLAG_INV_GLOBAL_L2 |
3501 RADV_CMD_FLAG_INV_VMEM_L1 |
3502 RADV_CMD_FLAG_INV_SMEM_L1;
3503 }