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radv: emit {CB,DB}_RMI_L2_CACHE_CONTROL at framebuffer time
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 bool src_render_loop,
58 VkImageLayout dst_layout,
59 bool dst_render_loop,
60 uint32_t src_family,
61 uint32_t dst_family,
62 const VkImageSubresourceRange *range,
63 struct radv_sample_locations_state *sample_locs);
64
65 const struct radv_dynamic_state default_dynamic_state = {
66 .viewport = {
67 .count = 0,
68 },
69 .scissor = {
70 .count = 0,
71 },
72 .line_width = 1.0f,
73 .depth_bias = {
74 .bias = 0.0f,
75 .clamp = 0.0f,
76 .slope = 0.0f,
77 },
78 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
79 .depth_bounds = {
80 .min = 0.0f,
81 .max = 1.0f,
82 },
83 .stencil_compare_mask = {
84 .front = ~0u,
85 .back = ~0u,
86 },
87 .stencil_write_mask = {
88 .front = ~0u,
89 .back = ~0u,
90 },
91 .stencil_reference = {
92 .front = 0u,
93 .back = 0u,
94 },
95 .line_stipple = {
96 .factor = 0u,
97 .pattern = 0u,
98 },
99 .cull_mode = 0u,
100 .front_face = 0u,
101 .primitive_topology = 0u,
102 };
103
104 static void
105 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
106 const struct radv_dynamic_state *src)
107 {
108 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
109 uint32_t copy_mask = src->mask;
110 uint32_t dest_mask = 0;
111
112 dest->discard_rectangle.count = src->discard_rectangle.count;
113 dest->sample_location.count = src->sample_location.count;
114
115 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
116 if (dest->viewport.count != src->viewport.count) {
117 dest->viewport.count = src->viewport.count;
118 dest_mask |= RADV_DYNAMIC_VIEWPORT;
119 }
120
121 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
122 src->viewport.count * sizeof(VkViewport))) {
123 typed_memcpy(dest->viewport.viewports,
124 src->viewport.viewports,
125 src->viewport.count);
126 dest_mask |= RADV_DYNAMIC_VIEWPORT;
127 }
128 }
129
130 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
131 if (dest->scissor.count != src->scissor.count) {
132 dest->scissor.count = src->scissor.count;
133 dest_mask |= RADV_DYNAMIC_SCISSOR;
134 }
135
136 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
137 src->scissor.count * sizeof(VkRect2D))) {
138 typed_memcpy(dest->scissor.scissors,
139 src->scissor.scissors, src->scissor.count);
140 dest_mask |= RADV_DYNAMIC_SCISSOR;
141 }
142 }
143
144 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
145 if (dest->line_width != src->line_width) {
146 dest->line_width = src->line_width;
147 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
148 }
149 }
150
151 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
152 if (memcmp(&dest->depth_bias, &src->depth_bias,
153 sizeof(src->depth_bias))) {
154 dest->depth_bias = src->depth_bias;
155 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
156 }
157 }
158
159 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
160 if (memcmp(&dest->blend_constants, &src->blend_constants,
161 sizeof(src->blend_constants))) {
162 typed_memcpy(dest->blend_constants,
163 src->blend_constants, 4);
164 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
165 }
166 }
167
168 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
169 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
170 sizeof(src->depth_bounds))) {
171 dest->depth_bounds = src->depth_bounds;
172 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
173 }
174 }
175
176 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
177 if (memcmp(&dest->stencil_compare_mask,
178 &src->stencil_compare_mask,
179 sizeof(src->stencil_compare_mask))) {
180 dest->stencil_compare_mask = src->stencil_compare_mask;
181 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
182 }
183 }
184
185 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
186 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
187 sizeof(src->stencil_write_mask))) {
188 dest->stencil_write_mask = src->stencil_write_mask;
189 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
190 }
191 }
192
193 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
194 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
195 sizeof(src->stencil_reference))) {
196 dest->stencil_reference = src->stencil_reference;
197 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
198 }
199 }
200
201 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
202 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
203 src->discard_rectangle.count * sizeof(VkRect2D))) {
204 typed_memcpy(dest->discard_rectangle.rectangles,
205 src->discard_rectangle.rectangles,
206 src->discard_rectangle.count);
207 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
208 }
209 }
210
211 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
212 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
213 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
214 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
215 memcmp(&dest->sample_location.locations,
216 &src->sample_location.locations,
217 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
218 dest->sample_location.per_pixel = src->sample_location.per_pixel;
219 dest->sample_location.grid_size = src->sample_location.grid_size;
220 typed_memcpy(dest->sample_location.locations,
221 src->sample_location.locations,
222 src->sample_location.count);
223 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
224 }
225 }
226
227 if (copy_mask & RADV_DYNAMIC_LINE_STIPPLE) {
228 if (memcmp(&dest->line_stipple, &src->line_stipple,
229 sizeof(src->line_stipple))) {
230 dest->line_stipple = src->line_stipple;
231 dest_mask |= RADV_DYNAMIC_LINE_STIPPLE;
232 }
233 }
234
235 if (copy_mask & RADV_DYNAMIC_CULL_MODE) {
236 if (dest->cull_mode != src->cull_mode) {
237 dest->cull_mode = src->cull_mode;
238 dest_mask |= RADV_DYNAMIC_CULL_MODE;
239 }
240 }
241
242 if (copy_mask & RADV_DYNAMIC_FRONT_FACE) {
243 if (dest->front_face != src->front_face) {
244 dest->front_face = src->front_face;
245 dest_mask |= RADV_DYNAMIC_FRONT_FACE;
246 }
247 }
248
249 if (copy_mask & RADV_DYNAMIC_PRIMITIVE_TOPOLOGY) {
250 if (dest->primitive_topology != src->primitive_topology) {
251 dest->primitive_topology = src->primitive_topology;
252 dest_mask |= RADV_DYNAMIC_PRIMITIVE_TOPOLOGY;
253 }
254 }
255
256 if (copy_mask & RADV_DYNAMIC_DEPTH_TEST_ENABLE) {
257 if (dest->depth_test_enable != src->depth_test_enable) {
258 dest->depth_test_enable = src->depth_test_enable;
259 dest_mask |= RADV_DYNAMIC_DEPTH_TEST_ENABLE;
260 }
261 }
262
263 if (copy_mask & RADV_DYNAMIC_DEPTH_WRITE_ENABLE) {
264 if (dest->depth_write_enable != src->depth_write_enable) {
265 dest->depth_write_enable = src->depth_write_enable;
266 dest_mask |= RADV_DYNAMIC_DEPTH_WRITE_ENABLE;
267 }
268 }
269
270 if (copy_mask & RADV_DYNAMIC_DEPTH_COMPARE_OP) {
271 if (dest->depth_compare_op != src->depth_compare_op) {
272 dest->depth_compare_op = src->depth_compare_op;
273 dest_mask |= RADV_DYNAMIC_DEPTH_COMPARE_OP;
274 }
275 }
276
277 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE) {
278 if (dest->depth_bounds_test_enable != src->depth_bounds_test_enable) {
279 dest->depth_bounds_test_enable = src->depth_bounds_test_enable;
280 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE;
281 }
282 }
283
284 if (copy_mask & RADV_DYNAMIC_STENCIL_TEST_ENABLE) {
285 if (dest->stencil_test_enable != src->stencil_test_enable) {
286 dest->stencil_test_enable = src->stencil_test_enable;
287 dest_mask |= RADV_DYNAMIC_STENCIL_TEST_ENABLE;
288 }
289 }
290
291 if (copy_mask & RADV_DYNAMIC_STENCIL_OP) {
292 if (memcmp(&dest->stencil_op, &src->stencil_op,
293 sizeof(src->stencil_op))) {
294 dest->stencil_op = src->stencil_op;
295 dest_mask |= RADV_DYNAMIC_STENCIL_OP;
296 }
297 }
298
299 cmd_buffer->state.dirty |= dest_mask;
300 }
301
302 static void
303 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
304 struct radv_pipeline *pipeline)
305 {
306 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
307 struct radv_shader_info *info;
308
309 if (!pipeline->streamout_shader ||
310 cmd_buffer->device->physical_device->use_ngg_streamout)
311 return;
312
313 info = &pipeline->streamout_shader->info;
314 for (int i = 0; i < MAX_SO_BUFFERS; i++)
315 so->stride_in_dw[i] = info->so.strides[i];
316
317 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
318 }
319
320 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
321 {
322 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
323 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
324 }
325
326 enum ring_type radv_queue_family_to_ring(int f) {
327 switch (f) {
328 case RADV_QUEUE_GENERAL:
329 return RING_GFX;
330 case RADV_QUEUE_COMPUTE:
331 return RING_COMPUTE;
332 case RADV_QUEUE_TRANSFER:
333 return RING_DMA;
334 default:
335 unreachable("Unknown queue family");
336 }
337 }
338
339 static void
340 radv_destroy_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
341 {
342 list_del(&cmd_buffer->pool_link);
343
344 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
345 &cmd_buffer->upload.list, list) {
346 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
347 list_del(&up->list);
348 free(up);
349 }
350
351 if (cmd_buffer->upload.upload_bo)
352 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
353
354 if (cmd_buffer->cs)
355 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
356
357 for (unsigned i = 0; i < MAX_BIND_POINTS; i++)
358 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
359
360 vk_object_base_finish(&cmd_buffer->base);
361 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
362 }
363
364 static VkResult radv_create_cmd_buffer(
365 struct radv_device * device,
366 struct radv_cmd_pool * pool,
367 VkCommandBufferLevel level,
368 VkCommandBuffer* pCommandBuffer)
369 {
370 struct radv_cmd_buffer *cmd_buffer;
371 unsigned ring;
372 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
373 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
374 if (cmd_buffer == NULL)
375 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
376
377 vk_object_base_init(&device->vk, &cmd_buffer->base,
378 VK_OBJECT_TYPE_COMMAND_BUFFER);
379
380 cmd_buffer->device = device;
381 cmd_buffer->pool = pool;
382 cmd_buffer->level = level;
383
384 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
385 cmd_buffer->queue_family_index = pool->queue_family_index;
386
387 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
388
389 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
390 if (!cmd_buffer->cs) {
391 radv_destroy_cmd_buffer(cmd_buffer);
392 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
393 }
394
395 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
396
397 list_inithead(&cmd_buffer->upload.list);
398
399 return VK_SUCCESS;
400 }
401
402 static VkResult
403 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
404 {
405 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
406
407 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
408 &cmd_buffer->upload.list, list) {
409 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
410 list_del(&up->list);
411 free(up);
412 }
413
414 cmd_buffer->push_constant_stages = 0;
415 cmd_buffer->scratch_size_per_wave_needed = 0;
416 cmd_buffer->scratch_waves_wanted = 0;
417 cmd_buffer->compute_scratch_size_per_wave_needed = 0;
418 cmd_buffer->compute_scratch_waves_wanted = 0;
419 cmd_buffer->esgs_ring_size_needed = 0;
420 cmd_buffer->gsvs_ring_size_needed = 0;
421 cmd_buffer->tess_rings_needed = false;
422 cmd_buffer->gds_needed = false;
423 cmd_buffer->gds_oa_needed = false;
424 cmd_buffer->sample_positions_needed = false;
425
426 if (cmd_buffer->upload.upload_bo)
427 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
428 cmd_buffer->upload.upload_bo);
429 cmd_buffer->upload.offset = 0;
430
431 cmd_buffer->record_result = VK_SUCCESS;
432
433 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
434
435 for (unsigned i = 0; i < MAX_BIND_POINTS; i++) {
436 cmd_buffer->descriptors[i].dirty = 0;
437 cmd_buffer->descriptors[i].valid = 0;
438 cmd_buffer->descriptors[i].push_dirty = false;
439 }
440
441 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
442 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
443 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
444 unsigned fence_offset, eop_bug_offset;
445 void *fence_ptr;
446
447 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
448 &fence_ptr);
449
450 cmd_buffer->gfx9_fence_va =
451 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
452 cmd_buffer->gfx9_fence_va += fence_offset;
453
454 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
455 /* Allocate a buffer for the EOP bug on GFX9. */
456 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
457 &eop_bug_offset, &fence_ptr);
458 cmd_buffer->gfx9_eop_bug_va =
459 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
460 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
461 }
462 }
463
464 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
465
466 return cmd_buffer->record_result;
467 }
468
469 static bool
470 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
471 uint64_t min_needed)
472 {
473 uint64_t new_size;
474 struct radeon_winsys_bo *bo;
475 struct radv_cmd_buffer_upload *upload;
476 struct radv_device *device = cmd_buffer->device;
477
478 new_size = MAX2(min_needed, 16 * 1024);
479 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
480
481 bo = device->ws->buffer_create(device->ws,
482 new_size, 4096,
483 RADEON_DOMAIN_GTT,
484 RADEON_FLAG_CPU_ACCESS|
485 RADEON_FLAG_NO_INTERPROCESS_SHARING |
486 RADEON_FLAG_32BIT |
487 RADEON_FLAG_GTT_WC,
488 RADV_BO_PRIORITY_UPLOAD_BUFFER);
489
490 if (!bo) {
491 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
492 return false;
493 }
494
495 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
496 if (cmd_buffer->upload.upload_bo) {
497 upload = malloc(sizeof(*upload));
498
499 if (!upload) {
500 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
501 device->ws->buffer_destroy(bo);
502 return false;
503 }
504
505 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
506 list_add(&upload->list, &cmd_buffer->upload.list);
507 }
508
509 cmd_buffer->upload.upload_bo = bo;
510 cmd_buffer->upload.size = new_size;
511 cmd_buffer->upload.offset = 0;
512 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
513
514 if (!cmd_buffer->upload.map) {
515 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
516 return false;
517 }
518
519 return true;
520 }
521
522 bool
523 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
524 unsigned size,
525 unsigned alignment,
526 unsigned *out_offset,
527 void **ptr)
528 {
529 assert(util_is_power_of_two_nonzero(alignment));
530
531 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
532 if (offset + size > cmd_buffer->upload.size) {
533 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
534 return false;
535 offset = 0;
536 }
537
538 *out_offset = offset;
539 *ptr = cmd_buffer->upload.map + offset;
540
541 cmd_buffer->upload.offset = offset + size;
542 return true;
543 }
544
545 bool
546 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
547 unsigned size, unsigned alignment,
548 const void *data, unsigned *out_offset)
549 {
550 uint8_t *ptr;
551
552 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
553 out_offset, (void **)&ptr))
554 return false;
555
556 if (ptr)
557 memcpy(ptr, data, size);
558
559 return true;
560 }
561
562 static void
563 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
564 unsigned count, const uint32_t *data)
565 {
566 struct radeon_cmdbuf *cs = cmd_buffer->cs;
567
568 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
569
570 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
571 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
572 S_370_WR_CONFIRM(1) |
573 S_370_ENGINE_SEL(V_370_ME));
574 radeon_emit(cs, va);
575 radeon_emit(cs, va >> 32);
576 radeon_emit_array(cs, data, count);
577 }
578
579 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
580 {
581 struct radv_device *device = cmd_buffer->device;
582 struct radeon_cmdbuf *cs = cmd_buffer->cs;
583 uint64_t va;
584
585 va = radv_buffer_get_va(device->trace_bo);
586 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
587 va += 4;
588
589 ++cmd_buffer->state.trace_id;
590 radv_emit_write_data_packet(cmd_buffer, va, 1,
591 &cmd_buffer->state.trace_id);
592
593 radeon_check_space(cmd_buffer->device->ws, cs, 2);
594
595 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
596 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
597 }
598
599 static void
600 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
601 enum radv_cmd_flush_bits flags)
602 {
603 if (unlikely(cmd_buffer->device->thread_trace_bo)) {
604 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
605 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_THREAD_TRACE_MARKER) | EVENT_INDEX(0));
606 }
607
608 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
609 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
610 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
611
612 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
613
614 /* Force wait for graphics or compute engines to be idle. */
615 si_cs_emit_cache_flush(cmd_buffer->cs,
616 cmd_buffer->device->physical_device->rad_info.chip_class,
617 &cmd_buffer->gfx9_fence_idx,
618 cmd_buffer->gfx9_fence_va,
619 radv_cmd_buffer_uses_mec(cmd_buffer),
620 flags, cmd_buffer->gfx9_eop_bug_va);
621 }
622
623 if (unlikely(cmd_buffer->device->trace_bo))
624 radv_cmd_buffer_trace_emit(cmd_buffer);
625 }
626
627 static void
628 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
629 struct radv_pipeline *pipeline, enum ring_type ring)
630 {
631 struct radv_device *device = cmd_buffer->device;
632 uint32_t data[2];
633 uint64_t va;
634
635 va = radv_buffer_get_va(device->trace_bo);
636
637 switch (ring) {
638 case RING_GFX:
639 va += 8;
640 break;
641 case RING_COMPUTE:
642 va += 16;
643 break;
644 default:
645 assert(!"invalid ring type");
646 }
647
648 uint64_t pipeline_address = (uintptr_t)pipeline;
649 data[0] = pipeline_address;
650 data[1] = pipeline_address >> 32;
651
652 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
653 }
654
655 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
656 VkPipelineBindPoint bind_point,
657 struct radv_descriptor_set *set,
658 unsigned idx)
659 {
660 struct radv_descriptor_state *descriptors_state =
661 radv_get_descriptors_state(cmd_buffer, bind_point);
662
663 descriptors_state->sets[idx] = set;
664
665 descriptors_state->valid |= (1u << idx); /* active descriptors */
666 descriptors_state->dirty |= (1u << idx);
667 }
668
669 static void
670 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
671 VkPipelineBindPoint bind_point)
672 {
673 struct radv_descriptor_state *descriptors_state =
674 radv_get_descriptors_state(cmd_buffer, bind_point);
675 struct radv_device *device = cmd_buffer->device;
676 uint32_t data[MAX_SETS * 2] = {};
677 uint64_t va;
678 unsigned i;
679 va = radv_buffer_get_va(device->trace_bo) + 24;
680
681 for_each_bit(i, descriptors_state->valid) {
682 struct radv_descriptor_set *set = descriptors_state->sets[i];
683 data[i * 2] = (uint64_t)(uintptr_t)set;
684 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
685 }
686
687 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
688 }
689
690 struct radv_userdata_info *
691 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
692 gl_shader_stage stage,
693 int idx)
694 {
695 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
696 return &shader->info.user_sgprs_locs.shader_data[idx];
697 }
698
699 static void
700 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
701 struct radv_pipeline *pipeline,
702 gl_shader_stage stage,
703 int idx, uint64_t va)
704 {
705 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
706 uint32_t base_reg = pipeline->user_data_0[stage];
707 if (loc->sgpr_idx == -1)
708 return;
709
710 assert(loc->num_sgprs == 1);
711
712 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
713 base_reg + loc->sgpr_idx * 4, va, false);
714 }
715
716 static void
717 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
718 struct radv_pipeline *pipeline,
719 struct radv_descriptor_state *descriptors_state,
720 gl_shader_stage stage)
721 {
722 struct radv_device *device = cmd_buffer->device;
723 struct radeon_cmdbuf *cs = cmd_buffer->cs;
724 uint32_t sh_base = pipeline->user_data_0[stage];
725 struct radv_userdata_locations *locs =
726 &pipeline->shaders[stage]->info.user_sgprs_locs;
727 unsigned mask = locs->descriptor_sets_enabled;
728
729 mask &= descriptors_state->dirty & descriptors_state->valid;
730
731 while (mask) {
732 int start, count;
733
734 u_bit_scan_consecutive_range(&mask, &start, &count);
735
736 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
737 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
738
739 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
740 for (int i = 0; i < count; i++) {
741 struct radv_descriptor_set *set =
742 descriptors_state->sets[start + i];
743
744 radv_emit_shader_pointer_body(device, cs, set->va, true);
745 }
746 }
747 }
748
749 /**
750 * Convert the user sample locations to hardware sample locations (the values
751 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
752 */
753 static void
754 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
755 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
756 {
757 uint32_t x_offset = x % state->grid_size.width;
758 uint32_t y_offset = y % state->grid_size.height;
759 uint32_t num_samples = (uint32_t)state->per_pixel;
760 VkSampleLocationEXT *user_locs;
761 uint32_t pixel_offset;
762
763 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
764
765 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
766 user_locs = &state->locations[pixel_offset];
767
768 for (uint32_t i = 0; i < num_samples; i++) {
769 float shifted_pos_x = user_locs[i].x - 0.5;
770 float shifted_pos_y = user_locs[i].y - 0.5;
771
772 int32_t scaled_pos_x = floorf(shifted_pos_x * 16);
773 int32_t scaled_pos_y = floorf(shifted_pos_y * 16);
774
775 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
776 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
777 }
778 }
779
780 /**
781 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
782 * locations.
783 */
784 static void
785 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
786 uint32_t *sample_locs_pixel)
787 {
788 for (uint32_t i = 0; i < num_samples; i++) {
789 uint32_t sample_reg_idx = i / 4;
790 uint32_t sample_loc_idx = i % 4;
791 int32_t pos_x = sample_locs[i].x;
792 int32_t pos_y = sample_locs[i].y;
793
794 uint32_t shift_x = 8 * sample_loc_idx;
795 uint32_t shift_y = shift_x + 4;
796
797 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
798 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
799 }
800 }
801
802 /**
803 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
804 * sample locations.
805 */
806 static uint64_t
807 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
808 VkOffset2D *sample_locs,
809 uint32_t num_samples)
810 {
811 uint32_t centroid_priorities[num_samples];
812 uint32_t sample_mask = num_samples - 1;
813 uint32_t distances[num_samples];
814 uint64_t centroid_priority = 0;
815
816 /* Compute the distances from center for each sample. */
817 for (int i = 0; i < num_samples; i++) {
818 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
819 (sample_locs[i].y * sample_locs[i].y);
820 }
821
822 /* Compute the centroid priorities by looking at the distances array. */
823 for (int i = 0; i < num_samples; i++) {
824 uint32_t min_idx = 0;
825
826 for (int j = 1; j < num_samples; j++) {
827 if (distances[j] < distances[min_idx])
828 min_idx = j;
829 }
830
831 centroid_priorities[i] = min_idx;
832 distances[min_idx] = 0xffffffff;
833 }
834
835 /* Compute the final centroid priority. */
836 for (int i = 0; i < 8; i++) {
837 centroid_priority |=
838 centroid_priorities[i & sample_mask] << (i * 4);
839 }
840
841 return centroid_priority << 32 | centroid_priority;
842 }
843
844 /**
845 * Emit the sample locations that are specified with VK_EXT_sample_locations.
846 */
847 static void
848 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
849 {
850 struct radv_sample_locations_state *sample_location =
851 &cmd_buffer->state.dynamic.sample_location;
852 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
853 struct radeon_cmdbuf *cs = cmd_buffer->cs;
854 uint32_t sample_locs_pixel[4][2] = {};
855 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
856 uint32_t max_sample_dist = 0;
857 uint64_t centroid_priority;
858
859 if (!cmd_buffer->state.dynamic.sample_location.count)
860 return;
861
862 /* Convert the user sample locations to hardware sample locations. */
863 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
864 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
865 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
866 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
867
868 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
869 for (uint32_t i = 0; i < 4; i++) {
870 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
871 sample_locs_pixel[i]);
872 }
873
874 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
875 centroid_priority =
876 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
877 num_samples);
878
879 /* Compute the maximum sample distance from the specified locations. */
880 for (unsigned i = 0; i < 4; ++i) {
881 for (uint32_t j = 0; j < num_samples; j++) {
882 VkOffset2D offset = sample_locs[i][j];
883 max_sample_dist = MAX2(max_sample_dist,
884 MAX2(abs(offset.x), abs(offset.y)));
885 }
886 }
887
888 /* Emit the specified user sample locations. */
889 switch (num_samples) {
890 case 2:
891 case 4:
892 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
893 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
894 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
895 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
896 break;
897 case 8:
898 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
899 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
900 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
901 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
902 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
903 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
904 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
905 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
906 break;
907 default:
908 unreachable("invalid number of samples");
909 }
910
911 /* Emit the maximum sample distance and the centroid priority. */
912 radeon_set_context_reg_rmw(cs, R_028BE0_PA_SC_AA_CONFIG,
913 S_028BE0_MAX_SAMPLE_DIST(max_sample_dist),
914 ~C_028BE0_MAX_SAMPLE_DIST);
915
916 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
917 radeon_emit(cs, centroid_priority);
918 radeon_emit(cs, centroid_priority >> 32);
919
920 /* GFX9: Flush DFSM when the AA mode changes. */
921 if (cmd_buffer->device->dfsm_allowed) {
922 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
923 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
924 }
925
926 cmd_buffer->state.context_roll_without_scissor_emitted = true;
927 }
928
929 static void
930 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
931 struct radv_pipeline *pipeline,
932 gl_shader_stage stage,
933 int idx, int count, uint32_t *values)
934 {
935 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
936 uint32_t base_reg = pipeline->user_data_0[stage];
937 if (loc->sgpr_idx == -1)
938 return;
939
940 assert(loc->num_sgprs == count);
941
942 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
943 radeon_emit_array(cmd_buffer->cs, values, count);
944 }
945
946 static void
947 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
948 struct radv_pipeline *pipeline)
949 {
950 int num_samples = pipeline->graphics.ms.num_samples;
951 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
952
953 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.needs_sample_positions)
954 cmd_buffer->sample_positions_needed = true;
955
956 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
957 return;
958
959 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
960
961 cmd_buffer->state.context_roll_without_scissor_emitted = true;
962 }
963
964 static void
965 radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer,
966 struct radv_pipeline *pipeline)
967 {
968 const struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
969
970
971 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
972 return;
973
974 if (old_pipeline &&
975 old_pipeline->graphics.binning.pa_sc_binner_cntl_0 == pipeline->graphics.binning.pa_sc_binner_cntl_0 &&
976 old_pipeline->graphics.binning.db_dfsm_control == pipeline->graphics.binning.db_dfsm_control)
977 return;
978
979 bool binning_flush = false;
980 if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 ||
981 cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 ||
982 cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 ||
983 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
984 binning_flush = !old_pipeline ||
985 G_028C44_BINNING_MODE(old_pipeline->graphics.binning.pa_sc_binner_cntl_0) !=
986 G_028C44_BINNING_MODE(pipeline->graphics.binning.pa_sc_binner_cntl_0);
987 }
988
989 radeon_set_context_reg(cmd_buffer->cs, R_028C44_PA_SC_BINNER_CNTL_0,
990 pipeline->graphics.binning.pa_sc_binner_cntl_0 |
991 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush));
992
993 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
994 radeon_set_context_reg(cmd_buffer->cs, R_028038_DB_DFSM_CONTROL,
995 pipeline->graphics.binning.db_dfsm_control);
996 } else {
997 radeon_set_context_reg(cmd_buffer->cs, R_028060_DB_DFSM_CONTROL,
998 pipeline->graphics.binning.db_dfsm_control);
999 }
1000
1001 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1002 }
1003
1004
1005 static void
1006 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
1007 struct radv_shader_variant *shader)
1008 {
1009 uint64_t va;
1010
1011 if (!shader)
1012 return;
1013
1014 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
1015
1016 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
1017 }
1018
1019 static void
1020 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
1021 struct radv_pipeline *pipeline,
1022 bool vertex_stage_only)
1023 {
1024 struct radv_cmd_state *state = &cmd_buffer->state;
1025 uint32_t mask = state->prefetch_L2_mask;
1026
1027 if (vertex_stage_only) {
1028 /* Fast prefetch path for starting draws as soon as possible.
1029 */
1030 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
1031 RADV_PREFETCH_VBO_DESCRIPTORS);
1032 }
1033
1034 if (mask & RADV_PREFETCH_VS)
1035 radv_emit_shader_prefetch(cmd_buffer,
1036 pipeline->shaders[MESA_SHADER_VERTEX]);
1037
1038 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
1039 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
1040
1041 if (mask & RADV_PREFETCH_TCS)
1042 radv_emit_shader_prefetch(cmd_buffer,
1043 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
1044
1045 if (mask & RADV_PREFETCH_TES)
1046 radv_emit_shader_prefetch(cmd_buffer,
1047 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
1048
1049 if (mask & RADV_PREFETCH_GS) {
1050 radv_emit_shader_prefetch(cmd_buffer,
1051 pipeline->shaders[MESA_SHADER_GEOMETRY]);
1052 if (radv_pipeline_has_gs_copy_shader(pipeline))
1053 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
1054 }
1055
1056 if (mask & RADV_PREFETCH_PS)
1057 radv_emit_shader_prefetch(cmd_buffer,
1058 pipeline->shaders[MESA_SHADER_FRAGMENT]);
1059
1060 state->prefetch_L2_mask &= ~mask;
1061 }
1062
1063 static void
1064 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
1065 {
1066 if (!cmd_buffer->device->physical_device->rad_info.rbplus_allowed)
1067 return;
1068
1069 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1070 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1071
1072 unsigned sx_ps_downconvert = 0;
1073 unsigned sx_blend_opt_epsilon = 0;
1074 unsigned sx_blend_opt_control = 0;
1075
1076 if (!cmd_buffer->state.attachments || !subpass)
1077 return;
1078
1079 for (unsigned i = 0; i < subpass->color_count; ++i) {
1080 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1081 /* We don't set the DISABLE bits, because the HW can't have holes,
1082 * so the SPI color format is set to 32-bit 1-component. */
1083 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1084 continue;
1085 }
1086
1087 int idx = subpass->color_attachments[i].attachment;
1088 struct radv_color_buffer_info *cb = &cmd_buffer->state.attachments[idx].cb;
1089
1090 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
1091 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
1092 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
1093 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
1094
1095 bool has_alpha, has_rgb;
1096
1097 /* Set if RGB and A are present. */
1098 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
1099
1100 if (format == V_028C70_COLOR_8 ||
1101 format == V_028C70_COLOR_16 ||
1102 format == V_028C70_COLOR_32)
1103 has_rgb = !has_alpha;
1104 else
1105 has_rgb = true;
1106
1107 /* Check the colormask and export format. */
1108 if (!(colormask & 0x7))
1109 has_rgb = false;
1110 if (!(colormask & 0x8))
1111 has_alpha = false;
1112
1113 if (spi_format == V_028714_SPI_SHADER_ZERO) {
1114 has_rgb = false;
1115 has_alpha = false;
1116 }
1117
1118 /* Disable value checking for disabled channels. */
1119 if (!has_rgb)
1120 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1121 if (!has_alpha)
1122 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1123
1124 /* Enable down-conversion for 32bpp and smaller formats. */
1125 switch (format) {
1126 case V_028C70_COLOR_8:
1127 case V_028C70_COLOR_8_8:
1128 case V_028C70_COLOR_8_8_8_8:
1129 /* For 1 and 2-channel formats, use the superset thereof. */
1130 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1131 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1132 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1133 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1134 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1135 }
1136 break;
1137
1138 case V_028C70_COLOR_5_6_5:
1139 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1140 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1141 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1142 }
1143 break;
1144
1145 case V_028C70_COLOR_1_5_5_5:
1146 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1147 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1148 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1149 }
1150 break;
1151
1152 case V_028C70_COLOR_4_4_4_4:
1153 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1154 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1155 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1156 }
1157 break;
1158
1159 case V_028C70_COLOR_32:
1160 if (swap == V_028C70_SWAP_STD &&
1161 spi_format == V_028714_SPI_SHADER_32_R)
1162 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1163 else if (swap == V_028C70_SWAP_ALT_REV &&
1164 spi_format == V_028714_SPI_SHADER_32_AR)
1165 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1166 break;
1167
1168 case V_028C70_COLOR_16:
1169 case V_028C70_COLOR_16_16:
1170 /* For 1-channel formats, use the superset thereof. */
1171 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1172 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1173 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1174 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1175 if (swap == V_028C70_SWAP_STD ||
1176 swap == V_028C70_SWAP_STD_REV)
1177 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1178 else
1179 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1180 }
1181 break;
1182
1183 case V_028C70_COLOR_10_11_11:
1184 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1185 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1186 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1187 }
1188 break;
1189
1190 case V_028C70_COLOR_2_10_10_10:
1191 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1192 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1193 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1194 }
1195 break;
1196 }
1197 }
1198
1199 /* Do not set the DISABLE bits for the unused attachments, as that
1200 * breaks dual source blending in SkQP and does not seem to improve
1201 * performance. */
1202
1203 if (sx_ps_downconvert == cmd_buffer->state.last_sx_ps_downconvert &&
1204 sx_blend_opt_epsilon == cmd_buffer->state.last_sx_blend_opt_epsilon &&
1205 sx_blend_opt_control == cmd_buffer->state.last_sx_blend_opt_control)
1206 return;
1207
1208 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1209 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1210 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1211 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1212
1213 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1214
1215 cmd_buffer->state.last_sx_ps_downconvert = sx_ps_downconvert;
1216 cmd_buffer->state.last_sx_blend_opt_epsilon = sx_blend_opt_epsilon;
1217 cmd_buffer->state.last_sx_blend_opt_control = sx_blend_opt_control;
1218 }
1219
1220 static void
1221 radv_emit_batch_break_on_new_ps(struct radv_cmd_buffer *cmd_buffer)
1222 {
1223 if (!cmd_buffer->device->pbb_allowed)
1224 return;
1225
1226 struct radv_binning_settings settings =
1227 radv_get_binning_settings(cmd_buffer->device->physical_device);
1228 bool break_for_new_ps =
1229 (!cmd_buffer->state.emitted_pipeline ||
1230 cmd_buffer->state.emitted_pipeline->shaders[MESA_SHADER_FRAGMENT] !=
1231 cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT]) &&
1232 (settings.context_states_per_bin > 1 ||
1233 settings.persistent_states_per_bin > 1);
1234 bool break_for_new_cb_target_mask =
1235 (!cmd_buffer->state.emitted_pipeline ||
1236 cmd_buffer->state.emitted_pipeline->graphics.cb_target_mask !=
1237 cmd_buffer->state.pipeline->graphics.cb_target_mask) &&
1238 settings.context_states_per_bin > 1;
1239
1240 if (!break_for_new_ps && !break_for_new_cb_target_mask)
1241 return;
1242
1243 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1244 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1245 }
1246
1247 static void
1248 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1249 {
1250 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1251
1252 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1253 return;
1254
1255 radv_update_multisample_state(cmd_buffer, pipeline);
1256 radv_update_binning_state(cmd_buffer, pipeline);
1257
1258 cmd_buffer->scratch_size_per_wave_needed = MAX2(cmd_buffer->scratch_size_per_wave_needed,
1259 pipeline->scratch_bytes_per_wave);
1260 cmd_buffer->scratch_waves_wanted = MAX2(cmd_buffer->scratch_waves_wanted,
1261 pipeline->max_waves);
1262
1263 if (!cmd_buffer->state.emitted_pipeline ||
1264 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1265 pipeline->graphics.can_use_guardband)
1266 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1267
1268 if (!cmd_buffer->state.emitted_pipeline ||
1269 cmd_buffer->state.emitted_pipeline->graphics.pa_su_sc_mode_cntl !=
1270 pipeline->graphics.pa_su_sc_mode_cntl)
1271 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_CULL_MODE |
1272 RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE;
1273
1274 if (!cmd_buffer->state.emitted_pipeline)
1275 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY;
1276
1277 if (!cmd_buffer->state.emitted_pipeline ||
1278 cmd_buffer->state.emitted_pipeline->graphics.db_depth_control !=
1279 pipeline->graphics.db_depth_control)
1280 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE |
1281 RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE |
1282 RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP |
1283 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE |
1284 RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE |
1285 RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP;
1286
1287 if (!cmd_buffer->state.emitted_pipeline)
1288 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP;
1289
1290 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1291
1292 if (!cmd_buffer->state.emitted_pipeline ||
1293 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1294 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1295 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1296 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1297 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1298 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1299 }
1300
1301 radv_emit_batch_break_on_new_ps(cmd_buffer);
1302
1303 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1304 if (!pipeline->shaders[i])
1305 continue;
1306
1307 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1308 pipeline->shaders[i]->bo);
1309 }
1310
1311 if (radv_pipeline_has_gs_copy_shader(pipeline))
1312 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1313 pipeline->gs_copy_shader->bo);
1314
1315 if (unlikely(cmd_buffer->device->trace_bo))
1316 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1317
1318 cmd_buffer->state.emitted_pipeline = pipeline;
1319
1320 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1321 }
1322
1323 static void
1324 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1325 {
1326 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1327 cmd_buffer->state.dynamic.viewport.viewports);
1328 }
1329
1330 static void
1331 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1332 {
1333 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1334
1335 si_write_scissors(cmd_buffer->cs, 0, count,
1336 cmd_buffer->state.dynamic.scissor.scissors,
1337 cmd_buffer->state.dynamic.viewport.viewports,
1338 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1339
1340 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1341 }
1342
1343 static void
1344 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1345 {
1346 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1347 return;
1348
1349 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1350 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1351 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1352 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1353 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1354 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1355 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1356 }
1357 }
1358
1359 static void
1360 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1361 {
1362 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1363
1364 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1365 S_028A08_WIDTH(CLAMP(width, 0, 0xFFFF)));
1366 }
1367
1368 static void
1369 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1370 {
1371 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1372
1373 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1374 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1375 }
1376
1377 static void
1378 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1379 {
1380 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1381
1382 radeon_set_context_reg_seq(cmd_buffer->cs,
1383 R_028430_DB_STENCILREFMASK, 2);
1384 radeon_emit(cmd_buffer->cs,
1385 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1386 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1387 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1388 S_028430_STENCILOPVAL(1));
1389 radeon_emit(cmd_buffer->cs,
1390 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1391 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1392 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1393 S_028434_STENCILOPVAL_BF(1));
1394 }
1395
1396 static void
1397 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1398 {
1399 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1400
1401 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1402 fui(d->depth_bounds.min));
1403 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1404 fui(d->depth_bounds.max));
1405 }
1406
1407 static void
1408 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1409 {
1410 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1411 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1412 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1413
1414
1415 radeon_set_context_reg_seq(cmd_buffer->cs,
1416 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1417 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1418 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1419 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1420 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1421 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1422 }
1423
1424 static void
1425 radv_emit_line_stipple(struct radv_cmd_buffer *cmd_buffer)
1426 {
1427 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1428 uint32_t auto_reset_cntl = 1;
1429
1430 if (d->primitive_topology == V_008958_DI_PT_LINESTRIP)
1431 auto_reset_cntl = 2;
1432
1433 radeon_set_context_reg(cmd_buffer->cs, R_028A0C_PA_SC_LINE_STIPPLE,
1434 S_028A0C_LINE_PATTERN(d->line_stipple.pattern) |
1435 S_028A0C_REPEAT_COUNT(d->line_stipple.factor - 1) |
1436 S_028A0C_AUTO_RESET_CNTL(auto_reset_cntl));
1437 }
1438
1439 static void
1440 radv_emit_culling(struct radv_cmd_buffer *cmd_buffer, uint32_t states)
1441 {
1442 unsigned pa_su_sc_mode_cntl = cmd_buffer->state.pipeline->graphics.pa_su_sc_mode_cntl;
1443 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1444
1445 if (states & RADV_CMD_DIRTY_DYNAMIC_CULL_MODE) {
1446 pa_su_sc_mode_cntl &= C_028814_CULL_FRONT;
1447 pa_su_sc_mode_cntl |= S_028814_CULL_FRONT(!!(d->cull_mode & VK_CULL_MODE_FRONT_BIT));
1448
1449 pa_su_sc_mode_cntl &= C_028814_CULL_BACK;
1450 pa_su_sc_mode_cntl |= S_028814_CULL_BACK(!!(d->cull_mode & VK_CULL_MODE_BACK_BIT));
1451 }
1452
1453 if (states & RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE) {
1454 pa_su_sc_mode_cntl &= C_028814_FACE;
1455 pa_su_sc_mode_cntl |= S_028814_FACE(d->front_face);
1456 }
1457
1458 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
1459 pa_su_sc_mode_cntl);
1460 }
1461
1462 static void
1463 radv_emit_primitive_topology(struct radv_cmd_buffer *cmd_buffer)
1464 {
1465 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1466
1467 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1468 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
1469 cmd_buffer->cs,
1470 R_030908_VGT_PRIMITIVE_TYPE, 1,
1471 d->primitive_topology);
1472 } else {
1473 radeon_set_config_reg(cmd_buffer->cs,
1474 R_008958_VGT_PRIMITIVE_TYPE,
1475 d->primitive_topology);
1476 }
1477 }
1478
1479 static void
1480 radv_emit_depth_control(struct radv_cmd_buffer *cmd_buffer, uint32_t states)
1481 {
1482 unsigned db_depth_control = cmd_buffer->state.pipeline->graphics.db_depth_control;
1483 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1484
1485 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE) {
1486 db_depth_control &= C_028800_Z_ENABLE;
1487 db_depth_control |= S_028800_Z_ENABLE(d->depth_test_enable ? 1 : 0);
1488 }
1489
1490 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE) {
1491 db_depth_control &= C_028800_Z_WRITE_ENABLE;
1492 db_depth_control |= S_028800_Z_WRITE_ENABLE(d->depth_write_enable ? 1 : 0);
1493 }
1494
1495 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP) {
1496 db_depth_control &= C_028800_ZFUNC;
1497 db_depth_control |= S_028800_ZFUNC(d->depth_compare_op);
1498 }
1499
1500 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE) {
1501 db_depth_control &= C_028800_DEPTH_BOUNDS_ENABLE;
1502 db_depth_control |= S_028800_DEPTH_BOUNDS_ENABLE(d->depth_bounds_test_enable ? 1 : 0);
1503 }
1504
1505 if (states & RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE) {
1506 db_depth_control &= C_028800_STENCIL_ENABLE;
1507 db_depth_control |= S_028800_STENCIL_ENABLE(d->stencil_test_enable ? 1 : 0);
1508
1509 db_depth_control &= C_028800_BACKFACE_ENABLE;
1510 db_depth_control |= S_028800_BACKFACE_ENABLE(d->stencil_test_enable ? 1 : 0);
1511 }
1512
1513 if (states & RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP) {
1514 db_depth_control &= C_028800_STENCILFUNC;
1515 db_depth_control |= S_028800_STENCILFUNC(d->stencil_op.front.compare_op);
1516
1517 db_depth_control &= C_028800_STENCILFUNC_BF;
1518 db_depth_control |= S_028800_STENCILFUNC_BF(d->stencil_op.back.compare_op);
1519 }
1520
1521 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL,
1522 db_depth_control);
1523 }
1524
1525 static void
1526 radv_emit_stencil_control(struct radv_cmd_buffer *cmd_buffer)
1527 {
1528 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1529
1530 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL,
1531 S_02842C_STENCILFAIL(si_translate_stencil_op(d->stencil_op.front.fail_op)) |
1532 S_02842C_STENCILZPASS(si_translate_stencil_op(d->stencil_op.front.pass_op)) |
1533 S_02842C_STENCILZFAIL(si_translate_stencil_op(d->stencil_op.front.depth_fail_op)) |
1534 S_02842C_STENCILFAIL_BF(si_translate_stencil_op(d->stencil_op.back.fail_op)) |
1535 S_02842C_STENCILZPASS_BF(si_translate_stencil_op(d->stencil_op.back.pass_op)) |
1536 S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(d->stencil_op.back.depth_fail_op)));
1537 }
1538
1539 static void
1540 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1541 int index,
1542 struct radv_color_buffer_info *cb,
1543 struct radv_image_view *iview,
1544 VkImageLayout layout,
1545 bool in_render_loop)
1546 {
1547 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1548 uint32_t cb_color_info = cb->cb_color_info;
1549 struct radv_image *image = iview->image;
1550
1551 if (!radv_layout_dcc_compressed(cmd_buffer->device, image, layout, in_render_loop,
1552 radv_image_queue_family_mask(image,
1553 cmd_buffer->queue_family_index,
1554 cmd_buffer->queue_family_index))) {
1555 cb_color_info &= C_028C70_DCC_ENABLE;
1556 }
1557
1558 if (!radv_layout_can_fast_clear(image, layout, in_render_loop,
1559 radv_image_queue_family_mask(image,
1560 cmd_buffer->queue_family_index,
1561 cmd_buffer->queue_family_index))) {
1562 cb_color_info &= C_028C70_COMPRESSION;
1563 }
1564
1565 if (radv_image_is_tc_compat_cmask(image) &&
1566 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1567 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1568 /* If this bit is set, the FMASK decompression operation
1569 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1570 */
1571 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1572 }
1573
1574 if (radv_image_has_fmask(image) &&
1575 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1576 radv_is_hw_resolve_pipeline(cmd_buffer))) {
1577 /* Make sure FMASK is enabled if it has been cleared because:
1578 *
1579 * 1) it's required for FMASK_DECOMPRESS operations to avoid
1580 * GPU hangs
1581 * 2) it's necessary for CB_RESOLVE which can read compressed
1582 * FMASK data anyways.
1583 */
1584 cb_color_info |= S_028C70_COMPRESSION(1);
1585 }
1586
1587 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1588 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1589 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1590 radeon_emit(cmd_buffer->cs, 0);
1591 radeon_emit(cmd_buffer->cs, 0);
1592 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1593 radeon_emit(cmd_buffer->cs, cb_color_info);
1594 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1595 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1596 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1597 radeon_emit(cmd_buffer->cs, 0);
1598 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1599 radeon_emit(cmd_buffer->cs, 0);
1600
1601 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1602 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1603
1604 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1605 cb->cb_color_base >> 32);
1606 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1607 cb->cb_color_cmask >> 32);
1608 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1609 cb->cb_color_fmask >> 32);
1610 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1611 cb->cb_dcc_base >> 32);
1612 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1613 cb->cb_color_attrib2);
1614 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1615 cb->cb_color_attrib3);
1616 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1617 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1618 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1619 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1620 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1621 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1622 radeon_emit(cmd_buffer->cs, cb_color_info);
1623 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1624 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1625 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1626 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1627 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1628 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1629
1630 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1631 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1632 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1633
1634 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1635 cb->cb_mrt_epitch);
1636 } else {
1637 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1638 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1639 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1640 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1641 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1642 radeon_emit(cmd_buffer->cs, cb_color_info);
1643 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1644 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1645 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1646 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1647 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1648 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1649
1650 if (is_vi) { /* DCC BASE */
1651 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1652 }
1653 }
1654
1655 if (radv_dcc_enabled(image, iview->base_mip)) {
1656 /* Drawing with DCC enabled also compresses colorbuffers. */
1657 VkImageSubresourceRange range = {
1658 .aspectMask = iview->aspect_mask,
1659 .baseMipLevel = iview->base_mip,
1660 .levelCount = iview->level_count,
1661 .baseArrayLayer = iview->base_layer,
1662 .layerCount = iview->layer_count,
1663 };
1664
1665 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1666 }
1667 }
1668
1669 static void
1670 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1671 struct radv_ds_buffer_info *ds,
1672 const struct radv_image_view *iview,
1673 VkImageLayout layout,
1674 bool in_render_loop, bool requires_cond_exec)
1675 {
1676 const struct radv_image *image = iview->image;
1677 uint32_t db_z_info = ds->db_z_info;
1678 uint32_t db_z_info_reg;
1679
1680 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug ||
1681 !radv_image_is_tc_compat_htile(image))
1682 return;
1683
1684 if (!radv_layout_is_htile_compressed(image, layout, in_render_loop,
1685 radv_image_queue_family_mask(image,
1686 cmd_buffer->queue_family_index,
1687 cmd_buffer->queue_family_index))) {
1688 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1689 }
1690
1691 db_z_info &= C_028040_ZRANGE_PRECISION;
1692
1693 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1694 db_z_info_reg = R_028038_DB_Z_INFO;
1695 } else {
1696 db_z_info_reg = R_028040_DB_Z_INFO;
1697 }
1698
1699 /* When we don't know the last fast clear value we need to emit a
1700 * conditional packet that will eventually skip the following
1701 * SET_CONTEXT_REG packet.
1702 */
1703 if (requires_cond_exec) {
1704 uint64_t va = radv_get_tc_compat_zrange_va(image, iview->base_mip);
1705
1706 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1707 radeon_emit(cmd_buffer->cs, va);
1708 radeon_emit(cmd_buffer->cs, va >> 32);
1709 radeon_emit(cmd_buffer->cs, 0);
1710 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1711 }
1712
1713 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1714 }
1715
1716 static void
1717 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1718 struct radv_ds_buffer_info *ds,
1719 struct radv_image_view *iview,
1720 VkImageLayout layout,
1721 bool in_render_loop)
1722 {
1723 const struct radv_image *image = iview->image;
1724 uint32_t db_z_info = ds->db_z_info;
1725 uint32_t db_stencil_info = ds->db_stencil_info;
1726
1727 if (!radv_layout_is_htile_compressed(image, layout, in_render_loop,
1728 radv_image_queue_family_mask(image,
1729 cmd_buffer->queue_family_index,
1730 cmd_buffer->queue_family_index))) {
1731 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1732 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1733 }
1734
1735 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1736 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1737
1738 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1739 /* Enable HTILE caching in L2 for small chips. */
1740 unsigned meta_write_policy, meta_read_policy;
1741 /* TODO: investigate whether LRU improves performance on other chips too */
1742 if (cmd_buffer->device->physical_device->rad_info.num_render_backends <= 4) {
1743 meta_write_policy = V_02807C_CACHE_LRU_WR; /* cache writes */
1744 meta_read_policy = V_02807C_CACHE_LRU_RD; /* cache reads */
1745 } else {
1746 meta_write_policy = V_02807C_CACHE_STREAM_WR; /* write combine */
1747 meta_read_policy = V_02807C_CACHE_NOA_RD; /* don't cache reads */
1748 }
1749
1750 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1751 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1752
1753 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1754 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1755 radeon_emit(cmd_buffer->cs, db_z_info);
1756 radeon_emit(cmd_buffer->cs, db_stencil_info);
1757 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1758 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1759 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1760 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1761
1762 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 6);
1763 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1764 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1765 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1766 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1767 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1768 radeon_emit(cmd_buffer->cs,
1769 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
1770 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
1771 S_02807C_HTILE_WR_POLICY(meta_write_policy) |
1772 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
1773 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD) |
1774 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD) |
1775 S_02807C_HTILE_RD_POLICY(meta_read_policy));
1776 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1777 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1778 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1779 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1780 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1781
1782 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1783 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1784 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1785 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1786 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1787 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1788 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1789 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1790 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1791 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1792 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1793
1794 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1795 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1796 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1797 } else {
1798 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1799
1800 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1801 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1802 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1803 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1804 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1805 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1806 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1807 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1808 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1809 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1810
1811 }
1812
1813 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1814 radv_update_zrange_precision(cmd_buffer, ds, iview, layout,
1815 in_render_loop, true);
1816
1817 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1818 ds->pa_su_poly_offset_db_fmt_cntl);
1819 }
1820
1821 /**
1822 * Update the fast clear depth/stencil values if the image is bound as a
1823 * depth/stencil buffer.
1824 */
1825 static void
1826 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1827 const struct radv_image_view *iview,
1828 VkClearDepthStencilValue ds_clear_value,
1829 VkImageAspectFlags aspects)
1830 {
1831 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1832 const struct radv_image *image = iview->image;
1833 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1834 uint32_t att_idx;
1835
1836 if (!cmd_buffer->state.attachments || !subpass)
1837 return;
1838
1839 if (!subpass->depth_stencil_attachment)
1840 return;
1841
1842 att_idx = subpass->depth_stencil_attachment->attachment;
1843 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1844 return;
1845
1846 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1847 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1848 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1849 radeon_emit(cs, ds_clear_value.stencil);
1850 radeon_emit(cs, fui(ds_clear_value.depth));
1851 } else if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1852 radeon_set_context_reg_seq(cs, R_02802C_DB_DEPTH_CLEAR, 1);
1853 radeon_emit(cs, fui(ds_clear_value.depth));
1854 } else {
1855 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1856 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 1);
1857 radeon_emit(cs, ds_clear_value.stencil);
1858 }
1859
1860 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1861 * only needed when clearing Z to 0.0.
1862 */
1863 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1864 ds_clear_value.depth == 0.0) {
1865 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1866 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1867
1868 radv_update_zrange_precision(cmd_buffer, &cmd_buffer->state.attachments[att_idx].ds,
1869 iview, layout, in_render_loop, false);
1870 }
1871
1872 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1873 }
1874
1875 /**
1876 * Set the clear depth/stencil values to the image's metadata.
1877 */
1878 static void
1879 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1880 struct radv_image *image,
1881 const VkImageSubresourceRange *range,
1882 VkClearDepthStencilValue ds_clear_value,
1883 VkImageAspectFlags aspects)
1884 {
1885 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1886 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel);
1887 uint32_t level_count = radv_get_levelCount(image, range);
1888
1889 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1890 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1891 /* Use the fastest way when both aspects are used. */
1892 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + 2 * level_count, cmd_buffer->state.predicating));
1893 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1894 S_370_WR_CONFIRM(1) |
1895 S_370_ENGINE_SEL(V_370_PFP));
1896 radeon_emit(cs, va);
1897 radeon_emit(cs, va >> 32);
1898
1899 for (uint32_t l = 0; l < level_count; l++) {
1900 radeon_emit(cs, ds_clear_value.stencil);
1901 radeon_emit(cs, fui(ds_clear_value.depth));
1902 }
1903 } else {
1904 /* Otherwise we need one WRITE_DATA packet per level. */
1905 for (uint32_t l = 0; l < level_count; l++) {
1906 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel + l);
1907 unsigned value;
1908
1909 if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1910 value = fui(ds_clear_value.depth);
1911 va += 4;
1912 } else {
1913 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1914 value = ds_clear_value.stencil;
1915 }
1916
1917 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1918 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1919 S_370_WR_CONFIRM(1) |
1920 S_370_ENGINE_SEL(V_370_PFP));
1921 radeon_emit(cs, va);
1922 radeon_emit(cs, va >> 32);
1923 radeon_emit(cs, value);
1924 }
1925 }
1926 }
1927
1928 /**
1929 * Update the TC-compat metadata value for this image.
1930 */
1931 static void
1932 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1933 struct radv_image *image,
1934 const VkImageSubresourceRange *range,
1935 uint32_t value)
1936 {
1937 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1938
1939 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug)
1940 return;
1941
1942 uint64_t va = radv_get_tc_compat_zrange_va(image, range->baseMipLevel);
1943 uint32_t level_count = radv_get_levelCount(image, range);
1944
1945 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + level_count, cmd_buffer->state.predicating));
1946 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1947 S_370_WR_CONFIRM(1) |
1948 S_370_ENGINE_SEL(V_370_PFP));
1949 radeon_emit(cs, va);
1950 radeon_emit(cs, va >> 32);
1951
1952 for (uint32_t l = 0; l < level_count; l++)
1953 radeon_emit(cs, value);
1954 }
1955
1956 static void
1957 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1958 const struct radv_image_view *iview,
1959 VkClearDepthStencilValue ds_clear_value)
1960 {
1961 VkImageSubresourceRange range = {
1962 .aspectMask = iview->aspect_mask,
1963 .baseMipLevel = iview->base_mip,
1964 .levelCount = iview->level_count,
1965 .baseArrayLayer = iview->base_layer,
1966 .layerCount = iview->layer_count,
1967 };
1968 uint32_t cond_val;
1969
1970 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1971 * depth clear value is 0.0f.
1972 */
1973 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1974
1975 radv_set_tc_compat_zrange_metadata(cmd_buffer, iview->image, &range,
1976 cond_val);
1977 }
1978
1979 /**
1980 * Update the clear depth/stencil values for this image.
1981 */
1982 void
1983 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1984 const struct radv_image_view *iview,
1985 VkClearDepthStencilValue ds_clear_value,
1986 VkImageAspectFlags aspects)
1987 {
1988 VkImageSubresourceRange range = {
1989 .aspectMask = iview->aspect_mask,
1990 .baseMipLevel = iview->base_mip,
1991 .levelCount = iview->level_count,
1992 .baseArrayLayer = iview->base_layer,
1993 .layerCount = iview->layer_count,
1994 };
1995 struct radv_image *image = iview->image;
1996
1997 assert(radv_image_has_htile(image));
1998
1999 radv_set_ds_clear_metadata(cmd_buffer, iview->image, &range,
2000 ds_clear_value, aspects);
2001
2002 if (radv_image_is_tc_compat_htile(image) &&
2003 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
2004 radv_update_tc_compat_zrange_metadata(cmd_buffer, iview,
2005 ds_clear_value);
2006 }
2007
2008 radv_update_bound_fast_clear_ds(cmd_buffer, iview, ds_clear_value,
2009 aspects);
2010 }
2011
2012 /**
2013 * Load the clear depth/stencil values from the image's metadata.
2014 */
2015 static void
2016 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
2017 const struct radv_image_view *iview)
2018 {
2019 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2020 const struct radv_image *image = iview->image;
2021 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
2022 uint64_t va = radv_get_ds_clear_value_va(image, iview->base_mip);
2023 unsigned reg_offset = 0, reg_count = 0;
2024
2025 if (!radv_image_has_htile(image))
2026 return;
2027
2028 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
2029 ++reg_count;
2030 } else {
2031 ++reg_offset;
2032 va += 4;
2033 }
2034 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
2035 ++reg_count;
2036
2037 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
2038
2039 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
2040 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, 0));
2041 radeon_emit(cs, va);
2042 radeon_emit(cs, va >> 32);
2043 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
2044 radeon_emit(cs, reg_count);
2045 } else {
2046 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2047 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2048 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2049 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
2050 radeon_emit(cs, va);
2051 radeon_emit(cs, va >> 32);
2052 radeon_emit(cs, reg >> 2);
2053 radeon_emit(cs, 0);
2054
2055 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
2056 radeon_emit(cs, 0);
2057 }
2058 }
2059
2060 /*
2061 * With DCC some colors don't require CMASK elimination before being
2062 * used as a texture. This sets a predicate value to determine if the
2063 * cmask eliminate is required.
2064 */
2065 void
2066 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
2067 struct radv_image *image,
2068 const VkImageSubresourceRange *range, bool value)
2069 {
2070 uint64_t pred_val = value;
2071 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
2072 uint32_t level_count = radv_get_levelCount(image, range);
2073 uint32_t count = 2 * level_count;
2074
2075 assert(radv_dcc_enabled(image, range->baseMipLevel));
2076
2077 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
2078 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
2079 S_370_WR_CONFIRM(1) |
2080 S_370_ENGINE_SEL(V_370_PFP));
2081 radeon_emit(cmd_buffer->cs, va);
2082 radeon_emit(cmd_buffer->cs, va >> 32);
2083
2084 for (uint32_t l = 0; l < level_count; l++) {
2085 radeon_emit(cmd_buffer->cs, pred_val);
2086 radeon_emit(cmd_buffer->cs, pred_val >> 32);
2087 }
2088 }
2089
2090 /**
2091 * Update the DCC predicate to reflect the compression state.
2092 */
2093 void
2094 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
2095 struct radv_image *image,
2096 const VkImageSubresourceRange *range, bool value)
2097 {
2098 uint64_t pred_val = value;
2099 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
2100 uint32_t level_count = radv_get_levelCount(image, range);
2101 uint32_t count = 2 * level_count;
2102
2103 assert(radv_dcc_enabled(image, range->baseMipLevel));
2104
2105 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
2106 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
2107 S_370_WR_CONFIRM(1) |
2108 S_370_ENGINE_SEL(V_370_PFP));
2109 radeon_emit(cmd_buffer->cs, va);
2110 radeon_emit(cmd_buffer->cs, va >> 32);
2111
2112 for (uint32_t l = 0; l < level_count; l++) {
2113 radeon_emit(cmd_buffer->cs, pred_val);
2114 radeon_emit(cmd_buffer->cs, pred_val >> 32);
2115 }
2116 }
2117
2118 /**
2119 * Update the fast clear color values if the image is bound as a color buffer.
2120 */
2121 static void
2122 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
2123 struct radv_image *image,
2124 int cb_idx,
2125 uint32_t color_values[2])
2126 {
2127 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2128 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2129 uint32_t att_idx;
2130
2131 if (!cmd_buffer->state.attachments || !subpass)
2132 return;
2133
2134 att_idx = subpass->color_attachments[cb_idx].attachment;
2135 if (att_idx == VK_ATTACHMENT_UNUSED)
2136 return;
2137
2138 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
2139 return;
2140
2141 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
2142 radeon_emit(cs, color_values[0]);
2143 radeon_emit(cs, color_values[1]);
2144
2145 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2146 }
2147
2148 /**
2149 * Set the clear color values to the image's metadata.
2150 */
2151 static void
2152 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
2153 struct radv_image *image,
2154 const VkImageSubresourceRange *range,
2155 uint32_t color_values[2])
2156 {
2157 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2158 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
2159 uint32_t level_count = radv_get_levelCount(image, range);
2160 uint32_t count = 2 * level_count;
2161
2162 assert(radv_image_has_cmask(image) ||
2163 radv_dcc_enabled(image, range->baseMipLevel));
2164
2165 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
2166 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
2167 S_370_WR_CONFIRM(1) |
2168 S_370_ENGINE_SEL(V_370_PFP));
2169 radeon_emit(cs, va);
2170 radeon_emit(cs, va >> 32);
2171
2172 for (uint32_t l = 0; l < level_count; l++) {
2173 radeon_emit(cs, color_values[0]);
2174 radeon_emit(cs, color_values[1]);
2175 }
2176 }
2177
2178 /**
2179 * Update the clear color values for this image.
2180 */
2181 void
2182 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
2183 const struct radv_image_view *iview,
2184 int cb_idx,
2185 uint32_t color_values[2])
2186 {
2187 struct radv_image *image = iview->image;
2188 VkImageSubresourceRange range = {
2189 .aspectMask = iview->aspect_mask,
2190 .baseMipLevel = iview->base_mip,
2191 .levelCount = iview->level_count,
2192 .baseArrayLayer = iview->base_layer,
2193 .layerCount = iview->layer_count,
2194 };
2195
2196 assert(radv_image_has_cmask(image) ||
2197 radv_dcc_enabled(image, iview->base_mip));
2198
2199 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
2200
2201 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
2202 color_values);
2203 }
2204
2205 /**
2206 * Load the clear color values from the image's metadata.
2207 */
2208 static void
2209 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
2210 struct radv_image_view *iview,
2211 int cb_idx)
2212 {
2213 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2214 struct radv_image *image = iview->image;
2215 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
2216
2217 if (!radv_image_has_cmask(image) &&
2218 !radv_dcc_enabled(image, iview->base_mip))
2219 return;
2220
2221 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
2222
2223 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
2224 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, cmd_buffer->state.predicating));
2225 radeon_emit(cs, va);
2226 radeon_emit(cs, va >> 32);
2227 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
2228 radeon_emit(cs, 2);
2229 } else {
2230 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
2231 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2232 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2233 COPY_DATA_COUNT_SEL);
2234 radeon_emit(cs, va);
2235 radeon_emit(cs, va >> 32);
2236 radeon_emit(cs, reg >> 2);
2237 radeon_emit(cs, 0);
2238
2239 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
2240 radeon_emit(cs, 0);
2241 }
2242 }
2243
2244 static void
2245 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
2246 {
2247 int i;
2248 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
2249 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2250
2251 /* this may happen for inherited secondary recording */
2252 if (!framebuffer)
2253 return;
2254
2255 for (i = 0; i < 8; ++i) {
2256 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
2257 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2258 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2259 continue;
2260 }
2261
2262 int idx = subpass->color_attachments[i].attachment;
2263 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2264 VkImageLayout layout = subpass->color_attachments[i].layout;
2265 bool in_render_loop = subpass->color_attachments[i].in_render_loop;
2266
2267 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->bo);
2268
2269 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
2270 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
2271 radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout, in_render_loop);
2272
2273 radv_load_color_clear_metadata(cmd_buffer, iview, i);
2274 }
2275
2276 if (subpass->depth_stencil_attachment) {
2277 int idx = subpass->depth_stencil_attachment->attachment;
2278 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
2279 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
2280 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2281 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->state.attachments[idx].iview->bo);
2282
2283 radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, iview, layout, in_render_loop);
2284
2285 if (cmd_buffer->state.attachments[idx].ds.offset_scale != cmd_buffer->state.offset_scale) {
2286 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2287 cmd_buffer->state.offset_scale = cmd_buffer->state.attachments[idx].ds.offset_scale;
2288 }
2289 radv_load_ds_clear_metadata(cmd_buffer, iview);
2290 } else {
2291 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
2292 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
2293 else
2294 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
2295
2296 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2297 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2298 }
2299 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2300 S_028208_BR_X(framebuffer->width) |
2301 S_028208_BR_Y(framebuffer->height));
2302
2303 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
2304 bool disable_constant_encode =
2305 cmd_buffer->device->physical_device->rad_info.has_dcc_constant_encode;
2306 enum chip_class chip_class =
2307 cmd_buffer->device->physical_device->rad_info.chip_class;
2308 uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
2309
2310 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
2311 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
2312 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
2313 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
2314 }
2315
2316 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2317 /* Enable CMASK/FMASK/DCC caching in L2 for small chips. */
2318 unsigned meta_write_policy, meta_read_policy;
2319 /* TODO: investigate whether LRU improves performance on other chips too */
2320 if (cmd_buffer->device->physical_device->rad_info.num_render_backends <= 4) {
2321 meta_write_policy = V_02807C_CACHE_LRU_WR; /* cache writes */
2322 meta_read_policy = V_02807C_CACHE_LRU_RD; /* cache reads */
2323 } else {
2324 meta_write_policy = V_02807C_CACHE_STREAM_WR; /* write combine */
2325 meta_read_policy = V_02807C_CACHE_NOA_RD; /* don't cache reads */
2326 }
2327
2328 radeon_set_context_reg(cmd_buffer->cs, R_028410_CB_RMI_GL2_CACHE_CONTROL,
2329 S_028410_CMASK_WR_POLICY(meta_write_policy) |
2330 S_028410_FMASK_WR_POLICY(meta_write_policy) |
2331 S_028410_DCC_WR_POLICY(meta_write_policy) |
2332 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR) |
2333 S_028410_CMASK_RD_POLICY(meta_read_policy) |
2334 S_028410_FMASK_RD_POLICY(meta_read_policy) |
2335 S_028410_DCC_RD_POLICY(meta_read_policy) |
2336 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD));
2337 }
2338
2339 if (cmd_buffer->device->dfsm_allowed) {
2340 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2341 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2342 }
2343
2344 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
2345 }
2346
2347 static void
2348 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer, bool indirect)
2349 {
2350 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2351 struct radv_cmd_state *state = &cmd_buffer->state;
2352
2353 if (state->index_type != state->last_index_type) {
2354 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2355 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2356 cs, R_03090C_VGT_INDEX_TYPE,
2357 2, state->index_type);
2358 } else {
2359 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2360 radeon_emit(cs, state->index_type);
2361 }
2362
2363 state->last_index_type = state->index_type;
2364 }
2365
2366 /* For the direct indexed draws we use DRAW_INDEX_2, which includes
2367 * the index_va and max_index_count already. */
2368 if (!indirect)
2369 return;
2370
2371 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2372 radeon_emit(cs, state->index_va);
2373 radeon_emit(cs, state->index_va >> 32);
2374
2375 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2376 radeon_emit(cs, state->max_index_count);
2377
2378 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
2379 }
2380
2381 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
2382 {
2383 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
2384 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2385 uint32_t pa_sc_mode_cntl_1 =
2386 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
2387 uint32_t db_count_control;
2388
2389 if(!cmd_buffer->state.active_occlusion_queries) {
2390 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2391 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2392 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2393 has_perfect_queries) {
2394 /* Re-enable out-of-order rasterization if the
2395 * bound pipeline supports it and if it's has
2396 * been disabled before starting any perfect
2397 * occlusion queries.
2398 */
2399 radeon_set_context_reg(cmd_buffer->cs,
2400 R_028A4C_PA_SC_MODE_CNTL_1,
2401 pa_sc_mode_cntl_1);
2402 }
2403 }
2404 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
2405 } else {
2406 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2407 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
2408 bool gfx10_perfect = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries;
2409
2410 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2411 /* Always enable PERFECT_ZPASS_COUNTS due to issues with partially
2412 * covered tiles, discards, and early depth testing. For more details,
2413 * see https://gitlab.freedesktop.org/mesa/mesa/-/issues/3218 */
2414 db_count_control =
2415 S_028004_PERFECT_ZPASS_COUNTS(1) |
2416 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
2417 S_028004_SAMPLE_RATE(sample_rate) |
2418 S_028004_ZPASS_ENABLE(1) |
2419 S_028004_SLICE_EVEN_ENABLE(1) |
2420 S_028004_SLICE_ODD_ENABLE(1);
2421
2422 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2423 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2424 has_perfect_queries) {
2425 /* If the bound pipeline has enabled
2426 * out-of-order rasterization, we should
2427 * disable it before starting any perfect
2428 * occlusion queries.
2429 */
2430 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2431
2432 radeon_set_context_reg(cmd_buffer->cs,
2433 R_028A4C_PA_SC_MODE_CNTL_1,
2434 pa_sc_mode_cntl_1);
2435 }
2436 } else {
2437 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2438 S_028004_SAMPLE_RATE(sample_rate);
2439 }
2440 }
2441
2442 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2443
2444 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2445 }
2446
2447 static void
2448 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2449 {
2450 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2451
2452 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2453 radv_emit_viewport(cmd_buffer);
2454
2455 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2456 !cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
2457 radv_emit_scissor(cmd_buffer);
2458
2459 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2460 radv_emit_line_width(cmd_buffer);
2461
2462 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2463 radv_emit_blend_constants(cmd_buffer);
2464
2465 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2466 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2467 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2468 radv_emit_stencil(cmd_buffer);
2469
2470 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2471 radv_emit_depth_bounds(cmd_buffer);
2472
2473 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2474 radv_emit_depth_bias(cmd_buffer);
2475
2476 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2477 radv_emit_discard_rectangle(cmd_buffer);
2478
2479 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2480 radv_emit_sample_locations(cmd_buffer);
2481
2482 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2483 radv_emit_line_stipple(cmd_buffer);
2484
2485 if (states & (RADV_CMD_DIRTY_DYNAMIC_CULL_MODE |
2486 RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE))
2487 radv_emit_culling(cmd_buffer, states);
2488
2489 if (states & RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY)
2490 radv_emit_primitive_topology(cmd_buffer);
2491
2492 if (states & (RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE |
2493 RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE |
2494 RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP |
2495 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE |
2496 RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE |
2497 RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP))
2498 radv_emit_depth_control(cmd_buffer, states);
2499
2500 if (states & RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP)
2501 radv_emit_stencil_control(cmd_buffer);
2502
2503 cmd_buffer->state.dirty &= ~states;
2504 }
2505
2506 static void
2507 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2508 VkPipelineBindPoint bind_point)
2509 {
2510 struct radv_descriptor_state *descriptors_state =
2511 radv_get_descriptors_state(cmd_buffer, bind_point);
2512 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2513 unsigned bo_offset;
2514
2515 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2516 set->mapped_ptr,
2517 &bo_offset))
2518 return;
2519
2520 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2521 set->va += bo_offset;
2522 }
2523
2524 static void
2525 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2526 VkPipelineBindPoint bind_point)
2527 {
2528 struct radv_descriptor_state *descriptors_state =
2529 radv_get_descriptors_state(cmd_buffer, bind_point);
2530 uint32_t size = MAX_SETS * 4;
2531 uint32_t offset;
2532 void *ptr;
2533
2534 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2535 256, &offset, &ptr))
2536 return;
2537
2538 for (unsigned i = 0; i < MAX_SETS; i++) {
2539 uint32_t *uptr = ((uint32_t *)ptr) + i;
2540 uint64_t set_va = 0;
2541 struct radv_descriptor_set *set = descriptors_state->sets[i];
2542 if (descriptors_state->valid & (1u << i))
2543 set_va = set->va;
2544 uptr[0] = set_va & 0xffffffff;
2545 }
2546
2547 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2548 va += offset;
2549
2550 if (cmd_buffer->state.pipeline) {
2551 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2552 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2553 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2554
2555 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2556 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2557 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2558
2559 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2560 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2561 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2562
2563 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2564 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2565 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2566
2567 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2568 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2569 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2570 }
2571
2572 if (cmd_buffer->state.compute_pipeline)
2573 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2574 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2575 }
2576
2577 static void
2578 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2579 VkShaderStageFlags stages)
2580 {
2581 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2582 VK_PIPELINE_BIND_POINT_COMPUTE :
2583 VK_PIPELINE_BIND_POINT_GRAPHICS;
2584 struct radv_descriptor_state *descriptors_state =
2585 radv_get_descriptors_state(cmd_buffer, bind_point);
2586 struct radv_cmd_state *state = &cmd_buffer->state;
2587 bool flush_indirect_descriptors;
2588
2589 if (!descriptors_state->dirty)
2590 return;
2591
2592 if (descriptors_state->push_dirty)
2593 radv_flush_push_descriptors(cmd_buffer, bind_point);
2594
2595 flush_indirect_descriptors =
2596 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2597 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2598 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2599 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2600
2601 if (flush_indirect_descriptors)
2602 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2603
2604 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2605 cmd_buffer->cs,
2606 MAX_SETS * MESA_SHADER_STAGES * 4);
2607
2608 if (cmd_buffer->state.pipeline) {
2609 radv_foreach_stage(stage, stages) {
2610 if (!cmd_buffer->state.pipeline->shaders[stage])
2611 continue;
2612
2613 radv_emit_descriptor_pointers(cmd_buffer,
2614 cmd_buffer->state.pipeline,
2615 descriptors_state, stage);
2616 }
2617 }
2618
2619 if (cmd_buffer->state.compute_pipeline &&
2620 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2621 radv_emit_descriptor_pointers(cmd_buffer,
2622 cmd_buffer->state.compute_pipeline,
2623 descriptors_state,
2624 MESA_SHADER_COMPUTE);
2625 }
2626
2627 descriptors_state->dirty = 0;
2628 descriptors_state->push_dirty = false;
2629
2630 assert(cmd_buffer->cs->cdw <= cdw_max);
2631
2632 if (unlikely(cmd_buffer->device->trace_bo))
2633 radv_save_descriptors(cmd_buffer, bind_point);
2634 }
2635
2636 static void
2637 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2638 VkShaderStageFlags stages)
2639 {
2640 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2641 ? cmd_buffer->state.compute_pipeline
2642 : cmd_buffer->state.pipeline;
2643 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2644 VK_PIPELINE_BIND_POINT_COMPUTE :
2645 VK_PIPELINE_BIND_POINT_GRAPHICS;
2646 struct radv_descriptor_state *descriptors_state =
2647 radv_get_descriptors_state(cmd_buffer, bind_point);
2648 struct radv_pipeline_layout *layout = pipeline->layout;
2649 struct radv_shader_variant *shader, *prev_shader;
2650 bool need_push_constants = false;
2651 unsigned offset;
2652 void *ptr;
2653 uint64_t va;
2654
2655 stages &= cmd_buffer->push_constant_stages;
2656 if (!stages ||
2657 (!layout->push_constant_size && !layout->dynamic_offset_count))
2658 return;
2659
2660 radv_foreach_stage(stage, stages) {
2661 shader = radv_get_shader(pipeline, stage);
2662 if (!shader)
2663 continue;
2664
2665 need_push_constants |= shader->info.loads_push_constants;
2666 need_push_constants |= shader->info.loads_dynamic_offsets;
2667
2668 uint8_t base = shader->info.base_inline_push_consts;
2669 uint8_t count = shader->info.num_inline_push_consts;
2670
2671 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2672 AC_UD_INLINE_PUSH_CONSTANTS,
2673 count,
2674 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2675 }
2676
2677 if (need_push_constants) {
2678 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2679 16 * layout->dynamic_offset_count,
2680 256, &offset, &ptr))
2681 return;
2682
2683 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2684 memcpy((char*)ptr + layout->push_constant_size,
2685 descriptors_state->dynamic_buffers,
2686 16 * layout->dynamic_offset_count);
2687
2688 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2689 va += offset;
2690
2691 ASSERTED unsigned cdw_max =
2692 radeon_check_space(cmd_buffer->device->ws,
2693 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2694
2695 prev_shader = NULL;
2696 radv_foreach_stage(stage, stages) {
2697 shader = radv_get_shader(pipeline, stage);
2698
2699 /* Avoid redundantly emitting the address for merged stages. */
2700 if (shader && shader != prev_shader) {
2701 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2702 AC_UD_PUSH_CONSTANTS, va);
2703
2704 prev_shader = shader;
2705 }
2706 }
2707 assert(cmd_buffer->cs->cdw <= cdw_max);
2708 }
2709
2710 cmd_buffer->push_constant_stages &= ~stages;
2711 }
2712
2713 static void
2714 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2715 bool pipeline_is_dirty)
2716 {
2717 if ((pipeline_is_dirty ||
2718 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2719 cmd_buffer->state.pipeline->num_vertex_bindings &&
2720 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.has_vertex_buffers) {
2721 unsigned vb_offset;
2722 void *vb_ptr;
2723 uint32_t i = 0;
2724 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2725 uint64_t va;
2726
2727 /* allocate some descriptor state for vertex buffers */
2728 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2729 &vb_offset, &vb_ptr))
2730 return;
2731
2732 for (i = 0; i < count; i++) {
2733 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2734 uint32_t offset;
2735 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2736 unsigned num_records;
2737 unsigned stride;
2738
2739 if (!buffer)
2740 continue;
2741
2742 va = radv_buffer_get_va(buffer->bo);
2743
2744 offset = cmd_buffer->vertex_bindings[i].offset;
2745 va += offset + buffer->offset;
2746
2747 if (cmd_buffer->vertex_bindings[i].size) {
2748 num_records = cmd_buffer->vertex_bindings[i].size;
2749 } else {
2750 num_records = buffer->size - offset;
2751 }
2752
2753 if (cmd_buffer->state.pipeline->graphics.uses_dynamic_stride) {
2754 stride = cmd_buffer->vertex_bindings[i].stride;
2755 } else {
2756 stride = cmd_buffer->state.pipeline->binding_stride[i];
2757 }
2758
2759 if (cmd_buffer->device->physical_device->rad_info.chip_class != GFX8 && stride)
2760 num_records /= stride;
2761
2762 uint32_t rsrc_word3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2763 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2764 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2765 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2766
2767 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2768 /* OOB_SELECT chooses the out-of-bounds check:
2769 * - 1: index >= NUM_RECORDS (Structured)
2770 * - 3: offset >= NUM_RECORDS (Raw)
2771 */
2772 int oob_select = stride ? V_008F0C_OOB_SELECT_STRUCTURED : V_008F0C_OOB_SELECT_RAW;
2773
2774 rsrc_word3 |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
2775 S_008F0C_OOB_SELECT(oob_select) |
2776 S_008F0C_RESOURCE_LEVEL(1);
2777 } else {
2778 rsrc_word3 |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2779 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2780 }
2781
2782 desc[0] = va;
2783 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2784 desc[2] = num_records;
2785 desc[3] = rsrc_word3;
2786 }
2787
2788 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2789 va += vb_offset;
2790
2791 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2792 AC_UD_VS_VERTEX_BUFFERS, va);
2793
2794 cmd_buffer->state.vb_va = va;
2795 cmd_buffer->state.vb_size = count * 16;
2796 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2797 }
2798 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2799 }
2800
2801 static void
2802 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2803 {
2804 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2805 struct radv_userdata_info *loc;
2806 uint32_t base_reg;
2807
2808 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2809 if (!radv_get_shader(pipeline, stage))
2810 continue;
2811
2812 loc = radv_lookup_user_sgpr(pipeline, stage,
2813 AC_UD_STREAMOUT_BUFFERS);
2814 if (loc->sgpr_idx == -1)
2815 continue;
2816
2817 base_reg = pipeline->user_data_0[stage];
2818
2819 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2820 base_reg + loc->sgpr_idx * 4, va, false);
2821 }
2822
2823 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
2824 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2825 if (loc->sgpr_idx != -1) {
2826 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2827
2828 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2829 base_reg + loc->sgpr_idx * 4, va, false);
2830 }
2831 }
2832 }
2833
2834 static void
2835 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2836 {
2837 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2838 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2839 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2840 unsigned so_offset;
2841 void *so_ptr;
2842 uint64_t va;
2843
2844 /* Allocate some descriptor state for streamout buffers. */
2845 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2846 MAX_SO_BUFFERS * 16, 256,
2847 &so_offset, &so_ptr))
2848 return;
2849
2850 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2851 struct radv_buffer *buffer = sb[i].buffer;
2852 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2853
2854 if (!(so->enabled_mask & (1 << i)))
2855 continue;
2856
2857 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2858
2859 va += sb[i].offset;
2860
2861 /* Set the descriptor.
2862 *
2863 * On GFX8, the format must be non-INVALID, otherwise
2864 * the buffer will be considered not bound and store
2865 * instructions will be no-ops.
2866 */
2867 uint32_t size = 0xffffffff;
2868
2869 /* Compute the correct buffer size for NGG streamout
2870 * because it's used to determine the max emit per
2871 * buffer.
2872 */
2873 if (cmd_buffer->device->physical_device->use_ngg_streamout)
2874 size = buffer->size - sb[i].offset;
2875
2876 uint32_t rsrc_word3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2877 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2878 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2879 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2880
2881 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2882 rsrc_word3 |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2883 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
2884 S_008F0C_RESOURCE_LEVEL(1);
2885 } else {
2886 rsrc_word3 |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2887 }
2888
2889 desc[0] = va;
2890 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2891 desc[2] = size;
2892 desc[3] = rsrc_word3;
2893 }
2894
2895 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2896 va += so_offset;
2897
2898 radv_emit_streamout_buffers(cmd_buffer, va);
2899 }
2900
2901 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2902 }
2903
2904 static void
2905 radv_flush_ngg_gs_state(struct radv_cmd_buffer *cmd_buffer)
2906 {
2907 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2908 struct radv_userdata_info *loc;
2909 uint32_t ngg_gs_state = 0;
2910 uint32_t base_reg;
2911
2912 if (!radv_pipeline_has_gs(pipeline) ||
2913 !radv_pipeline_has_ngg(pipeline))
2914 return;
2915
2916 /* By default NGG GS queries are disabled but they are enabled if the
2917 * command buffer has active GDS queries or if it's a secondary command
2918 * buffer that inherits the number of generated primitives.
2919 */
2920 if (cmd_buffer->state.active_pipeline_gds_queries ||
2921 (cmd_buffer->state.inherited_pipeline_statistics & VK_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_PRIMITIVES_BIT))
2922 ngg_gs_state = 1;
2923
2924 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_GEOMETRY,
2925 AC_UD_NGG_GS_STATE);
2926 base_reg = pipeline->user_data_0[MESA_SHADER_GEOMETRY];
2927 assert(loc->sgpr_idx != -1);
2928
2929 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
2930 ngg_gs_state);
2931 }
2932
2933 static void
2934 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2935 {
2936 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2937 radv_flush_streamout_descriptors(cmd_buffer);
2938 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2939 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2940 radv_flush_ngg_gs_state(cmd_buffer);
2941 }
2942
2943 struct radv_draw_info {
2944 /**
2945 * Number of vertices.
2946 */
2947 uint32_t count;
2948
2949 /**
2950 * Index of the first vertex.
2951 */
2952 int32_t vertex_offset;
2953
2954 /**
2955 * First instance id.
2956 */
2957 uint32_t first_instance;
2958
2959 /**
2960 * Number of instances.
2961 */
2962 uint32_t instance_count;
2963
2964 /**
2965 * First index (indexed draws only).
2966 */
2967 uint32_t first_index;
2968
2969 /**
2970 * Whether it's an indexed draw.
2971 */
2972 bool indexed;
2973
2974 /**
2975 * Indirect draw parameters resource.
2976 */
2977 struct radv_buffer *indirect;
2978 uint64_t indirect_offset;
2979 uint32_t stride;
2980
2981 /**
2982 * Draw count parameters resource.
2983 */
2984 struct radv_buffer *count_buffer;
2985 uint64_t count_buffer_offset;
2986
2987 /**
2988 * Stream output parameters resource.
2989 */
2990 struct radv_buffer *strmout_buffer;
2991 uint64_t strmout_buffer_offset;
2992 };
2993
2994 static uint32_t
2995 radv_get_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2996 {
2997 switch (cmd_buffer->state.index_type) {
2998 case V_028A7C_VGT_INDEX_8:
2999 return 0xffu;
3000 case V_028A7C_VGT_INDEX_16:
3001 return 0xffffu;
3002 case V_028A7C_VGT_INDEX_32:
3003 return 0xffffffffu;
3004 default:
3005 unreachable("invalid index type");
3006 }
3007 }
3008
3009 static void
3010 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
3011 bool instanced_draw, bool indirect_draw,
3012 bool count_from_stream_output,
3013 uint32_t draw_vertex_count)
3014 {
3015 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
3016 struct radv_cmd_state *state = &cmd_buffer->state;
3017 unsigned topology = state->dynamic.primitive_topology;
3018 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3019 unsigned ia_multi_vgt_param;
3020
3021 ia_multi_vgt_param =
3022 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
3023 indirect_draw,
3024 count_from_stream_output,
3025 draw_vertex_count,
3026 topology);
3027
3028 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
3029 if (info->chip_class == GFX9) {
3030 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
3031 cs,
3032 R_030960_IA_MULTI_VGT_PARAM,
3033 4, ia_multi_vgt_param);
3034 } else if (info->chip_class >= GFX7) {
3035 radeon_set_context_reg_idx(cs,
3036 R_028AA8_IA_MULTI_VGT_PARAM,
3037 1, ia_multi_vgt_param);
3038 } else {
3039 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
3040 ia_multi_vgt_param);
3041 }
3042 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
3043 }
3044 }
3045
3046 static void
3047 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
3048 const struct radv_draw_info *draw_info)
3049 {
3050 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
3051 struct radv_cmd_state *state = &cmd_buffer->state;
3052 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3053 int32_t primitive_reset_en;
3054
3055 /* Draw state. */
3056 if (info->chip_class < GFX10) {
3057 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
3058 draw_info->indirect,
3059 !!draw_info->strmout_buffer,
3060 draw_info->indirect ? 0 : draw_info->count);
3061 }
3062
3063 /* Primitive restart. */
3064 primitive_reset_en =
3065 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
3066
3067 if (primitive_reset_en != state->last_primitive_reset_en) {
3068 state->last_primitive_reset_en = primitive_reset_en;
3069 if (info->chip_class >= GFX9) {
3070 radeon_set_uconfig_reg(cs,
3071 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
3072 primitive_reset_en);
3073 } else {
3074 radeon_set_context_reg(cs,
3075 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
3076 primitive_reset_en);
3077 }
3078 }
3079
3080 if (primitive_reset_en) {
3081 uint32_t primitive_reset_index =
3082 radv_get_primitive_reset_index(cmd_buffer);
3083
3084 if (primitive_reset_index != state->last_primitive_reset_index) {
3085 radeon_set_context_reg(cs,
3086 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
3087 primitive_reset_index);
3088 state->last_primitive_reset_index = primitive_reset_index;
3089 }
3090 }
3091
3092 if (draw_info->strmout_buffer) {
3093 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
3094
3095 va += draw_info->strmout_buffer->offset +
3096 draw_info->strmout_buffer_offset;
3097
3098 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
3099 draw_info->stride);
3100
3101 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3102 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
3103 COPY_DATA_DST_SEL(COPY_DATA_REG) |
3104 COPY_DATA_WR_CONFIRM);
3105 radeon_emit(cs, va);
3106 radeon_emit(cs, va >> 32);
3107 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
3108 radeon_emit(cs, 0); /* unused */
3109
3110 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
3111 }
3112 }
3113
3114 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
3115 VkPipelineStageFlags src_stage_mask)
3116 {
3117 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
3118 VK_PIPELINE_STAGE_TRANSFER_BIT |
3119 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
3120 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
3121 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
3122 }
3123
3124 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
3125 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
3126 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
3127 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
3128 VK_PIPELINE_STAGE_TRANSFER_BIT |
3129 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
3130 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
3131 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
3132 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
3133 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
3134 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
3135 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
3136 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
3137 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
3138 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
3139 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
3140 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
3141 }
3142 }
3143
3144 static enum radv_cmd_flush_bits
3145 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
3146 VkAccessFlags src_flags,
3147 struct radv_image *image)
3148 {
3149 bool flush_CB_meta = true, flush_DB_meta = true;
3150 enum radv_cmd_flush_bits flush_bits = 0;
3151 uint32_t b;
3152
3153 if (image) {
3154 if (!radv_image_has_CB_metadata(image))
3155 flush_CB_meta = false;
3156 if (!radv_image_has_htile(image))
3157 flush_DB_meta = false;
3158 }
3159
3160 for_each_bit(b, src_flags) {
3161 switch ((VkAccessFlagBits)(1 << b)) {
3162 case VK_ACCESS_SHADER_WRITE_BIT:
3163 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
3164 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
3165 flush_bits |= RADV_CMD_FLAG_WB_L2;
3166 break;
3167 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
3168 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
3169 if (flush_CB_meta)
3170 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3171 break;
3172 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
3173 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
3174 if (flush_DB_meta)
3175 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3176 break;
3177 case VK_ACCESS_TRANSFER_WRITE_BIT:
3178 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3179 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3180 RADV_CMD_FLAG_INV_L2;
3181
3182 if (flush_CB_meta)
3183 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3184 if (flush_DB_meta)
3185 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3186 break;
3187 case VK_ACCESS_MEMORY_WRITE_BIT:
3188 flush_bits |= RADV_CMD_FLAG_INV_L2 |
3189 RADV_CMD_FLAG_WB_L2 |
3190 RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3191 RADV_CMD_FLAG_FLUSH_AND_INV_DB;
3192
3193 if (flush_CB_meta)
3194 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3195 if (flush_DB_meta)
3196 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3197 break;
3198 default:
3199 break;
3200 }
3201 }
3202 return flush_bits;
3203 }
3204
3205 static enum radv_cmd_flush_bits
3206 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
3207 VkAccessFlags dst_flags,
3208 struct radv_image *image)
3209 {
3210 bool flush_CB_meta = true, flush_DB_meta = true;
3211 enum radv_cmd_flush_bits flush_bits = 0;
3212 bool flush_CB = true, flush_DB = true;
3213 bool image_is_coherent = false;
3214 uint32_t b;
3215
3216 if (image) {
3217 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
3218 flush_CB = false;
3219 flush_DB = false;
3220 }
3221
3222 if (!radv_image_has_CB_metadata(image))
3223 flush_CB_meta = false;
3224 if (!radv_image_has_htile(image))
3225 flush_DB_meta = false;
3226
3227 /* TODO: implement shader coherent for GFX10 */
3228
3229 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
3230 if (image->info.samples == 1 &&
3231 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
3232 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
3233 !vk_format_is_stencil(image->vk_format)) {
3234 /* Single-sample color and single-sample depth
3235 * (not stencil) are coherent with shaders on
3236 * GFX9.
3237 */
3238 image_is_coherent = true;
3239 }
3240 }
3241 }
3242
3243 for_each_bit(b, dst_flags) {
3244 switch ((VkAccessFlagBits)(1 << b)) {
3245 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
3246 case VK_ACCESS_INDEX_READ_BIT:
3247 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
3248 break;
3249 case VK_ACCESS_UNIFORM_READ_BIT:
3250 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
3251 break;
3252 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
3253 case VK_ACCESS_TRANSFER_READ_BIT:
3254 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
3255 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
3256 RADV_CMD_FLAG_INV_L2;
3257 break;
3258 case VK_ACCESS_SHADER_READ_BIT:
3259 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
3260 /* Unlike LLVM, ACO uses SMEM for SSBOs and we have to
3261 * invalidate the scalar cache. */
3262 if (!cmd_buffer->device->physical_device->use_llvm)
3263 flush_bits |= RADV_CMD_FLAG_INV_SCACHE;
3264
3265 if (!image_is_coherent)
3266 flush_bits |= RADV_CMD_FLAG_INV_L2;
3267 break;
3268 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
3269 if (flush_CB)
3270 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
3271 if (flush_CB_meta)
3272 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3273 break;
3274 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
3275 if (flush_DB)
3276 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
3277 if (flush_DB_meta)
3278 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3279 break;
3280 case VK_ACCESS_MEMORY_READ_BIT:
3281 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
3282 RADV_CMD_FLAG_INV_SCACHE |
3283 RADV_CMD_FLAG_INV_L2;
3284 if (flush_CB)
3285 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
3286 if (flush_CB_meta)
3287 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3288 if (flush_DB)
3289 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
3290 if (flush_DB_meta)
3291 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3292 break;
3293 default:
3294 break;
3295 }
3296 }
3297 return flush_bits;
3298 }
3299
3300 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
3301 const struct radv_subpass_barrier *barrier)
3302 {
3303 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
3304 NULL);
3305 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
3306 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
3307 NULL);
3308 }
3309
3310 uint32_t
3311 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
3312 {
3313 struct radv_cmd_state *state = &cmd_buffer->state;
3314 uint32_t subpass_id = state->subpass - state->pass->subpasses;
3315
3316 /* The id of this subpass shouldn't exceed the number of subpasses in
3317 * this render pass minus 1.
3318 */
3319 assert(subpass_id < state->pass->subpass_count);
3320 return subpass_id;
3321 }
3322
3323 static struct radv_sample_locations_state *
3324 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3325 uint32_t att_idx,
3326 bool begin_subpass)
3327 {
3328 struct radv_cmd_state *state = &cmd_buffer->state;
3329 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
3330 struct radv_image_view *view = state->attachments[att_idx].iview;
3331
3332 if (view->image->info.samples == 1)
3333 return NULL;
3334
3335 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
3336 /* Return the initial sample locations if this is the initial
3337 * layout transition of the given subpass attachemnt.
3338 */
3339 if (state->attachments[att_idx].sample_location.count > 0)
3340 return &state->attachments[att_idx].sample_location;
3341 } else {
3342 /* Otherwise return the subpass sample locations if defined. */
3343 if (state->subpass_sample_locs) {
3344 /* Because the driver sets the current subpass before
3345 * initial layout transitions, we should use the sample
3346 * locations from the previous subpass to avoid an
3347 * off-by-one problem. Otherwise, use the sample
3348 * locations for the current subpass for final layout
3349 * transitions.
3350 */
3351 if (begin_subpass)
3352 subpass_id--;
3353
3354 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
3355 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
3356 return &state->subpass_sample_locs[i].sample_location;
3357 }
3358 }
3359 }
3360
3361 return NULL;
3362 }
3363
3364 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
3365 struct radv_subpass_attachment att,
3366 bool begin_subpass)
3367 {
3368 unsigned idx = att.attachment;
3369 struct radv_image_view *view = cmd_buffer->state.attachments[idx].iview;
3370 struct radv_sample_locations_state *sample_locs;
3371 VkImageSubresourceRange range;
3372 range.aspectMask = view->aspect_mask;
3373 range.baseMipLevel = view->base_mip;
3374 range.levelCount = 1;
3375 range.baseArrayLayer = view->base_layer;
3376 range.layerCount = cmd_buffer->state.framebuffer->layers;
3377
3378 if (cmd_buffer->state.subpass->view_mask) {
3379 /* If the current subpass uses multiview, the driver might have
3380 * performed a fast color/depth clear to the whole image
3381 * (including all layers). To make sure the driver will
3382 * decompress the image correctly (if needed), we have to
3383 * account for the "real" number of layers. If the view mask is
3384 * sparse, this will decompress more layers than needed.
3385 */
3386 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
3387 }
3388
3389 /* Get the subpass sample locations for the given attachment, if NULL
3390 * is returned the driver will use the default HW locations.
3391 */
3392 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
3393 begin_subpass);
3394
3395 /* Determine if the subpass uses separate depth/stencil layouts. */
3396 bool uses_separate_depth_stencil_layouts = false;
3397 if ((cmd_buffer->state.attachments[idx].current_layout !=
3398 cmd_buffer->state.attachments[idx].current_stencil_layout) ||
3399 (att.layout != att.stencil_layout)) {
3400 uses_separate_depth_stencil_layouts = true;
3401 }
3402
3403 /* For separate layouts, perform depth and stencil transitions
3404 * separately.
3405 */
3406 if (uses_separate_depth_stencil_layouts &&
3407 (range.aspectMask == (VK_IMAGE_ASPECT_DEPTH_BIT |
3408 VK_IMAGE_ASPECT_STENCIL_BIT))) {
3409 /* Depth-only transitions. */
3410 range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3411 radv_handle_image_transition(cmd_buffer,
3412 view->image,
3413 cmd_buffer->state.attachments[idx].current_layout,
3414 cmd_buffer->state.attachments[idx].current_in_render_loop,
3415 att.layout, att.in_render_loop,
3416 0, 0, &range, sample_locs);
3417
3418 /* Stencil-only transitions. */
3419 range.aspectMask = VK_IMAGE_ASPECT_STENCIL_BIT;
3420 radv_handle_image_transition(cmd_buffer,
3421 view->image,
3422 cmd_buffer->state.attachments[idx].current_stencil_layout,
3423 cmd_buffer->state.attachments[idx].current_in_render_loop,
3424 att.stencil_layout, att.in_render_loop,
3425 0, 0, &range, sample_locs);
3426 } else {
3427 radv_handle_image_transition(cmd_buffer,
3428 view->image,
3429 cmd_buffer->state.attachments[idx].current_layout,
3430 cmd_buffer->state.attachments[idx].current_in_render_loop,
3431 att.layout, att.in_render_loop,
3432 0, 0, &range, sample_locs);
3433 }
3434
3435 cmd_buffer->state.attachments[idx].current_layout = att.layout;
3436 cmd_buffer->state.attachments[idx].current_stencil_layout = att.stencil_layout;
3437 cmd_buffer->state.attachments[idx].current_in_render_loop = att.in_render_loop;
3438
3439
3440 }
3441
3442 void
3443 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
3444 const struct radv_subpass *subpass)
3445 {
3446 cmd_buffer->state.subpass = subpass;
3447
3448 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
3449 }
3450
3451 static VkResult
3452 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3453 struct radv_render_pass *pass,
3454 const VkRenderPassBeginInfo *info)
3455 {
3456 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
3457 vk_find_struct_const(info->pNext,
3458 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
3459 struct radv_cmd_state *state = &cmd_buffer->state;
3460
3461 if (!sample_locs) {
3462 state->subpass_sample_locs = NULL;
3463 return VK_SUCCESS;
3464 }
3465
3466 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
3467 const VkAttachmentSampleLocationsEXT *att_sample_locs =
3468 &sample_locs->pAttachmentInitialSampleLocations[i];
3469 uint32_t att_idx = att_sample_locs->attachmentIndex;
3470 struct radv_image *image = cmd_buffer->state.attachments[att_idx].iview->image;
3471
3472 assert(vk_format_is_depth_or_stencil(image->vk_format));
3473
3474 /* From the Vulkan spec 1.1.108:
3475 *
3476 * "If the image referenced by the framebuffer attachment at
3477 * index attachmentIndex was not created with
3478 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
3479 * then the values specified in sampleLocationsInfo are
3480 * ignored."
3481 */
3482 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
3483 continue;
3484
3485 const VkSampleLocationsInfoEXT *sample_locs_info =
3486 &att_sample_locs->sampleLocationsInfo;
3487
3488 state->attachments[att_idx].sample_location.per_pixel =
3489 sample_locs_info->sampleLocationsPerPixel;
3490 state->attachments[att_idx].sample_location.grid_size =
3491 sample_locs_info->sampleLocationGridSize;
3492 state->attachments[att_idx].sample_location.count =
3493 sample_locs_info->sampleLocationsCount;
3494 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
3495 sample_locs_info->pSampleLocations,
3496 sample_locs_info->sampleLocationsCount);
3497 }
3498
3499 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
3500 sample_locs->postSubpassSampleLocationsCount *
3501 sizeof(state->subpass_sample_locs[0]),
3502 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3503 if (state->subpass_sample_locs == NULL) {
3504 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3505 return cmd_buffer->record_result;
3506 }
3507
3508 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
3509
3510 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
3511 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
3512 &sample_locs->pPostSubpassSampleLocations[i];
3513 const VkSampleLocationsInfoEXT *sample_locs_info =
3514 &subpass_sample_locs_info->sampleLocationsInfo;
3515
3516 state->subpass_sample_locs[i].subpass_idx =
3517 subpass_sample_locs_info->subpassIndex;
3518 state->subpass_sample_locs[i].sample_location.per_pixel =
3519 sample_locs_info->sampleLocationsPerPixel;
3520 state->subpass_sample_locs[i].sample_location.grid_size =
3521 sample_locs_info->sampleLocationGridSize;
3522 state->subpass_sample_locs[i].sample_location.count =
3523 sample_locs_info->sampleLocationsCount;
3524 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
3525 sample_locs_info->pSampleLocations,
3526 sample_locs_info->sampleLocationsCount);
3527 }
3528
3529 return VK_SUCCESS;
3530 }
3531
3532 static VkResult
3533 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
3534 struct radv_render_pass *pass,
3535 const VkRenderPassBeginInfo *info)
3536 {
3537 struct radv_cmd_state *state = &cmd_buffer->state;
3538 const struct VkRenderPassAttachmentBeginInfo *attachment_info = NULL;
3539
3540 if (info) {
3541 attachment_info = vk_find_struct_const(info->pNext,
3542 RENDER_PASS_ATTACHMENT_BEGIN_INFO);
3543 }
3544
3545
3546 if (pass->attachment_count == 0) {
3547 state->attachments = NULL;
3548 return VK_SUCCESS;
3549 }
3550
3551 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
3552 pass->attachment_count *
3553 sizeof(state->attachments[0]),
3554 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3555 if (state->attachments == NULL) {
3556 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3557 return cmd_buffer->record_result;
3558 }
3559
3560 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
3561 struct radv_render_pass_attachment *att = &pass->attachments[i];
3562 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
3563 VkImageAspectFlags clear_aspects = 0;
3564
3565 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
3566 /* color attachment */
3567 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3568 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
3569 }
3570 } else {
3571 /* depthstencil attachment */
3572 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
3573 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3574 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
3575 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3576 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
3577 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3578 }
3579 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3580 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3581 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3582 }
3583 }
3584
3585 state->attachments[i].pending_clear_aspects = clear_aspects;
3586 state->attachments[i].cleared_views = 0;
3587 if (clear_aspects && info) {
3588 assert(info->clearValueCount > i);
3589 state->attachments[i].clear_value = info->pClearValues[i];
3590 }
3591
3592 state->attachments[i].current_layout = att->initial_layout;
3593 state->attachments[i].current_in_render_loop = false;
3594 state->attachments[i].current_stencil_layout = att->stencil_initial_layout;
3595 state->attachments[i].sample_location.count = 0;
3596
3597 struct radv_image_view *iview;
3598 if (attachment_info && attachment_info->attachmentCount > i) {
3599 iview = radv_image_view_from_handle(attachment_info->pAttachments[i]);
3600 } else {
3601 iview = state->framebuffer->attachments[i];
3602 }
3603
3604 state->attachments[i].iview = iview;
3605 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3606 radv_initialise_ds_surface(cmd_buffer->device, &state->attachments[i].ds, iview);
3607 } else {
3608 radv_initialise_color_surface(cmd_buffer->device, &state->attachments[i].cb, iview);
3609 }
3610 }
3611
3612 return VK_SUCCESS;
3613 }
3614
3615 VkResult radv_AllocateCommandBuffers(
3616 VkDevice _device,
3617 const VkCommandBufferAllocateInfo *pAllocateInfo,
3618 VkCommandBuffer *pCommandBuffers)
3619 {
3620 RADV_FROM_HANDLE(radv_device, device, _device);
3621 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
3622
3623 VkResult result = VK_SUCCESS;
3624 uint32_t i;
3625
3626 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
3627
3628 if (!list_is_empty(&pool->free_cmd_buffers)) {
3629 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
3630
3631 list_del(&cmd_buffer->pool_link);
3632 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
3633
3634 result = radv_reset_cmd_buffer(cmd_buffer);
3635 cmd_buffer->level = pAllocateInfo->level;
3636
3637 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
3638 } else {
3639 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
3640 &pCommandBuffers[i]);
3641 }
3642 if (result != VK_SUCCESS)
3643 break;
3644 }
3645
3646 if (result != VK_SUCCESS) {
3647 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
3648 i, pCommandBuffers);
3649
3650 /* From the Vulkan 1.0.66 spec:
3651 *
3652 * "vkAllocateCommandBuffers can be used to create multiple
3653 * command buffers. If the creation of any of those command
3654 * buffers fails, the implementation must destroy all
3655 * successfully created command buffer objects from this
3656 * command, set all entries of the pCommandBuffers array to
3657 * NULL and return the error."
3658 */
3659 memset(pCommandBuffers, 0,
3660 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
3661 }
3662
3663 return result;
3664 }
3665
3666 void radv_FreeCommandBuffers(
3667 VkDevice device,
3668 VkCommandPool commandPool,
3669 uint32_t commandBufferCount,
3670 const VkCommandBuffer *pCommandBuffers)
3671 {
3672 for (uint32_t i = 0; i < commandBufferCount; i++) {
3673 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
3674
3675 if (cmd_buffer) {
3676 if (cmd_buffer->pool) {
3677 list_del(&cmd_buffer->pool_link);
3678 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3679 } else
3680 radv_destroy_cmd_buffer(cmd_buffer);
3681
3682 }
3683 }
3684 }
3685
3686 VkResult radv_ResetCommandBuffer(
3687 VkCommandBuffer commandBuffer,
3688 VkCommandBufferResetFlags flags)
3689 {
3690 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3691 return radv_reset_cmd_buffer(cmd_buffer);
3692 }
3693
3694 VkResult radv_BeginCommandBuffer(
3695 VkCommandBuffer commandBuffer,
3696 const VkCommandBufferBeginInfo *pBeginInfo)
3697 {
3698 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3699 VkResult result = VK_SUCCESS;
3700
3701 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3702 /* If the command buffer has already been resetted with
3703 * vkResetCommandBuffer, no need to do it again.
3704 */
3705 result = radv_reset_cmd_buffer(cmd_buffer);
3706 if (result != VK_SUCCESS)
3707 return result;
3708 }
3709
3710 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3711 cmd_buffer->state.last_primitive_reset_en = -1;
3712 cmd_buffer->state.last_index_type = -1;
3713 cmd_buffer->state.last_num_instances = -1;
3714 cmd_buffer->state.last_vertex_offset = -1;
3715 cmd_buffer->state.last_first_instance = -1;
3716 cmd_buffer->state.predication_type = -1;
3717 cmd_buffer->state.last_sx_ps_downconvert = -1;
3718 cmd_buffer->state.last_sx_blend_opt_epsilon = -1;
3719 cmd_buffer->state.last_sx_blend_opt_control = -1;
3720 cmd_buffer->usage_flags = pBeginInfo->flags;
3721
3722 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3723 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3724 assert(pBeginInfo->pInheritanceInfo);
3725 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3726 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3727
3728 struct radv_subpass *subpass =
3729 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3730
3731 if (cmd_buffer->state.framebuffer) {
3732 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3733 if (result != VK_SUCCESS)
3734 return result;
3735 }
3736
3737 cmd_buffer->state.inherited_pipeline_statistics =
3738 pBeginInfo->pInheritanceInfo->pipelineStatistics;
3739
3740 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3741 }
3742
3743 if (unlikely(cmd_buffer->device->trace_bo))
3744 radv_cmd_buffer_trace_emit(cmd_buffer);
3745
3746 radv_describe_begin_cmd_buffer(cmd_buffer);
3747
3748 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3749
3750 return result;
3751 }
3752
3753 void radv_CmdBindVertexBuffers(
3754 VkCommandBuffer commandBuffer,
3755 uint32_t firstBinding,
3756 uint32_t bindingCount,
3757 const VkBuffer* pBuffers,
3758 const VkDeviceSize* pOffsets)
3759 {
3760 radv_CmdBindVertexBuffers2EXT(commandBuffer, firstBinding,
3761 bindingCount, pBuffers, pOffsets,
3762 NULL, NULL);
3763 }
3764
3765 void radv_CmdBindVertexBuffers2EXT(
3766 VkCommandBuffer commandBuffer,
3767 uint32_t firstBinding,
3768 uint32_t bindingCount,
3769 const VkBuffer* pBuffers,
3770 const VkDeviceSize* pOffsets,
3771 const VkDeviceSize* pSizes,
3772 const VkDeviceSize* pStrides)
3773 {
3774 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3775 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3776 bool changed = false;
3777
3778 /* We have to defer setting up vertex buffer since we need the buffer
3779 * stride from the pipeline. */
3780
3781 assert(firstBinding + bindingCount <= MAX_VBS);
3782 for (uint32_t i = 0; i < bindingCount; i++) {
3783 RADV_FROM_HANDLE(radv_buffer, buffer, pBuffers[i]);
3784 uint32_t idx = firstBinding + i;
3785 VkDeviceSize size = pSizes ? pSizes[i] : 0;
3786 VkDeviceSize stride = pStrides ? pStrides[i] : 0;
3787
3788 /* pSizes and pStrides are optional. */
3789 if (!changed &&
3790 (vb[idx].buffer != buffer ||
3791 vb[idx].offset != pOffsets[i] ||
3792 vb[idx].size != size ||
3793 vb[idx].stride != stride)) {
3794 changed = true;
3795 }
3796
3797 vb[idx].buffer = buffer;
3798 vb[idx].offset = pOffsets[i];
3799 vb[idx].size = size;
3800 vb[idx].stride = stride;
3801
3802 if (buffer) {
3803 radv_cs_add_buffer(cmd_buffer->device->ws,
3804 cmd_buffer->cs, vb[idx].buffer->bo);
3805 }
3806 }
3807
3808 if (!changed) {
3809 /* No state changes. */
3810 return;
3811 }
3812
3813 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3814 }
3815
3816 static uint32_t
3817 vk_to_index_type(VkIndexType type)
3818 {
3819 switch (type) {
3820 case VK_INDEX_TYPE_UINT8_EXT:
3821 return V_028A7C_VGT_INDEX_8;
3822 case VK_INDEX_TYPE_UINT16:
3823 return V_028A7C_VGT_INDEX_16;
3824 case VK_INDEX_TYPE_UINT32:
3825 return V_028A7C_VGT_INDEX_32;
3826 default:
3827 unreachable("invalid index type");
3828 }
3829 }
3830
3831 static uint32_t
3832 radv_get_vgt_index_size(uint32_t type)
3833 {
3834 switch (type) {
3835 case V_028A7C_VGT_INDEX_8:
3836 return 1;
3837 case V_028A7C_VGT_INDEX_16:
3838 return 2;
3839 case V_028A7C_VGT_INDEX_32:
3840 return 4;
3841 default:
3842 unreachable("invalid index type");
3843 }
3844 }
3845
3846 void radv_CmdBindIndexBuffer(
3847 VkCommandBuffer commandBuffer,
3848 VkBuffer buffer,
3849 VkDeviceSize offset,
3850 VkIndexType indexType)
3851 {
3852 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3853 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3854
3855 if (cmd_buffer->state.index_buffer == index_buffer &&
3856 cmd_buffer->state.index_offset == offset &&
3857 cmd_buffer->state.index_type == indexType) {
3858 /* No state changes. */
3859 return;
3860 }
3861
3862 cmd_buffer->state.index_buffer = index_buffer;
3863 cmd_buffer->state.index_offset = offset;
3864 cmd_buffer->state.index_type = vk_to_index_type(indexType);
3865 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3866 cmd_buffer->state.index_va += index_buffer->offset + offset;
3867
3868 int index_size = radv_get_vgt_index_size(vk_to_index_type(indexType));
3869 cmd_buffer->state.max_index_count = (index_buffer->size - offset) / index_size;
3870 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3871 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3872 }
3873
3874
3875 static void
3876 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3877 VkPipelineBindPoint bind_point,
3878 struct radv_descriptor_set *set, unsigned idx)
3879 {
3880 struct radeon_winsys *ws = cmd_buffer->device->ws;
3881
3882 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3883
3884 assert(set);
3885 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3886
3887 if (!cmd_buffer->device->use_global_bo_list) {
3888 for (unsigned j = 0; j < set->buffer_count; ++j)
3889 if (set->descriptors[j])
3890 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3891 }
3892
3893 if(set->bo)
3894 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3895 }
3896
3897 void radv_CmdBindDescriptorSets(
3898 VkCommandBuffer commandBuffer,
3899 VkPipelineBindPoint pipelineBindPoint,
3900 VkPipelineLayout _layout,
3901 uint32_t firstSet,
3902 uint32_t descriptorSetCount,
3903 const VkDescriptorSet* pDescriptorSets,
3904 uint32_t dynamicOffsetCount,
3905 const uint32_t* pDynamicOffsets)
3906 {
3907 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3908 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3909 unsigned dyn_idx = 0;
3910
3911 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3912 struct radv_descriptor_state *descriptors_state =
3913 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3914
3915 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3916 unsigned idx = i + firstSet;
3917 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3918
3919 /* If the set is already bound we only need to update the
3920 * (potentially changed) dynamic offsets. */
3921 if (descriptors_state->sets[idx] != set ||
3922 !(descriptors_state->valid & (1u << idx))) {
3923 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3924 }
3925
3926 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3927 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3928 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3929 assert(dyn_idx < dynamicOffsetCount);
3930
3931 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3932 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3933 dst[0] = va;
3934 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3935 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3936 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3937 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3938 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3939 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3940
3941 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
3942 dst[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3943 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3944 S_008F0C_RESOURCE_LEVEL(1);
3945 } else {
3946 dst[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3947 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3948 }
3949
3950 cmd_buffer->push_constant_stages |=
3951 set->layout->dynamic_shader_stages;
3952 }
3953 }
3954 }
3955
3956 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3957 struct radv_descriptor_set *set,
3958 struct radv_descriptor_set_layout *layout,
3959 VkPipelineBindPoint bind_point)
3960 {
3961 struct radv_descriptor_state *descriptors_state =
3962 radv_get_descriptors_state(cmd_buffer, bind_point);
3963 set->size = layout->size;
3964 set->layout = layout;
3965
3966 if (descriptors_state->push_set.capacity < set->size) {
3967 size_t new_size = MAX2(set->size, 1024);
3968 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3969 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3970
3971 free(set->mapped_ptr);
3972 set->mapped_ptr = malloc(new_size);
3973
3974 if (!set->mapped_ptr) {
3975 descriptors_state->push_set.capacity = 0;
3976 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3977 return false;
3978 }
3979
3980 descriptors_state->push_set.capacity = new_size;
3981 }
3982
3983 return true;
3984 }
3985
3986 void radv_meta_push_descriptor_set(
3987 struct radv_cmd_buffer* cmd_buffer,
3988 VkPipelineBindPoint pipelineBindPoint,
3989 VkPipelineLayout _layout,
3990 uint32_t set,
3991 uint32_t descriptorWriteCount,
3992 const VkWriteDescriptorSet* pDescriptorWrites)
3993 {
3994 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3995 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3996 unsigned bo_offset;
3997
3998 assert(set == 0);
3999 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
4000
4001 push_set->size = layout->set[set].layout->size;
4002 push_set->layout = layout->set[set].layout;
4003
4004 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
4005 &bo_offset,
4006 (void**) &push_set->mapped_ptr))
4007 return;
4008
4009 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
4010 push_set->va += bo_offset;
4011
4012 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
4013 radv_descriptor_set_to_handle(push_set),
4014 descriptorWriteCount, pDescriptorWrites, 0, NULL);
4015
4016 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
4017 }
4018
4019 void radv_CmdPushDescriptorSetKHR(
4020 VkCommandBuffer commandBuffer,
4021 VkPipelineBindPoint pipelineBindPoint,
4022 VkPipelineLayout _layout,
4023 uint32_t set,
4024 uint32_t descriptorWriteCount,
4025 const VkWriteDescriptorSet* pDescriptorWrites)
4026 {
4027 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4028 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
4029 struct radv_descriptor_state *descriptors_state =
4030 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
4031 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
4032
4033 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
4034
4035 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
4036 layout->set[set].layout,
4037 pipelineBindPoint))
4038 return;
4039
4040 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
4041 * because it is invalid, according to Vulkan spec.
4042 */
4043 for (int i = 0; i < descriptorWriteCount; i++) {
4044 ASSERTED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
4045 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
4046 }
4047
4048 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
4049 radv_descriptor_set_to_handle(push_set),
4050 descriptorWriteCount, pDescriptorWrites, 0, NULL);
4051
4052 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
4053 descriptors_state->push_dirty = true;
4054 }
4055
4056 void radv_CmdPushDescriptorSetWithTemplateKHR(
4057 VkCommandBuffer commandBuffer,
4058 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
4059 VkPipelineLayout _layout,
4060 uint32_t set,
4061 const void* pData)
4062 {
4063 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4064 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
4065 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
4066 struct radv_descriptor_state *descriptors_state =
4067 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
4068 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
4069
4070 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
4071
4072 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
4073 layout->set[set].layout,
4074 templ->bind_point))
4075 return;
4076
4077 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
4078 descriptorUpdateTemplate, pData);
4079
4080 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
4081 descriptors_state->push_dirty = true;
4082 }
4083
4084 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
4085 VkPipelineLayout layout,
4086 VkShaderStageFlags stageFlags,
4087 uint32_t offset,
4088 uint32_t size,
4089 const void* pValues)
4090 {
4091 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4092 memcpy(cmd_buffer->push_constants + offset, pValues, size);
4093 cmd_buffer->push_constant_stages |= stageFlags;
4094 }
4095
4096 VkResult radv_EndCommandBuffer(
4097 VkCommandBuffer commandBuffer)
4098 {
4099 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4100
4101 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
4102 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
4103 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
4104
4105 /* Make sure to sync all pending active queries at the end of
4106 * command buffer.
4107 */
4108 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
4109
4110 /* Since NGG streamout uses GDS, we need to make GDS idle when
4111 * we leave the IB, otherwise another process might overwrite
4112 * it while our shaders are busy.
4113 */
4114 if (cmd_buffer->gds_needed)
4115 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
4116
4117 si_emit_cache_flush(cmd_buffer);
4118 }
4119
4120 /* Make sure CP DMA is idle at the end of IBs because the kernel
4121 * doesn't wait for it.
4122 */
4123 si_cp_dma_wait_for_idle(cmd_buffer);
4124
4125 radv_describe_end_cmd_buffer(cmd_buffer);
4126
4127 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4128 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
4129
4130 VkResult result = cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs);
4131 if (result != VK_SUCCESS)
4132 return vk_error(cmd_buffer->device->instance, result);
4133
4134 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
4135
4136 return cmd_buffer->record_result;
4137 }
4138
4139 static void
4140 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
4141 {
4142 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4143
4144 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
4145 return;
4146
4147 assert(!pipeline->ctx_cs.cdw);
4148
4149 cmd_buffer->state.emitted_compute_pipeline = pipeline;
4150
4151 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
4152 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
4153
4154 cmd_buffer->compute_scratch_size_per_wave_needed = MAX2(cmd_buffer->compute_scratch_size_per_wave_needed,
4155 pipeline->scratch_bytes_per_wave);
4156 cmd_buffer->compute_scratch_waves_wanted = MAX2(cmd_buffer->compute_scratch_waves_wanted,
4157 pipeline->max_waves);
4158
4159 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
4160 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
4161
4162 if (unlikely(cmd_buffer->device->trace_bo))
4163 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
4164 }
4165
4166 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
4167 VkPipelineBindPoint bind_point)
4168 {
4169 struct radv_descriptor_state *descriptors_state =
4170 radv_get_descriptors_state(cmd_buffer, bind_point);
4171
4172 descriptors_state->dirty |= descriptors_state->valid;
4173 }
4174
4175 void radv_CmdBindPipeline(
4176 VkCommandBuffer commandBuffer,
4177 VkPipelineBindPoint pipelineBindPoint,
4178 VkPipeline _pipeline)
4179 {
4180 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4181 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
4182
4183 switch (pipelineBindPoint) {
4184 case VK_PIPELINE_BIND_POINT_COMPUTE:
4185 if (cmd_buffer->state.compute_pipeline == pipeline)
4186 return;
4187 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
4188
4189 cmd_buffer->state.compute_pipeline = pipeline;
4190 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
4191 break;
4192 case VK_PIPELINE_BIND_POINT_GRAPHICS:
4193 if (cmd_buffer->state.pipeline == pipeline)
4194 return;
4195 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
4196
4197 cmd_buffer->state.pipeline = pipeline;
4198 if (!pipeline)
4199 break;
4200
4201 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
4202 cmd_buffer->push_constant_stages |= pipeline->active_stages;
4203
4204 /* the new vertex shader might not have the same user regs */
4205 cmd_buffer->state.last_first_instance = -1;
4206 cmd_buffer->state.last_vertex_offset = -1;
4207
4208 /* Prefetch all pipeline shaders at first draw time. */
4209 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
4210
4211 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX10 &&
4212 cmd_buffer->state.emitted_pipeline &&
4213 radv_pipeline_has_ngg(cmd_buffer->state.emitted_pipeline) &&
4214 !radv_pipeline_has_ngg(cmd_buffer->state.pipeline)) {
4215 /* Transitioning from NGG to legacy GS requires
4216 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
4217 * at the beginning of IBs when legacy GS ring pointers
4218 * are set.
4219 */
4220 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
4221 }
4222
4223 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
4224 radv_bind_streamout_state(cmd_buffer, pipeline);
4225
4226 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
4227 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
4228 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
4229 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
4230
4231 if (radv_pipeline_has_tess(pipeline))
4232 cmd_buffer->tess_rings_needed = true;
4233 break;
4234 default:
4235 assert(!"invalid bind point");
4236 break;
4237 }
4238 }
4239
4240 void radv_CmdSetViewport(
4241 VkCommandBuffer commandBuffer,
4242 uint32_t firstViewport,
4243 uint32_t viewportCount,
4244 const VkViewport* pViewports)
4245 {
4246 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4247 struct radv_cmd_state *state = &cmd_buffer->state;
4248 ASSERTED const uint32_t total_count = firstViewport + viewportCount;
4249
4250 assert(firstViewport < MAX_VIEWPORTS);
4251 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
4252
4253 if (total_count <= state->dynamic.viewport.count &&
4254 !memcmp(state->dynamic.viewport.viewports + firstViewport,
4255 pViewports, viewportCount * sizeof(*pViewports))) {
4256 return;
4257 }
4258
4259 if (state->dynamic.viewport.count < total_count)
4260 state->dynamic.viewport.count = total_count;
4261
4262 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
4263 viewportCount * sizeof(*pViewports));
4264
4265 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
4266 }
4267
4268 void radv_CmdSetScissor(
4269 VkCommandBuffer commandBuffer,
4270 uint32_t firstScissor,
4271 uint32_t scissorCount,
4272 const VkRect2D* pScissors)
4273 {
4274 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4275 struct radv_cmd_state *state = &cmd_buffer->state;
4276 ASSERTED const uint32_t total_count = firstScissor + scissorCount;
4277
4278 assert(firstScissor < MAX_SCISSORS);
4279 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
4280
4281 if (total_count <= state->dynamic.scissor.count &&
4282 !memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
4283 scissorCount * sizeof(*pScissors))) {
4284 return;
4285 }
4286
4287 if (state->dynamic.scissor.count < total_count)
4288 state->dynamic.scissor.count = total_count;
4289
4290 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
4291 scissorCount * sizeof(*pScissors));
4292
4293 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
4294 }
4295
4296 void radv_CmdSetLineWidth(
4297 VkCommandBuffer commandBuffer,
4298 float lineWidth)
4299 {
4300 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4301
4302 if (cmd_buffer->state.dynamic.line_width == lineWidth)
4303 return;
4304
4305 cmd_buffer->state.dynamic.line_width = lineWidth;
4306 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
4307 }
4308
4309 void radv_CmdSetDepthBias(
4310 VkCommandBuffer commandBuffer,
4311 float depthBiasConstantFactor,
4312 float depthBiasClamp,
4313 float depthBiasSlopeFactor)
4314 {
4315 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4316 struct radv_cmd_state *state = &cmd_buffer->state;
4317
4318 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
4319 state->dynamic.depth_bias.clamp == depthBiasClamp &&
4320 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
4321 return;
4322 }
4323
4324 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
4325 state->dynamic.depth_bias.clamp = depthBiasClamp;
4326 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
4327
4328 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
4329 }
4330
4331 void radv_CmdSetBlendConstants(
4332 VkCommandBuffer commandBuffer,
4333 const float blendConstants[4])
4334 {
4335 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4336 struct radv_cmd_state *state = &cmd_buffer->state;
4337
4338 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
4339 return;
4340
4341 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
4342
4343 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
4344 }
4345
4346 void radv_CmdSetDepthBounds(
4347 VkCommandBuffer commandBuffer,
4348 float minDepthBounds,
4349 float maxDepthBounds)
4350 {
4351 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4352 struct radv_cmd_state *state = &cmd_buffer->state;
4353
4354 if (state->dynamic.depth_bounds.min == minDepthBounds &&
4355 state->dynamic.depth_bounds.max == maxDepthBounds) {
4356 return;
4357 }
4358
4359 state->dynamic.depth_bounds.min = minDepthBounds;
4360 state->dynamic.depth_bounds.max = maxDepthBounds;
4361
4362 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
4363 }
4364
4365 void radv_CmdSetStencilCompareMask(
4366 VkCommandBuffer commandBuffer,
4367 VkStencilFaceFlags faceMask,
4368 uint32_t compareMask)
4369 {
4370 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4371 struct radv_cmd_state *state = &cmd_buffer->state;
4372 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
4373 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
4374
4375 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4376 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4377 return;
4378 }
4379
4380 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4381 state->dynamic.stencil_compare_mask.front = compareMask;
4382 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4383 state->dynamic.stencil_compare_mask.back = compareMask;
4384
4385 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
4386 }
4387
4388 void radv_CmdSetStencilWriteMask(
4389 VkCommandBuffer commandBuffer,
4390 VkStencilFaceFlags faceMask,
4391 uint32_t writeMask)
4392 {
4393 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4394 struct radv_cmd_state *state = &cmd_buffer->state;
4395 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
4396 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
4397
4398 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4399 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4400 return;
4401 }
4402
4403 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4404 state->dynamic.stencil_write_mask.front = writeMask;
4405 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4406 state->dynamic.stencil_write_mask.back = writeMask;
4407
4408 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
4409 }
4410
4411 void radv_CmdSetStencilReference(
4412 VkCommandBuffer commandBuffer,
4413 VkStencilFaceFlags faceMask,
4414 uint32_t reference)
4415 {
4416 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4417 struct radv_cmd_state *state = &cmd_buffer->state;
4418 bool front_same = state->dynamic.stencil_reference.front == reference;
4419 bool back_same = state->dynamic.stencil_reference.back == reference;
4420
4421 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4422 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4423 return;
4424 }
4425
4426 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4427 cmd_buffer->state.dynamic.stencil_reference.front = reference;
4428 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4429 cmd_buffer->state.dynamic.stencil_reference.back = reference;
4430
4431 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
4432 }
4433
4434 void radv_CmdSetDiscardRectangleEXT(
4435 VkCommandBuffer commandBuffer,
4436 uint32_t firstDiscardRectangle,
4437 uint32_t discardRectangleCount,
4438 const VkRect2D* pDiscardRectangles)
4439 {
4440 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4441 struct radv_cmd_state *state = &cmd_buffer->state;
4442 ASSERTED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
4443
4444 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
4445 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
4446
4447 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
4448 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
4449 return;
4450 }
4451
4452 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
4453 pDiscardRectangles, discardRectangleCount);
4454
4455 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
4456 }
4457
4458 void radv_CmdSetSampleLocationsEXT(
4459 VkCommandBuffer commandBuffer,
4460 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
4461 {
4462 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4463 struct radv_cmd_state *state = &cmd_buffer->state;
4464
4465 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
4466
4467 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
4468 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
4469 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
4470 typed_memcpy(&state->dynamic.sample_location.locations[0],
4471 pSampleLocationsInfo->pSampleLocations,
4472 pSampleLocationsInfo->sampleLocationsCount);
4473
4474 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
4475 }
4476
4477 void radv_CmdSetLineStippleEXT(
4478 VkCommandBuffer commandBuffer,
4479 uint32_t lineStippleFactor,
4480 uint16_t lineStipplePattern)
4481 {
4482 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4483 struct radv_cmd_state *state = &cmd_buffer->state;
4484
4485 state->dynamic.line_stipple.factor = lineStippleFactor;
4486 state->dynamic.line_stipple.pattern = lineStipplePattern;
4487
4488 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE;
4489 }
4490
4491 void radv_CmdSetCullModeEXT(
4492 VkCommandBuffer commandBuffer,
4493 VkCullModeFlags cullMode)
4494 {
4495 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4496 struct radv_cmd_state *state = &cmd_buffer->state;
4497
4498 if (state->dynamic.cull_mode == cullMode)
4499 return;
4500
4501 state->dynamic.cull_mode = cullMode;
4502
4503 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_CULL_MODE;
4504 }
4505
4506 void radv_CmdSetFrontFaceEXT(
4507 VkCommandBuffer commandBuffer,
4508 VkFrontFace frontFace)
4509 {
4510 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4511 struct radv_cmd_state *state = &cmd_buffer->state;
4512
4513 if (state->dynamic.front_face == frontFace)
4514 return;
4515
4516 state->dynamic.front_face = frontFace;
4517
4518 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE;
4519 }
4520
4521 void radv_CmdSetPrimitiveTopologyEXT(
4522 VkCommandBuffer commandBuffer,
4523 VkPrimitiveTopology primitiveTopology)
4524 {
4525 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4526 struct radv_cmd_state *state = &cmd_buffer->state;
4527 unsigned primitive_topology = si_translate_prim(primitiveTopology);
4528
4529 if (state->dynamic.primitive_topology == primitive_topology)
4530 return;
4531
4532 state->dynamic.primitive_topology = primitive_topology;
4533
4534 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY;
4535 }
4536
4537 void radv_CmdSetViewportWithCountEXT(
4538 VkCommandBuffer commandBuffer,
4539 uint32_t viewportCount,
4540 const VkViewport* pViewports)
4541 {
4542 radv_CmdSetViewport(commandBuffer, 0, viewportCount, pViewports);
4543 }
4544
4545 void radv_CmdSetScissorWithCountEXT(
4546 VkCommandBuffer commandBuffer,
4547 uint32_t scissorCount,
4548 const VkRect2D* pScissors)
4549 {
4550 radv_CmdSetScissor(commandBuffer, 0, scissorCount, pScissors);
4551 }
4552
4553 void radv_CmdSetDepthTestEnableEXT(
4554 VkCommandBuffer commandBuffer,
4555 VkBool32 depthTestEnable)
4556
4557 {
4558 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4559 struct radv_cmd_state *state = &cmd_buffer->state;
4560
4561 if (state->dynamic.depth_test_enable == depthTestEnable)
4562 return;
4563
4564 state->dynamic.depth_test_enable = depthTestEnable;
4565
4566 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE;
4567 }
4568
4569 void radv_CmdSetDepthWriteEnableEXT(
4570 VkCommandBuffer commandBuffer,
4571 VkBool32 depthWriteEnable)
4572 {
4573 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4574 struct radv_cmd_state *state = &cmd_buffer->state;
4575
4576 if (state->dynamic.depth_write_enable == depthWriteEnable)
4577 return;
4578
4579 state->dynamic.depth_write_enable = depthWriteEnable;
4580
4581 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE;
4582 }
4583
4584 void radv_CmdSetDepthCompareOpEXT(
4585 VkCommandBuffer commandBuffer,
4586 VkCompareOp depthCompareOp)
4587 {
4588 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4589 struct radv_cmd_state *state = &cmd_buffer->state;
4590
4591 if (state->dynamic.depth_compare_op == depthCompareOp)
4592 return;
4593
4594 state->dynamic.depth_compare_op = depthCompareOp;
4595
4596 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP;
4597 }
4598
4599 void radv_CmdSetDepthBoundsTestEnableEXT(
4600 VkCommandBuffer commandBuffer,
4601 VkBool32 depthBoundsTestEnable)
4602 {
4603 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4604 struct radv_cmd_state *state = &cmd_buffer->state;
4605
4606 if (state->dynamic.depth_bounds_test_enable == depthBoundsTestEnable)
4607 return;
4608
4609 state->dynamic.depth_bounds_test_enable = depthBoundsTestEnable;
4610
4611 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE;
4612 }
4613
4614 void radv_CmdSetStencilTestEnableEXT(
4615 VkCommandBuffer commandBuffer,
4616 VkBool32 stencilTestEnable)
4617 {
4618 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4619 struct radv_cmd_state *state = &cmd_buffer->state;
4620
4621 if (state->dynamic.stencil_test_enable == stencilTestEnable)
4622 return;
4623
4624 state->dynamic.stencil_test_enable = stencilTestEnable;
4625
4626 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE;
4627 }
4628
4629 void radv_CmdSetStencilOpEXT(
4630 VkCommandBuffer commandBuffer,
4631 VkStencilFaceFlags faceMask,
4632 VkStencilOp failOp,
4633 VkStencilOp passOp,
4634 VkStencilOp depthFailOp,
4635 VkCompareOp compareOp)
4636 {
4637 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4638 struct radv_cmd_state *state = &cmd_buffer->state;
4639 bool front_same =
4640 state->dynamic.stencil_op.front.fail_op == failOp &&
4641 state->dynamic.stencil_op.front.pass_op == passOp &&
4642 state->dynamic.stencil_op.front.depth_fail_op == depthFailOp &&
4643 state->dynamic.stencil_op.front.compare_op == compareOp;
4644 bool back_same =
4645 state->dynamic.stencil_op.back.fail_op == failOp &&
4646 state->dynamic.stencil_op.back.pass_op == passOp &&
4647 state->dynamic.stencil_op.back.depth_fail_op == depthFailOp &&
4648 state->dynamic.stencil_op.back.compare_op == compareOp;
4649
4650 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4651 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same))
4652 return;
4653
4654 if (faceMask & VK_STENCIL_FACE_FRONT_BIT) {
4655 state->dynamic.stencil_op.front.fail_op = failOp;
4656 state->dynamic.stencil_op.front.pass_op = passOp;
4657 state->dynamic.stencil_op.front.depth_fail_op = depthFailOp;
4658 state->dynamic.stencil_op.front.compare_op = compareOp;
4659 }
4660
4661 if (faceMask & VK_STENCIL_FACE_BACK_BIT) {
4662 state->dynamic.stencil_op.back.fail_op = failOp;
4663 state->dynamic.stencil_op.back.pass_op = passOp;
4664 state->dynamic.stencil_op.back.depth_fail_op = depthFailOp;
4665 state->dynamic.stencil_op.back.compare_op = compareOp;
4666 }
4667
4668 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP;
4669 }
4670
4671 void radv_CmdExecuteCommands(
4672 VkCommandBuffer commandBuffer,
4673 uint32_t commandBufferCount,
4674 const VkCommandBuffer* pCmdBuffers)
4675 {
4676 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
4677
4678 assert(commandBufferCount > 0);
4679
4680 /* Emit pending flushes on primary prior to executing secondary */
4681 si_emit_cache_flush(primary);
4682
4683 for (uint32_t i = 0; i < commandBufferCount; i++) {
4684 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
4685
4686 primary->scratch_size_per_wave_needed = MAX2(primary->scratch_size_per_wave_needed,
4687 secondary->scratch_size_per_wave_needed);
4688 primary->scratch_waves_wanted = MAX2(primary->scratch_waves_wanted,
4689 secondary->scratch_waves_wanted);
4690 primary->compute_scratch_size_per_wave_needed = MAX2(primary->compute_scratch_size_per_wave_needed,
4691 secondary->compute_scratch_size_per_wave_needed);
4692 primary->compute_scratch_waves_wanted = MAX2(primary->compute_scratch_waves_wanted,
4693 secondary->compute_scratch_waves_wanted);
4694
4695 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
4696 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
4697 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
4698 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
4699 if (secondary->tess_rings_needed)
4700 primary->tess_rings_needed = true;
4701 if (secondary->sample_positions_needed)
4702 primary->sample_positions_needed = true;
4703 if (secondary->gds_needed)
4704 primary->gds_needed = true;
4705
4706 if (!secondary->state.framebuffer &&
4707 (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
4708 /* Emit the framebuffer state from primary if secondary
4709 * has been recorded without a framebuffer, otherwise
4710 * fast color/depth clears can't work.
4711 */
4712 radv_emit_framebuffer_state(primary);
4713 }
4714
4715 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
4716
4717
4718 /* When the secondary command buffer is compute only we don't
4719 * need to re-emit the current graphics pipeline.
4720 */
4721 if (secondary->state.emitted_pipeline) {
4722 primary->state.emitted_pipeline =
4723 secondary->state.emitted_pipeline;
4724 }
4725
4726 /* When the secondary command buffer is graphics only we don't
4727 * need to re-emit the current compute pipeline.
4728 */
4729 if (secondary->state.emitted_compute_pipeline) {
4730 primary->state.emitted_compute_pipeline =
4731 secondary->state.emitted_compute_pipeline;
4732 }
4733
4734 /* Only re-emit the draw packets when needed. */
4735 if (secondary->state.last_primitive_reset_en != -1) {
4736 primary->state.last_primitive_reset_en =
4737 secondary->state.last_primitive_reset_en;
4738 }
4739
4740 if (secondary->state.last_primitive_reset_index) {
4741 primary->state.last_primitive_reset_index =
4742 secondary->state.last_primitive_reset_index;
4743 }
4744
4745 if (secondary->state.last_ia_multi_vgt_param) {
4746 primary->state.last_ia_multi_vgt_param =
4747 secondary->state.last_ia_multi_vgt_param;
4748 }
4749
4750 primary->state.last_first_instance = secondary->state.last_first_instance;
4751 primary->state.last_num_instances = secondary->state.last_num_instances;
4752 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
4753 primary->state.last_sx_ps_downconvert = secondary->state.last_sx_ps_downconvert;
4754 primary->state.last_sx_blend_opt_epsilon = secondary->state.last_sx_blend_opt_epsilon;
4755 primary->state.last_sx_blend_opt_control = secondary->state.last_sx_blend_opt_control;
4756
4757 if (secondary->state.last_index_type != -1) {
4758 primary->state.last_index_type =
4759 secondary->state.last_index_type;
4760 }
4761 }
4762
4763 /* After executing commands from secondary buffers we have to dirty
4764 * some states.
4765 */
4766 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
4767 RADV_CMD_DIRTY_INDEX_BUFFER |
4768 RADV_CMD_DIRTY_DYNAMIC_ALL;
4769 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
4770 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
4771 }
4772
4773 VkResult radv_CreateCommandPool(
4774 VkDevice _device,
4775 const VkCommandPoolCreateInfo* pCreateInfo,
4776 const VkAllocationCallbacks* pAllocator,
4777 VkCommandPool* pCmdPool)
4778 {
4779 RADV_FROM_HANDLE(radv_device, device, _device);
4780 struct radv_cmd_pool *pool;
4781
4782 pool = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*pool), 8,
4783 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4784 if (pool == NULL)
4785 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4786
4787 vk_object_base_init(&device->vk, &pool->base,
4788 VK_OBJECT_TYPE_COMMAND_POOL);
4789
4790 if (pAllocator)
4791 pool->alloc = *pAllocator;
4792 else
4793 pool->alloc = device->vk.alloc;
4794
4795 list_inithead(&pool->cmd_buffers);
4796 list_inithead(&pool->free_cmd_buffers);
4797
4798 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
4799
4800 *pCmdPool = radv_cmd_pool_to_handle(pool);
4801
4802 return VK_SUCCESS;
4803
4804 }
4805
4806 void radv_DestroyCommandPool(
4807 VkDevice _device,
4808 VkCommandPool commandPool,
4809 const VkAllocationCallbacks* pAllocator)
4810 {
4811 RADV_FROM_HANDLE(radv_device, device, _device);
4812 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4813
4814 if (!pool)
4815 return;
4816
4817 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4818 &pool->cmd_buffers, pool_link) {
4819 radv_destroy_cmd_buffer(cmd_buffer);
4820 }
4821
4822 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4823 &pool->free_cmd_buffers, pool_link) {
4824 radv_destroy_cmd_buffer(cmd_buffer);
4825 }
4826
4827 vk_object_base_finish(&pool->base);
4828 vk_free2(&device->vk.alloc, pAllocator, pool);
4829 }
4830
4831 VkResult radv_ResetCommandPool(
4832 VkDevice device,
4833 VkCommandPool commandPool,
4834 VkCommandPoolResetFlags flags)
4835 {
4836 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4837 VkResult result;
4838
4839 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
4840 &pool->cmd_buffers, pool_link) {
4841 result = radv_reset_cmd_buffer(cmd_buffer);
4842 if (result != VK_SUCCESS)
4843 return result;
4844 }
4845
4846 return VK_SUCCESS;
4847 }
4848
4849 void radv_TrimCommandPool(
4850 VkDevice device,
4851 VkCommandPool commandPool,
4852 VkCommandPoolTrimFlags flags)
4853 {
4854 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4855
4856 if (!pool)
4857 return;
4858
4859 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4860 &pool->free_cmd_buffers, pool_link) {
4861 radv_destroy_cmd_buffer(cmd_buffer);
4862 }
4863 }
4864
4865 static void
4866 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
4867 uint32_t subpass_id)
4868 {
4869 struct radv_cmd_state *state = &cmd_buffer->state;
4870 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
4871
4872 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
4873 cmd_buffer->cs, 4096);
4874
4875 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
4876
4877 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
4878
4879 radv_describe_barrier_start(cmd_buffer, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC);
4880
4881 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4882 const uint32_t a = subpass->attachments[i].attachment;
4883 if (a == VK_ATTACHMENT_UNUSED)
4884 continue;
4885
4886 radv_handle_subpass_image_transition(cmd_buffer,
4887 subpass->attachments[i],
4888 true);
4889 }
4890
4891 radv_describe_barrier_end(cmd_buffer);
4892
4893 radv_cmd_buffer_clear_subpass(cmd_buffer);
4894
4895 assert(cmd_buffer->cs->cdw <= cdw_max);
4896 }
4897
4898 static void
4899 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
4900 {
4901 struct radv_cmd_state *state = &cmd_buffer->state;
4902 const struct radv_subpass *subpass = state->subpass;
4903 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
4904
4905 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4906
4907 radv_describe_barrier_start(cmd_buffer, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC);
4908
4909 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4910 const uint32_t a = subpass->attachments[i].attachment;
4911 if (a == VK_ATTACHMENT_UNUSED)
4912 continue;
4913
4914 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
4915 continue;
4916
4917 VkImageLayout layout = state->pass->attachments[a].final_layout;
4918 VkImageLayout stencil_layout = state->pass->attachments[a].stencil_final_layout;
4919 struct radv_subpass_attachment att = { a, layout, stencil_layout };
4920 radv_handle_subpass_image_transition(cmd_buffer, att, false);
4921 }
4922
4923 radv_describe_barrier_end(cmd_buffer);
4924 }
4925
4926 void
4927 radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer *cmd_buffer,
4928 const VkRenderPassBeginInfo *pRenderPassBegin)
4929 {
4930 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
4931 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
4932 VkResult result;
4933
4934 cmd_buffer->state.framebuffer = framebuffer;
4935 cmd_buffer->state.pass = pass;
4936 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
4937
4938 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
4939 if (result != VK_SUCCESS)
4940 return;
4941
4942 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
4943 if (result != VK_SUCCESS)
4944 return;
4945 }
4946
4947 void radv_CmdBeginRenderPass(
4948 VkCommandBuffer commandBuffer,
4949 const VkRenderPassBeginInfo* pRenderPassBegin,
4950 VkSubpassContents contents)
4951 {
4952 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4953
4954 radv_cmd_buffer_begin_render_pass(cmd_buffer, pRenderPassBegin);
4955
4956 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
4957 }
4958
4959 void radv_CmdBeginRenderPass2(
4960 VkCommandBuffer commandBuffer,
4961 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
4962 const VkSubpassBeginInfo* pSubpassBeginInfo)
4963 {
4964 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
4965 pSubpassBeginInfo->contents);
4966 }
4967
4968 void radv_CmdNextSubpass(
4969 VkCommandBuffer commandBuffer,
4970 VkSubpassContents contents)
4971 {
4972 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4973
4974 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
4975 radv_cmd_buffer_end_subpass(cmd_buffer);
4976 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
4977 }
4978
4979 void radv_CmdNextSubpass2(
4980 VkCommandBuffer commandBuffer,
4981 const VkSubpassBeginInfo* pSubpassBeginInfo,
4982 const VkSubpassEndInfo* pSubpassEndInfo)
4983 {
4984 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
4985 }
4986
4987 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
4988 {
4989 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
4990 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
4991 if (!radv_get_shader(pipeline, stage))
4992 continue;
4993
4994 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
4995 if (loc->sgpr_idx == -1)
4996 continue;
4997 uint32_t base_reg = pipeline->user_data_0[stage];
4998 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4999
5000 }
5001 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
5002 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
5003 if (loc->sgpr_idx != -1) {
5004 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
5005 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
5006 }
5007 }
5008 }
5009
5010 static void
5011 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
5012 uint32_t vertex_count,
5013 bool use_opaque)
5014 {
5015 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
5016 radeon_emit(cmd_buffer->cs, vertex_count);
5017 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
5018 S_0287F0_USE_OPAQUE(use_opaque));
5019 }
5020
5021 static void
5022 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
5023 uint64_t index_va,
5024 uint32_t index_count)
5025 {
5026 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
5027 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
5028 radeon_emit(cmd_buffer->cs, index_va);
5029 radeon_emit(cmd_buffer->cs, index_va >> 32);
5030 radeon_emit(cmd_buffer->cs, index_count);
5031 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
5032 }
5033
5034 static void
5035 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
5036 bool indexed,
5037 uint32_t draw_count,
5038 uint64_t count_va,
5039 uint32_t stride)
5040 {
5041 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5042 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
5043 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
5044 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id;
5045 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
5046 bool predicating = cmd_buffer->state.predicating;
5047 assert(base_reg);
5048
5049 /* just reset draw state for vertex data */
5050 cmd_buffer->state.last_first_instance = -1;
5051 cmd_buffer->state.last_num_instances = -1;
5052 cmd_buffer->state.last_vertex_offset = -1;
5053
5054 if (draw_count == 1 && !count_va && !draw_id_enable) {
5055 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
5056 PKT3_DRAW_INDIRECT, 3, predicating));
5057 radeon_emit(cs, 0);
5058 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
5059 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
5060 radeon_emit(cs, di_src_sel);
5061 } else {
5062 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
5063 PKT3_DRAW_INDIRECT_MULTI,
5064 8, predicating));
5065 radeon_emit(cs, 0);
5066 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
5067 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
5068 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
5069 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
5070 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
5071 radeon_emit(cs, draw_count); /* count */
5072 radeon_emit(cs, count_va); /* count_addr */
5073 radeon_emit(cs, count_va >> 32);
5074 radeon_emit(cs, stride); /* stride */
5075 radeon_emit(cs, di_src_sel);
5076 }
5077 }
5078
5079 static void
5080 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
5081 const struct radv_draw_info *info)
5082 {
5083 struct radv_cmd_state *state = &cmd_buffer->state;
5084 struct radeon_winsys *ws = cmd_buffer->device->ws;
5085 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5086
5087 if (info->indirect) {
5088 uint64_t va = radv_buffer_get_va(info->indirect->bo);
5089 uint64_t count_va = 0;
5090
5091 va += info->indirect->offset + info->indirect_offset;
5092
5093 radv_cs_add_buffer(ws, cs, info->indirect->bo);
5094
5095 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
5096 radeon_emit(cs, 1);
5097 radeon_emit(cs, va);
5098 radeon_emit(cs, va >> 32);
5099
5100 if (info->count_buffer) {
5101 count_va = radv_buffer_get_va(info->count_buffer->bo);
5102 count_va += info->count_buffer->offset +
5103 info->count_buffer_offset;
5104
5105 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
5106 }
5107
5108 if (!state->subpass->view_mask) {
5109 radv_cs_emit_indirect_draw_packet(cmd_buffer,
5110 info->indexed,
5111 info->count,
5112 count_va,
5113 info->stride);
5114 } else {
5115 unsigned i;
5116 for_each_bit(i, state->subpass->view_mask) {
5117 radv_emit_view_index(cmd_buffer, i);
5118
5119 radv_cs_emit_indirect_draw_packet(cmd_buffer,
5120 info->indexed,
5121 info->count,
5122 count_va,
5123 info->stride);
5124 }
5125 }
5126 } else {
5127 assert(state->pipeline->graphics.vtx_base_sgpr);
5128
5129 if (info->vertex_offset != state->last_vertex_offset ||
5130 info->first_instance != state->last_first_instance) {
5131 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
5132 state->pipeline->graphics.vtx_emit_num);
5133
5134 radeon_emit(cs, info->vertex_offset);
5135 radeon_emit(cs, info->first_instance);
5136 if (state->pipeline->graphics.vtx_emit_num == 3)
5137 radeon_emit(cs, 0);
5138 state->last_first_instance = info->first_instance;
5139 state->last_vertex_offset = info->vertex_offset;
5140 }
5141
5142 if (state->last_num_instances != info->instance_count) {
5143 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
5144 radeon_emit(cs, info->instance_count);
5145 state->last_num_instances = info->instance_count;
5146 }
5147
5148 if (info->indexed) {
5149 int index_size = radv_get_vgt_index_size(state->index_type);
5150 uint64_t index_va;
5151
5152 /* Skip draw calls with 0-sized index buffers. They
5153 * cause a hang on some chips, like Navi10-14.
5154 */
5155 if (!cmd_buffer->state.max_index_count)
5156 return;
5157
5158 index_va = state->index_va;
5159 index_va += info->first_index * index_size;
5160
5161 if (!state->subpass->view_mask) {
5162 radv_cs_emit_draw_indexed_packet(cmd_buffer,
5163 index_va,
5164 info->count);
5165 } else {
5166 unsigned i;
5167 for_each_bit(i, state->subpass->view_mask) {
5168 radv_emit_view_index(cmd_buffer, i);
5169
5170 radv_cs_emit_draw_indexed_packet(cmd_buffer,
5171 index_va,
5172 info->count);
5173 }
5174 }
5175 } else {
5176 if (!state->subpass->view_mask) {
5177 radv_cs_emit_draw_packet(cmd_buffer,
5178 info->count,
5179 !!info->strmout_buffer);
5180 } else {
5181 unsigned i;
5182 for_each_bit(i, state->subpass->view_mask) {
5183 radv_emit_view_index(cmd_buffer, i);
5184
5185 radv_cs_emit_draw_packet(cmd_buffer,
5186 info->count,
5187 !!info->strmout_buffer);
5188 }
5189 }
5190 }
5191 }
5192 }
5193
5194 /*
5195 * Vega and raven have a bug which triggers if there are multiple context
5196 * register contexts active at the same time with different scissor values.
5197 *
5198 * There are two possible workarounds:
5199 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
5200 * there is only ever 1 active set of scissor values at the same time.
5201 *
5202 * 2) Whenever the hardware switches contexts we have to set the scissor
5203 * registers again even if it is a noop. That way the new context gets
5204 * the correct scissor values.
5205 *
5206 * This implements option 2. radv_need_late_scissor_emission needs to
5207 * return true on affected HW if radv_emit_all_graphics_states sets
5208 * any context registers.
5209 */
5210 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
5211 const struct radv_draw_info *info)
5212 {
5213 struct radv_cmd_state *state = &cmd_buffer->state;
5214
5215 if (!cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
5216 return false;
5217
5218 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
5219 return true;
5220
5221 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
5222
5223 /* Index, vertex and streamout buffers don't change context regs, and
5224 * pipeline is already handled.
5225 */
5226 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
5227 RADV_CMD_DIRTY_VERTEX_BUFFER |
5228 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
5229 RADV_CMD_DIRTY_PIPELINE);
5230
5231 if (cmd_buffer->state.dirty & used_states)
5232 return true;
5233
5234 uint32_t primitive_reset_index =
5235 radv_get_primitive_reset_index(cmd_buffer);
5236
5237 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
5238 primitive_reset_index != state->last_primitive_reset_index)
5239 return true;
5240
5241 return false;
5242 }
5243
5244 static void
5245 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
5246 const struct radv_draw_info *info)
5247 {
5248 bool late_scissor_emission;
5249
5250 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
5251 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
5252 radv_emit_rbplus_state(cmd_buffer);
5253
5254 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
5255 radv_emit_graphics_pipeline(cmd_buffer);
5256
5257 /* This should be before the cmd_buffer->state.dirty is cleared
5258 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
5259 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
5260 late_scissor_emission =
5261 radv_need_late_scissor_emission(cmd_buffer, info);
5262
5263 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
5264 radv_emit_framebuffer_state(cmd_buffer);
5265
5266 if (info->indexed) {
5267 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
5268 radv_emit_index_buffer(cmd_buffer, info->indirect);
5269 } else {
5270 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
5271 * so the state must be re-emitted before the next indexed
5272 * draw.
5273 */
5274 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
5275 cmd_buffer->state.last_index_type = -1;
5276 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
5277 }
5278 }
5279
5280 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
5281
5282 radv_emit_draw_registers(cmd_buffer, info);
5283
5284 if (late_scissor_emission)
5285 radv_emit_scissor(cmd_buffer);
5286 }
5287
5288 static void
5289 radv_draw(struct radv_cmd_buffer *cmd_buffer,
5290 const struct radv_draw_info *info)
5291 {
5292 struct radeon_info *rad_info =
5293 &cmd_buffer->device->physical_device->rad_info;
5294 bool has_prefetch =
5295 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
5296 bool pipeline_is_dirty =
5297 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
5298 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
5299
5300 ASSERTED unsigned cdw_max =
5301 radeon_check_space(cmd_buffer->device->ws,
5302 cmd_buffer->cs, 4096);
5303
5304 if (likely(!info->indirect)) {
5305 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
5306 * no workaround for indirect draws, but we can at least skip
5307 * direct draws.
5308 */
5309 if (unlikely(!info->instance_count))
5310 return;
5311
5312 /* Handle count == 0. */
5313 if (unlikely(!info->count && !info->strmout_buffer))
5314 return;
5315 }
5316
5317 radv_describe_draw(cmd_buffer);
5318
5319 /* Use optimal packet order based on whether we need to sync the
5320 * pipeline.
5321 */
5322 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5323 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5324 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
5325 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
5326 /* If we have to wait for idle, set all states first, so that
5327 * all SET packets are processed in parallel with previous draw
5328 * calls. Then upload descriptors, set shader pointers, and
5329 * draw, and prefetch at the end. This ensures that the time
5330 * the CUs are idle is very short. (there are only SET_SH
5331 * packets between the wait and the draw)
5332 */
5333 radv_emit_all_graphics_states(cmd_buffer, info);
5334 si_emit_cache_flush(cmd_buffer);
5335 /* <-- CUs are idle here --> */
5336
5337 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
5338
5339 radv_emit_draw_packets(cmd_buffer, info);
5340 /* <-- CUs are busy here --> */
5341
5342 /* Start prefetches after the draw has been started. Both will
5343 * run in parallel, but starting the draw first is more
5344 * important.
5345 */
5346 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
5347 radv_emit_prefetch_L2(cmd_buffer,
5348 cmd_buffer->state.pipeline, false);
5349 }
5350 } else {
5351 /* If we don't wait for idle, start prefetches first, then set
5352 * states, and draw at the end.
5353 */
5354 si_emit_cache_flush(cmd_buffer);
5355
5356 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
5357 /* Only prefetch the vertex shader and VBO descriptors
5358 * in order to start the draw as soon as possible.
5359 */
5360 radv_emit_prefetch_L2(cmd_buffer,
5361 cmd_buffer->state.pipeline, true);
5362 }
5363
5364 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
5365
5366 radv_emit_all_graphics_states(cmd_buffer, info);
5367 radv_emit_draw_packets(cmd_buffer, info);
5368
5369 /* Prefetch the remaining shaders after the draw has been
5370 * started.
5371 */
5372 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
5373 radv_emit_prefetch_L2(cmd_buffer,
5374 cmd_buffer->state.pipeline, false);
5375 }
5376 }
5377
5378 /* Workaround for a VGT hang when streamout is enabled.
5379 * It must be done after drawing.
5380 */
5381 if (cmd_buffer->state.streamout.streamout_enabled &&
5382 (rad_info->family == CHIP_HAWAII ||
5383 rad_info->family == CHIP_TONGA ||
5384 rad_info->family == CHIP_FIJI)) {
5385 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
5386 }
5387
5388 assert(cmd_buffer->cs->cdw <= cdw_max);
5389 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
5390 }
5391
5392 void radv_CmdDraw(
5393 VkCommandBuffer commandBuffer,
5394 uint32_t vertexCount,
5395 uint32_t instanceCount,
5396 uint32_t firstVertex,
5397 uint32_t firstInstance)
5398 {
5399 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5400 struct radv_draw_info info = {};
5401
5402 info.count = vertexCount;
5403 info.instance_count = instanceCount;
5404 info.first_instance = firstInstance;
5405 info.vertex_offset = firstVertex;
5406
5407 radv_draw(cmd_buffer, &info);
5408 }
5409
5410 void radv_CmdDrawIndexed(
5411 VkCommandBuffer commandBuffer,
5412 uint32_t indexCount,
5413 uint32_t instanceCount,
5414 uint32_t firstIndex,
5415 int32_t vertexOffset,
5416 uint32_t firstInstance)
5417 {
5418 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5419 struct radv_draw_info info = {};
5420
5421 info.indexed = true;
5422 info.count = indexCount;
5423 info.instance_count = instanceCount;
5424 info.first_index = firstIndex;
5425 info.vertex_offset = vertexOffset;
5426 info.first_instance = firstInstance;
5427
5428 radv_draw(cmd_buffer, &info);
5429 }
5430
5431 void radv_CmdDrawIndirect(
5432 VkCommandBuffer commandBuffer,
5433 VkBuffer _buffer,
5434 VkDeviceSize offset,
5435 uint32_t drawCount,
5436 uint32_t stride)
5437 {
5438 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5439 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5440 struct radv_draw_info info = {};
5441
5442 info.count = drawCount;
5443 info.indirect = buffer;
5444 info.indirect_offset = offset;
5445 info.stride = stride;
5446
5447 radv_draw(cmd_buffer, &info);
5448 }
5449
5450 void radv_CmdDrawIndexedIndirect(
5451 VkCommandBuffer commandBuffer,
5452 VkBuffer _buffer,
5453 VkDeviceSize offset,
5454 uint32_t drawCount,
5455 uint32_t stride)
5456 {
5457 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5458 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5459 struct radv_draw_info info = {};
5460
5461 info.indexed = true;
5462 info.count = drawCount;
5463 info.indirect = buffer;
5464 info.indirect_offset = offset;
5465 info.stride = stride;
5466
5467 radv_draw(cmd_buffer, &info);
5468 }
5469
5470 void radv_CmdDrawIndirectCount(
5471 VkCommandBuffer commandBuffer,
5472 VkBuffer _buffer,
5473 VkDeviceSize offset,
5474 VkBuffer _countBuffer,
5475 VkDeviceSize countBufferOffset,
5476 uint32_t maxDrawCount,
5477 uint32_t stride)
5478 {
5479 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5480 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5481 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
5482 struct radv_draw_info info = {};
5483
5484 info.count = maxDrawCount;
5485 info.indirect = buffer;
5486 info.indirect_offset = offset;
5487 info.count_buffer = count_buffer;
5488 info.count_buffer_offset = countBufferOffset;
5489 info.stride = stride;
5490
5491 radv_draw(cmd_buffer, &info);
5492 }
5493
5494 void radv_CmdDrawIndexedIndirectCount(
5495 VkCommandBuffer commandBuffer,
5496 VkBuffer _buffer,
5497 VkDeviceSize offset,
5498 VkBuffer _countBuffer,
5499 VkDeviceSize countBufferOffset,
5500 uint32_t maxDrawCount,
5501 uint32_t stride)
5502 {
5503 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5504 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5505 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
5506 struct radv_draw_info info = {};
5507
5508 info.indexed = true;
5509 info.count = maxDrawCount;
5510 info.indirect = buffer;
5511 info.indirect_offset = offset;
5512 info.count_buffer = count_buffer;
5513 info.count_buffer_offset = countBufferOffset;
5514 info.stride = stride;
5515
5516 radv_draw(cmd_buffer, &info);
5517 }
5518
5519 struct radv_dispatch_info {
5520 /**
5521 * Determine the layout of the grid (in block units) to be used.
5522 */
5523 uint32_t blocks[3];
5524
5525 /**
5526 * A starting offset for the grid. If unaligned is set, the offset
5527 * must still be aligned.
5528 */
5529 uint32_t offsets[3];
5530 /**
5531 * Whether it's an unaligned compute dispatch.
5532 */
5533 bool unaligned;
5534
5535 /**
5536 * Indirect compute parameters resource.
5537 */
5538 struct radv_buffer *indirect;
5539 uint64_t indirect_offset;
5540 };
5541
5542 static void
5543 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
5544 const struct radv_dispatch_info *info)
5545 {
5546 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
5547 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5548 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
5549 struct radeon_winsys *ws = cmd_buffer->device->ws;
5550 bool predicating = cmd_buffer->state.predicating;
5551 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5552 struct radv_userdata_info *loc;
5553
5554 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
5555 AC_UD_CS_GRID_SIZE);
5556
5557 ASSERTED unsigned cdw_max = radeon_check_space(ws, cs, 25);
5558
5559 if (compute_shader->info.wave_size == 32) {
5560 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
5561 dispatch_initiator |= S_00B800_CS_W32_EN(1);
5562 }
5563
5564 if (info->indirect) {
5565 uint64_t va = radv_buffer_get_va(info->indirect->bo);
5566
5567 va += info->indirect->offset + info->indirect_offset;
5568
5569 radv_cs_add_buffer(ws, cs, info->indirect->bo);
5570
5571 if (loc->sgpr_idx != -1) {
5572 for (unsigned i = 0; i < 3; ++i) {
5573 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5574 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5575 COPY_DATA_DST_SEL(COPY_DATA_REG));
5576 radeon_emit(cs, (va + 4 * i));
5577 radeon_emit(cs, (va + 4 * i) >> 32);
5578 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
5579 + loc->sgpr_idx * 4) >> 2) + i);
5580 radeon_emit(cs, 0);
5581 }
5582 }
5583
5584 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
5585 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
5586 PKT3_SHADER_TYPE_S(1));
5587 radeon_emit(cs, va);
5588 radeon_emit(cs, va >> 32);
5589 radeon_emit(cs, dispatch_initiator);
5590 } else {
5591 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
5592 PKT3_SHADER_TYPE_S(1));
5593 radeon_emit(cs, 1);
5594 radeon_emit(cs, va);
5595 radeon_emit(cs, va >> 32);
5596
5597 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
5598 PKT3_SHADER_TYPE_S(1));
5599 radeon_emit(cs, 0);
5600 radeon_emit(cs, dispatch_initiator);
5601 }
5602 } else {
5603 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
5604 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
5605
5606 if (info->unaligned) {
5607 unsigned *cs_block_size = compute_shader->info.cs.block_size;
5608 unsigned remainder[3];
5609
5610 /* If aligned, these should be an entire block size,
5611 * not 0.
5612 */
5613 remainder[0] = blocks[0] + cs_block_size[0] -
5614 align_u32_npot(blocks[0], cs_block_size[0]);
5615 remainder[1] = blocks[1] + cs_block_size[1] -
5616 align_u32_npot(blocks[1], cs_block_size[1]);
5617 remainder[2] = blocks[2] + cs_block_size[2] -
5618 align_u32_npot(blocks[2], cs_block_size[2]);
5619
5620 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
5621 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
5622 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
5623
5624 for(unsigned i = 0; i < 3; ++i) {
5625 assert(offsets[i] % cs_block_size[i] == 0);
5626 offsets[i] /= cs_block_size[i];
5627 }
5628
5629 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5630 radeon_emit(cs,
5631 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
5632 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
5633 radeon_emit(cs,
5634 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
5635 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
5636 radeon_emit(cs,
5637 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
5638 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
5639
5640 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
5641 }
5642
5643 if (loc->sgpr_idx != -1) {
5644 assert(loc->num_sgprs == 3);
5645
5646 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
5647 loc->sgpr_idx * 4, 3);
5648 radeon_emit(cs, blocks[0]);
5649 radeon_emit(cs, blocks[1]);
5650 radeon_emit(cs, blocks[2]);
5651 }
5652
5653 if (offsets[0] || offsets[1] || offsets[2]) {
5654 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
5655 radeon_emit(cs, offsets[0]);
5656 radeon_emit(cs, offsets[1]);
5657 radeon_emit(cs, offsets[2]);
5658
5659 /* The blocks in the packet are not counts but end values. */
5660 for (unsigned i = 0; i < 3; ++i)
5661 blocks[i] += offsets[i];
5662 } else {
5663 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
5664 }
5665
5666 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
5667 PKT3_SHADER_TYPE_S(1));
5668 radeon_emit(cs, blocks[0]);
5669 radeon_emit(cs, blocks[1]);
5670 radeon_emit(cs, blocks[2]);
5671 radeon_emit(cs, dispatch_initiator);
5672 }
5673
5674 assert(cmd_buffer->cs->cdw <= cdw_max);
5675 }
5676
5677 static void
5678 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
5679 {
5680 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5681 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5682 }
5683
5684 static void
5685 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
5686 const struct radv_dispatch_info *info)
5687 {
5688 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
5689 bool has_prefetch =
5690 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
5691 bool pipeline_is_dirty = pipeline &&
5692 pipeline != cmd_buffer->state.emitted_compute_pipeline;
5693
5694 radv_describe_dispatch(cmd_buffer, 8, 8, 8);
5695
5696 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5697 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5698 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
5699 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
5700 /* If we have to wait for idle, set all states first, so that
5701 * all SET packets are processed in parallel with previous draw
5702 * calls. Then upload descriptors, set shader pointers, and
5703 * dispatch, and prefetch at the end. This ensures that the
5704 * time the CUs are idle is very short. (there are only SET_SH
5705 * packets between the wait and the draw)
5706 */
5707 radv_emit_compute_pipeline(cmd_buffer);
5708 si_emit_cache_flush(cmd_buffer);
5709 /* <-- CUs are idle here --> */
5710
5711 radv_upload_compute_shader_descriptors(cmd_buffer);
5712
5713 radv_emit_dispatch_packets(cmd_buffer, info);
5714 /* <-- CUs are busy here --> */
5715
5716 /* Start prefetches after the dispatch has been started. Both
5717 * will run in parallel, but starting the dispatch first is
5718 * more important.
5719 */
5720 if (has_prefetch && pipeline_is_dirty) {
5721 radv_emit_shader_prefetch(cmd_buffer,
5722 pipeline->shaders[MESA_SHADER_COMPUTE]);
5723 }
5724 } else {
5725 /* If we don't wait for idle, start prefetches first, then set
5726 * states, and dispatch at the end.
5727 */
5728 si_emit_cache_flush(cmd_buffer);
5729
5730 if (has_prefetch && pipeline_is_dirty) {
5731 radv_emit_shader_prefetch(cmd_buffer,
5732 pipeline->shaders[MESA_SHADER_COMPUTE]);
5733 }
5734
5735 radv_upload_compute_shader_descriptors(cmd_buffer);
5736
5737 radv_emit_compute_pipeline(cmd_buffer);
5738 radv_emit_dispatch_packets(cmd_buffer, info);
5739 }
5740
5741 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
5742 }
5743
5744 void radv_CmdDispatchBase(
5745 VkCommandBuffer commandBuffer,
5746 uint32_t base_x,
5747 uint32_t base_y,
5748 uint32_t base_z,
5749 uint32_t x,
5750 uint32_t y,
5751 uint32_t z)
5752 {
5753 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5754 struct radv_dispatch_info info = {};
5755
5756 info.blocks[0] = x;
5757 info.blocks[1] = y;
5758 info.blocks[2] = z;
5759
5760 info.offsets[0] = base_x;
5761 info.offsets[1] = base_y;
5762 info.offsets[2] = base_z;
5763 radv_dispatch(cmd_buffer, &info);
5764 }
5765
5766 void radv_CmdDispatch(
5767 VkCommandBuffer commandBuffer,
5768 uint32_t x,
5769 uint32_t y,
5770 uint32_t z)
5771 {
5772 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
5773 }
5774
5775 void radv_CmdDispatchIndirect(
5776 VkCommandBuffer commandBuffer,
5777 VkBuffer _buffer,
5778 VkDeviceSize offset)
5779 {
5780 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5781 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5782 struct radv_dispatch_info info = {};
5783
5784 info.indirect = buffer;
5785 info.indirect_offset = offset;
5786
5787 radv_dispatch(cmd_buffer, &info);
5788 }
5789
5790 void radv_unaligned_dispatch(
5791 struct radv_cmd_buffer *cmd_buffer,
5792 uint32_t x,
5793 uint32_t y,
5794 uint32_t z)
5795 {
5796 struct radv_dispatch_info info = {};
5797
5798 info.blocks[0] = x;
5799 info.blocks[1] = y;
5800 info.blocks[2] = z;
5801 info.unaligned = 1;
5802
5803 radv_dispatch(cmd_buffer, &info);
5804 }
5805
5806 void
5807 radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer *cmd_buffer)
5808 {
5809 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
5810 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
5811
5812 cmd_buffer->state.pass = NULL;
5813 cmd_buffer->state.subpass = NULL;
5814 cmd_buffer->state.attachments = NULL;
5815 cmd_buffer->state.framebuffer = NULL;
5816 cmd_buffer->state.subpass_sample_locs = NULL;
5817 }
5818
5819 void radv_CmdEndRenderPass(
5820 VkCommandBuffer commandBuffer)
5821 {
5822 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5823
5824 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
5825
5826 radv_cmd_buffer_end_subpass(cmd_buffer);
5827
5828 radv_cmd_buffer_end_render_pass(cmd_buffer);
5829 }
5830
5831 void radv_CmdEndRenderPass2(
5832 VkCommandBuffer commandBuffer,
5833 const VkSubpassEndInfo* pSubpassEndInfo)
5834 {
5835 radv_CmdEndRenderPass(commandBuffer);
5836 }
5837
5838 /*
5839 * For HTILE we have the following interesting clear words:
5840 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5841 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5842 * 0xfffffff0: Clear depth to 1.0
5843 * 0x00000000: Clear depth to 0.0
5844 */
5845 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
5846 struct radv_image *image,
5847 const VkImageSubresourceRange *range)
5848 {
5849 assert(range->baseMipLevel == 0);
5850 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
5851 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
5852 struct radv_cmd_state *state = &cmd_buffer->state;
5853 uint32_t htile_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5854 VkClearDepthStencilValue value = {};
5855 struct radv_barrier_data barrier = {};
5856
5857 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5858 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5859
5860 barrier.layout_transitions.init_mask_ram = 1;
5861 radv_describe_layout_transition(cmd_buffer, &barrier);
5862
5863 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, htile_value);
5864
5865 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5866
5867 if (vk_format_is_stencil(image->vk_format))
5868 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
5869
5870 radv_set_ds_clear_metadata(cmd_buffer, image, range, value, aspects);
5871
5872 if (radv_image_is_tc_compat_htile(image)) {
5873 /* Initialize the TC-compat metada value to 0 because by
5874 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5875 * need have to conditionally update its value when performing
5876 * a fast depth clear.
5877 */
5878 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, range, 0);
5879 }
5880 }
5881
5882 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
5883 struct radv_image *image,
5884 VkImageLayout src_layout,
5885 bool src_render_loop,
5886 VkImageLayout dst_layout,
5887 bool dst_render_loop,
5888 unsigned src_queue_mask,
5889 unsigned dst_queue_mask,
5890 const VkImageSubresourceRange *range,
5891 struct radv_sample_locations_state *sample_locs)
5892 {
5893 if (!radv_image_has_htile(image))
5894 return;
5895
5896 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5897 radv_initialize_htile(cmd_buffer, image, range);
5898 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5899 radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5900 radv_initialize_htile(cmd_buffer, image, range);
5901 } else if (radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5902 !radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5903 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5904 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5905
5906 radv_decompress_depth_stencil(cmd_buffer, image, range,
5907 sample_locs);
5908
5909 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5910 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5911 }
5912 }
5913
5914 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
5915 struct radv_image *image,
5916 const VkImageSubresourceRange *range,
5917 uint32_t value)
5918 {
5919 struct radv_cmd_state *state = &cmd_buffer->state;
5920 struct radv_barrier_data barrier = {};
5921
5922 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5923 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5924
5925 barrier.layout_transitions.init_mask_ram = 1;
5926 radv_describe_layout_transition(cmd_buffer, &barrier);
5927
5928 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
5929
5930 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5931 }
5932
5933 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
5934 struct radv_image *image,
5935 const VkImageSubresourceRange *range)
5936 {
5937 struct radv_cmd_state *state = &cmd_buffer->state;
5938 static const uint32_t fmask_clear_values[4] = {
5939 0x00000000,
5940 0x02020202,
5941 0xE4E4E4E4,
5942 0x76543210
5943 };
5944 uint32_t log2_samples = util_logbase2(image->info.samples);
5945 uint32_t value = fmask_clear_values[log2_samples];
5946 struct radv_barrier_data barrier = {};
5947
5948 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5949 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5950
5951 barrier.layout_transitions.init_mask_ram = 1;
5952 radv_describe_layout_transition(cmd_buffer, &barrier);
5953
5954 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
5955
5956 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5957 }
5958
5959 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
5960 struct radv_image *image,
5961 const VkImageSubresourceRange *range, uint32_t value)
5962 {
5963 struct radv_cmd_state *state = &cmd_buffer->state;
5964 struct radv_barrier_data barrier = {};
5965 unsigned size = 0;
5966
5967 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5968 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5969
5970 barrier.layout_transitions.init_mask_ram = 1;
5971 radv_describe_layout_transition(cmd_buffer, &barrier);
5972
5973 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
5974
5975 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
5976 /* When DCC is enabled with mipmaps, some levels might not
5977 * support fast clears and we have to initialize them as "fully
5978 * expanded".
5979 */
5980 /* Compute the size of all fast clearable DCC levels. */
5981 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
5982 struct legacy_surf_level *surf_level =
5983 &image->planes[0].surface.u.legacy.level[i];
5984 unsigned dcc_fast_clear_size =
5985 surf_level->dcc_slice_fast_clear_size * image->info.array_size;
5986
5987 if (!dcc_fast_clear_size)
5988 break;
5989
5990 size = surf_level->dcc_offset + dcc_fast_clear_size;
5991 }
5992
5993 /* Initialize the mipmap levels without DCC. */
5994 if (size != image->planes[0].surface.dcc_size) {
5995 state->flush_bits |=
5996 radv_fill_buffer(cmd_buffer, image->bo,
5997 image->offset + image->planes[0].surface.dcc_offset + size,
5998 image->planes[0].surface.dcc_size - size,
5999 0xffffffff);
6000 }
6001 }
6002
6003 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
6004 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
6005 }
6006
6007 /**
6008 * Initialize DCC/FMASK/CMASK metadata for a color image.
6009 */
6010 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
6011 struct radv_image *image,
6012 VkImageLayout src_layout,
6013 bool src_render_loop,
6014 VkImageLayout dst_layout,
6015 bool dst_render_loop,
6016 unsigned src_queue_mask,
6017 unsigned dst_queue_mask,
6018 const VkImageSubresourceRange *range)
6019 {
6020 if (radv_image_has_cmask(image)) {
6021 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
6022
6023 /* TODO: clarify this. */
6024 if (radv_image_has_fmask(image)) {
6025 value = 0xccccccccu;
6026 }
6027
6028 radv_initialise_cmask(cmd_buffer, image, range, value);
6029 }
6030
6031 if (radv_image_has_fmask(image)) {
6032 radv_initialize_fmask(cmd_buffer, image, range);
6033 }
6034
6035 if (radv_dcc_enabled(image, range->baseMipLevel)) {
6036 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
6037 bool need_decompress_pass = false;
6038
6039 if (radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout,
6040 dst_render_loop,
6041 dst_queue_mask)) {
6042 value = 0x20202020u;
6043 need_decompress_pass = true;
6044 }
6045
6046 radv_initialize_dcc(cmd_buffer, image, range, value);
6047
6048 radv_update_fce_metadata(cmd_buffer, image, range,
6049 need_decompress_pass);
6050 }
6051
6052 if (radv_image_has_cmask(image) ||
6053 radv_dcc_enabled(image, range->baseMipLevel)) {
6054 uint32_t color_values[2] = {};
6055 radv_set_color_clear_metadata(cmd_buffer, image, range,
6056 color_values);
6057 }
6058 }
6059
6060 /**
6061 * Handle color image transitions for DCC/FMASK/CMASK.
6062 */
6063 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
6064 struct radv_image *image,
6065 VkImageLayout src_layout,
6066 bool src_render_loop,
6067 VkImageLayout dst_layout,
6068 bool dst_render_loop,
6069 unsigned src_queue_mask,
6070 unsigned dst_queue_mask,
6071 const VkImageSubresourceRange *range)
6072 {
6073 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
6074 radv_init_color_image_metadata(cmd_buffer, image,
6075 src_layout, src_render_loop,
6076 dst_layout, dst_render_loop,
6077 src_queue_mask, dst_queue_mask,
6078 range);
6079 return;
6080 }
6081
6082 if (radv_dcc_enabled(image, range->baseMipLevel)) {
6083 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
6084 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
6085 } else if (radv_layout_dcc_compressed(cmd_buffer->device, image, src_layout, src_render_loop, src_queue_mask) &&
6086 !radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout, dst_render_loop, dst_queue_mask)) {
6087 radv_decompress_dcc(cmd_buffer, image, range);
6088 } else if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
6089 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
6090 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
6091 }
6092 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
6093 bool fce_eliminate = false, fmask_expand = false;
6094
6095 if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
6096 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
6097 fce_eliminate = true;
6098 }
6099
6100 if (radv_image_has_fmask(image)) {
6101 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
6102 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
6103 /* A FMASK decompress is required before doing
6104 * a MSAA decompress using FMASK.
6105 */
6106 fmask_expand = true;
6107 }
6108 }
6109
6110 if (fce_eliminate || fmask_expand)
6111 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
6112
6113 if (fmask_expand) {
6114 struct radv_barrier_data barrier = {};
6115 barrier.layout_transitions.fmask_color_expand = 1;
6116 radv_describe_layout_transition(cmd_buffer, &barrier);
6117
6118 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
6119 }
6120 }
6121 }
6122
6123 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
6124 struct radv_image *image,
6125 VkImageLayout src_layout,
6126 bool src_render_loop,
6127 VkImageLayout dst_layout,
6128 bool dst_render_loop,
6129 uint32_t src_family,
6130 uint32_t dst_family,
6131 const VkImageSubresourceRange *range,
6132 struct radv_sample_locations_state *sample_locs)
6133 {
6134 if (image->exclusive && src_family != dst_family) {
6135 /* This is an acquire or a release operation and there will be
6136 * a corresponding release/acquire. Do the transition in the
6137 * most flexible queue. */
6138
6139 assert(src_family == cmd_buffer->queue_family_index ||
6140 dst_family == cmd_buffer->queue_family_index);
6141
6142 if (src_family == VK_QUEUE_FAMILY_EXTERNAL ||
6143 src_family == VK_QUEUE_FAMILY_FOREIGN_EXT)
6144 return;
6145
6146 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
6147 return;
6148
6149 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
6150 (src_family == RADV_QUEUE_GENERAL ||
6151 dst_family == RADV_QUEUE_GENERAL))
6152 return;
6153 }
6154
6155 if (src_layout == dst_layout)
6156 return;
6157
6158 unsigned src_queue_mask =
6159 radv_image_queue_family_mask(image, src_family,
6160 cmd_buffer->queue_family_index);
6161 unsigned dst_queue_mask =
6162 radv_image_queue_family_mask(image, dst_family,
6163 cmd_buffer->queue_family_index);
6164
6165 if (vk_format_is_depth(image->vk_format)) {
6166 radv_handle_depth_image_transition(cmd_buffer, image,
6167 src_layout, src_render_loop,
6168 dst_layout, dst_render_loop,
6169 src_queue_mask, dst_queue_mask,
6170 range, sample_locs);
6171 } else {
6172 radv_handle_color_image_transition(cmd_buffer, image,
6173 src_layout, src_render_loop,
6174 dst_layout, dst_render_loop,
6175 src_queue_mask, dst_queue_mask,
6176 range);
6177 }
6178 }
6179
6180 struct radv_barrier_info {
6181 enum rgp_barrier_reason reason;
6182 uint32_t eventCount;
6183 const VkEvent *pEvents;
6184 VkPipelineStageFlags srcStageMask;
6185 VkPipelineStageFlags dstStageMask;
6186 };
6187
6188 static void
6189 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
6190 uint32_t memoryBarrierCount,
6191 const VkMemoryBarrier *pMemoryBarriers,
6192 uint32_t bufferMemoryBarrierCount,
6193 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
6194 uint32_t imageMemoryBarrierCount,
6195 const VkImageMemoryBarrier *pImageMemoryBarriers,
6196 const struct radv_barrier_info *info)
6197 {
6198 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6199 enum radv_cmd_flush_bits src_flush_bits = 0;
6200 enum radv_cmd_flush_bits dst_flush_bits = 0;
6201
6202 radv_describe_barrier_start(cmd_buffer, info->reason);
6203
6204 for (unsigned i = 0; i < info->eventCount; ++i) {
6205 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
6206 uint64_t va = radv_buffer_get_va(event->bo);
6207
6208 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
6209
6210 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
6211
6212 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
6213 assert(cmd_buffer->cs->cdw <= cdw_max);
6214 }
6215
6216 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
6217 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
6218 NULL);
6219 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
6220 NULL);
6221 }
6222
6223 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
6224 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
6225 NULL);
6226 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
6227 NULL);
6228 }
6229
6230 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
6231 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
6232
6233 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
6234 image);
6235 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
6236 image);
6237 }
6238
6239 /* The Vulkan spec 1.1.98 says:
6240 *
6241 * "An execution dependency with only
6242 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
6243 * will only prevent that stage from executing in subsequently
6244 * submitted commands. As this stage does not perform any actual
6245 * execution, this is not observable - in effect, it does not delay
6246 * processing of subsequent commands. Similarly an execution dependency
6247 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
6248 * will effectively not wait for any prior commands to complete."
6249 */
6250 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
6251 radv_stage_flush(cmd_buffer, info->srcStageMask);
6252 cmd_buffer->state.flush_bits |= src_flush_bits;
6253
6254 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
6255 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
6256
6257 const struct VkSampleLocationsInfoEXT *sample_locs_info =
6258 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
6259 SAMPLE_LOCATIONS_INFO_EXT);
6260 struct radv_sample_locations_state sample_locations = {};
6261
6262 if (sample_locs_info) {
6263 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
6264 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
6265 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
6266 sample_locations.count = sample_locs_info->sampleLocationsCount;
6267 typed_memcpy(&sample_locations.locations[0],
6268 sample_locs_info->pSampleLocations,
6269 sample_locs_info->sampleLocationsCount);
6270 }
6271
6272 radv_handle_image_transition(cmd_buffer, image,
6273 pImageMemoryBarriers[i].oldLayout,
6274 false, /* Outside of a renderpass we are never in a renderloop */
6275 pImageMemoryBarriers[i].newLayout,
6276 false, /* Outside of a renderpass we are never in a renderloop */
6277 pImageMemoryBarriers[i].srcQueueFamilyIndex,
6278 pImageMemoryBarriers[i].dstQueueFamilyIndex,
6279 &pImageMemoryBarriers[i].subresourceRange,
6280 sample_locs_info ? &sample_locations : NULL);
6281 }
6282
6283 /* Make sure CP DMA is idle because the driver might have performed a
6284 * DMA operation for copying or filling buffers/images.
6285 */
6286 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
6287 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
6288 si_cp_dma_wait_for_idle(cmd_buffer);
6289
6290 cmd_buffer->state.flush_bits |= dst_flush_bits;
6291
6292 radv_describe_barrier_end(cmd_buffer);
6293 }
6294
6295 void radv_CmdPipelineBarrier(
6296 VkCommandBuffer commandBuffer,
6297 VkPipelineStageFlags srcStageMask,
6298 VkPipelineStageFlags destStageMask,
6299 VkBool32 byRegion,
6300 uint32_t memoryBarrierCount,
6301 const VkMemoryBarrier* pMemoryBarriers,
6302 uint32_t bufferMemoryBarrierCount,
6303 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
6304 uint32_t imageMemoryBarrierCount,
6305 const VkImageMemoryBarrier* pImageMemoryBarriers)
6306 {
6307 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6308 struct radv_barrier_info info;
6309
6310 info.reason = RGP_BARRIER_EXTERNAL_CMD_PIPELINE_BARRIER;
6311 info.eventCount = 0;
6312 info.pEvents = NULL;
6313 info.srcStageMask = srcStageMask;
6314 info.dstStageMask = destStageMask;
6315
6316 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
6317 bufferMemoryBarrierCount, pBufferMemoryBarriers,
6318 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
6319 }
6320
6321
6322 static void write_event(struct radv_cmd_buffer *cmd_buffer,
6323 struct radv_event *event,
6324 VkPipelineStageFlags stageMask,
6325 unsigned value)
6326 {
6327 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6328 uint64_t va = radv_buffer_get_va(event->bo);
6329
6330 si_emit_cache_flush(cmd_buffer);
6331
6332 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
6333
6334 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
6335
6336 /* Flags that only require a top-of-pipe event. */
6337 VkPipelineStageFlags top_of_pipe_flags =
6338 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
6339
6340 /* Flags that only require a post-index-fetch event. */
6341 VkPipelineStageFlags post_index_fetch_flags =
6342 top_of_pipe_flags |
6343 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
6344 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
6345
6346 /* Make sure CP DMA is idle because the driver might have performed a
6347 * DMA operation for copying or filling buffers/images.
6348 */
6349 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
6350 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
6351 si_cp_dma_wait_for_idle(cmd_buffer);
6352
6353 /* TODO: Emit EOS events for syncing PS/CS stages. */
6354
6355 if (!(stageMask & ~top_of_pipe_flags)) {
6356 /* Just need to sync the PFP engine. */
6357 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
6358 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
6359 S_370_WR_CONFIRM(1) |
6360 S_370_ENGINE_SEL(V_370_PFP));
6361 radeon_emit(cs, va);
6362 radeon_emit(cs, va >> 32);
6363 radeon_emit(cs, value);
6364 } else if (!(stageMask & ~post_index_fetch_flags)) {
6365 /* Sync ME because PFP reads index and indirect buffers. */
6366 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
6367 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
6368 S_370_WR_CONFIRM(1) |
6369 S_370_ENGINE_SEL(V_370_ME));
6370 radeon_emit(cs, va);
6371 radeon_emit(cs, va >> 32);
6372 radeon_emit(cs, value);
6373 } else {
6374 /* Otherwise, sync all prior GPU work using an EOP event. */
6375 si_cs_emit_write_event_eop(cs,
6376 cmd_buffer->device->physical_device->rad_info.chip_class,
6377 radv_cmd_buffer_uses_mec(cmd_buffer),
6378 V_028A90_BOTTOM_OF_PIPE_TS, 0,
6379 EOP_DST_SEL_MEM,
6380 EOP_DATA_SEL_VALUE_32BIT, va, value,
6381 cmd_buffer->gfx9_eop_bug_va);
6382 }
6383
6384 assert(cmd_buffer->cs->cdw <= cdw_max);
6385 }
6386
6387 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
6388 VkEvent _event,
6389 VkPipelineStageFlags stageMask)
6390 {
6391 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6392 RADV_FROM_HANDLE(radv_event, event, _event);
6393
6394 write_event(cmd_buffer, event, stageMask, 1);
6395 }
6396
6397 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
6398 VkEvent _event,
6399 VkPipelineStageFlags stageMask)
6400 {
6401 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6402 RADV_FROM_HANDLE(radv_event, event, _event);
6403
6404 write_event(cmd_buffer, event, stageMask, 0);
6405 }
6406
6407 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
6408 uint32_t eventCount,
6409 const VkEvent* pEvents,
6410 VkPipelineStageFlags srcStageMask,
6411 VkPipelineStageFlags dstStageMask,
6412 uint32_t memoryBarrierCount,
6413 const VkMemoryBarrier* pMemoryBarriers,
6414 uint32_t bufferMemoryBarrierCount,
6415 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
6416 uint32_t imageMemoryBarrierCount,
6417 const VkImageMemoryBarrier* pImageMemoryBarriers)
6418 {
6419 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6420 struct radv_barrier_info info;
6421
6422 info.reason = RGP_BARRIER_EXTERNAL_CMD_WAIT_EVENTS;
6423 info.eventCount = eventCount;
6424 info.pEvents = pEvents;
6425 info.srcStageMask = 0;
6426
6427 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
6428 bufferMemoryBarrierCount, pBufferMemoryBarriers,
6429 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
6430 }
6431
6432
6433 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
6434 uint32_t deviceMask)
6435 {
6436 /* No-op */
6437 }
6438
6439 /* VK_EXT_conditional_rendering */
6440 void radv_CmdBeginConditionalRenderingEXT(
6441 VkCommandBuffer commandBuffer,
6442 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
6443 {
6444 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6445 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
6446 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6447 bool draw_visible = true;
6448 uint64_t pred_value = 0;
6449 uint64_t va, new_va;
6450 unsigned pred_offset;
6451
6452 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
6453
6454 /* By default, if the 32-bit value at offset in buffer memory is zero,
6455 * then the rendering commands are discarded, otherwise they are
6456 * executed as normal. If the inverted flag is set, all commands are
6457 * discarded if the value is non zero.
6458 */
6459 if (pConditionalRenderingBegin->flags &
6460 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
6461 draw_visible = false;
6462 }
6463
6464 si_emit_cache_flush(cmd_buffer);
6465
6466 /* From the Vulkan spec 1.1.107:
6467 *
6468 * "If the 32-bit value at offset in buffer memory is zero, then the
6469 * rendering commands are discarded, otherwise they are executed as
6470 * normal. If the value of the predicate in buffer memory changes while
6471 * conditional rendering is active, the rendering commands may be
6472 * discarded in an implementation-dependent way. Some implementations
6473 * may latch the value of the predicate upon beginning conditional
6474 * rendering while others may read it before every rendering command."
6475 *
6476 * But, the AMD hardware treats the predicate as a 64-bit value which
6477 * means we need a workaround in the driver. Luckily, it's not required
6478 * to support if the value changes when predication is active.
6479 *
6480 * The workaround is as follows:
6481 * 1) allocate a 64-value in the upload BO and initialize it to 0
6482 * 2) copy the 32-bit predicate value to the upload BO
6483 * 3) use the new allocated VA address for predication
6484 *
6485 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
6486 * in ME (+ sync PFP) instead of PFP.
6487 */
6488 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
6489
6490 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
6491
6492 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
6493 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
6494 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
6495 COPY_DATA_WR_CONFIRM);
6496 radeon_emit(cs, va);
6497 radeon_emit(cs, va >> 32);
6498 radeon_emit(cs, new_va);
6499 radeon_emit(cs, new_va >> 32);
6500
6501 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
6502 radeon_emit(cs, 0);
6503
6504 /* Enable predication for this command buffer. */
6505 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
6506 cmd_buffer->state.predicating = true;
6507
6508 /* Store conditional rendering user info. */
6509 cmd_buffer->state.predication_type = draw_visible;
6510 cmd_buffer->state.predication_va = new_va;
6511 }
6512
6513 void radv_CmdEndConditionalRenderingEXT(
6514 VkCommandBuffer commandBuffer)
6515 {
6516 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6517
6518 /* Disable predication for this command buffer. */
6519 si_emit_set_predication_state(cmd_buffer, false, 0);
6520 cmd_buffer->state.predicating = false;
6521
6522 /* Reset conditional rendering user info. */
6523 cmd_buffer->state.predication_type = -1;
6524 cmd_buffer->state.predication_va = 0;
6525 }
6526
6527 /* VK_EXT_transform_feedback */
6528 void radv_CmdBindTransformFeedbackBuffersEXT(
6529 VkCommandBuffer commandBuffer,
6530 uint32_t firstBinding,
6531 uint32_t bindingCount,
6532 const VkBuffer* pBuffers,
6533 const VkDeviceSize* pOffsets,
6534 const VkDeviceSize* pSizes)
6535 {
6536 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6537 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
6538 uint8_t enabled_mask = 0;
6539
6540 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
6541 for (uint32_t i = 0; i < bindingCount; i++) {
6542 uint32_t idx = firstBinding + i;
6543
6544 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
6545 sb[idx].offset = pOffsets[i];
6546
6547 if (!pSizes || pSizes[i] == VK_WHOLE_SIZE) {
6548 sb[idx].size = sb[idx].buffer->size - sb[idx].offset;
6549 } else {
6550 sb[idx].size = pSizes[i];
6551 }
6552
6553 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
6554 sb[idx].buffer->bo);
6555
6556 enabled_mask |= 1 << idx;
6557 }
6558
6559 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
6560
6561 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
6562 }
6563
6564 static void
6565 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
6566 {
6567 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6568 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6569
6570 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
6571 radeon_emit(cs,
6572 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
6573 S_028B94_RAST_STREAM(0) |
6574 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
6575 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
6576 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
6577 radeon_emit(cs, so->hw_enabled_mask &
6578 so->enabled_stream_buffers_mask);
6579
6580 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6581 }
6582
6583 static void
6584 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
6585 {
6586 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6587 bool old_streamout_enabled = so->streamout_enabled;
6588 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
6589
6590 so->streamout_enabled = enable;
6591
6592 so->hw_enabled_mask = so->enabled_mask |
6593 (so->enabled_mask << 4) |
6594 (so->enabled_mask << 8) |
6595 (so->enabled_mask << 12);
6596
6597 if (!cmd_buffer->device->physical_device->use_ngg_streamout &&
6598 ((old_streamout_enabled != so->streamout_enabled) ||
6599 (old_hw_enabled_mask != so->hw_enabled_mask)))
6600 radv_emit_streamout_enable(cmd_buffer);
6601
6602 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6603 cmd_buffer->gds_needed = true;
6604 cmd_buffer->gds_oa_needed = true;
6605 }
6606 }
6607
6608 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
6609 {
6610 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6611 unsigned reg_strmout_cntl;
6612
6613 /* The register is at different places on different ASICs. */
6614 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
6615 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
6616 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
6617 } else {
6618 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
6619 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
6620 }
6621
6622 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
6623 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
6624
6625 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
6626 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
6627 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
6628 radeon_emit(cs, 0);
6629 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
6630 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
6631 radeon_emit(cs, 4); /* poll interval */
6632 }
6633
6634 static void
6635 radv_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6636 uint32_t firstCounterBuffer,
6637 uint32_t counterBufferCount,
6638 const VkBuffer *pCounterBuffers,
6639 const VkDeviceSize *pCounterBufferOffsets)
6640
6641 {
6642 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
6643 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6644 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6645 uint32_t i;
6646
6647 radv_flush_vgt_streamout(cmd_buffer);
6648
6649 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6650 for_each_bit(i, so->enabled_mask) {
6651 int32_t counter_buffer_idx = i - firstCounterBuffer;
6652 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6653 counter_buffer_idx = -1;
6654
6655 /* AMD GCN binds streamout buffers as shader resources.
6656 * VGT only counts primitives and tells the shader through
6657 * SGPRs what to do.
6658 */
6659 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
6660 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
6661 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
6662
6663 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6664
6665 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6666 /* The array of counter buffers is optional. */
6667 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6668 uint64_t va = radv_buffer_get_va(buffer->bo);
6669
6670 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6671
6672 /* Append */
6673 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6674 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6675 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6676 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
6677 radeon_emit(cs, 0); /* unused */
6678 radeon_emit(cs, 0); /* unused */
6679 radeon_emit(cs, va); /* src address lo */
6680 radeon_emit(cs, va >> 32); /* src address hi */
6681
6682 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6683 } else {
6684 /* Start from the beginning. */
6685 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6686 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6687 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6688 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
6689 radeon_emit(cs, 0); /* unused */
6690 radeon_emit(cs, 0); /* unused */
6691 radeon_emit(cs, 0); /* unused */
6692 radeon_emit(cs, 0); /* unused */
6693 }
6694 }
6695
6696 radv_set_streamout_enable(cmd_buffer, true);
6697 }
6698
6699 static void
6700 gfx10_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6701 uint32_t firstCounterBuffer,
6702 uint32_t counterBufferCount,
6703 const VkBuffer *pCounterBuffers,
6704 const VkDeviceSize *pCounterBufferOffsets)
6705 {
6706 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6707 unsigned last_target = util_last_bit(so->enabled_mask) - 1;
6708 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6709 uint32_t i;
6710
6711 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6712 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6713
6714 /* Sync because the next streamout operation will overwrite GDS and we
6715 * have to make sure it's idle.
6716 * TODO: Improve by tracking if there is a streamout operation in
6717 * flight.
6718 */
6719 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
6720 si_emit_cache_flush(cmd_buffer);
6721
6722 for_each_bit(i, so->enabled_mask) {
6723 int32_t counter_buffer_idx = i - firstCounterBuffer;
6724 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6725 counter_buffer_idx = -1;
6726
6727 bool append = counter_buffer_idx >= 0 &&
6728 pCounterBuffers && pCounterBuffers[counter_buffer_idx];
6729 uint64_t va = 0;
6730
6731 if (append) {
6732 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6733
6734 va += radv_buffer_get_va(buffer->bo);
6735 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6736
6737 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6738 }
6739
6740 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
6741 radeon_emit(cs, S_411_SRC_SEL(append ? V_411_SRC_ADDR_TC_L2 : V_411_DATA) |
6742 S_411_DST_SEL(V_411_GDS) |
6743 S_411_CP_SYNC(i == last_target));
6744 radeon_emit(cs, va);
6745 radeon_emit(cs, va >> 32);
6746 radeon_emit(cs, 4 * i); /* destination in GDS */
6747 radeon_emit(cs, 0);
6748 radeon_emit(cs, S_414_BYTE_COUNT_GFX9(4) |
6749 S_414_DISABLE_WR_CONFIRM_GFX9(i != last_target));
6750 }
6751
6752 radv_set_streamout_enable(cmd_buffer, true);
6753 }
6754
6755 void radv_CmdBeginTransformFeedbackEXT(
6756 VkCommandBuffer commandBuffer,
6757 uint32_t firstCounterBuffer,
6758 uint32_t counterBufferCount,
6759 const VkBuffer* pCounterBuffers,
6760 const VkDeviceSize* pCounterBufferOffsets)
6761 {
6762 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6763
6764 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6765 gfx10_emit_streamout_begin(cmd_buffer,
6766 firstCounterBuffer, counterBufferCount,
6767 pCounterBuffers, pCounterBufferOffsets);
6768 } else {
6769 radv_emit_streamout_begin(cmd_buffer,
6770 firstCounterBuffer, counterBufferCount,
6771 pCounterBuffers, pCounterBufferOffsets);
6772 }
6773 }
6774
6775 static void
6776 radv_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6777 uint32_t firstCounterBuffer,
6778 uint32_t counterBufferCount,
6779 const VkBuffer *pCounterBuffers,
6780 const VkDeviceSize *pCounterBufferOffsets)
6781 {
6782 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6783 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6784 uint32_t i;
6785
6786 radv_flush_vgt_streamout(cmd_buffer);
6787
6788 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6789 for_each_bit(i, so->enabled_mask) {
6790 int32_t counter_buffer_idx = i - firstCounterBuffer;
6791 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6792 counter_buffer_idx = -1;
6793
6794 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6795 /* The array of counters buffer is optional. */
6796 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6797 uint64_t va = radv_buffer_get_va(buffer->bo);
6798
6799 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6800
6801 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6802 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6803 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6804 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
6805 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
6806 radeon_emit(cs, va); /* dst address lo */
6807 radeon_emit(cs, va >> 32); /* dst address hi */
6808 radeon_emit(cs, 0); /* unused */
6809 radeon_emit(cs, 0); /* unused */
6810
6811 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6812 }
6813
6814 /* Deactivate transform feedback by zeroing the buffer size.
6815 * The counters (primitives generated, primitives emitted) may
6816 * be enabled even if there is not buffer bound. This ensures
6817 * that the primitives-emitted query won't increment.
6818 */
6819 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
6820
6821 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6822 }
6823
6824 radv_set_streamout_enable(cmd_buffer, false);
6825 }
6826
6827 static void
6828 gfx10_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6829 uint32_t firstCounterBuffer,
6830 uint32_t counterBufferCount,
6831 const VkBuffer *pCounterBuffers,
6832 const VkDeviceSize *pCounterBufferOffsets)
6833 {
6834 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6835 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6836 uint32_t i;
6837
6838 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6839 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6840
6841 for_each_bit(i, so->enabled_mask) {
6842 int32_t counter_buffer_idx = i - firstCounterBuffer;
6843 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6844 counter_buffer_idx = -1;
6845
6846 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6847 /* The array of counters buffer is optional. */
6848 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6849 uint64_t va = radv_buffer_get_va(buffer->bo);
6850
6851 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6852
6853 si_cs_emit_write_event_eop(cs,
6854 cmd_buffer->device->physical_device->rad_info.chip_class,
6855 radv_cmd_buffer_uses_mec(cmd_buffer),
6856 V_028A90_PS_DONE, 0,
6857 EOP_DST_SEL_TC_L2,
6858 EOP_DATA_SEL_GDS,
6859 va, EOP_DATA_GDS(i, 1), 0);
6860
6861 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6862 }
6863 }
6864
6865 radv_set_streamout_enable(cmd_buffer, false);
6866 }
6867
6868 void radv_CmdEndTransformFeedbackEXT(
6869 VkCommandBuffer commandBuffer,
6870 uint32_t firstCounterBuffer,
6871 uint32_t counterBufferCount,
6872 const VkBuffer* pCounterBuffers,
6873 const VkDeviceSize* pCounterBufferOffsets)
6874 {
6875 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6876
6877 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6878 gfx10_emit_streamout_end(cmd_buffer,
6879 firstCounterBuffer, counterBufferCount,
6880 pCounterBuffers, pCounterBufferOffsets);
6881 } else {
6882 radv_emit_streamout_end(cmd_buffer,
6883 firstCounterBuffer, counterBufferCount,
6884 pCounterBuffers, pCounterBufferOffsets);
6885 }
6886 }
6887
6888 void radv_CmdDrawIndirectByteCountEXT(
6889 VkCommandBuffer commandBuffer,
6890 uint32_t instanceCount,
6891 uint32_t firstInstance,
6892 VkBuffer _counterBuffer,
6893 VkDeviceSize counterBufferOffset,
6894 uint32_t counterOffset,
6895 uint32_t vertexStride)
6896 {
6897 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6898 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
6899 struct radv_draw_info info = {};
6900
6901 info.instance_count = instanceCount;
6902 info.first_instance = firstInstance;
6903 info.strmout_buffer = counterBuffer;
6904 info.strmout_buffer_offset = counterBufferOffset;
6905 info.stride = vertexStride;
6906
6907 radv_draw(cmd_buffer, &info);
6908 }
6909
6910 /* VK_AMD_buffer_marker */
6911 void radv_CmdWriteBufferMarkerAMD(
6912 VkCommandBuffer commandBuffer,
6913 VkPipelineStageFlagBits pipelineStage,
6914 VkBuffer dstBuffer,
6915 VkDeviceSize dstOffset,
6916 uint32_t marker)
6917 {
6918 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6919 RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
6920 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6921 uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
6922
6923 si_emit_cache_flush(cmd_buffer);
6924
6925 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 12);
6926
6927 if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
6928 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
6929 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
6930 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
6931 COPY_DATA_WR_CONFIRM);
6932 radeon_emit(cs, marker);
6933 radeon_emit(cs, 0);
6934 radeon_emit(cs, va);
6935 radeon_emit(cs, va >> 32);
6936 } else {
6937 si_cs_emit_write_event_eop(cs,
6938 cmd_buffer->device->physical_device->rad_info.chip_class,
6939 radv_cmd_buffer_uses_mec(cmd_buffer),
6940 V_028A90_BOTTOM_OF_PIPE_TS, 0,
6941 EOP_DST_SEL_MEM,
6942 EOP_DATA_SEL_VALUE_32BIT,
6943 va, marker,
6944 cmd_buffer->gfx9_eop_bug_va);
6945 }
6946
6947 assert(cmd_buffer->cs->cdw <= cdw_max);
6948 }