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radv: add support for dynamic primitive topology
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 bool src_render_loop,
58 VkImageLayout dst_layout,
59 bool dst_render_loop,
60 uint32_t src_family,
61 uint32_t dst_family,
62 const VkImageSubresourceRange *range,
63 struct radv_sample_locations_state *sample_locs);
64
65 const struct radv_dynamic_state default_dynamic_state = {
66 .viewport = {
67 .count = 0,
68 },
69 .scissor = {
70 .count = 0,
71 },
72 .line_width = 1.0f,
73 .depth_bias = {
74 .bias = 0.0f,
75 .clamp = 0.0f,
76 .slope = 0.0f,
77 },
78 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
79 .depth_bounds = {
80 .min = 0.0f,
81 .max = 1.0f,
82 },
83 .stencil_compare_mask = {
84 .front = ~0u,
85 .back = ~0u,
86 },
87 .stencil_write_mask = {
88 .front = ~0u,
89 .back = ~0u,
90 },
91 .stencil_reference = {
92 .front = 0u,
93 .back = 0u,
94 },
95 .line_stipple = {
96 .factor = 0u,
97 .pattern = 0u,
98 },
99 .cull_mode = 0u,
100 .front_face = 0u,
101 .primitive_topology = 0u,
102 };
103
104 static void
105 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
106 const struct radv_dynamic_state *src)
107 {
108 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
109 uint32_t copy_mask = src->mask;
110 uint32_t dest_mask = 0;
111
112 dest->discard_rectangle.count = src->discard_rectangle.count;
113 dest->sample_location.count = src->sample_location.count;
114
115 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
116 dest->viewport.count = src->viewport.count;
117 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
118 src->viewport.count * sizeof(VkViewport))) {
119 typed_memcpy(dest->viewport.viewports,
120 src->viewport.viewports,
121 src->viewport.count);
122 dest_mask |= RADV_DYNAMIC_VIEWPORT;
123 }
124 }
125
126 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
127 dest->scissor.count = src->scissor.count;
128 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
129 src->scissor.count * sizeof(VkRect2D))) {
130 typed_memcpy(dest->scissor.scissors,
131 src->scissor.scissors, src->scissor.count);
132 dest_mask |= RADV_DYNAMIC_SCISSOR;
133 }
134 }
135
136 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
137 if (dest->line_width != src->line_width) {
138 dest->line_width = src->line_width;
139 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
140 }
141 }
142
143 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
144 if (memcmp(&dest->depth_bias, &src->depth_bias,
145 sizeof(src->depth_bias))) {
146 dest->depth_bias = src->depth_bias;
147 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
148 }
149 }
150
151 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
152 if (memcmp(&dest->blend_constants, &src->blend_constants,
153 sizeof(src->blend_constants))) {
154 typed_memcpy(dest->blend_constants,
155 src->blend_constants, 4);
156 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
157 }
158 }
159
160 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
161 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
162 sizeof(src->depth_bounds))) {
163 dest->depth_bounds = src->depth_bounds;
164 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
165 }
166 }
167
168 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
169 if (memcmp(&dest->stencil_compare_mask,
170 &src->stencil_compare_mask,
171 sizeof(src->stencil_compare_mask))) {
172 dest->stencil_compare_mask = src->stencil_compare_mask;
173 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
174 }
175 }
176
177 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
178 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
179 sizeof(src->stencil_write_mask))) {
180 dest->stencil_write_mask = src->stencil_write_mask;
181 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
182 }
183 }
184
185 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
186 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
187 sizeof(src->stencil_reference))) {
188 dest->stencil_reference = src->stencil_reference;
189 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
190 }
191 }
192
193 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
194 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
195 src->discard_rectangle.count * sizeof(VkRect2D))) {
196 typed_memcpy(dest->discard_rectangle.rectangles,
197 src->discard_rectangle.rectangles,
198 src->discard_rectangle.count);
199 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
200 }
201 }
202
203 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
204 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
205 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
206 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
207 memcmp(&dest->sample_location.locations,
208 &src->sample_location.locations,
209 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
210 dest->sample_location.per_pixel = src->sample_location.per_pixel;
211 dest->sample_location.grid_size = src->sample_location.grid_size;
212 typed_memcpy(dest->sample_location.locations,
213 src->sample_location.locations,
214 src->sample_location.count);
215 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
216 }
217 }
218
219 if (copy_mask & RADV_DYNAMIC_LINE_STIPPLE) {
220 if (memcmp(&dest->line_stipple, &src->line_stipple,
221 sizeof(src->line_stipple))) {
222 dest->line_stipple = src->line_stipple;
223 dest_mask |= RADV_DYNAMIC_LINE_STIPPLE;
224 }
225 }
226
227 if (copy_mask & RADV_DYNAMIC_CULL_MODE) {
228 if (dest->cull_mode != src->cull_mode) {
229 dest->cull_mode = src->cull_mode;
230 dest_mask |= RADV_DYNAMIC_CULL_MODE;
231 }
232 }
233
234 if (copy_mask & RADV_DYNAMIC_FRONT_FACE) {
235 if (dest->front_face != src->front_face) {
236 dest->front_face = src->front_face;
237 dest_mask |= RADV_DYNAMIC_FRONT_FACE;
238 }
239 }
240
241 if (copy_mask & RADV_DYNAMIC_PRIMITIVE_TOPOLOGY) {
242 if (dest->primitive_topology != src->primitive_topology) {
243 dest->primitive_topology = src->primitive_topology;
244 dest_mask |= RADV_DYNAMIC_PRIMITIVE_TOPOLOGY;
245 }
246 }
247
248 cmd_buffer->state.dirty |= dest_mask;
249 }
250
251 static void
252 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
253 struct radv_pipeline *pipeline)
254 {
255 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
256 struct radv_shader_info *info;
257
258 if (!pipeline->streamout_shader ||
259 cmd_buffer->device->physical_device->use_ngg_streamout)
260 return;
261
262 info = &pipeline->streamout_shader->info;
263 for (int i = 0; i < MAX_SO_BUFFERS; i++)
264 so->stride_in_dw[i] = info->so.strides[i];
265
266 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
267 }
268
269 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
270 {
271 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
272 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
273 }
274
275 enum ring_type radv_queue_family_to_ring(int f) {
276 switch (f) {
277 case RADV_QUEUE_GENERAL:
278 return RING_GFX;
279 case RADV_QUEUE_COMPUTE:
280 return RING_COMPUTE;
281 case RADV_QUEUE_TRANSFER:
282 return RING_DMA;
283 default:
284 unreachable("Unknown queue family");
285 }
286 }
287
288 static VkResult radv_create_cmd_buffer(
289 struct radv_device * device,
290 struct radv_cmd_pool * pool,
291 VkCommandBufferLevel level,
292 VkCommandBuffer* pCommandBuffer)
293 {
294 struct radv_cmd_buffer *cmd_buffer;
295 unsigned ring;
296 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
297 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
298 if (cmd_buffer == NULL)
299 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
300
301 vk_object_base_init(&device->vk, &cmd_buffer->base,
302 VK_OBJECT_TYPE_COMMAND_BUFFER);
303
304 cmd_buffer->device = device;
305 cmd_buffer->pool = pool;
306 cmd_buffer->level = level;
307
308 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
309 cmd_buffer->queue_family_index = pool->queue_family_index;
310
311 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
312
313 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
314 if (!cmd_buffer->cs) {
315 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
316 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
317 }
318
319 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
320
321 list_inithead(&cmd_buffer->upload.list);
322
323 return VK_SUCCESS;
324 }
325
326 static void
327 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
328 {
329 list_del(&cmd_buffer->pool_link);
330
331 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
332 &cmd_buffer->upload.list, list) {
333 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
334 list_del(&up->list);
335 free(up);
336 }
337
338 if (cmd_buffer->upload.upload_bo)
339 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
340 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
341
342 for (unsigned i = 0; i < MAX_BIND_POINTS; i++)
343 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
344
345 vk_object_base_finish(&cmd_buffer->base);
346
347 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
348 }
349
350 static VkResult
351 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
352 {
353 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
354
355 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
356 &cmd_buffer->upload.list, list) {
357 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
358 list_del(&up->list);
359 free(up);
360 }
361
362 cmd_buffer->push_constant_stages = 0;
363 cmd_buffer->scratch_size_per_wave_needed = 0;
364 cmd_buffer->scratch_waves_wanted = 0;
365 cmd_buffer->compute_scratch_size_per_wave_needed = 0;
366 cmd_buffer->compute_scratch_waves_wanted = 0;
367 cmd_buffer->esgs_ring_size_needed = 0;
368 cmd_buffer->gsvs_ring_size_needed = 0;
369 cmd_buffer->tess_rings_needed = false;
370 cmd_buffer->gds_needed = false;
371 cmd_buffer->gds_oa_needed = false;
372 cmd_buffer->sample_positions_needed = false;
373
374 if (cmd_buffer->upload.upload_bo)
375 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
376 cmd_buffer->upload.upload_bo);
377 cmd_buffer->upload.offset = 0;
378
379 cmd_buffer->record_result = VK_SUCCESS;
380
381 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
382
383 for (unsigned i = 0; i < MAX_BIND_POINTS; i++) {
384 cmd_buffer->descriptors[i].dirty = 0;
385 cmd_buffer->descriptors[i].valid = 0;
386 cmd_buffer->descriptors[i].push_dirty = false;
387 }
388
389 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
390 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
391 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
392 unsigned fence_offset, eop_bug_offset;
393 void *fence_ptr;
394
395 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
396 &fence_ptr);
397
398 cmd_buffer->gfx9_fence_va =
399 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
400 cmd_buffer->gfx9_fence_va += fence_offset;
401
402 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
403 /* Allocate a buffer for the EOP bug on GFX9. */
404 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
405 &eop_bug_offset, &fence_ptr);
406 cmd_buffer->gfx9_eop_bug_va =
407 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
408 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
409 }
410 }
411
412 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
413
414 return cmd_buffer->record_result;
415 }
416
417 static bool
418 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
419 uint64_t min_needed)
420 {
421 uint64_t new_size;
422 struct radeon_winsys_bo *bo;
423 struct radv_cmd_buffer_upload *upload;
424 struct radv_device *device = cmd_buffer->device;
425
426 new_size = MAX2(min_needed, 16 * 1024);
427 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
428
429 bo = device->ws->buffer_create(device->ws,
430 new_size, 4096,
431 RADEON_DOMAIN_GTT,
432 RADEON_FLAG_CPU_ACCESS|
433 RADEON_FLAG_NO_INTERPROCESS_SHARING |
434 RADEON_FLAG_32BIT,
435 RADV_BO_PRIORITY_UPLOAD_BUFFER);
436
437 if (!bo) {
438 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
439 return false;
440 }
441
442 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
443 if (cmd_buffer->upload.upload_bo) {
444 upload = malloc(sizeof(*upload));
445
446 if (!upload) {
447 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
448 device->ws->buffer_destroy(bo);
449 return false;
450 }
451
452 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
453 list_add(&upload->list, &cmd_buffer->upload.list);
454 }
455
456 cmd_buffer->upload.upload_bo = bo;
457 cmd_buffer->upload.size = new_size;
458 cmd_buffer->upload.offset = 0;
459 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
460
461 if (!cmd_buffer->upload.map) {
462 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
463 return false;
464 }
465
466 return true;
467 }
468
469 bool
470 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
471 unsigned size,
472 unsigned alignment,
473 unsigned *out_offset,
474 void **ptr)
475 {
476 assert(util_is_power_of_two_nonzero(alignment));
477
478 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
479 if (offset + size > cmd_buffer->upload.size) {
480 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
481 return false;
482 offset = 0;
483 }
484
485 *out_offset = offset;
486 *ptr = cmd_buffer->upload.map + offset;
487
488 cmd_buffer->upload.offset = offset + size;
489 return true;
490 }
491
492 bool
493 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
494 unsigned size, unsigned alignment,
495 const void *data, unsigned *out_offset)
496 {
497 uint8_t *ptr;
498
499 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
500 out_offset, (void **)&ptr))
501 return false;
502
503 if (ptr)
504 memcpy(ptr, data, size);
505
506 return true;
507 }
508
509 static void
510 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
511 unsigned count, const uint32_t *data)
512 {
513 struct radeon_cmdbuf *cs = cmd_buffer->cs;
514
515 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
516
517 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
518 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
519 S_370_WR_CONFIRM(1) |
520 S_370_ENGINE_SEL(V_370_ME));
521 radeon_emit(cs, va);
522 radeon_emit(cs, va >> 32);
523 radeon_emit_array(cs, data, count);
524 }
525
526 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
527 {
528 struct radv_device *device = cmd_buffer->device;
529 struct radeon_cmdbuf *cs = cmd_buffer->cs;
530 uint64_t va;
531
532 va = radv_buffer_get_va(device->trace_bo);
533 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
534 va += 4;
535
536 ++cmd_buffer->state.trace_id;
537 radv_emit_write_data_packet(cmd_buffer, va, 1,
538 &cmd_buffer->state.trace_id);
539
540 radeon_check_space(cmd_buffer->device->ws, cs, 2);
541
542 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
543 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
544 }
545
546 static void
547 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
548 enum radv_cmd_flush_bits flags)
549 {
550 if (unlikely(cmd_buffer->device->thread_trace_bo)) {
551 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
552 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_THREAD_TRACE_MARKER) | EVENT_INDEX(0));
553 }
554
555 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
556 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
557 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
558
559 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
560
561 /* Force wait for graphics or compute engines to be idle. */
562 si_cs_emit_cache_flush(cmd_buffer->cs,
563 cmd_buffer->device->physical_device->rad_info.chip_class,
564 &cmd_buffer->gfx9_fence_idx,
565 cmd_buffer->gfx9_fence_va,
566 radv_cmd_buffer_uses_mec(cmd_buffer),
567 flags, cmd_buffer->gfx9_eop_bug_va);
568 }
569
570 if (unlikely(cmd_buffer->device->trace_bo))
571 radv_cmd_buffer_trace_emit(cmd_buffer);
572 }
573
574 static void
575 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
576 struct radv_pipeline *pipeline, enum ring_type ring)
577 {
578 struct radv_device *device = cmd_buffer->device;
579 uint32_t data[2];
580 uint64_t va;
581
582 va = radv_buffer_get_va(device->trace_bo);
583
584 switch (ring) {
585 case RING_GFX:
586 va += 8;
587 break;
588 case RING_COMPUTE:
589 va += 16;
590 break;
591 default:
592 assert(!"invalid ring type");
593 }
594
595 uint64_t pipeline_address = (uintptr_t)pipeline;
596 data[0] = pipeline_address;
597 data[1] = pipeline_address >> 32;
598
599 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
600 }
601
602 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
603 VkPipelineBindPoint bind_point,
604 struct radv_descriptor_set *set,
605 unsigned idx)
606 {
607 struct radv_descriptor_state *descriptors_state =
608 radv_get_descriptors_state(cmd_buffer, bind_point);
609
610 descriptors_state->sets[idx] = set;
611
612 descriptors_state->valid |= (1u << idx); /* active descriptors */
613 descriptors_state->dirty |= (1u << idx);
614 }
615
616 static void
617 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
618 VkPipelineBindPoint bind_point)
619 {
620 struct radv_descriptor_state *descriptors_state =
621 radv_get_descriptors_state(cmd_buffer, bind_point);
622 struct radv_device *device = cmd_buffer->device;
623 uint32_t data[MAX_SETS * 2] = {};
624 uint64_t va;
625 unsigned i;
626 va = radv_buffer_get_va(device->trace_bo) + 24;
627
628 for_each_bit(i, descriptors_state->valid) {
629 struct radv_descriptor_set *set = descriptors_state->sets[i];
630 data[i * 2] = (uint64_t)(uintptr_t)set;
631 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
632 }
633
634 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
635 }
636
637 struct radv_userdata_info *
638 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
639 gl_shader_stage stage,
640 int idx)
641 {
642 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
643 return &shader->info.user_sgprs_locs.shader_data[idx];
644 }
645
646 static void
647 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
648 struct radv_pipeline *pipeline,
649 gl_shader_stage stage,
650 int idx, uint64_t va)
651 {
652 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
653 uint32_t base_reg = pipeline->user_data_0[stage];
654 if (loc->sgpr_idx == -1)
655 return;
656
657 assert(loc->num_sgprs == 1);
658
659 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
660 base_reg + loc->sgpr_idx * 4, va, false);
661 }
662
663 static void
664 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
665 struct radv_pipeline *pipeline,
666 struct radv_descriptor_state *descriptors_state,
667 gl_shader_stage stage)
668 {
669 struct radv_device *device = cmd_buffer->device;
670 struct radeon_cmdbuf *cs = cmd_buffer->cs;
671 uint32_t sh_base = pipeline->user_data_0[stage];
672 struct radv_userdata_locations *locs =
673 &pipeline->shaders[stage]->info.user_sgprs_locs;
674 unsigned mask = locs->descriptor_sets_enabled;
675
676 mask &= descriptors_state->dirty & descriptors_state->valid;
677
678 while (mask) {
679 int start, count;
680
681 u_bit_scan_consecutive_range(&mask, &start, &count);
682
683 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
684 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
685
686 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
687 for (int i = 0; i < count; i++) {
688 struct radv_descriptor_set *set =
689 descriptors_state->sets[start + i];
690
691 radv_emit_shader_pointer_body(device, cs, set->va, true);
692 }
693 }
694 }
695
696 /**
697 * Convert the user sample locations to hardware sample locations (the values
698 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
699 */
700 static void
701 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
702 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
703 {
704 uint32_t x_offset = x % state->grid_size.width;
705 uint32_t y_offset = y % state->grid_size.height;
706 uint32_t num_samples = (uint32_t)state->per_pixel;
707 VkSampleLocationEXT *user_locs;
708 uint32_t pixel_offset;
709
710 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
711
712 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
713 user_locs = &state->locations[pixel_offset];
714
715 for (uint32_t i = 0; i < num_samples; i++) {
716 float shifted_pos_x = user_locs[i].x - 0.5;
717 float shifted_pos_y = user_locs[i].y - 0.5;
718
719 int32_t scaled_pos_x = floorf(shifted_pos_x * 16);
720 int32_t scaled_pos_y = floorf(shifted_pos_y * 16);
721
722 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
723 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
724 }
725 }
726
727 /**
728 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
729 * locations.
730 */
731 static void
732 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
733 uint32_t *sample_locs_pixel)
734 {
735 for (uint32_t i = 0; i < num_samples; i++) {
736 uint32_t sample_reg_idx = i / 4;
737 uint32_t sample_loc_idx = i % 4;
738 int32_t pos_x = sample_locs[i].x;
739 int32_t pos_y = sample_locs[i].y;
740
741 uint32_t shift_x = 8 * sample_loc_idx;
742 uint32_t shift_y = shift_x + 4;
743
744 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
745 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
746 }
747 }
748
749 /**
750 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
751 * sample locations.
752 */
753 static uint64_t
754 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
755 VkOffset2D *sample_locs,
756 uint32_t num_samples)
757 {
758 uint32_t centroid_priorities[num_samples];
759 uint32_t sample_mask = num_samples - 1;
760 uint32_t distances[num_samples];
761 uint64_t centroid_priority = 0;
762
763 /* Compute the distances from center for each sample. */
764 for (int i = 0; i < num_samples; i++) {
765 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
766 (sample_locs[i].y * sample_locs[i].y);
767 }
768
769 /* Compute the centroid priorities by looking at the distances array. */
770 for (int i = 0; i < num_samples; i++) {
771 uint32_t min_idx = 0;
772
773 for (int j = 1; j < num_samples; j++) {
774 if (distances[j] < distances[min_idx])
775 min_idx = j;
776 }
777
778 centroid_priorities[i] = min_idx;
779 distances[min_idx] = 0xffffffff;
780 }
781
782 /* Compute the final centroid priority. */
783 for (int i = 0; i < 8; i++) {
784 centroid_priority |=
785 centroid_priorities[i & sample_mask] << (i * 4);
786 }
787
788 return centroid_priority << 32 | centroid_priority;
789 }
790
791 /**
792 * Emit the sample locations that are specified with VK_EXT_sample_locations.
793 */
794 static void
795 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
796 {
797 struct radv_sample_locations_state *sample_location =
798 &cmd_buffer->state.dynamic.sample_location;
799 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
800 struct radeon_cmdbuf *cs = cmd_buffer->cs;
801 uint32_t sample_locs_pixel[4][2] = {};
802 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
803 uint32_t max_sample_dist = 0;
804 uint64_t centroid_priority;
805
806 if (!cmd_buffer->state.dynamic.sample_location.count)
807 return;
808
809 /* Convert the user sample locations to hardware sample locations. */
810 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
811 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
812 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
813 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
814
815 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
816 for (uint32_t i = 0; i < 4; i++) {
817 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
818 sample_locs_pixel[i]);
819 }
820
821 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
822 centroid_priority =
823 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
824 num_samples);
825
826 /* Compute the maximum sample distance from the specified locations. */
827 for (unsigned i = 0; i < 4; ++i) {
828 for (uint32_t j = 0; j < num_samples; j++) {
829 VkOffset2D offset = sample_locs[i][j];
830 max_sample_dist = MAX2(max_sample_dist,
831 MAX2(abs(offset.x), abs(offset.y)));
832 }
833 }
834
835 /* Emit the specified user sample locations. */
836 switch (num_samples) {
837 case 2:
838 case 4:
839 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
840 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
841 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
842 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
843 break;
844 case 8:
845 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
846 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
847 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
848 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
849 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
850 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
851 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
852 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
853 break;
854 default:
855 unreachable("invalid number of samples");
856 }
857
858 /* Emit the maximum sample distance and the centroid priority. */
859 radeon_set_context_reg_rmw(cs, R_028BE0_PA_SC_AA_CONFIG,
860 S_028BE0_MAX_SAMPLE_DIST(max_sample_dist),
861 ~C_028BE0_MAX_SAMPLE_DIST);
862
863 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
864 radeon_emit(cs, centroid_priority);
865 radeon_emit(cs, centroid_priority >> 32);
866
867 /* GFX9: Flush DFSM when the AA mode changes. */
868 if (cmd_buffer->device->dfsm_allowed) {
869 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
870 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
871 }
872
873 cmd_buffer->state.context_roll_without_scissor_emitted = true;
874 }
875
876 static void
877 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
878 struct radv_pipeline *pipeline,
879 gl_shader_stage stage,
880 int idx, int count, uint32_t *values)
881 {
882 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
883 uint32_t base_reg = pipeline->user_data_0[stage];
884 if (loc->sgpr_idx == -1)
885 return;
886
887 assert(loc->num_sgprs == count);
888
889 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
890 radeon_emit_array(cmd_buffer->cs, values, count);
891 }
892
893 static void
894 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
895 struct radv_pipeline *pipeline)
896 {
897 int num_samples = pipeline->graphics.ms.num_samples;
898 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
899
900 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.needs_sample_positions)
901 cmd_buffer->sample_positions_needed = true;
902
903 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
904 return;
905
906 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
907
908 cmd_buffer->state.context_roll_without_scissor_emitted = true;
909 }
910
911 static void
912 radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer,
913 struct radv_pipeline *pipeline)
914 {
915 const struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
916
917
918 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
919 return;
920
921 if (old_pipeline &&
922 old_pipeline->graphics.binning.pa_sc_binner_cntl_0 == pipeline->graphics.binning.pa_sc_binner_cntl_0 &&
923 old_pipeline->graphics.binning.db_dfsm_control == pipeline->graphics.binning.db_dfsm_control)
924 return;
925
926 bool binning_flush = false;
927 if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 ||
928 cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 ||
929 cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 ||
930 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
931 binning_flush = !old_pipeline ||
932 G_028C44_BINNING_MODE(old_pipeline->graphics.binning.pa_sc_binner_cntl_0) !=
933 G_028C44_BINNING_MODE(pipeline->graphics.binning.pa_sc_binner_cntl_0);
934 }
935
936 radeon_set_context_reg(cmd_buffer->cs, R_028C44_PA_SC_BINNER_CNTL_0,
937 pipeline->graphics.binning.pa_sc_binner_cntl_0 |
938 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush));
939
940 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
941 radeon_set_context_reg(cmd_buffer->cs, R_028038_DB_DFSM_CONTROL,
942 pipeline->graphics.binning.db_dfsm_control);
943 } else {
944 radeon_set_context_reg(cmd_buffer->cs, R_028060_DB_DFSM_CONTROL,
945 pipeline->graphics.binning.db_dfsm_control);
946 }
947
948 cmd_buffer->state.context_roll_without_scissor_emitted = true;
949 }
950
951
952 static void
953 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
954 struct radv_shader_variant *shader)
955 {
956 uint64_t va;
957
958 if (!shader)
959 return;
960
961 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
962
963 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
964 }
965
966 static void
967 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
968 struct radv_pipeline *pipeline,
969 bool vertex_stage_only)
970 {
971 struct radv_cmd_state *state = &cmd_buffer->state;
972 uint32_t mask = state->prefetch_L2_mask;
973
974 if (vertex_stage_only) {
975 /* Fast prefetch path for starting draws as soon as possible.
976 */
977 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
978 RADV_PREFETCH_VBO_DESCRIPTORS);
979 }
980
981 if (mask & RADV_PREFETCH_VS)
982 radv_emit_shader_prefetch(cmd_buffer,
983 pipeline->shaders[MESA_SHADER_VERTEX]);
984
985 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
986 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
987
988 if (mask & RADV_PREFETCH_TCS)
989 radv_emit_shader_prefetch(cmd_buffer,
990 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
991
992 if (mask & RADV_PREFETCH_TES)
993 radv_emit_shader_prefetch(cmd_buffer,
994 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
995
996 if (mask & RADV_PREFETCH_GS) {
997 radv_emit_shader_prefetch(cmd_buffer,
998 pipeline->shaders[MESA_SHADER_GEOMETRY]);
999 if (radv_pipeline_has_gs_copy_shader(pipeline))
1000 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
1001 }
1002
1003 if (mask & RADV_PREFETCH_PS)
1004 radv_emit_shader_prefetch(cmd_buffer,
1005 pipeline->shaders[MESA_SHADER_FRAGMENT]);
1006
1007 state->prefetch_L2_mask &= ~mask;
1008 }
1009
1010 static void
1011 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
1012 {
1013 if (!cmd_buffer->device->physical_device->rad_info.rbplus_allowed)
1014 return;
1015
1016 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1017 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1018
1019 unsigned sx_ps_downconvert = 0;
1020 unsigned sx_blend_opt_epsilon = 0;
1021 unsigned sx_blend_opt_control = 0;
1022
1023 if (!cmd_buffer->state.attachments || !subpass)
1024 return;
1025
1026 for (unsigned i = 0; i < subpass->color_count; ++i) {
1027 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1028 /* We don't set the DISABLE bits, because the HW can't have holes,
1029 * so the SPI color format is set to 32-bit 1-component. */
1030 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1031 continue;
1032 }
1033
1034 int idx = subpass->color_attachments[i].attachment;
1035 struct radv_color_buffer_info *cb = &cmd_buffer->state.attachments[idx].cb;
1036
1037 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
1038 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
1039 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
1040 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
1041
1042 bool has_alpha, has_rgb;
1043
1044 /* Set if RGB and A are present. */
1045 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
1046
1047 if (format == V_028C70_COLOR_8 ||
1048 format == V_028C70_COLOR_16 ||
1049 format == V_028C70_COLOR_32)
1050 has_rgb = !has_alpha;
1051 else
1052 has_rgb = true;
1053
1054 /* Check the colormask and export format. */
1055 if (!(colormask & 0x7))
1056 has_rgb = false;
1057 if (!(colormask & 0x8))
1058 has_alpha = false;
1059
1060 if (spi_format == V_028714_SPI_SHADER_ZERO) {
1061 has_rgb = false;
1062 has_alpha = false;
1063 }
1064
1065 /* Disable value checking for disabled channels. */
1066 if (!has_rgb)
1067 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1068 if (!has_alpha)
1069 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1070
1071 /* Enable down-conversion for 32bpp and smaller formats. */
1072 switch (format) {
1073 case V_028C70_COLOR_8:
1074 case V_028C70_COLOR_8_8:
1075 case V_028C70_COLOR_8_8_8_8:
1076 /* For 1 and 2-channel formats, use the superset thereof. */
1077 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1078 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1079 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1080 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1081 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1082 }
1083 break;
1084
1085 case V_028C70_COLOR_5_6_5:
1086 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1087 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1088 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1089 }
1090 break;
1091
1092 case V_028C70_COLOR_1_5_5_5:
1093 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1094 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1095 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1096 }
1097 break;
1098
1099 case V_028C70_COLOR_4_4_4_4:
1100 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1101 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1102 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1103 }
1104 break;
1105
1106 case V_028C70_COLOR_32:
1107 if (swap == V_028C70_SWAP_STD &&
1108 spi_format == V_028714_SPI_SHADER_32_R)
1109 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1110 else if (swap == V_028C70_SWAP_ALT_REV &&
1111 spi_format == V_028714_SPI_SHADER_32_AR)
1112 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1113 break;
1114
1115 case V_028C70_COLOR_16:
1116 case V_028C70_COLOR_16_16:
1117 /* For 1-channel formats, use the superset thereof. */
1118 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1119 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1120 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1121 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1122 if (swap == V_028C70_SWAP_STD ||
1123 swap == V_028C70_SWAP_STD_REV)
1124 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1125 else
1126 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1127 }
1128 break;
1129
1130 case V_028C70_COLOR_10_11_11:
1131 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1132 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1133 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1134 }
1135 break;
1136
1137 case V_028C70_COLOR_2_10_10_10:
1138 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1139 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1140 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1141 }
1142 break;
1143 }
1144 }
1145
1146 /* Do not set the DISABLE bits for the unused attachments, as that
1147 * breaks dual source blending in SkQP and does not seem to improve
1148 * performance. */
1149
1150 if (sx_ps_downconvert == cmd_buffer->state.last_sx_ps_downconvert &&
1151 sx_blend_opt_epsilon == cmd_buffer->state.last_sx_blend_opt_epsilon &&
1152 sx_blend_opt_control == cmd_buffer->state.last_sx_blend_opt_control)
1153 return;
1154
1155 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1156 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1157 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1158 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1159
1160 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1161
1162 cmd_buffer->state.last_sx_ps_downconvert = sx_ps_downconvert;
1163 cmd_buffer->state.last_sx_blend_opt_epsilon = sx_blend_opt_epsilon;
1164 cmd_buffer->state.last_sx_blend_opt_control = sx_blend_opt_control;
1165 }
1166
1167 static void
1168 radv_emit_batch_break_on_new_ps(struct radv_cmd_buffer *cmd_buffer)
1169 {
1170 if (!cmd_buffer->device->pbb_allowed)
1171 return;
1172
1173 struct radv_binning_settings settings =
1174 radv_get_binning_settings(cmd_buffer->device->physical_device);
1175 bool break_for_new_ps =
1176 (!cmd_buffer->state.emitted_pipeline ||
1177 cmd_buffer->state.emitted_pipeline->shaders[MESA_SHADER_FRAGMENT] !=
1178 cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT]) &&
1179 (settings.context_states_per_bin > 1 ||
1180 settings.persistent_states_per_bin > 1);
1181 bool break_for_new_cb_target_mask =
1182 (!cmd_buffer->state.emitted_pipeline ||
1183 cmd_buffer->state.emitted_pipeline->graphics.cb_target_mask !=
1184 cmd_buffer->state.pipeline->graphics.cb_target_mask) &&
1185 settings.context_states_per_bin > 1;
1186
1187 if (!break_for_new_ps && !break_for_new_cb_target_mask)
1188 return;
1189
1190 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1191 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1192 }
1193
1194 static void
1195 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1196 {
1197 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1198
1199 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1200 return;
1201
1202 radv_update_multisample_state(cmd_buffer, pipeline);
1203 radv_update_binning_state(cmd_buffer, pipeline);
1204
1205 cmd_buffer->scratch_size_per_wave_needed = MAX2(cmd_buffer->scratch_size_per_wave_needed,
1206 pipeline->scratch_bytes_per_wave);
1207 cmd_buffer->scratch_waves_wanted = MAX2(cmd_buffer->scratch_waves_wanted,
1208 pipeline->max_waves);
1209
1210 if (!cmd_buffer->state.emitted_pipeline ||
1211 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1212 pipeline->graphics.can_use_guardband)
1213 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1214
1215 if (!cmd_buffer->state.emitted_pipeline ||
1216 cmd_buffer->state.emitted_pipeline->graphics.pa_su_sc_mode_cntl !=
1217 pipeline->graphics.pa_su_sc_mode_cntl)
1218 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_CULL_MODE |
1219 RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE;
1220
1221 if (!cmd_buffer->state.emitted_pipeline)
1222 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY;
1223
1224 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1225
1226 if (!cmd_buffer->state.emitted_pipeline ||
1227 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1228 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1229 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1230 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1231 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1232 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1233 }
1234
1235 radv_emit_batch_break_on_new_ps(cmd_buffer);
1236
1237 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1238 if (!pipeline->shaders[i])
1239 continue;
1240
1241 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1242 pipeline->shaders[i]->bo);
1243 }
1244
1245 if (radv_pipeline_has_gs_copy_shader(pipeline))
1246 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1247 pipeline->gs_copy_shader->bo);
1248
1249 if (unlikely(cmd_buffer->device->trace_bo))
1250 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1251
1252 cmd_buffer->state.emitted_pipeline = pipeline;
1253
1254 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1255 }
1256
1257 static void
1258 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1259 {
1260 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1261 cmd_buffer->state.dynamic.viewport.viewports);
1262 }
1263
1264 static void
1265 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1266 {
1267 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1268
1269 si_write_scissors(cmd_buffer->cs, 0, count,
1270 cmd_buffer->state.dynamic.scissor.scissors,
1271 cmd_buffer->state.dynamic.viewport.viewports,
1272 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1273
1274 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1275 }
1276
1277 static void
1278 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1279 {
1280 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1281 return;
1282
1283 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1284 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1285 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1286 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1287 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1288 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1289 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1290 }
1291 }
1292
1293 static void
1294 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1295 {
1296 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1297
1298 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1299 S_028A08_WIDTH(CLAMP(width, 0, 0xFFFF)));
1300 }
1301
1302 static void
1303 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1304 {
1305 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1306
1307 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1308 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1309 }
1310
1311 static void
1312 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1313 {
1314 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1315
1316 radeon_set_context_reg_seq(cmd_buffer->cs,
1317 R_028430_DB_STENCILREFMASK, 2);
1318 radeon_emit(cmd_buffer->cs,
1319 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1320 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1321 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1322 S_028430_STENCILOPVAL(1));
1323 radeon_emit(cmd_buffer->cs,
1324 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1325 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1326 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1327 S_028434_STENCILOPVAL_BF(1));
1328 }
1329
1330 static void
1331 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1332 {
1333 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1334
1335 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1336 fui(d->depth_bounds.min));
1337 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1338 fui(d->depth_bounds.max));
1339 }
1340
1341 static void
1342 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1343 {
1344 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1345 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1346 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1347
1348
1349 radeon_set_context_reg_seq(cmd_buffer->cs,
1350 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1351 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1352 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1353 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1354 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1355 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1356 }
1357
1358 static void
1359 radv_emit_line_stipple(struct radv_cmd_buffer *cmd_buffer)
1360 {
1361 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1362 uint32_t auto_reset_cntl = 1;
1363
1364 if (d->primitive_topology == V_008958_DI_PT_LINESTRIP)
1365 auto_reset_cntl = 2;
1366
1367 radeon_set_context_reg(cmd_buffer->cs, R_028A0C_PA_SC_LINE_STIPPLE,
1368 S_028A0C_LINE_PATTERN(d->line_stipple.pattern) |
1369 S_028A0C_REPEAT_COUNT(d->line_stipple.factor - 1) |
1370 S_028A0C_AUTO_RESET_CNTL(auto_reset_cntl));
1371 }
1372
1373 static void
1374 radv_emit_culling(struct radv_cmd_buffer *cmd_buffer, uint32_t states)
1375 {
1376 unsigned pa_su_sc_mode_cntl = cmd_buffer->state.pipeline->graphics.pa_su_sc_mode_cntl;
1377 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1378
1379 if (states & RADV_CMD_DIRTY_DYNAMIC_CULL_MODE) {
1380 pa_su_sc_mode_cntl &= C_028814_CULL_FRONT;
1381 pa_su_sc_mode_cntl |= S_028814_CULL_FRONT(!!(d->cull_mode & VK_CULL_MODE_FRONT_BIT));
1382
1383 pa_su_sc_mode_cntl &= C_028814_CULL_BACK;
1384 pa_su_sc_mode_cntl |= S_028814_CULL_BACK(!!(d->cull_mode & VK_CULL_MODE_BACK_BIT));
1385 }
1386
1387 if (states & RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE) {
1388 pa_su_sc_mode_cntl &= C_028814_FACE;
1389 pa_su_sc_mode_cntl |= S_028814_FACE(d->front_face);
1390 }
1391
1392 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
1393 pa_su_sc_mode_cntl);
1394 }
1395
1396 static void
1397 radv_emit_primitive_topology(struct radv_cmd_buffer *cmd_buffer)
1398 {
1399 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1400
1401 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1402 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
1403 cmd_buffer->cs,
1404 R_030908_VGT_PRIMITIVE_TYPE, 1,
1405 d->primitive_topology);
1406 } else {
1407 radeon_set_config_reg(cmd_buffer->cs,
1408 R_008958_VGT_PRIMITIVE_TYPE,
1409 d->primitive_topology);
1410 }
1411 }
1412
1413 static void
1414 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1415 int index,
1416 struct radv_color_buffer_info *cb,
1417 struct radv_image_view *iview,
1418 VkImageLayout layout,
1419 bool in_render_loop)
1420 {
1421 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1422 uint32_t cb_color_info = cb->cb_color_info;
1423 struct radv_image *image = iview->image;
1424
1425 if (!radv_layout_dcc_compressed(cmd_buffer->device, image, layout, in_render_loop,
1426 radv_image_queue_family_mask(image,
1427 cmd_buffer->queue_family_index,
1428 cmd_buffer->queue_family_index))) {
1429 cb_color_info &= C_028C70_DCC_ENABLE;
1430 }
1431
1432 if (!radv_layout_can_fast_clear(image, layout, in_render_loop,
1433 radv_image_queue_family_mask(image,
1434 cmd_buffer->queue_family_index,
1435 cmd_buffer->queue_family_index))) {
1436 cb_color_info &= C_028C70_COMPRESSION;
1437 }
1438
1439 if (radv_image_is_tc_compat_cmask(image) &&
1440 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1441 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1442 /* If this bit is set, the FMASK decompression operation
1443 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1444 */
1445 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1446 }
1447
1448 if (radv_image_has_fmask(image) &&
1449 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1450 radv_is_hw_resolve_pipeline(cmd_buffer))) {
1451 /* Make sure FMASK is enabled if it has been cleared because:
1452 *
1453 * 1) it's required for FMASK_DECOMPRESS operations to avoid
1454 * GPU hangs
1455 * 2) it's necessary for CB_RESOLVE which can read compressed
1456 * FMASK data anyways.
1457 */
1458 cb_color_info |= S_028C70_COMPRESSION(1);
1459 }
1460
1461 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1462 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1463 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1464 radeon_emit(cmd_buffer->cs, 0);
1465 radeon_emit(cmd_buffer->cs, 0);
1466 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1467 radeon_emit(cmd_buffer->cs, cb_color_info);
1468 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1469 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1470 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1471 radeon_emit(cmd_buffer->cs, 0);
1472 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1473 radeon_emit(cmd_buffer->cs, 0);
1474
1475 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1476 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1477
1478 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1479 cb->cb_color_base >> 32);
1480 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1481 cb->cb_color_cmask >> 32);
1482 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1483 cb->cb_color_fmask >> 32);
1484 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1485 cb->cb_dcc_base >> 32);
1486 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1487 cb->cb_color_attrib2);
1488 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1489 cb->cb_color_attrib3);
1490 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1491 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1492 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1493 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1494 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1495 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1496 radeon_emit(cmd_buffer->cs, cb_color_info);
1497 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1498 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1499 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1500 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1501 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1502 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1503
1504 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1505 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1506 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1507
1508 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1509 cb->cb_mrt_epitch);
1510 } else {
1511 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1512 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1513 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1514 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1515 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1516 radeon_emit(cmd_buffer->cs, cb_color_info);
1517 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1518 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1519 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1520 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1521 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1522 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1523
1524 if (is_vi) { /* DCC BASE */
1525 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1526 }
1527 }
1528
1529 if (radv_dcc_enabled(image, iview->base_mip)) {
1530 /* Drawing with DCC enabled also compresses colorbuffers. */
1531 VkImageSubresourceRange range = {
1532 .aspectMask = iview->aspect_mask,
1533 .baseMipLevel = iview->base_mip,
1534 .levelCount = iview->level_count,
1535 .baseArrayLayer = iview->base_layer,
1536 .layerCount = iview->layer_count,
1537 };
1538
1539 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1540 }
1541 }
1542
1543 static void
1544 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1545 struct radv_ds_buffer_info *ds,
1546 const struct radv_image_view *iview,
1547 VkImageLayout layout,
1548 bool in_render_loop, bool requires_cond_exec)
1549 {
1550 const struct radv_image *image = iview->image;
1551 uint32_t db_z_info = ds->db_z_info;
1552 uint32_t db_z_info_reg;
1553
1554 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug ||
1555 !radv_image_is_tc_compat_htile(image))
1556 return;
1557
1558 if (!radv_layout_is_htile_compressed(image, layout, in_render_loop,
1559 radv_image_queue_family_mask(image,
1560 cmd_buffer->queue_family_index,
1561 cmd_buffer->queue_family_index))) {
1562 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1563 }
1564
1565 db_z_info &= C_028040_ZRANGE_PRECISION;
1566
1567 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1568 db_z_info_reg = R_028038_DB_Z_INFO;
1569 } else {
1570 db_z_info_reg = R_028040_DB_Z_INFO;
1571 }
1572
1573 /* When we don't know the last fast clear value we need to emit a
1574 * conditional packet that will eventually skip the following
1575 * SET_CONTEXT_REG packet.
1576 */
1577 if (requires_cond_exec) {
1578 uint64_t va = radv_get_tc_compat_zrange_va(image, iview->base_mip);
1579
1580 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1581 radeon_emit(cmd_buffer->cs, va);
1582 radeon_emit(cmd_buffer->cs, va >> 32);
1583 radeon_emit(cmd_buffer->cs, 0);
1584 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1585 }
1586
1587 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1588 }
1589
1590 static void
1591 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1592 struct radv_ds_buffer_info *ds,
1593 struct radv_image_view *iview,
1594 VkImageLayout layout,
1595 bool in_render_loop)
1596 {
1597 const struct radv_image *image = iview->image;
1598 uint32_t db_z_info = ds->db_z_info;
1599 uint32_t db_stencil_info = ds->db_stencil_info;
1600
1601 if (!radv_layout_is_htile_compressed(image, layout, in_render_loop,
1602 radv_image_queue_family_mask(image,
1603 cmd_buffer->queue_family_index,
1604 cmd_buffer->queue_family_index))) {
1605 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1606 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1607 }
1608
1609 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1610 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1611
1612 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1613 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1614 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1615
1616 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1617 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1618 radeon_emit(cmd_buffer->cs, db_z_info);
1619 radeon_emit(cmd_buffer->cs, db_stencil_info);
1620 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1621 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1622 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1623 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1624
1625 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 5);
1626 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1627 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1628 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1629 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1630 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1631 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1632 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1633 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1634 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1635 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1636
1637 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1638 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1639 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1640 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1641 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1642 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1643 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1644 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1645 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1646 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1647 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1648
1649 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1650 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1651 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1652 } else {
1653 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1654
1655 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1656 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1657 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1658 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1659 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1660 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1661 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1662 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1663 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1664 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1665
1666 }
1667
1668 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1669 radv_update_zrange_precision(cmd_buffer, ds, iview, layout,
1670 in_render_loop, true);
1671
1672 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1673 ds->pa_su_poly_offset_db_fmt_cntl);
1674 }
1675
1676 /**
1677 * Update the fast clear depth/stencil values if the image is bound as a
1678 * depth/stencil buffer.
1679 */
1680 static void
1681 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1682 const struct radv_image_view *iview,
1683 VkClearDepthStencilValue ds_clear_value,
1684 VkImageAspectFlags aspects)
1685 {
1686 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1687 const struct radv_image *image = iview->image;
1688 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1689 uint32_t att_idx;
1690
1691 if (!cmd_buffer->state.attachments || !subpass)
1692 return;
1693
1694 if (!subpass->depth_stencil_attachment)
1695 return;
1696
1697 att_idx = subpass->depth_stencil_attachment->attachment;
1698 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1699 return;
1700
1701 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1702 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1703 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1704 radeon_emit(cs, ds_clear_value.stencil);
1705 radeon_emit(cs, fui(ds_clear_value.depth));
1706 } else if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1707 radeon_set_context_reg_seq(cs, R_02802C_DB_DEPTH_CLEAR, 1);
1708 radeon_emit(cs, fui(ds_clear_value.depth));
1709 } else {
1710 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1711 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 1);
1712 radeon_emit(cs, ds_clear_value.stencil);
1713 }
1714
1715 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1716 * only needed when clearing Z to 0.0.
1717 */
1718 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1719 ds_clear_value.depth == 0.0) {
1720 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1721 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1722
1723 radv_update_zrange_precision(cmd_buffer, &cmd_buffer->state.attachments[att_idx].ds,
1724 iview, layout, in_render_loop, false);
1725 }
1726
1727 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1728 }
1729
1730 /**
1731 * Set the clear depth/stencil values to the image's metadata.
1732 */
1733 static void
1734 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1735 struct radv_image *image,
1736 const VkImageSubresourceRange *range,
1737 VkClearDepthStencilValue ds_clear_value,
1738 VkImageAspectFlags aspects)
1739 {
1740 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1741 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel);
1742 uint32_t level_count = radv_get_levelCount(image, range);
1743
1744 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1745 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1746 /* Use the fastest way when both aspects are used. */
1747 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + 2 * level_count, cmd_buffer->state.predicating));
1748 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1749 S_370_WR_CONFIRM(1) |
1750 S_370_ENGINE_SEL(V_370_PFP));
1751 radeon_emit(cs, va);
1752 radeon_emit(cs, va >> 32);
1753
1754 for (uint32_t l = 0; l < level_count; l++) {
1755 radeon_emit(cs, ds_clear_value.stencil);
1756 radeon_emit(cs, fui(ds_clear_value.depth));
1757 }
1758 } else {
1759 /* Otherwise we need one WRITE_DATA packet per level. */
1760 for (uint32_t l = 0; l < level_count; l++) {
1761 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel + l);
1762 unsigned value;
1763
1764 if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1765 value = fui(ds_clear_value.depth);
1766 va += 4;
1767 } else {
1768 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1769 value = ds_clear_value.stencil;
1770 }
1771
1772 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1773 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1774 S_370_WR_CONFIRM(1) |
1775 S_370_ENGINE_SEL(V_370_PFP));
1776 radeon_emit(cs, va);
1777 radeon_emit(cs, va >> 32);
1778 radeon_emit(cs, value);
1779 }
1780 }
1781 }
1782
1783 /**
1784 * Update the TC-compat metadata value for this image.
1785 */
1786 static void
1787 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1788 struct radv_image *image,
1789 const VkImageSubresourceRange *range,
1790 uint32_t value)
1791 {
1792 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1793
1794 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug)
1795 return;
1796
1797 uint64_t va = radv_get_tc_compat_zrange_va(image, range->baseMipLevel);
1798 uint32_t level_count = radv_get_levelCount(image, range);
1799
1800 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + level_count, cmd_buffer->state.predicating));
1801 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1802 S_370_WR_CONFIRM(1) |
1803 S_370_ENGINE_SEL(V_370_PFP));
1804 radeon_emit(cs, va);
1805 radeon_emit(cs, va >> 32);
1806
1807 for (uint32_t l = 0; l < level_count; l++)
1808 radeon_emit(cs, value);
1809 }
1810
1811 static void
1812 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1813 const struct radv_image_view *iview,
1814 VkClearDepthStencilValue ds_clear_value)
1815 {
1816 VkImageSubresourceRange range = {
1817 .aspectMask = iview->aspect_mask,
1818 .baseMipLevel = iview->base_mip,
1819 .levelCount = iview->level_count,
1820 .baseArrayLayer = iview->base_layer,
1821 .layerCount = iview->layer_count,
1822 };
1823 uint32_t cond_val;
1824
1825 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1826 * depth clear value is 0.0f.
1827 */
1828 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1829
1830 radv_set_tc_compat_zrange_metadata(cmd_buffer, iview->image, &range,
1831 cond_val);
1832 }
1833
1834 /**
1835 * Update the clear depth/stencil values for this image.
1836 */
1837 void
1838 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1839 const struct radv_image_view *iview,
1840 VkClearDepthStencilValue ds_clear_value,
1841 VkImageAspectFlags aspects)
1842 {
1843 VkImageSubresourceRange range = {
1844 .aspectMask = iview->aspect_mask,
1845 .baseMipLevel = iview->base_mip,
1846 .levelCount = iview->level_count,
1847 .baseArrayLayer = iview->base_layer,
1848 .layerCount = iview->layer_count,
1849 };
1850 struct radv_image *image = iview->image;
1851
1852 assert(radv_image_has_htile(image));
1853
1854 radv_set_ds_clear_metadata(cmd_buffer, iview->image, &range,
1855 ds_clear_value, aspects);
1856
1857 if (radv_image_is_tc_compat_htile(image) &&
1858 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1859 radv_update_tc_compat_zrange_metadata(cmd_buffer, iview,
1860 ds_clear_value);
1861 }
1862
1863 radv_update_bound_fast_clear_ds(cmd_buffer, iview, ds_clear_value,
1864 aspects);
1865 }
1866
1867 /**
1868 * Load the clear depth/stencil values from the image's metadata.
1869 */
1870 static void
1871 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1872 const struct radv_image_view *iview)
1873 {
1874 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1875 const struct radv_image *image = iview->image;
1876 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1877 uint64_t va = radv_get_ds_clear_value_va(image, iview->base_mip);
1878 unsigned reg_offset = 0, reg_count = 0;
1879
1880 if (!radv_image_has_htile(image))
1881 return;
1882
1883 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1884 ++reg_count;
1885 } else {
1886 ++reg_offset;
1887 va += 4;
1888 }
1889 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1890 ++reg_count;
1891
1892 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1893
1894 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1895 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, 0));
1896 radeon_emit(cs, va);
1897 radeon_emit(cs, va >> 32);
1898 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1899 radeon_emit(cs, reg_count);
1900 } else {
1901 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1902 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1903 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1904 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1905 radeon_emit(cs, va);
1906 radeon_emit(cs, va >> 32);
1907 radeon_emit(cs, reg >> 2);
1908 radeon_emit(cs, 0);
1909
1910 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1911 radeon_emit(cs, 0);
1912 }
1913 }
1914
1915 /*
1916 * With DCC some colors don't require CMASK elimination before being
1917 * used as a texture. This sets a predicate value to determine if the
1918 * cmask eliminate is required.
1919 */
1920 void
1921 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1922 struct radv_image *image,
1923 const VkImageSubresourceRange *range, bool value)
1924 {
1925 uint64_t pred_val = value;
1926 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
1927 uint32_t level_count = radv_get_levelCount(image, range);
1928 uint32_t count = 2 * level_count;
1929
1930 assert(radv_dcc_enabled(image, range->baseMipLevel));
1931
1932 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1933 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1934 S_370_WR_CONFIRM(1) |
1935 S_370_ENGINE_SEL(V_370_PFP));
1936 radeon_emit(cmd_buffer->cs, va);
1937 radeon_emit(cmd_buffer->cs, va >> 32);
1938
1939 for (uint32_t l = 0; l < level_count; l++) {
1940 radeon_emit(cmd_buffer->cs, pred_val);
1941 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1942 }
1943 }
1944
1945 /**
1946 * Update the DCC predicate to reflect the compression state.
1947 */
1948 void
1949 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1950 struct radv_image *image,
1951 const VkImageSubresourceRange *range, bool value)
1952 {
1953 uint64_t pred_val = value;
1954 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
1955 uint32_t level_count = radv_get_levelCount(image, range);
1956 uint32_t count = 2 * level_count;
1957
1958 assert(radv_dcc_enabled(image, range->baseMipLevel));
1959
1960 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1961 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1962 S_370_WR_CONFIRM(1) |
1963 S_370_ENGINE_SEL(V_370_PFP));
1964 radeon_emit(cmd_buffer->cs, va);
1965 radeon_emit(cmd_buffer->cs, va >> 32);
1966
1967 for (uint32_t l = 0; l < level_count; l++) {
1968 radeon_emit(cmd_buffer->cs, pred_val);
1969 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1970 }
1971 }
1972
1973 /**
1974 * Update the fast clear color values if the image is bound as a color buffer.
1975 */
1976 static void
1977 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1978 struct radv_image *image,
1979 int cb_idx,
1980 uint32_t color_values[2])
1981 {
1982 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1983 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1984 uint32_t att_idx;
1985
1986 if (!cmd_buffer->state.attachments || !subpass)
1987 return;
1988
1989 att_idx = subpass->color_attachments[cb_idx].attachment;
1990 if (att_idx == VK_ATTACHMENT_UNUSED)
1991 return;
1992
1993 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1994 return;
1995
1996 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1997 radeon_emit(cs, color_values[0]);
1998 radeon_emit(cs, color_values[1]);
1999
2000 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2001 }
2002
2003 /**
2004 * Set the clear color values to the image's metadata.
2005 */
2006 static void
2007 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
2008 struct radv_image *image,
2009 const VkImageSubresourceRange *range,
2010 uint32_t color_values[2])
2011 {
2012 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2013 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
2014 uint32_t level_count = radv_get_levelCount(image, range);
2015 uint32_t count = 2 * level_count;
2016
2017 assert(radv_image_has_cmask(image) ||
2018 radv_dcc_enabled(image, range->baseMipLevel));
2019
2020 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
2021 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
2022 S_370_WR_CONFIRM(1) |
2023 S_370_ENGINE_SEL(V_370_PFP));
2024 radeon_emit(cs, va);
2025 radeon_emit(cs, va >> 32);
2026
2027 for (uint32_t l = 0; l < level_count; l++) {
2028 radeon_emit(cs, color_values[0]);
2029 radeon_emit(cs, color_values[1]);
2030 }
2031 }
2032
2033 /**
2034 * Update the clear color values for this image.
2035 */
2036 void
2037 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
2038 const struct radv_image_view *iview,
2039 int cb_idx,
2040 uint32_t color_values[2])
2041 {
2042 struct radv_image *image = iview->image;
2043 VkImageSubresourceRange range = {
2044 .aspectMask = iview->aspect_mask,
2045 .baseMipLevel = iview->base_mip,
2046 .levelCount = iview->level_count,
2047 .baseArrayLayer = iview->base_layer,
2048 .layerCount = iview->layer_count,
2049 };
2050
2051 assert(radv_image_has_cmask(image) ||
2052 radv_dcc_enabled(image, iview->base_mip));
2053
2054 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
2055
2056 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
2057 color_values);
2058 }
2059
2060 /**
2061 * Load the clear color values from the image's metadata.
2062 */
2063 static void
2064 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
2065 struct radv_image_view *iview,
2066 int cb_idx)
2067 {
2068 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2069 struct radv_image *image = iview->image;
2070 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
2071
2072 if (!radv_image_has_cmask(image) &&
2073 !radv_dcc_enabled(image, iview->base_mip))
2074 return;
2075
2076 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
2077
2078 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
2079 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, cmd_buffer->state.predicating));
2080 radeon_emit(cs, va);
2081 radeon_emit(cs, va >> 32);
2082 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
2083 radeon_emit(cs, 2);
2084 } else {
2085 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
2086 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2087 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2088 COPY_DATA_COUNT_SEL);
2089 radeon_emit(cs, va);
2090 radeon_emit(cs, va >> 32);
2091 radeon_emit(cs, reg >> 2);
2092 radeon_emit(cs, 0);
2093
2094 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
2095 radeon_emit(cs, 0);
2096 }
2097 }
2098
2099 static void
2100 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
2101 {
2102 int i;
2103 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
2104 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2105
2106 /* this may happen for inherited secondary recording */
2107 if (!framebuffer)
2108 return;
2109
2110 for (i = 0; i < 8; ++i) {
2111 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
2112 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2113 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2114 continue;
2115 }
2116
2117 int idx = subpass->color_attachments[i].attachment;
2118 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2119 VkImageLayout layout = subpass->color_attachments[i].layout;
2120 bool in_render_loop = subpass->color_attachments[i].in_render_loop;
2121
2122 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->bo);
2123
2124 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
2125 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
2126 radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout, in_render_loop);
2127
2128 radv_load_color_clear_metadata(cmd_buffer, iview, i);
2129 }
2130
2131 if (subpass->depth_stencil_attachment) {
2132 int idx = subpass->depth_stencil_attachment->attachment;
2133 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
2134 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
2135 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2136 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->state.attachments[idx].iview->bo);
2137
2138 radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, iview, layout, in_render_loop);
2139
2140 if (cmd_buffer->state.attachments[idx].ds.offset_scale != cmd_buffer->state.offset_scale) {
2141 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2142 cmd_buffer->state.offset_scale = cmd_buffer->state.attachments[idx].ds.offset_scale;
2143 }
2144 radv_load_ds_clear_metadata(cmd_buffer, iview);
2145 } else {
2146 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
2147 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
2148 else
2149 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
2150
2151 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2152 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2153 }
2154 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2155 S_028208_BR_X(framebuffer->width) |
2156 S_028208_BR_Y(framebuffer->height));
2157
2158 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
2159 bool disable_constant_encode =
2160 cmd_buffer->device->physical_device->rad_info.has_dcc_constant_encode;
2161 enum chip_class chip_class =
2162 cmd_buffer->device->physical_device->rad_info.chip_class;
2163 uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
2164
2165 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
2166 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
2167 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
2168 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
2169 }
2170
2171 if (cmd_buffer->device->dfsm_allowed) {
2172 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2173 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2174 }
2175
2176 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
2177 }
2178
2179 static void
2180 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer, bool indirect)
2181 {
2182 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2183 struct radv_cmd_state *state = &cmd_buffer->state;
2184
2185 if (state->index_type != state->last_index_type) {
2186 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2187 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2188 cs, R_03090C_VGT_INDEX_TYPE,
2189 2, state->index_type);
2190 } else {
2191 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2192 radeon_emit(cs, state->index_type);
2193 }
2194
2195 state->last_index_type = state->index_type;
2196 }
2197
2198 /* For the direct indexed draws we use DRAW_INDEX_2, which includes
2199 * the index_va and max_index_count already. */
2200 if (!indirect)
2201 return;
2202
2203 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2204 radeon_emit(cs, state->index_va);
2205 radeon_emit(cs, state->index_va >> 32);
2206
2207 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2208 radeon_emit(cs, state->max_index_count);
2209
2210 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
2211 }
2212
2213 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
2214 {
2215 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
2216 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2217 uint32_t pa_sc_mode_cntl_1 =
2218 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
2219 uint32_t db_count_control;
2220
2221 if(!cmd_buffer->state.active_occlusion_queries) {
2222 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2223 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2224 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2225 has_perfect_queries) {
2226 /* Re-enable out-of-order rasterization if the
2227 * bound pipeline supports it and if it's has
2228 * been disabled before starting any perfect
2229 * occlusion queries.
2230 */
2231 radeon_set_context_reg(cmd_buffer->cs,
2232 R_028A4C_PA_SC_MODE_CNTL_1,
2233 pa_sc_mode_cntl_1);
2234 }
2235 }
2236 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
2237 } else {
2238 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2239 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
2240 bool gfx10_perfect = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries;
2241
2242 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2243 /* Always enable PERFECT_ZPASS_COUNTS due to issues with partially
2244 * covered tiles, discards, and early depth testing. For more details,
2245 * see https://gitlab.freedesktop.org/mesa/mesa/-/issues/3218 */
2246 db_count_control =
2247 S_028004_PERFECT_ZPASS_COUNTS(1) |
2248 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
2249 S_028004_SAMPLE_RATE(sample_rate) |
2250 S_028004_ZPASS_ENABLE(1) |
2251 S_028004_SLICE_EVEN_ENABLE(1) |
2252 S_028004_SLICE_ODD_ENABLE(1);
2253
2254 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2255 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2256 has_perfect_queries) {
2257 /* If the bound pipeline has enabled
2258 * out-of-order rasterization, we should
2259 * disable it before starting any perfect
2260 * occlusion queries.
2261 */
2262 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2263
2264 radeon_set_context_reg(cmd_buffer->cs,
2265 R_028A4C_PA_SC_MODE_CNTL_1,
2266 pa_sc_mode_cntl_1);
2267 }
2268 } else {
2269 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2270 S_028004_SAMPLE_RATE(sample_rate);
2271 }
2272 }
2273
2274 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2275
2276 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2277 }
2278
2279 static void
2280 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2281 {
2282 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2283
2284 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2285 radv_emit_viewport(cmd_buffer);
2286
2287 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2288 !cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
2289 radv_emit_scissor(cmd_buffer);
2290
2291 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2292 radv_emit_line_width(cmd_buffer);
2293
2294 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2295 radv_emit_blend_constants(cmd_buffer);
2296
2297 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2298 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2299 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2300 radv_emit_stencil(cmd_buffer);
2301
2302 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2303 radv_emit_depth_bounds(cmd_buffer);
2304
2305 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2306 radv_emit_depth_bias(cmd_buffer);
2307
2308 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2309 radv_emit_discard_rectangle(cmd_buffer);
2310
2311 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2312 radv_emit_sample_locations(cmd_buffer);
2313
2314 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2315 radv_emit_line_stipple(cmd_buffer);
2316
2317 if (states & (RADV_CMD_DIRTY_DYNAMIC_CULL_MODE |
2318 RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE))
2319 radv_emit_culling(cmd_buffer, states);
2320
2321 if (states & RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY)
2322 radv_emit_primitive_topology(cmd_buffer);
2323
2324 cmd_buffer->state.dirty &= ~states;
2325 }
2326
2327 static void
2328 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2329 VkPipelineBindPoint bind_point)
2330 {
2331 struct radv_descriptor_state *descriptors_state =
2332 radv_get_descriptors_state(cmd_buffer, bind_point);
2333 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2334 unsigned bo_offset;
2335
2336 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2337 set->mapped_ptr,
2338 &bo_offset))
2339 return;
2340
2341 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2342 set->va += bo_offset;
2343 }
2344
2345 static void
2346 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2347 VkPipelineBindPoint bind_point)
2348 {
2349 struct radv_descriptor_state *descriptors_state =
2350 radv_get_descriptors_state(cmd_buffer, bind_point);
2351 uint32_t size = MAX_SETS * 4;
2352 uint32_t offset;
2353 void *ptr;
2354
2355 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2356 256, &offset, &ptr))
2357 return;
2358
2359 for (unsigned i = 0; i < MAX_SETS; i++) {
2360 uint32_t *uptr = ((uint32_t *)ptr) + i;
2361 uint64_t set_va = 0;
2362 struct radv_descriptor_set *set = descriptors_state->sets[i];
2363 if (descriptors_state->valid & (1u << i))
2364 set_va = set->va;
2365 uptr[0] = set_va & 0xffffffff;
2366 }
2367
2368 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2369 va += offset;
2370
2371 if (cmd_buffer->state.pipeline) {
2372 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2373 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2374 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2375
2376 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2377 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2378 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2379
2380 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2381 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2382 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2383
2384 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2385 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2386 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2387
2388 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2389 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2390 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2391 }
2392
2393 if (cmd_buffer->state.compute_pipeline)
2394 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2395 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2396 }
2397
2398 static void
2399 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2400 VkShaderStageFlags stages)
2401 {
2402 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2403 VK_PIPELINE_BIND_POINT_COMPUTE :
2404 VK_PIPELINE_BIND_POINT_GRAPHICS;
2405 struct radv_descriptor_state *descriptors_state =
2406 radv_get_descriptors_state(cmd_buffer, bind_point);
2407 struct radv_cmd_state *state = &cmd_buffer->state;
2408 bool flush_indirect_descriptors;
2409
2410 if (!descriptors_state->dirty)
2411 return;
2412
2413 if (descriptors_state->push_dirty)
2414 radv_flush_push_descriptors(cmd_buffer, bind_point);
2415
2416 flush_indirect_descriptors =
2417 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2418 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2419 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2420 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2421
2422 if (flush_indirect_descriptors)
2423 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2424
2425 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2426 cmd_buffer->cs,
2427 MAX_SETS * MESA_SHADER_STAGES * 4);
2428
2429 if (cmd_buffer->state.pipeline) {
2430 radv_foreach_stage(stage, stages) {
2431 if (!cmd_buffer->state.pipeline->shaders[stage])
2432 continue;
2433
2434 radv_emit_descriptor_pointers(cmd_buffer,
2435 cmd_buffer->state.pipeline,
2436 descriptors_state, stage);
2437 }
2438 }
2439
2440 if (cmd_buffer->state.compute_pipeline &&
2441 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2442 radv_emit_descriptor_pointers(cmd_buffer,
2443 cmd_buffer->state.compute_pipeline,
2444 descriptors_state,
2445 MESA_SHADER_COMPUTE);
2446 }
2447
2448 descriptors_state->dirty = 0;
2449 descriptors_state->push_dirty = false;
2450
2451 assert(cmd_buffer->cs->cdw <= cdw_max);
2452
2453 if (unlikely(cmd_buffer->device->trace_bo))
2454 radv_save_descriptors(cmd_buffer, bind_point);
2455 }
2456
2457 static void
2458 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2459 VkShaderStageFlags stages)
2460 {
2461 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2462 ? cmd_buffer->state.compute_pipeline
2463 : cmd_buffer->state.pipeline;
2464 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2465 VK_PIPELINE_BIND_POINT_COMPUTE :
2466 VK_PIPELINE_BIND_POINT_GRAPHICS;
2467 struct radv_descriptor_state *descriptors_state =
2468 radv_get_descriptors_state(cmd_buffer, bind_point);
2469 struct radv_pipeline_layout *layout = pipeline->layout;
2470 struct radv_shader_variant *shader, *prev_shader;
2471 bool need_push_constants = false;
2472 unsigned offset;
2473 void *ptr;
2474 uint64_t va;
2475
2476 stages &= cmd_buffer->push_constant_stages;
2477 if (!stages ||
2478 (!layout->push_constant_size && !layout->dynamic_offset_count))
2479 return;
2480
2481 radv_foreach_stage(stage, stages) {
2482 shader = radv_get_shader(pipeline, stage);
2483 if (!shader)
2484 continue;
2485
2486 need_push_constants |= shader->info.loads_push_constants;
2487 need_push_constants |= shader->info.loads_dynamic_offsets;
2488
2489 uint8_t base = shader->info.base_inline_push_consts;
2490 uint8_t count = shader->info.num_inline_push_consts;
2491
2492 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2493 AC_UD_INLINE_PUSH_CONSTANTS,
2494 count,
2495 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2496 }
2497
2498 if (need_push_constants) {
2499 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2500 16 * layout->dynamic_offset_count,
2501 256, &offset, &ptr))
2502 return;
2503
2504 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2505 memcpy((char*)ptr + layout->push_constant_size,
2506 descriptors_state->dynamic_buffers,
2507 16 * layout->dynamic_offset_count);
2508
2509 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2510 va += offset;
2511
2512 ASSERTED unsigned cdw_max =
2513 radeon_check_space(cmd_buffer->device->ws,
2514 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2515
2516 prev_shader = NULL;
2517 radv_foreach_stage(stage, stages) {
2518 shader = radv_get_shader(pipeline, stage);
2519
2520 /* Avoid redundantly emitting the address for merged stages. */
2521 if (shader && shader != prev_shader) {
2522 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2523 AC_UD_PUSH_CONSTANTS, va);
2524
2525 prev_shader = shader;
2526 }
2527 }
2528 assert(cmd_buffer->cs->cdw <= cdw_max);
2529 }
2530
2531 cmd_buffer->push_constant_stages &= ~stages;
2532 }
2533
2534 static void
2535 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2536 bool pipeline_is_dirty)
2537 {
2538 if ((pipeline_is_dirty ||
2539 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2540 cmd_buffer->state.pipeline->num_vertex_bindings &&
2541 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.has_vertex_buffers) {
2542 unsigned vb_offset;
2543 void *vb_ptr;
2544 uint32_t i = 0;
2545 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2546 uint64_t va;
2547
2548 /* allocate some descriptor state for vertex buffers */
2549 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2550 &vb_offset, &vb_ptr))
2551 return;
2552
2553 for (i = 0; i < count; i++) {
2554 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2555 uint32_t offset;
2556 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2557 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2558 unsigned num_records;
2559
2560 if (!buffer)
2561 continue;
2562
2563 va = radv_buffer_get_va(buffer->bo);
2564
2565 offset = cmd_buffer->vertex_bindings[i].offset;
2566 va += offset + buffer->offset;
2567
2568 num_records = buffer->size - offset;
2569 if (cmd_buffer->device->physical_device->rad_info.chip_class != GFX8 && stride)
2570 num_records /= stride;
2571
2572 desc[0] = va;
2573 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2574 desc[2] = num_records;
2575 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2576 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2577 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2578 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2579
2580 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2581 /* OOB_SELECT chooses the out-of-bounds check:
2582 * - 1: index >= NUM_RECORDS (Structured)
2583 * - 3: offset >= NUM_RECORDS (Raw)
2584 */
2585 int oob_select = stride ? V_008F0C_OOB_SELECT_STRUCTURED : V_008F0C_OOB_SELECT_RAW;
2586
2587 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
2588 S_008F0C_OOB_SELECT(oob_select) |
2589 S_008F0C_RESOURCE_LEVEL(1);
2590 } else {
2591 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2592 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2593 }
2594 }
2595
2596 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2597 va += vb_offset;
2598
2599 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2600 AC_UD_VS_VERTEX_BUFFERS, va);
2601
2602 cmd_buffer->state.vb_va = va;
2603 cmd_buffer->state.vb_size = count * 16;
2604 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2605 }
2606 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2607 }
2608
2609 static void
2610 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2611 {
2612 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2613 struct radv_userdata_info *loc;
2614 uint32_t base_reg;
2615
2616 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2617 if (!radv_get_shader(pipeline, stage))
2618 continue;
2619
2620 loc = radv_lookup_user_sgpr(pipeline, stage,
2621 AC_UD_STREAMOUT_BUFFERS);
2622 if (loc->sgpr_idx == -1)
2623 continue;
2624
2625 base_reg = pipeline->user_data_0[stage];
2626
2627 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2628 base_reg + loc->sgpr_idx * 4, va, false);
2629 }
2630
2631 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
2632 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2633 if (loc->sgpr_idx != -1) {
2634 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2635
2636 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2637 base_reg + loc->sgpr_idx * 4, va, false);
2638 }
2639 }
2640 }
2641
2642 static void
2643 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2644 {
2645 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2646 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2647 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2648 unsigned so_offset;
2649 void *so_ptr;
2650 uint64_t va;
2651
2652 /* Allocate some descriptor state for streamout buffers. */
2653 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2654 MAX_SO_BUFFERS * 16, 256,
2655 &so_offset, &so_ptr))
2656 return;
2657
2658 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2659 struct radv_buffer *buffer = sb[i].buffer;
2660 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2661
2662 if (!(so->enabled_mask & (1 << i)))
2663 continue;
2664
2665 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2666
2667 va += sb[i].offset;
2668
2669 /* Set the descriptor.
2670 *
2671 * On GFX8, the format must be non-INVALID, otherwise
2672 * the buffer will be considered not bound and store
2673 * instructions will be no-ops.
2674 */
2675 uint32_t size = 0xffffffff;
2676
2677 /* Compute the correct buffer size for NGG streamout
2678 * because it's used to determine the max emit per
2679 * buffer.
2680 */
2681 if (cmd_buffer->device->physical_device->use_ngg_streamout)
2682 size = buffer->size - sb[i].offset;
2683
2684 desc[0] = va;
2685 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2686 desc[2] = size;
2687 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2688 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2689 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2690 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2691
2692 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2693 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2694 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
2695 S_008F0C_RESOURCE_LEVEL(1);
2696 } else {
2697 desc[3] |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2698 }
2699 }
2700
2701 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2702 va += so_offset;
2703
2704 radv_emit_streamout_buffers(cmd_buffer, va);
2705 }
2706
2707 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2708 }
2709
2710 static void
2711 radv_flush_ngg_gs_state(struct radv_cmd_buffer *cmd_buffer)
2712 {
2713 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2714 struct radv_userdata_info *loc;
2715 uint32_t ngg_gs_state = 0;
2716 uint32_t base_reg;
2717
2718 if (!radv_pipeline_has_gs(pipeline) ||
2719 !radv_pipeline_has_ngg(pipeline))
2720 return;
2721
2722 /* By default NGG GS queries are disabled but they are enabled if the
2723 * command buffer has active GDS queries or if it's a secondary command
2724 * buffer that inherits the number of generated primitives.
2725 */
2726 if (cmd_buffer->state.active_pipeline_gds_queries ||
2727 (cmd_buffer->state.inherited_pipeline_statistics & VK_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_PRIMITIVES_BIT))
2728 ngg_gs_state = 1;
2729
2730 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_GEOMETRY,
2731 AC_UD_NGG_GS_STATE);
2732 base_reg = pipeline->user_data_0[MESA_SHADER_GEOMETRY];
2733 assert(loc->sgpr_idx != -1);
2734
2735 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
2736 ngg_gs_state);
2737 }
2738
2739 static void
2740 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2741 {
2742 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2743 radv_flush_streamout_descriptors(cmd_buffer);
2744 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2745 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2746 radv_flush_ngg_gs_state(cmd_buffer);
2747 }
2748
2749 struct radv_draw_info {
2750 /**
2751 * Number of vertices.
2752 */
2753 uint32_t count;
2754
2755 /**
2756 * Index of the first vertex.
2757 */
2758 int32_t vertex_offset;
2759
2760 /**
2761 * First instance id.
2762 */
2763 uint32_t first_instance;
2764
2765 /**
2766 * Number of instances.
2767 */
2768 uint32_t instance_count;
2769
2770 /**
2771 * First index (indexed draws only).
2772 */
2773 uint32_t first_index;
2774
2775 /**
2776 * Whether it's an indexed draw.
2777 */
2778 bool indexed;
2779
2780 /**
2781 * Indirect draw parameters resource.
2782 */
2783 struct radv_buffer *indirect;
2784 uint64_t indirect_offset;
2785 uint32_t stride;
2786
2787 /**
2788 * Draw count parameters resource.
2789 */
2790 struct radv_buffer *count_buffer;
2791 uint64_t count_buffer_offset;
2792
2793 /**
2794 * Stream output parameters resource.
2795 */
2796 struct radv_buffer *strmout_buffer;
2797 uint64_t strmout_buffer_offset;
2798 };
2799
2800 static uint32_t
2801 radv_get_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2802 {
2803 switch (cmd_buffer->state.index_type) {
2804 case V_028A7C_VGT_INDEX_8:
2805 return 0xffu;
2806 case V_028A7C_VGT_INDEX_16:
2807 return 0xffffu;
2808 case V_028A7C_VGT_INDEX_32:
2809 return 0xffffffffu;
2810 default:
2811 unreachable("invalid index type");
2812 }
2813 }
2814
2815 static void
2816 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
2817 bool instanced_draw, bool indirect_draw,
2818 bool count_from_stream_output,
2819 uint32_t draw_vertex_count)
2820 {
2821 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2822 struct radv_cmd_state *state = &cmd_buffer->state;
2823 unsigned topology = state->dynamic.primitive_topology;
2824 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2825 unsigned ia_multi_vgt_param;
2826
2827 ia_multi_vgt_param =
2828 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2829 indirect_draw,
2830 count_from_stream_output,
2831 draw_vertex_count,
2832 topology);
2833
2834 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2835 if (info->chip_class == GFX9) {
2836 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2837 cs,
2838 R_030960_IA_MULTI_VGT_PARAM,
2839 4, ia_multi_vgt_param);
2840 } else if (info->chip_class >= GFX7) {
2841 radeon_set_context_reg_idx(cs,
2842 R_028AA8_IA_MULTI_VGT_PARAM,
2843 1, ia_multi_vgt_param);
2844 } else {
2845 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2846 ia_multi_vgt_param);
2847 }
2848 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2849 }
2850 }
2851
2852 static void
2853 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2854 const struct radv_draw_info *draw_info)
2855 {
2856 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2857 struct radv_cmd_state *state = &cmd_buffer->state;
2858 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2859 int32_t primitive_reset_en;
2860
2861 /* Draw state. */
2862 if (info->chip_class < GFX10) {
2863 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2864 draw_info->indirect,
2865 !!draw_info->strmout_buffer,
2866 draw_info->indirect ? 0 : draw_info->count);
2867 }
2868
2869 /* Primitive restart. */
2870 primitive_reset_en =
2871 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2872
2873 if (primitive_reset_en != state->last_primitive_reset_en) {
2874 state->last_primitive_reset_en = primitive_reset_en;
2875 if (info->chip_class >= GFX9) {
2876 radeon_set_uconfig_reg(cs,
2877 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2878 primitive_reset_en);
2879 } else {
2880 radeon_set_context_reg(cs,
2881 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2882 primitive_reset_en);
2883 }
2884 }
2885
2886 if (primitive_reset_en) {
2887 uint32_t primitive_reset_index =
2888 radv_get_primitive_reset_index(cmd_buffer);
2889
2890 if (primitive_reset_index != state->last_primitive_reset_index) {
2891 radeon_set_context_reg(cs,
2892 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2893 primitive_reset_index);
2894 state->last_primitive_reset_index = primitive_reset_index;
2895 }
2896 }
2897
2898 if (draw_info->strmout_buffer) {
2899 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2900
2901 va += draw_info->strmout_buffer->offset +
2902 draw_info->strmout_buffer_offset;
2903
2904 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2905 draw_info->stride);
2906
2907 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2908 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2909 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2910 COPY_DATA_WR_CONFIRM);
2911 radeon_emit(cs, va);
2912 radeon_emit(cs, va >> 32);
2913 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2914 radeon_emit(cs, 0); /* unused */
2915
2916 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2917 }
2918 }
2919
2920 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2921 VkPipelineStageFlags src_stage_mask)
2922 {
2923 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2924 VK_PIPELINE_STAGE_TRANSFER_BIT |
2925 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2926 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2927 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2928 }
2929
2930 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2931 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2932 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2933 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2934 VK_PIPELINE_STAGE_TRANSFER_BIT |
2935 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2936 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2937 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2938 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2939 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2940 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2941 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2942 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2943 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2944 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2945 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2946 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2947 }
2948 }
2949
2950 static enum radv_cmd_flush_bits
2951 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2952 VkAccessFlags src_flags,
2953 struct radv_image *image)
2954 {
2955 bool flush_CB_meta = true, flush_DB_meta = true;
2956 enum radv_cmd_flush_bits flush_bits = 0;
2957 uint32_t b;
2958
2959 if (image) {
2960 if (!radv_image_has_CB_metadata(image))
2961 flush_CB_meta = false;
2962 if (!radv_image_has_htile(image))
2963 flush_DB_meta = false;
2964 }
2965
2966 for_each_bit(b, src_flags) {
2967 switch ((VkAccessFlagBits)(1 << b)) {
2968 case VK_ACCESS_SHADER_WRITE_BIT:
2969 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2970 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2971 flush_bits |= RADV_CMD_FLAG_WB_L2;
2972 break;
2973 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2974 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2975 if (flush_CB_meta)
2976 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2977 break;
2978 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2979 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2980 if (flush_DB_meta)
2981 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2982 break;
2983 case VK_ACCESS_TRANSFER_WRITE_BIT:
2984 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2985 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2986 RADV_CMD_FLAG_INV_L2;
2987
2988 if (flush_CB_meta)
2989 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2990 if (flush_DB_meta)
2991 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2992 break;
2993 case VK_ACCESS_MEMORY_WRITE_BIT:
2994 flush_bits |= RADV_CMD_FLAG_INV_L2 |
2995 RADV_CMD_FLAG_WB_L2 |
2996 RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2997 RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2998
2999 if (flush_CB_meta)
3000 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3001 if (flush_DB_meta)
3002 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3003 break;
3004 default:
3005 break;
3006 }
3007 }
3008 return flush_bits;
3009 }
3010
3011 static enum radv_cmd_flush_bits
3012 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
3013 VkAccessFlags dst_flags,
3014 struct radv_image *image)
3015 {
3016 bool flush_CB_meta = true, flush_DB_meta = true;
3017 enum radv_cmd_flush_bits flush_bits = 0;
3018 bool flush_CB = true, flush_DB = true;
3019 bool image_is_coherent = false;
3020 uint32_t b;
3021
3022 if (image) {
3023 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
3024 flush_CB = false;
3025 flush_DB = false;
3026 }
3027
3028 if (!radv_image_has_CB_metadata(image))
3029 flush_CB_meta = false;
3030 if (!radv_image_has_htile(image))
3031 flush_DB_meta = false;
3032
3033 /* TODO: implement shader coherent for GFX10 */
3034
3035 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
3036 if (image->info.samples == 1 &&
3037 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
3038 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
3039 !vk_format_is_stencil(image->vk_format)) {
3040 /* Single-sample color and single-sample depth
3041 * (not stencil) are coherent with shaders on
3042 * GFX9.
3043 */
3044 image_is_coherent = true;
3045 }
3046 }
3047 }
3048
3049 for_each_bit(b, dst_flags) {
3050 switch ((VkAccessFlagBits)(1 << b)) {
3051 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
3052 case VK_ACCESS_INDEX_READ_BIT:
3053 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
3054 break;
3055 case VK_ACCESS_UNIFORM_READ_BIT:
3056 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
3057 break;
3058 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
3059 case VK_ACCESS_TRANSFER_READ_BIT:
3060 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
3061 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
3062 RADV_CMD_FLAG_INV_L2;
3063 break;
3064 case VK_ACCESS_SHADER_READ_BIT:
3065 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
3066 /* Unlike LLVM, ACO uses SMEM for SSBOs and we have to
3067 * invalidate the scalar cache. */
3068 if (!cmd_buffer->device->physical_device->use_llvm)
3069 flush_bits |= RADV_CMD_FLAG_INV_SCACHE;
3070
3071 if (!image_is_coherent)
3072 flush_bits |= RADV_CMD_FLAG_INV_L2;
3073 break;
3074 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
3075 if (flush_CB)
3076 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
3077 if (flush_CB_meta)
3078 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3079 break;
3080 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
3081 if (flush_DB)
3082 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
3083 if (flush_DB_meta)
3084 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3085 break;
3086 case VK_ACCESS_MEMORY_READ_BIT:
3087 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
3088 RADV_CMD_FLAG_INV_SCACHE |
3089 RADV_CMD_FLAG_INV_L2;
3090 if (flush_CB)
3091 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
3092 if (flush_CB_meta)
3093 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3094 if (flush_DB)
3095 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
3096 if (flush_DB_meta)
3097 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3098 break;
3099 default:
3100 break;
3101 }
3102 }
3103 return flush_bits;
3104 }
3105
3106 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
3107 const struct radv_subpass_barrier *barrier)
3108 {
3109 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
3110 NULL);
3111 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
3112 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
3113 NULL);
3114 }
3115
3116 uint32_t
3117 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
3118 {
3119 struct radv_cmd_state *state = &cmd_buffer->state;
3120 uint32_t subpass_id = state->subpass - state->pass->subpasses;
3121
3122 /* The id of this subpass shouldn't exceed the number of subpasses in
3123 * this render pass minus 1.
3124 */
3125 assert(subpass_id < state->pass->subpass_count);
3126 return subpass_id;
3127 }
3128
3129 static struct radv_sample_locations_state *
3130 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3131 uint32_t att_idx,
3132 bool begin_subpass)
3133 {
3134 struct radv_cmd_state *state = &cmd_buffer->state;
3135 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
3136 struct radv_image_view *view = state->attachments[att_idx].iview;
3137
3138 if (view->image->info.samples == 1)
3139 return NULL;
3140
3141 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
3142 /* Return the initial sample locations if this is the initial
3143 * layout transition of the given subpass attachemnt.
3144 */
3145 if (state->attachments[att_idx].sample_location.count > 0)
3146 return &state->attachments[att_idx].sample_location;
3147 } else {
3148 /* Otherwise return the subpass sample locations if defined. */
3149 if (state->subpass_sample_locs) {
3150 /* Because the driver sets the current subpass before
3151 * initial layout transitions, we should use the sample
3152 * locations from the previous subpass to avoid an
3153 * off-by-one problem. Otherwise, use the sample
3154 * locations for the current subpass for final layout
3155 * transitions.
3156 */
3157 if (begin_subpass)
3158 subpass_id--;
3159
3160 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
3161 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
3162 return &state->subpass_sample_locs[i].sample_location;
3163 }
3164 }
3165 }
3166
3167 return NULL;
3168 }
3169
3170 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
3171 struct radv_subpass_attachment att,
3172 bool begin_subpass)
3173 {
3174 unsigned idx = att.attachment;
3175 struct radv_image_view *view = cmd_buffer->state.attachments[idx].iview;
3176 struct radv_sample_locations_state *sample_locs;
3177 VkImageSubresourceRange range;
3178 range.aspectMask = view->aspect_mask;
3179 range.baseMipLevel = view->base_mip;
3180 range.levelCount = 1;
3181 range.baseArrayLayer = view->base_layer;
3182 range.layerCount = cmd_buffer->state.framebuffer->layers;
3183
3184 if (cmd_buffer->state.subpass->view_mask) {
3185 /* If the current subpass uses multiview, the driver might have
3186 * performed a fast color/depth clear to the whole image
3187 * (including all layers). To make sure the driver will
3188 * decompress the image correctly (if needed), we have to
3189 * account for the "real" number of layers. If the view mask is
3190 * sparse, this will decompress more layers than needed.
3191 */
3192 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
3193 }
3194
3195 /* Get the subpass sample locations for the given attachment, if NULL
3196 * is returned the driver will use the default HW locations.
3197 */
3198 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
3199 begin_subpass);
3200
3201 /* Determine if the subpass uses separate depth/stencil layouts. */
3202 bool uses_separate_depth_stencil_layouts = false;
3203 if ((cmd_buffer->state.attachments[idx].current_layout !=
3204 cmd_buffer->state.attachments[idx].current_stencil_layout) ||
3205 (att.layout != att.stencil_layout)) {
3206 uses_separate_depth_stencil_layouts = true;
3207 }
3208
3209 /* For separate layouts, perform depth and stencil transitions
3210 * separately.
3211 */
3212 if (uses_separate_depth_stencil_layouts &&
3213 (range.aspectMask == (VK_IMAGE_ASPECT_DEPTH_BIT |
3214 VK_IMAGE_ASPECT_STENCIL_BIT))) {
3215 /* Depth-only transitions. */
3216 range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3217 radv_handle_image_transition(cmd_buffer,
3218 view->image,
3219 cmd_buffer->state.attachments[idx].current_layout,
3220 cmd_buffer->state.attachments[idx].current_in_render_loop,
3221 att.layout, att.in_render_loop,
3222 0, 0, &range, sample_locs);
3223
3224 /* Stencil-only transitions. */
3225 range.aspectMask = VK_IMAGE_ASPECT_STENCIL_BIT;
3226 radv_handle_image_transition(cmd_buffer,
3227 view->image,
3228 cmd_buffer->state.attachments[idx].current_stencil_layout,
3229 cmd_buffer->state.attachments[idx].current_in_render_loop,
3230 att.stencil_layout, att.in_render_loop,
3231 0, 0, &range, sample_locs);
3232 } else {
3233 radv_handle_image_transition(cmd_buffer,
3234 view->image,
3235 cmd_buffer->state.attachments[idx].current_layout,
3236 cmd_buffer->state.attachments[idx].current_in_render_loop,
3237 att.layout, att.in_render_loop,
3238 0, 0, &range, sample_locs);
3239 }
3240
3241 cmd_buffer->state.attachments[idx].current_layout = att.layout;
3242 cmd_buffer->state.attachments[idx].current_stencil_layout = att.stencil_layout;
3243 cmd_buffer->state.attachments[idx].current_in_render_loop = att.in_render_loop;
3244
3245
3246 }
3247
3248 void
3249 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
3250 const struct radv_subpass *subpass)
3251 {
3252 cmd_buffer->state.subpass = subpass;
3253
3254 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
3255 }
3256
3257 static VkResult
3258 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3259 struct radv_render_pass *pass,
3260 const VkRenderPassBeginInfo *info)
3261 {
3262 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
3263 vk_find_struct_const(info->pNext,
3264 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
3265 struct radv_cmd_state *state = &cmd_buffer->state;
3266
3267 if (!sample_locs) {
3268 state->subpass_sample_locs = NULL;
3269 return VK_SUCCESS;
3270 }
3271
3272 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
3273 const VkAttachmentSampleLocationsEXT *att_sample_locs =
3274 &sample_locs->pAttachmentInitialSampleLocations[i];
3275 uint32_t att_idx = att_sample_locs->attachmentIndex;
3276 struct radv_image *image = cmd_buffer->state.attachments[att_idx].iview->image;
3277
3278 assert(vk_format_is_depth_or_stencil(image->vk_format));
3279
3280 /* From the Vulkan spec 1.1.108:
3281 *
3282 * "If the image referenced by the framebuffer attachment at
3283 * index attachmentIndex was not created with
3284 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
3285 * then the values specified in sampleLocationsInfo are
3286 * ignored."
3287 */
3288 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
3289 continue;
3290
3291 const VkSampleLocationsInfoEXT *sample_locs_info =
3292 &att_sample_locs->sampleLocationsInfo;
3293
3294 state->attachments[att_idx].sample_location.per_pixel =
3295 sample_locs_info->sampleLocationsPerPixel;
3296 state->attachments[att_idx].sample_location.grid_size =
3297 sample_locs_info->sampleLocationGridSize;
3298 state->attachments[att_idx].sample_location.count =
3299 sample_locs_info->sampleLocationsCount;
3300 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
3301 sample_locs_info->pSampleLocations,
3302 sample_locs_info->sampleLocationsCount);
3303 }
3304
3305 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
3306 sample_locs->postSubpassSampleLocationsCount *
3307 sizeof(state->subpass_sample_locs[0]),
3308 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3309 if (state->subpass_sample_locs == NULL) {
3310 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3311 return cmd_buffer->record_result;
3312 }
3313
3314 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
3315
3316 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
3317 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
3318 &sample_locs->pPostSubpassSampleLocations[i];
3319 const VkSampleLocationsInfoEXT *sample_locs_info =
3320 &subpass_sample_locs_info->sampleLocationsInfo;
3321
3322 state->subpass_sample_locs[i].subpass_idx =
3323 subpass_sample_locs_info->subpassIndex;
3324 state->subpass_sample_locs[i].sample_location.per_pixel =
3325 sample_locs_info->sampleLocationsPerPixel;
3326 state->subpass_sample_locs[i].sample_location.grid_size =
3327 sample_locs_info->sampleLocationGridSize;
3328 state->subpass_sample_locs[i].sample_location.count =
3329 sample_locs_info->sampleLocationsCount;
3330 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
3331 sample_locs_info->pSampleLocations,
3332 sample_locs_info->sampleLocationsCount);
3333 }
3334
3335 return VK_SUCCESS;
3336 }
3337
3338 static VkResult
3339 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
3340 struct radv_render_pass *pass,
3341 const VkRenderPassBeginInfo *info)
3342 {
3343 struct radv_cmd_state *state = &cmd_buffer->state;
3344 const struct VkRenderPassAttachmentBeginInfo *attachment_info = NULL;
3345
3346 if (info) {
3347 attachment_info = vk_find_struct_const(info->pNext,
3348 RENDER_PASS_ATTACHMENT_BEGIN_INFO);
3349 }
3350
3351
3352 if (pass->attachment_count == 0) {
3353 state->attachments = NULL;
3354 return VK_SUCCESS;
3355 }
3356
3357 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
3358 pass->attachment_count *
3359 sizeof(state->attachments[0]),
3360 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3361 if (state->attachments == NULL) {
3362 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3363 return cmd_buffer->record_result;
3364 }
3365
3366 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
3367 struct radv_render_pass_attachment *att = &pass->attachments[i];
3368 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
3369 VkImageAspectFlags clear_aspects = 0;
3370
3371 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
3372 /* color attachment */
3373 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3374 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
3375 }
3376 } else {
3377 /* depthstencil attachment */
3378 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
3379 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3380 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
3381 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3382 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
3383 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3384 }
3385 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3386 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3387 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3388 }
3389 }
3390
3391 state->attachments[i].pending_clear_aspects = clear_aspects;
3392 state->attachments[i].cleared_views = 0;
3393 if (clear_aspects && info) {
3394 assert(info->clearValueCount > i);
3395 state->attachments[i].clear_value = info->pClearValues[i];
3396 }
3397
3398 state->attachments[i].current_layout = att->initial_layout;
3399 state->attachments[i].current_stencil_layout = att->stencil_initial_layout;
3400 state->attachments[i].sample_location.count = 0;
3401
3402 struct radv_image_view *iview;
3403 if (attachment_info && attachment_info->attachmentCount > i) {
3404 iview = radv_image_view_from_handle(attachment_info->pAttachments[i]);
3405 } else {
3406 iview = state->framebuffer->attachments[i];
3407 }
3408
3409 state->attachments[i].iview = iview;
3410 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3411 radv_initialise_ds_surface(cmd_buffer->device, &state->attachments[i].ds, iview);
3412 } else {
3413 radv_initialise_color_surface(cmd_buffer->device, &state->attachments[i].cb, iview);
3414 }
3415 }
3416
3417 return VK_SUCCESS;
3418 }
3419
3420 VkResult radv_AllocateCommandBuffers(
3421 VkDevice _device,
3422 const VkCommandBufferAllocateInfo *pAllocateInfo,
3423 VkCommandBuffer *pCommandBuffers)
3424 {
3425 RADV_FROM_HANDLE(radv_device, device, _device);
3426 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
3427
3428 VkResult result = VK_SUCCESS;
3429 uint32_t i;
3430
3431 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
3432
3433 if (!list_is_empty(&pool->free_cmd_buffers)) {
3434 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
3435
3436 list_del(&cmd_buffer->pool_link);
3437 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
3438
3439 result = radv_reset_cmd_buffer(cmd_buffer);
3440 cmd_buffer->level = pAllocateInfo->level;
3441
3442 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
3443 } else {
3444 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
3445 &pCommandBuffers[i]);
3446 }
3447 if (result != VK_SUCCESS)
3448 break;
3449 }
3450
3451 if (result != VK_SUCCESS) {
3452 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
3453 i, pCommandBuffers);
3454
3455 /* From the Vulkan 1.0.66 spec:
3456 *
3457 * "vkAllocateCommandBuffers can be used to create multiple
3458 * command buffers. If the creation of any of those command
3459 * buffers fails, the implementation must destroy all
3460 * successfully created command buffer objects from this
3461 * command, set all entries of the pCommandBuffers array to
3462 * NULL and return the error."
3463 */
3464 memset(pCommandBuffers, 0,
3465 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
3466 }
3467
3468 return result;
3469 }
3470
3471 void radv_FreeCommandBuffers(
3472 VkDevice device,
3473 VkCommandPool commandPool,
3474 uint32_t commandBufferCount,
3475 const VkCommandBuffer *pCommandBuffers)
3476 {
3477 for (uint32_t i = 0; i < commandBufferCount; i++) {
3478 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
3479
3480 if (cmd_buffer) {
3481 if (cmd_buffer->pool) {
3482 list_del(&cmd_buffer->pool_link);
3483 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3484 } else
3485 radv_cmd_buffer_destroy(cmd_buffer);
3486
3487 }
3488 }
3489 }
3490
3491 VkResult radv_ResetCommandBuffer(
3492 VkCommandBuffer commandBuffer,
3493 VkCommandBufferResetFlags flags)
3494 {
3495 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3496 return radv_reset_cmd_buffer(cmd_buffer);
3497 }
3498
3499 VkResult radv_BeginCommandBuffer(
3500 VkCommandBuffer commandBuffer,
3501 const VkCommandBufferBeginInfo *pBeginInfo)
3502 {
3503 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3504 VkResult result = VK_SUCCESS;
3505
3506 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3507 /* If the command buffer has already been resetted with
3508 * vkResetCommandBuffer, no need to do it again.
3509 */
3510 result = radv_reset_cmd_buffer(cmd_buffer);
3511 if (result != VK_SUCCESS)
3512 return result;
3513 }
3514
3515 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3516 cmd_buffer->state.last_primitive_reset_en = -1;
3517 cmd_buffer->state.last_index_type = -1;
3518 cmd_buffer->state.last_num_instances = -1;
3519 cmd_buffer->state.last_vertex_offset = -1;
3520 cmd_buffer->state.last_first_instance = -1;
3521 cmd_buffer->state.predication_type = -1;
3522 cmd_buffer->state.last_sx_ps_downconvert = -1;
3523 cmd_buffer->state.last_sx_blend_opt_epsilon = -1;
3524 cmd_buffer->state.last_sx_blend_opt_control = -1;
3525 cmd_buffer->usage_flags = pBeginInfo->flags;
3526
3527 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3528 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3529 assert(pBeginInfo->pInheritanceInfo);
3530 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3531 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3532
3533 struct radv_subpass *subpass =
3534 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3535
3536 if (cmd_buffer->state.framebuffer) {
3537 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3538 if (result != VK_SUCCESS)
3539 return result;
3540 }
3541
3542 cmd_buffer->state.inherited_pipeline_statistics =
3543 pBeginInfo->pInheritanceInfo->pipelineStatistics;
3544
3545 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3546 }
3547
3548 if (unlikely(cmd_buffer->device->trace_bo))
3549 radv_cmd_buffer_trace_emit(cmd_buffer);
3550
3551 radv_describe_begin_cmd_buffer(cmd_buffer);
3552
3553 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3554
3555 return result;
3556 }
3557
3558 void radv_CmdBindVertexBuffers(
3559 VkCommandBuffer commandBuffer,
3560 uint32_t firstBinding,
3561 uint32_t bindingCount,
3562 const VkBuffer* pBuffers,
3563 const VkDeviceSize* pOffsets)
3564 {
3565 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3566 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3567 bool changed = false;
3568
3569 /* We have to defer setting up vertex buffer since we need the buffer
3570 * stride from the pipeline. */
3571
3572 assert(firstBinding + bindingCount <= MAX_VBS);
3573 for (uint32_t i = 0; i < bindingCount; i++) {
3574 RADV_FROM_HANDLE(radv_buffer, buffer, pBuffers[i]);
3575 uint32_t idx = firstBinding + i;
3576
3577 if (!changed &&
3578 (vb[idx].buffer != buffer ||
3579 vb[idx].offset != pOffsets[i])) {
3580 changed = true;
3581 }
3582
3583 vb[idx].buffer = buffer;
3584 vb[idx].offset = pOffsets[i];
3585
3586 if (buffer) {
3587 radv_cs_add_buffer(cmd_buffer->device->ws,
3588 cmd_buffer->cs, vb[idx].buffer->bo);
3589 }
3590 }
3591
3592 if (!changed) {
3593 /* No state changes. */
3594 return;
3595 }
3596
3597 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3598 }
3599
3600 static uint32_t
3601 vk_to_index_type(VkIndexType type)
3602 {
3603 switch (type) {
3604 case VK_INDEX_TYPE_UINT8_EXT:
3605 return V_028A7C_VGT_INDEX_8;
3606 case VK_INDEX_TYPE_UINT16:
3607 return V_028A7C_VGT_INDEX_16;
3608 case VK_INDEX_TYPE_UINT32:
3609 return V_028A7C_VGT_INDEX_32;
3610 default:
3611 unreachable("invalid index type");
3612 }
3613 }
3614
3615 static uint32_t
3616 radv_get_vgt_index_size(uint32_t type)
3617 {
3618 switch (type) {
3619 case V_028A7C_VGT_INDEX_8:
3620 return 1;
3621 case V_028A7C_VGT_INDEX_16:
3622 return 2;
3623 case V_028A7C_VGT_INDEX_32:
3624 return 4;
3625 default:
3626 unreachable("invalid index type");
3627 }
3628 }
3629
3630 void radv_CmdBindIndexBuffer(
3631 VkCommandBuffer commandBuffer,
3632 VkBuffer buffer,
3633 VkDeviceSize offset,
3634 VkIndexType indexType)
3635 {
3636 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3637 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3638
3639 if (cmd_buffer->state.index_buffer == index_buffer &&
3640 cmd_buffer->state.index_offset == offset &&
3641 cmd_buffer->state.index_type == indexType) {
3642 /* No state changes. */
3643 return;
3644 }
3645
3646 cmd_buffer->state.index_buffer = index_buffer;
3647 cmd_buffer->state.index_offset = offset;
3648 cmd_buffer->state.index_type = vk_to_index_type(indexType);
3649 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3650 cmd_buffer->state.index_va += index_buffer->offset + offset;
3651
3652 int index_size = radv_get_vgt_index_size(vk_to_index_type(indexType));
3653 cmd_buffer->state.max_index_count = (index_buffer->size - offset) / index_size;
3654 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3655 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3656 }
3657
3658
3659 static void
3660 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3661 VkPipelineBindPoint bind_point,
3662 struct radv_descriptor_set *set, unsigned idx)
3663 {
3664 struct radeon_winsys *ws = cmd_buffer->device->ws;
3665
3666 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3667
3668 assert(set);
3669 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3670
3671 if (!cmd_buffer->device->use_global_bo_list) {
3672 for (unsigned j = 0; j < set->buffer_count; ++j)
3673 if (set->descriptors[j])
3674 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3675 }
3676
3677 if(set->bo)
3678 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3679 }
3680
3681 void radv_CmdBindDescriptorSets(
3682 VkCommandBuffer commandBuffer,
3683 VkPipelineBindPoint pipelineBindPoint,
3684 VkPipelineLayout _layout,
3685 uint32_t firstSet,
3686 uint32_t descriptorSetCount,
3687 const VkDescriptorSet* pDescriptorSets,
3688 uint32_t dynamicOffsetCount,
3689 const uint32_t* pDynamicOffsets)
3690 {
3691 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3692 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3693 unsigned dyn_idx = 0;
3694
3695 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3696 struct radv_descriptor_state *descriptors_state =
3697 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3698
3699 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3700 unsigned idx = i + firstSet;
3701 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3702
3703 /* If the set is already bound we only need to update the
3704 * (potentially changed) dynamic offsets. */
3705 if (descriptors_state->sets[idx] != set ||
3706 !(descriptors_state->valid & (1u << idx))) {
3707 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3708 }
3709
3710 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3711 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3712 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3713 assert(dyn_idx < dynamicOffsetCount);
3714
3715 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3716 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3717 dst[0] = va;
3718 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3719 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3720 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3721 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3722 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3723 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3724
3725 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
3726 dst[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3727 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3728 S_008F0C_RESOURCE_LEVEL(1);
3729 } else {
3730 dst[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3731 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3732 }
3733
3734 cmd_buffer->push_constant_stages |=
3735 set->layout->dynamic_shader_stages;
3736 }
3737 }
3738 }
3739
3740 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3741 struct radv_descriptor_set *set,
3742 struct radv_descriptor_set_layout *layout,
3743 VkPipelineBindPoint bind_point)
3744 {
3745 struct radv_descriptor_state *descriptors_state =
3746 radv_get_descriptors_state(cmd_buffer, bind_point);
3747 set->size = layout->size;
3748 set->layout = layout;
3749
3750 if (descriptors_state->push_set.capacity < set->size) {
3751 size_t new_size = MAX2(set->size, 1024);
3752 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3753 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3754
3755 free(set->mapped_ptr);
3756 set->mapped_ptr = malloc(new_size);
3757
3758 if (!set->mapped_ptr) {
3759 descriptors_state->push_set.capacity = 0;
3760 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3761 return false;
3762 }
3763
3764 descriptors_state->push_set.capacity = new_size;
3765 }
3766
3767 return true;
3768 }
3769
3770 void radv_meta_push_descriptor_set(
3771 struct radv_cmd_buffer* cmd_buffer,
3772 VkPipelineBindPoint pipelineBindPoint,
3773 VkPipelineLayout _layout,
3774 uint32_t set,
3775 uint32_t descriptorWriteCount,
3776 const VkWriteDescriptorSet* pDescriptorWrites)
3777 {
3778 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3779 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3780 unsigned bo_offset;
3781
3782 assert(set == 0);
3783 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3784
3785 push_set->size = layout->set[set].layout->size;
3786 push_set->layout = layout->set[set].layout;
3787
3788 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3789 &bo_offset,
3790 (void**) &push_set->mapped_ptr))
3791 return;
3792
3793 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3794 push_set->va += bo_offset;
3795
3796 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3797 radv_descriptor_set_to_handle(push_set),
3798 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3799
3800 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3801 }
3802
3803 void radv_CmdPushDescriptorSetKHR(
3804 VkCommandBuffer commandBuffer,
3805 VkPipelineBindPoint pipelineBindPoint,
3806 VkPipelineLayout _layout,
3807 uint32_t set,
3808 uint32_t descriptorWriteCount,
3809 const VkWriteDescriptorSet* pDescriptorWrites)
3810 {
3811 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3812 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3813 struct radv_descriptor_state *descriptors_state =
3814 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3815 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3816
3817 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3818
3819 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3820 layout->set[set].layout,
3821 pipelineBindPoint))
3822 return;
3823
3824 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3825 * because it is invalid, according to Vulkan spec.
3826 */
3827 for (int i = 0; i < descriptorWriteCount; i++) {
3828 ASSERTED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
3829 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
3830 }
3831
3832 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3833 radv_descriptor_set_to_handle(push_set),
3834 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3835
3836 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3837 descriptors_state->push_dirty = true;
3838 }
3839
3840 void radv_CmdPushDescriptorSetWithTemplateKHR(
3841 VkCommandBuffer commandBuffer,
3842 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
3843 VkPipelineLayout _layout,
3844 uint32_t set,
3845 const void* pData)
3846 {
3847 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3848 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3849 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
3850 struct radv_descriptor_state *descriptors_state =
3851 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
3852 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3853
3854 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3855
3856 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3857 layout->set[set].layout,
3858 templ->bind_point))
3859 return;
3860
3861 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
3862 descriptorUpdateTemplate, pData);
3863
3864 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
3865 descriptors_state->push_dirty = true;
3866 }
3867
3868 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
3869 VkPipelineLayout layout,
3870 VkShaderStageFlags stageFlags,
3871 uint32_t offset,
3872 uint32_t size,
3873 const void* pValues)
3874 {
3875 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3876 memcpy(cmd_buffer->push_constants + offset, pValues, size);
3877 cmd_buffer->push_constant_stages |= stageFlags;
3878 }
3879
3880 VkResult radv_EndCommandBuffer(
3881 VkCommandBuffer commandBuffer)
3882 {
3883 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3884
3885 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
3886 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
3887 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
3888
3889 /* Make sure to sync all pending active queries at the end of
3890 * command buffer.
3891 */
3892 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
3893
3894 /* Since NGG streamout uses GDS, we need to make GDS idle when
3895 * we leave the IB, otherwise another process might overwrite
3896 * it while our shaders are busy.
3897 */
3898 if (cmd_buffer->gds_needed)
3899 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
3900
3901 si_emit_cache_flush(cmd_buffer);
3902 }
3903
3904 /* Make sure CP DMA is idle at the end of IBs because the kernel
3905 * doesn't wait for it.
3906 */
3907 si_cp_dma_wait_for_idle(cmd_buffer);
3908
3909 radv_describe_end_cmd_buffer(cmd_buffer);
3910
3911 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3912 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
3913
3914 VkResult result = cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs);
3915 if (result != VK_SUCCESS)
3916 return vk_error(cmd_buffer->device->instance, result);
3917
3918 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
3919
3920 return cmd_buffer->record_result;
3921 }
3922
3923 static void
3924 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
3925 {
3926 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3927
3928 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
3929 return;
3930
3931 assert(!pipeline->ctx_cs.cdw);
3932
3933 cmd_buffer->state.emitted_compute_pipeline = pipeline;
3934
3935 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
3936 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
3937
3938 cmd_buffer->compute_scratch_size_per_wave_needed = MAX2(cmd_buffer->compute_scratch_size_per_wave_needed,
3939 pipeline->scratch_bytes_per_wave);
3940 cmd_buffer->compute_scratch_waves_wanted = MAX2(cmd_buffer->compute_scratch_waves_wanted,
3941 pipeline->max_waves);
3942
3943 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3944 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
3945
3946 if (unlikely(cmd_buffer->device->trace_bo))
3947 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
3948 }
3949
3950 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
3951 VkPipelineBindPoint bind_point)
3952 {
3953 struct radv_descriptor_state *descriptors_state =
3954 radv_get_descriptors_state(cmd_buffer, bind_point);
3955
3956 descriptors_state->dirty |= descriptors_state->valid;
3957 }
3958
3959 void radv_CmdBindPipeline(
3960 VkCommandBuffer commandBuffer,
3961 VkPipelineBindPoint pipelineBindPoint,
3962 VkPipeline _pipeline)
3963 {
3964 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3965 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3966
3967 switch (pipelineBindPoint) {
3968 case VK_PIPELINE_BIND_POINT_COMPUTE:
3969 if (cmd_buffer->state.compute_pipeline == pipeline)
3970 return;
3971 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3972
3973 cmd_buffer->state.compute_pipeline = pipeline;
3974 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3975 break;
3976 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3977 if (cmd_buffer->state.pipeline == pipeline)
3978 return;
3979 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3980
3981 cmd_buffer->state.pipeline = pipeline;
3982 if (!pipeline)
3983 break;
3984
3985 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3986 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3987
3988 /* the new vertex shader might not have the same user regs */
3989 cmd_buffer->state.last_first_instance = -1;
3990 cmd_buffer->state.last_vertex_offset = -1;
3991
3992 /* Prefetch all pipeline shaders at first draw time. */
3993 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3994
3995 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX10 &&
3996 cmd_buffer->state.emitted_pipeline &&
3997 radv_pipeline_has_ngg(cmd_buffer->state.emitted_pipeline) &&
3998 !radv_pipeline_has_ngg(cmd_buffer->state.pipeline)) {
3999 /* Transitioning from NGG to legacy GS requires
4000 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
4001 * at the beginning of IBs when legacy GS ring pointers
4002 * are set.
4003 */
4004 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
4005 }
4006
4007 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
4008 radv_bind_streamout_state(cmd_buffer, pipeline);
4009
4010 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
4011 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
4012 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
4013 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
4014
4015 if (radv_pipeline_has_tess(pipeline))
4016 cmd_buffer->tess_rings_needed = true;
4017 break;
4018 default:
4019 assert(!"invalid bind point");
4020 break;
4021 }
4022 }
4023
4024 void radv_CmdSetViewport(
4025 VkCommandBuffer commandBuffer,
4026 uint32_t firstViewport,
4027 uint32_t viewportCount,
4028 const VkViewport* pViewports)
4029 {
4030 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4031 struct radv_cmd_state *state = &cmd_buffer->state;
4032 ASSERTED const uint32_t total_count = firstViewport + viewportCount;
4033
4034 assert(firstViewport < MAX_VIEWPORTS);
4035 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
4036
4037 if (total_count <= state->dynamic.viewport.count &&
4038 !memcmp(state->dynamic.viewport.viewports + firstViewport,
4039 pViewports, viewportCount * sizeof(*pViewports))) {
4040 return;
4041 }
4042
4043 if (state->dynamic.viewport.count < total_count)
4044 state->dynamic.viewport.count = total_count;
4045
4046 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
4047 viewportCount * sizeof(*pViewports));
4048
4049 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
4050 }
4051
4052 void radv_CmdSetScissor(
4053 VkCommandBuffer commandBuffer,
4054 uint32_t firstScissor,
4055 uint32_t scissorCount,
4056 const VkRect2D* pScissors)
4057 {
4058 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4059 struct radv_cmd_state *state = &cmd_buffer->state;
4060 ASSERTED const uint32_t total_count = firstScissor + scissorCount;
4061
4062 assert(firstScissor < MAX_SCISSORS);
4063 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
4064
4065 if (total_count <= state->dynamic.scissor.count &&
4066 !memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
4067 scissorCount * sizeof(*pScissors))) {
4068 return;
4069 }
4070
4071 if (state->dynamic.scissor.count < total_count)
4072 state->dynamic.scissor.count = total_count;
4073
4074 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
4075 scissorCount * sizeof(*pScissors));
4076
4077 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
4078 }
4079
4080 void radv_CmdSetLineWidth(
4081 VkCommandBuffer commandBuffer,
4082 float lineWidth)
4083 {
4084 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4085
4086 if (cmd_buffer->state.dynamic.line_width == lineWidth)
4087 return;
4088
4089 cmd_buffer->state.dynamic.line_width = lineWidth;
4090 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
4091 }
4092
4093 void radv_CmdSetDepthBias(
4094 VkCommandBuffer commandBuffer,
4095 float depthBiasConstantFactor,
4096 float depthBiasClamp,
4097 float depthBiasSlopeFactor)
4098 {
4099 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4100 struct radv_cmd_state *state = &cmd_buffer->state;
4101
4102 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
4103 state->dynamic.depth_bias.clamp == depthBiasClamp &&
4104 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
4105 return;
4106 }
4107
4108 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
4109 state->dynamic.depth_bias.clamp = depthBiasClamp;
4110 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
4111
4112 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
4113 }
4114
4115 void radv_CmdSetBlendConstants(
4116 VkCommandBuffer commandBuffer,
4117 const float blendConstants[4])
4118 {
4119 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4120 struct radv_cmd_state *state = &cmd_buffer->state;
4121
4122 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
4123 return;
4124
4125 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
4126
4127 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
4128 }
4129
4130 void radv_CmdSetDepthBounds(
4131 VkCommandBuffer commandBuffer,
4132 float minDepthBounds,
4133 float maxDepthBounds)
4134 {
4135 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4136 struct radv_cmd_state *state = &cmd_buffer->state;
4137
4138 if (state->dynamic.depth_bounds.min == minDepthBounds &&
4139 state->dynamic.depth_bounds.max == maxDepthBounds) {
4140 return;
4141 }
4142
4143 state->dynamic.depth_bounds.min = minDepthBounds;
4144 state->dynamic.depth_bounds.max = maxDepthBounds;
4145
4146 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
4147 }
4148
4149 void radv_CmdSetStencilCompareMask(
4150 VkCommandBuffer commandBuffer,
4151 VkStencilFaceFlags faceMask,
4152 uint32_t compareMask)
4153 {
4154 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4155 struct radv_cmd_state *state = &cmd_buffer->state;
4156 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
4157 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
4158
4159 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4160 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4161 return;
4162 }
4163
4164 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4165 state->dynamic.stencil_compare_mask.front = compareMask;
4166 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4167 state->dynamic.stencil_compare_mask.back = compareMask;
4168
4169 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
4170 }
4171
4172 void radv_CmdSetStencilWriteMask(
4173 VkCommandBuffer commandBuffer,
4174 VkStencilFaceFlags faceMask,
4175 uint32_t writeMask)
4176 {
4177 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4178 struct radv_cmd_state *state = &cmd_buffer->state;
4179 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
4180 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
4181
4182 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4183 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4184 return;
4185 }
4186
4187 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4188 state->dynamic.stencil_write_mask.front = writeMask;
4189 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4190 state->dynamic.stencil_write_mask.back = writeMask;
4191
4192 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
4193 }
4194
4195 void radv_CmdSetStencilReference(
4196 VkCommandBuffer commandBuffer,
4197 VkStencilFaceFlags faceMask,
4198 uint32_t reference)
4199 {
4200 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4201 struct radv_cmd_state *state = &cmd_buffer->state;
4202 bool front_same = state->dynamic.stencil_reference.front == reference;
4203 bool back_same = state->dynamic.stencil_reference.back == reference;
4204
4205 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4206 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4207 return;
4208 }
4209
4210 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4211 cmd_buffer->state.dynamic.stencil_reference.front = reference;
4212 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4213 cmd_buffer->state.dynamic.stencil_reference.back = reference;
4214
4215 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
4216 }
4217
4218 void radv_CmdSetDiscardRectangleEXT(
4219 VkCommandBuffer commandBuffer,
4220 uint32_t firstDiscardRectangle,
4221 uint32_t discardRectangleCount,
4222 const VkRect2D* pDiscardRectangles)
4223 {
4224 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4225 struct radv_cmd_state *state = &cmd_buffer->state;
4226 ASSERTED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
4227
4228 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
4229 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
4230
4231 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
4232 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
4233 return;
4234 }
4235
4236 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
4237 pDiscardRectangles, discardRectangleCount);
4238
4239 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
4240 }
4241
4242 void radv_CmdSetSampleLocationsEXT(
4243 VkCommandBuffer commandBuffer,
4244 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
4245 {
4246 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4247 struct radv_cmd_state *state = &cmd_buffer->state;
4248
4249 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
4250
4251 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
4252 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
4253 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
4254 typed_memcpy(&state->dynamic.sample_location.locations[0],
4255 pSampleLocationsInfo->pSampleLocations,
4256 pSampleLocationsInfo->sampleLocationsCount);
4257
4258 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
4259 }
4260
4261 void radv_CmdSetLineStippleEXT(
4262 VkCommandBuffer commandBuffer,
4263 uint32_t lineStippleFactor,
4264 uint16_t lineStipplePattern)
4265 {
4266 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4267 struct radv_cmd_state *state = &cmd_buffer->state;
4268
4269 state->dynamic.line_stipple.factor = lineStippleFactor;
4270 state->dynamic.line_stipple.pattern = lineStipplePattern;
4271
4272 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE;
4273 }
4274
4275 void radv_CmdSetCullModeEXT(
4276 VkCommandBuffer commandBuffer,
4277 VkCullModeFlags cullMode)
4278 {
4279 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4280 struct radv_cmd_state *state = &cmd_buffer->state;
4281
4282 if (state->dynamic.cull_mode == cullMode)
4283 return;
4284
4285 state->dynamic.cull_mode = cullMode;
4286
4287 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_CULL_MODE;
4288 }
4289
4290 void radv_CmdSetFrontFaceEXT(
4291 VkCommandBuffer commandBuffer,
4292 VkFrontFace frontFace)
4293 {
4294 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4295 struct radv_cmd_state *state = &cmd_buffer->state;
4296
4297 if (state->dynamic.front_face == frontFace)
4298 return;
4299
4300 state->dynamic.front_face = frontFace;
4301
4302 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE;
4303 }
4304
4305 void radv_CmdSetPrimitiveTopologyEXT(
4306 VkCommandBuffer commandBuffer,
4307 VkPrimitiveTopology primitiveTopology)
4308 {
4309 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4310 struct radv_cmd_state *state = &cmd_buffer->state;
4311 unsigned primitive_topology = si_translate_prim(primitiveTopology);
4312
4313 if (state->dynamic.primitive_topology == primitive_topology)
4314 return;
4315
4316 state->dynamic.primitive_topology = primitive_topology;
4317
4318 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY;
4319 }
4320
4321 void radv_CmdExecuteCommands(
4322 VkCommandBuffer commandBuffer,
4323 uint32_t commandBufferCount,
4324 const VkCommandBuffer* pCmdBuffers)
4325 {
4326 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
4327
4328 assert(commandBufferCount > 0);
4329
4330 /* Emit pending flushes on primary prior to executing secondary */
4331 si_emit_cache_flush(primary);
4332
4333 for (uint32_t i = 0; i < commandBufferCount; i++) {
4334 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
4335
4336 primary->scratch_size_per_wave_needed = MAX2(primary->scratch_size_per_wave_needed,
4337 secondary->scratch_size_per_wave_needed);
4338 primary->scratch_waves_wanted = MAX2(primary->scratch_waves_wanted,
4339 secondary->scratch_waves_wanted);
4340 primary->compute_scratch_size_per_wave_needed = MAX2(primary->compute_scratch_size_per_wave_needed,
4341 secondary->compute_scratch_size_per_wave_needed);
4342 primary->compute_scratch_waves_wanted = MAX2(primary->compute_scratch_waves_wanted,
4343 secondary->compute_scratch_waves_wanted);
4344
4345 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
4346 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
4347 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
4348 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
4349 if (secondary->tess_rings_needed)
4350 primary->tess_rings_needed = true;
4351 if (secondary->sample_positions_needed)
4352 primary->sample_positions_needed = true;
4353 if (secondary->gds_needed)
4354 primary->gds_needed = true;
4355
4356 if (!secondary->state.framebuffer &&
4357 (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
4358 /* Emit the framebuffer state from primary if secondary
4359 * has been recorded without a framebuffer, otherwise
4360 * fast color/depth clears can't work.
4361 */
4362 radv_emit_framebuffer_state(primary);
4363 }
4364
4365 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
4366
4367
4368 /* When the secondary command buffer is compute only we don't
4369 * need to re-emit the current graphics pipeline.
4370 */
4371 if (secondary->state.emitted_pipeline) {
4372 primary->state.emitted_pipeline =
4373 secondary->state.emitted_pipeline;
4374 }
4375
4376 /* When the secondary command buffer is graphics only we don't
4377 * need to re-emit the current compute pipeline.
4378 */
4379 if (secondary->state.emitted_compute_pipeline) {
4380 primary->state.emitted_compute_pipeline =
4381 secondary->state.emitted_compute_pipeline;
4382 }
4383
4384 /* Only re-emit the draw packets when needed. */
4385 if (secondary->state.last_primitive_reset_en != -1) {
4386 primary->state.last_primitive_reset_en =
4387 secondary->state.last_primitive_reset_en;
4388 }
4389
4390 if (secondary->state.last_primitive_reset_index) {
4391 primary->state.last_primitive_reset_index =
4392 secondary->state.last_primitive_reset_index;
4393 }
4394
4395 if (secondary->state.last_ia_multi_vgt_param) {
4396 primary->state.last_ia_multi_vgt_param =
4397 secondary->state.last_ia_multi_vgt_param;
4398 }
4399
4400 primary->state.last_first_instance = secondary->state.last_first_instance;
4401 primary->state.last_num_instances = secondary->state.last_num_instances;
4402 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
4403 primary->state.last_sx_ps_downconvert = secondary->state.last_sx_ps_downconvert;
4404 primary->state.last_sx_blend_opt_epsilon = secondary->state.last_sx_blend_opt_epsilon;
4405 primary->state.last_sx_blend_opt_control = secondary->state.last_sx_blend_opt_control;
4406
4407 if (secondary->state.last_index_type != -1) {
4408 primary->state.last_index_type =
4409 secondary->state.last_index_type;
4410 }
4411 }
4412
4413 /* After executing commands from secondary buffers we have to dirty
4414 * some states.
4415 */
4416 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
4417 RADV_CMD_DIRTY_INDEX_BUFFER |
4418 RADV_CMD_DIRTY_DYNAMIC_ALL;
4419 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
4420 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
4421 }
4422
4423 VkResult radv_CreateCommandPool(
4424 VkDevice _device,
4425 const VkCommandPoolCreateInfo* pCreateInfo,
4426 const VkAllocationCallbacks* pAllocator,
4427 VkCommandPool* pCmdPool)
4428 {
4429 RADV_FROM_HANDLE(radv_device, device, _device);
4430 struct radv_cmd_pool *pool;
4431
4432 pool = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*pool), 8,
4433 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4434 if (pool == NULL)
4435 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4436
4437 vk_object_base_init(&device->vk, &pool->base,
4438 VK_OBJECT_TYPE_COMMAND_POOL);
4439
4440 if (pAllocator)
4441 pool->alloc = *pAllocator;
4442 else
4443 pool->alloc = device->vk.alloc;
4444
4445 list_inithead(&pool->cmd_buffers);
4446 list_inithead(&pool->free_cmd_buffers);
4447
4448 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
4449
4450 *pCmdPool = radv_cmd_pool_to_handle(pool);
4451
4452 return VK_SUCCESS;
4453
4454 }
4455
4456 void radv_DestroyCommandPool(
4457 VkDevice _device,
4458 VkCommandPool commandPool,
4459 const VkAllocationCallbacks* pAllocator)
4460 {
4461 RADV_FROM_HANDLE(radv_device, device, _device);
4462 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4463
4464 if (!pool)
4465 return;
4466
4467 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4468 &pool->cmd_buffers, pool_link) {
4469 radv_cmd_buffer_destroy(cmd_buffer);
4470 }
4471
4472 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4473 &pool->free_cmd_buffers, pool_link) {
4474 radv_cmd_buffer_destroy(cmd_buffer);
4475 }
4476
4477 vk_object_base_finish(&pool->base);
4478 vk_free2(&device->vk.alloc, pAllocator, pool);
4479 }
4480
4481 VkResult radv_ResetCommandPool(
4482 VkDevice device,
4483 VkCommandPool commandPool,
4484 VkCommandPoolResetFlags flags)
4485 {
4486 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4487 VkResult result;
4488
4489 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
4490 &pool->cmd_buffers, pool_link) {
4491 result = radv_reset_cmd_buffer(cmd_buffer);
4492 if (result != VK_SUCCESS)
4493 return result;
4494 }
4495
4496 return VK_SUCCESS;
4497 }
4498
4499 void radv_TrimCommandPool(
4500 VkDevice device,
4501 VkCommandPool commandPool,
4502 VkCommandPoolTrimFlags flags)
4503 {
4504 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4505
4506 if (!pool)
4507 return;
4508
4509 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4510 &pool->free_cmd_buffers, pool_link) {
4511 radv_cmd_buffer_destroy(cmd_buffer);
4512 }
4513 }
4514
4515 static void
4516 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
4517 uint32_t subpass_id)
4518 {
4519 struct radv_cmd_state *state = &cmd_buffer->state;
4520 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
4521
4522 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
4523 cmd_buffer->cs, 4096);
4524
4525 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
4526
4527 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
4528
4529 radv_describe_barrier_start(cmd_buffer, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC);
4530
4531 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4532 const uint32_t a = subpass->attachments[i].attachment;
4533 if (a == VK_ATTACHMENT_UNUSED)
4534 continue;
4535
4536 radv_handle_subpass_image_transition(cmd_buffer,
4537 subpass->attachments[i],
4538 true);
4539 }
4540
4541 radv_describe_barrier_end(cmd_buffer);
4542
4543 radv_cmd_buffer_clear_subpass(cmd_buffer);
4544
4545 assert(cmd_buffer->cs->cdw <= cdw_max);
4546 }
4547
4548 static void
4549 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
4550 {
4551 struct radv_cmd_state *state = &cmd_buffer->state;
4552 const struct radv_subpass *subpass = state->subpass;
4553 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
4554
4555 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4556
4557 radv_describe_barrier_start(cmd_buffer, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC);
4558
4559 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4560 const uint32_t a = subpass->attachments[i].attachment;
4561 if (a == VK_ATTACHMENT_UNUSED)
4562 continue;
4563
4564 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
4565 continue;
4566
4567 VkImageLayout layout = state->pass->attachments[a].final_layout;
4568 VkImageLayout stencil_layout = state->pass->attachments[a].stencil_final_layout;
4569 struct radv_subpass_attachment att = { a, layout, stencil_layout };
4570 radv_handle_subpass_image_transition(cmd_buffer, att, false);
4571 }
4572
4573 radv_describe_barrier_end(cmd_buffer);
4574 }
4575
4576 void
4577 radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer *cmd_buffer,
4578 const VkRenderPassBeginInfo *pRenderPassBegin)
4579 {
4580 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
4581 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
4582 VkResult result;
4583
4584 cmd_buffer->state.framebuffer = framebuffer;
4585 cmd_buffer->state.pass = pass;
4586 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
4587
4588 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
4589 if (result != VK_SUCCESS)
4590 return;
4591
4592 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
4593 if (result != VK_SUCCESS)
4594 return;
4595 }
4596
4597 void radv_CmdBeginRenderPass(
4598 VkCommandBuffer commandBuffer,
4599 const VkRenderPassBeginInfo* pRenderPassBegin,
4600 VkSubpassContents contents)
4601 {
4602 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4603
4604 radv_cmd_buffer_begin_render_pass(cmd_buffer, pRenderPassBegin);
4605
4606 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
4607 }
4608
4609 void radv_CmdBeginRenderPass2(
4610 VkCommandBuffer commandBuffer,
4611 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
4612 const VkSubpassBeginInfo* pSubpassBeginInfo)
4613 {
4614 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
4615 pSubpassBeginInfo->contents);
4616 }
4617
4618 void radv_CmdNextSubpass(
4619 VkCommandBuffer commandBuffer,
4620 VkSubpassContents contents)
4621 {
4622 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4623
4624 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
4625 radv_cmd_buffer_end_subpass(cmd_buffer);
4626 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
4627 }
4628
4629 void radv_CmdNextSubpass2(
4630 VkCommandBuffer commandBuffer,
4631 const VkSubpassBeginInfo* pSubpassBeginInfo,
4632 const VkSubpassEndInfo* pSubpassEndInfo)
4633 {
4634 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
4635 }
4636
4637 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
4638 {
4639 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
4640 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
4641 if (!radv_get_shader(pipeline, stage))
4642 continue;
4643
4644 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
4645 if (loc->sgpr_idx == -1)
4646 continue;
4647 uint32_t base_reg = pipeline->user_data_0[stage];
4648 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4649
4650 }
4651 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
4652 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
4653 if (loc->sgpr_idx != -1) {
4654 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
4655 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4656 }
4657 }
4658 }
4659
4660 static void
4661 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4662 uint32_t vertex_count,
4663 bool use_opaque)
4664 {
4665 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
4666 radeon_emit(cmd_buffer->cs, vertex_count);
4667 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
4668 S_0287F0_USE_OPAQUE(use_opaque));
4669 }
4670
4671 static void
4672 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
4673 uint64_t index_va,
4674 uint32_t index_count)
4675 {
4676 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
4677 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
4678 radeon_emit(cmd_buffer->cs, index_va);
4679 radeon_emit(cmd_buffer->cs, index_va >> 32);
4680 radeon_emit(cmd_buffer->cs, index_count);
4681 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
4682 }
4683
4684 static void
4685 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4686 bool indexed,
4687 uint32_t draw_count,
4688 uint64_t count_va,
4689 uint32_t stride)
4690 {
4691 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4692 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
4693 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
4694 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id;
4695 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
4696 bool predicating = cmd_buffer->state.predicating;
4697 assert(base_reg);
4698
4699 /* just reset draw state for vertex data */
4700 cmd_buffer->state.last_first_instance = -1;
4701 cmd_buffer->state.last_num_instances = -1;
4702 cmd_buffer->state.last_vertex_offset = -1;
4703
4704 if (draw_count == 1 && !count_va && !draw_id_enable) {
4705 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
4706 PKT3_DRAW_INDIRECT, 3, predicating));
4707 radeon_emit(cs, 0);
4708 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4709 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4710 radeon_emit(cs, di_src_sel);
4711 } else {
4712 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
4713 PKT3_DRAW_INDIRECT_MULTI,
4714 8, predicating));
4715 radeon_emit(cs, 0);
4716 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4717 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4718 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
4719 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
4720 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
4721 radeon_emit(cs, draw_count); /* count */
4722 radeon_emit(cs, count_va); /* count_addr */
4723 radeon_emit(cs, count_va >> 32);
4724 radeon_emit(cs, stride); /* stride */
4725 radeon_emit(cs, di_src_sel);
4726 }
4727 }
4728
4729 static void
4730 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
4731 const struct radv_draw_info *info)
4732 {
4733 struct radv_cmd_state *state = &cmd_buffer->state;
4734 struct radeon_winsys *ws = cmd_buffer->device->ws;
4735 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4736
4737 if (info->indirect) {
4738 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4739 uint64_t count_va = 0;
4740
4741 va += info->indirect->offset + info->indirect_offset;
4742
4743 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4744
4745 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
4746 radeon_emit(cs, 1);
4747 radeon_emit(cs, va);
4748 radeon_emit(cs, va >> 32);
4749
4750 if (info->count_buffer) {
4751 count_va = radv_buffer_get_va(info->count_buffer->bo);
4752 count_va += info->count_buffer->offset +
4753 info->count_buffer_offset;
4754
4755 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
4756 }
4757
4758 if (!state->subpass->view_mask) {
4759 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4760 info->indexed,
4761 info->count,
4762 count_va,
4763 info->stride);
4764 } else {
4765 unsigned i;
4766 for_each_bit(i, state->subpass->view_mask) {
4767 radv_emit_view_index(cmd_buffer, i);
4768
4769 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4770 info->indexed,
4771 info->count,
4772 count_va,
4773 info->stride);
4774 }
4775 }
4776 } else {
4777 assert(state->pipeline->graphics.vtx_base_sgpr);
4778
4779 if (info->vertex_offset != state->last_vertex_offset ||
4780 info->first_instance != state->last_first_instance) {
4781 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
4782 state->pipeline->graphics.vtx_emit_num);
4783
4784 radeon_emit(cs, info->vertex_offset);
4785 radeon_emit(cs, info->first_instance);
4786 if (state->pipeline->graphics.vtx_emit_num == 3)
4787 radeon_emit(cs, 0);
4788 state->last_first_instance = info->first_instance;
4789 state->last_vertex_offset = info->vertex_offset;
4790 }
4791
4792 if (state->last_num_instances != info->instance_count) {
4793 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
4794 radeon_emit(cs, info->instance_count);
4795 state->last_num_instances = info->instance_count;
4796 }
4797
4798 if (info->indexed) {
4799 int index_size = radv_get_vgt_index_size(state->index_type);
4800 uint64_t index_va;
4801
4802 /* Skip draw calls with 0-sized index buffers. They
4803 * cause a hang on some chips, like Navi10-14.
4804 */
4805 if (!cmd_buffer->state.max_index_count)
4806 return;
4807
4808 index_va = state->index_va;
4809 index_va += info->first_index * index_size;
4810
4811 if (!state->subpass->view_mask) {
4812 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4813 index_va,
4814 info->count);
4815 } else {
4816 unsigned i;
4817 for_each_bit(i, state->subpass->view_mask) {
4818 radv_emit_view_index(cmd_buffer, i);
4819
4820 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4821 index_va,
4822 info->count);
4823 }
4824 }
4825 } else {
4826 if (!state->subpass->view_mask) {
4827 radv_cs_emit_draw_packet(cmd_buffer,
4828 info->count,
4829 !!info->strmout_buffer);
4830 } else {
4831 unsigned i;
4832 for_each_bit(i, state->subpass->view_mask) {
4833 radv_emit_view_index(cmd_buffer, i);
4834
4835 radv_cs_emit_draw_packet(cmd_buffer,
4836 info->count,
4837 !!info->strmout_buffer);
4838 }
4839 }
4840 }
4841 }
4842 }
4843
4844 /*
4845 * Vega and raven have a bug which triggers if there are multiple context
4846 * register contexts active at the same time with different scissor values.
4847 *
4848 * There are two possible workarounds:
4849 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4850 * there is only ever 1 active set of scissor values at the same time.
4851 *
4852 * 2) Whenever the hardware switches contexts we have to set the scissor
4853 * registers again even if it is a noop. That way the new context gets
4854 * the correct scissor values.
4855 *
4856 * This implements option 2. radv_need_late_scissor_emission needs to
4857 * return true on affected HW if radv_emit_all_graphics_states sets
4858 * any context registers.
4859 */
4860 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
4861 const struct radv_draw_info *info)
4862 {
4863 struct radv_cmd_state *state = &cmd_buffer->state;
4864
4865 if (!cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
4866 return false;
4867
4868 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
4869 return true;
4870
4871 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
4872
4873 /* Index, vertex and streamout buffers don't change context regs, and
4874 * pipeline is already handled.
4875 */
4876 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
4877 RADV_CMD_DIRTY_VERTEX_BUFFER |
4878 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
4879 RADV_CMD_DIRTY_PIPELINE);
4880
4881 if (cmd_buffer->state.dirty & used_states)
4882 return true;
4883
4884 uint32_t primitive_reset_index =
4885 radv_get_primitive_reset_index(cmd_buffer);
4886
4887 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
4888 primitive_reset_index != state->last_primitive_reset_index)
4889 return true;
4890
4891 return false;
4892 }
4893
4894 static void
4895 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
4896 const struct radv_draw_info *info)
4897 {
4898 bool late_scissor_emission;
4899
4900 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
4901 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
4902 radv_emit_rbplus_state(cmd_buffer);
4903
4904 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
4905 radv_emit_graphics_pipeline(cmd_buffer);
4906
4907 /* This should be before the cmd_buffer->state.dirty is cleared
4908 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4909 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4910 late_scissor_emission =
4911 radv_need_late_scissor_emission(cmd_buffer, info);
4912
4913 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
4914 radv_emit_framebuffer_state(cmd_buffer);
4915
4916 if (info->indexed) {
4917 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
4918 radv_emit_index_buffer(cmd_buffer, info->indirect);
4919 } else {
4920 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4921 * so the state must be re-emitted before the next indexed
4922 * draw.
4923 */
4924 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
4925 cmd_buffer->state.last_index_type = -1;
4926 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
4927 }
4928 }
4929
4930 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
4931
4932 radv_emit_draw_registers(cmd_buffer, info);
4933
4934 if (late_scissor_emission)
4935 radv_emit_scissor(cmd_buffer);
4936 }
4937
4938 static void
4939 radv_draw(struct radv_cmd_buffer *cmd_buffer,
4940 const struct radv_draw_info *info)
4941 {
4942 struct radeon_info *rad_info =
4943 &cmd_buffer->device->physical_device->rad_info;
4944 bool has_prefetch =
4945 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4946 bool pipeline_is_dirty =
4947 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
4948 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
4949
4950 ASSERTED unsigned cdw_max =
4951 radeon_check_space(cmd_buffer->device->ws,
4952 cmd_buffer->cs, 4096);
4953
4954 if (likely(!info->indirect)) {
4955 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4956 * no workaround for indirect draws, but we can at least skip
4957 * direct draws.
4958 */
4959 if (unlikely(!info->instance_count))
4960 return;
4961
4962 /* Handle count == 0. */
4963 if (unlikely(!info->count && !info->strmout_buffer))
4964 return;
4965 }
4966
4967 radv_describe_draw(cmd_buffer);
4968
4969 /* Use optimal packet order based on whether we need to sync the
4970 * pipeline.
4971 */
4972 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4973 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4974 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4975 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4976 /* If we have to wait for idle, set all states first, so that
4977 * all SET packets are processed in parallel with previous draw
4978 * calls. Then upload descriptors, set shader pointers, and
4979 * draw, and prefetch at the end. This ensures that the time
4980 * the CUs are idle is very short. (there are only SET_SH
4981 * packets between the wait and the draw)
4982 */
4983 radv_emit_all_graphics_states(cmd_buffer, info);
4984 si_emit_cache_flush(cmd_buffer);
4985 /* <-- CUs are idle here --> */
4986
4987 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4988
4989 radv_emit_draw_packets(cmd_buffer, info);
4990 /* <-- CUs are busy here --> */
4991
4992 /* Start prefetches after the draw has been started. Both will
4993 * run in parallel, but starting the draw first is more
4994 * important.
4995 */
4996 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4997 radv_emit_prefetch_L2(cmd_buffer,
4998 cmd_buffer->state.pipeline, false);
4999 }
5000 } else {
5001 /* If we don't wait for idle, start prefetches first, then set
5002 * states, and draw at the end.
5003 */
5004 si_emit_cache_flush(cmd_buffer);
5005
5006 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
5007 /* Only prefetch the vertex shader and VBO descriptors
5008 * in order to start the draw as soon as possible.
5009 */
5010 radv_emit_prefetch_L2(cmd_buffer,
5011 cmd_buffer->state.pipeline, true);
5012 }
5013
5014 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
5015
5016 radv_emit_all_graphics_states(cmd_buffer, info);
5017 radv_emit_draw_packets(cmd_buffer, info);
5018
5019 /* Prefetch the remaining shaders after the draw has been
5020 * started.
5021 */
5022 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
5023 radv_emit_prefetch_L2(cmd_buffer,
5024 cmd_buffer->state.pipeline, false);
5025 }
5026 }
5027
5028 /* Workaround for a VGT hang when streamout is enabled.
5029 * It must be done after drawing.
5030 */
5031 if (cmd_buffer->state.streamout.streamout_enabled &&
5032 (rad_info->family == CHIP_HAWAII ||
5033 rad_info->family == CHIP_TONGA ||
5034 rad_info->family == CHIP_FIJI)) {
5035 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
5036 }
5037
5038 assert(cmd_buffer->cs->cdw <= cdw_max);
5039 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
5040 }
5041
5042 void radv_CmdDraw(
5043 VkCommandBuffer commandBuffer,
5044 uint32_t vertexCount,
5045 uint32_t instanceCount,
5046 uint32_t firstVertex,
5047 uint32_t firstInstance)
5048 {
5049 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5050 struct radv_draw_info info = {};
5051
5052 info.count = vertexCount;
5053 info.instance_count = instanceCount;
5054 info.first_instance = firstInstance;
5055 info.vertex_offset = firstVertex;
5056
5057 radv_draw(cmd_buffer, &info);
5058 }
5059
5060 void radv_CmdDrawIndexed(
5061 VkCommandBuffer commandBuffer,
5062 uint32_t indexCount,
5063 uint32_t instanceCount,
5064 uint32_t firstIndex,
5065 int32_t vertexOffset,
5066 uint32_t firstInstance)
5067 {
5068 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5069 struct radv_draw_info info = {};
5070
5071 info.indexed = true;
5072 info.count = indexCount;
5073 info.instance_count = instanceCount;
5074 info.first_index = firstIndex;
5075 info.vertex_offset = vertexOffset;
5076 info.first_instance = firstInstance;
5077
5078 radv_draw(cmd_buffer, &info);
5079 }
5080
5081 void radv_CmdDrawIndirect(
5082 VkCommandBuffer commandBuffer,
5083 VkBuffer _buffer,
5084 VkDeviceSize offset,
5085 uint32_t drawCount,
5086 uint32_t stride)
5087 {
5088 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5089 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5090 struct radv_draw_info info = {};
5091
5092 info.count = drawCount;
5093 info.indirect = buffer;
5094 info.indirect_offset = offset;
5095 info.stride = stride;
5096
5097 radv_draw(cmd_buffer, &info);
5098 }
5099
5100 void radv_CmdDrawIndexedIndirect(
5101 VkCommandBuffer commandBuffer,
5102 VkBuffer _buffer,
5103 VkDeviceSize offset,
5104 uint32_t drawCount,
5105 uint32_t stride)
5106 {
5107 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5108 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5109 struct radv_draw_info info = {};
5110
5111 info.indexed = true;
5112 info.count = drawCount;
5113 info.indirect = buffer;
5114 info.indirect_offset = offset;
5115 info.stride = stride;
5116
5117 radv_draw(cmd_buffer, &info);
5118 }
5119
5120 void radv_CmdDrawIndirectCount(
5121 VkCommandBuffer commandBuffer,
5122 VkBuffer _buffer,
5123 VkDeviceSize offset,
5124 VkBuffer _countBuffer,
5125 VkDeviceSize countBufferOffset,
5126 uint32_t maxDrawCount,
5127 uint32_t stride)
5128 {
5129 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5130 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5131 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
5132 struct radv_draw_info info = {};
5133
5134 info.count = maxDrawCount;
5135 info.indirect = buffer;
5136 info.indirect_offset = offset;
5137 info.count_buffer = count_buffer;
5138 info.count_buffer_offset = countBufferOffset;
5139 info.stride = stride;
5140
5141 radv_draw(cmd_buffer, &info);
5142 }
5143
5144 void radv_CmdDrawIndexedIndirectCount(
5145 VkCommandBuffer commandBuffer,
5146 VkBuffer _buffer,
5147 VkDeviceSize offset,
5148 VkBuffer _countBuffer,
5149 VkDeviceSize countBufferOffset,
5150 uint32_t maxDrawCount,
5151 uint32_t stride)
5152 {
5153 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5154 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5155 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
5156 struct radv_draw_info info = {};
5157
5158 info.indexed = true;
5159 info.count = maxDrawCount;
5160 info.indirect = buffer;
5161 info.indirect_offset = offset;
5162 info.count_buffer = count_buffer;
5163 info.count_buffer_offset = countBufferOffset;
5164 info.stride = stride;
5165
5166 radv_draw(cmd_buffer, &info);
5167 }
5168
5169 struct radv_dispatch_info {
5170 /**
5171 * Determine the layout of the grid (in block units) to be used.
5172 */
5173 uint32_t blocks[3];
5174
5175 /**
5176 * A starting offset for the grid. If unaligned is set, the offset
5177 * must still be aligned.
5178 */
5179 uint32_t offsets[3];
5180 /**
5181 * Whether it's an unaligned compute dispatch.
5182 */
5183 bool unaligned;
5184
5185 /**
5186 * Indirect compute parameters resource.
5187 */
5188 struct radv_buffer *indirect;
5189 uint64_t indirect_offset;
5190 };
5191
5192 static void
5193 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
5194 const struct radv_dispatch_info *info)
5195 {
5196 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
5197 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5198 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
5199 struct radeon_winsys *ws = cmd_buffer->device->ws;
5200 bool predicating = cmd_buffer->state.predicating;
5201 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5202 struct radv_userdata_info *loc;
5203
5204 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
5205 AC_UD_CS_GRID_SIZE);
5206
5207 ASSERTED unsigned cdw_max = radeon_check_space(ws, cs, 25);
5208
5209 if (compute_shader->info.wave_size == 32) {
5210 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
5211 dispatch_initiator |= S_00B800_CS_W32_EN(1);
5212 }
5213
5214 if (info->indirect) {
5215 uint64_t va = radv_buffer_get_va(info->indirect->bo);
5216
5217 va += info->indirect->offset + info->indirect_offset;
5218
5219 radv_cs_add_buffer(ws, cs, info->indirect->bo);
5220
5221 if (loc->sgpr_idx != -1) {
5222 for (unsigned i = 0; i < 3; ++i) {
5223 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5224 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5225 COPY_DATA_DST_SEL(COPY_DATA_REG));
5226 radeon_emit(cs, (va + 4 * i));
5227 radeon_emit(cs, (va + 4 * i) >> 32);
5228 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
5229 + loc->sgpr_idx * 4) >> 2) + i);
5230 radeon_emit(cs, 0);
5231 }
5232 }
5233
5234 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
5235 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
5236 PKT3_SHADER_TYPE_S(1));
5237 radeon_emit(cs, va);
5238 radeon_emit(cs, va >> 32);
5239 radeon_emit(cs, dispatch_initiator);
5240 } else {
5241 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
5242 PKT3_SHADER_TYPE_S(1));
5243 radeon_emit(cs, 1);
5244 radeon_emit(cs, va);
5245 radeon_emit(cs, va >> 32);
5246
5247 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
5248 PKT3_SHADER_TYPE_S(1));
5249 radeon_emit(cs, 0);
5250 radeon_emit(cs, dispatch_initiator);
5251 }
5252 } else {
5253 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
5254 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
5255
5256 if (info->unaligned) {
5257 unsigned *cs_block_size = compute_shader->info.cs.block_size;
5258 unsigned remainder[3];
5259
5260 /* If aligned, these should be an entire block size,
5261 * not 0.
5262 */
5263 remainder[0] = blocks[0] + cs_block_size[0] -
5264 align_u32_npot(blocks[0], cs_block_size[0]);
5265 remainder[1] = blocks[1] + cs_block_size[1] -
5266 align_u32_npot(blocks[1], cs_block_size[1]);
5267 remainder[2] = blocks[2] + cs_block_size[2] -
5268 align_u32_npot(blocks[2], cs_block_size[2]);
5269
5270 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
5271 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
5272 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
5273
5274 for(unsigned i = 0; i < 3; ++i) {
5275 assert(offsets[i] % cs_block_size[i] == 0);
5276 offsets[i] /= cs_block_size[i];
5277 }
5278
5279 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5280 radeon_emit(cs,
5281 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
5282 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
5283 radeon_emit(cs,
5284 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
5285 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
5286 radeon_emit(cs,
5287 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
5288 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
5289
5290 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
5291 }
5292
5293 if (loc->sgpr_idx != -1) {
5294 assert(loc->num_sgprs == 3);
5295
5296 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
5297 loc->sgpr_idx * 4, 3);
5298 radeon_emit(cs, blocks[0]);
5299 radeon_emit(cs, blocks[1]);
5300 radeon_emit(cs, blocks[2]);
5301 }
5302
5303 if (offsets[0] || offsets[1] || offsets[2]) {
5304 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
5305 radeon_emit(cs, offsets[0]);
5306 radeon_emit(cs, offsets[1]);
5307 radeon_emit(cs, offsets[2]);
5308
5309 /* The blocks in the packet are not counts but end values. */
5310 for (unsigned i = 0; i < 3; ++i)
5311 blocks[i] += offsets[i];
5312 } else {
5313 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
5314 }
5315
5316 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
5317 PKT3_SHADER_TYPE_S(1));
5318 radeon_emit(cs, blocks[0]);
5319 radeon_emit(cs, blocks[1]);
5320 radeon_emit(cs, blocks[2]);
5321 radeon_emit(cs, dispatch_initiator);
5322 }
5323
5324 assert(cmd_buffer->cs->cdw <= cdw_max);
5325 }
5326
5327 static void
5328 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
5329 {
5330 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5331 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5332 }
5333
5334 static void
5335 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
5336 const struct radv_dispatch_info *info)
5337 {
5338 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
5339 bool has_prefetch =
5340 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
5341 bool pipeline_is_dirty = pipeline &&
5342 pipeline != cmd_buffer->state.emitted_compute_pipeline;
5343
5344 radv_describe_dispatch(cmd_buffer, 8, 8, 8);
5345
5346 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5347 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5348 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
5349 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
5350 /* If we have to wait for idle, set all states first, so that
5351 * all SET packets are processed in parallel with previous draw
5352 * calls. Then upload descriptors, set shader pointers, and
5353 * dispatch, and prefetch at the end. This ensures that the
5354 * time the CUs are idle is very short. (there are only SET_SH
5355 * packets between the wait and the draw)
5356 */
5357 radv_emit_compute_pipeline(cmd_buffer);
5358 si_emit_cache_flush(cmd_buffer);
5359 /* <-- CUs are idle here --> */
5360
5361 radv_upload_compute_shader_descriptors(cmd_buffer);
5362
5363 radv_emit_dispatch_packets(cmd_buffer, info);
5364 /* <-- CUs are busy here --> */
5365
5366 /* Start prefetches after the dispatch has been started. Both
5367 * will run in parallel, but starting the dispatch first is
5368 * more important.
5369 */
5370 if (has_prefetch && pipeline_is_dirty) {
5371 radv_emit_shader_prefetch(cmd_buffer,
5372 pipeline->shaders[MESA_SHADER_COMPUTE]);
5373 }
5374 } else {
5375 /* If we don't wait for idle, start prefetches first, then set
5376 * states, and dispatch at the end.
5377 */
5378 si_emit_cache_flush(cmd_buffer);
5379
5380 if (has_prefetch && pipeline_is_dirty) {
5381 radv_emit_shader_prefetch(cmd_buffer,
5382 pipeline->shaders[MESA_SHADER_COMPUTE]);
5383 }
5384
5385 radv_upload_compute_shader_descriptors(cmd_buffer);
5386
5387 radv_emit_compute_pipeline(cmd_buffer);
5388 radv_emit_dispatch_packets(cmd_buffer, info);
5389 }
5390
5391 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
5392 }
5393
5394 void radv_CmdDispatchBase(
5395 VkCommandBuffer commandBuffer,
5396 uint32_t base_x,
5397 uint32_t base_y,
5398 uint32_t base_z,
5399 uint32_t x,
5400 uint32_t y,
5401 uint32_t z)
5402 {
5403 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5404 struct radv_dispatch_info info = {};
5405
5406 info.blocks[0] = x;
5407 info.blocks[1] = y;
5408 info.blocks[2] = z;
5409
5410 info.offsets[0] = base_x;
5411 info.offsets[1] = base_y;
5412 info.offsets[2] = base_z;
5413 radv_dispatch(cmd_buffer, &info);
5414 }
5415
5416 void radv_CmdDispatch(
5417 VkCommandBuffer commandBuffer,
5418 uint32_t x,
5419 uint32_t y,
5420 uint32_t z)
5421 {
5422 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
5423 }
5424
5425 void radv_CmdDispatchIndirect(
5426 VkCommandBuffer commandBuffer,
5427 VkBuffer _buffer,
5428 VkDeviceSize offset)
5429 {
5430 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5431 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5432 struct radv_dispatch_info info = {};
5433
5434 info.indirect = buffer;
5435 info.indirect_offset = offset;
5436
5437 radv_dispatch(cmd_buffer, &info);
5438 }
5439
5440 void radv_unaligned_dispatch(
5441 struct radv_cmd_buffer *cmd_buffer,
5442 uint32_t x,
5443 uint32_t y,
5444 uint32_t z)
5445 {
5446 struct radv_dispatch_info info = {};
5447
5448 info.blocks[0] = x;
5449 info.blocks[1] = y;
5450 info.blocks[2] = z;
5451 info.unaligned = 1;
5452
5453 radv_dispatch(cmd_buffer, &info);
5454 }
5455
5456 void
5457 radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer *cmd_buffer)
5458 {
5459 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
5460 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
5461
5462 cmd_buffer->state.pass = NULL;
5463 cmd_buffer->state.subpass = NULL;
5464 cmd_buffer->state.attachments = NULL;
5465 cmd_buffer->state.framebuffer = NULL;
5466 cmd_buffer->state.subpass_sample_locs = NULL;
5467 }
5468
5469 void radv_CmdEndRenderPass(
5470 VkCommandBuffer commandBuffer)
5471 {
5472 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5473
5474 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
5475
5476 radv_cmd_buffer_end_subpass(cmd_buffer);
5477
5478 radv_cmd_buffer_end_render_pass(cmd_buffer);
5479 }
5480
5481 void radv_CmdEndRenderPass2(
5482 VkCommandBuffer commandBuffer,
5483 const VkSubpassEndInfo* pSubpassEndInfo)
5484 {
5485 radv_CmdEndRenderPass(commandBuffer);
5486 }
5487
5488 /*
5489 * For HTILE we have the following interesting clear words:
5490 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5491 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5492 * 0xfffffff0: Clear depth to 1.0
5493 * 0x00000000: Clear depth to 0.0
5494 */
5495 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
5496 struct radv_image *image,
5497 const VkImageSubresourceRange *range)
5498 {
5499 assert(range->baseMipLevel == 0);
5500 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
5501 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
5502 struct radv_cmd_state *state = &cmd_buffer->state;
5503 uint32_t htile_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5504 VkClearDepthStencilValue value = {};
5505 struct radv_barrier_data barrier = {};
5506
5507 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5508 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5509
5510 barrier.layout_transitions.init_mask_ram = 1;
5511 radv_describe_layout_transition(cmd_buffer, &barrier);
5512
5513 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, htile_value);
5514
5515 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5516
5517 if (vk_format_is_stencil(image->vk_format))
5518 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
5519
5520 radv_set_ds_clear_metadata(cmd_buffer, image, range, value, aspects);
5521
5522 if (radv_image_is_tc_compat_htile(image)) {
5523 /* Initialize the TC-compat metada value to 0 because by
5524 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5525 * need have to conditionally update its value when performing
5526 * a fast depth clear.
5527 */
5528 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, range, 0);
5529 }
5530 }
5531
5532 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
5533 struct radv_image *image,
5534 VkImageLayout src_layout,
5535 bool src_render_loop,
5536 VkImageLayout dst_layout,
5537 bool dst_render_loop,
5538 unsigned src_queue_mask,
5539 unsigned dst_queue_mask,
5540 const VkImageSubresourceRange *range,
5541 struct radv_sample_locations_state *sample_locs)
5542 {
5543 if (!radv_image_has_htile(image))
5544 return;
5545
5546 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5547 radv_initialize_htile(cmd_buffer, image, range);
5548 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5549 radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5550 radv_initialize_htile(cmd_buffer, image, range);
5551 } else if (radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5552 !radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5553 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5554 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5555
5556 radv_decompress_depth_stencil(cmd_buffer, image, range,
5557 sample_locs);
5558
5559 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5560 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5561 }
5562 }
5563
5564 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
5565 struct radv_image *image,
5566 const VkImageSubresourceRange *range,
5567 uint32_t value)
5568 {
5569 struct radv_cmd_state *state = &cmd_buffer->state;
5570 struct radv_barrier_data barrier = {};
5571
5572 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5573 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5574
5575 barrier.layout_transitions.init_mask_ram = 1;
5576 radv_describe_layout_transition(cmd_buffer, &barrier);
5577
5578 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
5579
5580 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5581 }
5582
5583 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
5584 struct radv_image *image,
5585 const VkImageSubresourceRange *range)
5586 {
5587 struct radv_cmd_state *state = &cmd_buffer->state;
5588 static const uint32_t fmask_clear_values[4] = {
5589 0x00000000,
5590 0x02020202,
5591 0xE4E4E4E4,
5592 0x76543210
5593 };
5594 uint32_t log2_samples = util_logbase2(image->info.samples);
5595 uint32_t value = fmask_clear_values[log2_samples];
5596 struct radv_barrier_data barrier = {};
5597
5598 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5599 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5600
5601 barrier.layout_transitions.init_mask_ram = 1;
5602 radv_describe_layout_transition(cmd_buffer, &barrier);
5603
5604 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
5605
5606 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5607 }
5608
5609 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
5610 struct radv_image *image,
5611 const VkImageSubresourceRange *range, uint32_t value)
5612 {
5613 struct radv_cmd_state *state = &cmd_buffer->state;
5614 struct radv_barrier_data barrier = {};
5615 unsigned size = 0;
5616
5617 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5618 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5619
5620 barrier.layout_transitions.init_mask_ram = 1;
5621 radv_describe_layout_transition(cmd_buffer, &barrier);
5622
5623 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
5624
5625 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
5626 /* When DCC is enabled with mipmaps, some levels might not
5627 * support fast clears and we have to initialize them as "fully
5628 * expanded".
5629 */
5630 /* Compute the size of all fast clearable DCC levels. */
5631 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
5632 struct legacy_surf_level *surf_level =
5633 &image->planes[0].surface.u.legacy.level[i];
5634 unsigned dcc_fast_clear_size =
5635 surf_level->dcc_slice_fast_clear_size * image->info.array_size;
5636
5637 if (!dcc_fast_clear_size)
5638 break;
5639
5640 size = surf_level->dcc_offset + dcc_fast_clear_size;
5641 }
5642
5643 /* Initialize the mipmap levels without DCC. */
5644 if (size != image->planes[0].surface.dcc_size) {
5645 state->flush_bits |=
5646 radv_fill_buffer(cmd_buffer, image->bo,
5647 image->offset + image->planes[0].surface.dcc_offset + size,
5648 image->planes[0].surface.dcc_size - size,
5649 0xffffffff);
5650 }
5651 }
5652
5653 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5654 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5655 }
5656
5657 /**
5658 * Initialize DCC/FMASK/CMASK metadata for a color image.
5659 */
5660 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
5661 struct radv_image *image,
5662 VkImageLayout src_layout,
5663 bool src_render_loop,
5664 VkImageLayout dst_layout,
5665 bool dst_render_loop,
5666 unsigned src_queue_mask,
5667 unsigned dst_queue_mask,
5668 const VkImageSubresourceRange *range)
5669 {
5670 if (radv_image_has_cmask(image)) {
5671 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5672
5673 /* TODO: clarify this. */
5674 if (radv_image_has_fmask(image)) {
5675 value = 0xccccccccu;
5676 }
5677
5678 radv_initialise_cmask(cmd_buffer, image, range, value);
5679 }
5680
5681 if (radv_image_has_fmask(image)) {
5682 radv_initialize_fmask(cmd_buffer, image, range);
5683 }
5684
5685 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5686 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5687 bool need_decompress_pass = false;
5688
5689 if (radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout,
5690 dst_render_loop,
5691 dst_queue_mask)) {
5692 value = 0x20202020u;
5693 need_decompress_pass = true;
5694 }
5695
5696 radv_initialize_dcc(cmd_buffer, image, range, value);
5697
5698 radv_update_fce_metadata(cmd_buffer, image, range,
5699 need_decompress_pass);
5700 }
5701
5702 if (radv_image_has_cmask(image) ||
5703 radv_dcc_enabled(image, range->baseMipLevel)) {
5704 uint32_t color_values[2] = {};
5705 radv_set_color_clear_metadata(cmd_buffer, image, range,
5706 color_values);
5707 }
5708 }
5709
5710 /**
5711 * Handle color image transitions for DCC/FMASK/CMASK.
5712 */
5713 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
5714 struct radv_image *image,
5715 VkImageLayout src_layout,
5716 bool src_render_loop,
5717 VkImageLayout dst_layout,
5718 bool dst_render_loop,
5719 unsigned src_queue_mask,
5720 unsigned dst_queue_mask,
5721 const VkImageSubresourceRange *range)
5722 {
5723 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5724 radv_init_color_image_metadata(cmd_buffer, image,
5725 src_layout, src_render_loop,
5726 dst_layout, dst_render_loop,
5727 src_queue_mask, dst_queue_mask,
5728 range);
5729 return;
5730 }
5731
5732 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5733 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
5734 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
5735 } else if (radv_layout_dcc_compressed(cmd_buffer->device, image, src_layout, src_render_loop, src_queue_mask) &&
5736 !radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout, dst_render_loop, dst_queue_mask)) {
5737 radv_decompress_dcc(cmd_buffer, image, range);
5738 } else if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5739 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5740 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5741 }
5742 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
5743 bool fce_eliminate = false, fmask_expand = false;
5744
5745 if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5746 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5747 fce_eliminate = true;
5748 }
5749
5750 if (radv_image_has_fmask(image)) {
5751 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
5752 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
5753 /* A FMASK decompress is required before doing
5754 * a MSAA decompress using FMASK.
5755 */
5756 fmask_expand = true;
5757 }
5758 }
5759
5760 if (fce_eliminate || fmask_expand)
5761 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5762
5763 if (fmask_expand) {
5764 struct radv_barrier_data barrier = {};
5765 barrier.layout_transitions.fmask_color_expand = 1;
5766 radv_describe_layout_transition(cmd_buffer, &barrier);
5767
5768 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
5769 }
5770 }
5771 }
5772
5773 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
5774 struct radv_image *image,
5775 VkImageLayout src_layout,
5776 bool src_render_loop,
5777 VkImageLayout dst_layout,
5778 bool dst_render_loop,
5779 uint32_t src_family,
5780 uint32_t dst_family,
5781 const VkImageSubresourceRange *range,
5782 struct radv_sample_locations_state *sample_locs)
5783 {
5784 if (image->exclusive && src_family != dst_family) {
5785 /* This is an acquire or a release operation and there will be
5786 * a corresponding release/acquire. Do the transition in the
5787 * most flexible queue. */
5788
5789 assert(src_family == cmd_buffer->queue_family_index ||
5790 dst_family == cmd_buffer->queue_family_index);
5791
5792 if (src_family == VK_QUEUE_FAMILY_EXTERNAL ||
5793 src_family == VK_QUEUE_FAMILY_FOREIGN_EXT)
5794 return;
5795
5796 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
5797 return;
5798
5799 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
5800 (src_family == RADV_QUEUE_GENERAL ||
5801 dst_family == RADV_QUEUE_GENERAL))
5802 return;
5803 }
5804
5805 if (src_layout == dst_layout)
5806 return;
5807
5808 unsigned src_queue_mask =
5809 radv_image_queue_family_mask(image, src_family,
5810 cmd_buffer->queue_family_index);
5811 unsigned dst_queue_mask =
5812 radv_image_queue_family_mask(image, dst_family,
5813 cmd_buffer->queue_family_index);
5814
5815 if (vk_format_is_depth(image->vk_format)) {
5816 radv_handle_depth_image_transition(cmd_buffer, image,
5817 src_layout, src_render_loop,
5818 dst_layout, dst_render_loop,
5819 src_queue_mask, dst_queue_mask,
5820 range, sample_locs);
5821 } else {
5822 radv_handle_color_image_transition(cmd_buffer, image,
5823 src_layout, src_render_loop,
5824 dst_layout, dst_render_loop,
5825 src_queue_mask, dst_queue_mask,
5826 range);
5827 }
5828 }
5829
5830 struct radv_barrier_info {
5831 enum rgp_barrier_reason reason;
5832 uint32_t eventCount;
5833 const VkEvent *pEvents;
5834 VkPipelineStageFlags srcStageMask;
5835 VkPipelineStageFlags dstStageMask;
5836 };
5837
5838 static void
5839 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
5840 uint32_t memoryBarrierCount,
5841 const VkMemoryBarrier *pMemoryBarriers,
5842 uint32_t bufferMemoryBarrierCount,
5843 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
5844 uint32_t imageMemoryBarrierCount,
5845 const VkImageMemoryBarrier *pImageMemoryBarriers,
5846 const struct radv_barrier_info *info)
5847 {
5848 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5849 enum radv_cmd_flush_bits src_flush_bits = 0;
5850 enum radv_cmd_flush_bits dst_flush_bits = 0;
5851
5852 radv_describe_barrier_start(cmd_buffer, info->reason);
5853
5854 for (unsigned i = 0; i < info->eventCount; ++i) {
5855 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
5856 uint64_t va = radv_buffer_get_va(event->bo);
5857
5858 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5859
5860 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
5861
5862 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
5863 assert(cmd_buffer->cs->cdw <= cdw_max);
5864 }
5865
5866 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
5867 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
5868 NULL);
5869 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
5870 NULL);
5871 }
5872
5873 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
5874 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
5875 NULL);
5876 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
5877 NULL);
5878 }
5879
5880 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5881 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5882
5883 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
5884 image);
5885 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
5886 image);
5887 }
5888
5889 /* The Vulkan spec 1.1.98 says:
5890 *
5891 * "An execution dependency with only
5892 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5893 * will only prevent that stage from executing in subsequently
5894 * submitted commands. As this stage does not perform any actual
5895 * execution, this is not observable - in effect, it does not delay
5896 * processing of subsequent commands. Similarly an execution dependency
5897 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5898 * will effectively not wait for any prior commands to complete."
5899 */
5900 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
5901 radv_stage_flush(cmd_buffer, info->srcStageMask);
5902 cmd_buffer->state.flush_bits |= src_flush_bits;
5903
5904 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5905 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5906
5907 const struct VkSampleLocationsInfoEXT *sample_locs_info =
5908 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
5909 SAMPLE_LOCATIONS_INFO_EXT);
5910 struct radv_sample_locations_state sample_locations = {};
5911
5912 if (sample_locs_info) {
5913 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
5914 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
5915 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
5916 sample_locations.count = sample_locs_info->sampleLocationsCount;
5917 typed_memcpy(&sample_locations.locations[0],
5918 sample_locs_info->pSampleLocations,
5919 sample_locs_info->sampleLocationsCount);
5920 }
5921
5922 radv_handle_image_transition(cmd_buffer, image,
5923 pImageMemoryBarriers[i].oldLayout,
5924 false, /* Outside of a renderpass we are never in a renderloop */
5925 pImageMemoryBarriers[i].newLayout,
5926 false, /* Outside of a renderpass we are never in a renderloop */
5927 pImageMemoryBarriers[i].srcQueueFamilyIndex,
5928 pImageMemoryBarriers[i].dstQueueFamilyIndex,
5929 &pImageMemoryBarriers[i].subresourceRange,
5930 sample_locs_info ? &sample_locations : NULL);
5931 }
5932
5933 /* Make sure CP DMA is idle because the driver might have performed a
5934 * DMA operation for copying or filling buffers/images.
5935 */
5936 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5937 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5938 si_cp_dma_wait_for_idle(cmd_buffer);
5939
5940 cmd_buffer->state.flush_bits |= dst_flush_bits;
5941
5942 radv_describe_barrier_end(cmd_buffer);
5943 }
5944
5945 void radv_CmdPipelineBarrier(
5946 VkCommandBuffer commandBuffer,
5947 VkPipelineStageFlags srcStageMask,
5948 VkPipelineStageFlags destStageMask,
5949 VkBool32 byRegion,
5950 uint32_t memoryBarrierCount,
5951 const VkMemoryBarrier* pMemoryBarriers,
5952 uint32_t bufferMemoryBarrierCount,
5953 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5954 uint32_t imageMemoryBarrierCount,
5955 const VkImageMemoryBarrier* pImageMemoryBarriers)
5956 {
5957 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5958 struct radv_barrier_info info;
5959
5960 info.reason = RGP_BARRIER_EXTERNAL_CMD_PIPELINE_BARRIER;
5961 info.eventCount = 0;
5962 info.pEvents = NULL;
5963 info.srcStageMask = srcStageMask;
5964 info.dstStageMask = destStageMask;
5965
5966 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5967 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5968 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5969 }
5970
5971
5972 static void write_event(struct radv_cmd_buffer *cmd_buffer,
5973 struct radv_event *event,
5974 VkPipelineStageFlags stageMask,
5975 unsigned value)
5976 {
5977 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5978 uint64_t va = radv_buffer_get_va(event->bo);
5979
5980 si_emit_cache_flush(cmd_buffer);
5981
5982 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5983
5984 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
5985
5986 /* Flags that only require a top-of-pipe event. */
5987 VkPipelineStageFlags top_of_pipe_flags =
5988 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
5989
5990 /* Flags that only require a post-index-fetch event. */
5991 VkPipelineStageFlags post_index_fetch_flags =
5992 top_of_pipe_flags |
5993 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
5994 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
5995
5996 /* Make sure CP DMA is idle because the driver might have performed a
5997 * DMA operation for copying or filling buffers/images.
5998 */
5999 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
6000 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
6001 si_cp_dma_wait_for_idle(cmd_buffer);
6002
6003 /* TODO: Emit EOS events for syncing PS/CS stages. */
6004
6005 if (!(stageMask & ~top_of_pipe_flags)) {
6006 /* Just need to sync the PFP engine. */
6007 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
6008 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
6009 S_370_WR_CONFIRM(1) |
6010 S_370_ENGINE_SEL(V_370_PFP));
6011 radeon_emit(cs, va);
6012 radeon_emit(cs, va >> 32);
6013 radeon_emit(cs, value);
6014 } else if (!(stageMask & ~post_index_fetch_flags)) {
6015 /* Sync ME because PFP reads index and indirect buffers. */
6016 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
6017 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
6018 S_370_WR_CONFIRM(1) |
6019 S_370_ENGINE_SEL(V_370_ME));
6020 radeon_emit(cs, va);
6021 radeon_emit(cs, va >> 32);
6022 radeon_emit(cs, value);
6023 } else {
6024 /* Otherwise, sync all prior GPU work using an EOP event. */
6025 si_cs_emit_write_event_eop(cs,
6026 cmd_buffer->device->physical_device->rad_info.chip_class,
6027 radv_cmd_buffer_uses_mec(cmd_buffer),
6028 V_028A90_BOTTOM_OF_PIPE_TS, 0,
6029 EOP_DST_SEL_MEM,
6030 EOP_DATA_SEL_VALUE_32BIT, va, value,
6031 cmd_buffer->gfx9_eop_bug_va);
6032 }
6033
6034 assert(cmd_buffer->cs->cdw <= cdw_max);
6035 }
6036
6037 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
6038 VkEvent _event,
6039 VkPipelineStageFlags stageMask)
6040 {
6041 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6042 RADV_FROM_HANDLE(radv_event, event, _event);
6043
6044 write_event(cmd_buffer, event, stageMask, 1);
6045 }
6046
6047 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
6048 VkEvent _event,
6049 VkPipelineStageFlags stageMask)
6050 {
6051 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6052 RADV_FROM_HANDLE(radv_event, event, _event);
6053
6054 write_event(cmd_buffer, event, stageMask, 0);
6055 }
6056
6057 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
6058 uint32_t eventCount,
6059 const VkEvent* pEvents,
6060 VkPipelineStageFlags srcStageMask,
6061 VkPipelineStageFlags dstStageMask,
6062 uint32_t memoryBarrierCount,
6063 const VkMemoryBarrier* pMemoryBarriers,
6064 uint32_t bufferMemoryBarrierCount,
6065 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
6066 uint32_t imageMemoryBarrierCount,
6067 const VkImageMemoryBarrier* pImageMemoryBarriers)
6068 {
6069 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6070 struct radv_barrier_info info;
6071
6072 info.reason = RGP_BARRIER_EXTERNAL_CMD_WAIT_EVENTS;
6073 info.eventCount = eventCount;
6074 info.pEvents = pEvents;
6075 info.srcStageMask = 0;
6076
6077 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
6078 bufferMemoryBarrierCount, pBufferMemoryBarriers,
6079 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
6080 }
6081
6082
6083 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
6084 uint32_t deviceMask)
6085 {
6086 /* No-op */
6087 }
6088
6089 /* VK_EXT_conditional_rendering */
6090 void radv_CmdBeginConditionalRenderingEXT(
6091 VkCommandBuffer commandBuffer,
6092 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
6093 {
6094 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6095 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
6096 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6097 bool draw_visible = true;
6098 uint64_t pred_value = 0;
6099 uint64_t va, new_va;
6100 unsigned pred_offset;
6101
6102 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
6103
6104 /* By default, if the 32-bit value at offset in buffer memory is zero,
6105 * then the rendering commands are discarded, otherwise they are
6106 * executed as normal. If the inverted flag is set, all commands are
6107 * discarded if the value is non zero.
6108 */
6109 if (pConditionalRenderingBegin->flags &
6110 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
6111 draw_visible = false;
6112 }
6113
6114 si_emit_cache_flush(cmd_buffer);
6115
6116 /* From the Vulkan spec 1.1.107:
6117 *
6118 * "If the 32-bit value at offset in buffer memory is zero, then the
6119 * rendering commands are discarded, otherwise they are executed as
6120 * normal. If the value of the predicate in buffer memory changes while
6121 * conditional rendering is active, the rendering commands may be
6122 * discarded in an implementation-dependent way. Some implementations
6123 * may latch the value of the predicate upon beginning conditional
6124 * rendering while others may read it before every rendering command."
6125 *
6126 * But, the AMD hardware treats the predicate as a 64-bit value which
6127 * means we need a workaround in the driver. Luckily, it's not required
6128 * to support if the value changes when predication is active.
6129 *
6130 * The workaround is as follows:
6131 * 1) allocate a 64-value in the upload BO and initialize it to 0
6132 * 2) copy the 32-bit predicate value to the upload BO
6133 * 3) use the new allocated VA address for predication
6134 *
6135 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
6136 * in ME (+ sync PFP) instead of PFP.
6137 */
6138 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
6139
6140 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
6141
6142 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
6143 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
6144 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
6145 COPY_DATA_WR_CONFIRM);
6146 radeon_emit(cs, va);
6147 radeon_emit(cs, va >> 32);
6148 radeon_emit(cs, new_va);
6149 radeon_emit(cs, new_va >> 32);
6150
6151 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
6152 radeon_emit(cs, 0);
6153
6154 /* Enable predication for this command buffer. */
6155 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
6156 cmd_buffer->state.predicating = true;
6157
6158 /* Store conditional rendering user info. */
6159 cmd_buffer->state.predication_type = draw_visible;
6160 cmd_buffer->state.predication_va = new_va;
6161 }
6162
6163 void radv_CmdEndConditionalRenderingEXT(
6164 VkCommandBuffer commandBuffer)
6165 {
6166 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6167
6168 /* Disable predication for this command buffer. */
6169 si_emit_set_predication_state(cmd_buffer, false, 0);
6170 cmd_buffer->state.predicating = false;
6171
6172 /* Reset conditional rendering user info. */
6173 cmd_buffer->state.predication_type = -1;
6174 cmd_buffer->state.predication_va = 0;
6175 }
6176
6177 /* VK_EXT_transform_feedback */
6178 void radv_CmdBindTransformFeedbackBuffersEXT(
6179 VkCommandBuffer commandBuffer,
6180 uint32_t firstBinding,
6181 uint32_t bindingCount,
6182 const VkBuffer* pBuffers,
6183 const VkDeviceSize* pOffsets,
6184 const VkDeviceSize* pSizes)
6185 {
6186 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6187 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
6188 uint8_t enabled_mask = 0;
6189
6190 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
6191 for (uint32_t i = 0; i < bindingCount; i++) {
6192 uint32_t idx = firstBinding + i;
6193
6194 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
6195 sb[idx].offset = pOffsets[i];
6196
6197 if (!pSizes || pSizes[i] == VK_WHOLE_SIZE) {
6198 sb[idx].size = sb[idx].buffer->size - sb[idx].offset;
6199 } else {
6200 sb[idx].size = pSizes[i];
6201 }
6202
6203 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
6204 sb[idx].buffer->bo);
6205
6206 enabled_mask |= 1 << idx;
6207 }
6208
6209 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
6210
6211 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
6212 }
6213
6214 static void
6215 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
6216 {
6217 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6218 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6219
6220 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
6221 radeon_emit(cs,
6222 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
6223 S_028B94_RAST_STREAM(0) |
6224 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
6225 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
6226 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
6227 radeon_emit(cs, so->hw_enabled_mask &
6228 so->enabled_stream_buffers_mask);
6229
6230 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6231 }
6232
6233 static void
6234 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
6235 {
6236 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6237 bool old_streamout_enabled = so->streamout_enabled;
6238 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
6239
6240 so->streamout_enabled = enable;
6241
6242 so->hw_enabled_mask = so->enabled_mask |
6243 (so->enabled_mask << 4) |
6244 (so->enabled_mask << 8) |
6245 (so->enabled_mask << 12);
6246
6247 if (!cmd_buffer->device->physical_device->use_ngg_streamout &&
6248 ((old_streamout_enabled != so->streamout_enabled) ||
6249 (old_hw_enabled_mask != so->hw_enabled_mask)))
6250 radv_emit_streamout_enable(cmd_buffer);
6251
6252 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6253 cmd_buffer->gds_needed = true;
6254 cmd_buffer->gds_oa_needed = true;
6255 }
6256 }
6257
6258 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
6259 {
6260 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6261 unsigned reg_strmout_cntl;
6262
6263 /* The register is at different places on different ASICs. */
6264 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
6265 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
6266 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
6267 } else {
6268 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
6269 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
6270 }
6271
6272 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
6273 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
6274
6275 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
6276 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
6277 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
6278 radeon_emit(cs, 0);
6279 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
6280 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
6281 radeon_emit(cs, 4); /* poll interval */
6282 }
6283
6284 static void
6285 radv_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6286 uint32_t firstCounterBuffer,
6287 uint32_t counterBufferCount,
6288 const VkBuffer *pCounterBuffers,
6289 const VkDeviceSize *pCounterBufferOffsets)
6290
6291 {
6292 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
6293 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6294 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6295 uint32_t i;
6296
6297 radv_flush_vgt_streamout(cmd_buffer);
6298
6299 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6300 for_each_bit(i, so->enabled_mask) {
6301 int32_t counter_buffer_idx = i - firstCounterBuffer;
6302 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6303 counter_buffer_idx = -1;
6304
6305 /* AMD GCN binds streamout buffers as shader resources.
6306 * VGT only counts primitives and tells the shader through
6307 * SGPRs what to do.
6308 */
6309 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
6310 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
6311 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
6312
6313 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6314
6315 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6316 /* The array of counter buffers is optional. */
6317 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6318 uint64_t va = radv_buffer_get_va(buffer->bo);
6319
6320 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6321
6322 /* Append */
6323 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6324 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6325 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6326 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
6327 radeon_emit(cs, 0); /* unused */
6328 radeon_emit(cs, 0); /* unused */
6329 radeon_emit(cs, va); /* src address lo */
6330 radeon_emit(cs, va >> 32); /* src address hi */
6331
6332 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6333 } else {
6334 /* Start from the beginning. */
6335 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6336 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6337 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6338 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
6339 radeon_emit(cs, 0); /* unused */
6340 radeon_emit(cs, 0); /* unused */
6341 radeon_emit(cs, 0); /* unused */
6342 radeon_emit(cs, 0); /* unused */
6343 }
6344 }
6345
6346 radv_set_streamout_enable(cmd_buffer, true);
6347 }
6348
6349 static void
6350 gfx10_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6351 uint32_t firstCounterBuffer,
6352 uint32_t counterBufferCount,
6353 const VkBuffer *pCounterBuffers,
6354 const VkDeviceSize *pCounterBufferOffsets)
6355 {
6356 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6357 unsigned last_target = util_last_bit(so->enabled_mask) - 1;
6358 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6359 uint32_t i;
6360
6361 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6362 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6363
6364 /* Sync because the next streamout operation will overwrite GDS and we
6365 * have to make sure it's idle.
6366 * TODO: Improve by tracking if there is a streamout operation in
6367 * flight.
6368 */
6369 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
6370 si_emit_cache_flush(cmd_buffer);
6371
6372 for_each_bit(i, so->enabled_mask) {
6373 int32_t counter_buffer_idx = i - firstCounterBuffer;
6374 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6375 counter_buffer_idx = -1;
6376
6377 bool append = counter_buffer_idx >= 0 &&
6378 pCounterBuffers && pCounterBuffers[counter_buffer_idx];
6379 uint64_t va = 0;
6380
6381 if (append) {
6382 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6383
6384 va += radv_buffer_get_va(buffer->bo);
6385 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6386
6387 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6388 }
6389
6390 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
6391 radeon_emit(cs, S_411_SRC_SEL(append ? V_411_SRC_ADDR_TC_L2 : V_411_DATA) |
6392 S_411_DST_SEL(V_411_GDS) |
6393 S_411_CP_SYNC(i == last_target));
6394 radeon_emit(cs, va);
6395 radeon_emit(cs, va >> 32);
6396 radeon_emit(cs, 4 * i); /* destination in GDS */
6397 radeon_emit(cs, 0);
6398 radeon_emit(cs, S_414_BYTE_COUNT_GFX9(4) |
6399 S_414_DISABLE_WR_CONFIRM_GFX9(i != last_target));
6400 }
6401
6402 radv_set_streamout_enable(cmd_buffer, true);
6403 }
6404
6405 void radv_CmdBeginTransformFeedbackEXT(
6406 VkCommandBuffer commandBuffer,
6407 uint32_t firstCounterBuffer,
6408 uint32_t counterBufferCount,
6409 const VkBuffer* pCounterBuffers,
6410 const VkDeviceSize* pCounterBufferOffsets)
6411 {
6412 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6413
6414 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6415 gfx10_emit_streamout_begin(cmd_buffer,
6416 firstCounterBuffer, counterBufferCount,
6417 pCounterBuffers, pCounterBufferOffsets);
6418 } else {
6419 radv_emit_streamout_begin(cmd_buffer,
6420 firstCounterBuffer, counterBufferCount,
6421 pCounterBuffers, pCounterBufferOffsets);
6422 }
6423 }
6424
6425 static void
6426 radv_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6427 uint32_t firstCounterBuffer,
6428 uint32_t counterBufferCount,
6429 const VkBuffer *pCounterBuffers,
6430 const VkDeviceSize *pCounterBufferOffsets)
6431 {
6432 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6433 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6434 uint32_t i;
6435
6436 radv_flush_vgt_streamout(cmd_buffer);
6437
6438 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6439 for_each_bit(i, so->enabled_mask) {
6440 int32_t counter_buffer_idx = i - firstCounterBuffer;
6441 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6442 counter_buffer_idx = -1;
6443
6444 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6445 /* The array of counters buffer is optional. */
6446 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6447 uint64_t va = radv_buffer_get_va(buffer->bo);
6448
6449 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6450
6451 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6452 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6453 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6454 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
6455 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
6456 radeon_emit(cs, va); /* dst address lo */
6457 radeon_emit(cs, va >> 32); /* dst address hi */
6458 radeon_emit(cs, 0); /* unused */
6459 radeon_emit(cs, 0); /* unused */
6460
6461 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6462 }
6463
6464 /* Deactivate transform feedback by zeroing the buffer size.
6465 * The counters (primitives generated, primitives emitted) may
6466 * be enabled even if there is not buffer bound. This ensures
6467 * that the primitives-emitted query won't increment.
6468 */
6469 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
6470
6471 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6472 }
6473
6474 radv_set_streamout_enable(cmd_buffer, false);
6475 }
6476
6477 static void
6478 gfx10_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6479 uint32_t firstCounterBuffer,
6480 uint32_t counterBufferCount,
6481 const VkBuffer *pCounterBuffers,
6482 const VkDeviceSize *pCounterBufferOffsets)
6483 {
6484 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6485 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6486 uint32_t i;
6487
6488 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6489 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6490
6491 for_each_bit(i, so->enabled_mask) {
6492 int32_t counter_buffer_idx = i - firstCounterBuffer;
6493 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6494 counter_buffer_idx = -1;
6495
6496 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6497 /* The array of counters buffer is optional. */
6498 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6499 uint64_t va = radv_buffer_get_va(buffer->bo);
6500
6501 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6502
6503 si_cs_emit_write_event_eop(cs,
6504 cmd_buffer->device->physical_device->rad_info.chip_class,
6505 radv_cmd_buffer_uses_mec(cmd_buffer),
6506 V_028A90_PS_DONE, 0,
6507 EOP_DST_SEL_TC_L2,
6508 EOP_DATA_SEL_GDS,
6509 va, EOP_DATA_GDS(i, 1), 0);
6510
6511 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6512 }
6513 }
6514
6515 radv_set_streamout_enable(cmd_buffer, false);
6516 }
6517
6518 void radv_CmdEndTransformFeedbackEXT(
6519 VkCommandBuffer commandBuffer,
6520 uint32_t firstCounterBuffer,
6521 uint32_t counterBufferCount,
6522 const VkBuffer* pCounterBuffers,
6523 const VkDeviceSize* pCounterBufferOffsets)
6524 {
6525 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6526
6527 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6528 gfx10_emit_streamout_end(cmd_buffer,
6529 firstCounterBuffer, counterBufferCount,
6530 pCounterBuffers, pCounterBufferOffsets);
6531 } else {
6532 radv_emit_streamout_end(cmd_buffer,
6533 firstCounterBuffer, counterBufferCount,
6534 pCounterBuffers, pCounterBufferOffsets);
6535 }
6536 }
6537
6538 void radv_CmdDrawIndirectByteCountEXT(
6539 VkCommandBuffer commandBuffer,
6540 uint32_t instanceCount,
6541 uint32_t firstInstance,
6542 VkBuffer _counterBuffer,
6543 VkDeviceSize counterBufferOffset,
6544 uint32_t counterOffset,
6545 uint32_t vertexStride)
6546 {
6547 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6548 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
6549 struct radv_draw_info info = {};
6550
6551 info.instance_count = instanceCount;
6552 info.first_instance = firstInstance;
6553 info.strmout_buffer = counterBuffer;
6554 info.strmout_buffer_offset = counterBufferOffset;
6555 info.stride = vertexStride;
6556
6557 radv_draw(cmd_buffer, &info);
6558 }
6559
6560 /* VK_AMD_buffer_marker */
6561 void radv_CmdWriteBufferMarkerAMD(
6562 VkCommandBuffer commandBuffer,
6563 VkPipelineStageFlagBits pipelineStage,
6564 VkBuffer dstBuffer,
6565 VkDeviceSize dstOffset,
6566 uint32_t marker)
6567 {
6568 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6569 RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
6570 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6571 uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
6572
6573 si_emit_cache_flush(cmd_buffer);
6574
6575 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 12);
6576
6577 if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
6578 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
6579 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
6580 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
6581 COPY_DATA_WR_CONFIRM);
6582 radeon_emit(cs, marker);
6583 radeon_emit(cs, 0);
6584 radeon_emit(cs, va);
6585 radeon_emit(cs, va >> 32);
6586 } else {
6587 si_cs_emit_write_event_eop(cs,
6588 cmd_buffer->device->physical_device->rad_info.chip_class,
6589 radv_cmd_buffer_uses_mec(cmd_buffer),
6590 V_028A90_BOTTOM_OF_PIPE_TS, 0,
6591 EOP_DST_SEL_MEM,
6592 EOP_DATA_SEL_VALUE_32BIT,
6593 va, marker,
6594 cmd_buffer->gfx9_eop_bug_va);
6595 }
6596
6597 assert(cmd_buffer->cs->cdw <= cdw_max);
6598 }