2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
33 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
41 RADV_PREFETCH_VBO_DESCRIPTORS
= (1 << 0),
42 RADV_PREFETCH_VS
= (1 << 1),
43 RADV_PREFETCH_TCS
= (1 << 2),
44 RADV_PREFETCH_TES
= (1 << 3),
45 RADV_PREFETCH_GS
= (1 << 4),
46 RADV_PREFETCH_PS
= (1 << 5),
47 RADV_PREFETCH_SHADERS
= (RADV_PREFETCH_VS
|
54 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
55 struct radv_image
*image
,
56 VkImageLayout src_layout
,
58 VkImageLayout dst_layout
,
62 const VkImageSubresourceRange
*range
,
63 struct radv_sample_locations_state
*sample_locs
);
65 const struct radv_dynamic_state default_dynamic_state
= {
78 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
83 .stencil_compare_mask
= {
87 .stencil_write_mask
= {
91 .stencil_reference
= {
102 radv_bind_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
,
103 const struct radv_dynamic_state
*src
)
105 struct radv_dynamic_state
*dest
= &cmd_buffer
->state
.dynamic
;
106 uint32_t copy_mask
= src
->mask
;
107 uint32_t dest_mask
= 0;
109 /* Make sure to copy the number of viewports/scissors because they can
110 * only be specified at pipeline creation time.
112 dest
->viewport
.count
= src
->viewport
.count
;
113 dest
->scissor
.count
= src
->scissor
.count
;
114 dest
->discard_rectangle
.count
= src
->discard_rectangle
.count
;
115 dest
->sample_location
.count
= src
->sample_location
.count
;
117 if (copy_mask
& RADV_DYNAMIC_VIEWPORT
) {
118 if (memcmp(&dest
->viewport
.viewports
, &src
->viewport
.viewports
,
119 src
->viewport
.count
* sizeof(VkViewport
))) {
120 typed_memcpy(dest
->viewport
.viewports
,
121 src
->viewport
.viewports
,
122 src
->viewport
.count
);
123 dest_mask
|= RADV_DYNAMIC_VIEWPORT
;
127 if (copy_mask
& RADV_DYNAMIC_SCISSOR
) {
128 if (memcmp(&dest
->scissor
.scissors
, &src
->scissor
.scissors
,
129 src
->scissor
.count
* sizeof(VkRect2D
))) {
130 typed_memcpy(dest
->scissor
.scissors
,
131 src
->scissor
.scissors
, src
->scissor
.count
);
132 dest_mask
|= RADV_DYNAMIC_SCISSOR
;
136 if (copy_mask
& RADV_DYNAMIC_LINE_WIDTH
) {
137 if (dest
->line_width
!= src
->line_width
) {
138 dest
->line_width
= src
->line_width
;
139 dest_mask
|= RADV_DYNAMIC_LINE_WIDTH
;
143 if (copy_mask
& RADV_DYNAMIC_DEPTH_BIAS
) {
144 if (memcmp(&dest
->depth_bias
, &src
->depth_bias
,
145 sizeof(src
->depth_bias
))) {
146 dest
->depth_bias
= src
->depth_bias
;
147 dest_mask
|= RADV_DYNAMIC_DEPTH_BIAS
;
151 if (copy_mask
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
152 if (memcmp(&dest
->blend_constants
, &src
->blend_constants
,
153 sizeof(src
->blend_constants
))) {
154 typed_memcpy(dest
->blend_constants
,
155 src
->blend_constants
, 4);
156 dest_mask
|= RADV_DYNAMIC_BLEND_CONSTANTS
;
160 if (copy_mask
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
161 if (memcmp(&dest
->depth_bounds
, &src
->depth_bounds
,
162 sizeof(src
->depth_bounds
))) {
163 dest
->depth_bounds
= src
->depth_bounds
;
164 dest_mask
|= RADV_DYNAMIC_DEPTH_BOUNDS
;
168 if (copy_mask
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
169 if (memcmp(&dest
->stencil_compare_mask
,
170 &src
->stencil_compare_mask
,
171 sizeof(src
->stencil_compare_mask
))) {
172 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
173 dest_mask
|= RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
177 if (copy_mask
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
178 if (memcmp(&dest
->stencil_write_mask
, &src
->stencil_write_mask
,
179 sizeof(src
->stencil_write_mask
))) {
180 dest
->stencil_write_mask
= src
->stencil_write_mask
;
181 dest_mask
|= RADV_DYNAMIC_STENCIL_WRITE_MASK
;
185 if (copy_mask
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
186 if (memcmp(&dest
->stencil_reference
, &src
->stencil_reference
,
187 sizeof(src
->stencil_reference
))) {
188 dest
->stencil_reference
= src
->stencil_reference
;
189 dest_mask
|= RADV_DYNAMIC_STENCIL_REFERENCE
;
193 if (copy_mask
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
194 if (memcmp(&dest
->discard_rectangle
.rectangles
, &src
->discard_rectangle
.rectangles
,
195 src
->discard_rectangle
.count
* sizeof(VkRect2D
))) {
196 typed_memcpy(dest
->discard_rectangle
.rectangles
,
197 src
->discard_rectangle
.rectangles
,
198 src
->discard_rectangle
.count
);
199 dest_mask
|= RADV_DYNAMIC_DISCARD_RECTANGLE
;
203 if (copy_mask
& RADV_DYNAMIC_SAMPLE_LOCATIONS
) {
204 if (dest
->sample_location
.per_pixel
!= src
->sample_location
.per_pixel
||
205 dest
->sample_location
.grid_size
.width
!= src
->sample_location
.grid_size
.width
||
206 dest
->sample_location
.grid_size
.height
!= src
->sample_location
.grid_size
.height
||
207 memcmp(&dest
->sample_location
.locations
,
208 &src
->sample_location
.locations
,
209 src
->sample_location
.count
* sizeof(VkSampleLocationEXT
))) {
210 dest
->sample_location
.per_pixel
= src
->sample_location
.per_pixel
;
211 dest
->sample_location
.grid_size
= src
->sample_location
.grid_size
;
212 typed_memcpy(dest
->sample_location
.locations
,
213 src
->sample_location
.locations
,
214 src
->sample_location
.count
);
215 dest_mask
|= RADV_DYNAMIC_SAMPLE_LOCATIONS
;
219 if (copy_mask
& RADV_DYNAMIC_LINE_STIPPLE
) {
220 if (memcmp(&dest
->line_stipple
, &src
->line_stipple
,
221 sizeof(src
->line_stipple
))) {
222 dest
->line_stipple
= src
->line_stipple
;
223 dest_mask
|= RADV_DYNAMIC_LINE_STIPPLE
;
227 cmd_buffer
->state
.dirty
|= dest_mask
;
231 radv_bind_streamout_state(struct radv_cmd_buffer
*cmd_buffer
,
232 struct radv_pipeline
*pipeline
)
234 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
235 struct radv_shader_info
*info
;
237 if (!pipeline
->streamout_shader
||
238 cmd_buffer
->device
->physical_device
->use_ngg_streamout
)
241 info
= &pipeline
->streamout_shader
->info
;
242 for (int i
= 0; i
< MAX_SO_BUFFERS
; i
++)
243 so
->stride_in_dw
[i
] = info
->so
.strides
[i
];
245 so
->enabled_stream_buffers_mask
= info
->so
.enabled_stream_buffers_mask
;
248 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
)
250 return cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
251 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
254 enum ring_type
radv_queue_family_to_ring(int f
) {
256 case RADV_QUEUE_GENERAL
:
258 case RADV_QUEUE_COMPUTE
:
260 case RADV_QUEUE_TRANSFER
:
263 unreachable("Unknown queue family");
267 static VkResult
radv_create_cmd_buffer(
268 struct radv_device
* device
,
269 struct radv_cmd_pool
* pool
,
270 VkCommandBufferLevel level
,
271 VkCommandBuffer
* pCommandBuffer
)
273 struct radv_cmd_buffer
*cmd_buffer
;
275 cmd_buffer
= vk_zalloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
276 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
277 if (cmd_buffer
== NULL
)
278 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
280 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
281 cmd_buffer
->device
= device
;
282 cmd_buffer
->pool
= pool
;
283 cmd_buffer
->level
= level
;
286 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
287 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
290 /* Init the pool_link so we can safely call list_del when we destroy
293 list_inithead(&cmd_buffer
->pool_link
);
294 cmd_buffer
->queue_family_index
= RADV_QUEUE_GENERAL
;
297 ring
= radv_queue_family_to_ring(cmd_buffer
->queue_family_index
);
299 cmd_buffer
->cs
= device
->ws
->cs_create(device
->ws
, ring
);
300 if (!cmd_buffer
->cs
) {
301 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
302 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
305 *pCommandBuffer
= radv_cmd_buffer_to_handle(cmd_buffer
);
307 list_inithead(&cmd_buffer
->upload
.list
);
313 radv_cmd_buffer_destroy(struct radv_cmd_buffer
*cmd_buffer
)
315 list_del(&cmd_buffer
->pool_link
);
317 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
318 &cmd_buffer
->upload
.list
, list
) {
319 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
324 if (cmd_buffer
->upload
.upload_bo
)
325 cmd_buffer
->device
->ws
->buffer_destroy(cmd_buffer
->upload
.upload_bo
);
326 cmd_buffer
->device
->ws
->cs_destroy(cmd_buffer
->cs
);
328 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++)
329 free(cmd_buffer
->descriptors
[i
].push_set
.set
.mapped_ptr
);
331 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
335 radv_reset_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
)
337 cmd_buffer
->device
->ws
->cs_reset(cmd_buffer
->cs
);
339 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
340 &cmd_buffer
->upload
.list
, list
) {
341 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
346 cmd_buffer
->push_constant_stages
= 0;
347 cmd_buffer
->scratch_size_per_wave_needed
= 0;
348 cmd_buffer
->scratch_waves_wanted
= 0;
349 cmd_buffer
->compute_scratch_size_per_wave_needed
= 0;
350 cmd_buffer
->compute_scratch_waves_wanted
= 0;
351 cmd_buffer
->esgs_ring_size_needed
= 0;
352 cmd_buffer
->gsvs_ring_size_needed
= 0;
353 cmd_buffer
->tess_rings_needed
= false;
354 cmd_buffer
->gds_needed
= false;
355 cmd_buffer
->gds_oa_needed
= false;
356 cmd_buffer
->sample_positions_needed
= false;
358 if (cmd_buffer
->upload
.upload_bo
)
359 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
360 cmd_buffer
->upload
.upload_bo
);
361 cmd_buffer
->upload
.offset
= 0;
363 cmd_buffer
->record_result
= VK_SUCCESS
;
365 memset(cmd_buffer
->vertex_bindings
, 0, sizeof(cmd_buffer
->vertex_bindings
));
367 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++) {
368 cmd_buffer
->descriptors
[i
].dirty
= 0;
369 cmd_buffer
->descriptors
[i
].valid
= 0;
370 cmd_buffer
->descriptors
[i
].push_dirty
= false;
373 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
374 cmd_buffer
->queue_family_index
== RADV_QUEUE_GENERAL
) {
375 unsigned num_db
= cmd_buffer
->device
->physical_device
->rad_info
.num_render_backends
;
376 unsigned fence_offset
, eop_bug_offset
;
379 radv_cmd_buffer_upload_alloc(cmd_buffer
, 8, 8, &fence_offset
,
382 cmd_buffer
->gfx9_fence_va
=
383 radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
384 cmd_buffer
->gfx9_fence_va
+= fence_offset
;
386 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
387 /* Allocate a buffer for the EOP bug on GFX9. */
388 radv_cmd_buffer_upload_alloc(cmd_buffer
, 16 * num_db
, 8,
389 &eop_bug_offset
, &fence_ptr
);
390 cmd_buffer
->gfx9_eop_bug_va
=
391 radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
392 cmd_buffer
->gfx9_eop_bug_va
+= eop_bug_offset
;
396 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_INITIAL
;
398 return cmd_buffer
->record_result
;
402 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer
*cmd_buffer
,
406 struct radeon_winsys_bo
*bo
;
407 struct radv_cmd_buffer_upload
*upload
;
408 struct radv_device
*device
= cmd_buffer
->device
;
410 new_size
= MAX2(min_needed
, 16 * 1024);
411 new_size
= MAX2(new_size
, 2 * cmd_buffer
->upload
.size
);
413 bo
= device
->ws
->buffer_create(device
->ws
,
416 RADEON_FLAG_CPU_ACCESS
|
417 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
419 RADV_BO_PRIORITY_UPLOAD_BUFFER
);
422 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
426 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
, bo
);
427 if (cmd_buffer
->upload
.upload_bo
) {
428 upload
= malloc(sizeof(*upload
));
431 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
432 device
->ws
->buffer_destroy(bo
);
436 memcpy(upload
, &cmd_buffer
->upload
, sizeof(*upload
));
437 list_add(&upload
->list
, &cmd_buffer
->upload
.list
);
440 cmd_buffer
->upload
.upload_bo
= bo
;
441 cmd_buffer
->upload
.size
= new_size
;
442 cmd_buffer
->upload
.offset
= 0;
443 cmd_buffer
->upload
.map
= device
->ws
->buffer_map(cmd_buffer
->upload
.upload_bo
);
445 if (!cmd_buffer
->upload
.map
) {
446 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
454 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
457 unsigned *out_offset
,
460 assert(util_is_power_of_two_nonzero(alignment
));
462 uint64_t offset
= align(cmd_buffer
->upload
.offset
, alignment
);
463 if (offset
+ size
> cmd_buffer
->upload
.size
) {
464 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer
, size
))
469 *out_offset
= offset
;
470 *ptr
= cmd_buffer
->upload
.map
+ offset
;
472 cmd_buffer
->upload
.offset
= offset
+ size
;
477 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
478 unsigned size
, unsigned alignment
,
479 const void *data
, unsigned *out_offset
)
483 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
, alignment
,
484 out_offset
, (void **)&ptr
))
488 memcpy(ptr
, data
, size
);
494 radv_emit_write_data_packet(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
495 unsigned count
, const uint32_t *data
)
497 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
499 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 4 + count
);
501 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
502 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
503 S_370_WR_CONFIRM(1) |
504 S_370_ENGINE_SEL(V_370_ME
));
506 radeon_emit(cs
, va
>> 32);
507 radeon_emit_array(cs
, data
, count
);
510 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
)
512 struct radv_device
*device
= cmd_buffer
->device
;
513 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
516 va
= radv_buffer_get_va(device
->trace_bo
);
517 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
)
520 ++cmd_buffer
->state
.trace_id
;
521 radv_emit_write_data_packet(cmd_buffer
, va
, 1,
522 &cmd_buffer
->state
.trace_id
);
524 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 2);
526 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
527 radeon_emit(cs
, AC_ENCODE_TRACE_POINT(cmd_buffer
->state
.trace_id
));
531 radv_cmd_buffer_after_draw(struct radv_cmd_buffer
*cmd_buffer
,
532 enum radv_cmd_flush_bits flags
)
534 if (unlikely(cmd_buffer
->device
->thread_trace_bo
)) {
535 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
536 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_THREAD_TRACE_MARKER
) | EVENT_INDEX(0));
539 if (cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_SYNC_SHADERS
) {
540 assert(flags
& (RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
541 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
));
543 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 4);
545 /* Force wait for graphics or compute engines to be idle. */
546 si_cs_emit_cache_flush(cmd_buffer
->cs
,
547 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
548 &cmd_buffer
->gfx9_fence_idx
,
549 cmd_buffer
->gfx9_fence_va
,
550 radv_cmd_buffer_uses_mec(cmd_buffer
),
551 flags
, cmd_buffer
->gfx9_eop_bug_va
);
554 if (unlikely(cmd_buffer
->device
->trace_bo
))
555 radv_cmd_buffer_trace_emit(cmd_buffer
);
559 radv_save_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
560 struct radv_pipeline
*pipeline
, enum ring_type ring
)
562 struct radv_device
*device
= cmd_buffer
->device
;
566 va
= radv_buffer_get_va(device
->trace_bo
);
576 assert(!"invalid ring type");
579 uint64_t pipeline_address
= (uintptr_t)pipeline
;
580 data
[0] = pipeline_address
;
581 data
[1] = pipeline_address
>> 32;
583 radv_emit_write_data_packet(cmd_buffer
, va
, 2, data
);
586 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
587 VkPipelineBindPoint bind_point
,
588 struct radv_descriptor_set
*set
,
591 struct radv_descriptor_state
*descriptors_state
=
592 radv_get_descriptors_state(cmd_buffer
, bind_point
);
594 descriptors_state
->sets
[idx
] = set
;
596 descriptors_state
->valid
|= (1u << idx
); /* active descriptors */
597 descriptors_state
->dirty
|= (1u << idx
);
601 radv_save_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
602 VkPipelineBindPoint bind_point
)
604 struct radv_descriptor_state
*descriptors_state
=
605 radv_get_descriptors_state(cmd_buffer
, bind_point
);
606 struct radv_device
*device
= cmd_buffer
->device
;
607 uint32_t data
[MAX_SETS
* 2] = {};
610 va
= radv_buffer_get_va(device
->trace_bo
) + 24;
612 for_each_bit(i
, descriptors_state
->valid
) {
613 struct radv_descriptor_set
*set
= descriptors_state
->sets
[i
];
614 data
[i
* 2] = (uint64_t)(uintptr_t)set
;
615 data
[i
* 2 + 1] = (uint64_t)(uintptr_t)set
>> 32;
618 radv_emit_write_data_packet(cmd_buffer
, va
, MAX_SETS
* 2, data
);
621 struct radv_userdata_info
*
622 radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
623 gl_shader_stage stage
,
626 struct radv_shader_variant
*shader
= radv_get_shader(pipeline
, stage
);
627 return &shader
->info
.user_sgprs_locs
.shader_data
[idx
];
631 radv_emit_userdata_address(struct radv_cmd_buffer
*cmd_buffer
,
632 struct radv_pipeline
*pipeline
,
633 gl_shader_stage stage
,
634 int idx
, uint64_t va
)
636 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
637 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
638 if (loc
->sgpr_idx
== -1)
641 assert(loc
->num_sgprs
== 1);
643 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
644 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
648 radv_emit_descriptor_pointers(struct radv_cmd_buffer
*cmd_buffer
,
649 struct radv_pipeline
*pipeline
,
650 struct radv_descriptor_state
*descriptors_state
,
651 gl_shader_stage stage
)
653 struct radv_device
*device
= cmd_buffer
->device
;
654 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
655 uint32_t sh_base
= pipeline
->user_data_0
[stage
];
656 struct radv_userdata_locations
*locs
=
657 &pipeline
->shaders
[stage
]->info
.user_sgprs_locs
;
658 unsigned mask
= locs
->descriptor_sets_enabled
;
660 mask
&= descriptors_state
->dirty
& descriptors_state
->valid
;
665 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
667 struct radv_userdata_info
*loc
= &locs
->descriptor_sets
[start
];
668 unsigned sh_offset
= sh_base
+ loc
->sgpr_idx
* 4;
670 radv_emit_shader_pointer_head(cs
, sh_offset
, count
, true);
671 for (int i
= 0; i
< count
; i
++) {
672 struct radv_descriptor_set
*set
=
673 descriptors_state
->sets
[start
+ i
];
675 radv_emit_shader_pointer_body(device
, cs
, set
->va
, true);
681 * Convert the user sample locations to hardware sample locations (the values
682 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
685 radv_convert_user_sample_locs(struct radv_sample_locations_state
*state
,
686 uint32_t x
, uint32_t y
, VkOffset2D
*sample_locs
)
688 uint32_t x_offset
= x
% state
->grid_size
.width
;
689 uint32_t y_offset
= y
% state
->grid_size
.height
;
690 uint32_t num_samples
= (uint32_t)state
->per_pixel
;
691 VkSampleLocationEXT
*user_locs
;
692 uint32_t pixel_offset
;
694 pixel_offset
= (x_offset
+ y_offset
* state
->grid_size
.width
) * num_samples
;
696 assert(pixel_offset
<= MAX_SAMPLE_LOCATIONS
);
697 user_locs
= &state
->locations
[pixel_offset
];
699 for (uint32_t i
= 0; i
< num_samples
; i
++) {
700 float shifted_pos_x
= user_locs
[i
].x
- 0.5;
701 float shifted_pos_y
= user_locs
[i
].y
- 0.5;
703 int32_t scaled_pos_x
= floor(shifted_pos_x
* 16);
704 int32_t scaled_pos_y
= floor(shifted_pos_y
* 16);
706 sample_locs
[i
].x
= CLAMP(scaled_pos_x
, -8, 7);
707 sample_locs
[i
].y
= CLAMP(scaled_pos_y
, -8, 7);
712 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
716 radv_compute_sample_locs_pixel(uint32_t num_samples
, VkOffset2D
*sample_locs
,
717 uint32_t *sample_locs_pixel
)
719 for (uint32_t i
= 0; i
< num_samples
; i
++) {
720 uint32_t sample_reg_idx
= i
/ 4;
721 uint32_t sample_loc_idx
= i
% 4;
722 int32_t pos_x
= sample_locs
[i
].x
;
723 int32_t pos_y
= sample_locs
[i
].y
;
725 uint32_t shift_x
= 8 * sample_loc_idx
;
726 uint32_t shift_y
= shift_x
+ 4;
728 sample_locs_pixel
[sample_reg_idx
] |= (pos_x
& 0xf) << shift_x
;
729 sample_locs_pixel
[sample_reg_idx
] |= (pos_y
& 0xf) << shift_y
;
734 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
738 radv_compute_centroid_priority(struct radv_cmd_buffer
*cmd_buffer
,
739 VkOffset2D
*sample_locs
,
740 uint32_t num_samples
)
742 uint32_t centroid_priorities
[num_samples
];
743 uint32_t sample_mask
= num_samples
- 1;
744 uint32_t distances
[num_samples
];
745 uint64_t centroid_priority
= 0;
747 /* Compute the distances from center for each sample. */
748 for (int i
= 0; i
< num_samples
; i
++) {
749 distances
[i
] = (sample_locs
[i
].x
* sample_locs
[i
].x
) +
750 (sample_locs
[i
].y
* sample_locs
[i
].y
);
753 /* Compute the centroid priorities by looking at the distances array. */
754 for (int i
= 0; i
< num_samples
; i
++) {
755 uint32_t min_idx
= 0;
757 for (int j
= 1; j
< num_samples
; j
++) {
758 if (distances
[j
] < distances
[min_idx
])
762 centroid_priorities
[i
] = min_idx
;
763 distances
[min_idx
] = 0xffffffff;
766 /* Compute the final centroid priority. */
767 for (int i
= 0; i
< 8; i
++) {
769 centroid_priorities
[i
& sample_mask
] << (i
* 4);
772 return centroid_priority
<< 32 | centroid_priority
;
776 * Emit the sample locations that are specified with VK_EXT_sample_locations.
779 radv_emit_sample_locations(struct radv_cmd_buffer
*cmd_buffer
)
781 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
782 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
783 struct radv_sample_locations_state
*sample_location
=
784 &cmd_buffer
->state
.dynamic
.sample_location
;
785 uint32_t num_samples
= (uint32_t)sample_location
->per_pixel
;
786 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
787 uint32_t sample_locs_pixel
[4][2] = {};
788 VkOffset2D sample_locs
[4][8]; /* 8 is the max. sample count supported */
789 uint32_t max_sample_dist
= 0;
790 uint64_t centroid_priority
;
792 if (!cmd_buffer
->state
.dynamic
.sample_location
.count
)
795 /* Convert the user sample locations to hardware sample locations. */
796 radv_convert_user_sample_locs(sample_location
, 0, 0, sample_locs
[0]);
797 radv_convert_user_sample_locs(sample_location
, 1, 0, sample_locs
[1]);
798 radv_convert_user_sample_locs(sample_location
, 0, 1, sample_locs
[2]);
799 radv_convert_user_sample_locs(sample_location
, 1, 1, sample_locs
[3]);
801 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
802 for (uint32_t i
= 0; i
< 4; i
++) {
803 radv_compute_sample_locs_pixel(num_samples
, sample_locs
[i
],
804 sample_locs_pixel
[i
]);
807 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
809 radv_compute_centroid_priority(cmd_buffer
, sample_locs
[0],
812 /* Compute the maximum sample distance from the specified locations. */
813 for (uint32_t i
= 0; i
< num_samples
; i
++) {
814 VkOffset2D offset
= sample_locs
[0][i
];
815 max_sample_dist
= MAX2(max_sample_dist
,
816 MAX2(abs(offset
.x
), abs(offset
.y
)));
819 /* Emit the specified user sample locations. */
820 switch (num_samples
) {
823 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_pixel
[0][0]);
824 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_pixel
[1][0]);
825 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_pixel
[2][0]);
826 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_pixel
[3][0]);
829 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_pixel
[0][0]);
830 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_pixel
[1][0]);
831 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_pixel
[2][0]);
832 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_pixel
[3][0]);
833 radeon_set_context_reg(cs
, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1
, sample_locs_pixel
[0][1]);
834 radeon_set_context_reg(cs
, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1
, sample_locs_pixel
[1][1]);
835 radeon_set_context_reg(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1
, sample_locs_pixel
[2][1]);
836 radeon_set_context_reg(cs
, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1
, sample_locs_pixel
[3][1]);
839 unreachable("invalid number of samples");
842 /* Emit the maximum sample distance and the centroid priority. */
843 uint32_t pa_sc_aa_config
= ms
->pa_sc_aa_config
;
845 pa_sc_aa_config
&= C_028BE0_MAX_SAMPLE_DIST
;
846 pa_sc_aa_config
|= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist
);
848 radeon_set_context_reg_seq(cs
, R_028BE0_PA_SC_AA_CONFIG
, 1);
849 radeon_emit(cs
, pa_sc_aa_config
);
851 radeon_set_context_reg_seq(cs
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
852 radeon_emit(cs
, centroid_priority
);
853 radeon_emit(cs
, centroid_priority
>> 32);
855 /* GFX9: Flush DFSM when the AA mode changes. */
856 if (cmd_buffer
->device
->dfsm_allowed
) {
857 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
858 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
861 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
865 radv_emit_inline_push_consts(struct radv_cmd_buffer
*cmd_buffer
,
866 struct radv_pipeline
*pipeline
,
867 gl_shader_stage stage
,
868 int idx
, int count
, uint32_t *values
)
870 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
871 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
872 if (loc
->sgpr_idx
== -1)
875 assert(loc
->num_sgprs
== count
);
877 radeon_set_sh_reg_seq(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, count
);
878 radeon_emit_array(cmd_buffer
->cs
, values
, count
);
882 radv_update_multisample_state(struct radv_cmd_buffer
*cmd_buffer
,
883 struct radv_pipeline
*pipeline
)
885 int num_samples
= pipeline
->graphics
.ms
.num_samples
;
886 struct radv_pipeline
*old_pipeline
= cmd_buffer
->state
.emitted_pipeline
;
888 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.needs_sample_positions
)
889 cmd_buffer
->sample_positions_needed
= true;
891 if (old_pipeline
&& num_samples
== old_pipeline
->graphics
.ms
.num_samples
)
894 radv_emit_default_sample_locations(cmd_buffer
->cs
, num_samples
);
896 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
900 radv_update_binning_state(struct radv_cmd_buffer
*cmd_buffer
,
901 struct radv_pipeline
*pipeline
)
903 const struct radv_pipeline
*old_pipeline
= cmd_buffer
->state
.emitted_pipeline
;
906 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX9
)
910 old_pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
== pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
&&
911 old_pipeline
->graphics
.binning
.db_dfsm_control
== pipeline
->graphics
.binning
.db_dfsm_control
)
914 bool binning_flush
= false;
915 if (cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_VEGA12
||
916 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_VEGA20
||
917 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_RAVEN2
||
918 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
919 binning_flush
= !old_pipeline
||
920 G_028C44_BINNING_MODE(old_pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
) !=
921 G_028C44_BINNING_MODE(pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
);
924 radeon_set_context_reg(cmd_buffer
->cs
, R_028C44_PA_SC_BINNER_CNTL_0
,
925 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
|
926 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush
));
928 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
929 radeon_set_context_reg(cmd_buffer
->cs
, R_028038_DB_DFSM_CONTROL
,
930 pipeline
->graphics
.binning
.db_dfsm_control
);
932 radeon_set_context_reg(cmd_buffer
->cs
, R_028060_DB_DFSM_CONTROL
,
933 pipeline
->graphics
.binning
.db_dfsm_control
);
936 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
941 radv_emit_shader_prefetch(struct radv_cmd_buffer
*cmd_buffer
,
942 struct radv_shader_variant
*shader
)
949 va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
951 si_cp_dma_prefetch(cmd_buffer
, va
, shader
->code_size
);
955 radv_emit_prefetch_L2(struct radv_cmd_buffer
*cmd_buffer
,
956 struct radv_pipeline
*pipeline
,
957 bool vertex_stage_only
)
959 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
960 uint32_t mask
= state
->prefetch_L2_mask
;
962 if (vertex_stage_only
) {
963 /* Fast prefetch path for starting draws as soon as possible.
965 mask
= state
->prefetch_L2_mask
& (RADV_PREFETCH_VS
|
966 RADV_PREFETCH_VBO_DESCRIPTORS
);
969 if (mask
& RADV_PREFETCH_VS
)
970 radv_emit_shader_prefetch(cmd_buffer
,
971 pipeline
->shaders
[MESA_SHADER_VERTEX
]);
973 if (mask
& RADV_PREFETCH_VBO_DESCRIPTORS
)
974 si_cp_dma_prefetch(cmd_buffer
, state
->vb_va
, state
->vb_size
);
976 if (mask
& RADV_PREFETCH_TCS
)
977 radv_emit_shader_prefetch(cmd_buffer
,
978 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]);
980 if (mask
& RADV_PREFETCH_TES
)
981 radv_emit_shader_prefetch(cmd_buffer
,
982 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]);
984 if (mask
& RADV_PREFETCH_GS
) {
985 radv_emit_shader_prefetch(cmd_buffer
,
986 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]);
987 if (radv_pipeline_has_gs_copy_shader(pipeline
))
988 radv_emit_shader_prefetch(cmd_buffer
, pipeline
->gs_copy_shader
);
991 if (mask
& RADV_PREFETCH_PS
)
992 radv_emit_shader_prefetch(cmd_buffer
,
993 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
995 state
->prefetch_L2_mask
&= ~mask
;
999 radv_emit_rbplus_state(struct radv_cmd_buffer
*cmd_buffer
)
1001 if (!cmd_buffer
->device
->physical_device
->rad_info
.rbplus_allowed
)
1004 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1005 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1007 unsigned sx_ps_downconvert
= 0;
1008 unsigned sx_blend_opt_epsilon
= 0;
1009 unsigned sx_blend_opt_control
= 0;
1011 if (!cmd_buffer
->state
.attachments
|| !subpass
)
1014 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1015 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
1016 /* We don't set the DISABLE bits, because the HW can't have holes,
1017 * so the SPI color format is set to 32-bit 1-component. */
1018 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
1022 int idx
= subpass
->color_attachments
[i
].attachment
;
1023 struct radv_color_buffer_info
*cb
= &cmd_buffer
->state
.attachments
[idx
].cb
;
1025 unsigned format
= G_028C70_FORMAT(cb
->cb_color_info
);
1026 unsigned swap
= G_028C70_COMP_SWAP(cb
->cb_color_info
);
1027 uint32_t spi_format
= (pipeline
->graphics
.col_format
>> (i
* 4)) & 0xf;
1028 uint32_t colormask
= (pipeline
->graphics
.cb_target_mask
>> (i
* 4)) & 0xf;
1030 bool has_alpha
, has_rgb
;
1032 /* Set if RGB and A are present. */
1033 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(cb
->cb_color_attrib
);
1035 if (format
== V_028C70_COLOR_8
||
1036 format
== V_028C70_COLOR_16
||
1037 format
== V_028C70_COLOR_32
)
1038 has_rgb
= !has_alpha
;
1042 /* Check the colormask and export format. */
1043 if (!(colormask
& 0x7))
1045 if (!(colormask
& 0x8))
1048 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
1053 /* Disable value checking for disabled channels. */
1055 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
1057 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
1059 /* Enable down-conversion for 32bpp and smaller formats. */
1061 case V_028C70_COLOR_8
:
1062 case V_028C70_COLOR_8_8
:
1063 case V_028C70_COLOR_8_8_8_8
:
1064 /* For 1 and 2-channel formats, use the superset thereof. */
1065 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
1066 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
1067 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
1068 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
1069 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
1073 case V_028C70_COLOR_5_6_5
:
1074 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1075 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
1076 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
1080 case V_028C70_COLOR_1_5_5_5
:
1081 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1082 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
1083 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
1087 case V_028C70_COLOR_4_4_4_4
:
1088 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1089 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
1090 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
1094 case V_028C70_COLOR_32
:
1095 if (swap
== V_028C70_SWAP_STD
&&
1096 spi_format
== V_028714_SPI_SHADER_32_R
)
1097 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
1098 else if (swap
== V_028C70_SWAP_ALT_REV
&&
1099 spi_format
== V_028714_SPI_SHADER_32_AR
)
1100 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
1103 case V_028C70_COLOR_16
:
1104 case V_028C70_COLOR_16_16
:
1105 /* For 1-channel formats, use the superset thereof. */
1106 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
1107 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
1108 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
1109 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
1110 if (swap
== V_028C70_SWAP_STD
||
1111 swap
== V_028C70_SWAP_STD_REV
)
1112 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
1114 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
1118 case V_028C70_COLOR_10_11_11
:
1119 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1120 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
1121 sx_blend_opt_epsilon
|= V_028758_11BIT_FORMAT
<< (i
* 4);
1125 case V_028C70_COLOR_2_10_10_10
:
1126 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1127 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
1128 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
1134 /* Do not set the DISABLE bits for the unused attachments, as that
1135 * breaks dual source blending in SkQP and does not seem to improve
1138 if (sx_ps_downconvert
== cmd_buffer
->state
.last_sx_ps_downconvert
&&
1139 sx_blend_opt_epsilon
== cmd_buffer
->state
.last_sx_blend_opt_epsilon
&&
1140 sx_blend_opt_control
== cmd_buffer
->state
.last_sx_blend_opt_control
)
1143 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
1144 radeon_emit(cmd_buffer
->cs
, sx_ps_downconvert
);
1145 radeon_emit(cmd_buffer
->cs
, sx_blend_opt_epsilon
);
1146 radeon_emit(cmd_buffer
->cs
, sx_blend_opt_control
);
1148 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1150 cmd_buffer
->state
.last_sx_ps_downconvert
= sx_ps_downconvert
;
1151 cmd_buffer
->state
.last_sx_blend_opt_epsilon
= sx_blend_opt_epsilon
;
1152 cmd_buffer
->state
.last_sx_blend_opt_control
= sx_blend_opt_control
;
1156 radv_emit_batch_break_on_new_ps(struct radv_cmd_buffer
*cmd_buffer
)
1158 if (!cmd_buffer
->device
->pbb_allowed
)
1161 struct radv_binning_settings settings
=
1162 radv_get_binning_settings(cmd_buffer
->device
->physical_device
);
1163 bool break_for_new_ps
=
1164 (!cmd_buffer
->state
.emitted_pipeline
||
1165 cmd_buffer
->state
.emitted_pipeline
->shaders
[MESA_SHADER_FRAGMENT
] !=
1166 cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_FRAGMENT
]) &&
1167 (settings
.context_states_per_bin
> 1 ||
1168 settings
.persistent_states_per_bin
> 1);
1169 bool break_for_new_cb_target_mask
=
1170 (!cmd_buffer
->state
.emitted_pipeline
||
1171 cmd_buffer
->state
.emitted_pipeline
->graphics
.cb_target_mask
!=
1172 cmd_buffer
->state
.pipeline
->graphics
.cb_target_mask
) &&
1173 settings
.context_states_per_bin
> 1;
1175 if (!break_for_new_ps
&& !break_for_new_cb_target_mask
)
1178 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1179 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
1183 radv_emit_graphics_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
1185 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1187 if (!pipeline
|| cmd_buffer
->state
.emitted_pipeline
== pipeline
)
1190 radv_update_multisample_state(cmd_buffer
, pipeline
);
1191 radv_update_binning_state(cmd_buffer
, pipeline
);
1193 cmd_buffer
->scratch_size_per_wave_needed
= MAX2(cmd_buffer
->scratch_size_per_wave_needed
,
1194 pipeline
->scratch_bytes_per_wave
);
1195 cmd_buffer
->scratch_waves_wanted
= MAX2(cmd_buffer
->scratch_waves_wanted
,
1196 pipeline
->max_waves
);
1198 if (!cmd_buffer
->state
.emitted_pipeline
||
1199 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
!=
1200 pipeline
->graphics
.can_use_guardband
)
1201 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
1203 radeon_emit_array(cmd_buffer
->cs
, pipeline
->cs
.buf
, pipeline
->cs
.cdw
);
1205 if (!cmd_buffer
->state
.emitted_pipeline
||
1206 cmd_buffer
->state
.emitted_pipeline
->ctx_cs
.cdw
!= pipeline
->ctx_cs
.cdw
||
1207 cmd_buffer
->state
.emitted_pipeline
->ctx_cs_hash
!= pipeline
->ctx_cs_hash
||
1208 memcmp(cmd_buffer
->state
.emitted_pipeline
->ctx_cs
.buf
,
1209 pipeline
->ctx_cs
.buf
, pipeline
->ctx_cs
.cdw
* 4)) {
1210 radeon_emit_array(cmd_buffer
->cs
, pipeline
->ctx_cs
.buf
, pipeline
->ctx_cs
.cdw
);
1211 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1214 radv_emit_batch_break_on_new_ps(cmd_buffer
);
1216 for (unsigned i
= 0; i
< MESA_SHADER_COMPUTE
; i
++) {
1217 if (!pipeline
->shaders
[i
])
1220 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
1221 pipeline
->shaders
[i
]->bo
);
1224 if (radv_pipeline_has_gs_copy_shader(pipeline
))
1225 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
1226 pipeline
->gs_copy_shader
->bo
);
1228 if (unlikely(cmd_buffer
->device
->trace_bo
))
1229 radv_save_pipeline(cmd_buffer
, pipeline
, RING_GFX
);
1231 cmd_buffer
->state
.emitted_pipeline
= pipeline
;
1233 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_PIPELINE
;
1237 radv_emit_viewport(struct radv_cmd_buffer
*cmd_buffer
)
1239 si_write_viewport(cmd_buffer
->cs
, 0, cmd_buffer
->state
.dynamic
.viewport
.count
,
1240 cmd_buffer
->state
.dynamic
.viewport
.viewports
);
1244 radv_emit_scissor(struct radv_cmd_buffer
*cmd_buffer
)
1246 uint32_t count
= cmd_buffer
->state
.dynamic
.scissor
.count
;
1248 si_write_scissors(cmd_buffer
->cs
, 0, count
,
1249 cmd_buffer
->state
.dynamic
.scissor
.scissors
,
1250 cmd_buffer
->state
.dynamic
.viewport
.viewports
,
1251 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
);
1253 cmd_buffer
->state
.context_roll_without_scissor_emitted
= false;
1257 radv_emit_discard_rectangle(struct radv_cmd_buffer
*cmd_buffer
)
1259 if (!cmd_buffer
->state
.dynamic
.discard_rectangle
.count
)
1262 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028210_PA_SC_CLIPRECT_0_TL
,
1263 cmd_buffer
->state
.dynamic
.discard_rectangle
.count
* 2);
1264 for (unsigned i
= 0; i
< cmd_buffer
->state
.dynamic
.discard_rectangle
.count
; ++i
) {
1265 VkRect2D rect
= cmd_buffer
->state
.dynamic
.discard_rectangle
.rectangles
[i
];
1266 radeon_emit(cmd_buffer
->cs
, S_028210_TL_X(rect
.offset
.x
) | S_028210_TL_Y(rect
.offset
.y
));
1267 radeon_emit(cmd_buffer
->cs
, S_028214_BR_X(rect
.offset
.x
+ rect
.extent
.width
) |
1268 S_028214_BR_Y(rect
.offset
.y
+ rect
.extent
.height
));
1273 radv_emit_line_width(struct radv_cmd_buffer
*cmd_buffer
)
1275 unsigned width
= cmd_buffer
->state
.dynamic
.line_width
* 8;
1277 radeon_set_context_reg(cmd_buffer
->cs
, R_028A08_PA_SU_LINE_CNTL
,
1278 S_028A08_WIDTH(CLAMP(width
, 0, 0xFFF)));
1282 radv_emit_blend_constants(struct radv_cmd_buffer
*cmd_buffer
)
1284 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1286 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028414_CB_BLEND_RED
, 4);
1287 radeon_emit_array(cmd_buffer
->cs
, (uint32_t *)d
->blend_constants
, 4);
1291 radv_emit_stencil(struct radv_cmd_buffer
*cmd_buffer
)
1293 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1295 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1296 R_028430_DB_STENCILREFMASK
, 2);
1297 radeon_emit(cmd_buffer
->cs
,
1298 S_028430_STENCILTESTVAL(d
->stencil_reference
.front
) |
1299 S_028430_STENCILMASK(d
->stencil_compare_mask
.front
) |
1300 S_028430_STENCILWRITEMASK(d
->stencil_write_mask
.front
) |
1301 S_028430_STENCILOPVAL(1));
1302 radeon_emit(cmd_buffer
->cs
,
1303 S_028434_STENCILTESTVAL_BF(d
->stencil_reference
.back
) |
1304 S_028434_STENCILMASK_BF(d
->stencil_compare_mask
.back
) |
1305 S_028434_STENCILWRITEMASK_BF(d
->stencil_write_mask
.back
) |
1306 S_028434_STENCILOPVAL_BF(1));
1310 radv_emit_depth_bounds(struct radv_cmd_buffer
*cmd_buffer
)
1312 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1314 radeon_set_context_reg(cmd_buffer
->cs
, R_028020_DB_DEPTH_BOUNDS_MIN
,
1315 fui(d
->depth_bounds
.min
));
1316 radeon_set_context_reg(cmd_buffer
->cs
, R_028024_DB_DEPTH_BOUNDS_MAX
,
1317 fui(d
->depth_bounds
.max
));
1321 radv_emit_depth_bias(struct radv_cmd_buffer
*cmd_buffer
)
1323 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1324 unsigned slope
= fui(d
->depth_bias
.slope
* 16.0f
);
1325 unsigned bias
= fui(d
->depth_bias
.bias
* cmd_buffer
->state
.offset_scale
);
1328 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1329 R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, 5);
1330 radeon_emit(cmd_buffer
->cs
, fui(d
->depth_bias
.clamp
)); /* CLAMP */
1331 radeon_emit(cmd_buffer
->cs
, slope
); /* FRONT SCALE */
1332 radeon_emit(cmd_buffer
->cs
, bias
); /* FRONT OFFSET */
1333 radeon_emit(cmd_buffer
->cs
, slope
); /* BACK SCALE */
1334 radeon_emit(cmd_buffer
->cs
, bias
); /* BACK OFFSET */
1338 radv_emit_line_stipple(struct radv_cmd_buffer
*cmd_buffer
)
1340 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1341 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1342 uint32_t auto_reset_cntl
= 1;
1344 if (pipeline
->graphics
.topology
== VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
)
1345 auto_reset_cntl
= 2;
1347 radeon_set_context_reg(cmd_buffer
->cs
, R_028A0C_PA_SC_LINE_STIPPLE
,
1348 S_028A0C_LINE_PATTERN(d
->line_stipple
.pattern
) |
1349 S_028A0C_REPEAT_COUNT(d
->line_stipple
.factor
- 1) |
1350 S_028A0C_AUTO_RESET_CNTL(auto_reset_cntl
));
1354 radv_emit_fb_color_state(struct radv_cmd_buffer
*cmd_buffer
,
1356 struct radv_color_buffer_info
*cb
,
1357 struct radv_image_view
*iview
,
1358 VkImageLayout layout
,
1359 bool in_render_loop
)
1361 bool is_vi
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX8
;
1362 uint32_t cb_color_info
= cb
->cb_color_info
;
1363 struct radv_image
*image
= iview
->image
;
1365 if (!radv_layout_dcc_compressed(cmd_buffer
->device
, image
, layout
, in_render_loop
,
1366 radv_image_queue_family_mask(image
,
1367 cmd_buffer
->queue_family_index
,
1368 cmd_buffer
->queue_family_index
))) {
1369 cb_color_info
&= C_028C70_DCC_ENABLE
;
1372 if (radv_image_is_tc_compat_cmask(image
) &&
1373 (radv_is_fmask_decompress_pipeline(cmd_buffer
) ||
1374 radv_is_dcc_decompress_pipeline(cmd_buffer
))) {
1375 /* If this bit is set, the FMASK decompression operation
1376 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1378 cb_color_info
&= C_028C70_FMASK_COMPRESS_1FRAG_ONLY
;
1381 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
1382 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1383 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1384 radeon_emit(cmd_buffer
->cs
, 0);
1385 radeon_emit(cmd_buffer
->cs
, 0);
1386 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1387 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1388 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1389 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1390 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1391 radeon_emit(cmd_buffer
->cs
, 0);
1392 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1393 radeon_emit(cmd_buffer
->cs
, 0);
1395 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, 1);
1396 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
);
1398 radeon_set_context_reg(cmd_buffer
->cs
, R_028E40_CB_COLOR0_BASE_EXT
+ index
* 4,
1399 cb
->cb_color_base
>> 32);
1400 radeon_set_context_reg(cmd_buffer
->cs
, R_028E60_CB_COLOR0_CMASK_BASE_EXT
+ index
* 4,
1401 cb
->cb_color_cmask
>> 32);
1402 radeon_set_context_reg(cmd_buffer
->cs
, R_028E80_CB_COLOR0_FMASK_BASE_EXT
+ index
* 4,
1403 cb
->cb_color_fmask
>> 32);
1404 radeon_set_context_reg(cmd_buffer
->cs
, R_028EA0_CB_COLOR0_DCC_BASE_EXT
+ index
* 4,
1405 cb
->cb_dcc_base
>> 32);
1406 radeon_set_context_reg(cmd_buffer
->cs
, R_028EC0_CB_COLOR0_ATTRIB2
+ index
* 4,
1407 cb
->cb_color_attrib2
);
1408 radeon_set_context_reg(cmd_buffer
->cs
, R_028EE0_CB_COLOR0_ATTRIB3
+ index
* 4,
1409 cb
->cb_color_attrib3
);
1410 } else if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
1411 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1412 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1413 radeon_emit(cmd_buffer
->cs
, S_028C64_BASE_256B(cb
->cb_color_base
>> 32));
1414 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib2
);
1415 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1416 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1417 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1418 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1419 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1420 radeon_emit(cmd_buffer
->cs
, S_028C80_BASE_256B(cb
->cb_color_cmask
>> 32));
1421 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1422 radeon_emit(cmd_buffer
->cs
, S_028C88_BASE_256B(cb
->cb_color_fmask
>> 32));
1424 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, 2);
1425 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
);
1426 radeon_emit(cmd_buffer
->cs
, S_028C98_BASE_256B(cb
->cb_dcc_base
>> 32));
1428 radeon_set_context_reg(cmd_buffer
->cs
, R_0287A0_CB_MRT0_EPITCH
+ index
* 4,
1431 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1432 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1433 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_pitch
);
1434 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_slice
);
1435 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1436 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1437 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1438 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1439 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1440 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask_slice
);
1441 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1442 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask_slice
);
1444 if (is_vi
) { /* DCC BASE */
1445 radeon_set_context_reg(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, cb
->cb_dcc_base
);
1449 if (radv_dcc_enabled(image
, iview
->base_mip
)) {
1450 /* Drawing with DCC enabled also compresses colorbuffers. */
1451 VkImageSubresourceRange range
= {
1452 .aspectMask
= iview
->aspect_mask
,
1453 .baseMipLevel
= iview
->base_mip
,
1454 .levelCount
= iview
->level_count
,
1455 .baseArrayLayer
= iview
->base_layer
,
1456 .layerCount
= iview
->layer_count
,
1459 radv_update_dcc_metadata(cmd_buffer
, image
, &range
, true);
1464 radv_update_zrange_precision(struct radv_cmd_buffer
*cmd_buffer
,
1465 struct radv_ds_buffer_info
*ds
,
1466 const struct radv_image_view
*iview
,
1467 VkImageLayout layout
,
1468 bool in_render_loop
, bool requires_cond_exec
)
1470 const struct radv_image
*image
= iview
->image
;
1471 uint32_t db_z_info
= ds
->db_z_info
;
1472 uint32_t db_z_info_reg
;
1474 if (!cmd_buffer
->device
->physical_device
->rad_info
.has_tc_compat_zrange_bug
||
1475 !radv_image_is_tc_compat_htile(image
))
1478 if (!radv_layout_has_htile(image
, layout
, in_render_loop
,
1479 radv_image_queue_family_mask(image
,
1480 cmd_buffer
->queue_family_index
,
1481 cmd_buffer
->queue_family_index
))) {
1482 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1485 db_z_info
&= C_028040_ZRANGE_PRECISION
;
1487 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
1488 db_z_info_reg
= R_028038_DB_Z_INFO
;
1490 db_z_info_reg
= R_028040_DB_Z_INFO
;
1493 /* When we don't know the last fast clear value we need to emit a
1494 * conditional packet that will eventually skip the following
1495 * SET_CONTEXT_REG packet.
1497 if (requires_cond_exec
) {
1498 uint64_t va
= radv_get_tc_compat_zrange_va(image
, iview
->base_mip
);
1500 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COND_EXEC
, 3, 0));
1501 radeon_emit(cmd_buffer
->cs
, va
);
1502 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1503 radeon_emit(cmd_buffer
->cs
, 0);
1504 radeon_emit(cmd_buffer
->cs
, 3); /* SET_CONTEXT_REG size */
1507 radeon_set_context_reg(cmd_buffer
->cs
, db_z_info_reg
, db_z_info
);
1511 radv_emit_fb_ds_state(struct radv_cmd_buffer
*cmd_buffer
,
1512 struct radv_ds_buffer_info
*ds
,
1513 struct radv_image_view
*iview
,
1514 VkImageLayout layout
,
1515 bool in_render_loop
)
1517 const struct radv_image
*image
= iview
->image
;
1518 uint32_t db_z_info
= ds
->db_z_info
;
1519 uint32_t db_stencil_info
= ds
->db_stencil_info
;
1521 if (!radv_layout_has_htile(image
, layout
, in_render_loop
,
1522 radv_image_queue_family_mask(image
,
1523 cmd_buffer
->queue_family_index
,
1524 cmd_buffer
->queue_family_index
))) {
1525 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1526 db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
1529 radeon_set_context_reg(cmd_buffer
->cs
, R_028008_DB_DEPTH_VIEW
, ds
->db_depth_view
);
1530 radeon_set_context_reg(cmd_buffer
->cs
, R_028ABC_DB_HTILE_SURFACE
, ds
->db_htile_surface
);
1532 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
1533 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
1534 radeon_set_context_reg(cmd_buffer
->cs
, R_02801C_DB_DEPTH_SIZE_XY
, ds
->db_depth_size
);
1536 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 7);
1537 radeon_emit(cmd_buffer
->cs
, S_02803C_RESOURCE_LEVEL(1));
1538 radeon_emit(cmd_buffer
->cs
, db_z_info
);
1539 radeon_emit(cmd_buffer
->cs
, db_stencil_info
);
1540 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
);
1541 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
);
1542 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
);
1543 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
);
1545 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028068_DB_Z_READ_BASE_HI
, 5);
1546 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
>> 32);
1547 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
>> 32);
1548 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
>> 32);
1549 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
>> 32);
1550 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
>> 32);
1551 } else if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
1552 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
1553 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
);
1554 radeon_emit(cmd_buffer
->cs
, S_028018_BASE_HI(ds
->db_htile_data_base
>> 32));
1555 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
);
1557 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 10);
1558 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* DB_Z_INFO */
1559 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* DB_STENCIL_INFO */
1560 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* DB_Z_READ_BASE */
1561 radeon_emit(cmd_buffer
->cs
, S_028044_BASE_HI(ds
->db_z_read_base
>> 32)); /* DB_Z_READ_BASE_HI */
1562 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* DB_STENCIL_READ_BASE */
1563 radeon_emit(cmd_buffer
->cs
, S_02804C_BASE_HI(ds
->db_stencil_read_base
>> 32)); /* DB_STENCIL_READ_BASE_HI */
1564 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* DB_Z_WRITE_BASE */
1565 radeon_emit(cmd_buffer
->cs
, S_028054_BASE_HI(ds
->db_z_write_base
>> 32)); /* DB_Z_WRITE_BASE_HI */
1566 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* DB_STENCIL_WRITE_BASE */
1567 radeon_emit(cmd_buffer
->cs
, S_02805C_BASE_HI(ds
->db_stencil_write_base
>> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1569 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028068_DB_Z_INFO2
, 2);
1570 radeon_emit(cmd_buffer
->cs
, ds
->db_z_info2
);
1571 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_info2
);
1573 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
1575 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 9);
1576 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_info
); /* R_02803C_DB_DEPTH_INFO */
1577 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* R_028040_DB_Z_INFO */
1578 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
1579 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* R_028048_DB_Z_READ_BASE */
1580 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* R_02804C_DB_STENCIL_READ_BASE */
1581 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* R_028050_DB_Z_WRITE_BASE */
1582 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
1583 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
1584 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
1588 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1589 radv_update_zrange_precision(cmd_buffer
, ds
, iview
, layout
,
1590 in_render_loop
, true);
1592 radeon_set_context_reg(cmd_buffer
->cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1593 ds
->pa_su_poly_offset_db_fmt_cntl
);
1597 * Update the fast clear depth/stencil values if the image is bound as a
1598 * depth/stencil buffer.
1601 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer
*cmd_buffer
,
1602 const struct radv_image_view
*iview
,
1603 VkClearDepthStencilValue ds_clear_value
,
1604 VkImageAspectFlags aspects
)
1606 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1607 const struct radv_image
*image
= iview
->image
;
1608 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1611 if (!cmd_buffer
->state
.attachments
|| !subpass
)
1614 if (!subpass
->depth_stencil_attachment
)
1617 att_idx
= subpass
->depth_stencil_attachment
->attachment
;
1618 if (cmd_buffer
->state
.attachments
[att_idx
].iview
->image
!= image
)
1621 if (aspects
== (VK_IMAGE_ASPECT_DEPTH_BIT
|
1622 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
1623 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
1624 radeon_emit(cs
, ds_clear_value
.stencil
);
1625 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1626 } else if (aspects
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
1627 radeon_set_context_reg_seq(cs
, R_02802C_DB_DEPTH_CLEAR
, 1);
1628 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1630 assert(aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
1631 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 1);
1632 radeon_emit(cs
, ds_clear_value
.stencil
);
1635 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1636 * only needed when clearing Z to 0.0.
1638 if ((aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
1639 ds_clear_value
.depth
== 0.0) {
1640 VkImageLayout layout
= subpass
->depth_stencil_attachment
->layout
;
1641 bool in_render_loop
= subpass
->depth_stencil_attachment
->in_render_loop
;
1643 radv_update_zrange_precision(cmd_buffer
, &cmd_buffer
->state
.attachments
[att_idx
].ds
,
1644 iview
, layout
, in_render_loop
, false);
1647 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1651 * Set the clear depth/stencil values to the image's metadata.
1654 radv_set_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1655 struct radv_image
*image
,
1656 const VkImageSubresourceRange
*range
,
1657 VkClearDepthStencilValue ds_clear_value
,
1658 VkImageAspectFlags aspects
)
1660 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1661 uint64_t va
= radv_get_ds_clear_value_va(image
, range
->baseMipLevel
);
1662 uint32_t level_count
= radv_get_levelCount(image
, range
);
1664 if (aspects
== (VK_IMAGE_ASPECT_DEPTH_BIT
|
1665 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
1666 /* Use the fastest way when both aspects are used. */
1667 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + 2 * level_count
, cmd_buffer
->state
.predicating
));
1668 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1669 S_370_WR_CONFIRM(1) |
1670 S_370_ENGINE_SEL(V_370_PFP
));
1671 radeon_emit(cs
, va
);
1672 radeon_emit(cs
, va
>> 32);
1674 for (uint32_t l
= 0; l
< level_count
; l
++) {
1675 radeon_emit(cs
, ds_clear_value
.stencil
);
1676 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1679 /* Otherwise we need one WRITE_DATA packet per level. */
1680 for (uint32_t l
= 0; l
< level_count
; l
++) {
1681 uint64_t va
= radv_get_ds_clear_value_va(image
, range
->baseMipLevel
+ l
);
1684 if (aspects
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
1685 value
= fui(ds_clear_value
.depth
);
1688 assert(aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
1689 value
= ds_clear_value
.stencil
;
1692 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, cmd_buffer
->state
.predicating
));
1693 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1694 S_370_WR_CONFIRM(1) |
1695 S_370_ENGINE_SEL(V_370_PFP
));
1696 radeon_emit(cs
, va
);
1697 radeon_emit(cs
, va
>> 32);
1698 radeon_emit(cs
, value
);
1704 * Update the TC-compat metadata value for this image.
1707 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1708 struct radv_image
*image
,
1709 const VkImageSubresourceRange
*range
,
1712 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1714 if (!cmd_buffer
->device
->physical_device
->rad_info
.has_tc_compat_zrange_bug
)
1717 uint64_t va
= radv_get_tc_compat_zrange_va(image
, range
->baseMipLevel
);
1718 uint32_t level_count
= radv_get_levelCount(image
, range
);
1720 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + level_count
, cmd_buffer
->state
.predicating
));
1721 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1722 S_370_WR_CONFIRM(1) |
1723 S_370_ENGINE_SEL(V_370_PFP
));
1724 radeon_emit(cs
, va
);
1725 radeon_emit(cs
, va
>> 32);
1727 for (uint32_t l
= 0; l
< level_count
; l
++)
1728 radeon_emit(cs
, value
);
1732 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1733 const struct radv_image_view
*iview
,
1734 VkClearDepthStencilValue ds_clear_value
)
1736 VkImageSubresourceRange range
= {
1737 .aspectMask
= iview
->aspect_mask
,
1738 .baseMipLevel
= iview
->base_mip
,
1739 .levelCount
= iview
->level_count
,
1740 .baseArrayLayer
= iview
->base_layer
,
1741 .layerCount
= iview
->layer_count
,
1745 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1746 * depth clear value is 0.0f.
1748 cond_val
= ds_clear_value
.depth
== 0.0f
? UINT_MAX
: 0;
1750 radv_set_tc_compat_zrange_metadata(cmd_buffer
, iview
->image
, &range
,
1755 * Update the clear depth/stencil values for this image.
1758 radv_update_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1759 const struct radv_image_view
*iview
,
1760 VkClearDepthStencilValue ds_clear_value
,
1761 VkImageAspectFlags aspects
)
1763 VkImageSubresourceRange range
= {
1764 .aspectMask
= iview
->aspect_mask
,
1765 .baseMipLevel
= iview
->base_mip
,
1766 .levelCount
= iview
->level_count
,
1767 .baseArrayLayer
= iview
->base_layer
,
1768 .layerCount
= iview
->layer_count
,
1770 struct radv_image
*image
= iview
->image
;
1772 assert(radv_image_has_htile(image
));
1774 radv_set_ds_clear_metadata(cmd_buffer
, iview
->image
, &range
,
1775 ds_clear_value
, aspects
);
1777 if (radv_image_is_tc_compat_htile(image
) &&
1778 (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
1779 radv_update_tc_compat_zrange_metadata(cmd_buffer
, iview
,
1783 radv_update_bound_fast_clear_ds(cmd_buffer
, iview
, ds_clear_value
,
1788 * Load the clear depth/stencil values from the image's metadata.
1791 radv_load_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1792 const struct radv_image_view
*iview
)
1794 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1795 const struct radv_image
*image
= iview
->image
;
1796 VkImageAspectFlags aspects
= vk_format_aspects(image
->vk_format
);
1797 uint64_t va
= radv_get_ds_clear_value_va(image
, iview
->base_mip
);
1798 unsigned reg_offset
= 0, reg_count
= 0;
1800 if (!radv_image_has_htile(image
))
1803 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1809 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1812 uint32_t reg
= R_028028_DB_STENCIL_CLEAR
+ 4 * reg_offset
;
1814 if (cmd_buffer
->device
->physical_device
->rad_info
.has_load_ctx_reg_pkt
) {
1815 radeon_emit(cs
, PKT3(PKT3_LOAD_CONTEXT_REG
, 3, 0));
1816 radeon_emit(cs
, va
);
1817 radeon_emit(cs
, va
>> 32);
1818 radeon_emit(cs
, (reg
- SI_CONTEXT_REG_OFFSET
) >> 2);
1819 radeon_emit(cs
, reg_count
);
1821 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
1822 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
1823 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1824 (reg_count
== 2 ? COPY_DATA_COUNT_SEL
: 0));
1825 radeon_emit(cs
, va
);
1826 radeon_emit(cs
, va
>> 32);
1827 radeon_emit(cs
, reg
>> 2);
1830 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1836 * With DCC some colors don't require CMASK elimination before being
1837 * used as a texture. This sets a predicate value to determine if the
1838 * cmask eliminate is required.
1841 radv_update_fce_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1842 struct radv_image
*image
,
1843 const VkImageSubresourceRange
*range
, bool value
)
1845 uint64_t pred_val
= value
;
1846 uint64_t va
= radv_image_get_fce_pred_va(image
, range
->baseMipLevel
);
1847 uint32_t level_count
= radv_get_levelCount(image
, range
);
1848 uint32_t count
= 2 * level_count
;
1850 assert(radv_dcc_enabled(image
, range
->baseMipLevel
));
1852 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
1853 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM
) |
1854 S_370_WR_CONFIRM(1) |
1855 S_370_ENGINE_SEL(V_370_PFP
));
1856 radeon_emit(cmd_buffer
->cs
, va
);
1857 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1859 for (uint32_t l
= 0; l
< level_count
; l
++) {
1860 radeon_emit(cmd_buffer
->cs
, pred_val
);
1861 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1866 * Update the DCC predicate to reflect the compression state.
1869 radv_update_dcc_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1870 struct radv_image
*image
,
1871 const VkImageSubresourceRange
*range
, bool value
)
1873 uint64_t pred_val
= value
;
1874 uint64_t va
= radv_image_get_dcc_pred_va(image
, range
->baseMipLevel
);
1875 uint32_t level_count
= radv_get_levelCount(image
, range
);
1876 uint32_t count
= 2 * level_count
;
1878 assert(radv_dcc_enabled(image
, range
->baseMipLevel
));
1880 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
1881 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM
) |
1882 S_370_WR_CONFIRM(1) |
1883 S_370_ENGINE_SEL(V_370_PFP
));
1884 radeon_emit(cmd_buffer
->cs
, va
);
1885 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1887 for (uint32_t l
= 0; l
< level_count
; l
++) {
1888 radeon_emit(cmd_buffer
->cs
, pred_val
);
1889 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1894 * Update the fast clear color values if the image is bound as a color buffer.
1897 radv_update_bound_fast_clear_color(struct radv_cmd_buffer
*cmd_buffer
,
1898 struct radv_image
*image
,
1900 uint32_t color_values
[2])
1902 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1903 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1906 if (!cmd_buffer
->state
.attachments
|| !subpass
)
1909 att_idx
= subpass
->color_attachments
[cb_idx
].attachment
;
1910 if (att_idx
== VK_ATTACHMENT_UNUSED
)
1913 if (cmd_buffer
->state
.attachments
[att_idx
].iview
->image
!= image
)
1916 radeon_set_context_reg_seq(cs
, R_028C8C_CB_COLOR0_CLEAR_WORD0
+ cb_idx
* 0x3c, 2);
1917 radeon_emit(cs
, color_values
[0]);
1918 radeon_emit(cs
, color_values
[1]);
1920 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1924 * Set the clear color values to the image's metadata.
1927 radv_set_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1928 struct radv_image
*image
,
1929 const VkImageSubresourceRange
*range
,
1930 uint32_t color_values
[2])
1932 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1933 uint64_t va
= radv_image_get_fast_clear_va(image
, range
->baseMipLevel
);
1934 uint32_t level_count
= radv_get_levelCount(image
, range
);
1935 uint32_t count
= 2 * level_count
;
1937 assert(radv_image_has_cmask(image
) ||
1938 radv_dcc_enabled(image
, range
->baseMipLevel
));
1940 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, cmd_buffer
->state
.predicating
));
1941 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1942 S_370_WR_CONFIRM(1) |
1943 S_370_ENGINE_SEL(V_370_PFP
));
1944 radeon_emit(cs
, va
);
1945 radeon_emit(cs
, va
>> 32);
1947 for (uint32_t l
= 0; l
< level_count
; l
++) {
1948 radeon_emit(cs
, color_values
[0]);
1949 radeon_emit(cs
, color_values
[1]);
1954 * Update the clear color values for this image.
1957 radv_update_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1958 const struct radv_image_view
*iview
,
1960 uint32_t color_values
[2])
1962 struct radv_image
*image
= iview
->image
;
1963 VkImageSubresourceRange range
= {
1964 .aspectMask
= iview
->aspect_mask
,
1965 .baseMipLevel
= iview
->base_mip
,
1966 .levelCount
= iview
->level_count
,
1967 .baseArrayLayer
= iview
->base_layer
,
1968 .layerCount
= iview
->layer_count
,
1971 assert(radv_image_has_cmask(image
) ||
1972 radv_dcc_enabled(image
, iview
->base_mip
));
1974 radv_set_color_clear_metadata(cmd_buffer
, image
, &range
, color_values
);
1976 radv_update_bound_fast_clear_color(cmd_buffer
, image
, cb_idx
,
1981 * Load the clear color values from the image's metadata.
1984 radv_load_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1985 struct radv_image_view
*iview
,
1988 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1989 struct radv_image
*image
= iview
->image
;
1990 uint64_t va
= radv_image_get_fast_clear_va(image
, iview
->base_mip
);
1992 if (!radv_image_has_cmask(image
) &&
1993 !radv_dcc_enabled(image
, iview
->base_mip
))
1996 uint32_t reg
= R_028C8C_CB_COLOR0_CLEAR_WORD0
+ cb_idx
* 0x3c;
1998 if (cmd_buffer
->device
->physical_device
->rad_info
.has_load_ctx_reg_pkt
) {
1999 radeon_emit(cs
, PKT3(PKT3_LOAD_CONTEXT_REG
, 3, cmd_buffer
->state
.predicating
));
2000 radeon_emit(cs
, va
);
2001 radeon_emit(cs
, va
>> 32);
2002 radeon_emit(cs
, (reg
- SI_CONTEXT_REG_OFFSET
) >> 2);
2005 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, cmd_buffer
->state
.predicating
));
2006 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
2007 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
2008 COPY_DATA_COUNT_SEL
);
2009 radeon_emit(cs
, va
);
2010 radeon_emit(cs
, va
>> 32);
2011 radeon_emit(cs
, reg
>> 2);
2014 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, cmd_buffer
->state
.predicating
));
2020 radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer
)
2023 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
2024 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2026 /* this may happen for inherited secondary recording */
2030 for (i
= 0; i
< 8; ++i
) {
2031 if (i
>= subpass
->color_count
|| subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
2032 radeon_set_context_reg(cmd_buffer
->cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
2033 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
2037 int idx
= subpass
->color_attachments
[i
].attachment
;
2038 struct radv_image_view
*iview
= cmd_buffer
->state
.attachments
[idx
].iview
;
2039 VkImageLayout layout
= subpass
->color_attachments
[i
].layout
;
2040 bool in_render_loop
= subpass
->color_attachments
[i
].in_render_loop
;
2042 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, iview
->bo
);
2044 assert(iview
->aspect_mask
& (VK_IMAGE_ASPECT_COLOR_BIT
| VK_IMAGE_ASPECT_PLANE_0_BIT
|
2045 VK_IMAGE_ASPECT_PLANE_1_BIT
| VK_IMAGE_ASPECT_PLANE_2_BIT
));
2046 radv_emit_fb_color_state(cmd_buffer
, i
, &cmd_buffer
->state
.attachments
[idx
].cb
, iview
, layout
, in_render_loop
);
2048 radv_load_color_clear_metadata(cmd_buffer
, iview
, i
);
2051 if (subpass
->depth_stencil_attachment
) {
2052 int idx
= subpass
->depth_stencil_attachment
->attachment
;
2053 VkImageLayout layout
= subpass
->depth_stencil_attachment
->layout
;
2054 bool in_render_loop
= subpass
->depth_stencil_attachment
->in_render_loop
;
2055 struct radv_image_view
*iview
= cmd_buffer
->state
.attachments
[idx
].iview
;
2056 struct radv_image
*image
= iview
->image
;
2057 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, cmd_buffer
->state
.attachments
[idx
].iview
->bo
);
2058 ASSERTED
uint32_t queue_mask
= radv_image_queue_family_mask(image
,
2059 cmd_buffer
->queue_family_index
,
2060 cmd_buffer
->queue_family_index
);
2061 /* We currently don't support writing decompressed HTILE */
2062 assert(radv_layout_has_htile(image
, layout
, in_render_loop
, queue_mask
) ==
2063 radv_layout_is_htile_compressed(image
, layout
, in_render_loop
, queue_mask
));
2065 radv_emit_fb_ds_state(cmd_buffer
, &cmd_buffer
->state
.attachments
[idx
].ds
, iview
, layout
, in_render_loop
);
2067 if (cmd_buffer
->state
.attachments
[idx
].ds
.offset_scale
!= cmd_buffer
->state
.offset_scale
) {
2068 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2069 cmd_buffer
->state
.offset_scale
= cmd_buffer
->state
.attachments
[idx
].ds
.offset_scale
;
2071 radv_load_ds_clear_metadata(cmd_buffer
, iview
);
2073 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
)
2074 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 2);
2076 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028040_DB_Z_INFO
, 2);
2078 radeon_emit(cmd_buffer
->cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
2079 radeon_emit(cmd_buffer
->cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
2081 radeon_set_context_reg(cmd_buffer
->cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
2082 S_028208_BR_X(framebuffer
->width
) |
2083 S_028208_BR_Y(framebuffer
->height
));
2085 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX8
) {
2086 bool disable_constant_encode
=
2087 cmd_buffer
->device
->physical_device
->rad_info
.has_dcc_constant_encode
;
2088 enum chip_class chip_class
=
2089 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
;
2090 uint8_t watermark
= chip_class
>= GFX10
? 6 : 4;
2092 radeon_set_context_reg(cmd_buffer
->cs
, R_028424_CB_DCC_CONTROL
,
2093 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class
<= GFX9
) |
2094 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark
) |
2095 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode
));
2098 if (cmd_buffer
->device
->dfsm_allowed
) {
2099 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2100 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
2103 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_FRAMEBUFFER
;
2107 radv_emit_index_buffer(struct radv_cmd_buffer
*cmd_buffer
, bool indirect
)
2109 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
2110 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2112 if (state
->index_type
!= state
->last_index_type
) {
2113 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2114 radeon_set_uconfig_reg_idx(cmd_buffer
->device
->physical_device
,
2115 cs
, R_03090C_VGT_INDEX_TYPE
,
2116 2, state
->index_type
);
2118 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
2119 radeon_emit(cs
, state
->index_type
);
2122 state
->last_index_type
= state
->index_type
;
2125 /* For the direct indexed draws we use DRAW_INDEX_2, which includes
2126 * the index_va and max_index_count already. */
2130 radeon_emit(cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
2131 radeon_emit(cs
, state
->index_va
);
2132 radeon_emit(cs
, state
->index_va
>> 32);
2134 radeon_emit(cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
2135 radeon_emit(cs
, state
->max_index_count
);
2137 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_INDEX_BUFFER
;
2140 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
)
2142 bool has_perfect_queries
= cmd_buffer
->state
.perfect_occlusion_queries_enabled
;
2143 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2144 uint32_t pa_sc_mode_cntl_1
=
2145 pipeline
? pipeline
->graphics
.ms
.pa_sc_mode_cntl_1
: 0;
2146 uint32_t db_count_control
;
2148 if(!cmd_buffer
->state
.active_occlusion_queries
) {
2149 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2150 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1
) &&
2151 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
&&
2152 has_perfect_queries
) {
2153 /* Re-enable out-of-order rasterization if the
2154 * bound pipeline supports it and if it's has
2155 * been disabled before starting any perfect
2156 * occlusion queries.
2158 radeon_set_context_reg(cmd_buffer
->cs
,
2159 R_028A4C_PA_SC_MODE_CNTL_1
,
2163 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
2165 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2166 uint32_t sample_rate
= subpass
? util_logbase2(subpass
->max_sample_count
) : 0;
2167 bool gfx10_perfect
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&& has_perfect_queries
;
2169 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2171 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries
) |
2172 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect
) |
2173 S_028004_SAMPLE_RATE(sample_rate
) |
2174 S_028004_ZPASS_ENABLE(1) |
2175 S_028004_SLICE_EVEN_ENABLE(1) |
2176 S_028004_SLICE_ODD_ENABLE(1);
2178 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1
) &&
2179 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
&&
2180 has_perfect_queries
) {
2181 /* If the bound pipeline has enabled
2182 * out-of-order rasterization, we should
2183 * disable it before starting any perfect
2184 * occlusion queries.
2186 pa_sc_mode_cntl_1
&= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE
;
2188 radeon_set_context_reg(cmd_buffer
->cs
,
2189 R_028A4C_PA_SC_MODE_CNTL_1
,
2193 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
2194 S_028004_SAMPLE_RATE(sample_rate
);
2198 radeon_set_context_reg(cmd_buffer
->cs
, R_028004_DB_COUNT_CONTROL
, db_count_control
);
2200 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
2204 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
)
2206 uint32_t states
= cmd_buffer
->state
.dirty
& cmd_buffer
->state
.emitted_pipeline
->graphics
.needed_dynamic_state
;
2208 if (states
& (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
2209 radv_emit_viewport(cmd_buffer
);
2211 if (states
& (RADV_CMD_DIRTY_DYNAMIC_SCISSOR
| RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
) &&
2212 !cmd_buffer
->device
->physical_device
->rad_info
.has_gfx9_scissor_bug
)
2213 radv_emit_scissor(cmd_buffer
);
2215 if (states
& RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
)
2216 radv_emit_line_width(cmd_buffer
);
2218 if (states
& RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
)
2219 radv_emit_blend_constants(cmd_buffer
);
2221 if (states
& (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
|
2222 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
|
2223 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
))
2224 radv_emit_stencil(cmd_buffer
);
2226 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
)
2227 radv_emit_depth_bounds(cmd_buffer
);
2229 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
)
2230 radv_emit_depth_bias(cmd_buffer
);
2232 if (states
& RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
)
2233 radv_emit_discard_rectangle(cmd_buffer
);
2235 if (states
& RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
)
2236 radv_emit_sample_locations(cmd_buffer
);
2238 if (states
& RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
)
2239 radv_emit_line_stipple(cmd_buffer
);
2241 cmd_buffer
->state
.dirty
&= ~states
;
2245 radv_flush_push_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
2246 VkPipelineBindPoint bind_point
)
2248 struct radv_descriptor_state
*descriptors_state
=
2249 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2250 struct radv_descriptor_set
*set
= &descriptors_state
->push_set
.set
;
2253 if (!radv_cmd_buffer_upload_data(cmd_buffer
, set
->size
, 32,
2258 set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2259 set
->va
+= bo_offset
;
2263 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer
*cmd_buffer
,
2264 VkPipelineBindPoint bind_point
)
2266 struct radv_descriptor_state
*descriptors_state
=
2267 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2268 uint32_t size
= MAX_SETS
* 4;
2272 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
,
2273 256, &offset
, &ptr
))
2276 for (unsigned i
= 0; i
< MAX_SETS
; i
++) {
2277 uint32_t *uptr
= ((uint32_t *)ptr
) + i
;
2278 uint64_t set_va
= 0;
2279 struct radv_descriptor_set
*set
= descriptors_state
->sets
[i
];
2280 if (descriptors_state
->valid
& (1u << i
))
2282 uptr
[0] = set_va
& 0xffffffff;
2285 uint64_t va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2288 if (cmd_buffer
->state
.pipeline
) {
2289 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
])
2290 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
2291 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2293 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_FRAGMENT
])
2294 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_FRAGMENT
,
2295 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2297 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
))
2298 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
2299 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2301 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
2302 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_CTRL
,
2303 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2305 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
2306 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_EVAL
,
2307 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2310 if (cmd_buffer
->state
.compute_pipeline
)
2311 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
, MESA_SHADER_COMPUTE
,
2312 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2316 radv_flush_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
2317 VkShaderStageFlags stages
)
2319 VkPipelineBindPoint bind_point
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
?
2320 VK_PIPELINE_BIND_POINT_COMPUTE
:
2321 VK_PIPELINE_BIND_POINT_GRAPHICS
;
2322 struct radv_descriptor_state
*descriptors_state
=
2323 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2324 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2325 bool flush_indirect_descriptors
;
2327 if (!descriptors_state
->dirty
)
2330 if (descriptors_state
->push_dirty
)
2331 radv_flush_push_descriptors(cmd_buffer
, bind_point
);
2333 flush_indirect_descriptors
=
2334 (bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
&&
2335 state
->pipeline
&& state
->pipeline
->need_indirect_descriptor_sets
) ||
2336 (bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
&&
2337 state
->compute_pipeline
&& state
->compute_pipeline
->need_indirect_descriptor_sets
);
2339 if (flush_indirect_descriptors
)
2340 radv_flush_indirect_descriptor_sets(cmd_buffer
, bind_point
);
2342 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
2344 MAX_SETS
* MESA_SHADER_STAGES
* 4);
2346 if (cmd_buffer
->state
.pipeline
) {
2347 radv_foreach_stage(stage
, stages
) {
2348 if (!cmd_buffer
->state
.pipeline
->shaders
[stage
])
2351 radv_emit_descriptor_pointers(cmd_buffer
,
2352 cmd_buffer
->state
.pipeline
,
2353 descriptors_state
, stage
);
2357 if (cmd_buffer
->state
.compute_pipeline
&&
2358 (stages
& VK_SHADER_STAGE_COMPUTE_BIT
)) {
2359 radv_emit_descriptor_pointers(cmd_buffer
,
2360 cmd_buffer
->state
.compute_pipeline
,
2362 MESA_SHADER_COMPUTE
);
2365 descriptors_state
->dirty
= 0;
2366 descriptors_state
->push_dirty
= false;
2368 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2370 if (unlikely(cmd_buffer
->device
->trace_bo
))
2371 radv_save_descriptors(cmd_buffer
, bind_point
);
2375 radv_flush_constants(struct radv_cmd_buffer
*cmd_buffer
,
2376 VkShaderStageFlags stages
)
2378 struct radv_pipeline
*pipeline
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
2379 ? cmd_buffer
->state
.compute_pipeline
2380 : cmd_buffer
->state
.pipeline
;
2381 VkPipelineBindPoint bind_point
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
?
2382 VK_PIPELINE_BIND_POINT_COMPUTE
:
2383 VK_PIPELINE_BIND_POINT_GRAPHICS
;
2384 struct radv_descriptor_state
*descriptors_state
=
2385 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2386 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
2387 struct radv_shader_variant
*shader
, *prev_shader
;
2388 bool need_push_constants
= false;
2393 stages
&= cmd_buffer
->push_constant_stages
;
2395 (!layout
->push_constant_size
&& !layout
->dynamic_offset_count
))
2398 radv_foreach_stage(stage
, stages
) {
2399 shader
= radv_get_shader(pipeline
, stage
);
2403 need_push_constants
|= shader
->info
.loads_push_constants
;
2404 need_push_constants
|= shader
->info
.loads_dynamic_offsets
;
2406 uint8_t base
= shader
->info
.base_inline_push_consts
;
2407 uint8_t count
= shader
->info
.num_inline_push_consts
;
2409 radv_emit_inline_push_consts(cmd_buffer
, pipeline
, stage
,
2410 AC_UD_INLINE_PUSH_CONSTANTS
,
2412 (uint32_t *)&cmd_buffer
->push_constants
[base
* 4]);
2415 if (need_push_constants
) {
2416 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, layout
->push_constant_size
+
2417 16 * layout
->dynamic_offset_count
,
2418 256, &offset
, &ptr
))
2421 memcpy(ptr
, cmd_buffer
->push_constants
, layout
->push_constant_size
);
2422 memcpy((char*)ptr
+ layout
->push_constant_size
,
2423 descriptors_state
->dynamic_buffers
,
2424 16 * layout
->dynamic_offset_count
);
2426 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2429 ASSERTED
unsigned cdw_max
=
2430 radeon_check_space(cmd_buffer
->device
->ws
,
2431 cmd_buffer
->cs
, MESA_SHADER_STAGES
* 4);
2434 radv_foreach_stage(stage
, stages
) {
2435 shader
= radv_get_shader(pipeline
, stage
);
2437 /* Avoid redundantly emitting the address for merged stages. */
2438 if (shader
&& shader
!= prev_shader
) {
2439 radv_emit_userdata_address(cmd_buffer
, pipeline
, stage
,
2440 AC_UD_PUSH_CONSTANTS
, va
);
2442 prev_shader
= shader
;
2445 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2448 cmd_buffer
->push_constant_stages
&= ~stages
;
2452 radv_flush_vertex_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
2453 bool pipeline_is_dirty
)
2455 if ((pipeline_is_dirty
||
2456 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_VERTEX_BUFFER
)) &&
2457 cmd_buffer
->state
.pipeline
->num_vertex_bindings
&&
2458 radv_get_shader(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
)->info
.vs
.has_vertex_buffers
) {
2462 uint32_t count
= cmd_buffer
->state
.pipeline
->num_vertex_bindings
;
2465 /* allocate some descriptor state for vertex buffers */
2466 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, count
* 16, 256,
2467 &vb_offset
, &vb_ptr
))
2470 for (i
= 0; i
< count
; i
++) {
2471 uint32_t *desc
= &((uint32_t *)vb_ptr
)[i
* 4];
2473 struct radv_buffer
*buffer
= cmd_buffer
->vertex_bindings
[i
].buffer
;
2474 uint32_t stride
= cmd_buffer
->state
.pipeline
->binding_stride
[i
];
2475 unsigned num_records
;
2480 va
= radv_buffer_get_va(buffer
->bo
);
2482 offset
= cmd_buffer
->vertex_bindings
[i
].offset
;
2483 va
+= offset
+ buffer
->offset
;
2485 num_records
= buffer
->size
- offset
;
2486 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
!= GFX8
&& stride
)
2487 num_records
/= stride
;
2490 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(stride
);
2491 desc
[2] = num_records
;
2492 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2493 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2494 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2495 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2497 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2498 /* OOB_SELECT chooses the out-of-bounds check:
2499 * - 1: index >= NUM_RECORDS (Structured)
2500 * - 3: offset >= NUM_RECORDS (Raw)
2502 int oob_select
= stride
? V_008F0C_OOB_SELECT_STRUCTURED
: V_008F0C_OOB_SELECT_RAW
;
2504 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT
) |
2505 S_008F0C_OOB_SELECT(oob_select
) |
2506 S_008F0C_RESOURCE_LEVEL(1);
2508 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT
) |
2509 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2513 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2516 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
2517 AC_UD_VS_VERTEX_BUFFERS
, va
);
2519 cmd_buffer
->state
.vb_va
= va
;
2520 cmd_buffer
->state
.vb_size
= count
* 16;
2521 cmd_buffer
->state
.prefetch_L2_mask
|= RADV_PREFETCH_VBO_DESCRIPTORS
;
2523 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_VERTEX_BUFFER
;
2527 radv_emit_streamout_buffers(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
)
2529 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2530 struct radv_userdata_info
*loc
;
2533 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
2534 if (!radv_get_shader(pipeline
, stage
))
2537 loc
= radv_lookup_user_sgpr(pipeline
, stage
,
2538 AC_UD_STREAMOUT_BUFFERS
);
2539 if (loc
->sgpr_idx
== -1)
2542 base_reg
= pipeline
->user_data_0
[stage
];
2544 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
2545 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
2548 if (radv_pipeline_has_gs_copy_shader(pipeline
)) {
2549 loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_STREAMOUT_BUFFERS
];
2550 if (loc
->sgpr_idx
!= -1) {
2551 base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2553 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
2554 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
2560 radv_flush_streamout_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
2562 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_STREAMOUT_BUFFER
) {
2563 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
2564 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
2569 /* Allocate some descriptor state for streamout buffers. */
2570 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
,
2571 MAX_SO_BUFFERS
* 16, 256,
2572 &so_offset
, &so_ptr
))
2575 for (uint32_t i
= 0; i
< MAX_SO_BUFFERS
; i
++) {
2576 struct radv_buffer
*buffer
= sb
[i
].buffer
;
2577 uint32_t *desc
= &((uint32_t *)so_ptr
)[i
* 4];
2579 if (!(so
->enabled_mask
& (1 << i
)))
2582 va
= radv_buffer_get_va(buffer
->bo
) + buffer
->offset
;
2586 /* Set the descriptor.
2588 * On GFX8, the format must be non-INVALID, otherwise
2589 * the buffer will be considered not bound and store
2590 * instructions will be no-ops.
2592 uint32_t size
= 0xffffffff;
2594 /* Compute the correct buffer size for NGG streamout
2595 * because it's used to determine the max emit per
2598 if (cmd_buffer
->device
->physical_device
->use_ngg_streamout
)
2599 size
= buffer
->size
- sb
[i
].offset
;
2602 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
2604 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2605 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2606 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2607 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2609 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2610 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2611 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
2612 S_008F0C_RESOURCE_LEVEL(1);
2614 desc
[3] |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2618 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2621 radv_emit_streamout_buffers(cmd_buffer
, va
);
2624 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER
;
2628 radv_flush_ngg_gs_state(struct radv_cmd_buffer
*cmd_buffer
)
2630 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2631 struct radv_userdata_info
*loc
;
2632 uint32_t ngg_gs_state
= 0;
2635 if (!radv_pipeline_has_gs(pipeline
) ||
2636 !radv_pipeline_has_ngg(pipeline
))
2639 /* By default NGG GS queries are disabled but they are enabled if the
2640 * command buffer has active GDS queries or if it's a secondary command
2641 * buffer that inherits the number of generated primitives.
2643 if (cmd_buffer
->state
.active_pipeline_gds_queries
||
2644 (cmd_buffer
->state
.inherited_pipeline_statistics
& VK_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_PRIMITIVES_BIT
))
2647 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_GEOMETRY
,
2648 AC_UD_NGG_GS_STATE
);
2649 base_reg
= pipeline
->user_data_0
[MESA_SHADER_GEOMETRY
];
2650 assert(loc
->sgpr_idx
!= -1);
2652 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4,
2657 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
, bool pipeline_is_dirty
)
2659 radv_flush_vertex_descriptors(cmd_buffer
, pipeline_is_dirty
);
2660 radv_flush_streamout_descriptors(cmd_buffer
);
2661 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
2662 radv_flush_constants(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
2663 radv_flush_ngg_gs_state(cmd_buffer
);
2666 struct radv_draw_info
{
2668 * Number of vertices.
2673 * Index of the first vertex.
2675 int32_t vertex_offset
;
2678 * First instance id.
2680 uint32_t first_instance
;
2683 * Number of instances.
2685 uint32_t instance_count
;
2688 * First index (indexed draws only).
2690 uint32_t first_index
;
2693 * Whether it's an indexed draw.
2698 * Indirect draw parameters resource.
2700 struct radv_buffer
*indirect
;
2701 uint64_t indirect_offset
;
2705 * Draw count parameters resource.
2707 struct radv_buffer
*count_buffer
;
2708 uint64_t count_buffer_offset
;
2711 * Stream output parameters resource.
2713 struct radv_buffer
*strmout_buffer
;
2714 uint64_t strmout_buffer_offset
;
2718 radv_get_primitive_reset_index(struct radv_cmd_buffer
*cmd_buffer
)
2720 switch (cmd_buffer
->state
.index_type
) {
2721 case V_028A7C_VGT_INDEX_8
:
2723 case V_028A7C_VGT_INDEX_16
:
2725 case V_028A7C_VGT_INDEX_32
:
2728 unreachable("invalid index type");
2733 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
2734 bool instanced_draw
, bool indirect_draw
,
2735 bool count_from_stream_output
,
2736 uint32_t draw_vertex_count
)
2738 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
2739 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2740 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
2741 unsigned ia_multi_vgt_param
;
2743 ia_multi_vgt_param
=
2744 si_get_ia_multi_vgt_param(cmd_buffer
, instanced_draw
,
2746 count_from_stream_output
,
2749 if (state
->last_ia_multi_vgt_param
!= ia_multi_vgt_param
) {
2750 if (info
->chip_class
== GFX9
) {
2751 radeon_set_uconfig_reg_idx(cmd_buffer
->device
->physical_device
,
2753 R_030960_IA_MULTI_VGT_PARAM
,
2754 4, ia_multi_vgt_param
);
2755 } else if (info
->chip_class
>= GFX7
) {
2756 radeon_set_context_reg_idx(cs
,
2757 R_028AA8_IA_MULTI_VGT_PARAM
,
2758 1, ia_multi_vgt_param
);
2760 radeon_set_context_reg(cs
, R_028AA8_IA_MULTI_VGT_PARAM
,
2761 ia_multi_vgt_param
);
2763 state
->last_ia_multi_vgt_param
= ia_multi_vgt_param
;
2768 radv_emit_draw_registers(struct radv_cmd_buffer
*cmd_buffer
,
2769 const struct radv_draw_info
*draw_info
)
2771 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
2772 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2773 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
2774 int32_t primitive_reset_en
;
2777 if (info
->chip_class
< GFX10
) {
2778 si_emit_ia_multi_vgt_param(cmd_buffer
, draw_info
->instance_count
> 1,
2779 draw_info
->indirect
,
2780 !!draw_info
->strmout_buffer
,
2781 draw_info
->indirect
? 0 : draw_info
->count
);
2784 /* Primitive restart. */
2785 primitive_reset_en
=
2786 draw_info
->indexed
&& state
->pipeline
->graphics
.prim_restart_enable
;
2788 if (primitive_reset_en
!= state
->last_primitive_reset_en
) {
2789 state
->last_primitive_reset_en
= primitive_reset_en
;
2790 if (info
->chip_class
>= GFX9
) {
2791 radeon_set_uconfig_reg(cs
,
2792 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN
,
2793 primitive_reset_en
);
2795 radeon_set_context_reg(cs
,
2796 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
,
2797 primitive_reset_en
);
2801 if (primitive_reset_en
) {
2802 uint32_t primitive_reset_index
=
2803 radv_get_primitive_reset_index(cmd_buffer
);
2805 if (primitive_reset_index
!= state
->last_primitive_reset_index
) {
2806 radeon_set_context_reg(cs
,
2807 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
2808 primitive_reset_index
);
2809 state
->last_primitive_reset_index
= primitive_reset_index
;
2813 if (draw_info
->strmout_buffer
) {
2814 uint64_t va
= radv_buffer_get_va(draw_info
->strmout_buffer
->bo
);
2816 va
+= draw_info
->strmout_buffer
->offset
+
2817 draw_info
->strmout_buffer_offset
;
2819 radeon_set_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
,
2822 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
2823 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
2824 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
2825 COPY_DATA_WR_CONFIRM
);
2826 radeon_emit(cs
, va
);
2827 radeon_emit(cs
, va
>> 32);
2828 radeon_emit(cs
, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2);
2829 radeon_emit(cs
, 0); /* unused */
2831 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, draw_info
->strmout_buffer
->bo
);
2835 static void radv_stage_flush(struct radv_cmd_buffer
*cmd_buffer
,
2836 VkPipelineStageFlags src_stage_mask
)
2838 if (src_stage_mask
& (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT
|
2839 VK_PIPELINE_STAGE_TRANSFER_BIT
|
2840 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
2841 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
2842 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
;
2845 if (src_stage_mask
& (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT
|
2846 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT
|
2847 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT
|
2848 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
|
2849 VK_PIPELINE_STAGE_TRANSFER_BIT
|
2850 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
2851 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT
|
2852 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
2853 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
2854 } else if (src_stage_mask
& (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
2855 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
|
2856 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT
|
2857 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT
|
2858 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT
|
2859 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT
|
2860 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT
)) {
2861 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VS_PARTIAL_FLUSH
;
2865 static enum radv_cmd_flush_bits
2866 radv_src_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
2867 VkAccessFlags src_flags
,
2868 struct radv_image
*image
)
2870 bool flush_CB_meta
= true, flush_DB_meta
= true;
2871 enum radv_cmd_flush_bits flush_bits
= 0;
2875 if (!radv_image_has_CB_metadata(image
))
2876 flush_CB_meta
= false;
2877 if (!radv_image_has_htile(image
))
2878 flush_DB_meta
= false;
2881 for_each_bit(b
, src_flags
) {
2882 switch ((VkAccessFlagBits
)(1 << b
)) {
2883 case VK_ACCESS_SHADER_WRITE_BIT
:
2884 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT
:
2885 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
:
2886 flush_bits
|= RADV_CMD_FLAG_WB_L2
;
2888 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2889 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
2891 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2893 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2894 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
2896 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2898 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2899 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
2900 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
2901 RADV_CMD_FLAG_INV_L2
;
2904 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2906 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2915 static enum radv_cmd_flush_bits
2916 radv_dst_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
2917 VkAccessFlags dst_flags
,
2918 struct radv_image
*image
)
2920 bool flush_CB_meta
= true, flush_DB_meta
= true;
2921 enum radv_cmd_flush_bits flush_bits
= 0;
2922 bool flush_CB
= true, flush_DB
= true;
2923 bool image_is_coherent
= false;
2927 if (!(image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
)) {
2932 if (!radv_image_has_CB_metadata(image
))
2933 flush_CB_meta
= false;
2934 if (!radv_image_has_htile(image
))
2935 flush_DB_meta
= false;
2937 /* TODO: implement shader coherent for GFX10 */
2939 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
2940 if (image
->info
.samples
== 1 &&
2941 (image
->usage
& (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
|
2942 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
)) &&
2943 !vk_format_is_stencil(image
->vk_format
)) {
2944 /* Single-sample color and single-sample depth
2945 * (not stencil) are coherent with shaders on
2948 image_is_coherent
= true;
2953 for_each_bit(b
, dst_flags
) {
2954 switch ((VkAccessFlagBits
)(1 << b
)) {
2955 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2956 case VK_ACCESS_INDEX_READ_BIT
:
2957 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
:
2959 case VK_ACCESS_UNIFORM_READ_BIT
:
2960 flush_bits
|= RADV_CMD_FLAG_INV_VCACHE
| RADV_CMD_FLAG_INV_SCACHE
;
2962 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2963 case VK_ACCESS_TRANSFER_READ_BIT
:
2964 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2965 flush_bits
|= RADV_CMD_FLAG_INV_VCACHE
|
2966 RADV_CMD_FLAG_INV_L2
;
2968 case VK_ACCESS_SHADER_READ_BIT
:
2969 flush_bits
|= RADV_CMD_FLAG_INV_VCACHE
;
2970 /* Unlike LLVM, ACO uses SMEM for SSBOs and we have to
2971 * invalidate the scalar cache. */
2972 if (cmd_buffer
->device
->physical_device
->use_aco
&&
2973 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX8
)
2974 flush_bits
|= RADV_CMD_FLAG_INV_SCACHE
;
2976 if (!image_is_coherent
)
2977 flush_bits
|= RADV_CMD_FLAG_INV_L2
;
2979 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
:
2981 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
2983 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2985 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
:
2987 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
2989 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2998 void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
,
2999 const struct radv_subpass_barrier
*barrier
)
3001 cmd_buffer
->state
.flush_bits
|= radv_src_access_flush(cmd_buffer
, barrier
->src_access_mask
,
3003 radv_stage_flush(cmd_buffer
, barrier
->src_stage_mask
);
3004 cmd_buffer
->state
.flush_bits
|= radv_dst_access_flush(cmd_buffer
, barrier
->dst_access_mask
,
3009 radv_get_subpass_id(struct radv_cmd_buffer
*cmd_buffer
)
3011 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3012 uint32_t subpass_id
= state
->subpass
- state
->pass
->subpasses
;
3014 /* The id of this subpass shouldn't exceed the number of subpasses in
3015 * this render pass minus 1.
3017 assert(subpass_id
< state
->pass
->subpass_count
);
3021 static struct radv_sample_locations_state
*
3022 radv_get_attachment_sample_locations(struct radv_cmd_buffer
*cmd_buffer
,
3026 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3027 uint32_t subpass_id
= radv_get_subpass_id(cmd_buffer
);
3028 struct radv_image_view
*view
= state
->attachments
[att_idx
].iview
;
3030 if (view
->image
->info
.samples
== 1)
3033 if (state
->pass
->attachments
[att_idx
].first_subpass_idx
== subpass_id
) {
3034 /* Return the initial sample locations if this is the initial
3035 * layout transition of the given subpass attachemnt.
3037 if (state
->attachments
[att_idx
].sample_location
.count
> 0)
3038 return &state
->attachments
[att_idx
].sample_location
;
3040 /* Otherwise return the subpass sample locations if defined. */
3041 if (state
->subpass_sample_locs
) {
3042 /* Because the driver sets the current subpass before
3043 * initial layout transitions, we should use the sample
3044 * locations from the previous subpass to avoid an
3045 * off-by-one problem. Otherwise, use the sample
3046 * locations for the current subpass for final layout
3052 for (uint32_t i
= 0; i
< state
->num_subpass_sample_locs
; i
++) {
3053 if (state
->subpass_sample_locs
[i
].subpass_idx
== subpass_id
)
3054 return &state
->subpass_sample_locs
[i
].sample_location
;
3062 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3063 struct radv_subpass_attachment att
,
3066 unsigned idx
= att
.attachment
;
3067 struct radv_image_view
*view
= cmd_buffer
->state
.attachments
[idx
].iview
;
3068 struct radv_sample_locations_state
*sample_locs
;
3069 VkImageSubresourceRange range
;
3070 range
.aspectMask
= view
->aspect_mask
;
3071 range
.baseMipLevel
= view
->base_mip
;
3072 range
.levelCount
= 1;
3073 range
.baseArrayLayer
= view
->base_layer
;
3074 range
.layerCount
= cmd_buffer
->state
.framebuffer
->layers
;
3076 if (cmd_buffer
->state
.subpass
->view_mask
) {
3077 /* If the current subpass uses multiview, the driver might have
3078 * performed a fast color/depth clear to the whole image
3079 * (including all layers). To make sure the driver will
3080 * decompress the image correctly (if needed), we have to
3081 * account for the "real" number of layers. If the view mask is
3082 * sparse, this will decompress more layers than needed.
3084 range
.layerCount
= util_last_bit(cmd_buffer
->state
.subpass
->view_mask
);
3087 /* Get the subpass sample locations for the given attachment, if NULL
3088 * is returned the driver will use the default HW locations.
3090 sample_locs
= radv_get_attachment_sample_locations(cmd_buffer
, idx
,
3093 /* Determine if the subpass uses separate depth/stencil layouts. */
3094 bool uses_separate_depth_stencil_layouts
= false;
3095 if ((cmd_buffer
->state
.attachments
[idx
].current_layout
!=
3096 cmd_buffer
->state
.attachments
[idx
].current_stencil_layout
) ||
3097 (att
.layout
!= att
.stencil_layout
)) {
3098 uses_separate_depth_stencil_layouts
= true;
3101 /* For separate layouts, perform depth and stencil transitions
3104 if (uses_separate_depth_stencil_layouts
&&
3105 (range
.aspectMask
== (VK_IMAGE_ASPECT_DEPTH_BIT
|
3106 VK_IMAGE_ASPECT_STENCIL_BIT
))) {
3107 /* Depth-only transitions. */
3108 range
.aspectMask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
3109 radv_handle_image_transition(cmd_buffer
,
3111 cmd_buffer
->state
.attachments
[idx
].current_layout
,
3112 cmd_buffer
->state
.attachments
[idx
].current_in_render_loop
,
3113 att
.layout
, att
.in_render_loop
,
3114 0, 0, &range
, sample_locs
);
3116 /* Stencil-only transitions. */
3117 range
.aspectMask
= VK_IMAGE_ASPECT_STENCIL_BIT
;
3118 radv_handle_image_transition(cmd_buffer
,
3120 cmd_buffer
->state
.attachments
[idx
].current_stencil_layout
,
3121 cmd_buffer
->state
.attachments
[idx
].current_in_render_loop
,
3122 att
.stencil_layout
, att
.in_render_loop
,
3123 0, 0, &range
, sample_locs
);
3125 radv_handle_image_transition(cmd_buffer
,
3127 cmd_buffer
->state
.attachments
[idx
].current_layout
,
3128 cmd_buffer
->state
.attachments
[idx
].current_in_render_loop
,
3129 att
.layout
, att
.in_render_loop
,
3130 0, 0, &range
, sample_locs
);
3133 cmd_buffer
->state
.attachments
[idx
].current_layout
= att
.layout
;
3134 cmd_buffer
->state
.attachments
[idx
].current_stencil_layout
= att
.stencil_layout
;
3135 cmd_buffer
->state
.attachments
[idx
].current_in_render_loop
= att
.in_render_loop
;
3141 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
3142 const struct radv_subpass
*subpass
)
3144 cmd_buffer
->state
.subpass
= subpass
;
3146 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_FRAMEBUFFER
;
3150 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer
*cmd_buffer
,
3151 struct radv_render_pass
*pass
,
3152 const VkRenderPassBeginInfo
*info
)
3154 const struct VkRenderPassSampleLocationsBeginInfoEXT
*sample_locs
=
3155 vk_find_struct_const(info
->pNext
,
3156 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT
);
3157 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3160 state
->subpass_sample_locs
= NULL
;
3164 for (uint32_t i
= 0; i
< sample_locs
->attachmentInitialSampleLocationsCount
; i
++) {
3165 const VkAttachmentSampleLocationsEXT
*att_sample_locs
=
3166 &sample_locs
->pAttachmentInitialSampleLocations
[i
];
3167 uint32_t att_idx
= att_sample_locs
->attachmentIndex
;
3168 struct radv_image
*image
= cmd_buffer
->state
.attachments
[att_idx
].iview
->image
;
3170 assert(vk_format_is_depth_or_stencil(image
->vk_format
));
3172 /* From the Vulkan spec 1.1.108:
3174 * "If the image referenced by the framebuffer attachment at
3175 * index attachmentIndex was not created with
3176 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
3177 * then the values specified in sampleLocationsInfo are
3180 if (!(image
->flags
& VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
))
3183 const VkSampleLocationsInfoEXT
*sample_locs_info
=
3184 &att_sample_locs
->sampleLocationsInfo
;
3186 state
->attachments
[att_idx
].sample_location
.per_pixel
=
3187 sample_locs_info
->sampleLocationsPerPixel
;
3188 state
->attachments
[att_idx
].sample_location
.grid_size
=
3189 sample_locs_info
->sampleLocationGridSize
;
3190 state
->attachments
[att_idx
].sample_location
.count
=
3191 sample_locs_info
->sampleLocationsCount
;
3192 typed_memcpy(&state
->attachments
[att_idx
].sample_location
.locations
[0],
3193 sample_locs_info
->pSampleLocations
,
3194 sample_locs_info
->sampleLocationsCount
);
3197 state
->subpass_sample_locs
= vk_alloc(&cmd_buffer
->pool
->alloc
,
3198 sample_locs
->postSubpassSampleLocationsCount
*
3199 sizeof(state
->subpass_sample_locs
[0]),
3200 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3201 if (state
->subpass_sample_locs
== NULL
) {
3202 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
3203 return cmd_buffer
->record_result
;
3206 state
->num_subpass_sample_locs
= sample_locs
->postSubpassSampleLocationsCount
;
3208 for (uint32_t i
= 0; i
< sample_locs
->postSubpassSampleLocationsCount
; i
++) {
3209 const VkSubpassSampleLocationsEXT
*subpass_sample_locs_info
=
3210 &sample_locs
->pPostSubpassSampleLocations
[i
];
3211 const VkSampleLocationsInfoEXT
*sample_locs_info
=
3212 &subpass_sample_locs_info
->sampleLocationsInfo
;
3214 state
->subpass_sample_locs
[i
].subpass_idx
=
3215 subpass_sample_locs_info
->subpassIndex
;
3216 state
->subpass_sample_locs
[i
].sample_location
.per_pixel
=
3217 sample_locs_info
->sampleLocationsPerPixel
;
3218 state
->subpass_sample_locs
[i
].sample_location
.grid_size
=
3219 sample_locs_info
->sampleLocationGridSize
;
3220 state
->subpass_sample_locs
[i
].sample_location
.count
=
3221 sample_locs_info
->sampleLocationsCount
;
3222 typed_memcpy(&state
->subpass_sample_locs
[i
].sample_location
.locations
[0],
3223 sample_locs_info
->pSampleLocations
,
3224 sample_locs_info
->sampleLocationsCount
);
3231 radv_cmd_state_setup_attachments(struct radv_cmd_buffer
*cmd_buffer
,
3232 struct radv_render_pass
*pass
,
3233 const VkRenderPassBeginInfo
*info
)
3235 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3236 const struct VkRenderPassAttachmentBeginInfo
*attachment_info
= NULL
;
3239 attachment_info
= vk_find_struct_const(info
->pNext
,
3240 RENDER_PASS_ATTACHMENT_BEGIN_INFO
);
3244 if (pass
->attachment_count
== 0) {
3245 state
->attachments
= NULL
;
3249 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
3250 pass
->attachment_count
*
3251 sizeof(state
->attachments
[0]),
3252 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3253 if (state
->attachments
== NULL
) {
3254 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
3255 return cmd_buffer
->record_result
;
3258 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
3259 struct radv_render_pass_attachment
*att
= &pass
->attachments
[i
];
3260 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
3261 VkImageAspectFlags clear_aspects
= 0;
3263 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
3264 /* color attachment */
3265 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
3266 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
3269 /* depthstencil attachment */
3270 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
3271 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
3272 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
3273 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
3274 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_DONT_CARE
)
3275 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
3277 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
3278 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
3279 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
3283 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
3284 state
->attachments
[i
].cleared_views
= 0;
3285 if (clear_aspects
&& info
) {
3286 assert(info
->clearValueCount
> i
);
3287 state
->attachments
[i
].clear_value
= info
->pClearValues
[i
];
3290 state
->attachments
[i
].current_layout
= att
->initial_layout
;
3291 state
->attachments
[i
].current_stencil_layout
= att
->stencil_initial_layout
;
3292 state
->attachments
[i
].sample_location
.count
= 0;
3294 struct radv_image_view
*iview
;
3295 if (attachment_info
&& attachment_info
->attachmentCount
> i
) {
3296 iview
= radv_image_view_from_handle(attachment_info
->pAttachments
[i
]);
3298 iview
= state
->framebuffer
->attachments
[i
];
3301 state
->attachments
[i
].iview
= iview
;
3302 if (iview
->aspect_mask
& (VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3303 radv_initialise_ds_surface(cmd_buffer
->device
, &state
->attachments
[i
].ds
, iview
);
3305 radv_initialise_color_surface(cmd_buffer
->device
, &state
->attachments
[i
].cb
, iview
);
3312 VkResult
radv_AllocateCommandBuffers(
3314 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
3315 VkCommandBuffer
*pCommandBuffers
)
3317 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3318 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
3320 VkResult result
= VK_SUCCESS
;
3323 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
3325 if (!list_is_empty(&pool
->free_cmd_buffers
)) {
3326 struct radv_cmd_buffer
*cmd_buffer
= list_first_entry(&pool
->free_cmd_buffers
, struct radv_cmd_buffer
, pool_link
);
3328 list_del(&cmd_buffer
->pool_link
);
3329 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
3331 result
= radv_reset_cmd_buffer(cmd_buffer
);
3332 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
3333 cmd_buffer
->level
= pAllocateInfo
->level
;
3335 pCommandBuffers
[i
] = radv_cmd_buffer_to_handle(cmd_buffer
);
3337 result
= radv_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
3338 &pCommandBuffers
[i
]);
3340 if (result
!= VK_SUCCESS
)
3344 if (result
!= VK_SUCCESS
) {
3345 radv_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
,
3346 i
, pCommandBuffers
);
3348 /* From the Vulkan 1.0.66 spec:
3350 * "vkAllocateCommandBuffers can be used to create multiple
3351 * command buffers. If the creation of any of those command
3352 * buffers fails, the implementation must destroy all
3353 * successfully created command buffer objects from this
3354 * command, set all entries of the pCommandBuffers array to
3355 * NULL and return the error."
3357 memset(pCommandBuffers
, 0,
3358 sizeof(*pCommandBuffers
) * pAllocateInfo
->commandBufferCount
);
3364 void radv_FreeCommandBuffers(
3366 VkCommandPool commandPool
,
3367 uint32_t commandBufferCount
,
3368 const VkCommandBuffer
*pCommandBuffers
)
3370 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
3371 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
3374 if (cmd_buffer
->pool
) {
3375 list_del(&cmd_buffer
->pool_link
);
3376 list_addtail(&cmd_buffer
->pool_link
, &cmd_buffer
->pool
->free_cmd_buffers
);
3378 radv_cmd_buffer_destroy(cmd_buffer
);
3384 VkResult
radv_ResetCommandBuffer(
3385 VkCommandBuffer commandBuffer
,
3386 VkCommandBufferResetFlags flags
)
3388 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3389 return radv_reset_cmd_buffer(cmd_buffer
);
3392 VkResult
radv_BeginCommandBuffer(
3393 VkCommandBuffer commandBuffer
,
3394 const VkCommandBufferBeginInfo
*pBeginInfo
)
3396 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3397 VkResult result
= VK_SUCCESS
;
3399 if (cmd_buffer
->status
!= RADV_CMD_BUFFER_STATUS_INITIAL
) {
3400 /* If the command buffer has already been resetted with
3401 * vkResetCommandBuffer, no need to do it again.
3403 result
= radv_reset_cmd_buffer(cmd_buffer
);
3404 if (result
!= VK_SUCCESS
)
3408 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
3409 cmd_buffer
->state
.last_primitive_reset_en
= -1;
3410 cmd_buffer
->state
.last_index_type
= -1;
3411 cmd_buffer
->state
.last_num_instances
= -1;
3412 cmd_buffer
->state
.last_vertex_offset
= -1;
3413 cmd_buffer
->state
.last_first_instance
= -1;
3414 cmd_buffer
->state
.predication_type
= -1;
3415 cmd_buffer
->state
.last_sx_ps_downconvert
= -1;
3416 cmd_buffer
->state
.last_sx_blend_opt_epsilon
= -1;
3417 cmd_buffer
->state
.last_sx_blend_opt_control
= -1;
3418 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
3420 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
&&
3421 (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
)) {
3422 assert(pBeginInfo
->pInheritanceInfo
);
3423 cmd_buffer
->state
.framebuffer
= radv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
3424 cmd_buffer
->state
.pass
= radv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
3426 struct radv_subpass
*subpass
=
3427 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
3429 if (cmd_buffer
->state
.framebuffer
) {
3430 result
= radv_cmd_state_setup_attachments(cmd_buffer
, cmd_buffer
->state
.pass
, NULL
);
3431 if (result
!= VK_SUCCESS
)
3435 cmd_buffer
->state
.inherited_pipeline_statistics
=
3436 pBeginInfo
->pInheritanceInfo
->pipelineStatistics
;
3438 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
);
3441 if (unlikely(cmd_buffer
->device
->trace_bo
))
3442 radv_cmd_buffer_trace_emit(cmd_buffer
);
3444 radv_describe_begin_cmd_buffer(cmd_buffer
);
3446 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_RECORDING
;
3451 void radv_CmdBindVertexBuffers(
3452 VkCommandBuffer commandBuffer
,
3453 uint32_t firstBinding
,
3454 uint32_t bindingCount
,
3455 const VkBuffer
* pBuffers
,
3456 const VkDeviceSize
* pOffsets
)
3458 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3459 struct radv_vertex_binding
*vb
= cmd_buffer
->vertex_bindings
;
3460 bool changed
= false;
3462 /* We have to defer setting up vertex buffer since we need the buffer
3463 * stride from the pipeline. */
3465 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
3466 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
3467 uint32_t idx
= firstBinding
+ i
;
3470 (vb
[idx
].buffer
!= radv_buffer_from_handle(pBuffers
[i
]) ||
3471 vb
[idx
].offset
!= pOffsets
[i
])) {
3475 vb
[idx
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
3476 vb
[idx
].offset
= pOffsets
[i
];
3478 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
3479 vb
[idx
].buffer
->bo
);
3483 /* No state changes. */
3487 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_VERTEX_BUFFER
;
3491 vk_to_index_type(VkIndexType type
)
3494 case VK_INDEX_TYPE_UINT8_EXT
:
3495 return V_028A7C_VGT_INDEX_8
;
3496 case VK_INDEX_TYPE_UINT16
:
3497 return V_028A7C_VGT_INDEX_16
;
3498 case VK_INDEX_TYPE_UINT32
:
3499 return V_028A7C_VGT_INDEX_32
;
3501 unreachable("invalid index type");
3506 radv_get_vgt_index_size(uint32_t type
)
3509 case V_028A7C_VGT_INDEX_8
:
3511 case V_028A7C_VGT_INDEX_16
:
3513 case V_028A7C_VGT_INDEX_32
:
3516 unreachable("invalid index type");
3520 void radv_CmdBindIndexBuffer(
3521 VkCommandBuffer commandBuffer
,
3523 VkDeviceSize offset
,
3524 VkIndexType indexType
)
3526 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3527 RADV_FROM_HANDLE(radv_buffer
, index_buffer
, buffer
);
3529 if (cmd_buffer
->state
.index_buffer
== index_buffer
&&
3530 cmd_buffer
->state
.index_offset
== offset
&&
3531 cmd_buffer
->state
.index_type
== indexType
) {
3532 /* No state changes. */
3536 cmd_buffer
->state
.index_buffer
= index_buffer
;
3537 cmd_buffer
->state
.index_offset
= offset
;
3538 cmd_buffer
->state
.index_type
= vk_to_index_type(indexType
);
3539 cmd_buffer
->state
.index_va
= radv_buffer_get_va(index_buffer
->bo
);
3540 cmd_buffer
->state
.index_va
+= index_buffer
->offset
+ offset
;
3542 int index_size
= radv_get_vgt_index_size(vk_to_index_type(indexType
));
3543 cmd_buffer
->state
.max_index_count
= (index_buffer
->size
- offset
) / index_size
;
3544 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
3545 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, index_buffer
->bo
);
3550 radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
3551 VkPipelineBindPoint bind_point
,
3552 struct radv_descriptor_set
*set
, unsigned idx
)
3554 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
3556 radv_set_descriptor_set(cmd_buffer
, bind_point
, set
, idx
);
3559 assert(!(set
->layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
));
3561 if (!cmd_buffer
->device
->use_global_bo_list
) {
3562 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
)
3563 if (set
->descriptors
[j
])
3564 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->descriptors
[j
]);
3568 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->bo
);
3571 void radv_CmdBindDescriptorSets(
3572 VkCommandBuffer commandBuffer
,
3573 VkPipelineBindPoint pipelineBindPoint
,
3574 VkPipelineLayout _layout
,
3576 uint32_t descriptorSetCount
,
3577 const VkDescriptorSet
* pDescriptorSets
,
3578 uint32_t dynamicOffsetCount
,
3579 const uint32_t* pDynamicOffsets
)
3581 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3582 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3583 unsigned dyn_idx
= 0;
3585 const bool no_dynamic_bounds
= cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
3586 struct radv_descriptor_state
*descriptors_state
=
3587 radv_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
3589 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
3590 unsigned idx
= i
+ firstSet
;
3591 RADV_FROM_HANDLE(radv_descriptor_set
, set
, pDescriptorSets
[i
]);
3593 /* If the set is already bound we only need to update the
3594 * (potentially changed) dynamic offsets. */
3595 if (descriptors_state
->sets
[idx
] != set
||
3596 !(descriptors_state
->valid
& (1u << idx
))) {
3597 radv_bind_descriptor_set(cmd_buffer
, pipelineBindPoint
, set
, idx
);
3600 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
3601 unsigned idx
= j
+ layout
->set
[i
+ firstSet
].dynamic_offset_start
;
3602 uint32_t *dst
= descriptors_state
->dynamic_buffers
+ idx
* 4;
3603 assert(dyn_idx
< dynamicOffsetCount
);
3605 struct radv_descriptor_range
*range
= set
->dynamic_descriptors
+ j
;
3606 uint64_t va
= range
->va
+ pDynamicOffsets
[dyn_idx
];
3608 dst
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
3609 dst
[2] = no_dynamic_bounds
? 0xffffffffu
: range
->size
;
3610 dst
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3611 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3612 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3613 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3615 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3616 dst
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3617 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
3618 S_008F0C_RESOURCE_LEVEL(1);
3620 dst
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3621 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3624 cmd_buffer
->push_constant_stages
|=
3625 set
->layout
->dynamic_shader_stages
;
3630 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
3631 struct radv_descriptor_set
*set
,
3632 struct radv_descriptor_set_layout
*layout
,
3633 VkPipelineBindPoint bind_point
)
3635 struct radv_descriptor_state
*descriptors_state
=
3636 radv_get_descriptors_state(cmd_buffer
, bind_point
);
3637 set
->size
= layout
->size
;
3638 set
->layout
= layout
;
3640 if (descriptors_state
->push_set
.capacity
< set
->size
) {
3641 size_t new_size
= MAX2(set
->size
, 1024);
3642 new_size
= MAX2(new_size
, 2 * descriptors_state
->push_set
.capacity
);
3643 new_size
= MIN2(new_size
, 96 * MAX_PUSH_DESCRIPTORS
);
3645 free(set
->mapped_ptr
);
3646 set
->mapped_ptr
= malloc(new_size
);
3648 if (!set
->mapped_ptr
) {
3649 descriptors_state
->push_set
.capacity
= 0;
3650 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
3654 descriptors_state
->push_set
.capacity
= new_size
;
3660 void radv_meta_push_descriptor_set(
3661 struct radv_cmd_buffer
* cmd_buffer
,
3662 VkPipelineBindPoint pipelineBindPoint
,
3663 VkPipelineLayout _layout
,
3665 uint32_t descriptorWriteCount
,
3666 const VkWriteDescriptorSet
* pDescriptorWrites
)
3668 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3669 struct radv_descriptor_set
*push_set
= &cmd_buffer
->meta_push_descriptors
;
3673 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
3675 push_set
->size
= layout
->set
[set
].layout
->size
;
3676 push_set
->layout
= layout
->set
[set
].layout
;
3678 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, push_set
->size
, 32,
3680 (void**) &push_set
->mapped_ptr
))
3683 push_set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
3684 push_set
->va
+= bo_offset
;
3686 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
3687 radv_descriptor_set_to_handle(push_set
),
3688 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
3690 radv_set_descriptor_set(cmd_buffer
, pipelineBindPoint
, push_set
, set
);
3693 void radv_CmdPushDescriptorSetKHR(
3694 VkCommandBuffer commandBuffer
,
3695 VkPipelineBindPoint pipelineBindPoint
,
3696 VkPipelineLayout _layout
,
3698 uint32_t descriptorWriteCount
,
3699 const VkWriteDescriptorSet
* pDescriptorWrites
)
3701 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3702 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3703 struct radv_descriptor_state
*descriptors_state
=
3704 radv_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
3705 struct radv_descriptor_set
*push_set
= &descriptors_state
->push_set
.set
;
3707 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
3709 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
,
3710 layout
->set
[set
].layout
,
3714 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3715 * because it is invalid, according to Vulkan spec.
3717 for (int i
= 0; i
< descriptorWriteCount
; i
++) {
3718 ASSERTED
const VkWriteDescriptorSet
*writeset
= &pDescriptorWrites
[i
];
3719 assert(writeset
->descriptorType
!= VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
);
3722 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
3723 radv_descriptor_set_to_handle(push_set
),
3724 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
3726 radv_set_descriptor_set(cmd_buffer
, pipelineBindPoint
, push_set
, set
);
3727 descriptors_state
->push_dirty
= true;
3730 void radv_CmdPushDescriptorSetWithTemplateKHR(
3731 VkCommandBuffer commandBuffer
,
3732 VkDescriptorUpdateTemplate descriptorUpdateTemplate
,
3733 VkPipelineLayout _layout
,
3737 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3738 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3739 RADV_FROM_HANDLE(radv_descriptor_update_template
, templ
, descriptorUpdateTemplate
);
3740 struct radv_descriptor_state
*descriptors_state
=
3741 radv_get_descriptors_state(cmd_buffer
, templ
->bind_point
);
3742 struct radv_descriptor_set
*push_set
= &descriptors_state
->push_set
.set
;
3744 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
3746 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
,
3747 layout
->set
[set
].layout
,
3751 radv_update_descriptor_set_with_template(cmd_buffer
->device
, cmd_buffer
, push_set
,
3752 descriptorUpdateTemplate
, pData
);
3754 radv_set_descriptor_set(cmd_buffer
, templ
->bind_point
, push_set
, set
);
3755 descriptors_state
->push_dirty
= true;
3758 void radv_CmdPushConstants(VkCommandBuffer commandBuffer
,
3759 VkPipelineLayout layout
,
3760 VkShaderStageFlags stageFlags
,
3763 const void* pValues
)
3765 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3766 memcpy(cmd_buffer
->push_constants
+ offset
, pValues
, size
);
3767 cmd_buffer
->push_constant_stages
|= stageFlags
;
3770 VkResult
radv_EndCommandBuffer(
3771 VkCommandBuffer commandBuffer
)
3773 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3775 if (cmd_buffer
->queue_family_index
!= RADV_QUEUE_TRANSFER
) {
3776 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX6
)
3777 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
| RADV_CMD_FLAG_WB_L2
;
3779 /* Make sure to sync all pending active queries at the end of
3782 cmd_buffer
->state
.flush_bits
|= cmd_buffer
->active_query_flush_bits
;
3784 /* Since NGG streamout uses GDS, we need to make GDS idle when
3785 * we leave the IB, otherwise another process might overwrite
3786 * it while our shaders are busy.
3788 if (cmd_buffer
->gds_needed
)
3789 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
3791 si_emit_cache_flush(cmd_buffer
);
3794 /* Make sure CP DMA is idle at the end of IBs because the kernel
3795 * doesn't wait for it.
3797 si_cp_dma_wait_for_idle(cmd_buffer
);
3799 radv_describe_end_cmd_buffer(cmd_buffer
);
3801 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
3802 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.subpass_sample_locs
);
3804 if (!cmd_buffer
->device
->ws
->cs_finalize(cmd_buffer
->cs
))
3805 return vk_error(cmd_buffer
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3807 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_EXECUTABLE
;
3809 return cmd_buffer
->record_result
;
3813 radv_emit_compute_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
3815 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
3817 if (!pipeline
|| pipeline
== cmd_buffer
->state
.emitted_compute_pipeline
)
3820 assert(!pipeline
->ctx_cs
.cdw
);
3822 cmd_buffer
->state
.emitted_compute_pipeline
= pipeline
;
3824 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, pipeline
->cs
.cdw
);
3825 radeon_emit_array(cmd_buffer
->cs
, pipeline
->cs
.buf
, pipeline
->cs
.cdw
);
3827 cmd_buffer
->compute_scratch_size_per_wave_needed
= MAX2(cmd_buffer
->compute_scratch_size_per_wave_needed
,
3828 pipeline
->scratch_bytes_per_wave
);
3829 cmd_buffer
->compute_scratch_waves_wanted
= MAX2(cmd_buffer
->compute_scratch_waves_wanted
,
3830 pipeline
->max_waves
);
3832 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
3833 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->bo
);
3835 if (unlikely(cmd_buffer
->device
->trace_bo
))
3836 radv_save_pipeline(cmd_buffer
, pipeline
, RING_COMPUTE
);
3839 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer
*cmd_buffer
,
3840 VkPipelineBindPoint bind_point
)
3842 struct radv_descriptor_state
*descriptors_state
=
3843 radv_get_descriptors_state(cmd_buffer
, bind_point
);
3845 descriptors_state
->dirty
|= descriptors_state
->valid
;
3848 void radv_CmdBindPipeline(
3849 VkCommandBuffer commandBuffer
,
3850 VkPipelineBindPoint pipelineBindPoint
,
3851 VkPipeline _pipeline
)
3853 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3854 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
3856 switch (pipelineBindPoint
) {
3857 case VK_PIPELINE_BIND_POINT_COMPUTE
:
3858 if (cmd_buffer
->state
.compute_pipeline
== pipeline
)
3860 radv_mark_descriptor_sets_dirty(cmd_buffer
, pipelineBindPoint
);
3862 cmd_buffer
->state
.compute_pipeline
= pipeline
;
3863 cmd_buffer
->push_constant_stages
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3865 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
3866 if (cmd_buffer
->state
.pipeline
== pipeline
)
3868 radv_mark_descriptor_sets_dirty(cmd_buffer
, pipelineBindPoint
);
3870 cmd_buffer
->state
.pipeline
= pipeline
;
3874 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
;
3875 cmd_buffer
->push_constant_stages
|= pipeline
->active_stages
;
3877 /* the new vertex shader might not have the same user regs */
3878 cmd_buffer
->state
.last_first_instance
= -1;
3879 cmd_buffer
->state
.last_vertex_offset
= -1;
3881 /* Prefetch all pipeline shaders at first draw time. */
3882 cmd_buffer
->state
.prefetch_L2_mask
|= RADV_PREFETCH_SHADERS
;
3884 if ((cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_NAVI10
||
3885 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_NAVI12
||
3886 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_NAVI14
) &&
3887 cmd_buffer
->state
.emitted_pipeline
&&
3888 radv_pipeline_has_ngg(cmd_buffer
->state
.emitted_pipeline
) &&
3889 !radv_pipeline_has_ngg(cmd_buffer
->state
.pipeline
)) {
3890 /* Transitioning from NGG to legacy GS requires
3891 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
3892 * at the beginning of IBs when legacy GS ring pointers
3895 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VGT_FLUSH
;
3898 radv_bind_dynamic_state(cmd_buffer
, &pipeline
->dynamic_state
);
3899 radv_bind_streamout_state(cmd_buffer
, pipeline
);
3901 if (pipeline
->graphics
.esgs_ring_size
> cmd_buffer
->esgs_ring_size_needed
)
3902 cmd_buffer
->esgs_ring_size_needed
= pipeline
->graphics
.esgs_ring_size
;
3903 if (pipeline
->graphics
.gsvs_ring_size
> cmd_buffer
->gsvs_ring_size_needed
)
3904 cmd_buffer
->gsvs_ring_size_needed
= pipeline
->graphics
.gsvs_ring_size
;
3906 if (radv_pipeline_has_tess(pipeline
))
3907 cmd_buffer
->tess_rings_needed
= true;
3910 assert(!"invalid bind point");
3915 void radv_CmdSetViewport(
3916 VkCommandBuffer commandBuffer
,
3917 uint32_t firstViewport
,
3918 uint32_t viewportCount
,
3919 const VkViewport
* pViewports
)
3921 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3922 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3923 ASSERTED
const uint32_t total_count
= firstViewport
+ viewportCount
;
3925 assert(firstViewport
< MAX_VIEWPORTS
);
3926 assert(total_count
>= 1 && total_count
<= MAX_VIEWPORTS
);
3928 if (!memcmp(state
->dynamic
.viewport
.viewports
+ firstViewport
,
3929 pViewports
, viewportCount
* sizeof(*pViewports
))) {
3933 memcpy(state
->dynamic
.viewport
.viewports
+ firstViewport
, pViewports
,
3934 viewportCount
* sizeof(*pViewports
));
3936 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
3939 void radv_CmdSetScissor(
3940 VkCommandBuffer commandBuffer
,
3941 uint32_t firstScissor
,
3942 uint32_t scissorCount
,
3943 const VkRect2D
* pScissors
)
3945 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3946 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3947 ASSERTED
const uint32_t total_count
= firstScissor
+ scissorCount
;
3949 assert(firstScissor
< MAX_SCISSORS
);
3950 assert(total_count
>= 1 && total_count
<= MAX_SCISSORS
);
3952 if (!memcmp(state
->dynamic
.scissor
.scissors
+ firstScissor
, pScissors
,
3953 scissorCount
* sizeof(*pScissors
))) {
3957 memcpy(state
->dynamic
.scissor
.scissors
+ firstScissor
, pScissors
,
3958 scissorCount
* sizeof(*pScissors
));
3960 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
3963 void radv_CmdSetLineWidth(
3964 VkCommandBuffer commandBuffer
,
3967 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3969 if (cmd_buffer
->state
.dynamic
.line_width
== lineWidth
)
3972 cmd_buffer
->state
.dynamic
.line_width
= lineWidth
;
3973 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
3976 void radv_CmdSetDepthBias(
3977 VkCommandBuffer commandBuffer
,
3978 float depthBiasConstantFactor
,
3979 float depthBiasClamp
,
3980 float depthBiasSlopeFactor
)
3982 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3983 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3985 if (state
->dynamic
.depth_bias
.bias
== depthBiasConstantFactor
&&
3986 state
->dynamic
.depth_bias
.clamp
== depthBiasClamp
&&
3987 state
->dynamic
.depth_bias
.slope
== depthBiasSlopeFactor
) {
3991 state
->dynamic
.depth_bias
.bias
= depthBiasConstantFactor
;
3992 state
->dynamic
.depth_bias
.clamp
= depthBiasClamp
;
3993 state
->dynamic
.depth_bias
.slope
= depthBiasSlopeFactor
;
3995 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
3998 void radv_CmdSetBlendConstants(
3999 VkCommandBuffer commandBuffer
,
4000 const float blendConstants
[4])
4002 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4003 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4005 if (!memcmp(state
->dynamic
.blend_constants
, blendConstants
, sizeof(float) * 4))
4008 memcpy(state
->dynamic
.blend_constants
, blendConstants
, sizeof(float) * 4);
4010 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
4013 void radv_CmdSetDepthBounds(
4014 VkCommandBuffer commandBuffer
,
4015 float minDepthBounds
,
4016 float maxDepthBounds
)
4018 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4019 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4021 if (state
->dynamic
.depth_bounds
.min
== minDepthBounds
&&
4022 state
->dynamic
.depth_bounds
.max
== maxDepthBounds
) {
4026 state
->dynamic
.depth_bounds
.min
= minDepthBounds
;
4027 state
->dynamic
.depth_bounds
.max
= maxDepthBounds
;
4029 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
4032 void radv_CmdSetStencilCompareMask(
4033 VkCommandBuffer commandBuffer
,
4034 VkStencilFaceFlags faceMask
,
4035 uint32_t compareMask
)
4037 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4038 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4039 bool front_same
= state
->dynamic
.stencil_compare_mask
.front
== compareMask
;
4040 bool back_same
= state
->dynamic
.stencil_compare_mask
.back
== compareMask
;
4042 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
4043 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
)) {
4047 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
4048 state
->dynamic
.stencil_compare_mask
.front
= compareMask
;
4049 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
4050 state
->dynamic
.stencil_compare_mask
.back
= compareMask
;
4052 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
4055 void radv_CmdSetStencilWriteMask(
4056 VkCommandBuffer commandBuffer
,
4057 VkStencilFaceFlags faceMask
,
4060 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4061 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4062 bool front_same
= state
->dynamic
.stencil_write_mask
.front
== writeMask
;
4063 bool back_same
= state
->dynamic
.stencil_write_mask
.back
== writeMask
;
4065 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
4066 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
)) {
4070 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
4071 state
->dynamic
.stencil_write_mask
.front
= writeMask
;
4072 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
4073 state
->dynamic
.stencil_write_mask
.back
= writeMask
;
4075 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
4078 void radv_CmdSetStencilReference(
4079 VkCommandBuffer commandBuffer
,
4080 VkStencilFaceFlags faceMask
,
4083 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4084 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4085 bool front_same
= state
->dynamic
.stencil_reference
.front
== reference
;
4086 bool back_same
= state
->dynamic
.stencil_reference
.back
== reference
;
4088 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
4089 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
)) {
4093 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
4094 cmd_buffer
->state
.dynamic
.stencil_reference
.front
= reference
;
4095 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
4096 cmd_buffer
->state
.dynamic
.stencil_reference
.back
= reference
;
4098 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
4101 void radv_CmdSetDiscardRectangleEXT(
4102 VkCommandBuffer commandBuffer
,
4103 uint32_t firstDiscardRectangle
,
4104 uint32_t discardRectangleCount
,
4105 const VkRect2D
* pDiscardRectangles
)
4107 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4108 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4109 ASSERTED
const uint32_t total_count
= firstDiscardRectangle
+ discardRectangleCount
;
4111 assert(firstDiscardRectangle
< MAX_DISCARD_RECTANGLES
);
4112 assert(total_count
>= 1 && total_count
<= MAX_DISCARD_RECTANGLES
);
4114 if (!memcmp(state
->dynamic
.discard_rectangle
.rectangles
+ firstDiscardRectangle
,
4115 pDiscardRectangles
, discardRectangleCount
* sizeof(*pDiscardRectangles
))) {
4119 typed_memcpy(&state
->dynamic
.discard_rectangle
.rectangles
[firstDiscardRectangle
],
4120 pDiscardRectangles
, discardRectangleCount
);
4122 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
;
4125 void radv_CmdSetSampleLocationsEXT(
4126 VkCommandBuffer commandBuffer
,
4127 const VkSampleLocationsInfoEXT
* pSampleLocationsInfo
)
4129 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4130 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4132 assert(pSampleLocationsInfo
->sampleLocationsCount
<= MAX_SAMPLE_LOCATIONS
);
4134 state
->dynamic
.sample_location
.per_pixel
= pSampleLocationsInfo
->sampleLocationsPerPixel
;
4135 state
->dynamic
.sample_location
.grid_size
= pSampleLocationsInfo
->sampleLocationGridSize
;
4136 state
->dynamic
.sample_location
.count
= pSampleLocationsInfo
->sampleLocationsCount
;
4137 typed_memcpy(&state
->dynamic
.sample_location
.locations
[0],
4138 pSampleLocationsInfo
->pSampleLocations
,
4139 pSampleLocationsInfo
->sampleLocationsCount
);
4141 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
;
4144 void radv_CmdSetLineStippleEXT(
4145 VkCommandBuffer commandBuffer
,
4146 uint32_t lineStippleFactor
,
4147 uint16_t lineStipplePattern
)
4149 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4150 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4152 state
->dynamic
.line_stipple
.factor
= lineStippleFactor
;
4153 state
->dynamic
.line_stipple
.pattern
= lineStipplePattern
;
4155 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
;
4158 void radv_CmdExecuteCommands(
4159 VkCommandBuffer commandBuffer
,
4160 uint32_t commandBufferCount
,
4161 const VkCommandBuffer
* pCmdBuffers
)
4163 RADV_FROM_HANDLE(radv_cmd_buffer
, primary
, commandBuffer
);
4165 assert(commandBufferCount
> 0);
4167 /* Emit pending flushes on primary prior to executing secondary */
4168 si_emit_cache_flush(primary
);
4170 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
4171 RADV_FROM_HANDLE(radv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
4173 primary
->scratch_size_per_wave_needed
= MAX2(primary
->scratch_size_per_wave_needed
,
4174 secondary
->scratch_size_per_wave_needed
);
4175 primary
->scratch_waves_wanted
= MAX2(primary
->scratch_waves_wanted
,
4176 secondary
->scratch_waves_wanted
);
4177 primary
->compute_scratch_size_per_wave_needed
= MAX2(primary
->compute_scratch_size_per_wave_needed
,
4178 secondary
->compute_scratch_size_per_wave_needed
);
4179 primary
->compute_scratch_waves_wanted
= MAX2(primary
->compute_scratch_waves_wanted
,
4180 secondary
->compute_scratch_waves_wanted
);
4182 if (secondary
->esgs_ring_size_needed
> primary
->esgs_ring_size_needed
)
4183 primary
->esgs_ring_size_needed
= secondary
->esgs_ring_size_needed
;
4184 if (secondary
->gsvs_ring_size_needed
> primary
->gsvs_ring_size_needed
)
4185 primary
->gsvs_ring_size_needed
= secondary
->gsvs_ring_size_needed
;
4186 if (secondary
->tess_rings_needed
)
4187 primary
->tess_rings_needed
= true;
4188 if (secondary
->sample_positions_needed
)
4189 primary
->sample_positions_needed
= true;
4190 if (secondary
->gds_needed
)
4191 primary
->gds_needed
= true;
4193 if (!secondary
->state
.framebuffer
&&
4194 (primary
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
)) {
4195 /* Emit the framebuffer state from primary if secondary
4196 * has been recorded without a framebuffer, otherwise
4197 * fast color/depth clears can't work.
4199 radv_emit_framebuffer_state(primary
);
4202 primary
->device
->ws
->cs_execute_secondary(primary
->cs
, secondary
->cs
);
4205 /* When the secondary command buffer is compute only we don't
4206 * need to re-emit the current graphics pipeline.
4208 if (secondary
->state
.emitted_pipeline
) {
4209 primary
->state
.emitted_pipeline
=
4210 secondary
->state
.emitted_pipeline
;
4213 /* When the secondary command buffer is graphics only we don't
4214 * need to re-emit the current compute pipeline.
4216 if (secondary
->state
.emitted_compute_pipeline
) {
4217 primary
->state
.emitted_compute_pipeline
=
4218 secondary
->state
.emitted_compute_pipeline
;
4221 /* Only re-emit the draw packets when needed. */
4222 if (secondary
->state
.last_primitive_reset_en
!= -1) {
4223 primary
->state
.last_primitive_reset_en
=
4224 secondary
->state
.last_primitive_reset_en
;
4227 if (secondary
->state
.last_primitive_reset_index
) {
4228 primary
->state
.last_primitive_reset_index
=
4229 secondary
->state
.last_primitive_reset_index
;
4232 if (secondary
->state
.last_ia_multi_vgt_param
) {
4233 primary
->state
.last_ia_multi_vgt_param
=
4234 secondary
->state
.last_ia_multi_vgt_param
;
4237 primary
->state
.last_first_instance
= secondary
->state
.last_first_instance
;
4238 primary
->state
.last_num_instances
= secondary
->state
.last_num_instances
;
4239 primary
->state
.last_vertex_offset
= secondary
->state
.last_vertex_offset
;
4240 primary
->state
.last_sx_ps_downconvert
= secondary
->state
.last_sx_ps_downconvert
;
4241 primary
->state
.last_sx_blend_opt_epsilon
= secondary
->state
.last_sx_blend_opt_epsilon
;
4242 primary
->state
.last_sx_blend_opt_control
= secondary
->state
.last_sx_blend_opt_control
;
4244 if (secondary
->state
.last_index_type
!= -1) {
4245 primary
->state
.last_index_type
=
4246 secondary
->state
.last_index_type
;
4250 /* After executing commands from secondary buffers we have to dirty
4253 primary
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
|
4254 RADV_CMD_DIRTY_INDEX_BUFFER
|
4255 RADV_CMD_DIRTY_DYNAMIC_ALL
;
4256 radv_mark_descriptor_sets_dirty(primary
, VK_PIPELINE_BIND_POINT_GRAPHICS
);
4257 radv_mark_descriptor_sets_dirty(primary
, VK_PIPELINE_BIND_POINT_COMPUTE
);
4260 VkResult
radv_CreateCommandPool(
4262 const VkCommandPoolCreateInfo
* pCreateInfo
,
4263 const VkAllocationCallbacks
* pAllocator
,
4264 VkCommandPool
* pCmdPool
)
4266 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4267 struct radv_cmd_pool
*pool
;
4269 pool
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
4270 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4272 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4275 pool
->alloc
= *pAllocator
;
4277 pool
->alloc
= device
->alloc
;
4279 list_inithead(&pool
->cmd_buffers
);
4280 list_inithead(&pool
->free_cmd_buffers
);
4282 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
4284 *pCmdPool
= radv_cmd_pool_to_handle(pool
);
4290 void radv_DestroyCommandPool(
4292 VkCommandPool commandPool
,
4293 const VkAllocationCallbacks
* pAllocator
)
4295 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4296 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
4301 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
4302 &pool
->cmd_buffers
, pool_link
) {
4303 radv_cmd_buffer_destroy(cmd_buffer
);
4306 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
4307 &pool
->free_cmd_buffers
, pool_link
) {
4308 radv_cmd_buffer_destroy(cmd_buffer
);
4311 vk_free2(&device
->alloc
, pAllocator
, pool
);
4314 VkResult
radv_ResetCommandPool(
4316 VkCommandPool commandPool
,
4317 VkCommandPoolResetFlags flags
)
4319 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
4322 list_for_each_entry(struct radv_cmd_buffer
, cmd_buffer
,
4323 &pool
->cmd_buffers
, pool_link
) {
4324 result
= radv_reset_cmd_buffer(cmd_buffer
);
4325 if (result
!= VK_SUCCESS
)
4332 void radv_TrimCommandPool(
4334 VkCommandPool commandPool
,
4335 VkCommandPoolTrimFlags flags
)
4337 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
4342 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
4343 &pool
->free_cmd_buffers
, pool_link
) {
4344 radv_cmd_buffer_destroy(cmd_buffer
);
4349 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer
*cmd_buffer
,
4350 uint32_t subpass_id
)
4352 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4353 struct radv_subpass
*subpass
= &state
->pass
->subpasses
[subpass_id
];
4355 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
4356 cmd_buffer
->cs
, 4096);
4358 radv_subpass_barrier(cmd_buffer
, &subpass
->start_barrier
);
4360 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
);
4362 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4363 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4364 if (a
== VK_ATTACHMENT_UNUSED
)
4367 radv_handle_subpass_image_transition(cmd_buffer
,
4368 subpass
->attachments
[i
],
4372 radv_cmd_buffer_clear_subpass(cmd_buffer
);
4374 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4378 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer
*cmd_buffer
)
4380 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4381 const struct radv_subpass
*subpass
= state
->subpass
;
4382 uint32_t subpass_id
= radv_get_subpass_id(cmd_buffer
);
4384 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
4386 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4387 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4388 if (a
== VK_ATTACHMENT_UNUSED
)
4391 if (state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
4394 VkImageLayout layout
= state
->pass
->attachments
[a
].final_layout
;
4395 VkImageLayout stencil_layout
= state
->pass
->attachments
[a
].stencil_final_layout
;
4396 struct radv_subpass_attachment att
= { a
, layout
, stencil_layout
};
4397 radv_handle_subpass_image_transition(cmd_buffer
, att
, false);
4401 void radv_CmdBeginRenderPass(
4402 VkCommandBuffer commandBuffer
,
4403 const VkRenderPassBeginInfo
* pRenderPassBegin
,
4404 VkSubpassContents contents
)
4406 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4407 RADV_FROM_HANDLE(radv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
4408 RADV_FROM_HANDLE(radv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
4411 cmd_buffer
->state
.framebuffer
= framebuffer
;
4412 cmd_buffer
->state
.pass
= pass
;
4413 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
4415 result
= radv_cmd_state_setup_attachments(cmd_buffer
, pass
, pRenderPassBegin
);
4416 if (result
!= VK_SUCCESS
)
4419 result
= radv_cmd_state_setup_sample_locations(cmd_buffer
, pass
, pRenderPassBegin
);
4420 if (result
!= VK_SUCCESS
)
4423 radv_cmd_buffer_begin_subpass(cmd_buffer
, 0);
4426 void radv_CmdBeginRenderPass2(
4427 VkCommandBuffer commandBuffer
,
4428 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
4429 const VkSubpassBeginInfo
* pSubpassBeginInfo
)
4431 radv_CmdBeginRenderPass(commandBuffer
, pRenderPassBeginInfo
,
4432 pSubpassBeginInfo
->contents
);
4435 void radv_CmdNextSubpass(
4436 VkCommandBuffer commandBuffer
,
4437 VkSubpassContents contents
)
4439 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4441 uint32_t prev_subpass
= radv_get_subpass_id(cmd_buffer
);
4442 radv_cmd_buffer_end_subpass(cmd_buffer
);
4443 radv_cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
4446 void radv_CmdNextSubpass2(
4447 VkCommandBuffer commandBuffer
,
4448 const VkSubpassBeginInfo
* pSubpassBeginInfo
,
4449 const VkSubpassEndInfo
* pSubpassEndInfo
)
4451 radv_CmdNextSubpass(commandBuffer
, pSubpassBeginInfo
->contents
);
4454 static void radv_emit_view_index(struct radv_cmd_buffer
*cmd_buffer
, unsigned index
)
4456 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
4457 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
4458 if (!radv_get_shader(pipeline
, stage
))
4461 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, AC_UD_VIEW_INDEX
);
4462 if (loc
->sgpr_idx
== -1)
4464 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
4465 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
4468 if (radv_pipeline_has_gs_copy_shader(pipeline
)) {
4469 struct radv_userdata_info
*loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_VIEW_INDEX
];
4470 if (loc
->sgpr_idx
!= -1) {
4471 uint32_t base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
4472 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
4478 radv_cs_emit_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
4479 uint32_t vertex_count
,
4482 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, cmd_buffer
->state
.predicating
));
4483 radeon_emit(cmd_buffer
->cs
, vertex_count
);
4484 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
4485 S_0287F0_USE_OPAQUE(use_opaque
));
4489 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer
*cmd_buffer
,
4491 uint32_t index_count
)
4493 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, cmd_buffer
->state
.predicating
));
4494 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.max_index_count
);
4495 radeon_emit(cmd_buffer
->cs
, index_va
);
4496 radeon_emit(cmd_buffer
->cs
, index_va
>> 32);
4497 radeon_emit(cmd_buffer
->cs
, index_count
);
4498 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_DMA
);
4502 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
4504 uint32_t draw_count
,
4508 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4509 unsigned di_src_sel
= indexed
? V_0287F0_DI_SRC_SEL_DMA
4510 : V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
4511 bool draw_id_enable
= radv_get_shader(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
)->info
.vs
.needs_draw_id
;
4512 uint32_t base_reg
= cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
;
4513 bool predicating
= cmd_buffer
->state
.predicating
;
4516 /* just reset draw state for vertex data */
4517 cmd_buffer
->state
.last_first_instance
= -1;
4518 cmd_buffer
->state
.last_num_instances
= -1;
4519 cmd_buffer
->state
.last_vertex_offset
= -1;
4521 if (draw_count
== 1 && !count_va
&& !draw_id_enable
) {
4522 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT
:
4523 PKT3_DRAW_INDIRECT
, 3, predicating
));
4525 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
4526 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
4527 radeon_emit(cs
, di_src_sel
);
4529 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT_MULTI
:
4530 PKT3_DRAW_INDIRECT_MULTI
,
4533 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
4534 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
4535 radeon_emit(cs
, (((base_reg
+ 8) - SI_SH_REG_OFFSET
) >> 2) |
4536 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable
) |
4537 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va
));
4538 radeon_emit(cs
, draw_count
); /* count */
4539 radeon_emit(cs
, count_va
); /* count_addr */
4540 radeon_emit(cs
, count_va
>> 32);
4541 radeon_emit(cs
, stride
); /* stride */
4542 radeon_emit(cs
, di_src_sel
);
4547 radv_emit_draw_packets(struct radv_cmd_buffer
*cmd_buffer
,
4548 const struct radv_draw_info
*info
)
4550 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4551 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
4552 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4554 if (info
->indirect
) {
4555 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
4556 uint64_t count_va
= 0;
4558 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
4560 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
);
4562 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
4564 radeon_emit(cs
, va
);
4565 radeon_emit(cs
, va
>> 32);
4567 if (info
->count_buffer
) {
4568 count_va
= radv_buffer_get_va(info
->count_buffer
->bo
);
4569 count_va
+= info
->count_buffer
->offset
+
4570 info
->count_buffer_offset
;
4572 radv_cs_add_buffer(ws
, cs
, info
->count_buffer
->bo
);
4575 if (!state
->subpass
->view_mask
) {
4576 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
4583 for_each_bit(i
, state
->subpass
->view_mask
) {
4584 radv_emit_view_index(cmd_buffer
, i
);
4586 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
4594 assert(state
->pipeline
->graphics
.vtx_base_sgpr
);
4596 if (info
->vertex_offset
!= state
->last_vertex_offset
||
4597 info
->first_instance
!= state
->last_first_instance
) {
4598 radeon_set_sh_reg_seq(cs
, state
->pipeline
->graphics
.vtx_base_sgpr
,
4599 state
->pipeline
->graphics
.vtx_emit_num
);
4601 radeon_emit(cs
, info
->vertex_offset
);
4602 radeon_emit(cs
, info
->first_instance
);
4603 if (state
->pipeline
->graphics
.vtx_emit_num
== 3)
4605 state
->last_first_instance
= info
->first_instance
;
4606 state
->last_vertex_offset
= info
->vertex_offset
;
4609 if (state
->last_num_instances
!= info
->instance_count
) {
4610 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, false));
4611 radeon_emit(cs
, info
->instance_count
);
4612 state
->last_num_instances
= info
->instance_count
;
4615 if (info
->indexed
) {
4616 int index_size
= radv_get_vgt_index_size(state
->index_type
);
4619 /* Skip draw calls with 0-sized index buffers. They
4620 * cause a hang on some chips, like Navi10-14.
4622 if (!cmd_buffer
->state
.max_index_count
)
4625 index_va
= state
->index_va
;
4626 index_va
+= info
->first_index
* index_size
;
4628 if (!state
->subpass
->view_mask
) {
4629 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
4634 for_each_bit(i
, state
->subpass
->view_mask
) {
4635 radv_emit_view_index(cmd_buffer
, i
);
4637 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
4643 if (!state
->subpass
->view_mask
) {
4644 radv_cs_emit_draw_packet(cmd_buffer
,
4646 !!info
->strmout_buffer
);
4649 for_each_bit(i
, state
->subpass
->view_mask
) {
4650 radv_emit_view_index(cmd_buffer
, i
);
4652 radv_cs_emit_draw_packet(cmd_buffer
,
4654 !!info
->strmout_buffer
);
4662 * Vega and raven have a bug which triggers if there are multiple context
4663 * register contexts active at the same time with different scissor values.
4665 * There are two possible workarounds:
4666 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4667 * there is only ever 1 active set of scissor values at the same time.
4669 * 2) Whenever the hardware switches contexts we have to set the scissor
4670 * registers again even if it is a noop. That way the new context gets
4671 * the correct scissor values.
4673 * This implements option 2. radv_need_late_scissor_emission needs to
4674 * return true on affected HW if radv_emit_all_graphics_states sets
4675 * any context registers.
4677 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer
*cmd_buffer
,
4678 const struct radv_draw_info
*info
)
4680 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4682 if (!cmd_buffer
->device
->physical_device
->rad_info
.has_gfx9_scissor_bug
)
4685 if (cmd_buffer
->state
.context_roll_without_scissor_emitted
|| info
->strmout_buffer
)
4688 uint32_t used_states
= cmd_buffer
->state
.pipeline
->graphics
.needed_dynamic_state
| ~RADV_CMD_DIRTY_DYNAMIC_ALL
;
4690 /* Index, vertex and streamout buffers don't change context regs, and
4691 * pipeline is already handled.
4693 used_states
&= ~(RADV_CMD_DIRTY_INDEX_BUFFER
|
4694 RADV_CMD_DIRTY_VERTEX_BUFFER
|
4695 RADV_CMD_DIRTY_STREAMOUT_BUFFER
|
4696 RADV_CMD_DIRTY_PIPELINE
);
4698 if (cmd_buffer
->state
.dirty
& used_states
)
4701 uint32_t primitive_reset_index
=
4702 radv_get_primitive_reset_index(cmd_buffer
);
4704 if (info
->indexed
&& state
->pipeline
->graphics
.prim_restart_enable
&&
4705 primitive_reset_index
!= state
->last_primitive_reset_index
)
4712 radv_emit_all_graphics_states(struct radv_cmd_buffer
*cmd_buffer
,
4713 const struct radv_draw_info
*info
)
4715 bool late_scissor_emission
;
4717 if ((cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
) ||
4718 cmd_buffer
->state
.emitted_pipeline
!= cmd_buffer
->state
.pipeline
)
4719 radv_emit_rbplus_state(cmd_buffer
);
4721 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
)
4722 radv_emit_graphics_pipeline(cmd_buffer
);
4724 /* This should be before the cmd_buffer->state.dirty is cleared
4725 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4726 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4727 late_scissor_emission
=
4728 radv_need_late_scissor_emission(cmd_buffer
, info
);
4730 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
)
4731 radv_emit_framebuffer_state(cmd_buffer
);
4733 if (info
->indexed
) {
4734 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_INDEX_BUFFER
)
4735 radv_emit_index_buffer(cmd_buffer
, info
->indirect
);
4737 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4738 * so the state must be re-emitted before the next indexed
4741 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4742 cmd_buffer
->state
.last_index_type
= -1;
4743 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
4747 radv_cmd_buffer_flush_dynamic_state(cmd_buffer
);
4749 radv_emit_draw_registers(cmd_buffer
, info
);
4751 if (late_scissor_emission
)
4752 radv_emit_scissor(cmd_buffer
);
4756 radv_draw(struct radv_cmd_buffer
*cmd_buffer
,
4757 const struct radv_draw_info
*info
)
4759 struct radeon_info
*rad_info
=
4760 &cmd_buffer
->device
->physical_device
->rad_info
;
4762 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
4763 bool pipeline_is_dirty
=
4764 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
) &&
4765 cmd_buffer
->state
.pipeline
!= cmd_buffer
->state
.emitted_pipeline
;
4767 ASSERTED
unsigned cdw_max
=
4768 radeon_check_space(cmd_buffer
->device
->ws
,
4769 cmd_buffer
->cs
, 4096);
4771 if (likely(!info
->indirect
)) {
4772 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4773 * no workaround for indirect draws, but we can at least skip
4776 if (unlikely(!info
->instance_count
))
4779 /* Handle count == 0. */
4780 if (unlikely(!info
->count
&& !info
->strmout_buffer
))
4784 /* Use optimal packet order based on whether we need to sync the
4787 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4788 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4789 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
4790 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
4791 /* If we have to wait for idle, set all states first, so that
4792 * all SET packets are processed in parallel with previous draw
4793 * calls. Then upload descriptors, set shader pointers, and
4794 * draw, and prefetch at the end. This ensures that the time
4795 * the CUs are idle is very short. (there are only SET_SH
4796 * packets between the wait and the draw)
4798 radv_emit_all_graphics_states(cmd_buffer
, info
);
4799 si_emit_cache_flush(cmd_buffer
);
4800 /* <-- CUs are idle here --> */
4802 radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
);
4804 radv_emit_draw_packets(cmd_buffer
, info
);
4805 /* <-- CUs are busy here --> */
4807 /* Start prefetches after the draw has been started. Both will
4808 * run in parallel, but starting the draw first is more
4811 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
4812 radv_emit_prefetch_L2(cmd_buffer
,
4813 cmd_buffer
->state
.pipeline
, false);
4816 /* If we don't wait for idle, start prefetches first, then set
4817 * states, and draw at the end.
4819 si_emit_cache_flush(cmd_buffer
);
4821 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
4822 /* Only prefetch the vertex shader and VBO descriptors
4823 * in order to start the draw as soon as possible.
4825 radv_emit_prefetch_L2(cmd_buffer
,
4826 cmd_buffer
->state
.pipeline
, true);
4829 radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
);
4831 radv_emit_all_graphics_states(cmd_buffer
, info
);
4832 radv_emit_draw_packets(cmd_buffer
, info
);
4834 /* Prefetch the remaining shaders after the draw has been
4837 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
4838 radv_emit_prefetch_L2(cmd_buffer
,
4839 cmd_buffer
->state
.pipeline
, false);
4843 /* Workaround for a VGT hang when streamout is enabled.
4844 * It must be done after drawing.
4846 if (cmd_buffer
->state
.streamout
.streamout_enabled
&&
4847 (rad_info
->family
== CHIP_HAWAII
||
4848 rad_info
->family
== CHIP_TONGA
||
4849 rad_info
->family
== CHIP_FIJI
)) {
4850 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
;
4853 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4854 radv_cmd_buffer_after_draw(cmd_buffer
, RADV_CMD_FLAG_PS_PARTIAL_FLUSH
);
4858 VkCommandBuffer commandBuffer
,
4859 uint32_t vertexCount
,
4860 uint32_t instanceCount
,
4861 uint32_t firstVertex
,
4862 uint32_t firstInstance
)
4864 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4865 struct radv_draw_info info
= {};
4867 info
.count
= vertexCount
;
4868 info
.instance_count
= instanceCount
;
4869 info
.first_instance
= firstInstance
;
4870 info
.vertex_offset
= firstVertex
;
4872 radv_draw(cmd_buffer
, &info
);
4875 void radv_CmdDrawIndexed(
4876 VkCommandBuffer commandBuffer
,
4877 uint32_t indexCount
,
4878 uint32_t instanceCount
,
4879 uint32_t firstIndex
,
4880 int32_t vertexOffset
,
4881 uint32_t firstInstance
)
4883 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4884 struct radv_draw_info info
= {};
4886 info
.indexed
= true;
4887 info
.count
= indexCount
;
4888 info
.instance_count
= instanceCount
;
4889 info
.first_index
= firstIndex
;
4890 info
.vertex_offset
= vertexOffset
;
4891 info
.first_instance
= firstInstance
;
4893 radv_draw(cmd_buffer
, &info
);
4896 void radv_CmdDrawIndirect(
4897 VkCommandBuffer commandBuffer
,
4899 VkDeviceSize offset
,
4903 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4904 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4905 struct radv_draw_info info
= {};
4907 info
.count
= drawCount
;
4908 info
.indirect
= buffer
;
4909 info
.indirect_offset
= offset
;
4910 info
.stride
= stride
;
4912 radv_draw(cmd_buffer
, &info
);
4915 void radv_CmdDrawIndexedIndirect(
4916 VkCommandBuffer commandBuffer
,
4918 VkDeviceSize offset
,
4922 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4923 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4924 struct radv_draw_info info
= {};
4926 info
.indexed
= true;
4927 info
.count
= drawCount
;
4928 info
.indirect
= buffer
;
4929 info
.indirect_offset
= offset
;
4930 info
.stride
= stride
;
4932 radv_draw(cmd_buffer
, &info
);
4935 void radv_CmdDrawIndirectCount(
4936 VkCommandBuffer commandBuffer
,
4938 VkDeviceSize offset
,
4939 VkBuffer _countBuffer
,
4940 VkDeviceSize countBufferOffset
,
4941 uint32_t maxDrawCount
,
4944 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4945 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4946 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
4947 struct radv_draw_info info
= {};
4949 info
.count
= maxDrawCount
;
4950 info
.indirect
= buffer
;
4951 info
.indirect_offset
= offset
;
4952 info
.count_buffer
= count_buffer
;
4953 info
.count_buffer_offset
= countBufferOffset
;
4954 info
.stride
= stride
;
4956 radv_draw(cmd_buffer
, &info
);
4959 void radv_CmdDrawIndexedIndirectCount(
4960 VkCommandBuffer commandBuffer
,
4962 VkDeviceSize offset
,
4963 VkBuffer _countBuffer
,
4964 VkDeviceSize countBufferOffset
,
4965 uint32_t maxDrawCount
,
4968 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4969 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4970 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
4971 struct radv_draw_info info
= {};
4973 info
.indexed
= true;
4974 info
.count
= maxDrawCount
;
4975 info
.indirect
= buffer
;
4976 info
.indirect_offset
= offset
;
4977 info
.count_buffer
= count_buffer
;
4978 info
.count_buffer_offset
= countBufferOffset
;
4979 info
.stride
= stride
;
4981 radv_draw(cmd_buffer
, &info
);
4984 struct radv_dispatch_info
{
4986 * Determine the layout of the grid (in block units) to be used.
4991 * A starting offset for the grid. If unaligned is set, the offset
4992 * must still be aligned.
4994 uint32_t offsets
[3];
4996 * Whether it's an unaligned compute dispatch.
5001 * Indirect compute parameters resource.
5003 struct radv_buffer
*indirect
;
5004 uint64_t indirect_offset
;
5008 radv_emit_dispatch_packets(struct radv_cmd_buffer
*cmd_buffer
,
5009 const struct radv_dispatch_info
*info
)
5011 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
5012 struct radv_shader_variant
*compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
5013 unsigned dispatch_initiator
= cmd_buffer
->device
->dispatch_initiator
;
5014 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
5015 bool predicating
= cmd_buffer
->state
.predicating
;
5016 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5017 struct radv_userdata_info
*loc
;
5019 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_COMPUTE
,
5020 AC_UD_CS_GRID_SIZE
);
5022 ASSERTED
unsigned cdw_max
= radeon_check_space(ws
, cs
, 25);
5024 if (compute_shader
->info
.wave_size
== 32) {
5025 assert(cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
5026 dispatch_initiator
|= S_00B800_CS_W32_EN(1);
5029 if (info
->indirect
) {
5030 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
5032 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
5034 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
);
5036 if (loc
->sgpr_idx
!= -1) {
5037 for (unsigned i
= 0; i
< 3; ++i
) {
5038 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
5039 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
5040 COPY_DATA_DST_SEL(COPY_DATA_REG
));
5041 radeon_emit(cs
, (va
+ 4 * i
));
5042 radeon_emit(cs
, (va
+ 4 * i
) >> 32);
5043 radeon_emit(cs
, ((R_00B900_COMPUTE_USER_DATA_0
5044 + loc
->sgpr_idx
* 4) >> 2) + i
);
5049 if (radv_cmd_buffer_uses_mec(cmd_buffer
)) {
5050 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 2, predicating
) |
5051 PKT3_SHADER_TYPE_S(1));
5052 radeon_emit(cs
, va
);
5053 radeon_emit(cs
, va
>> 32);
5054 radeon_emit(cs
, dispatch_initiator
);
5056 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0) |
5057 PKT3_SHADER_TYPE_S(1));
5059 radeon_emit(cs
, va
);
5060 radeon_emit(cs
, va
>> 32);
5062 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 1, predicating
) |
5063 PKT3_SHADER_TYPE_S(1));
5065 radeon_emit(cs
, dispatch_initiator
);
5068 unsigned blocks
[3] = { info
->blocks
[0], info
->blocks
[1], info
->blocks
[2] };
5069 unsigned offsets
[3] = { info
->offsets
[0], info
->offsets
[1], info
->offsets
[2] };
5071 if (info
->unaligned
) {
5072 unsigned *cs_block_size
= compute_shader
->info
.cs
.block_size
;
5073 unsigned remainder
[3];
5075 /* If aligned, these should be an entire block size,
5078 remainder
[0] = blocks
[0] + cs_block_size
[0] -
5079 align_u32_npot(blocks
[0], cs_block_size
[0]);
5080 remainder
[1] = blocks
[1] + cs_block_size
[1] -
5081 align_u32_npot(blocks
[1], cs_block_size
[1]);
5082 remainder
[2] = blocks
[2] + cs_block_size
[2] -
5083 align_u32_npot(blocks
[2], cs_block_size
[2]);
5085 blocks
[0] = round_up_u32(blocks
[0], cs_block_size
[0]);
5086 blocks
[1] = round_up_u32(blocks
[1], cs_block_size
[1]);
5087 blocks
[2] = round_up_u32(blocks
[2], cs_block_size
[2]);
5089 for(unsigned i
= 0; i
< 3; ++i
) {
5090 assert(offsets
[i
] % cs_block_size
[i
] == 0);
5091 offsets
[i
] /= cs_block_size
[i
];
5094 radeon_set_sh_reg_seq(cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
5096 S_00B81C_NUM_THREAD_FULL(cs_block_size
[0]) |
5097 S_00B81C_NUM_THREAD_PARTIAL(remainder
[0]));
5099 S_00B81C_NUM_THREAD_FULL(cs_block_size
[1]) |
5100 S_00B81C_NUM_THREAD_PARTIAL(remainder
[1]));
5102 S_00B81C_NUM_THREAD_FULL(cs_block_size
[2]) |
5103 S_00B81C_NUM_THREAD_PARTIAL(remainder
[2]));
5105 dispatch_initiator
|= S_00B800_PARTIAL_TG_EN(1);
5108 if (loc
->sgpr_idx
!= -1) {
5109 assert(loc
->num_sgprs
== 3);
5111 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
5112 loc
->sgpr_idx
* 4, 3);
5113 radeon_emit(cs
, blocks
[0]);
5114 radeon_emit(cs
, blocks
[1]);
5115 radeon_emit(cs
, blocks
[2]);
5118 if (offsets
[0] || offsets
[1] || offsets
[2]) {
5119 radeon_set_sh_reg_seq(cs
, R_00B810_COMPUTE_START_X
, 3);
5120 radeon_emit(cs
, offsets
[0]);
5121 radeon_emit(cs
, offsets
[1]);
5122 radeon_emit(cs
, offsets
[2]);
5124 /* The blocks in the packet are not counts but end values. */
5125 for (unsigned i
= 0; i
< 3; ++i
)
5126 blocks
[i
] += offsets
[i
];
5128 dispatch_initiator
|= S_00B800_FORCE_START_AT_000(1);
5131 radeon_emit(cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, predicating
) |
5132 PKT3_SHADER_TYPE_S(1));
5133 radeon_emit(cs
, blocks
[0]);
5134 radeon_emit(cs
, blocks
[1]);
5135 radeon_emit(cs
, blocks
[2]);
5136 radeon_emit(cs
, dispatch_initiator
);
5139 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
5143 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
5145 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
5146 radv_flush_constants(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
5150 radv_dispatch(struct radv_cmd_buffer
*cmd_buffer
,
5151 const struct radv_dispatch_info
*info
)
5153 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
5155 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
5156 bool pipeline_is_dirty
= pipeline
&&
5157 pipeline
!= cmd_buffer
->state
.emitted_compute_pipeline
;
5159 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5160 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
5161 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
5162 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
5163 /* If we have to wait for idle, set all states first, so that
5164 * all SET packets are processed in parallel with previous draw
5165 * calls. Then upload descriptors, set shader pointers, and
5166 * dispatch, and prefetch at the end. This ensures that the
5167 * time the CUs are idle is very short. (there are only SET_SH
5168 * packets between the wait and the draw)
5170 radv_emit_compute_pipeline(cmd_buffer
);
5171 si_emit_cache_flush(cmd_buffer
);
5172 /* <-- CUs are idle here --> */
5174 radv_upload_compute_shader_descriptors(cmd_buffer
);
5176 radv_emit_dispatch_packets(cmd_buffer
, info
);
5177 /* <-- CUs are busy here --> */
5179 /* Start prefetches after the dispatch has been started. Both
5180 * will run in parallel, but starting the dispatch first is
5183 if (has_prefetch
&& pipeline_is_dirty
) {
5184 radv_emit_shader_prefetch(cmd_buffer
,
5185 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
5188 /* If we don't wait for idle, start prefetches first, then set
5189 * states, and dispatch at the end.
5191 si_emit_cache_flush(cmd_buffer
);
5193 if (has_prefetch
&& pipeline_is_dirty
) {
5194 radv_emit_shader_prefetch(cmd_buffer
,
5195 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
5198 radv_upload_compute_shader_descriptors(cmd_buffer
);
5200 radv_emit_compute_pipeline(cmd_buffer
);
5201 radv_emit_dispatch_packets(cmd_buffer
, info
);
5204 radv_cmd_buffer_after_draw(cmd_buffer
, RADV_CMD_FLAG_CS_PARTIAL_FLUSH
);
5207 void radv_CmdDispatchBase(
5208 VkCommandBuffer commandBuffer
,
5216 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5217 struct radv_dispatch_info info
= {};
5223 info
.offsets
[0] = base_x
;
5224 info
.offsets
[1] = base_y
;
5225 info
.offsets
[2] = base_z
;
5226 radv_dispatch(cmd_buffer
, &info
);
5229 void radv_CmdDispatch(
5230 VkCommandBuffer commandBuffer
,
5235 radv_CmdDispatchBase(commandBuffer
, 0, 0, 0, x
, y
, z
);
5238 void radv_CmdDispatchIndirect(
5239 VkCommandBuffer commandBuffer
,
5241 VkDeviceSize offset
)
5243 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5244 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
5245 struct radv_dispatch_info info
= {};
5247 info
.indirect
= buffer
;
5248 info
.indirect_offset
= offset
;
5250 radv_dispatch(cmd_buffer
, &info
);
5253 void radv_unaligned_dispatch(
5254 struct radv_cmd_buffer
*cmd_buffer
,
5259 struct radv_dispatch_info info
= {};
5266 radv_dispatch(cmd_buffer
, &info
);
5269 void radv_CmdEndRenderPass(
5270 VkCommandBuffer commandBuffer
)
5272 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5274 radv_subpass_barrier(cmd_buffer
, &cmd_buffer
->state
.pass
->end_barrier
);
5276 radv_cmd_buffer_end_subpass(cmd_buffer
);
5278 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
5279 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.subpass_sample_locs
);
5281 cmd_buffer
->state
.pass
= NULL
;
5282 cmd_buffer
->state
.subpass
= NULL
;
5283 cmd_buffer
->state
.attachments
= NULL
;
5284 cmd_buffer
->state
.framebuffer
= NULL
;
5285 cmd_buffer
->state
.subpass_sample_locs
= NULL
;
5288 void radv_CmdEndRenderPass2(
5289 VkCommandBuffer commandBuffer
,
5290 const VkSubpassEndInfo
* pSubpassEndInfo
)
5292 radv_CmdEndRenderPass(commandBuffer
);
5296 * For HTILE we have the following interesting clear words:
5297 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5298 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5299 * 0xfffffff0: Clear depth to 1.0
5300 * 0x00000000: Clear depth to 0.0
5302 static void radv_initialize_htile(struct radv_cmd_buffer
*cmd_buffer
,
5303 struct radv_image
*image
,
5304 const VkImageSubresourceRange
*range
)
5306 assert(range
->baseMipLevel
== 0);
5307 assert(range
->levelCount
== 1 || range
->levelCount
== VK_REMAINING_ARRAY_LAYERS
);
5308 VkImageAspectFlags aspects
= VK_IMAGE_ASPECT_DEPTH_BIT
;
5309 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
5310 uint32_t htile_value
= vk_format_is_stencil(image
->vk_format
) ? 0xfffff30f : 0xfffc000f;
5311 VkClearDepthStencilValue value
= {};
5313 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
5314 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
5316 state
->flush_bits
|= radv_clear_htile(cmd_buffer
, image
, range
, htile_value
);
5318 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
5320 if (vk_format_is_stencil(image
->vk_format
))
5321 aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
5323 radv_set_ds_clear_metadata(cmd_buffer
, image
, range
, value
, aspects
);
5325 if (radv_image_is_tc_compat_htile(image
)) {
5326 /* Initialize the TC-compat metada value to 0 because by
5327 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5328 * need have to conditionally update its value when performing
5329 * a fast depth clear.
5331 radv_set_tc_compat_zrange_metadata(cmd_buffer
, image
, range
, 0);
5335 static void radv_handle_depth_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
5336 struct radv_image
*image
,
5337 VkImageLayout src_layout
,
5338 bool src_render_loop
,
5339 VkImageLayout dst_layout
,
5340 bool dst_render_loop
,
5341 unsigned src_queue_mask
,
5342 unsigned dst_queue_mask
,
5343 const VkImageSubresourceRange
*range
,
5344 struct radv_sample_locations_state
*sample_locs
)
5346 if (!radv_image_has_htile(image
))
5349 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
5350 radv_initialize_htile(cmd_buffer
, image
, range
);
5351 } else if (!radv_layout_is_htile_compressed(image
, src_layout
, src_render_loop
, src_queue_mask
) &&
5352 radv_layout_is_htile_compressed(image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
5353 radv_initialize_htile(cmd_buffer
, image
, range
);
5354 } else if (radv_layout_is_htile_compressed(image
, src_layout
, src_render_loop
, src_queue_mask
) &&
5355 !radv_layout_is_htile_compressed(image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
5356 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
5357 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
5359 radv_decompress_depth_image_inplace(cmd_buffer
, image
, range
,
5362 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
5363 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
5367 static void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
5368 struct radv_image
*image
,
5369 const VkImageSubresourceRange
*range
,
5372 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
5374 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5375 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5377 state
->flush_bits
|= radv_clear_cmask(cmd_buffer
, image
, range
, value
);
5379 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5382 void radv_initialize_fmask(struct radv_cmd_buffer
*cmd_buffer
,
5383 struct radv_image
*image
,
5384 const VkImageSubresourceRange
*range
)
5386 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
5387 static const uint32_t fmask_clear_values
[4] = {
5393 uint32_t log2_samples
= util_logbase2(image
->info
.samples
);
5394 uint32_t value
= fmask_clear_values
[log2_samples
];
5396 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5397 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5399 state
->flush_bits
|= radv_clear_fmask(cmd_buffer
, image
, range
, value
);
5401 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5404 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
5405 struct radv_image
*image
,
5406 const VkImageSubresourceRange
*range
, uint32_t value
)
5408 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
5411 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5412 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5414 state
->flush_bits
|= radv_clear_dcc(cmd_buffer
, image
, range
, value
);
5416 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX8
) {
5417 /* When DCC is enabled with mipmaps, some levels might not
5418 * support fast clears and we have to initialize them as "fully
5421 /* Compute the size of all fast clearable DCC levels. */
5422 for (unsigned i
= 0; i
< image
->planes
[0].surface
.num_dcc_levels
; i
++) {
5423 struct legacy_surf_level
*surf_level
=
5424 &image
->planes
[0].surface
.u
.legacy
.level
[i
];
5425 unsigned dcc_fast_clear_size
=
5426 surf_level
->dcc_slice_fast_clear_size
* image
->info
.array_size
;
5428 if (!dcc_fast_clear_size
)
5431 size
= surf_level
->dcc_offset
+ dcc_fast_clear_size
;
5434 /* Initialize the mipmap levels without DCC. */
5435 if (size
!= image
->planes
[0].surface
.dcc_size
) {
5436 state
->flush_bits
|=
5437 radv_fill_buffer(cmd_buffer
, image
->bo
,
5438 image
->offset
+ image
->dcc_offset
+ size
,
5439 image
->planes
[0].surface
.dcc_size
- size
,
5444 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5445 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5449 * Initialize DCC/FMASK/CMASK metadata for a color image.
5451 static void radv_init_color_image_metadata(struct radv_cmd_buffer
*cmd_buffer
,
5452 struct radv_image
*image
,
5453 VkImageLayout src_layout
,
5454 bool src_render_loop
,
5455 VkImageLayout dst_layout
,
5456 bool dst_render_loop
,
5457 unsigned src_queue_mask
,
5458 unsigned dst_queue_mask
,
5459 const VkImageSubresourceRange
*range
)
5461 if (radv_image_has_cmask(image
)) {
5462 uint32_t value
= 0xffffffffu
; /* Fully expanded mode. */
5464 /* TODO: clarify this. */
5465 if (radv_image_has_fmask(image
)) {
5466 value
= 0xccccccccu
;
5469 radv_initialise_cmask(cmd_buffer
, image
, range
, value
);
5472 if (radv_image_has_fmask(image
)) {
5473 radv_initialize_fmask(cmd_buffer
, image
, range
);
5476 if (radv_dcc_enabled(image
, range
->baseMipLevel
)) {
5477 uint32_t value
= 0xffffffffu
; /* Fully expanded mode. */
5478 bool need_decompress_pass
= false;
5480 if (radv_layout_dcc_compressed(cmd_buffer
->device
, image
, dst_layout
,
5483 value
= 0x20202020u
;
5484 need_decompress_pass
= true;
5487 radv_initialize_dcc(cmd_buffer
, image
, range
, value
);
5489 radv_update_fce_metadata(cmd_buffer
, image
, range
,
5490 need_decompress_pass
);
5493 if (radv_image_has_cmask(image
) ||
5494 radv_dcc_enabled(image
, range
->baseMipLevel
)) {
5495 uint32_t color_values
[2] = {};
5496 radv_set_color_clear_metadata(cmd_buffer
, image
, range
,
5502 * Handle color image transitions for DCC/FMASK/CMASK.
5504 static void radv_handle_color_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
5505 struct radv_image
*image
,
5506 VkImageLayout src_layout
,
5507 bool src_render_loop
,
5508 VkImageLayout dst_layout
,
5509 bool dst_render_loop
,
5510 unsigned src_queue_mask
,
5511 unsigned dst_queue_mask
,
5512 const VkImageSubresourceRange
*range
)
5514 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
5515 radv_init_color_image_metadata(cmd_buffer
, image
,
5516 src_layout
, src_render_loop
,
5517 dst_layout
, dst_render_loop
,
5518 src_queue_mask
, dst_queue_mask
,
5523 if (radv_dcc_enabled(image
, range
->baseMipLevel
)) {
5524 if (src_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
5525 radv_initialize_dcc(cmd_buffer
, image
, range
, 0xffffffffu
);
5526 } else if (radv_layout_dcc_compressed(cmd_buffer
->device
, image
, src_layout
, src_render_loop
, src_queue_mask
) &&
5527 !radv_layout_dcc_compressed(cmd_buffer
->device
, image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
5528 radv_decompress_dcc(cmd_buffer
, image
, range
);
5529 } else if (radv_layout_can_fast_clear(image
, src_layout
, src_render_loop
, src_queue_mask
) &&
5530 !radv_layout_can_fast_clear(image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
5531 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
5533 } else if (radv_image_has_cmask(image
) || radv_image_has_fmask(image
)) {
5534 bool fce_eliminate
= false, fmask_expand
= false;
5536 if (radv_layout_can_fast_clear(image
, src_layout
, src_render_loop
, src_queue_mask
) &&
5537 !radv_layout_can_fast_clear(image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
5538 fce_eliminate
= true;
5541 if (radv_image_has_fmask(image
)) {
5542 if (src_layout
!= VK_IMAGE_LAYOUT_GENERAL
&&
5543 dst_layout
== VK_IMAGE_LAYOUT_GENERAL
) {
5544 /* A FMASK decompress is required before doing
5545 * a MSAA decompress using FMASK.
5547 fmask_expand
= true;
5551 if (fce_eliminate
|| fmask_expand
)
5552 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
5555 radv_expand_fmask_image_inplace(cmd_buffer
, image
, range
);
5559 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
5560 struct radv_image
*image
,
5561 VkImageLayout src_layout
,
5562 bool src_render_loop
,
5563 VkImageLayout dst_layout
,
5564 bool dst_render_loop
,
5565 uint32_t src_family
,
5566 uint32_t dst_family
,
5567 const VkImageSubresourceRange
*range
,
5568 struct radv_sample_locations_state
*sample_locs
)
5570 if (image
->exclusive
&& src_family
!= dst_family
) {
5571 /* This is an acquire or a release operation and there will be
5572 * a corresponding release/acquire. Do the transition in the
5573 * most flexible queue. */
5575 assert(src_family
== cmd_buffer
->queue_family_index
||
5576 dst_family
== cmd_buffer
->queue_family_index
);
5578 if (src_family
== VK_QUEUE_FAMILY_EXTERNAL
||
5579 src_family
== VK_QUEUE_FAMILY_FOREIGN_EXT
)
5582 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_TRANSFER
)
5585 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
5586 (src_family
== RADV_QUEUE_GENERAL
||
5587 dst_family
== RADV_QUEUE_GENERAL
))
5591 if (src_layout
== dst_layout
)
5594 unsigned src_queue_mask
=
5595 radv_image_queue_family_mask(image
, src_family
,
5596 cmd_buffer
->queue_family_index
);
5597 unsigned dst_queue_mask
=
5598 radv_image_queue_family_mask(image
, dst_family
,
5599 cmd_buffer
->queue_family_index
);
5601 if (vk_format_is_depth(image
->vk_format
)) {
5602 radv_handle_depth_image_transition(cmd_buffer
, image
,
5603 src_layout
, src_render_loop
,
5604 dst_layout
, dst_render_loop
,
5605 src_queue_mask
, dst_queue_mask
,
5606 range
, sample_locs
);
5608 radv_handle_color_image_transition(cmd_buffer
, image
,
5609 src_layout
, src_render_loop
,
5610 dst_layout
, dst_render_loop
,
5611 src_queue_mask
, dst_queue_mask
,
5616 struct radv_barrier_info
{
5617 uint32_t eventCount
;
5618 const VkEvent
*pEvents
;
5619 VkPipelineStageFlags srcStageMask
;
5620 VkPipelineStageFlags dstStageMask
;
5624 radv_barrier(struct radv_cmd_buffer
*cmd_buffer
,
5625 uint32_t memoryBarrierCount
,
5626 const VkMemoryBarrier
*pMemoryBarriers
,
5627 uint32_t bufferMemoryBarrierCount
,
5628 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
5629 uint32_t imageMemoryBarrierCount
,
5630 const VkImageMemoryBarrier
*pImageMemoryBarriers
,
5631 const struct radv_barrier_info
*info
)
5633 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5634 enum radv_cmd_flush_bits src_flush_bits
= 0;
5635 enum radv_cmd_flush_bits dst_flush_bits
= 0;
5637 for (unsigned i
= 0; i
< info
->eventCount
; ++i
) {
5638 RADV_FROM_HANDLE(radv_event
, event
, info
->pEvents
[i
]);
5639 uint64_t va
= radv_buffer_get_va(event
->bo
);
5641 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
);
5643 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 7);
5645 radv_cp_wait_mem(cs
, WAIT_REG_MEM_EQUAL
, va
, 1, 0xffffffff);
5646 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
5649 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
5650 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pMemoryBarriers
[i
].srcAccessMask
,
5652 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pMemoryBarriers
[i
].dstAccessMask
,
5656 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
5657 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].srcAccessMask
,
5659 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].dstAccessMask
,
5663 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
5664 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
5666 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].srcAccessMask
,
5668 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].dstAccessMask
,
5672 /* The Vulkan spec 1.1.98 says:
5674 * "An execution dependency with only
5675 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5676 * will only prevent that stage from executing in subsequently
5677 * submitted commands. As this stage does not perform any actual
5678 * execution, this is not observable - in effect, it does not delay
5679 * processing of subsequent commands. Similarly an execution dependency
5680 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5681 * will effectively not wait for any prior commands to complete."
5683 if (info
->dstStageMask
!= VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
)
5684 radv_stage_flush(cmd_buffer
, info
->srcStageMask
);
5685 cmd_buffer
->state
.flush_bits
|= src_flush_bits
;
5687 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
5688 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
5690 const struct VkSampleLocationsInfoEXT
*sample_locs_info
=
5691 vk_find_struct_const(pImageMemoryBarriers
[i
].pNext
,
5692 SAMPLE_LOCATIONS_INFO_EXT
);
5693 struct radv_sample_locations_state sample_locations
= {};
5695 if (sample_locs_info
) {
5696 assert(image
->flags
& VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
);
5697 sample_locations
.per_pixel
= sample_locs_info
->sampleLocationsPerPixel
;
5698 sample_locations
.grid_size
= sample_locs_info
->sampleLocationGridSize
;
5699 sample_locations
.count
= sample_locs_info
->sampleLocationsCount
;
5700 typed_memcpy(&sample_locations
.locations
[0],
5701 sample_locs_info
->pSampleLocations
,
5702 sample_locs_info
->sampleLocationsCount
);
5705 radv_handle_image_transition(cmd_buffer
, image
,
5706 pImageMemoryBarriers
[i
].oldLayout
,
5707 false, /* Outside of a renderpass we are never in a renderloop */
5708 pImageMemoryBarriers
[i
].newLayout
,
5709 false, /* Outside of a renderpass we are never in a renderloop */
5710 pImageMemoryBarriers
[i
].srcQueueFamilyIndex
,
5711 pImageMemoryBarriers
[i
].dstQueueFamilyIndex
,
5712 &pImageMemoryBarriers
[i
].subresourceRange
,
5713 sample_locs_info
? &sample_locations
: NULL
);
5716 /* Make sure CP DMA is idle because the driver might have performed a
5717 * DMA operation for copying or filling buffers/images.
5719 if (info
->srcStageMask
& (VK_PIPELINE_STAGE_TRANSFER_BIT
|
5720 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
))
5721 si_cp_dma_wait_for_idle(cmd_buffer
);
5723 cmd_buffer
->state
.flush_bits
|= dst_flush_bits
;
5726 void radv_CmdPipelineBarrier(
5727 VkCommandBuffer commandBuffer
,
5728 VkPipelineStageFlags srcStageMask
,
5729 VkPipelineStageFlags destStageMask
,
5731 uint32_t memoryBarrierCount
,
5732 const VkMemoryBarrier
* pMemoryBarriers
,
5733 uint32_t bufferMemoryBarrierCount
,
5734 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
5735 uint32_t imageMemoryBarrierCount
,
5736 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
5738 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5739 struct radv_barrier_info info
;
5741 info
.eventCount
= 0;
5742 info
.pEvents
= NULL
;
5743 info
.srcStageMask
= srcStageMask
;
5744 info
.dstStageMask
= destStageMask
;
5746 radv_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
5747 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
5748 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
5752 static void write_event(struct radv_cmd_buffer
*cmd_buffer
,
5753 struct radv_event
*event
,
5754 VkPipelineStageFlags stageMask
,
5757 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5758 uint64_t va
= radv_buffer_get_va(event
->bo
);
5760 si_emit_cache_flush(cmd_buffer
);
5762 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
);
5764 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 21);
5766 /* Flags that only require a top-of-pipe event. */
5767 VkPipelineStageFlags top_of_pipe_flags
=
5768 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
;
5770 /* Flags that only require a post-index-fetch event. */
5771 VkPipelineStageFlags post_index_fetch_flags
=
5773 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
5774 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
;
5776 /* Make sure CP DMA is idle because the driver might have performed a
5777 * DMA operation for copying or filling buffers/images.
5779 if (stageMask
& (VK_PIPELINE_STAGE_TRANSFER_BIT
|
5780 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
))
5781 si_cp_dma_wait_for_idle(cmd_buffer
);
5783 /* TODO: Emit EOS events for syncing PS/CS stages. */
5785 if (!(stageMask
& ~top_of_pipe_flags
)) {
5786 /* Just need to sync the PFP engine. */
5787 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
5788 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
5789 S_370_WR_CONFIRM(1) |
5790 S_370_ENGINE_SEL(V_370_PFP
));
5791 radeon_emit(cs
, va
);
5792 radeon_emit(cs
, va
>> 32);
5793 radeon_emit(cs
, value
);
5794 } else if (!(stageMask
& ~post_index_fetch_flags
)) {
5795 /* Sync ME because PFP reads index and indirect buffers. */
5796 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
5797 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
5798 S_370_WR_CONFIRM(1) |
5799 S_370_ENGINE_SEL(V_370_ME
));
5800 radeon_emit(cs
, va
);
5801 radeon_emit(cs
, va
>> 32);
5802 radeon_emit(cs
, value
);
5804 /* Otherwise, sync all prior GPU work using an EOP event. */
5805 si_cs_emit_write_event_eop(cs
,
5806 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
5807 radv_cmd_buffer_uses_mec(cmd_buffer
),
5808 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
5810 EOP_DATA_SEL_VALUE_32BIT
, va
, value
,
5811 cmd_buffer
->gfx9_eop_bug_va
);
5814 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
5817 void radv_CmdSetEvent(VkCommandBuffer commandBuffer
,
5819 VkPipelineStageFlags stageMask
)
5821 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5822 RADV_FROM_HANDLE(radv_event
, event
, _event
);
5824 write_event(cmd_buffer
, event
, stageMask
, 1);
5827 void radv_CmdResetEvent(VkCommandBuffer commandBuffer
,
5829 VkPipelineStageFlags stageMask
)
5831 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5832 RADV_FROM_HANDLE(radv_event
, event
, _event
);
5834 write_event(cmd_buffer
, event
, stageMask
, 0);
5837 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer
,
5838 uint32_t eventCount
,
5839 const VkEvent
* pEvents
,
5840 VkPipelineStageFlags srcStageMask
,
5841 VkPipelineStageFlags dstStageMask
,
5842 uint32_t memoryBarrierCount
,
5843 const VkMemoryBarrier
* pMemoryBarriers
,
5844 uint32_t bufferMemoryBarrierCount
,
5845 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
5846 uint32_t imageMemoryBarrierCount
,
5847 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
5849 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5850 struct radv_barrier_info info
;
5852 info
.eventCount
= eventCount
;
5853 info
.pEvents
= pEvents
;
5854 info
.srcStageMask
= 0;
5856 radv_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
5857 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
5858 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
5862 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer
,
5863 uint32_t deviceMask
)
5868 /* VK_EXT_conditional_rendering */
5869 void radv_CmdBeginConditionalRenderingEXT(
5870 VkCommandBuffer commandBuffer
,
5871 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
5873 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5874 RADV_FROM_HANDLE(radv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
5875 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5876 bool draw_visible
= true;
5877 uint64_t pred_value
= 0;
5878 uint64_t va
, new_va
;
5879 unsigned pred_offset
;
5881 va
= radv_buffer_get_va(buffer
->bo
) + pConditionalRenderingBegin
->offset
;
5883 /* By default, if the 32-bit value at offset in buffer memory is zero,
5884 * then the rendering commands are discarded, otherwise they are
5885 * executed as normal. If the inverted flag is set, all commands are
5886 * discarded if the value is non zero.
5888 if (pConditionalRenderingBegin
->flags
&
5889 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
) {
5890 draw_visible
= false;
5893 si_emit_cache_flush(cmd_buffer
);
5895 /* From the Vulkan spec 1.1.107:
5897 * "If the 32-bit value at offset in buffer memory is zero, then the
5898 * rendering commands are discarded, otherwise they are executed as
5899 * normal. If the value of the predicate in buffer memory changes while
5900 * conditional rendering is active, the rendering commands may be
5901 * discarded in an implementation-dependent way. Some implementations
5902 * may latch the value of the predicate upon beginning conditional
5903 * rendering while others may read it before every rendering command."
5905 * But, the AMD hardware treats the predicate as a 64-bit value which
5906 * means we need a workaround in the driver. Luckily, it's not required
5907 * to support if the value changes when predication is active.
5909 * The workaround is as follows:
5910 * 1) allocate a 64-value in the upload BO and initialize it to 0
5911 * 2) copy the 32-bit predicate value to the upload BO
5912 * 3) use the new allocated VA address for predication
5914 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5915 * in ME (+ sync PFP) instead of PFP.
5917 radv_cmd_buffer_upload_data(cmd_buffer
, 8, 16, &pred_value
, &pred_offset
);
5919 new_va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
) + pred_offset
;
5921 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
5922 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
5923 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM
) |
5924 COPY_DATA_WR_CONFIRM
);
5925 radeon_emit(cs
, va
);
5926 radeon_emit(cs
, va
>> 32);
5927 radeon_emit(cs
, new_va
);
5928 radeon_emit(cs
, new_va
>> 32);
5930 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
5933 /* Enable predication for this command buffer. */
5934 si_emit_set_predication_state(cmd_buffer
, draw_visible
, new_va
);
5935 cmd_buffer
->state
.predicating
= true;
5937 /* Store conditional rendering user info. */
5938 cmd_buffer
->state
.predication_type
= draw_visible
;
5939 cmd_buffer
->state
.predication_va
= new_va
;
5942 void radv_CmdEndConditionalRenderingEXT(
5943 VkCommandBuffer commandBuffer
)
5945 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5947 /* Disable predication for this command buffer. */
5948 si_emit_set_predication_state(cmd_buffer
, false, 0);
5949 cmd_buffer
->state
.predicating
= false;
5951 /* Reset conditional rendering user info. */
5952 cmd_buffer
->state
.predication_type
= -1;
5953 cmd_buffer
->state
.predication_va
= 0;
5956 /* VK_EXT_transform_feedback */
5957 void radv_CmdBindTransformFeedbackBuffersEXT(
5958 VkCommandBuffer commandBuffer
,
5959 uint32_t firstBinding
,
5960 uint32_t bindingCount
,
5961 const VkBuffer
* pBuffers
,
5962 const VkDeviceSize
* pOffsets
,
5963 const VkDeviceSize
* pSizes
)
5965 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5966 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
5967 uint8_t enabled_mask
= 0;
5969 assert(firstBinding
+ bindingCount
<= MAX_SO_BUFFERS
);
5970 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
5971 uint32_t idx
= firstBinding
+ i
;
5973 sb
[idx
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
5974 sb
[idx
].offset
= pOffsets
[i
];
5975 sb
[idx
].size
= pSizes
[i
];
5977 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
5978 sb
[idx
].buffer
->bo
);
5980 enabled_mask
|= 1 << idx
;
5983 cmd_buffer
->state
.streamout
.enabled_mask
|= enabled_mask
;
5985 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_STREAMOUT_BUFFER
;
5989 radv_emit_streamout_enable(struct radv_cmd_buffer
*cmd_buffer
)
5991 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
5992 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5994 radeon_set_context_reg_seq(cs
, R_028B94_VGT_STRMOUT_CONFIG
, 2);
5996 S_028B94_STREAMOUT_0_EN(so
->streamout_enabled
) |
5997 S_028B94_RAST_STREAM(0) |
5998 S_028B94_STREAMOUT_1_EN(so
->streamout_enabled
) |
5999 S_028B94_STREAMOUT_2_EN(so
->streamout_enabled
) |
6000 S_028B94_STREAMOUT_3_EN(so
->streamout_enabled
));
6001 radeon_emit(cs
, so
->hw_enabled_mask
&
6002 so
->enabled_stream_buffers_mask
);
6004 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
6008 radv_set_streamout_enable(struct radv_cmd_buffer
*cmd_buffer
, bool enable
)
6010 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
6011 bool old_streamout_enabled
= so
->streamout_enabled
;
6012 uint32_t old_hw_enabled_mask
= so
->hw_enabled_mask
;
6014 so
->streamout_enabled
= enable
;
6016 so
->hw_enabled_mask
= so
->enabled_mask
|
6017 (so
->enabled_mask
<< 4) |
6018 (so
->enabled_mask
<< 8) |
6019 (so
->enabled_mask
<< 12);
6021 if (!cmd_buffer
->device
->physical_device
->use_ngg_streamout
&&
6022 ((old_streamout_enabled
!= so
->streamout_enabled
) ||
6023 (old_hw_enabled_mask
!= so
->hw_enabled_mask
)))
6024 radv_emit_streamout_enable(cmd_buffer
);
6026 if (cmd_buffer
->device
->physical_device
->use_ngg_streamout
) {
6027 cmd_buffer
->gds_needed
= true;
6028 cmd_buffer
->gds_oa_needed
= true;
6032 static void radv_flush_vgt_streamout(struct radv_cmd_buffer
*cmd_buffer
)
6034 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
6035 unsigned reg_strmout_cntl
;
6037 /* The register is at different places on different ASICs. */
6038 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
6039 reg_strmout_cntl
= R_0300FC_CP_STRMOUT_CNTL
;
6040 radeon_set_uconfig_reg(cs
, reg_strmout_cntl
, 0);
6042 reg_strmout_cntl
= R_0084FC_CP_STRMOUT_CNTL
;
6043 radeon_set_config_reg(cs
, reg_strmout_cntl
, 0);
6046 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
6047 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH
) | EVENT_INDEX(0));
6049 radeon_emit(cs
, PKT3(PKT3_WAIT_REG_MEM
, 5, 0));
6050 radeon_emit(cs
, WAIT_REG_MEM_EQUAL
); /* wait until the register is equal to the reference value */
6051 radeon_emit(cs
, reg_strmout_cntl
>> 2); /* register */
6053 radeon_emit(cs
, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
6054 radeon_emit(cs
, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
6055 radeon_emit(cs
, 4); /* poll interval */
6059 radv_emit_streamout_begin(struct radv_cmd_buffer
*cmd_buffer
,
6060 uint32_t firstCounterBuffer
,
6061 uint32_t counterBufferCount
,
6062 const VkBuffer
*pCounterBuffers
,
6063 const VkDeviceSize
*pCounterBufferOffsets
)
6066 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
6067 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
6068 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
6071 radv_flush_vgt_streamout(cmd_buffer
);
6073 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
6074 for_each_bit(i
, so
->enabled_mask
) {
6075 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
6076 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
6077 counter_buffer_idx
= -1;
6079 /* AMD GCN binds streamout buffers as shader resources.
6080 * VGT only counts primitives and tells the shader through
6083 radeon_set_context_reg_seq(cs
, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0
+ 16*i
, 2);
6084 radeon_emit(cs
, sb
[i
].size
>> 2); /* BUFFER_SIZE (in DW) */
6085 radeon_emit(cs
, so
->stride_in_dw
[i
]); /* VTX_STRIDE (in DW) */
6087 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
6089 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
6090 /* The array of counter buffers is optional. */
6091 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
6092 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
6094 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
6097 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
6098 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
6099 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6100 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM
)); /* control */
6101 radeon_emit(cs
, 0); /* unused */
6102 radeon_emit(cs
, 0); /* unused */
6103 radeon_emit(cs
, va
); /* src address lo */
6104 radeon_emit(cs
, va
>> 32); /* src address hi */
6106 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
6108 /* Start from the beginning. */
6109 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
6110 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
6111 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6112 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET
)); /* control */
6113 radeon_emit(cs
, 0); /* unused */
6114 radeon_emit(cs
, 0); /* unused */
6115 radeon_emit(cs
, 0); /* unused */
6116 radeon_emit(cs
, 0); /* unused */
6120 radv_set_streamout_enable(cmd_buffer
, true);
6124 gfx10_emit_streamout_begin(struct radv_cmd_buffer
*cmd_buffer
,
6125 uint32_t firstCounterBuffer
,
6126 uint32_t counterBufferCount
,
6127 const VkBuffer
*pCounterBuffers
,
6128 const VkDeviceSize
*pCounterBufferOffsets
)
6130 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
6131 unsigned last_target
= util_last_bit(so
->enabled_mask
) - 1;
6132 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
6135 assert(cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
6136 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
6138 /* Sync because the next streamout operation will overwrite GDS and we
6139 * have to make sure it's idle.
6140 * TODO: Improve by tracking if there is a streamout operation in
6143 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VS_PARTIAL_FLUSH
;
6144 si_emit_cache_flush(cmd_buffer
);
6146 for_each_bit(i
, so
->enabled_mask
) {
6147 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
6148 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
6149 counter_buffer_idx
= -1;
6151 bool append
= counter_buffer_idx
>= 0 &&
6152 pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
];
6156 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
6158 va
+= radv_buffer_get_va(buffer
->bo
);
6159 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
6161 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
6164 radeon_emit(cs
, PKT3(PKT3_DMA_DATA
, 5, 0));
6165 radeon_emit(cs
, S_411_SRC_SEL(append
? V_411_SRC_ADDR_TC_L2
: V_411_DATA
) |
6166 S_411_DST_SEL(V_411_GDS
) |
6167 S_411_CP_SYNC(i
== last_target
));
6168 radeon_emit(cs
, va
);
6169 radeon_emit(cs
, va
>> 32);
6170 radeon_emit(cs
, 4 * i
); /* destination in GDS */
6172 radeon_emit(cs
, S_414_BYTE_COUNT_GFX9(4) |
6173 S_414_DISABLE_WR_CONFIRM_GFX9(i
!= last_target
));
6176 radv_set_streamout_enable(cmd_buffer
, true);
6179 void radv_CmdBeginTransformFeedbackEXT(
6180 VkCommandBuffer commandBuffer
,
6181 uint32_t firstCounterBuffer
,
6182 uint32_t counterBufferCount
,
6183 const VkBuffer
* pCounterBuffers
,
6184 const VkDeviceSize
* pCounterBufferOffsets
)
6186 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6188 if (cmd_buffer
->device
->physical_device
->use_ngg_streamout
) {
6189 gfx10_emit_streamout_begin(cmd_buffer
,
6190 firstCounterBuffer
, counterBufferCount
,
6191 pCounterBuffers
, pCounterBufferOffsets
);
6193 radv_emit_streamout_begin(cmd_buffer
,
6194 firstCounterBuffer
, counterBufferCount
,
6195 pCounterBuffers
, pCounterBufferOffsets
);
6200 radv_emit_streamout_end(struct radv_cmd_buffer
*cmd_buffer
,
6201 uint32_t firstCounterBuffer
,
6202 uint32_t counterBufferCount
,
6203 const VkBuffer
*pCounterBuffers
,
6204 const VkDeviceSize
*pCounterBufferOffsets
)
6206 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
6207 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
6210 radv_flush_vgt_streamout(cmd_buffer
);
6212 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
6213 for_each_bit(i
, so
->enabled_mask
) {
6214 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
6215 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
6216 counter_buffer_idx
= -1;
6218 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
6219 /* The array of counters buffer is optional. */
6220 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
6221 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
6223 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
6225 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
6226 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
6227 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6228 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE
) |
6229 STRMOUT_STORE_BUFFER_FILLED_SIZE
); /* control */
6230 radeon_emit(cs
, va
); /* dst address lo */
6231 radeon_emit(cs
, va
>> 32); /* dst address hi */
6232 radeon_emit(cs
, 0); /* unused */
6233 radeon_emit(cs
, 0); /* unused */
6235 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
6238 /* Deactivate transform feedback by zeroing the buffer size.
6239 * The counters (primitives generated, primitives emitted) may
6240 * be enabled even if there is not buffer bound. This ensures
6241 * that the primitives-emitted query won't increment.
6243 radeon_set_context_reg(cs
, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0
+ 16*i
, 0);
6245 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
6248 radv_set_streamout_enable(cmd_buffer
, false);
6252 gfx10_emit_streamout_end(struct radv_cmd_buffer
*cmd_buffer
,
6253 uint32_t firstCounterBuffer
,
6254 uint32_t counterBufferCount
,
6255 const VkBuffer
*pCounterBuffers
,
6256 const VkDeviceSize
*pCounterBufferOffsets
)
6258 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
6259 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
6262 assert(cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
6263 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
6265 for_each_bit(i
, so
->enabled_mask
) {
6266 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
6267 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
6268 counter_buffer_idx
= -1;
6270 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
6271 /* The array of counters buffer is optional. */
6272 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
6273 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
6275 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
6277 si_cs_emit_write_event_eop(cs
,
6278 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
6279 radv_cmd_buffer_uses_mec(cmd_buffer
),
6280 V_028A90_PS_DONE
, 0,
6283 va
, EOP_DATA_GDS(i
, 1), 0);
6285 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
6289 radv_set_streamout_enable(cmd_buffer
, false);
6292 void radv_CmdEndTransformFeedbackEXT(
6293 VkCommandBuffer commandBuffer
,
6294 uint32_t firstCounterBuffer
,
6295 uint32_t counterBufferCount
,
6296 const VkBuffer
* pCounterBuffers
,
6297 const VkDeviceSize
* pCounterBufferOffsets
)
6299 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6301 if (cmd_buffer
->device
->physical_device
->use_ngg_streamout
) {
6302 gfx10_emit_streamout_end(cmd_buffer
,
6303 firstCounterBuffer
, counterBufferCount
,
6304 pCounterBuffers
, pCounterBufferOffsets
);
6306 radv_emit_streamout_end(cmd_buffer
,
6307 firstCounterBuffer
, counterBufferCount
,
6308 pCounterBuffers
, pCounterBufferOffsets
);
6312 void radv_CmdDrawIndirectByteCountEXT(
6313 VkCommandBuffer commandBuffer
,
6314 uint32_t instanceCount
,
6315 uint32_t firstInstance
,
6316 VkBuffer _counterBuffer
,
6317 VkDeviceSize counterBufferOffset
,
6318 uint32_t counterOffset
,
6319 uint32_t vertexStride
)
6321 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6322 RADV_FROM_HANDLE(radv_buffer
, counterBuffer
, _counterBuffer
);
6323 struct radv_draw_info info
= {};
6325 info
.instance_count
= instanceCount
;
6326 info
.first_instance
= firstInstance
;
6327 info
.strmout_buffer
= counterBuffer
;
6328 info
.strmout_buffer_offset
= counterBufferOffset
;
6329 info
.stride
= vertexStride
;
6331 radv_draw(cmd_buffer
, &info
);
6334 /* VK_AMD_buffer_marker */
6335 void radv_CmdWriteBufferMarkerAMD(
6336 VkCommandBuffer commandBuffer
,
6337 VkPipelineStageFlagBits pipelineStage
,
6339 VkDeviceSize dstOffset
,
6342 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6343 RADV_FROM_HANDLE(radv_buffer
, buffer
, dstBuffer
);
6344 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
6345 uint64_t va
= radv_buffer_get_va(buffer
->bo
) + dstOffset
;
6347 si_emit_cache_flush(cmd_buffer
);
6349 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 12);
6351 if (!(pipelineStage
& ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
)) {
6352 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
6353 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_IMM
) |
6354 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM
) |
6355 COPY_DATA_WR_CONFIRM
);
6356 radeon_emit(cs
, marker
);
6358 radeon_emit(cs
, va
);
6359 radeon_emit(cs
, va
>> 32);
6361 si_cs_emit_write_event_eop(cs
,
6362 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
6363 radv_cmd_buffer_uses_mec(cmd_buffer
),
6364 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
6366 EOP_DATA_SEL_VALUE_32BIT
,
6368 cmd_buffer
->gfx9_eop_bug_va
);
6371 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);