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radv: Use correct clear words for HTILE.
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_cs.h"
31 #include "sid.h"
32 #include "vk_format.h"
33 #include "radv_meta.h"
34
35 #include "ac_debug.h"
36
37 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
38 struct radv_image *image,
39 VkImageLayout src_layout,
40 VkImageLayout dst_layout,
41 uint32_t src_family,
42 uint32_t dst_family,
43 const VkImageSubresourceRange *range,
44 VkImageAspectFlags pending_clears);
45
46 const struct radv_dynamic_state default_dynamic_state = {
47 .viewport = {
48 .count = 0,
49 },
50 .scissor = {
51 .count = 0,
52 },
53 .line_width = 1.0f,
54 .depth_bias = {
55 .bias = 0.0f,
56 .clamp = 0.0f,
57 .slope = 0.0f,
58 },
59 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
60 .depth_bounds = {
61 .min = 0.0f,
62 .max = 1.0f,
63 },
64 .stencil_compare_mask = {
65 .front = ~0u,
66 .back = ~0u,
67 },
68 .stencil_write_mask = {
69 .front = ~0u,
70 .back = ~0u,
71 },
72 .stencil_reference = {
73 .front = 0u,
74 .back = 0u,
75 },
76 };
77
78 void
79 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
80 const struct radv_dynamic_state *src,
81 uint32_t copy_mask)
82 {
83 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
84 dest->viewport.count = src->viewport.count;
85 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
86 src->viewport.count);
87 }
88
89 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
90 dest->scissor.count = src->scissor.count;
91 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
92 src->scissor.count);
93 }
94
95 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
96 dest->line_width = src->line_width;
97
98 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
99 dest->depth_bias = src->depth_bias;
100
101 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
102 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
103
104 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
105 dest->depth_bounds = src->depth_bounds;
106
107 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
108 dest->stencil_compare_mask = src->stencil_compare_mask;
109
110 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
111 dest->stencil_write_mask = src->stencil_write_mask;
112
113 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
114 dest->stencil_reference = src->stencil_reference;
115 }
116
117 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
118 {
119 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
120 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
121 }
122
123 enum ring_type radv_queue_family_to_ring(int f) {
124 switch (f) {
125 case RADV_QUEUE_GENERAL:
126 return RING_GFX;
127 case RADV_QUEUE_COMPUTE:
128 return RING_COMPUTE;
129 case RADV_QUEUE_TRANSFER:
130 return RING_DMA;
131 default:
132 unreachable("Unknown queue family");
133 }
134 }
135
136 static VkResult radv_create_cmd_buffer(
137 struct radv_device * device,
138 struct radv_cmd_pool * pool,
139 VkCommandBufferLevel level,
140 VkCommandBuffer* pCommandBuffer)
141 {
142 struct radv_cmd_buffer *cmd_buffer;
143 VkResult result;
144 unsigned ring;
145 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
146 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
147 if (cmd_buffer == NULL)
148 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
149
150 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
151 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
152 cmd_buffer->device = device;
153 cmd_buffer->pool = pool;
154 cmd_buffer->level = level;
155
156 if (pool) {
157 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
158 cmd_buffer->queue_family_index = pool->queue_family_index;
159
160 } else {
161 /* Init the pool_link so we can safefly call list_del when we destroy
162 * the command buffer
163 */
164 list_inithead(&cmd_buffer->pool_link);
165 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
166 }
167
168 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
169
170 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
171 if (!cmd_buffer->cs) {
172 result = VK_ERROR_OUT_OF_HOST_MEMORY;
173 goto fail;
174 }
175
176 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
177
178 cmd_buffer->upload.offset = 0;
179 cmd_buffer->upload.size = 0;
180 list_inithead(&cmd_buffer->upload.list);
181
182 return VK_SUCCESS;
183
184 fail:
185 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
186
187 return result;
188 }
189
190 static void
191 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
192 {
193 list_del(&cmd_buffer->pool_link);
194
195 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
196 &cmd_buffer->upload.list, list) {
197 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
198 list_del(&up->list);
199 free(up);
200 }
201
202 if (cmd_buffer->upload.upload_bo)
203 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
204 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
205 free(cmd_buffer->push_descriptors.set.mapped_ptr);
206 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
207 }
208
209 static void radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
210 {
211
212 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
213
214 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
215 &cmd_buffer->upload.list, list) {
216 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
217 list_del(&up->list);
218 free(up);
219 }
220
221 cmd_buffer->scratch_size_needed = 0;
222 cmd_buffer->compute_scratch_size_needed = 0;
223 cmd_buffer->esgs_ring_size_needed = 0;
224 cmd_buffer->gsvs_ring_size_needed = 0;
225 cmd_buffer->tess_rings_needed = false;
226 cmd_buffer->sample_positions_needed = false;
227
228 if (cmd_buffer->upload.upload_bo)
229 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
230 cmd_buffer->upload.upload_bo, 8);
231 cmd_buffer->upload.offset = 0;
232
233 cmd_buffer->record_fail = false;
234
235 cmd_buffer->ring_offsets_idx = -1;
236 }
237
238 static bool
239 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
240 uint64_t min_needed)
241 {
242 uint64_t new_size;
243 struct radeon_winsys_bo *bo;
244 struct radv_cmd_buffer_upload *upload;
245 struct radv_device *device = cmd_buffer->device;
246
247 new_size = MAX2(min_needed, 16 * 1024);
248 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
249
250 bo = device->ws->buffer_create(device->ws,
251 new_size, 4096,
252 RADEON_DOMAIN_GTT,
253 RADEON_FLAG_CPU_ACCESS);
254
255 if (!bo) {
256 cmd_buffer->record_fail = true;
257 return false;
258 }
259
260 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
261 if (cmd_buffer->upload.upload_bo) {
262 upload = malloc(sizeof(*upload));
263
264 if (!upload) {
265 cmd_buffer->record_fail = true;
266 device->ws->buffer_destroy(bo);
267 return false;
268 }
269
270 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
271 list_add(&upload->list, &cmd_buffer->upload.list);
272 }
273
274 cmd_buffer->upload.upload_bo = bo;
275 cmd_buffer->upload.size = new_size;
276 cmd_buffer->upload.offset = 0;
277 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
278
279 if (!cmd_buffer->upload.map) {
280 cmd_buffer->record_fail = true;
281 return false;
282 }
283
284 return true;
285 }
286
287 bool
288 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
289 unsigned size,
290 unsigned alignment,
291 unsigned *out_offset,
292 void **ptr)
293 {
294 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
295 if (offset + size > cmd_buffer->upload.size) {
296 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
297 return false;
298 offset = 0;
299 }
300
301 *out_offset = offset;
302 *ptr = cmd_buffer->upload.map + offset;
303
304 cmd_buffer->upload.offset = offset + size;
305 return true;
306 }
307
308 bool
309 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
310 unsigned size, unsigned alignment,
311 const void *data, unsigned *out_offset)
312 {
313 uint8_t *ptr;
314
315 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
316 out_offset, (void **)&ptr))
317 return false;
318
319 if (ptr)
320 memcpy(ptr, data, size);
321
322 return true;
323 }
324
325 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
326 {
327 struct radv_device *device = cmd_buffer->device;
328 struct radeon_winsys_cs *cs = cmd_buffer->cs;
329 uint64_t va;
330
331 if (!device->trace_bo)
332 return;
333
334 va = device->ws->buffer_get_va(device->trace_bo);
335
336 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
337
338 ++cmd_buffer->state.trace_id;
339 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
340 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
341 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
342 S_370_WR_CONFIRM(1) |
343 S_370_ENGINE_SEL(V_370_ME));
344 radeon_emit(cs, va);
345 radeon_emit(cs, va >> 32);
346 radeon_emit(cs, cmd_buffer->state.trace_id);
347 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
348 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
349 }
350
351 static void
352 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
353 struct radv_pipeline *pipeline)
354 {
355 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
356 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
357 8);
358 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
359 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
360 }
361
362 static void
363 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
364 struct radv_pipeline *pipeline)
365 {
366 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
367 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
368 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
369
370 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
371 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
372 }
373
374 /* 12.4 fixed-point */
375 static unsigned radv_pack_float_12p4(float x)
376 {
377 return x <= 0 ? 0 :
378 x >= 4096 ? 0xffff : x * 16;
379 }
380
381 static uint32_t
382 shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs, bool has_tess)
383 {
384 switch (stage) {
385 case MESA_SHADER_FRAGMENT:
386 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
387 case MESA_SHADER_VERTEX:
388 if (has_tess)
389 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
390 else
391 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
392 case MESA_SHADER_GEOMETRY:
393 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
394 case MESA_SHADER_COMPUTE:
395 return R_00B900_COMPUTE_USER_DATA_0;
396 case MESA_SHADER_TESS_CTRL:
397 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
398 case MESA_SHADER_TESS_EVAL:
399 if (has_gs)
400 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
401 else
402 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
403 default:
404 unreachable("unknown shader");
405 }
406 }
407
408 static struct ac_userdata_info *
409 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
410 gl_shader_stage stage,
411 int idx)
412 {
413 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
414 }
415
416 static void
417 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
418 struct radv_pipeline *pipeline,
419 gl_shader_stage stage,
420 int idx, uint64_t va)
421 {
422 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
423 uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
424 if (loc->sgpr_idx == -1)
425 return;
426 assert(loc->num_sgprs == 2);
427 assert(!loc->indirect);
428 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
429 radeon_emit(cmd_buffer->cs, va);
430 radeon_emit(cmd_buffer->cs, va >> 32);
431 }
432
433 static void
434 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
435 struct radv_pipeline *pipeline)
436 {
437 int num_samples = pipeline->graphics.ms.num_samples;
438 struct radv_multisample_state *ms = &pipeline->graphics.ms;
439 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
440
441 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
442 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
443 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
444
445 radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa);
446 radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
447
448 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
449 return;
450
451 radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
452 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
453 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
454
455 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
456
457 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
458 uint32_t offset;
459 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
460 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
461 if (loc->sgpr_idx == -1)
462 return;
463 assert(loc->num_sgprs == 1);
464 assert(!loc->indirect);
465 switch (num_samples) {
466 default:
467 offset = 0;
468 break;
469 case 2:
470 offset = 1;
471 break;
472 case 4:
473 offset = 3;
474 break;
475 case 8:
476 offset = 7;
477 break;
478 case 16:
479 offset = 15;
480 break;
481 }
482
483 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
484 cmd_buffer->sample_positions_needed = true;
485 }
486 }
487
488 static void
489 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
490 struct radv_pipeline *pipeline)
491 {
492 struct radv_raster_state *raster = &pipeline->graphics.raster;
493
494 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
495 raster->pa_cl_clip_cntl);
496
497 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
498 raster->spi_interp_control);
499
500 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A00_PA_SU_POINT_SIZE, 2);
501 unsigned tmp = (unsigned)(1.0 * 8.0);
502 radeon_emit(cmd_buffer->cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
503 radeon_emit(cmd_buffer->cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
504 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
505
506 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
507 raster->pa_su_vtx_cntl);
508
509 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
510 raster->pa_su_sc_mode_cntl);
511 }
512
513 static void
514 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
515 struct radv_pipeline *pipeline,
516 struct radv_shader_variant *shader,
517 struct ac_vs_output_info *outinfo)
518 {
519 struct radeon_winsys *ws = cmd_buffer->device->ws;
520 uint64_t va = ws->buffer_get_va(shader->bo);
521 unsigned export_count;
522
523 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
524 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
525
526 export_count = MAX2(1, outinfo->param_exports);
527 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
528 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
529
530 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
531 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
532 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
533 V_02870C_SPI_SHADER_4COMP :
534 V_02870C_SPI_SHADER_NONE) |
535 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
536 V_02870C_SPI_SHADER_4COMP :
537 V_02870C_SPI_SHADER_NONE) |
538 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
539 V_02870C_SPI_SHADER_4COMP :
540 V_02870C_SPI_SHADER_NONE));
541
542
543 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
544 radeon_emit(cmd_buffer->cs, va >> 8);
545 radeon_emit(cmd_buffer->cs, va >> 40);
546 radeon_emit(cmd_buffer->cs, shader->rsrc1);
547 radeon_emit(cmd_buffer->cs, shader->rsrc2);
548
549 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
550 S_028818_VTX_W0_FMT(1) |
551 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
552 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
553 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
554
555
556 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
557 pipeline->graphics.pa_cl_vs_out_cntl);
558
559 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
560 S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
561 }
562
563 static void
564 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
565 struct radv_shader_variant *shader,
566 struct ac_es_output_info *outinfo)
567 {
568 struct radeon_winsys *ws = cmd_buffer->device->ws;
569 uint64_t va = ws->buffer_get_va(shader->bo);
570
571 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
572 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
573
574 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
575 outinfo->esgs_itemsize / 4);
576 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
577 radeon_emit(cmd_buffer->cs, va >> 8);
578 radeon_emit(cmd_buffer->cs, va >> 40);
579 radeon_emit(cmd_buffer->cs, shader->rsrc1);
580 radeon_emit(cmd_buffer->cs, shader->rsrc2);
581 }
582
583 static void
584 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
585 struct radv_shader_variant *shader)
586 {
587 struct radeon_winsys *ws = cmd_buffer->device->ws;
588 uint64_t va = ws->buffer_get_va(shader->bo);
589 uint32_t rsrc2 = shader->rsrc2;
590
591 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
592 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
593
594 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
595 radeon_emit(cmd_buffer->cs, va >> 8);
596 radeon_emit(cmd_buffer->cs, va >> 40);
597
598 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
599 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
600 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
601 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
602
603 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
604 radeon_emit(cmd_buffer->cs, shader->rsrc1);
605 radeon_emit(cmd_buffer->cs, rsrc2);
606 }
607
608 static void
609 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
610 struct radv_shader_variant *shader)
611 {
612 struct radeon_winsys *ws = cmd_buffer->device->ws;
613 uint64_t va = ws->buffer_get_va(shader->bo);
614
615 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
616 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
617
618 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
619 radeon_emit(cmd_buffer->cs, va >> 8);
620 radeon_emit(cmd_buffer->cs, va >> 40);
621 radeon_emit(cmd_buffer->cs, shader->rsrc1);
622 radeon_emit(cmd_buffer->cs, shader->rsrc2);
623 }
624
625 static void
626 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
627 struct radv_pipeline *pipeline)
628 {
629 struct radv_shader_variant *vs;
630
631 assert (pipeline->shaders[MESA_SHADER_VERTEX]);
632
633 vs = pipeline->shaders[MESA_SHADER_VERTEX];
634
635 if (vs->info.vs.as_ls)
636 radv_emit_hw_ls(cmd_buffer, vs);
637 else if (vs->info.vs.as_es)
638 radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info);
639 else
640 radv_emit_hw_vs(cmd_buffer, pipeline, vs, &vs->info.vs.outinfo);
641
642 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, 0);
643 }
644
645
646 static void
647 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
648 struct radv_pipeline *pipeline)
649 {
650 if (!radv_pipeline_has_tess(pipeline))
651 return;
652
653 struct radv_shader_variant *tes, *tcs;
654
655 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
656 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
657
658 if (tes->info.tes.as_es)
659 radv_emit_hw_es(cmd_buffer, tes, &tes->info.tes.es_info);
660 else
661 radv_emit_hw_vs(cmd_buffer, pipeline, tes, &tes->info.tes.outinfo);
662
663 radv_emit_hw_hs(cmd_buffer, tcs);
664
665 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
666 pipeline->graphics.tess.tf_param);
667
668 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
669 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
670 pipeline->graphics.tess.ls_hs_config);
671 else
672 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
673 pipeline->graphics.tess.ls_hs_config);
674
675 struct ac_userdata_info *loc;
676
677 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
678 if (loc->sgpr_idx != -1) {
679 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
680 assert(loc->num_sgprs == 4);
681 assert(!loc->indirect);
682 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
683 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
684 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
685 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
686 pipeline->graphics.tess.num_tcs_input_cp << 26);
687 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
688 }
689
690 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
691 if (loc->sgpr_idx != -1) {
692 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
693 assert(loc->num_sgprs == 1);
694 assert(!loc->indirect);
695
696 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
697 pipeline->graphics.tess.offchip_layout);
698 }
699
700 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
701 if (loc->sgpr_idx != -1) {
702 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
703 assert(loc->num_sgprs == 1);
704 assert(!loc->indirect);
705
706 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
707 pipeline->graphics.tess.tcs_in_layout);
708 }
709 }
710
711 static void
712 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
713 struct radv_pipeline *pipeline)
714 {
715 struct radeon_winsys *ws = cmd_buffer->device->ws;
716 struct radv_shader_variant *gs;
717 uint64_t va;
718
719 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
720
721 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
722 if (!gs)
723 return;
724
725 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
726
727 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
728 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
729 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
730 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
731
732 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
733
734 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
735
736 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
737 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
738 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
739 radeon_emit(cmd_buffer->cs, 0);
740 radeon_emit(cmd_buffer->cs, 0);
741 radeon_emit(cmd_buffer->cs, 0);
742
743 uint32_t gs_num_invocations = gs->info.gs.invocations;
744 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
745 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
746 S_028B90_ENABLE(gs_num_invocations > 0));
747
748 va = ws->buffer_get_va(gs->bo);
749 ws->cs_add_buffer(cmd_buffer->cs, gs->bo, 8);
750 si_cp_dma_prefetch(cmd_buffer, va, gs->code_size);
751 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
752 radeon_emit(cmd_buffer->cs, va >> 8);
753 radeon_emit(cmd_buffer->cs, va >> 40);
754 radeon_emit(cmd_buffer->cs, gs->rsrc1);
755 radeon_emit(cmd_buffer->cs, gs->rsrc2);
756
757 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader, &pipeline->gs_copy_shader->info.vs.outinfo);
758
759 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
760 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
761 if (loc->sgpr_idx != -1) {
762 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
763 uint32_t num_entries = 64;
764 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
765
766 if (is_vi)
767 num_entries *= stride;
768
769 stride = S_008F04_STRIDE(stride);
770 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
771 radeon_emit(cmd_buffer->cs, stride);
772 radeon_emit(cmd_buffer->cs, num_entries);
773 }
774 }
775
776 static void
777 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
778 struct radv_pipeline *pipeline)
779 {
780 struct radeon_winsys *ws = cmd_buffer->device->ws;
781 struct radv_shader_variant *ps;
782 uint64_t va;
783 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
784 struct radv_blend_state *blend = &pipeline->graphics.blend;
785 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
786
787 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
788
789 va = ws->buffer_get_va(ps->bo);
790 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
791 si_cp_dma_prefetch(cmd_buffer, va, ps->code_size);
792
793 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
794 radeon_emit(cmd_buffer->cs, va >> 8);
795 radeon_emit(cmd_buffer->cs, va >> 40);
796 radeon_emit(cmd_buffer->cs, ps->rsrc1);
797 radeon_emit(cmd_buffer->cs, ps->rsrc2);
798
799 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
800 pipeline->graphics.db_shader_control);
801
802 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
803 ps->config.spi_ps_input_ena);
804
805 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
806 ps->config.spi_ps_input_addr);
807
808 if (ps->info.fs.force_persample)
809 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
810
811 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
812 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
813
814 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
815
816 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
817 pipeline->graphics.shader_z_format);
818
819 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
820
821 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
822 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
823
824 if (pipeline->graphics.ps_input_cntl_num) {
825 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
826 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
827 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
828 }
829 }
830 }
831
832 static void polaris_set_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
833 struct radv_pipeline *pipeline)
834 {
835 uint32_t vtx_reuse_depth = 30;
836 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
837 return;
838
839 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
840 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD)
841 vtx_reuse_depth = 14;
842 }
843 radeon_set_context_reg(cmd_buffer->cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
844 vtx_reuse_depth);
845 }
846
847 static void
848 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer,
849 struct radv_pipeline *pipeline)
850 {
851 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
852 return;
853
854 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
855 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
856 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
857 radv_update_multisample_state(cmd_buffer, pipeline);
858 radv_emit_vertex_shader(cmd_buffer, pipeline);
859 radv_emit_tess_shaders(cmd_buffer, pipeline);
860 radv_emit_geometry_shader(cmd_buffer, pipeline);
861 radv_emit_fragment_shader(cmd_buffer, pipeline);
862 polaris_set_vgt_vertex_reuse(cmd_buffer, pipeline);
863
864 cmd_buffer->scratch_size_needed =
865 MAX2(cmd_buffer->scratch_size_needed,
866 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
867
868 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
869 S_0286E8_WAVES(pipeline->max_waves) |
870 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
871
872 if (!cmd_buffer->state.emitted_pipeline ||
873 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
874 pipeline->graphics.can_use_guardband)
875 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
876 cmd_buffer->state.emitted_pipeline = pipeline;
877 }
878
879 static void
880 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
881 {
882 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
883 cmd_buffer->state.dynamic.viewport.viewports);
884 }
885
886 static void
887 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
888 {
889 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
890 si_write_scissors(cmd_buffer->cs, 0, count,
891 cmd_buffer->state.dynamic.scissor.scissors,
892 cmd_buffer->state.dynamic.viewport.viewports,
893 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
894 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
895 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
896 }
897
898 static void
899 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
900 int index,
901 struct radv_color_buffer_info *cb)
902 {
903 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
904 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
905 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
906 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
907 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
908 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
909 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
910 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
911 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
912 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
913 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
914 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
915 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
916
917 if (is_vi) { /* DCC BASE */
918 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
919 }
920 }
921
922 static void
923 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
924 struct radv_ds_buffer_info *ds,
925 struct radv_image *image,
926 VkImageLayout layout)
927 {
928 uint32_t db_z_info = ds->db_z_info;
929 uint32_t db_stencil_info = ds->db_stencil_info;
930
931 if (!radv_layout_has_htile(image, layout,
932 radv_image_queue_family_mask(image,
933 cmd_buffer->queue_family_index,
934 cmd_buffer->queue_family_index))) {
935 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
936 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
937 }
938
939 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
940 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
941
942 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
943 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
944 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
945 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
946 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
947 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
948 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
949 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
950 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
951 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
952
953 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
954 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
955 ds->pa_su_poly_offset_db_fmt_cntl);
956 }
957
958 void
959 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
960 struct radv_image *image,
961 VkClearDepthStencilValue ds_clear_value,
962 VkImageAspectFlags aspects)
963 {
964 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
965 va += image->offset + image->clear_value_offset;
966 unsigned reg_offset = 0, reg_count = 0;
967
968 if (!image->surface.htile_size || !aspects)
969 return;
970
971 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
972 ++reg_count;
973 } else {
974 ++reg_offset;
975 va += 4;
976 }
977 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
978 ++reg_count;
979
980 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
981
982 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
983 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
984 S_370_WR_CONFIRM(1) |
985 S_370_ENGINE_SEL(V_370_PFP));
986 radeon_emit(cmd_buffer->cs, va);
987 radeon_emit(cmd_buffer->cs, va >> 32);
988 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
989 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
990 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
991 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
992
993 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
994 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
995 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
996 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
997 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
998 }
999
1000 static void
1001 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1002 struct radv_image *image)
1003 {
1004 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1005 va += image->offset + image->clear_value_offset;
1006
1007 if (!image->surface.htile_size)
1008 return;
1009
1010 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1011
1012 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1013 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1014 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1015 COPY_DATA_COUNT_SEL);
1016 radeon_emit(cmd_buffer->cs, va);
1017 radeon_emit(cmd_buffer->cs, va >> 32);
1018 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
1019 radeon_emit(cmd_buffer->cs, 0);
1020
1021 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1022 radeon_emit(cmd_buffer->cs, 0);
1023 }
1024
1025 void
1026 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1027 struct radv_image *image,
1028 int idx,
1029 uint32_t color_values[2])
1030 {
1031 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1032 va += image->offset + image->clear_value_offset;
1033
1034 if (!image->cmask.size && !image->surface.dcc_size)
1035 return;
1036
1037 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1038
1039 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1040 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1041 S_370_WR_CONFIRM(1) |
1042 S_370_ENGINE_SEL(V_370_PFP));
1043 radeon_emit(cmd_buffer->cs, va);
1044 radeon_emit(cmd_buffer->cs, va >> 32);
1045 radeon_emit(cmd_buffer->cs, color_values[0]);
1046 radeon_emit(cmd_buffer->cs, color_values[1]);
1047
1048 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1049 radeon_emit(cmd_buffer->cs, color_values[0]);
1050 radeon_emit(cmd_buffer->cs, color_values[1]);
1051 }
1052
1053 static void
1054 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1055 struct radv_image *image,
1056 int idx)
1057 {
1058 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1059 va += image->offset + image->clear_value_offset;
1060
1061 if (!image->cmask.size && !image->surface.dcc_size)
1062 return;
1063
1064 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1065 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1066
1067 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1068 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1069 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1070 COPY_DATA_COUNT_SEL);
1071 radeon_emit(cmd_buffer->cs, va);
1072 radeon_emit(cmd_buffer->cs, va >> 32);
1073 radeon_emit(cmd_buffer->cs, reg >> 2);
1074 radeon_emit(cmd_buffer->cs, 0);
1075
1076 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1077 radeon_emit(cmd_buffer->cs, 0);
1078 }
1079
1080 void
1081 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1082 {
1083 int i;
1084 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1085 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1086
1087 for (i = 0; i < subpass->color_count; ++i) {
1088 int idx = subpass->color_attachments[i].attachment;
1089 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1090
1091 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1092
1093 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1094 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1095
1096 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1097 }
1098
1099 for (i = subpass->color_count; i < 8; i++)
1100 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1101 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1102
1103 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1104 int idx = subpass->depth_stencil_attachment.attachment;
1105 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1106 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1107 struct radv_image *image = att->attachment->image;
1108 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1109 uint32_t queue_mask = radv_image_queue_family_mask(image,
1110 cmd_buffer->queue_family_index,
1111 cmd_buffer->queue_family_index);
1112 /* We currently don't support writing decompressed HTILE */
1113 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1114 radv_layout_is_htile_compressed(image, layout, queue_mask));
1115
1116 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1117
1118 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1119 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1120 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1121 }
1122 radv_load_depth_clear_regs(cmd_buffer, image);
1123 } else {
1124 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1125 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1126 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1127 }
1128 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1129 S_028208_BR_X(framebuffer->width) |
1130 S_028208_BR_Y(framebuffer->height));
1131 }
1132
1133 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1134 {
1135 uint32_t db_count_control;
1136
1137 if(!cmd_buffer->state.active_occlusion_queries) {
1138 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1139 db_count_control = 0;
1140 } else {
1141 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1142 }
1143 } else {
1144 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1145 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1146 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1147 S_028004_ZPASS_ENABLE(1) |
1148 S_028004_SLICE_EVEN_ENABLE(1) |
1149 S_028004_SLICE_ODD_ENABLE(1);
1150 } else {
1151 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1152 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1153 }
1154 }
1155
1156 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1157 }
1158
1159 static void
1160 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1161 {
1162 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1163
1164 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1165 return;
1166
1167 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1168 radv_emit_viewport(cmd_buffer);
1169
1170 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1171 radv_emit_scissor(cmd_buffer);
1172
1173 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH) {
1174 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1175 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1176 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1177 }
1178
1179 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
1180 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1181 radeon_emit_array(cmd_buffer->cs, (uint32_t*)d->blend_constants, 4);
1182 }
1183
1184 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1185 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1186 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK)) {
1187 radeon_set_context_reg_seq(cmd_buffer->cs, R_028430_DB_STENCILREFMASK, 2);
1188 radeon_emit(cmd_buffer->cs, S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1189 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1190 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1191 S_028430_STENCILOPVAL(1));
1192 radeon_emit(cmd_buffer->cs, S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1193 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1194 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1195 S_028434_STENCILOPVAL_BF(1));
1196 }
1197
1198 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1199 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) {
1200 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, fui(d->depth_bounds.min));
1201 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX, fui(d->depth_bounds.max));
1202 }
1203
1204 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1205 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
1206 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1207 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1208 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1209
1210 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1211 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1212 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1213 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1214 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1215 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1216 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1217 }
1218 }
1219
1220 cmd_buffer->state.dirty = 0;
1221 }
1222
1223 static void
1224 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1225 struct radv_pipeline *pipeline,
1226 int idx,
1227 uint64_t va,
1228 gl_shader_stage stage)
1229 {
1230 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1231 uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
1232
1233 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1234 return;
1235
1236 assert(!desc_set_loc->indirect);
1237 assert(desc_set_loc->num_sgprs == 2);
1238 radeon_set_sh_reg_seq(cmd_buffer->cs,
1239 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1240 radeon_emit(cmd_buffer->cs, va);
1241 radeon_emit(cmd_buffer->cs, va >> 32);
1242 }
1243
1244 static void
1245 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1246 struct radv_pipeline *pipeline,
1247 VkShaderStageFlags stages,
1248 struct radv_descriptor_set *set,
1249 unsigned idx)
1250 {
1251 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1252 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1253 idx, set->va,
1254 MESA_SHADER_FRAGMENT);
1255
1256 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1257 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1258 idx, set->va,
1259 MESA_SHADER_VERTEX);
1260
1261 if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(pipeline))
1262 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1263 idx, set->va,
1264 MESA_SHADER_GEOMETRY);
1265
1266 if ((stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT) && radv_pipeline_has_tess(pipeline))
1267 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1268 idx, set->va,
1269 MESA_SHADER_TESS_CTRL);
1270
1271 if ((stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) && radv_pipeline_has_tess(pipeline))
1272 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1273 idx, set->va,
1274 MESA_SHADER_TESS_EVAL);
1275
1276 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1277 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1278 idx, set->va,
1279 MESA_SHADER_COMPUTE);
1280 }
1281
1282 static void
1283 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1284 {
1285 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1286 uint32_t *ptr = NULL;
1287 unsigned bo_offset;
1288
1289 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, set->size, 32,
1290 &bo_offset,
1291 (void**) &ptr))
1292 return;
1293
1294 set->va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1295 set->va += bo_offset;
1296
1297 memcpy(ptr, set->mapped_ptr, set->size);
1298 }
1299
1300 static void
1301 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1302 struct radv_pipeline *pipeline)
1303 {
1304 uint32_t size = MAX_SETS * 2 * 4;
1305 uint32_t offset;
1306 void *ptr;
1307
1308 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1309 256, &offset, &ptr))
1310 return;
1311
1312 for (unsigned i = 0; i < MAX_SETS; i++) {
1313 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1314 uint64_t set_va = 0;
1315 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1316 if (set)
1317 set_va = set->va;
1318 uptr[0] = set_va & 0xffffffff;
1319 uptr[1] = set_va >> 32;
1320 }
1321
1322 uint64_t va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1323 va += offset;
1324
1325 if (pipeline->shaders[MESA_SHADER_VERTEX])
1326 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1327 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1328
1329 if (pipeline->shaders[MESA_SHADER_FRAGMENT])
1330 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
1331 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1332
1333 if (radv_pipeline_has_gs(pipeline))
1334 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_GEOMETRY,
1335 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1336
1337 if (radv_pipeline_has_tess(pipeline))
1338 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_TESS_CTRL,
1339 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1340
1341 if (radv_pipeline_has_tess(pipeline))
1342 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_TESS_EVAL,
1343 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1344
1345 if (pipeline->shaders[MESA_SHADER_COMPUTE])
1346 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_COMPUTE,
1347 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1348 }
1349
1350 static void
1351 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1352 struct radv_pipeline *pipeline,
1353 VkShaderStageFlags stages)
1354 {
1355 unsigned i;
1356
1357 if (!cmd_buffer->state.descriptors_dirty)
1358 return;
1359
1360 if (cmd_buffer->state.push_descriptors_dirty)
1361 radv_flush_push_descriptors(cmd_buffer);
1362
1363 if (pipeline->need_indirect_descriptor_sets) {
1364 radv_flush_indirect_descriptor_sets(cmd_buffer, pipeline);
1365 }
1366
1367 for (i = 0; i < MAX_SETS; i++) {
1368 if (!(cmd_buffer->state.descriptors_dirty & (1u << i)))
1369 continue;
1370 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1371 if (!set)
1372 continue;
1373
1374 radv_emit_descriptor_set_userdata(cmd_buffer, pipeline, stages, set, i);
1375 }
1376 cmd_buffer->state.descriptors_dirty = 0;
1377 cmd_buffer->state.push_descriptors_dirty = false;
1378 }
1379
1380 static void
1381 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1382 struct radv_pipeline *pipeline,
1383 VkShaderStageFlags stages)
1384 {
1385 struct radv_pipeline_layout *layout = pipeline->layout;
1386 unsigned offset;
1387 void *ptr;
1388 uint64_t va;
1389
1390 stages &= cmd_buffer->push_constant_stages;
1391 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1392 return;
1393
1394 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1395 16 * layout->dynamic_offset_count,
1396 256, &offset, &ptr))
1397 return;
1398
1399 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1400 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1401 16 * layout->dynamic_offset_count);
1402
1403 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1404 va += offset;
1405
1406 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1407 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1408 AC_UD_PUSH_CONSTANTS, va);
1409
1410 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1411 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
1412 AC_UD_PUSH_CONSTANTS, va);
1413
1414 if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(pipeline))
1415 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_GEOMETRY,
1416 AC_UD_PUSH_CONSTANTS, va);
1417
1418 if ((stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT) && radv_pipeline_has_tess(pipeline))
1419 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_TESS_CTRL,
1420 AC_UD_PUSH_CONSTANTS, va);
1421
1422 if ((stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) && radv_pipeline_has_tess(pipeline))
1423 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_TESS_EVAL,
1424 AC_UD_PUSH_CONSTANTS, va);
1425
1426 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1427 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_COMPUTE,
1428 AC_UD_PUSH_CONSTANTS, va);
1429
1430 cmd_buffer->push_constant_stages &= ~stages;
1431 }
1432
1433 static void radv_emit_primitive_reset_state(struct radv_cmd_buffer *cmd_buffer,
1434 bool indexed_draw)
1435 {
1436 int32_t primitive_reset_en = indexed_draw && cmd_buffer->state.pipeline->graphics.prim_restart_enable;
1437
1438 if (primitive_reset_en != cmd_buffer->state.last_primitive_reset_en) {
1439 cmd_buffer->state.last_primitive_reset_en = primitive_reset_en;
1440 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1441 primitive_reset_en);
1442 }
1443
1444 if (primitive_reset_en) {
1445 uint32_t primitive_reset_index = cmd_buffer->state.index_type ? 0xffffffffu : 0xffffu;
1446
1447 if (primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
1448 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
1449 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1450 primitive_reset_index);
1451 }
1452 }
1453 }
1454
1455 static void
1456 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer,
1457 bool indexed_draw, bool instanced_draw,
1458 bool indirect_draw,
1459 uint32_t draw_vertex_count)
1460 {
1461 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1462 struct radv_device *device = cmd_buffer->device;
1463 uint32_t ia_multi_vgt_param;
1464
1465 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1466 cmd_buffer->cs, 4096);
1467
1468 if ((cmd_buffer->state.vertex_descriptors_dirty || cmd_buffer->state.vb_dirty) &&
1469 cmd_buffer->state.pipeline->num_vertex_attribs &&
1470 cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.has_vertex_buffers) {
1471 unsigned vb_offset;
1472 void *vb_ptr;
1473 uint32_t i = 0;
1474 uint32_t num_attribs = cmd_buffer->state.pipeline->num_vertex_attribs;
1475 uint64_t va;
1476
1477 /* allocate some descriptor state for vertex buffers */
1478 radv_cmd_buffer_upload_alloc(cmd_buffer, num_attribs * 16, 256,
1479 &vb_offset, &vb_ptr);
1480
1481 for (i = 0; i < num_attribs; i++) {
1482 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1483 uint32_t offset;
1484 int vb = cmd_buffer->state.pipeline->va_binding[i];
1485 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1486 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1487
1488 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1489 va = device->ws->buffer_get_va(buffer->bo);
1490
1491 offset = cmd_buffer->state.vertex_bindings[vb].offset + cmd_buffer->state.pipeline->va_offset[i];
1492 va += offset + buffer->offset;
1493 desc[0] = va;
1494 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1495 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1496 desc[2] = (buffer->size - offset - cmd_buffer->state.pipeline->va_format_size[i]) / stride + 1;
1497 else
1498 desc[2] = buffer->size - offset;
1499 desc[3] = cmd_buffer->state.pipeline->va_rsrc_word3[i];
1500 }
1501
1502 va = device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1503 va += vb_offset;
1504
1505 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1506 AC_UD_VS_VERTEX_BUFFERS, va);
1507 }
1508
1509 cmd_buffer->state.vertex_descriptors_dirty = false;
1510 cmd_buffer->state.vb_dirty = 0;
1511 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1512 radv_emit_graphics_pipeline(cmd_buffer, pipeline);
1513
1514 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1515 radv_emit_framebuffer_state(cmd_buffer);
1516
1517 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, draw_vertex_count);
1518 if (cmd_buffer->state.last_ia_multi_vgt_param != ia_multi_vgt_param) {
1519 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
1520 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1521 else
1522 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1523 cmd_buffer->state.last_ia_multi_vgt_param = ia_multi_vgt_param;
1524 }
1525
1526 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) {
1527 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
1528
1529 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1530 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, cmd_buffer->state.pipeline->graphics.prim);
1531 } else {
1532 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, cmd_buffer->state.pipeline->graphics.prim);
1533 }
1534 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, cmd_buffer->state.pipeline->graphics.gs_out);
1535 }
1536
1537 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1538
1539 radv_emit_primitive_reset_state(cmd_buffer, indexed_draw);
1540
1541 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.pipeline,
1542 VK_SHADER_STAGE_ALL_GRAPHICS);
1543 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1544 VK_SHADER_STAGE_ALL_GRAPHICS);
1545
1546 assert(cmd_buffer->cs->cdw <= cdw_max);
1547
1548 si_emit_cache_flush(cmd_buffer);
1549 }
1550
1551 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1552 VkPipelineStageFlags src_stage_mask)
1553 {
1554 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1555 VK_PIPELINE_STAGE_TRANSFER_BIT |
1556 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1557 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1558 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1559 }
1560
1561 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1562 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1563 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1564 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1565 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1566 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1567 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1568 VK_PIPELINE_STAGE_TRANSFER_BIT |
1569 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1570 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1571 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1572 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1573 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1574 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1575 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1576 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1577 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1578 }
1579 }
1580
1581 static enum radv_cmd_flush_bits
1582 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1583 VkAccessFlags src_flags)
1584 {
1585 enum radv_cmd_flush_bits flush_bits = 0;
1586 uint32_t b;
1587 for_each_bit(b, src_flags) {
1588 switch ((VkAccessFlagBits)(1 << b)) {
1589 case VK_ACCESS_SHADER_WRITE_BIT:
1590 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1591 break;
1592 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1593 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1594 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1595 break;
1596 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1597 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1598 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1599 break;
1600 case VK_ACCESS_TRANSFER_WRITE_BIT:
1601 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1602 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1603 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1604 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1605 RADV_CMD_FLAG_INV_GLOBAL_L2;
1606 break;
1607 default:
1608 break;
1609 }
1610 }
1611 return flush_bits;
1612 }
1613
1614 static enum radv_cmd_flush_bits
1615 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1616 VkAccessFlags dst_flags,
1617 struct radv_image *image)
1618 {
1619 enum radv_cmd_flush_bits flush_bits = 0;
1620 uint32_t b;
1621 for_each_bit(b, dst_flags) {
1622 switch ((VkAccessFlagBits)(1 << b)) {
1623 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1624 case VK_ACCESS_INDEX_READ_BIT:
1625 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1626 break;
1627 case VK_ACCESS_UNIFORM_READ_BIT:
1628 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1629 break;
1630 case VK_ACCESS_SHADER_READ_BIT:
1631 case VK_ACCESS_TRANSFER_READ_BIT:
1632 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1633 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1634 RADV_CMD_FLAG_INV_GLOBAL_L2;
1635 break;
1636 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1637 /* TODO: change to image && when the image gets passed
1638 * through from the subpass. */
1639 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1640 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1641 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1642 break;
1643 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1644 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1645 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1646 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1647 break;
1648 default:
1649 break;
1650 }
1651 }
1652 return flush_bits;
1653 }
1654
1655 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1656 {
1657 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1658 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1659 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1660 NULL);
1661 }
1662
1663 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1664 VkAttachmentReference att)
1665 {
1666 unsigned idx = att.attachment;
1667 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1668 VkImageSubresourceRange range;
1669 range.aspectMask = 0;
1670 range.baseMipLevel = view->base_mip;
1671 range.levelCount = 1;
1672 range.baseArrayLayer = view->base_layer;
1673 range.layerCount = cmd_buffer->state.framebuffer->layers;
1674
1675 radv_handle_image_transition(cmd_buffer,
1676 view->image,
1677 cmd_buffer->state.attachments[idx].current_layout,
1678 att.layout, 0, 0, &range,
1679 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1680
1681 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1682
1683
1684 }
1685
1686 void
1687 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1688 const struct radv_subpass *subpass, bool transitions)
1689 {
1690 if (transitions) {
1691 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1692
1693 for (unsigned i = 0; i < subpass->color_count; ++i) {
1694 radv_handle_subpass_image_transition(cmd_buffer,
1695 subpass->color_attachments[i]);
1696 }
1697
1698 for (unsigned i = 0; i < subpass->input_count; ++i) {
1699 radv_handle_subpass_image_transition(cmd_buffer,
1700 subpass->input_attachments[i]);
1701 }
1702
1703 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1704 radv_handle_subpass_image_transition(cmd_buffer,
1705 subpass->depth_stencil_attachment);
1706 }
1707 }
1708
1709 cmd_buffer->state.subpass = subpass;
1710
1711 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1712 }
1713
1714 static void
1715 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1716 struct radv_render_pass *pass,
1717 const VkRenderPassBeginInfo *info)
1718 {
1719 struct radv_cmd_state *state = &cmd_buffer->state;
1720
1721 if (pass->attachment_count == 0) {
1722 state->attachments = NULL;
1723 return;
1724 }
1725
1726 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1727 pass->attachment_count *
1728 sizeof(state->attachments[0]),
1729 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1730 if (state->attachments == NULL) {
1731 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1732 abort();
1733 }
1734
1735 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1736 struct radv_render_pass_attachment *att = &pass->attachments[i];
1737 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1738 VkImageAspectFlags clear_aspects = 0;
1739
1740 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1741 /* color attachment */
1742 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1743 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1744 }
1745 } else {
1746 /* depthstencil attachment */
1747 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1748 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1749 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1750 }
1751 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1752 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1753 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1754 }
1755 }
1756
1757 state->attachments[i].pending_clear_aspects = clear_aspects;
1758 if (clear_aspects && info) {
1759 assert(info->clearValueCount > i);
1760 state->attachments[i].clear_value = info->pClearValues[i];
1761 }
1762
1763 state->attachments[i].current_layout = att->initial_layout;
1764 }
1765 }
1766
1767 VkResult radv_AllocateCommandBuffers(
1768 VkDevice _device,
1769 const VkCommandBufferAllocateInfo *pAllocateInfo,
1770 VkCommandBuffer *pCommandBuffers)
1771 {
1772 RADV_FROM_HANDLE(radv_device, device, _device);
1773 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1774
1775 VkResult result = VK_SUCCESS;
1776 uint32_t i;
1777
1778 memset(pCommandBuffers, 0,
1779 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
1780
1781 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1782
1783 if (!list_empty(&pool->free_cmd_buffers)) {
1784 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1785
1786 list_del(&cmd_buffer->pool_link);
1787 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1788
1789 radv_reset_cmd_buffer(cmd_buffer);
1790 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1791 cmd_buffer->level = pAllocateInfo->level;
1792
1793 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
1794 result = VK_SUCCESS;
1795 } else {
1796 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1797 &pCommandBuffers[i]);
1798 }
1799 if (result != VK_SUCCESS)
1800 break;
1801 }
1802
1803 if (result != VK_SUCCESS)
1804 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1805 i, pCommandBuffers);
1806
1807 return result;
1808 }
1809
1810 void radv_FreeCommandBuffers(
1811 VkDevice device,
1812 VkCommandPool commandPool,
1813 uint32_t commandBufferCount,
1814 const VkCommandBuffer *pCommandBuffers)
1815 {
1816 for (uint32_t i = 0; i < commandBufferCount; i++) {
1817 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1818
1819 if (cmd_buffer) {
1820 if (cmd_buffer->pool) {
1821 list_del(&cmd_buffer->pool_link);
1822 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
1823 } else
1824 radv_cmd_buffer_destroy(cmd_buffer);
1825
1826 }
1827 }
1828 }
1829
1830 VkResult radv_ResetCommandBuffer(
1831 VkCommandBuffer commandBuffer,
1832 VkCommandBufferResetFlags flags)
1833 {
1834 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1835 radv_reset_cmd_buffer(cmd_buffer);
1836 return VK_SUCCESS;
1837 }
1838
1839 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
1840 {
1841 struct radv_device *device = cmd_buffer->device;
1842 if (device->gfx_init) {
1843 uint64_t va = device->ws->buffer_get_va(device->gfx_init);
1844 device->ws->cs_add_buffer(cmd_buffer->cs, device->gfx_init, 8);
1845 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
1846 radeon_emit(cmd_buffer->cs, va);
1847 radeon_emit(cmd_buffer->cs, (va >> 32) & 0xffff);
1848 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
1849 } else
1850 si_init_config(cmd_buffer);
1851 }
1852
1853 VkResult radv_BeginCommandBuffer(
1854 VkCommandBuffer commandBuffer,
1855 const VkCommandBufferBeginInfo *pBeginInfo)
1856 {
1857 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1858 radv_reset_cmd_buffer(cmd_buffer);
1859
1860 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1861 cmd_buffer->state.last_primitive_reset_en = -1;
1862
1863 /* setup initial configuration into command buffer */
1864 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1865 switch (cmd_buffer->queue_family_index) {
1866 case RADV_QUEUE_GENERAL:
1867 emit_gfx_buffer_state(cmd_buffer);
1868 radv_set_db_count_control(cmd_buffer);
1869 break;
1870 case RADV_QUEUE_COMPUTE:
1871 si_init_compute(cmd_buffer);
1872 break;
1873 case RADV_QUEUE_TRANSFER:
1874 default:
1875 break;
1876 }
1877 }
1878
1879 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1880 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1881 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1882
1883 struct radv_subpass *subpass =
1884 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1885
1886 radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1887 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
1888 }
1889
1890 radv_cmd_buffer_trace_emit(cmd_buffer);
1891 return VK_SUCCESS;
1892 }
1893
1894 void radv_CmdBindVertexBuffers(
1895 VkCommandBuffer commandBuffer,
1896 uint32_t firstBinding,
1897 uint32_t bindingCount,
1898 const VkBuffer* pBuffers,
1899 const VkDeviceSize* pOffsets)
1900 {
1901 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1902 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
1903
1904 /* We have to defer setting up vertex buffer since we need the buffer
1905 * stride from the pipeline. */
1906
1907 assert(firstBinding + bindingCount < MAX_VBS);
1908 for (uint32_t i = 0; i < bindingCount; i++) {
1909 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
1910 vb[firstBinding + i].offset = pOffsets[i];
1911 cmd_buffer->state.vb_dirty |= 1 << (firstBinding + i);
1912 }
1913 }
1914
1915 void radv_CmdBindIndexBuffer(
1916 VkCommandBuffer commandBuffer,
1917 VkBuffer buffer,
1918 VkDeviceSize offset,
1919 VkIndexType indexType)
1920 {
1921 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1922
1923 cmd_buffer->state.index_buffer = radv_buffer_from_handle(buffer);
1924 cmd_buffer->state.index_offset = offset;
1925 cmd_buffer->state.index_type = indexType; /* vk matches hw */
1926 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
1927 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, cmd_buffer->state.index_buffer->bo, 8);
1928 }
1929
1930
1931 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1932 struct radv_descriptor_set *set,
1933 unsigned idx)
1934 {
1935 struct radeon_winsys *ws = cmd_buffer->device->ws;
1936
1937 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
1938
1939 cmd_buffer->state.descriptors[idx] = set;
1940 cmd_buffer->state.descriptors_dirty |= (1u << idx);
1941 if (!set)
1942 return;
1943
1944 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
1945 if (set->descriptors[j])
1946 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
1947
1948 if(set->bo)
1949 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
1950 }
1951
1952 void radv_CmdBindDescriptorSets(
1953 VkCommandBuffer commandBuffer,
1954 VkPipelineBindPoint pipelineBindPoint,
1955 VkPipelineLayout _layout,
1956 uint32_t firstSet,
1957 uint32_t descriptorSetCount,
1958 const VkDescriptorSet* pDescriptorSets,
1959 uint32_t dynamicOffsetCount,
1960 const uint32_t* pDynamicOffsets)
1961 {
1962 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1963 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
1964 unsigned dyn_idx = 0;
1965
1966 for (unsigned i = 0; i < descriptorSetCount; ++i) {
1967 unsigned idx = i + firstSet;
1968 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
1969 radv_bind_descriptor_set(cmd_buffer, set, idx);
1970
1971 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1972 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
1973 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
1974 assert(dyn_idx < dynamicOffsetCount);
1975
1976 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
1977 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
1978 dst[0] = va;
1979 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
1980 dst[2] = range->size;
1981 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1982 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1983 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1984 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1985 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1986 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1987 cmd_buffer->push_constant_stages |=
1988 set->layout->dynamic_shader_stages;
1989 }
1990 }
1991 }
1992
1993 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1994 struct radv_descriptor_set *set,
1995 struct radv_descriptor_set_layout *layout)
1996 {
1997 set->size = layout->size;
1998 set->layout = layout;
1999
2000 if (cmd_buffer->push_descriptors.capacity < set->size) {
2001 size_t new_size = MAX2(set->size, 1024);
2002 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2003 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2004
2005 free(set->mapped_ptr);
2006 set->mapped_ptr = malloc(new_size);
2007
2008 if (!set->mapped_ptr) {
2009 cmd_buffer->push_descriptors.capacity = 0;
2010 cmd_buffer->record_fail = true;
2011 return false;
2012 }
2013
2014 cmd_buffer->push_descriptors.capacity = new_size;
2015 }
2016
2017 return true;
2018 }
2019
2020 void radv_meta_push_descriptor_set(
2021 struct radv_cmd_buffer* cmd_buffer,
2022 VkPipelineBindPoint pipelineBindPoint,
2023 VkPipelineLayout _layout,
2024 uint32_t set,
2025 uint32_t descriptorWriteCount,
2026 const VkWriteDescriptorSet* pDescriptorWrites)
2027 {
2028 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2029 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2030 unsigned bo_offset;
2031
2032 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2033
2034 push_set->size = layout->set[set].layout->size;
2035 push_set->layout = layout->set[set].layout;
2036
2037 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2038 &bo_offset,
2039 (void**) &push_set->mapped_ptr))
2040 return;
2041
2042 push_set->va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
2043 push_set->va += bo_offset;
2044
2045 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2046 radv_descriptor_set_to_handle(push_set),
2047 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2048
2049 cmd_buffer->state.descriptors[set] = push_set;
2050 cmd_buffer->state.descriptors_dirty |= (1u << set);
2051 }
2052
2053 void radv_CmdPushDescriptorSetKHR(
2054 VkCommandBuffer commandBuffer,
2055 VkPipelineBindPoint pipelineBindPoint,
2056 VkPipelineLayout _layout,
2057 uint32_t set,
2058 uint32_t descriptorWriteCount,
2059 const VkWriteDescriptorSet* pDescriptorWrites)
2060 {
2061 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2062 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2063 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2064
2065 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2066
2067 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2068 return;
2069
2070 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2071 radv_descriptor_set_to_handle(push_set),
2072 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2073
2074 cmd_buffer->state.descriptors[set] = push_set;
2075 cmd_buffer->state.descriptors_dirty |= (1u << set);
2076 cmd_buffer->state.push_descriptors_dirty = true;
2077 }
2078
2079 void radv_CmdPushDescriptorSetWithTemplateKHR(
2080 VkCommandBuffer commandBuffer,
2081 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2082 VkPipelineLayout _layout,
2083 uint32_t set,
2084 const void* pData)
2085 {
2086 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2087 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2088 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2089
2090 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2091
2092 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2093 return;
2094
2095 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2096 descriptorUpdateTemplate, pData);
2097
2098 cmd_buffer->state.descriptors[set] = push_set;
2099 cmd_buffer->state.descriptors_dirty |= (1u << set);
2100 cmd_buffer->state.push_descriptors_dirty = true;
2101 }
2102
2103 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2104 VkPipelineLayout layout,
2105 VkShaderStageFlags stageFlags,
2106 uint32_t offset,
2107 uint32_t size,
2108 const void* pValues)
2109 {
2110 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2111 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2112 cmd_buffer->push_constant_stages |= stageFlags;
2113 }
2114
2115 VkResult radv_EndCommandBuffer(
2116 VkCommandBuffer commandBuffer)
2117 {
2118 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2119
2120 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER)
2121 si_emit_cache_flush(cmd_buffer);
2122
2123 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs) ||
2124 cmd_buffer->record_fail)
2125 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2126 return VK_SUCCESS;
2127 }
2128
2129 static void
2130 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2131 {
2132 struct radeon_winsys *ws = cmd_buffer->device->ws;
2133 struct radv_shader_variant *compute_shader;
2134 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2135 uint64_t va;
2136
2137 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2138 return;
2139
2140 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2141
2142 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2143 va = ws->buffer_get_va(compute_shader->bo);
2144
2145 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
2146 si_cp_dma_prefetch(cmd_buffer, va, compute_shader->code_size);
2147
2148 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2149 cmd_buffer->cs, 16);
2150
2151 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2152 radeon_emit(cmd_buffer->cs, va >> 8);
2153 radeon_emit(cmd_buffer->cs, va >> 40);
2154
2155 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2156 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2157 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2158
2159
2160 cmd_buffer->compute_scratch_size_needed =
2161 MAX2(cmd_buffer->compute_scratch_size_needed,
2162 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2163
2164 /* change these once we have scratch support */
2165 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2166 S_00B860_WAVES(pipeline->max_waves) |
2167 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2168
2169 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2170 radeon_emit(cmd_buffer->cs,
2171 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2172 radeon_emit(cmd_buffer->cs,
2173 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2174 radeon_emit(cmd_buffer->cs,
2175 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2176
2177 assert(cmd_buffer->cs->cdw <= cdw_max);
2178 }
2179
2180
2181 void radv_CmdBindPipeline(
2182 VkCommandBuffer commandBuffer,
2183 VkPipelineBindPoint pipelineBindPoint,
2184 VkPipeline _pipeline)
2185 {
2186 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2187 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2188
2189 for (unsigned i = 0; i < MAX_SETS; i++) {
2190 if (cmd_buffer->state.descriptors[i])
2191 cmd_buffer->state.descriptors_dirty |= (1u << i);
2192 }
2193
2194 switch (pipelineBindPoint) {
2195 case VK_PIPELINE_BIND_POINT_COMPUTE:
2196 cmd_buffer->state.compute_pipeline = pipeline;
2197 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2198 break;
2199 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2200 cmd_buffer->state.pipeline = pipeline;
2201 cmd_buffer->state.vertex_descriptors_dirty = true;
2202 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2203 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2204
2205 /* Apply the dynamic state from the pipeline */
2206 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
2207 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
2208 &pipeline->dynamic_state,
2209 pipeline->dynamic_state_mask);
2210
2211 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2212 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2213 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2214 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2215
2216 if (radv_pipeline_has_tess(pipeline))
2217 cmd_buffer->tess_rings_needed = true;
2218
2219 if (radv_pipeline_has_gs(pipeline)) {
2220 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2221 AC_UD_SCRATCH_RING_OFFSETS);
2222 if (cmd_buffer->ring_offsets_idx == -1)
2223 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2224 else if (loc->sgpr_idx != -1)
2225 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2226 }
2227 break;
2228 default:
2229 assert(!"invalid bind point");
2230 break;
2231 }
2232 }
2233
2234 void radv_CmdSetViewport(
2235 VkCommandBuffer commandBuffer,
2236 uint32_t firstViewport,
2237 uint32_t viewportCount,
2238 const VkViewport* pViewports)
2239 {
2240 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2241
2242 const uint32_t total_count = firstViewport + viewportCount;
2243 if (cmd_buffer->state.dynamic.viewport.count < total_count)
2244 cmd_buffer->state.dynamic.viewport.count = total_count;
2245
2246 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2247 pViewports, viewportCount * sizeof(*pViewports));
2248
2249 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2250 }
2251
2252 void radv_CmdSetScissor(
2253 VkCommandBuffer commandBuffer,
2254 uint32_t firstScissor,
2255 uint32_t scissorCount,
2256 const VkRect2D* pScissors)
2257 {
2258 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2259
2260 const uint32_t total_count = firstScissor + scissorCount;
2261 if (cmd_buffer->state.dynamic.scissor.count < total_count)
2262 cmd_buffer->state.dynamic.scissor.count = total_count;
2263
2264 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2265 pScissors, scissorCount * sizeof(*pScissors));
2266 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2267 }
2268
2269 void radv_CmdSetLineWidth(
2270 VkCommandBuffer commandBuffer,
2271 float lineWidth)
2272 {
2273 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2274 cmd_buffer->state.dynamic.line_width = lineWidth;
2275 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2276 }
2277
2278 void radv_CmdSetDepthBias(
2279 VkCommandBuffer commandBuffer,
2280 float depthBiasConstantFactor,
2281 float depthBiasClamp,
2282 float depthBiasSlopeFactor)
2283 {
2284 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2285
2286 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2287 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2288 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2289
2290 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2291 }
2292
2293 void radv_CmdSetBlendConstants(
2294 VkCommandBuffer commandBuffer,
2295 const float blendConstants[4])
2296 {
2297 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2298
2299 memcpy(cmd_buffer->state.dynamic.blend_constants,
2300 blendConstants, sizeof(float) * 4);
2301
2302 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2303 }
2304
2305 void radv_CmdSetDepthBounds(
2306 VkCommandBuffer commandBuffer,
2307 float minDepthBounds,
2308 float maxDepthBounds)
2309 {
2310 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2311
2312 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2313 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2314
2315 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2316 }
2317
2318 void radv_CmdSetStencilCompareMask(
2319 VkCommandBuffer commandBuffer,
2320 VkStencilFaceFlags faceMask,
2321 uint32_t compareMask)
2322 {
2323 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2324
2325 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2326 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2327 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2328 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2329
2330 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2331 }
2332
2333 void radv_CmdSetStencilWriteMask(
2334 VkCommandBuffer commandBuffer,
2335 VkStencilFaceFlags faceMask,
2336 uint32_t writeMask)
2337 {
2338 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2339
2340 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2341 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2342 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2343 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2344
2345 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2346 }
2347
2348 void radv_CmdSetStencilReference(
2349 VkCommandBuffer commandBuffer,
2350 VkStencilFaceFlags faceMask,
2351 uint32_t reference)
2352 {
2353 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2354
2355 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2356 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2357 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2358 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2359
2360 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2361 }
2362
2363
2364 void radv_CmdExecuteCommands(
2365 VkCommandBuffer commandBuffer,
2366 uint32_t commandBufferCount,
2367 const VkCommandBuffer* pCmdBuffers)
2368 {
2369 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2370
2371 /* Emit pending flushes on primary prior to executing secondary */
2372 si_emit_cache_flush(primary);
2373
2374 for (uint32_t i = 0; i < commandBufferCount; i++) {
2375 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2376
2377 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2378 secondary->scratch_size_needed);
2379 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2380 secondary->compute_scratch_size_needed);
2381
2382 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2383 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2384 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2385 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2386 if (secondary->tess_rings_needed)
2387 primary->tess_rings_needed = true;
2388 if (secondary->sample_positions_needed)
2389 primary->sample_positions_needed = true;
2390
2391 if (secondary->ring_offsets_idx != -1) {
2392 if (primary->ring_offsets_idx == -1)
2393 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2394 else
2395 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2396 }
2397 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2398 }
2399
2400 /* if we execute secondary we need to re-emit out pipelines */
2401 if (commandBufferCount) {
2402 primary->state.emitted_pipeline = NULL;
2403 primary->state.emitted_compute_pipeline = NULL;
2404 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2405 primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
2406 primary->state.last_primitive_reset_en = -1;
2407 primary->state.last_primitive_reset_index = 0;
2408 }
2409 }
2410
2411 VkResult radv_CreateCommandPool(
2412 VkDevice _device,
2413 const VkCommandPoolCreateInfo* pCreateInfo,
2414 const VkAllocationCallbacks* pAllocator,
2415 VkCommandPool* pCmdPool)
2416 {
2417 RADV_FROM_HANDLE(radv_device, device, _device);
2418 struct radv_cmd_pool *pool;
2419
2420 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2421 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2422 if (pool == NULL)
2423 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2424
2425 if (pAllocator)
2426 pool->alloc = *pAllocator;
2427 else
2428 pool->alloc = device->alloc;
2429
2430 list_inithead(&pool->cmd_buffers);
2431 list_inithead(&pool->free_cmd_buffers);
2432
2433 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2434
2435 *pCmdPool = radv_cmd_pool_to_handle(pool);
2436
2437 return VK_SUCCESS;
2438
2439 }
2440
2441 void radv_DestroyCommandPool(
2442 VkDevice _device,
2443 VkCommandPool commandPool,
2444 const VkAllocationCallbacks* pAllocator)
2445 {
2446 RADV_FROM_HANDLE(radv_device, device, _device);
2447 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2448
2449 if (!pool)
2450 return;
2451
2452 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2453 &pool->cmd_buffers, pool_link) {
2454 radv_cmd_buffer_destroy(cmd_buffer);
2455 }
2456
2457 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2458 &pool->free_cmd_buffers, pool_link) {
2459 radv_cmd_buffer_destroy(cmd_buffer);
2460 }
2461
2462 vk_free2(&device->alloc, pAllocator, pool);
2463 }
2464
2465 VkResult radv_ResetCommandPool(
2466 VkDevice device,
2467 VkCommandPool commandPool,
2468 VkCommandPoolResetFlags flags)
2469 {
2470 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2471
2472 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2473 &pool->cmd_buffers, pool_link) {
2474 radv_reset_cmd_buffer(cmd_buffer);
2475 }
2476
2477 return VK_SUCCESS;
2478 }
2479
2480 void radv_TrimCommandPoolKHR(
2481 VkDevice device,
2482 VkCommandPool commandPool,
2483 VkCommandPoolTrimFlagsKHR flags)
2484 {
2485 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2486
2487 if (!pool)
2488 return;
2489
2490 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2491 &pool->free_cmd_buffers, pool_link) {
2492 radv_cmd_buffer_destroy(cmd_buffer);
2493 }
2494 }
2495
2496 void radv_CmdBeginRenderPass(
2497 VkCommandBuffer commandBuffer,
2498 const VkRenderPassBeginInfo* pRenderPassBegin,
2499 VkSubpassContents contents)
2500 {
2501 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2502 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2503 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2504
2505 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2506 cmd_buffer->cs, 2048);
2507
2508 cmd_buffer->state.framebuffer = framebuffer;
2509 cmd_buffer->state.pass = pass;
2510 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2511 radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2512
2513 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2514 assert(cmd_buffer->cs->cdw <= cdw_max);
2515
2516 radv_cmd_buffer_clear_subpass(cmd_buffer);
2517 }
2518
2519 void radv_CmdNextSubpass(
2520 VkCommandBuffer commandBuffer,
2521 VkSubpassContents contents)
2522 {
2523 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2524
2525 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2526
2527 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2528 2048);
2529
2530 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2531 radv_cmd_buffer_clear_subpass(cmd_buffer);
2532 }
2533
2534 void radv_CmdDraw(
2535 VkCommandBuffer commandBuffer,
2536 uint32_t vertexCount,
2537 uint32_t instanceCount,
2538 uint32_t firstVertex,
2539 uint32_t firstInstance)
2540 {
2541 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2542
2543 radv_cmd_buffer_flush_state(cmd_buffer, false, (instanceCount > 1), false, vertexCount);
2544
2545 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2546
2547 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2548 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2549 if (loc->sgpr_idx != -1) {
2550 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
2551 radv_pipeline_has_tess(cmd_buffer->state.pipeline));
2552 int vs_num = 2;
2553 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2554 vs_num = 3;
2555
2556 assert (loc->num_sgprs == vs_num);
2557 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, vs_num);
2558 radeon_emit(cmd_buffer->cs, firstVertex);
2559 radeon_emit(cmd_buffer->cs, firstInstance);
2560 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2561 radeon_emit(cmd_buffer->cs, 0);
2562 }
2563 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2564 radeon_emit(cmd_buffer->cs, instanceCount);
2565
2566 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, 0));
2567 radeon_emit(cmd_buffer->cs, vertexCount);
2568 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2569 S_0287F0_USE_OPAQUE(0));
2570
2571 assert(cmd_buffer->cs->cdw <= cdw_max);
2572
2573 radv_cmd_buffer_trace_emit(cmd_buffer);
2574 }
2575
2576 void radv_CmdDrawIndexed(
2577 VkCommandBuffer commandBuffer,
2578 uint32_t indexCount,
2579 uint32_t instanceCount,
2580 uint32_t firstIndex,
2581 int32_t vertexOffset,
2582 uint32_t firstInstance)
2583 {
2584 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2585 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2586 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2587 uint64_t index_va;
2588
2589 radv_cmd_buffer_flush_state(cmd_buffer, true, (instanceCount > 1), false, indexCount);
2590
2591 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2592
2593 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2594 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2595
2596 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2597 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2598 if (loc->sgpr_idx != -1) {
2599 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
2600 radv_pipeline_has_tess(cmd_buffer->state.pipeline));
2601 int vs_num = 2;
2602 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2603 vs_num = 3;
2604
2605 assert (loc->num_sgprs == vs_num);
2606 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, vs_num);
2607 radeon_emit(cmd_buffer->cs, vertexOffset);
2608 radeon_emit(cmd_buffer->cs, firstInstance);
2609 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2610 radeon_emit(cmd_buffer->cs, 0);
2611 }
2612 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2613 radeon_emit(cmd_buffer->cs, instanceCount);
2614
2615 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2616 index_va += firstIndex * index_size + cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2617 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2618 radeon_emit(cmd_buffer->cs, index_max_size);
2619 radeon_emit(cmd_buffer->cs, index_va);
2620 radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
2621 radeon_emit(cmd_buffer->cs, indexCount);
2622 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2623
2624 assert(cmd_buffer->cs->cdw <= cdw_max);
2625 radv_cmd_buffer_trace_emit(cmd_buffer);
2626 }
2627
2628 static void
2629 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
2630 VkBuffer _buffer,
2631 VkDeviceSize offset,
2632 VkBuffer _count_buffer,
2633 VkDeviceSize count_offset,
2634 uint32_t draw_count,
2635 uint32_t stride,
2636 bool indexed)
2637 {
2638 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2639 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
2640 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2641 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2642 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2643 uint64_t indirect_va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2644 indirect_va += offset + buffer->offset;
2645 uint64_t count_va = 0;
2646
2647 if (count_buffer) {
2648 count_va = cmd_buffer->device->ws->buffer_get_va(count_buffer->bo);
2649 count_va += count_offset + count_buffer->offset;
2650 }
2651
2652 if (!draw_count)
2653 return;
2654
2655 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
2656
2657 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2658 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2659 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
2660 radv_pipeline_has_tess(cmd_buffer->state.pipeline));
2661 bool draw_id_enable = cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id;
2662 assert(loc->sgpr_idx != -1);
2663 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2664 radeon_emit(cs, 1);
2665 radeon_emit(cs, indirect_va);
2666 radeon_emit(cs, indirect_va >> 32);
2667
2668 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2669 PKT3_DRAW_INDIRECT_MULTI,
2670 8, false));
2671 radeon_emit(cs, 0);
2672 radeon_emit(cs, ((base_reg + loc->sgpr_idx * 4) - SI_SH_REG_OFFSET) >> 2);
2673 radeon_emit(cs, ((base_reg + (loc->sgpr_idx + 1) * 4) - SI_SH_REG_OFFSET) >> 2);
2674 radeon_emit(cs, (((base_reg + (loc->sgpr_idx + 2) * 4) - SI_SH_REG_OFFSET) >> 2) |
2675 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
2676 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2677 radeon_emit(cs, draw_count); /* count */
2678 radeon_emit(cs, count_va); /* count_addr */
2679 radeon_emit(cs, count_va >> 32);
2680 radeon_emit(cs, stride); /* stride */
2681 radeon_emit(cs, di_src_sel);
2682 radv_cmd_buffer_trace_emit(cmd_buffer);
2683 }
2684
2685 static void
2686 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
2687 VkBuffer buffer,
2688 VkDeviceSize offset,
2689 VkBuffer countBuffer,
2690 VkDeviceSize countBufferOffset,
2691 uint32_t maxDrawCount,
2692 uint32_t stride)
2693 {
2694 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2695 radv_cmd_buffer_flush_state(cmd_buffer, false, false, true, 0);
2696
2697 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2698 cmd_buffer->cs, 14);
2699
2700 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2701 countBuffer, countBufferOffset, maxDrawCount, stride, false);
2702
2703 assert(cmd_buffer->cs->cdw <= cdw_max);
2704 }
2705
2706 static void
2707 radv_cmd_draw_indexed_indirect_count(
2708 VkCommandBuffer commandBuffer,
2709 VkBuffer buffer,
2710 VkDeviceSize offset,
2711 VkBuffer countBuffer,
2712 VkDeviceSize countBufferOffset,
2713 uint32_t maxDrawCount,
2714 uint32_t stride)
2715 {
2716 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2717 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2718 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2719 uint64_t index_va;
2720 radv_cmd_buffer_flush_state(cmd_buffer, true, false, true, 0);
2721
2722 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2723 index_va += cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2724
2725 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 21);
2726
2727 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2728 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2729
2730 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2731 radeon_emit(cmd_buffer->cs, index_va);
2732 radeon_emit(cmd_buffer->cs, index_va >> 32);
2733
2734 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2735 radeon_emit(cmd_buffer->cs, index_max_size);
2736
2737 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2738 countBuffer, countBufferOffset, maxDrawCount, stride, true);
2739
2740 assert(cmd_buffer->cs->cdw <= cdw_max);
2741 }
2742
2743 void radv_CmdDrawIndirect(
2744 VkCommandBuffer commandBuffer,
2745 VkBuffer buffer,
2746 VkDeviceSize offset,
2747 uint32_t drawCount,
2748 uint32_t stride)
2749 {
2750 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2751 VK_NULL_HANDLE, 0, drawCount, stride);
2752 }
2753
2754 void radv_CmdDrawIndexedIndirect(
2755 VkCommandBuffer commandBuffer,
2756 VkBuffer buffer,
2757 VkDeviceSize offset,
2758 uint32_t drawCount,
2759 uint32_t stride)
2760 {
2761 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2762 VK_NULL_HANDLE, 0, drawCount, stride);
2763 }
2764
2765 void radv_CmdDrawIndirectCountAMD(
2766 VkCommandBuffer commandBuffer,
2767 VkBuffer buffer,
2768 VkDeviceSize offset,
2769 VkBuffer countBuffer,
2770 VkDeviceSize countBufferOffset,
2771 uint32_t maxDrawCount,
2772 uint32_t stride)
2773 {
2774 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2775 countBuffer, countBufferOffset,
2776 maxDrawCount, stride);
2777 }
2778
2779 void radv_CmdDrawIndexedIndirectCountAMD(
2780 VkCommandBuffer commandBuffer,
2781 VkBuffer buffer,
2782 VkDeviceSize offset,
2783 VkBuffer countBuffer,
2784 VkDeviceSize countBufferOffset,
2785 uint32_t maxDrawCount,
2786 uint32_t stride)
2787 {
2788 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2789 countBuffer, countBufferOffset,
2790 maxDrawCount, stride);
2791 }
2792
2793 static void
2794 radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
2795 {
2796 radv_emit_compute_pipeline(cmd_buffer);
2797 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.compute_pipeline,
2798 VK_SHADER_STAGE_COMPUTE_BIT);
2799 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
2800 VK_SHADER_STAGE_COMPUTE_BIT);
2801 si_emit_cache_flush(cmd_buffer);
2802 }
2803
2804 void radv_CmdDispatch(
2805 VkCommandBuffer commandBuffer,
2806 uint32_t x,
2807 uint32_t y,
2808 uint32_t z)
2809 {
2810 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2811
2812 radv_flush_compute_state(cmd_buffer);
2813
2814 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2815
2816 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2817 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2818 if (loc->sgpr_idx != -1) {
2819 assert(!loc->indirect);
2820 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
2821 assert(loc->num_sgprs == grid_used);
2822 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used);
2823 radeon_emit(cmd_buffer->cs, x);
2824 if (grid_used > 1)
2825 radeon_emit(cmd_buffer->cs, y);
2826 if (grid_used > 2)
2827 radeon_emit(cmd_buffer->cs, z);
2828 }
2829
2830 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2831 PKT3_SHADER_TYPE_S(1));
2832 radeon_emit(cmd_buffer->cs, x);
2833 radeon_emit(cmd_buffer->cs, y);
2834 radeon_emit(cmd_buffer->cs, z);
2835 radeon_emit(cmd_buffer->cs, 1);
2836
2837 assert(cmd_buffer->cs->cdw <= cdw_max);
2838 radv_cmd_buffer_trace_emit(cmd_buffer);
2839 }
2840
2841 void radv_CmdDispatchIndirect(
2842 VkCommandBuffer commandBuffer,
2843 VkBuffer _buffer,
2844 VkDeviceSize offset)
2845 {
2846 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2847 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2848 uint64_t va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2849 va += buffer->offset + offset;
2850
2851 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
2852
2853 radv_flush_compute_state(cmd_buffer);
2854
2855 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 25);
2856 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2857 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2858 if (loc->sgpr_idx != -1) {
2859 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
2860 for (unsigned i = 0; i < grid_used; ++i) {
2861 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
2862 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
2863 COPY_DATA_DST_SEL(COPY_DATA_REG));
2864 radeon_emit(cmd_buffer->cs, (va + 4 * i));
2865 radeon_emit(cmd_buffer->cs, (va + 4 * i) >> 32);
2866 radeon_emit(cmd_buffer->cs, ((R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4) >> 2) + i);
2867 radeon_emit(cmd_buffer->cs, 0);
2868 }
2869 }
2870
2871 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
2872 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
2873 PKT3_SHADER_TYPE_S(1));
2874 radeon_emit(cmd_buffer->cs, va);
2875 radeon_emit(cmd_buffer->cs, va >> 32);
2876 radeon_emit(cmd_buffer->cs, 1);
2877 } else {
2878 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_BASE, 2, 0) |
2879 PKT3_SHADER_TYPE_S(1));
2880 radeon_emit(cmd_buffer->cs, 1);
2881 radeon_emit(cmd_buffer->cs, va);
2882 radeon_emit(cmd_buffer->cs, va >> 32);
2883
2884 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
2885 PKT3_SHADER_TYPE_S(1));
2886 radeon_emit(cmd_buffer->cs, 0);
2887 radeon_emit(cmd_buffer->cs, 1);
2888 }
2889
2890 assert(cmd_buffer->cs->cdw <= cdw_max);
2891 radv_cmd_buffer_trace_emit(cmd_buffer);
2892 }
2893
2894 void radv_unaligned_dispatch(
2895 struct radv_cmd_buffer *cmd_buffer,
2896 uint32_t x,
2897 uint32_t y,
2898 uint32_t z)
2899 {
2900 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2901 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2902 uint32_t blocks[3], remainder[3];
2903
2904 blocks[0] = round_up_u32(x, compute_shader->info.cs.block_size[0]);
2905 blocks[1] = round_up_u32(y, compute_shader->info.cs.block_size[1]);
2906 blocks[2] = round_up_u32(z, compute_shader->info.cs.block_size[2]);
2907
2908 /* If aligned, these should be an entire block size, not 0 */
2909 remainder[0] = x + compute_shader->info.cs.block_size[0] - align_u32_npot(x, compute_shader->info.cs.block_size[0]);
2910 remainder[1] = y + compute_shader->info.cs.block_size[1] - align_u32_npot(y, compute_shader->info.cs.block_size[1]);
2911 remainder[2] = z + compute_shader->info.cs.block_size[2] - align_u32_npot(z, compute_shader->info.cs.block_size[2]);
2912
2913 radv_flush_compute_state(cmd_buffer);
2914
2915 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2916
2917 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2918 radeon_emit(cmd_buffer->cs,
2919 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]) |
2920 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
2921 radeon_emit(cmd_buffer->cs,
2922 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]) |
2923 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
2924 radeon_emit(cmd_buffer->cs,
2925 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]) |
2926 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
2927
2928 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2929 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2930 if (loc->sgpr_idx != -1) {
2931 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
2932 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used);
2933 radeon_emit(cmd_buffer->cs, blocks[0]);
2934 if (grid_used > 1)
2935 radeon_emit(cmd_buffer->cs, blocks[1]);
2936 if (grid_used > 2)
2937 radeon_emit(cmd_buffer->cs, blocks[2]);
2938 }
2939 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2940 PKT3_SHADER_TYPE_S(1));
2941 radeon_emit(cmd_buffer->cs, blocks[0]);
2942 radeon_emit(cmd_buffer->cs, blocks[1]);
2943 radeon_emit(cmd_buffer->cs, blocks[2]);
2944 radeon_emit(cmd_buffer->cs, S_00B800_COMPUTE_SHADER_EN(1) |
2945 S_00B800_PARTIAL_TG_EN(1));
2946
2947 assert(cmd_buffer->cs->cdw <= cdw_max);
2948 radv_cmd_buffer_trace_emit(cmd_buffer);
2949 }
2950
2951 void radv_CmdEndRenderPass(
2952 VkCommandBuffer commandBuffer)
2953 {
2954 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2955
2956 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
2957
2958 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2959
2960 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
2961 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
2962 radv_handle_subpass_image_transition(cmd_buffer,
2963 (VkAttachmentReference){i, layout});
2964 }
2965
2966 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2967
2968 cmd_buffer->state.pass = NULL;
2969 cmd_buffer->state.subpass = NULL;
2970 cmd_buffer->state.attachments = NULL;
2971 cmd_buffer->state.framebuffer = NULL;
2972 }
2973
2974 /*
2975 * For HTILE we have the following interesting clear words:
2976 * 0x0000030f: Uncompressed.
2977 * 0xfffffff0: Clear depth to 1.0
2978 * 0x00000000: Clear depth to 0.0
2979 */
2980 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
2981 struct radv_image *image,
2982 const VkImageSubresourceRange *range,
2983 uint32_t clear_word)
2984 {
2985 assert(range->baseMipLevel == 0);
2986 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
2987 unsigned layer_count = radv_get_layerCount(image, range);
2988 uint64_t size = image->surface.htile_slice_size * layer_count;
2989 uint64_t offset = image->offset + image->htile_offset +
2990 image->surface.htile_slice_size * range->baseArrayLayer;
2991
2992 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2993 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2994
2995 radv_fill_buffer(cmd_buffer, image->bo, offset, size, clear_word);
2996
2997 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
2998 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2999 RADV_CMD_FLAG_INV_VMEM_L1 |
3000 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3001 }
3002
3003 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3004 struct radv_image *image,
3005 VkImageLayout src_layout,
3006 VkImageLayout dst_layout,
3007 unsigned src_queue_mask,
3008 unsigned dst_queue_mask,
3009 const VkImageSubresourceRange *range,
3010 VkImageAspectFlags pending_clears)
3011 {
3012 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3013 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3014 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3015 cmd_buffer->state.render_area.extent.width == image->info.width &&
3016 cmd_buffer->state.render_area.extent.height == image->info.height) {
3017 /* The clear will initialize htile. */
3018 return;
3019 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3020 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3021 /* TODO: merge with the clear if applicable */
3022 radv_initialize_htile(cmd_buffer, image, range, 0);
3023 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3024 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3025 radv_initialize_htile(cmd_buffer, image, range, 0x0000030f);
3026 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3027 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3028 VkImageSubresourceRange local_range = *range;
3029 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3030 local_range.baseMipLevel = 0;
3031 local_range.levelCount = 1;
3032
3033 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3034 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3035
3036 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3037
3038 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3039 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3040 }
3041 }
3042
3043 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3044 struct radv_image *image, uint32_t value)
3045 {
3046 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3047 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3048
3049 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
3050 image->cmask.size, value);
3051
3052 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3053 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3054 RADV_CMD_FLAG_INV_VMEM_L1 |
3055 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3056 }
3057
3058 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3059 struct radv_image *image,
3060 VkImageLayout src_layout,
3061 VkImageLayout dst_layout,
3062 unsigned src_queue_mask,
3063 unsigned dst_queue_mask,
3064 const VkImageSubresourceRange *range,
3065 VkImageAspectFlags pending_clears)
3066 {
3067 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3068 if (image->fmask.size)
3069 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3070 else
3071 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3072 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3073 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3074 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3075 }
3076 }
3077
3078 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3079 struct radv_image *image, uint32_t value)
3080 {
3081
3082 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3083 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3084
3085 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
3086 image->surface.dcc_size, value);
3087
3088 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3089 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3090 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3091 RADV_CMD_FLAG_INV_VMEM_L1 |
3092 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3093 }
3094
3095 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3096 struct radv_image *image,
3097 VkImageLayout src_layout,
3098 VkImageLayout dst_layout,
3099 unsigned src_queue_mask,
3100 unsigned dst_queue_mask,
3101 const VkImageSubresourceRange *range,
3102 VkImageAspectFlags pending_clears)
3103 {
3104 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3105 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
3106 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3107 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3108 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3109 }
3110 }
3111
3112 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3113 struct radv_image *image,
3114 VkImageLayout src_layout,
3115 VkImageLayout dst_layout,
3116 uint32_t src_family,
3117 uint32_t dst_family,
3118 const VkImageSubresourceRange *range,
3119 VkImageAspectFlags pending_clears)
3120 {
3121 if (image->exclusive && src_family != dst_family) {
3122 /* This is an acquire or a release operation and there will be
3123 * a corresponding release/acquire. Do the transition in the
3124 * most flexible queue. */
3125
3126 assert(src_family == cmd_buffer->queue_family_index ||
3127 dst_family == cmd_buffer->queue_family_index);
3128
3129 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3130 return;
3131
3132 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3133 (src_family == RADV_QUEUE_GENERAL ||
3134 dst_family == RADV_QUEUE_GENERAL))
3135 return;
3136 }
3137
3138 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3139 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3140
3141 if (image->surface.htile_size)
3142 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3143 dst_layout, src_queue_mask,
3144 dst_queue_mask, range,
3145 pending_clears);
3146
3147 if (image->cmask.size)
3148 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3149 dst_layout, src_queue_mask,
3150 dst_queue_mask, range,
3151 pending_clears);
3152
3153 if (image->surface.dcc_size)
3154 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3155 dst_layout, src_queue_mask,
3156 dst_queue_mask, range,
3157 pending_clears);
3158 }
3159
3160 void radv_CmdPipelineBarrier(
3161 VkCommandBuffer commandBuffer,
3162 VkPipelineStageFlags srcStageMask,
3163 VkPipelineStageFlags destStageMask,
3164 VkBool32 byRegion,
3165 uint32_t memoryBarrierCount,
3166 const VkMemoryBarrier* pMemoryBarriers,
3167 uint32_t bufferMemoryBarrierCount,
3168 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3169 uint32_t imageMemoryBarrierCount,
3170 const VkImageMemoryBarrier* pImageMemoryBarriers)
3171 {
3172 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3173 enum radv_cmd_flush_bits src_flush_bits = 0;
3174 enum radv_cmd_flush_bits dst_flush_bits = 0;
3175
3176 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3177 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3178 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3179 NULL);
3180 }
3181
3182 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3183 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3184 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3185 NULL);
3186 }
3187
3188 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3189 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3190 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3191 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3192 image);
3193 }
3194
3195 radv_stage_flush(cmd_buffer, srcStageMask);
3196 cmd_buffer->state.flush_bits |= src_flush_bits;
3197
3198 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3199 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3200 radv_handle_image_transition(cmd_buffer, image,
3201 pImageMemoryBarriers[i].oldLayout,
3202 pImageMemoryBarriers[i].newLayout,
3203 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3204 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3205 &pImageMemoryBarriers[i].subresourceRange,
3206 0);
3207 }
3208
3209 cmd_buffer->state.flush_bits |= dst_flush_bits;
3210 }
3211
3212
3213 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3214 struct radv_event *event,
3215 VkPipelineStageFlags stageMask,
3216 unsigned value)
3217 {
3218 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3219 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3220
3221 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3222
3223 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 12);
3224
3225 /* TODO: this is overkill. Probably should figure something out from
3226 * the stage mask. */
3227
3228 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK) {
3229 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
3230 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
3231 EVENT_INDEX(5));
3232 radeon_emit(cs, va);
3233 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
3234 radeon_emit(cs, 2);
3235 radeon_emit(cs, 0);
3236 }
3237
3238 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
3239 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
3240 EVENT_INDEX(5));
3241 radeon_emit(cs, va);
3242 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
3243 radeon_emit(cs, value);
3244 radeon_emit(cs, 0);
3245
3246 assert(cmd_buffer->cs->cdw <= cdw_max);
3247 }
3248
3249 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3250 VkEvent _event,
3251 VkPipelineStageFlags stageMask)
3252 {
3253 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3254 RADV_FROM_HANDLE(radv_event, event, _event);
3255
3256 write_event(cmd_buffer, event, stageMask, 1);
3257 }
3258
3259 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3260 VkEvent _event,
3261 VkPipelineStageFlags stageMask)
3262 {
3263 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3264 RADV_FROM_HANDLE(radv_event, event, _event);
3265
3266 write_event(cmd_buffer, event, stageMask, 0);
3267 }
3268
3269 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3270 uint32_t eventCount,
3271 const VkEvent* pEvents,
3272 VkPipelineStageFlags srcStageMask,
3273 VkPipelineStageFlags dstStageMask,
3274 uint32_t memoryBarrierCount,
3275 const VkMemoryBarrier* pMemoryBarriers,
3276 uint32_t bufferMemoryBarrierCount,
3277 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3278 uint32_t imageMemoryBarrierCount,
3279 const VkImageMemoryBarrier* pImageMemoryBarriers)
3280 {
3281 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3282 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3283
3284 for (unsigned i = 0; i < eventCount; ++i) {
3285 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3286 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3287
3288 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3289
3290 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3291
3292 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
3293 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
3294 radeon_emit(cs, va);
3295 radeon_emit(cs, va >> 32);
3296 radeon_emit(cs, 1); /* reference value */
3297 radeon_emit(cs, 0xffffffff); /* mask */
3298 radeon_emit(cs, 4); /* poll interval */
3299
3300 assert(cmd_buffer->cs->cdw <= cdw_max);
3301 }
3302
3303
3304 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3305 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3306
3307 radv_handle_image_transition(cmd_buffer, image,
3308 pImageMemoryBarriers[i].oldLayout,
3309 pImageMemoryBarriers[i].newLayout,
3310 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3311 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3312 &pImageMemoryBarriers[i].subresourceRange,
3313 0);
3314 }
3315
3316 /* TODO: figure out how to do memory barriers without waiting */
3317 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3318 RADV_CMD_FLAG_INV_GLOBAL_L2 |
3319 RADV_CMD_FLAG_INV_VMEM_L1 |
3320 RADV_CMD_FLAG_INV_SMEM_L1;
3321 }