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radv/gfx10: allocate GDS/OA buffer objects for NGG streamout
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 bool src_render_loop,
58 VkImageLayout dst_layout,
59 bool dst_render_loop,
60 uint32_t src_family,
61 uint32_t dst_family,
62 const VkImageSubresourceRange *range,
63 struct radv_sample_locations_state *sample_locs);
64
65 const struct radv_dynamic_state default_dynamic_state = {
66 .viewport = {
67 .count = 0,
68 },
69 .scissor = {
70 .count = 0,
71 },
72 .line_width = 1.0f,
73 .depth_bias = {
74 .bias = 0.0f,
75 .clamp = 0.0f,
76 .slope = 0.0f,
77 },
78 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
79 .depth_bounds = {
80 .min = 0.0f,
81 .max = 1.0f,
82 },
83 .stencil_compare_mask = {
84 .front = ~0u,
85 .back = ~0u,
86 },
87 .stencil_write_mask = {
88 .front = ~0u,
89 .back = ~0u,
90 },
91 .stencil_reference = {
92 .front = 0u,
93 .back = 0u,
94 },
95 };
96
97 static void
98 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
99 const struct radv_dynamic_state *src)
100 {
101 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
102 uint32_t copy_mask = src->mask;
103 uint32_t dest_mask = 0;
104
105 /* Make sure to copy the number of viewports/scissors because they can
106 * only be specified at pipeline creation time.
107 */
108 dest->viewport.count = src->viewport.count;
109 dest->scissor.count = src->scissor.count;
110 dest->discard_rectangle.count = src->discard_rectangle.count;
111 dest->sample_location.count = src->sample_location.count;
112
113 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
114 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
115 src->viewport.count * sizeof(VkViewport))) {
116 typed_memcpy(dest->viewport.viewports,
117 src->viewport.viewports,
118 src->viewport.count);
119 dest_mask |= RADV_DYNAMIC_VIEWPORT;
120 }
121 }
122
123 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
124 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
125 src->scissor.count * sizeof(VkRect2D))) {
126 typed_memcpy(dest->scissor.scissors,
127 src->scissor.scissors, src->scissor.count);
128 dest_mask |= RADV_DYNAMIC_SCISSOR;
129 }
130 }
131
132 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
133 if (dest->line_width != src->line_width) {
134 dest->line_width = src->line_width;
135 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
136 }
137 }
138
139 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
140 if (memcmp(&dest->depth_bias, &src->depth_bias,
141 sizeof(src->depth_bias))) {
142 dest->depth_bias = src->depth_bias;
143 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
144 }
145 }
146
147 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
148 if (memcmp(&dest->blend_constants, &src->blend_constants,
149 sizeof(src->blend_constants))) {
150 typed_memcpy(dest->blend_constants,
151 src->blend_constants, 4);
152 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
153 }
154 }
155
156 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
157 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
158 sizeof(src->depth_bounds))) {
159 dest->depth_bounds = src->depth_bounds;
160 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
161 }
162 }
163
164 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
165 if (memcmp(&dest->stencil_compare_mask,
166 &src->stencil_compare_mask,
167 sizeof(src->stencil_compare_mask))) {
168 dest->stencil_compare_mask = src->stencil_compare_mask;
169 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
170 }
171 }
172
173 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
174 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
175 sizeof(src->stencil_write_mask))) {
176 dest->stencil_write_mask = src->stencil_write_mask;
177 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
178 }
179 }
180
181 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
182 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
183 sizeof(src->stencil_reference))) {
184 dest->stencil_reference = src->stencil_reference;
185 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
186 }
187 }
188
189 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
190 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
191 src->discard_rectangle.count * sizeof(VkRect2D))) {
192 typed_memcpy(dest->discard_rectangle.rectangles,
193 src->discard_rectangle.rectangles,
194 src->discard_rectangle.count);
195 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
196 }
197 }
198
199 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
200 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
201 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
202 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
203 memcmp(&dest->sample_location.locations,
204 &src->sample_location.locations,
205 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
206 dest->sample_location.per_pixel = src->sample_location.per_pixel;
207 dest->sample_location.grid_size = src->sample_location.grid_size;
208 typed_memcpy(dest->sample_location.locations,
209 src->sample_location.locations,
210 src->sample_location.count);
211 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
212 }
213 }
214
215 cmd_buffer->state.dirty |= dest_mask;
216 }
217
218 static void
219 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
220 struct radv_pipeline *pipeline)
221 {
222 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
223 struct radv_shader_info *info;
224
225 if (!pipeline->streamout_shader ||
226 cmd_buffer->device->physical_device->use_ngg_streamout)
227 return;
228
229 info = &pipeline->streamout_shader->info;
230 for (int i = 0; i < MAX_SO_BUFFERS; i++)
231 so->stride_in_dw[i] = info->so.strides[i];
232
233 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
234 }
235
236 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
237 {
238 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
239 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
240 }
241
242 enum ring_type radv_queue_family_to_ring(int f) {
243 switch (f) {
244 case RADV_QUEUE_GENERAL:
245 return RING_GFX;
246 case RADV_QUEUE_COMPUTE:
247 return RING_COMPUTE;
248 case RADV_QUEUE_TRANSFER:
249 return RING_DMA;
250 default:
251 unreachable("Unknown queue family");
252 }
253 }
254
255 static VkResult radv_create_cmd_buffer(
256 struct radv_device * device,
257 struct radv_cmd_pool * pool,
258 VkCommandBufferLevel level,
259 VkCommandBuffer* pCommandBuffer)
260 {
261 struct radv_cmd_buffer *cmd_buffer;
262 unsigned ring;
263 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
264 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
265 if (cmd_buffer == NULL)
266 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
267
268 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
269 cmd_buffer->device = device;
270 cmd_buffer->pool = pool;
271 cmd_buffer->level = level;
272
273 if (pool) {
274 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
275 cmd_buffer->queue_family_index = pool->queue_family_index;
276
277 } else {
278 /* Init the pool_link so we can safely call list_del when we destroy
279 * the command buffer
280 */
281 list_inithead(&cmd_buffer->pool_link);
282 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
283 }
284
285 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
286
287 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
288 if (!cmd_buffer->cs) {
289 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
290 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
291 }
292
293 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
294
295 list_inithead(&cmd_buffer->upload.list);
296
297 return VK_SUCCESS;
298 }
299
300 static void
301 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
302 {
303 list_del(&cmd_buffer->pool_link);
304
305 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
306 &cmd_buffer->upload.list, list) {
307 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
308 list_del(&up->list);
309 free(up);
310 }
311
312 if (cmd_buffer->upload.upload_bo)
313 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
314 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
315
316 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
317 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
318
319 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
320 }
321
322 static VkResult
323 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
324 {
325 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
326
327 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
328 &cmd_buffer->upload.list, list) {
329 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
330 list_del(&up->list);
331 free(up);
332 }
333
334 cmd_buffer->push_constant_stages = 0;
335 cmd_buffer->scratch_size_needed = 0;
336 cmd_buffer->compute_scratch_size_needed = 0;
337 cmd_buffer->esgs_ring_size_needed = 0;
338 cmd_buffer->gsvs_ring_size_needed = 0;
339 cmd_buffer->tess_rings_needed = false;
340 cmd_buffer->gds_needed = false;
341 cmd_buffer->sample_positions_needed = false;
342
343 if (cmd_buffer->upload.upload_bo)
344 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
345 cmd_buffer->upload.upload_bo);
346 cmd_buffer->upload.offset = 0;
347
348 cmd_buffer->record_result = VK_SUCCESS;
349
350 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
351
352 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
353 cmd_buffer->descriptors[i].dirty = 0;
354 cmd_buffer->descriptors[i].valid = 0;
355 cmd_buffer->descriptors[i].push_dirty = false;
356 }
357
358 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
359 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
360 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
361 unsigned fence_offset, eop_bug_offset;
362 void *fence_ptr;
363
364 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
365 &fence_ptr);
366
367 cmd_buffer->gfx9_fence_va =
368 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
369 cmd_buffer->gfx9_fence_va += fence_offset;
370
371 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
372 /* Allocate a buffer for the EOP bug on GFX9. */
373 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
374 &eop_bug_offset, &fence_ptr);
375 cmd_buffer->gfx9_eop_bug_va =
376 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
377 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
378 }
379 }
380
381 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
382
383 return cmd_buffer->record_result;
384 }
385
386 static bool
387 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
388 uint64_t min_needed)
389 {
390 uint64_t new_size;
391 struct radeon_winsys_bo *bo;
392 struct radv_cmd_buffer_upload *upload;
393 struct radv_device *device = cmd_buffer->device;
394
395 new_size = MAX2(min_needed, 16 * 1024);
396 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
397
398 bo = device->ws->buffer_create(device->ws,
399 new_size, 4096,
400 RADEON_DOMAIN_GTT,
401 RADEON_FLAG_CPU_ACCESS|
402 RADEON_FLAG_NO_INTERPROCESS_SHARING |
403 RADEON_FLAG_32BIT,
404 RADV_BO_PRIORITY_UPLOAD_BUFFER);
405
406 if (!bo) {
407 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
408 return false;
409 }
410
411 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
412 if (cmd_buffer->upload.upload_bo) {
413 upload = malloc(sizeof(*upload));
414
415 if (!upload) {
416 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
417 device->ws->buffer_destroy(bo);
418 return false;
419 }
420
421 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
422 list_add(&upload->list, &cmd_buffer->upload.list);
423 }
424
425 cmd_buffer->upload.upload_bo = bo;
426 cmd_buffer->upload.size = new_size;
427 cmd_buffer->upload.offset = 0;
428 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
429
430 if (!cmd_buffer->upload.map) {
431 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
432 return false;
433 }
434
435 return true;
436 }
437
438 bool
439 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
440 unsigned size,
441 unsigned alignment,
442 unsigned *out_offset,
443 void **ptr)
444 {
445 assert(util_is_power_of_two_nonzero(alignment));
446
447 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
448 if (offset + size > cmd_buffer->upload.size) {
449 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
450 return false;
451 offset = 0;
452 }
453
454 *out_offset = offset;
455 *ptr = cmd_buffer->upload.map + offset;
456
457 cmd_buffer->upload.offset = offset + size;
458 return true;
459 }
460
461 bool
462 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
463 unsigned size, unsigned alignment,
464 const void *data, unsigned *out_offset)
465 {
466 uint8_t *ptr;
467
468 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
469 out_offset, (void **)&ptr))
470 return false;
471
472 if (ptr)
473 memcpy(ptr, data, size);
474
475 return true;
476 }
477
478 static void
479 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
480 unsigned count, const uint32_t *data)
481 {
482 struct radeon_cmdbuf *cs = cmd_buffer->cs;
483
484 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
485
486 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
487 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
488 S_370_WR_CONFIRM(1) |
489 S_370_ENGINE_SEL(V_370_ME));
490 radeon_emit(cs, va);
491 radeon_emit(cs, va >> 32);
492 radeon_emit_array(cs, data, count);
493 }
494
495 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
496 {
497 struct radv_device *device = cmd_buffer->device;
498 struct radeon_cmdbuf *cs = cmd_buffer->cs;
499 uint64_t va;
500
501 va = radv_buffer_get_va(device->trace_bo);
502 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
503 va += 4;
504
505 ++cmd_buffer->state.trace_id;
506 radv_emit_write_data_packet(cmd_buffer, va, 1,
507 &cmd_buffer->state.trace_id);
508
509 radeon_check_space(cmd_buffer->device->ws, cs, 2);
510
511 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
512 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
513 }
514
515 static void
516 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
517 enum radv_cmd_flush_bits flags)
518 {
519 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
520 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
521 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
522
523 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
524
525 /* Force wait for graphics or compute engines to be idle. */
526 si_cs_emit_cache_flush(cmd_buffer->cs,
527 cmd_buffer->device->physical_device->rad_info.chip_class,
528 &cmd_buffer->gfx9_fence_idx,
529 cmd_buffer->gfx9_fence_va,
530 radv_cmd_buffer_uses_mec(cmd_buffer),
531 flags, cmd_buffer->gfx9_eop_bug_va);
532 }
533
534 if (unlikely(cmd_buffer->device->trace_bo))
535 radv_cmd_buffer_trace_emit(cmd_buffer);
536 }
537
538 static void
539 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
540 struct radv_pipeline *pipeline, enum ring_type ring)
541 {
542 struct radv_device *device = cmd_buffer->device;
543 uint32_t data[2];
544 uint64_t va;
545
546 va = radv_buffer_get_va(device->trace_bo);
547
548 switch (ring) {
549 case RING_GFX:
550 va += 8;
551 break;
552 case RING_COMPUTE:
553 va += 16;
554 break;
555 default:
556 assert(!"invalid ring type");
557 }
558
559 data[0] = (uintptr_t)pipeline;
560 data[1] = (uintptr_t)pipeline >> 32;
561
562 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
563 }
564
565 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
566 VkPipelineBindPoint bind_point,
567 struct radv_descriptor_set *set,
568 unsigned idx)
569 {
570 struct radv_descriptor_state *descriptors_state =
571 radv_get_descriptors_state(cmd_buffer, bind_point);
572
573 descriptors_state->sets[idx] = set;
574
575 descriptors_state->valid |= (1u << idx); /* active descriptors */
576 descriptors_state->dirty |= (1u << idx);
577 }
578
579 static void
580 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
581 VkPipelineBindPoint bind_point)
582 {
583 struct radv_descriptor_state *descriptors_state =
584 radv_get_descriptors_state(cmd_buffer, bind_point);
585 struct radv_device *device = cmd_buffer->device;
586 uint32_t data[MAX_SETS * 2] = {};
587 uint64_t va;
588 unsigned i;
589 va = radv_buffer_get_va(device->trace_bo) + 24;
590
591 for_each_bit(i, descriptors_state->valid) {
592 struct radv_descriptor_set *set = descriptors_state->sets[i];
593 data[i * 2] = (uint64_t)(uintptr_t)set;
594 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
595 }
596
597 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
598 }
599
600 struct radv_userdata_info *
601 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
602 gl_shader_stage stage,
603 int idx)
604 {
605 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
606 return &shader->info.user_sgprs_locs.shader_data[idx];
607 }
608
609 static void
610 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
611 struct radv_pipeline *pipeline,
612 gl_shader_stage stage,
613 int idx, uint64_t va)
614 {
615 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
616 uint32_t base_reg = pipeline->user_data_0[stage];
617 if (loc->sgpr_idx == -1)
618 return;
619
620 assert(loc->num_sgprs == 1);
621
622 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
623 base_reg + loc->sgpr_idx * 4, va, false);
624 }
625
626 static void
627 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
628 struct radv_pipeline *pipeline,
629 struct radv_descriptor_state *descriptors_state,
630 gl_shader_stage stage)
631 {
632 struct radv_device *device = cmd_buffer->device;
633 struct radeon_cmdbuf *cs = cmd_buffer->cs;
634 uint32_t sh_base = pipeline->user_data_0[stage];
635 struct radv_userdata_locations *locs =
636 &pipeline->shaders[stage]->info.user_sgprs_locs;
637 unsigned mask = locs->descriptor_sets_enabled;
638
639 mask &= descriptors_state->dirty & descriptors_state->valid;
640
641 while (mask) {
642 int start, count;
643
644 u_bit_scan_consecutive_range(&mask, &start, &count);
645
646 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
647 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
648
649 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
650 for (int i = 0; i < count; i++) {
651 struct radv_descriptor_set *set =
652 descriptors_state->sets[start + i];
653
654 radv_emit_shader_pointer_body(device, cs, set->va, true);
655 }
656 }
657 }
658
659 /**
660 * Convert the user sample locations to hardware sample locations (the values
661 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
662 */
663 static void
664 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
665 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
666 {
667 uint32_t x_offset = x % state->grid_size.width;
668 uint32_t y_offset = y % state->grid_size.height;
669 uint32_t num_samples = (uint32_t)state->per_pixel;
670 VkSampleLocationEXT *user_locs;
671 uint32_t pixel_offset;
672
673 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
674
675 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
676 user_locs = &state->locations[pixel_offset];
677
678 for (uint32_t i = 0; i < num_samples; i++) {
679 float shifted_pos_x = user_locs[i].x - 0.5;
680 float shifted_pos_y = user_locs[i].y - 0.5;
681
682 int32_t scaled_pos_x = floor(shifted_pos_x * 16);
683 int32_t scaled_pos_y = floor(shifted_pos_y * 16);
684
685 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
686 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
687 }
688 }
689
690 /**
691 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
692 * locations.
693 */
694 static void
695 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
696 uint32_t *sample_locs_pixel)
697 {
698 for (uint32_t i = 0; i < num_samples; i++) {
699 uint32_t sample_reg_idx = i / 4;
700 uint32_t sample_loc_idx = i % 4;
701 int32_t pos_x = sample_locs[i].x;
702 int32_t pos_y = sample_locs[i].y;
703
704 uint32_t shift_x = 8 * sample_loc_idx;
705 uint32_t shift_y = shift_x + 4;
706
707 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
708 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
709 }
710 }
711
712 /**
713 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
714 * sample locations.
715 */
716 static uint64_t
717 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
718 VkOffset2D *sample_locs,
719 uint32_t num_samples)
720 {
721 uint32_t centroid_priorities[num_samples];
722 uint32_t sample_mask = num_samples - 1;
723 uint32_t distances[num_samples];
724 uint64_t centroid_priority = 0;
725
726 /* Compute the distances from center for each sample. */
727 for (int i = 0; i < num_samples; i++) {
728 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
729 (sample_locs[i].y * sample_locs[i].y);
730 }
731
732 /* Compute the centroid priorities by looking at the distances array. */
733 for (int i = 0; i < num_samples; i++) {
734 uint32_t min_idx = 0;
735
736 for (int j = 1; j < num_samples; j++) {
737 if (distances[j] < distances[min_idx])
738 min_idx = j;
739 }
740
741 centroid_priorities[i] = min_idx;
742 distances[min_idx] = 0xffffffff;
743 }
744
745 /* Compute the final centroid priority. */
746 for (int i = 0; i < 8; i++) {
747 centroid_priority |=
748 centroid_priorities[i & sample_mask] << (i * 4);
749 }
750
751 return centroid_priority << 32 | centroid_priority;
752 }
753
754 /**
755 * Emit the sample locations that are specified with VK_EXT_sample_locations.
756 */
757 static void
758 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
759 {
760 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
761 struct radv_multisample_state *ms = &pipeline->graphics.ms;
762 struct radv_sample_locations_state *sample_location =
763 &cmd_buffer->state.dynamic.sample_location;
764 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
765 struct radeon_cmdbuf *cs = cmd_buffer->cs;
766 uint32_t sample_locs_pixel[4][2] = {};
767 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
768 uint32_t max_sample_dist = 0;
769 uint64_t centroid_priority;
770
771 if (!cmd_buffer->state.dynamic.sample_location.count)
772 return;
773
774 /* Convert the user sample locations to hardware sample locations. */
775 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
776 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
777 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
778 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
779
780 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
781 for (uint32_t i = 0; i < 4; i++) {
782 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
783 sample_locs_pixel[i]);
784 }
785
786 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
787 centroid_priority =
788 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
789 num_samples);
790
791 /* Compute the maximum sample distance from the specified locations. */
792 for (uint32_t i = 0; i < num_samples; i++) {
793 VkOffset2D offset = sample_locs[0][i];
794 max_sample_dist = MAX2(max_sample_dist,
795 MAX2(abs(offset.x), abs(offset.y)));
796 }
797
798 /* Emit the specified user sample locations. */
799 switch (num_samples) {
800 case 2:
801 case 4:
802 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
803 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
804 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
805 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
806 break;
807 case 8:
808 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
809 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
810 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
811 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
812 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
813 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
814 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
815 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
816 break;
817 default:
818 unreachable("invalid number of samples");
819 }
820
821 /* Emit the maximum sample distance and the centroid priority. */
822 uint32_t pa_sc_aa_config = ms->pa_sc_aa_config;
823
824 pa_sc_aa_config &= C_028BE0_MAX_SAMPLE_DIST;
825 pa_sc_aa_config |= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist);
826
827 radeon_set_context_reg_seq(cs, R_028BE0_PA_SC_AA_CONFIG, 1);
828 radeon_emit(cs, pa_sc_aa_config);
829
830 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
831 radeon_emit(cs, centroid_priority);
832 radeon_emit(cs, centroid_priority >> 32);
833
834 /* GFX9: Flush DFSM when the AA mode changes. */
835 if (cmd_buffer->device->dfsm_allowed) {
836 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
837 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
838 }
839
840 cmd_buffer->state.context_roll_without_scissor_emitted = true;
841 }
842
843 static void
844 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
845 struct radv_pipeline *pipeline,
846 gl_shader_stage stage,
847 int idx, int count, uint32_t *values)
848 {
849 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
850 uint32_t base_reg = pipeline->user_data_0[stage];
851 if (loc->sgpr_idx == -1)
852 return;
853
854 assert(loc->num_sgprs == count);
855
856 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
857 radeon_emit_array(cmd_buffer->cs, values, count);
858 }
859
860 static void
861 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
862 struct radv_pipeline *pipeline)
863 {
864 int num_samples = pipeline->graphics.ms.num_samples;
865 struct radv_multisample_state *ms = &pipeline->graphics.ms;
866 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
867
868 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.needs_sample_positions)
869 cmd_buffer->sample_positions_needed = true;
870
871 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
872 return;
873
874 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
875 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
876 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
877
878 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
879
880 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
881
882 /* GFX9: Flush DFSM when the AA mode changes. */
883 if (cmd_buffer->device->dfsm_allowed) {
884 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
885 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
886 }
887
888 cmd_buffer->state.context_roll_without_scissor_emitted = true;
889 }
890
891 static void
892 radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer,
893 struct radv_pipeline *pipeline)
894 {
895 const struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
896
897
898 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
899 return;
900
901 if (old_pipeline &&
902 old_pipeline->graphics.binning.pa_sc_binner_cntl_0 == pipeline->graphics.binning.pa_sc_binner_cntl_0 &&
903 old_pipeline->graphics.binning.db_dfsm_control == pipeline->graphics.binning.db_dfsm_control)
904 return;
905
906 bool binning_flush = false;
907 if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 ||
908 cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 ||
909 cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 ||
910 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
911 binning_flush = !old_pipeline ||
912 G_028C44_BINNING_MODE(old_pipeline->graphics.binning.pa_sc_binner_cntl_0) !=
913 G_028C44_BINNING_MODE(pipeline->graphics.binning.pa_sc_binner_cntl_0);
914 }
915
916 radeon_set_context_reg(cmd_buffer->cs, R_028C44_PA_SC_BINNER_CNTL_0,
917 pipeline->graphics.binning.pa_sc_binner_cntl_0 |
918 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush));
919
920 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
921 radeon_set_context_reg(cmd_buffer->cs, R_028038_DB_DFSM_CONTROL,
922 pipeline->graphics.binning.db_dfsm_control);
923 } else {
924 radeon_set_context_reg(cmd_buffer->cs, R_028060_DB_DFSM_CONTROL,
925 pipeline->graphics.binning.db_dfsm_control);
926 }
927
928 cmd_buffer->state.context_roll_without_scissor_emitted = true;
929 }
930
931
932 static void
933 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
934 struct radv_shader_variant *shader)
935 {
936 uint64_t va;
937
938 if (!shader)
939 return;
940
941 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
942
943 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
944 }
945
946 static void
947 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
948 struct radv_pipeline *pipeline,
949 bool vertex_stage_only)
950 {
951 struct radv_cmd_state *state = &cmd_buffer->state;
952 uint32_t mask = state->prefetch_L2_mask;
953
954 if (vertex_stage_only) {
955 /* Fast prefetch path for starting draws as soon as possible.
956 */
957 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
958 RADV_PREFETCH_VBO_DESCRIPTORS);
959 }
960
961 if (mask & RADV_PREFETCH_VS)
962 radv_emit_shader_prefetch(cmd_buffer,
963 pipeline->shaders[MESA_SHADER_VERTEX]);
964
965 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
966 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
967
968 if (mask & RADV_PREFETCH_TCS)
969 radv_emit_shader_prefetch(cmd_buffer,
970 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
971
972 if (mask & RADV_PREFETCH_TES)
973 radv_emit_shader_prefetch(cmd_buffer,
974 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
975
976 if (mask & RADV_PREFETCH_GS) {
977 radv_emit_shader_prefetch(cmd_buffer,
978 pipeline->shaders[MESA_SHADER_GEOMETRY]);
979 if (radv_pipeline_has_gs_copy_shader(pipeline))
980 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
981 }
982
983 if (mask & RADV_PREFETCH_PS)
984 radv_emit_shader_prefetch(cmd_buffer,
985 pipeline->shaders[MESA_SHADER_FRAGMENT]);
986
987 state->prefetch_L2_mask &= ~mask;
988 }
989
990 static void
991 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
992 {
993 if (!cmd_buffer->device->physical_device->rad_info.rbplus_allowed)
994 return;
995
996 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
997 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
998
999 unsigned sx_ps_downconvert = 0;
1000 unsigned sx_blend_opt_epsilon = 0;
1001 unsigned sx_blend_opt_control = 0;
1002
1003 for (unsigned i = 0; i < subpass->color_count; ++i) {
1004 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1005 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1006 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1007 continue;
1008 }
1009
1010 int idx = subpass->color_attachments[i].attachment;
1011 struct radv_color_buffer_info *cb = &cmd_buffer->state.attachments[idx].cb;
1012
1013 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
1014 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
1015 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
1016 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
1017
1018 bool has_alpha, has_rgb;
1019
1020 /* Set if RGB and A are present. */
1021 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
1022
1023 if (format == V_028C70_COLOR_8 ||
1024 format == V_028C70_COLOR_16 ||
1025 format == V_028C70_COLOR_32)
1026 has_rgb = !has_alpha;
1027 else
1028 has_rgb = true;
1029
1030 /* Check the colormask and export format. */
1031 if (!(colormask & 0x7))
1032 has_rgb = false;
1033 if (!(colormask & 0x8))
1034 has_alpha = false;
1035
1036 if (spi_format == V_028714_SPI_SHADER_ZERO) {
1037 has_rgb = false;
1038 has_alpha = false;
1039 }
1040
1041 /* Disable value checking for disabled channels. */
1042 if (!has_rgb)
1043 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1044 if (!has_alpha)
1045 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1046
1047 /* Enable down-conversion for 32bpp and smaller formats. */
1048 switch (format) {
1049 case V_028C70_COLOR_8:
1050 case V_028C70_COLOR_8_8:
1051 case V_028C70_COLOR_8_8_8_8:
1052 /* For 1 and 2-channel formats, use the superset thereof. */
1053 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1054 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1055 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1056 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1057 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1058 }
1059 break;
1060
1061 case V_028C70_COLOR_5_6_5:
1062 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1063 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1064 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1065 }
1066 break;
1067
1068 case V_028C70_COLOR_1_5_5_5:
1069 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1070 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1071 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1072 }
1073 break;
1074
1075 case V_028C70_COLOR_4_4_4_4:
1076 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1077 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1078 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1079 }
1080 break;
1081
1082 case V_028C70_COLOR_32:
1083 if (swap == V_028C70_SWAP_STD &&
1084 spi_format == V_028714_SPI_SHADER_32_R)
1085 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1086 else if (swap == V_028C70_SWAP_ALT_REV &&
1087 spi_format == V_028714_SPI_SHADER_32_AR)
1088 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1089 break;
1090
1091 case V_028C70_COLOR_16:
1092 case V_028C70_COLOR_16_16:
1093 /* For 1-channel formats, use the superset thereof. */
1094 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1095 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1096 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1097 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1098 if (swap == V_028C70_SWAP_STD ||
1099 swap == V_028C70_SWAP_STD_REV)
1100 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1101 else
1102 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1103 }
1104 break;
1105
1106 case V_028C70_COLOR_10_11_11:
1107 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1108 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1109 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1110 }
1111 break;
1112
1113 case V_028C70_COLOR_2_10_10_10:
1114 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1115 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1116 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1117 }
1118 break;
1119 }
1120 }
1121
1122 for (unsigned i = subpass->color_count; i < 8; ++i) {
1123 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1124 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1125 }
1126 /* TODO: avoid redundantly setting context registers */
1127 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1128 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1129 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1130 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1131
1132 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1133 }
1134
1135 static void
1136 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1137 {
1138 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1139
1140 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1141 return;
1142
1143 radv_update_multisample_state(cmd_buffer, pipeline);
1144 radv_update_binning_state(cmd_buffer, pipeline);
1145
1146 cmd_buffer->scratch_size_needed =
1147 MAX2(cmd_buffer->scratch_size_needed,
1148 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1149
1150 if (!cmd_buffer->state.emitted_pipeline ||
1151 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1152 pipeline->graphics.can_use_guardband)
1153 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1154
1155 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1156
1157 if (!cmd_buffer->state.emitted_pipeline ||
1158 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1159 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1160 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1161 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1162 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1163 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1164 }
1165
1166 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1167 if (!pipeline->shaders[i])
1168 continue;
1169
1170 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1171 pipeline->shaders[i]->bo);
1172 }
1173
1174 if (radv_pipeline_has_gs_copy_shader(pipeline))
1175 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1176 pipeline->gs_copy_shader->bo);
1177
1178 if (unlikely(cmd_buffer->device->trace_bo))
1179 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1180
1181 cmd_buffer->state.emitted_pipeline = pipeline;
1182
1183 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1184 }
1185
1186 static void
1187 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1188 {
1189 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1190 cmd_buffer->state.dynamic.viewport.viewports);
1191 }
1192
1193 static void
1194 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1195 {
1196 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1197
1198 si_write_scissors(cmd_buffer->cs, 0, count,
1199 cmd_buffer->state.dynamic.scissor.scissors,
1200 cmd_buffer->state.dynamic.viewport.viewports,
1201 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1202
1203 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1204 }
1205
1206 static void
1207 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1208 {
1209 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1210 return;
1211
1212 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1213 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1214 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1215 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1216 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1217 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1218 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1219 }
1220 }
1221
1222 static void
1223 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1224 {
1225 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1226
1227 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1228 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1229 }
1230
1231 static void
1232 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1233 {
1234 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1235
1236 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1237 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1238 }
1239
1240 static void
1241 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1242 {
1243 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1244
1245 radeon_set_context_reg_seq(cmd_buffer->cs,
1246 R_028430_DB_STENCILREFMASK, 2);
1247 radeon_emit(cmd_buffer->cs,
1248 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1249 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1250 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1251 S_028430_STENCILOPVAL(1));
1252 radeon_emit(cmd_buffer->cs,
1253 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1254 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1255 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1256 S_028434_STENCILOPVAL_BF(1));
1257 }
1258
1259 static void
1260 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1261 {
1262 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1263
1264 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1265 fui(d->depth_bounds.min));
1266 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1267 fui(d->depth_bounds.max));
1268 }
1269
1270 static void
1271 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1272 {
1273 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1274 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1275 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1276
1277
1278 radeon_set_context_reg_seq(cmd_buffer->cs,
1279 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1280 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1281 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1282 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1283 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1284 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1285 }
1286
1287 static void
1288 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1289 int index,
1290 struct radv_color_buffer_info *cb,
1291 struct radv_image_view *iview,
1292 VkImageLayout layout,
1293 bool in_render_loop)
1294 {
1295 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1296 uint32_t cb_color_info = cb->cb_color_info;
1297 struct radv_image *image = iview->image;
1298
1299 if (!radv_layout_dcc_compressed(cmd_buffer->device, image, layout, in_render_loop,
1300 radv_image_queue_family_mask(image,
1301 cmd_buffer->queue_family_index,
1302 cmd_buffer->queue_family_index))) {
1303 cb_color_info &= C_028C70_DCC_ENABLE;
1304 }
1305
1306 if (radv_image_is_tc_compat_cmask(image) &&
1307 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1308 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1309 /* If this bit is set, the FMASK decompression operation
1310 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1311 */
1312 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1313 }
1314
1315 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1316 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1317 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1318 radeon_emit(cmd_buffer->cs, 0);
1319 radeon_emit(cmd_buffer->cs, 0);
1320 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1321 radeon_emit(cmd_buffer->cs, cb_color_info);
1322 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1323 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1324 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1325 radeon_emit(cmd_buffer->cs, 0);
1326 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1327 radeon_emit(cmd_buffer->cs, 0);
1328
1329 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1330 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1331
1332 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1333 cb->cb_color_base >> 32);
1334 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1335 cb->cb_color_cmask >> 32);
1336 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1337 cb->cb_color_fmask >> 32);
1338 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1339 cb->cb_dcc_base >> 32);
1340 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1341 cb->cb_color_attrib2);
1342 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1343 cb->cb_color_attrib3);
1344 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1345 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1346 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1347 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1348 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1349 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1350 radeon_emit(cmd_buffer->cs, cb_color_info);
1351 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1352 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1353 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1354 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1355 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1356 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1357
1358 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1359 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1360 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1361
1362 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1363 cb->cb_mrt_epitch);
1364 } else {
1365 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1366 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1367 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1368 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1369 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1370 radeon_emit(cmd_buffer->cs, cb_color_info);
1371 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1372 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1373 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1374 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1375 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1376 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1377
1378 if (is_vi) { /* DCC BASE */
1379 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1380 }
1381 }
1382
1383 if (radv_dcc_enabled(image, iview->base_mip)) {
1384 /* Drawing with DCC enabled also compresses colorbuffers. */
1385 VkImageSubresourceRange range = {
1386 .aspectMask = iview->aspect_mask,
1387 .baseMipLevel = iview->base_mip,
1388 .levelCount = iview->level_count,
1389 .baseArrayLayer = iview->base_layer,
1390 .layerCount = iview->layer_count,
1391 };
1392
1393 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1394 }
1395 }
1396
1397 static void
1398 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1399 struct radv_ds_buffer_info *ds,
1400 const struct radv_image_view *iview,
1401 VkImageLayout layout,
1402 bool in_render_loop, bool requires_cond_exec)
1403 {
1404 const struct radv_image *image = iview->image;
1405 uint32_t db_z_info = ds->db_z_info;
1406 uint32_t db_z_info_reg;
1407
1408 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug ||
1409 !radv_image_is_tc_compat_htile(image))
1410 return;
1411
1412 if (!radv_layout_has_htile(image, layout, in_render_loop,
1413 radv_image_queue_family_mask(image,
1414 cmd_buffer->queue_family_index,
1415 cmd_buffer->queue_family_index))) {
1416 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1417 }
1418
1419 db_z_info &= C_028040_ZRANGE_PRECISION;
1420
1421 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1422 db_z_info_reg = R_028038_DB_Z_INFO;
1423 } else {
1424 db_z_info_reg = R_028040_DB_Z_INFO;
1425 }
1426
1427 /* When we don't know the last fast clear value we need to emit a
1428 * conditional packet that will eventually skip the following
1429 * SET_CONTEXT_REG packet.
1430 */
1431 if (requires_cond_exec) {
1432 uint64_t va = radv_get_tc_compat_zrange_va(image, iview->base_mip);
1433
1434 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1435 radeon_emit(cmd_buffer->cs, va);
1436 radeon_emit(cmd_buffer->cs, va >> 32);
1437 radeon_emit(cmd_buffer->cs, 0);
1438 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1439 }
1440
1441 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1442 }
1443
1444 static void
1445 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1446 struct radv_ds_buffer_info *ds,
1447 struct radv_image_view *iview,
1448 VkImageLayout layout,
1449 bool in_render_loop)
1450 {
1451 const struct radv_image *image = iview->image;
1452 uint32_t db_z_info = ds->db_z_info;
1453 uint32_t db_stencil_info = ds->db_stencil_info;
1454
1455 if (!radv_layout_has_htile(image, layout, in_render_loop,
1456 radv_image_queue_family_mask(image,
1457 cmd_buffer->queue_family_index,
1458 cmd_buffer->queue_family_index))) {
1459 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1460 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1461 }
1462
1463 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1464 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1465
1466 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1467 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1468 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1469
1470 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1471 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1472 radeon_emit(cmd_buffer->cs, db_z_info);
1473 radeon_emit(cmd_buffer->cs, db_stencil_info);
1474 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1475 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1476 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1477 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1478
1479 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 5);
1480 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1481 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1482 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1483 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1484 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1485 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1486 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1487 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1488 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1489 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1490
1491 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1492 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1493 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1494 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1495 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1496 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1497 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1498 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1499 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1500 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1501 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1502
1503 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1504 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1505 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1506 } else {
1507 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1508
1509 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1510 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1511 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1512 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1513 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1514 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1515 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1516 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1517 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1518 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1519
1520 }
1521
1522 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1523 radv_update_zrange_precision(cmd_buffer, ds, iview, layout,
1524 in_render_loop, true);
1525
1526 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1527 ds->pa_su_poly_offset_db_fmt_cntl);
1528 }
1529
1530 /**
1531 * Update the fast clear depth/stencil values if the image is bound as a
1532 * depth/stencil buffer.
1533 */
1534 static void
1535 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1536 const struct radv_image_view *iview,
1537 VkClearDepthStencilValue ds_clear_value,
1538 VkImageAspectFlags aspects)
1539 {
1540 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1541 const struct radv_image *image = iview->image;
1542 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1543 uint32_t att_idx;
1544
1545 if (!cmd_buffer->state.attachments || !subpass)
1546 return;
1547
1548 if (!subpass->depth_stencil_attachment)
1549 return;
1550
1551 att_idx = subpass->depth_stencil_attachment->attachment;
1552 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1553 return;
1554
1555 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1556 radeon_emit(cs, ds_clear_value.stencil);
1557 radeon_emit(cs, fui(ds_clear_value.depth));
1558
1559 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1560 * only needed when clearing Z to 0.0.
1561 */
1562 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1563 ds_clear_value.depth == 0.0) {
1564 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1565 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1566
1567 radv_update_zrange_precision(cmd_buffer, &cmd_buffer->state.attachments[att_idx].ds,
1568 iview, layout, in_render_loop, false);
1569 }
1570
1571 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1572 }
1573
1574 /**
1575 * Set the clear depth/stencil values to the image's metadata.
1576 */
1577 static void
1578 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1579 struct radv_image *image,
1580 const VkImageSubresourceRange *range,
1581 VkClearDepthStencilValue ds_clear_value,
1582 VkImageAspectFlags aspects)
1583 {
1584 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1585 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel);
1586 uint32_t level_count = radv_get_levelCount(image, range);
1587
1588 if (aspects & (VK_IMAGE_ASPECT_DEPTH_BIT |
1589 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1590 /* Use the fastest way when both aspects are used. */
1591 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + 2 * level_count, cmd_buffer->state.predicating));
1592 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1593 S_370_WR_CONFIRM(1) |
1594 S_370_ENGINE_SEL(V_370_PFP));
1595 radeon_emit(cs, va);
1596 radeon_emit(cs, va >> 32);
1597
1598 for (uint32_t l = 0; l < level_count; l++) {
1599 radeon_emit(cs, ds_clear_value.stencil);
1600 radeon_emit(cs, fui(ds_clear_value.depth));
1601 }
1602 } else {
1603 /* Otherwise we need one WRITE_DATA packet per level. */
1604 for (uint32_t l = 0; l < level_count; l++) {
1605 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel + l);
1606 unsigned value;
1607
1608 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
1609 value = fui(ds_clear_value.depth);
1610 va += 4;
1611 } else {
1612 value = ds_clear_value.stencil;
1613 }
1614
1615 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1616 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1617 S_370_WR_CONFIRM(1) |
1618 S_370_ENGINE_SEL(V_370_PFP));
1619 radeon_emit(cs, va);
1620 radeon_emit(cs, va >> 32);
1621 radeon_emit(cs, value);
1622 }
1623 }
1624 }
1625
1626 /**
1627 * Update the TC-compat metadata value for this image.
1628 */
1629 static void
1630 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1631 struct radv_image *image,
1632 const VkImageSubresourceRange *range,
1633 uint32_t value)
1634 {
1635 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1636
1637 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug)
1638 return;
1639
1640 uint64_t va = radv_get_tc_compat_zrange_va(image, range->baseMipLevel);
1641 uint32_t level_count = radv_get_levelCount(image, range);
1642
1643 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + level_count, cmd_buffer->state.predicating));
1644 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1645 S_370_WR_CONFIRM(1) |
1646 S_370_ENGINE_SEL(V_370_PFP));
1647 radeon_emit(cs, va);
1648 radeon_emit(cs, va >> 32);
1649
1650 for (uint32_t l = 0; l < level_count; l++)
1651 radeon_emit(cs, value);
1652 }
1653
1654 static void
1655 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1656 const struct radv_image_view *iview,
1657 VkClearDepthStencilValue ds_clear_value)
1658 {
1659 VkImageSubresourceRange range = {
1660 .aspectMask = iview->aspect_mask,
1661 .baseMipLevel = iview->base_mip,
1662 .levelCount = iview->level_count,
1663 .baseArrayLayer = iview->base_layer,
1664 .layerCount = iview->layer_count,
1665 };
1666 uint32_t cond_val;
1667
1668 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1669 * depth clear value is 0.0f.
1670 */
1671 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1672
1673 radv_set_tc_compat_zrange_metadata(cmd_buffer, iview->image, &range,
1674 cond_val);
1675 }
1676
1677 /**
1678 * Update the clear depth/stencil values for this image.
1679 */
1680 void
1681 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1682 const struct radv_image_view *iview,
1683 VkClearDepthStencilValue ds_clear_value,
1684 VkImageAspectFlags aspects)
1685 {
1686 VkImageSubresourceRange range = {
1687 .aspectMask = iview->aspect_mask,
1688 .baseMipLevel = iview->base_mip,
1689 .levelCount = iview->level_count,
1690 .baseArrayLayer = iview->base_layer,
1691 .layerCount = iview->layer_count,
1692 };
1693 struct radv_image *image = iview->image;
1694
1695 assert(radv_image_has_htile(image));
1696
1697 radv_set_ds_clear_metadata(cmd_buffer, iview->image, &range,
1698 ds_clear_value, aspects);
1699
1700 if (radv_image_is_tc_compat_htile(image) &&
1701 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1702 radv_update_tc_compat_zrange_metadata(cmd_buffer, iview,
1703 ds_clear_value);
1704 }
1705
1706 radv_update_bound_fast_clear_ds(cmd_buffer, iview, ds_clear_value,
1707 aspects);
1708 }
1709
1710 /**
1711 * Load the clear depth/stencil values from the image's metadata.
1712 */
1713 static void
1714 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1715 const struct radv_image_view *iview)
1716 {
1717 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1718 const struct radv_image *image = iview->image;
1719 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1720 uint64_t va = radv_get_ds_clear_value_va(image, iview->base_mip);
1721 unsigned reg_offset = 0, reg_count = 0;
1722
1723 if (!radv_image_has_htile(image))
1724 return;
1725
1726 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1727 ++reg_count;
1728 } else {
1729 ++reg_offset;
1730 va += 4;
1731 }
1732 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1733 ++reg_count;
1734
1735 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1736
1737 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1738 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1739 radeon_emit(cs, va);
1740 radeon_emit(cs, va >> 32);
1741 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1742 radeon_emit(cs, reg_count);
1743 } else {
1744 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1745 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1746 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1747 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1748 radeon_emit(cs, va);
1749 radeon_emit(cs, va >> 32);
1750 radeon_emit(cs, reg >> 2);
1751 radeon_emit(cs, 0);
1752
1753 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1754 radeon_emit(cs, 0);
1755 }
1756 }
1757
1758 /*
1759 * With DCC some colors don't require CMASK elimination before being
1760 * used as a texture. This sets a predicate value to determine if the
1761 * cmask eliminate is required.
1762 */
1763 void
1764 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1765 struct radv_image *image,
1766 const VkImageSubresourceRange *range, bool value)
1767 {
1768 uint64_t pred_val = value;
1769 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
1770 uint32_t level_count = radv_get_levelCount(image, range);
1771 uint32_t count = 2 * level_count;
1772
1773 assert(radv_dcc_enabled(image, range->baseMipLevel));
1774
1775 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1776 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1777 S_370_WR_CONFIRM(1) |
1778 S_370_ENGINE_SEL(V_370_PFP));
1779 radeon_emit(cmd_buffer->cs, va);
1780 radeon_emit(cmd_buffer->cs, va >> 32);
1781
1782 for (uint32_t l = 0; l < level_count; l++) {
1783 radeon_emit(cmd_buffer->cs, pred_val);
1784 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1785 }
1786 }
1787
1788 /**
1789 * Update the DCC predicate to reflect the compression state.
1790 */
1791 void
1792 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1793 struct radv_image *image,
1794 const VkImageSubresourceRange *range, bool value)
1795 {
1796 uint64_t pred_val = value;
1797 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
1798 uint32_t level_count = radv_get_levelCount(image, range);
1799 uint32_t count = 2 * level_count;
1800
1801 assert(radv_dcc_enabled(image, range->baseMipLevel));
1802
1803 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1804 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1805 S_370_WR_CONFIRM(1) |
1806 S_370_ENGINE_SEL(V_370_PFP));
1807 radeon_emit(cmd_buffer->cs, va);
1808 radeon_emit(cmd_buffer->cs, va >> 32);
1809
1810 for (uint32_t l = 0; l < level_count; l++) {
1811 radeon_emit(cmd_buffer->cs, pred_val);
1812 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1813 }
1814 }
1815
1816 /**
1817 * Update the fast clear color values if the image is bound as a color buffer.
1818 */
1819 static void
1820 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1821 struct radv_image *image,
1822 int cb_idx,
1823 uint32_t color_values[2])
1824 {
1825 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1826 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1827 uint32_t att_idx;
1828
1829 if (!cmd_buffer->state.attachments || !subpass)
1830 return;
1831
1832 att_idx = subpass->color_attachments[cb_idx].attachment;
1833 if (att_idx == VK_ATTACHMENT_UNUSED)
1834 return;
1835
1836 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1837 return;
1838
1839 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1840 radeon_emit(cs, color_values[0]);
1841 radeon_emit(cs, color_values[1]);
1842
1843 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1844 }
1845
1846 /**
1847 * Set the clear color values to the image's metadata.
1848 */
1849 static void
1850 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1851 struct radv_image *image,
1852 const VkImageSubresourceRange *range,
1853 uint32_t color_values[2])
1854 {
1855 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1856 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
1857 uint32_t level_count = radv_get_levelCount(image, range);
1858 uint32_t count = 2 * level_count;
1859
1860 assert(radv_image_has_cmask(image) ||
1861 radv_dcc_enabled(image, range->baseMipLevel));
1862
1863 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
1864 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1865 S_370_WR_CONFIRM(1) |
1866 S_370_ENGINE_SEL(V_370_PFP));
1867 radeon_emit(cs, va);
1868 radeon_emit(cs, va >> 32);
1869
1870 for (uint32_t l = 0; l < level_count; l++) {
1871 radeon_emit(cs, color_values[0]);
1872 radeon_emit(cs, color_values[1]);
1873 }
1874 }
1875
1876 /**
1877 * Update the clear color values for this image.
1878 */
1879 void
1880 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1881 const struct radv_image_view *iview,
1882 int cb_idx,
1883 uint32_t color_values[2])
1884 {
1885 struct radv_image *image = iview->image;
1886 VkImageSubresourceRange range = {
1887 .aspectMask = iview->aspect_mask,
1888 .baseMipLevel = iview->base_mip,
1889 .levelCount = iview->level_count,
1890 .baseArrayLayer = iview->base_layer,
1891 .layerCount = iview->layer_count,
1892 };
1893
1894 assert(radv_image_has_cmask(image) ||
1895 radv_dcc_enabled(image, iview->base_mip));
1896
1897 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
1898
1899 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1900 color_values);
1901 }
1902
1903 /**
1904 * Load the clear color values from the image's metadata.
1905 */
1906 static void
1907 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1908 struct radv_image_view *iview,
1909 int cb_idx)
1910 {
1911 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1912 struct radv_image *image = iview->image;
1913 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
1914
1915 if (!radv_image_has_cmask(image) &&
1916 !radv_dcc_enabled(image, iview->base_mip))
1917 return;
1918
1919 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1920
1921 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1922 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1923 radeon_emit(cs, va);
1924 radeon_emit(cs, va >> 32);
1925 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1926 radeon_emit(cs, 2);
1927 } else {
1928 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1929 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1930 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1931 COPY_DATA_COUNT_SEL);
1932 radeon_emit(cs, va);
1933 radeon_emit(cs, va >> 32);
1934 radeon_emit(cs, reg >> 2);
1935 radeon_emit(cs, 0);
1936
1937 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1938 radeon_emit(cs, 0);
1939 }
1940 }
1941
1942 static void
1943 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1944 {
1945 int i;
1946 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1947 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1948
1949 /* this may happen for inherited secondary recording */
1950 if (!framebuffer)
1951 return;
1952
1953 for (i = 0; i < 8; ++i) {
1954 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1955 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1956 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1957 continue;
1958 }
1959
1960 int idx = subpass->color_attachments[i].attachment;
1961 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
1962 VkImageLayout layout = subpass->color_attachments[i].layout;
1963 bool in_render_loop = subpass->color_attachments[i].in_render_loop;
1964
1965 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->bo);
1966
1967 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
1968 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
1969 radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout, in_render_loop);
1970
1971 radv_load_color_clear_metadata(cmd_buffer, iview, i);
1972 }
1973
1974 if (subpass->depth_stencil_attachment) {
1975 int idx = subpass->depth_stencil_attachment->attachment;
1976 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1977 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1978 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
1979 struct radv_image *image = iview->image;
1980 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->state.attachments[idx].iview->bo);
1981 ASSERTED uint32_t queue_mask = radv_image_queue_family_mask(image,
1982 cmd_buffer->queue_family_index,
1983 cmd_buffer->queue_family_index);
1984 /* We currently don't support writing decompressed HTILE */
1985 assert(radv_layout_has_htile(image, layout, in_render_loop, queue_mask) ==
1986 radv_layout_is_htile_compressed(image, layout, in_render_loop, queue_mask));
1987
1988 radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, iview, layout, in_render_loop);
1989
1990 if (cmd_buffer->state.attachments[idx].ds.offset_scale != cmd_buffer->state.offset_scale) {
1991 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1992 cmd_buffer->state.offset_scale = cmd_buffer->state.attachments[idx].ds.offset_scale;
1993 }
1994 radv_load_ds_clear_metadata(cmd_buffer, iview);
1995 } else {
1996 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
1997 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1998 else
1999 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
2000
2001 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2002 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2003 }
2004 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2005 S_028208_BR_X(framebuffer->width) |
2006 S_028208_BR_Y(framebuffer->height));
2007
2008 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
2009 bool disable_constant_encode =
2010 cmd_buffer->device->physical_device->rad_info.has_dcc_constant_encode;
2011 enum chip_class chip_class =
2012 cmd_buffer->device->physical_device->rad_info.chip_class;
2013 uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
2014
2015 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
2016 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
2017 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
2018 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
2019 }
2020
2021 if (cmd_buffer->device->pbb_allowed) {
2022 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2023 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2024 }
2025
2026 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
2027 }
2028
2029 static void
2030 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
2031 {
2032 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2033 struct radv_cmd_state *state = &cmd_buffer->state;
2034
2035 if (state->index_type != state->last_index_type) {
2036 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2037 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2038 cs, R_03090C_VGT_INDEX_TYPE,
2039 2, state->index_type);
2040 } else {
2041 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2042 radeon_emit(cs, state->index_type);
2043 }
2044
2045 state->last_index_type = state->index_type;
2046 }
2047
2048 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2049 radeon_emit(cs, state->index_va);
2050 radeon_emit(cs, state->index_va >> 32);
2051
2052 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2053 radeon_emit(cs, state->max_index_count);
2054
2055 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
2056 }
2057
2058 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
2059 {
2060 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
2061 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2062 uint32_t pa_sc_mode_cntl_1 =
2063 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
2064 uint32_t db_count_control;
2065
2066 if(!cmd_buffer->state.active_occlusion_queries) {
2067 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2068 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2069 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2070 has_perfect_queries) {
2071 /* Re-enable out-of-order rasterization if the
2072 * bound pipeline supports it and if it's has
2073 * been disabled before starting any perfect
2074 * occlusion queries.
2075 */
2076 radeon_set_context_reg(cmd_buffer->cs,
2077 R_028A4C_PA_SC_MODE_CNTL_1,
2078 pa_sc_mode_cntl_1);
2079 }
2080 }
2081 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
2082 } else {
2083 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2084 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
2085 bool gfx10_perfect = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries;
2086
2087 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2088 db_count_control =
2089 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
2090 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
2091 S_028004_SAMPLE_RATE(sample_rate) |
2092 S_028004_ZPASS_ENABLE(1) |
2093 S_028004_SLICE_EVEN_ENABLE(1) |
2094 S_028004_SLICE_ODD_ENABLE(1);
2095
2096 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2097 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2098 has_perfect_queries) {
2099 /* If the bound pipeline has enabled
2100 * out-of-order rasterization, we should
2101 * disable it before starting any perfect
2102 * occlusion queries.
2103 */
2104 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2105
2106 radeon_set_context_reg(cmd_buffer->cs,
2107 R_028A4C_PA_SC_MODE_CNTL_1,
2108 pa_sc_mode_cntl_1);
2109 }
2110 } else {
2111 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2112 S_028004_SAMPLE_RATE(sample_rate);
2113 }
2114 }
2115
2116 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2117
2118 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2119 }
2120
2121 static void
2122 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2123 {
2124 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2125
2126 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2127 radv_emit_viewport(cmd_buffer);
2128
2129 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2130 !cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
2131 radv_emit_scissor(cmd_buffer);
2132
2133 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2134 radv_emit_line_width(cmd_buffer);
2135
2136 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2137 radv_emit_blend_constants(cmd_buffer);
2138
2139 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2140 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2141 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2142 radv_emit_stencil(cmd_buffer);
2143
2144 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2145 radv_emit_depth_bounds(cmd_buffer);
2146
2147 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2148 radv_emit_depth_bias(cmd_buffer);
2149
2150 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2151 radv_emit_discard_rectangle(cmd_buffer);
2152
2153 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2154 radv_emit_sample_locations(cmd_buffer);
2155
2156 cmd_buffer->state.dirty &= ~states;
2157 }
2158
2159 static void
2160 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2161 VkPipelineBindPoint bind_point)
2162 {
2163 struct radv_descriptor_state *descriptors_state =
2164 radv_get_descriptors_state(cmd_buffer, bind_point);
2165 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2166 unsigned bo_offset;
2167
2168 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2169 set->mapped_ptr,
2170 &bo_offset))
2171 return;
2172
2173 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2174 set->va += bo_offset;
2175 }
2176
2177 static void
2178 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2179 VkPipelineBindPoint bind_point)
2180 {
2181 struct radv_descriptor_state *descriptors_state =
2182 radv_get_descriptors_state(cmd_buffer, bind_point);
2183 uint32_t size = MAX_SETS * 4;
2184 uint32_t offset;
2185 void *ptr;
2186
2187 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2188 256, &offset, &ptr))
2189 return;
2190
2191 for (unsigned i = 0; i < MAX_SETS; i++) {
2192 uint32_t *uptr = ((uint32_t *)ptr) + i;
2193 uint64_t set_va = 0;
2194 struct radv_descriptor_set *set = descriptors_state->sets[i];
2195 if (descriptors_state->valid & (1u << i))
2196 set_va = set->va;
2197 uptr[0] = set_va & 0xffffffff;
2198 }
2199
2200 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2201 va += offset;
2202
2203 if (cmd_buffer->state.pipeline) {
2204 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2205 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2206 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2207
2208 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2209 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2210 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2211
2212 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2213 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2214 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2215
2216 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2217 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2218 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2219
2220 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2221 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2222 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2223 }
2224
2225 if (cmd_buffer->state.compute_pipeline)
2226 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2227 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2228 }
2229
2230 static void
2231 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2232 VkShaderStageFlags stages)
2233 {
2234 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2235 VK_PIPELINE_BIND_POINT_COMPUTE :
2236 VK_PIPELINE_BIND_POINT_GRAPHICS;
2237 struct radv_descriptor_state *descriptors_state =
2238 radv_get_descriptors_state(cmd_buffer, bind_point);
2239 struct radv_cmd_state *state = &cmd_buffer->state;
2240 bool flush_indirect_descriptors;
2241
2242 if (!descriptors_state->dirty)
2243 return;
2244
2245 if (descriptors_state->push_dirty)
2246 radv_flush_push_descriptors(cmd_buffer, bind_point);
2247
2248 flush_indirect_descriptors =
2249 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2250 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2251 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2252 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2253
2254 if (flush_indirect_descriptors)
2255 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2256
2257 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2258 cmd_buffer->cs,
2259 MAX_SETS * MESA_SHADER_STAGES * 4);
2260
2261 if (cmd_buffer->state.pipeline) {
2262 radv_foreach_stage(stage, stages) {
2263 if (!cmd_buffer->state.pipeline->shaders[stage])
2264 continue;
2265
2266 radv_emit_descriptor_pointers(cmd_buffer,
2267 cmd_buffer->state.pipeline,
2268 descriptors_state, stage);
2269 }
2270 }
2271
2272 if (cmd_buffer->state.compute_pipeline &&
2273 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2274 radv_emit_descriptor_pointers(cmd_buffer,
2275 cmd_buffer->state.compute_pipeline,
2276 descriptors_state,
2277 MESA_SHADER_COMPUTE);
2278 }
2279
2280 descriptors_state->dirty = 0;
2281 descriptors_state->push_dirty = false;
2282
2283 assert(cmd_buffer->cs->cdw <= cdw_max);
2284
2285 if (unlikely(cmd_buffer->device->trace_bo))
2286 radv_save_descriptors(cmd_buffer, bind_point);
2287 }
2288
2289 static void
2290 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2291 VkShaderStageFlags stages)
2292 {
2293 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2294 ? cmd_buffer->state.compute_pipeline
2295 : cmd_buffer->state.pipeline;
2296 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2297 VK_PIPELINE_BIND_POINT_COMPUTE :
2298 VK_PIPELINE_BIND_POINT_GRAPHICS;
2299 struct radv_descriptor_state *descriptors_state =
2300 radv_get_descriptors_state(cmd_buffer, bind_point);
2301 struct radv_pipeline_layout *layout = pipeline->layout;
2302 struct radv_shader_variant *shader, *prev_shader;
2303 bool need_push_constants = false;
2304 unsigned offset;
2305 void *ptr;
2306 uint64_t va;
2307
2308 stages &= cmd_buffer->push_constant_stages;
2309 if (!stages ||
2310 (!layout->push_constant_size && !layout->dynamic_offset_count))
2311 return;
2312
2313 radv_foreach_stage(stage, stages) {
2314 if (!pipeline->shaders[stage])
2315 continue;
2316
2317 need_push_constants |= pipeline->shaders[stage]->info.loads_push_constants;
2318 need_push_constants |= pipeline->shaders[stage]->info.loads_dynamic_offsets;
2319
2320 uint8_t base = pipeline->shaders[stage]->info.base_inline_push_consts;
2321 uint8_t count = pipeline->shaders[stage]->info.num_inline_push_consts;
2322
2323 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2324 AC_UD_INLINE_PUSH_CONSTANTS,
2325 count,
2326 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2327 }
2328
2329 if (need_push_constants) {
2330 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2331 16 * layout->dynamic_offset_count,
2332 256, &offset, &ptr))
2333 return;
2334
2335 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2336 memcpy((char*)ptr + layout->push_constant_size,
2337 descriptors_state->dynamic_buffers,
2338 16 * layout->dynamic_offset_count);
2339
2340 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2341 va += offset;
2342
2343 ASSERTED unsigned cdw_max =
2344 radeon_check_space(cmd_buffer->device->ws,
2345 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2346
2347 prev_shader = NULL;
2348 radv_foreach_stage(stage, stages) {
2349 shader = radv_get_shader(pipeline, stage);
2350
2351 /* Avoid redundantly emitting the address for merged stages. */
2352 if (shader && shader != prev_shader) {
2353 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2354 AC_UD_PUSH_CONSTANTS, va);
2355
2356 prev_shader = shader;
2357 }
2358 }
2359 assert(cmd_buffer->cs->cdw <= cdw_max);
2360 }
2361
2362 cmd_buffer->push_constant_stages &= ~stages;
2363 }
2364
2365 static void
2366 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2367 bool pipeline_is_dirty)
2368 {
2369 if ((pipeline_is_dirty ||
2370 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2371 cmd_buffer->state.pipeline->num_vertex_bindings &&
2372 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.has_vertex_buffers) {
2373 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
2374 unsigned vb_offset;
2375 void *vb_ptr;
2376 uint32_t i = 0;
2377 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2378 uint64_t va;
2379
2380 /* allocate some descriptor state for vertex buffers */
2381 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2382 &vb_offset, &vb_ptr))
2383 return;
2384
2385 for (i = 0; i < count; i++) {
2386 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2387 uint32_t offset;
2388 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2389 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2390
2391 if (!buffer)
2392 continue;
2393
2394 va = radv_buffer_get_va(buffer->bo);
2395
2396 offset = cmd_buffer->vertex_bindings[i].offset;
2397 va += offset + buffer->offset;
2398 desc[0] = va;
2399 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2400 if (cmd_buffer->device->physical_device->rad_info.chip_class <= GFX7 && stride)
2401 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
2402 else
2403 desc[2] = buffer->size - offset;
2404 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2405 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2406 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2407 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2408
2409 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2410 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
2411 S_008F0C_OOB_SELECT(1) |
2412 S_008F0C_RESOURCE_LEVEL(1);
2413 } else {
2414 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2415 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2416 }
2417 }
2418
2419 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2420 va += vb_offset;
2421
2422 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2423 AC_UD_VS_VERTEX_BUFFERS, va);
2424
2425 cmd_buffer->state.vb_va = va;
2426 cmd_buffer->state.vb_size = count * 16;
2427 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2428 }
2429 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2430 }
2431
2432 static void
2433 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2434 {
2435 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2436 struct radv_userdata_info *loc;
2437 uint32_t base_reg;
2438
2439 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2440 if (!radv_get_shader(pipeline, stage))
2441 continue;
2442
2443 loc = radv_lookup_user_sgpr(pipeline, stage,
2444 AC_UD_STREAMOUT_BUFFERS);
2445 if (loc->sgpr_idx == -1)
2446 continue;
2447
2448 base_reg = pipeline->user_data_0[stage];
2449
2450 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2451 base_reg + loc->sgpr_idx * 4, va, false);
2452 }
2453
2454 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
2455 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2456 if (loc->sgpr_idx != -1) {
2457 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2458
2459 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2460 base_reg + loc->sgpr_idx * 4, va, false);
2461 }
2462 }
2463 }
2464
2465 static void
2466 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2467 {
2468 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2469 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2470 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2471 unsigned so_offset;
2472 void *so_ptr;
2473 uint64_t va;
2474
2475 /* Allocate some descriptor state for streamout buffers. */
2476 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2477 MAX_SO_BUFFERS * 16, 256,
2478 &so_offset, &so_ptr))
2479 return;
2480
2481 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2482 struct radv_buffer *buffer = sb[i].buffer;
2483 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2484
2485 if (!(so->enabled_mask & (1 << i)))
2486 continue;
2487
2488 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2489
2490 va += sb[i].offset;
2491
2492 /* Set the descriptor.
2493 *
2494 * On GFX8, the format must be non-INVALID, otherwise
2495 * the buffer will be considered not bound and store
2496 * instructions will be no-ops.
2497 */
2498 desc[0] = va;
2499 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2500 desc[2] = 0xffffffff;
2501 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2502 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2503 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2504 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2505
2506 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2507 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2508 S_008F0C_OOB_SELECT(3) |
2509 S_008F0C_RESOURCE_LEVEL(1);
2510 } else {
2511 desc[3] |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2512 }
2513 }
2514
2515 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2516 va += so_offset;
2517
2518 radv_emit_streamout_buffers(cmd_buffer, va);
2519 }
2520
2521 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2522 }
2523
2524 static void
2525 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2526 {
2527 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2528 radv_flush_streamout_descriptors(cmd_buffer);
2529 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2530 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2531 }
2532
2533 struct radv_draw_info {
2534 /**
2535 * Number of vertices.
2536 */
2537 uint32_t count;
2538
2539 /**
2540 * Index of the first vertex.
2541 */
2542 int32_t vertex_offset;
2543
2544 /**
2545 * First instance id.
2546 */
2547 uint32_t first_instance;
2548
2549 /**
2550 * Number of instances.
2551 */
2552 uint32_t instance_count;
2553
2554 /**
2555 * First index (indexed draws only).
2556 */
2557 uint32_t first_index;
2558
2559 /**
2560 * Whether it's an indexed draw.
2561 */
2562 bool indexed;
2563
2564 /**
2565 * Indirect draw parameters resource.
2566 */
2567 struct radv_buffer *indirect;
2568 uint64_t indirect_offset;
2569 uint32_t stride;
2570
2571 /**
2572 * Draw count parameters resource.
2573 */
2574 struct radv_buffer *count_buffer;
2575 uint64_t count_buffer_offset;
2576
2577 /**
2578 * Stream output parameters resource.
2579 */
2580 struct radv_buffer *strmout_buffer;
2581 uint64_t strmout_buffer_offset;
2582 };
2583
2584 static uint32_t
2585 radv_get_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2586 {
2587 switch (cmd_buffer->state.index_type) {
2588 case V_028A7C_VGT_INDEX_8:
2589 return 0xffu;
2590 case V_028A7C_VGT_INDEX_16:
2591 return 0xffffu;
2592 case V_028A7C_VGT_INDEX_32:
2593 return 0xffffffffu;
2594 default:
2595 unreachable("invalid index type");
2596 }
2597 }
2598
2599 static void
2600 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
2601 bool instanced_draw, bool indirect_draw,
2602 bool count_from_stream_output,
2603 uint32_t draw_vertex_count)
2604 {
2605 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2606 struct radv_cmd_state *state = &cmd_buffer->state;
2607 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2608 unsigned ia_multi_vgt_param;
2609
2610 ia_multi_vgt_param =
2611 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2612 indirect_draw,
2613 count_from_stream_output,
2614 draw_vertex_count);
2615
2616 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2617 if (info->chip_class == GFX9) {
2618 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2619 cs,
2620 R_030960_IA_MULTI_VGT_PARAM,
2621 4, ia_multi_vgt_param);
2622 } else if (info->chip_class >= GFX7) {
2623 radeon_set_context_reg_idx(cs,
2624 R_028AA8_IA_MULTI_VGT_PARAM,
2625 1, ia_multi_vgt_param);
2626 } else {
2627 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2628 ia_multi_vgt_param);
2629 }
2630 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2631 }
2632 }
2633
2634 static void
2635 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2636 const struct radv_draw_info *draw_info)
2637 {
2638 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2639 struct radv_cmd_state *state = &cmd_buffer->state;
2640 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2641 int32_t primitive_reset_en;
2642
2643 /* Draw state. */
2644 if (info->chip_class < GFX10) {
2645 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2646 draw_info->indirect,
2647 !!draw_info->strmout_buffer,
2648 draw_info->indirect ? 0 : draw_info->count);
2649 }
2650
2651 /* Primitive restart. */
2652 primitive_reset_en =
2653 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2654
2655 if (primitive_reset_en != state->last_primitive_reset_en) {
2656 state->last_primitive_reset_en = primitive_reset_en;
2657 if (info->chip_class >= GFX9) {
2658 radeon_set_uconfig_reg(cs,
2659 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2660 primitive_reset_en);
2661 } else {
2662 radeon_set_context_reg(cs,
2663 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2664 primitive_reset_en);
2665 }
2666 }
2667
2668 if (primitive_reset_en) {
2669 uint32_t primitive_reset_index =
2670 radv_get_primitive_reset_index(cmd_buffer);
2671
2672 if (primitive_reset_index != state->last_primitive_reset_index) {
2673 radeon_set_context_reg(cs,
2674 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2675 primitive_reset_index);
2676 state->last_primitive_reset_index = primitive_reset_index;
2677 }
2678 }
2679
2680 if (draw_info->strmout_buffer) {
2681 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2682
2683 va += draw_info->strmout_buffer->offset +
2684 draw_info->strmout_buffer_offset;
2685
2686 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2687 draw_info->stride);
2688
2689 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2690 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2691 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2692 COPY_DATA_WR_CONFIRM);
2693 radeon_emit(cs, va);
2694 radeon_emit(cs, va >> 32);
2695 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2696 radeon_emit(cs, 0); /* unused */
2697
2698 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2699 }
2700 }
2701
2702 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2703 VkPipelineStageFlags src_stage_mask)
2704 {
2705 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2706 VK_PIPELINE_STAGE_TRANSFER_BIT |
2707 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2708 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2709 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2710 }
2711
2712 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2713 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2714 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2715 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2716 VK_PIPELINE_STAGE_TRANSFER_BIT |
2717 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2718 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2719 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2720 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2721 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2722 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2723 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2724 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2725 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2726 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2727 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2728 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2729 }
2730 }
2731
2732 static enum radv_cmd_flush_bits
2733 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2734 VkAccessFlags src_flags,
2735 struct radv_image *image)
2736 {
2737 bool flush_CB_meta = true, flush_DB_meta = true;
2738 enum radv_cmd_flush_bits flush_bits = 0;
2739 uint32_t b;
2740
2741 if (image) {
2742 if (!radv_image_has_CB_metadata(image))
2743 flush_CB_meta = false;
2744 if (!radv_image_has_htile(image))
2745 flush_DB_meta = false;
2746 }
2747
2748 for_each_bit(b, src_flags) {
2749 switch ((VkAccessFlagBits)(1 << b)) {
2750 case VK_ACCESS_SHADER_WRITE_BIT:
2751 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2752 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2753 flush_bits |= RADV_CMD_FLAG_WB_L2;
2754 break;
2755 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2756 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2757 if (flush_CB_meta)
2758 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2759 break;
2760 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2761 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2762 if (flush_DB_meta)
2763 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2764 break;
2765 case VK_ACCESS_TRANSFER_WRITE_BIT:
2766 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2767 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2768 RADV_CMD_FLAG_INV_L2;
2769
2770 if (flush_CB_meta)
2771 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2772 if (flush_DB_meta)
2773 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2774 break;
2775 default:
2776 break;
2777 }
2778 }
2779 return flush_bits;
2780 }
2781
2782 static enum radv_cmd_flush_bits
2783 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2784 VkAccessFlags dst_flags,
2785 struct radv_image *image)
2786 {
2787 bool flush_CB_meta = true, flush_DB_meta = true;
2788 enum radv_cmd_flush_bits flush_bits = 0;
2789 bool flush_CB = true, flush_DB = true;
2790 bool image_is_coherent = false;
2791 uint32_t b;
2792
2793 if (image) {
2794 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2795 flush_CB = false;
2796 flush_DB = false;
2797 }
2798
2799 if (!radv_image_has_CB_metadata(image))
2800 flush_CB_meta = false;
2801 if (!radv_image_has_htile(image))
2802 flush_DB_meta = false;
2803
2804 /* TODO: implement shader coherent for GFX10 */
2805
2806 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
2807 if (image->info.samples == 1 &&
2808 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2809 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2810 !vk_format_is_stencil(image->vk_format)) {
2811 /* Single-sample color and single-sample depth
2812 * (not stencil) are coherent with shaders on
2813 * GFX9.
2814 */
2815 image_is_coherent = true;
2816 }
2817 }
2818 }
2819
2820 for_each_bit(b, dst_flags) {
2821 switch ((VkAccessFlagBits)(1 << b)) {
2822 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2823 case VK_ACCESS_INDEX_READ_BIT:
2824 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2825 break;
2826 case VK_ACCESS_UNIFORM_READ_BIT:
2827 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
2828 break;
2829 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2830 case VK_ACCESS_TRANSFER_READ_BIT:
2831 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2832 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
2833 RADV_CMD_FLAG_INV_L2;
2834 break;
2835 case VK_ACCESS_SHADER_READ_BIT:
2836 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
2837
2838 if (!image_is_coherent)
2839 flush_bits |= RADV_CMD_FLAG_INV_L2;
2840 break;
2841 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2842 if (flush_CB)
2843 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2844 if (flush_CB_meta)
2845 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2846 break;
2847 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2848 if (flush_DB)
2849 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2850 if (flush_DB_meta)
2851 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2852 break;
2853 default:
2854 break;
2855 }
2856 }
2857 return flush_bits;
2858 }
2859
2860 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2861 const struct radv_subpass_barrier *barrier)
2862 {
2863 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2864 NULL);
2865 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2866 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2867 NULL);
2868 }
2869
2870 uint32_t
2871 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
2872 {
2873 struct radv_cmd_state *state = &cmd_buffer->state;
2874 uint32_t subpass_id = state->subpass - state->pass->subpasses;
2875
2876 /* The id of this subpass shouldn't exceed the number of subpasses in
2877 * this render pass minus 1.
2878 */
2879 assert(subpass_id < state->pass->subpass_count);
2880 return subpass_id;
2881 }
2882
2883 static struct radv_sample_locations_state *
2884 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2885 uint32_t att_idx,
2886 bool begin_subpass)
2887 {
2888 struct radv_cmd_state *state = &cmd_buffer->state;
2889 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
2890 struct radv_image_view *view = state->attachments[att_idx].iview;
2891
2892 if (view->image->info.samples == 1)
2893 return NULL;
2894
2895 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
2896 /* Return the initial sample locations if this is the initial
2897 * layout transition of the given subpass attachemnt.
2898 */
2899 if (state->attachments[att_idx].sample_location.count > 0)
2900 return &state->attachments[att_idx].sample_location;
2901 } else {
2902 /* Otherwise return the subpass sample locations if defined. */
2903 if (state->subpass_sample_locs) {
2904 /* Because the driver sets the current subpass before
2905 * initial layout transitions, we should use the sample
2906 * locations from the previous subpass to avoid an
2907 * off-by-one problem. Otherwise, use the sample
2908 * locations for the current subpass for final layout
2909 * transitions.
2910 */
2911 if (begin_subpass)
2912 subpass_id--;
2913
2914 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
2915 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
2916 return &state->subpass_sample_locs[i].sample_location;
2917 }
2918 }
2919 }
2920
2921 return NULL;
2922 }
2923
2924 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2925 struct radv_subpass_attachment att,
2926 bool begin_subpass)
2927 {
2928 unsigned idx = att.attachment;
2929 struct radv_image_view *view = cmd_buffer->state.attachments[idx].iview;
2930 struct radv_sample_locations_state *sample_locs;
2931 VkImageSubresourceRange range;
2932 range.aspectMask = 0;
2933 range.baseMipLevel = view->base_mip;
2934 range.levelCount = 1;
2935 range.baseArrayLayer = view->base_layer;
2936 range.layerCount = cmd_buffer->state.framebuffer->layers;
2937
2938 if (cmd_buffer->state.subpass->view_mask) {
2939 /* If the current subpass uses multiview, the driver might have
2940 * performed a fast color/depth clear to the whole image
2941 * (including all layers). To make sure the driver will
2942 * decompress the image correctly (if needed), we have to
2943 * account for the "real" number of layers. If the view mask is
2944 * sparse, this will decompress more layers than needed.
2945 */
2946 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
2947 }
2948
2949 /* Get the subpass sample locations for the given attachment, if NULL
2950 * is returned the driver will use the default HW locations.
2951 */
2952 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
2953 begin_subpass);
2954
2955 radv_handle_image_transition(cmd_buffer,
2956 view->image,
2957 cmd_buffer->state.attachments[idx].current_layout,
2958 cmd_buffer->state.attachments[idx].current_in_render_loop,
2959 att.layout, att.in_render_loop,
2960 0, 0, &range, sample_locs);
2961
2962 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2963 cmd_buffer->state.attachments[idx].current_in_render_loop = att.in_render_loop;
2964
2965
2966 }
2967
2968 void
2969 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2970 const struct radv_subpass *subpass)
2971 {
2972 cmd_buffer->state.subpass = subpass;
2973
2974 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2975 }
2976
2977 static VkResult
2978 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2979 struct radv_render_pass *pass,
2980 const VkRenderPassBeginInfo *info)
2981 {
2982 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
2983 vk_find_struct_const(info->pNext,
2984 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
2985 struct radv_cmd_state *state = &cmd_buffer->state;
2986
2987 if (!sample_locs) {
2988 state->subpass_sample_locs = NULL;
2989 return VK_SUCCESS;
2990 }
2991
2992 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
2993 const VkAttachmentSampleLocationsEXT *att_sample_locs =
2994 &sample_locs->pAttachmentInitialSampleLocations[i];
2995 uint32_t att_idx = att_sample_locs->attachmentIndex;
2996 struct radv_image *image = cmd_buffer->state.attachments[att_idx].iview->image;
2997
2998 assert(vk_format_is_depth_or_stencil(image->vk_format));
2999
3000 /* From the Vulkan spec 1.1.108:
3001 *
3002 * "If the image referenced by the framebuffer attachment at
3003 * index attachmentIndex was not created with
3004 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
3005 * then the values specified in sampleLocationsInfo are
3006 * ignored."
3007 */
3008 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
3009 continue;
3010
3011 const VkSampleLocationsInfoEXT *sample_locs_info =
3012 &att_sample_locs->sampleLocationsInfo;
3013
3014 state->attachments[att_idx].sample_location.per_pixel =
3015 sample_locs_info->sampleLocationsPerPixel;
3016 state->attachments[att_idx].sample_location.grid_size =
3017 sample_locs_info->sampleLocationGridSize;
3018 state->attachments[att_idx].sample_location.count =
3019 sample_locs_info->sampleLocationsCount;
3020 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
3021 sample_locs_info->pSampleLocations,
3022 sample_locs_info->sampleLocationsCount);
3023 }
3024
3025 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
3026 sample_locs->postSubpassSampleLocationsCount *
3027 sizeof(state->subpass_sample_locs[0]),
3028 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3029 if (state->subpass_sample_locs == NULL) {
3030 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3031 return cmd_buffer->record_result;
3032 }
3033
3034 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
3035
3036 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
3037 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
3038 &sample_locs->pPostSubpassSampleLocations[i];
3039 const VkSampleLocationsInfoEXT *sample_locs_info =
3040 &subpass_sample_locs_info->sampleLocationsInfo;
3041
3042 state->subpass_sample_locs[i].subpass_idx =
3043 subpass_sample_locs_info->subpassIndex;
3044 state->subpass_sample_locs[i].sample_location.per_pixel =
3045 sample_locs_info->sampleLocationsPerPixel;
3046 state->subpass_sample_locs[i].sample_location.grid_size =
3047 sample_locs_info->sampleLocationGridSize;
3048 state->subpass_sample_locs[i].sample_location.count =
3049 sample_locs_info->sampleLocationsCount;
3050 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
3051 sample_locs_info->pSampleLocations,
3052 sample_locs_info->sampleLocationsCount);
3053 }
3054
3055 return VK_SUCCESS;
3056 }
3057
3058 static VkResult
3059 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
3060 struct radv_render_pass *pass,
3061 const VkRenderPassBeginInfo *info)
3062 {
3063 struct radv_cmd_state *state = &cmd_buffer->state;
3064 const struct VkRenderPassAttachmentBeginInfoKHR *attachment_info = NULL;
3065
3066 if (info) {
3067 attachment_info = vk_find_struct_const(info->pNext,
3068 RENDER_PASS_ATTACHMENT_BEGIN_INFO_KHR);
3069 }
3070
3071
3072 if (pass->attachment_count == 0) {
3073 state->attachments = NULL;
3074 return VK_SUCCESS;
3075 }
3076
3077 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
3078 pass->attachment_count *
3079 sizeof(state->attachments[0]),
3080 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3081 if (state->attachments == NULL) {
3082 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3083 return cmd_buffer->record_result;
3084 }
3085
3086 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
3087 struct radv_render_pass_attachment *att = &pass->attachments[i];
3088 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
3089 VkImageAspectFlags clear_aspects = 0;
3090
3091 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
3092 /* color attachment */
3093 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3094 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
3095 }
3096 } else {
3097 /* depthstencil attachment */
3098 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
3099 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3100 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
3101 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3102 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
3103 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3104 }
3105 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3106 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3107 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3108 }
3109 }
3110
3111 state->attachments[i].pending_clear_aspects = clear_aspects;
3112 state->attachments[i].cleared_views = 0;
3113 if (clear_aspects && info) {
3114 assert(info->clearValueCount > i);
3115 state->attachments[i].clear_value = info->pClearValues[i];
3116 }
3117
3118 state->attachments[i].current_layout = att->initial_layout;
3119 state->attachments[i].sample_location.count = 0;
3120
3121 struct radv_image_view *iview;
3122 if (attachment_info && attachment_info->attachmentCount > i) {
3123 iview = radv_image_view_from_handle(attachment_info->pAttachments[i]);
3124 } else {
3125 iview = state->framebuffer->attachments[i];
3126 }
3127
3128 state->attachments[i].iview = iview;
3129 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3130 radv_initialise_ds_surface(cmd_buffer->device, &state->attachments[i].ds, iview);
3131 } else {
3132 radv_initialise_color_surface(cmd_buffer->device, &state->attachments[i].cb, iview);
3133 }
3134 }
3135
3136 return VK_SUCCESS;
3137 }
3138
3139 VkResult radv_AllocateCommandBuffers(
3140 VkDevice _device,
3141 const VkCommandBufferAllocateInfo *pAllocateInfo,
3142 VkCommandBuffer *pCommandBuffers)
3143 {
3144 RADV_FROM_HANDLE(radv_device, device, _device);
3145 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
3146
3147 VkResult result = VK_SUCCESS;
3148 uint32_t i;
3149
3150 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
3151
3152 if (!list_empty(&pool->free_cmd_buffers)) {
3153 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
3154
3155 list_del(&cmd_buffer->pool_link);
3156 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
3157
3158 result = radv_reset_cmd_buffer(cmd_buffer);
3159 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
3160 cmd_buffer->level = pAllocateInfo->level;
3161
3162 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
3163 } else {
3164 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
3165 &pCommandBuffers[i]);
3166 }
3167 if (result != VK_SUCCESS)
3168 break;
3169 }
3170
3171 if (result != VK_SUCCESS) {
3172 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
3173 i, pCommandBuffers);
3174
3175 /* From the Vulkan 1.0.66 spec:
3176 *
3177 * "vkAllocateCommandBuffers can be used to create multiple
3178 * command buffers. If the creation of any of those command
3179 * buffers fails, the implementation must destroy all
3180 * successfully created command buffer objects from this
3181 * command, set all entries of the pCommandBuffers array to
3182 * NULL and return the error."
3183 */
3184 memset(pCommandBuffers, 0,
3185 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
3186 }
3187
3188 return result;
3189 }
3190
3191 void radv_FreeCommandBuffers(
3192 VkDevice device,
3193 VkCommandPool commandPool,
3194 uint32_t commandBufferCount,
3195 const VkCommandBuffer *pCommandBuffers)
3196 {
3197 for (uint32_t i = 0; i < commandBufferCount; i++) {
3198 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
3199
3200 if (cmd_buffer) {
3201 if (cmd_buffer->pool) {
3202 list_del(&cmd_buffer->pool_link);
3203 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3204 } else
3205 radv_cmd_buffer_destroy(cmd_buffer);
3206
3207 }
3208 }
3209 }
3210
3211 VkResult radv_ResetCommandBuffer(
3212 VkCommandBuffer commandBuffer,
3213 VkCommandBufferResetFlags flags)
3214 {
3215 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3216 return radv_reset_cmd_buffer(cmd_buffer);
3217 }
3218
3219 VkResult radv_BeginCommandBuffer(
3220 VkCommandBuffer commandBuffer,
3221 const VkCommandBufferBeginInfo *pBeginInfo)
3222 {
3223 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3224 VkResult result = VK_SUCCESS;
3225
3226 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3227 /* If the command buffer has already been resetted with
3228 * vkResetCommandBuffer, no need to do it again.
3229 */
3230 result = radv_reset_cmd_buffer(cmd_buffer);
3231 if (result != VK_SUCCESS)
3232 return result;
3233 }
3234
3235 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3236 cmd_buffer->state.last_primitive_reset_en = -1;
3237 cmd_buffer->state.last_index_type = -1;
3238 cmd_buffer->state.last_num_instances = -1;
3239 cmd_buffer->state.last_vertex_offset = -1;
3240 cmd_buffer->state.last_first_instance = -1;
3241 cmd_buffer->state.predication_type = -1;
3242 cmd_buffer->usage_flags = pBeginInfo->flags;
3243
3244 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3245 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3246 assert(pBeginInfo->pInheritanceInfo);
3247 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3248 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3249
3250 struct radv_subpass *subpass =
3251 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3252
3253 if (cmd_buffer->state.framebuffer) {
3254 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3255 if (result != VK_SUCCESS)
3256 return result;
3257 }
3258
3259 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3260 }
3261
3262 if (unlikely(cmd_buffer->device->trace_bo)) {
3263 struct radv_device *device = cmd_buffer->device;
3264
3265 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
3266 device->trace_bo);
3267
3268 radv_cmd_buffer_trace_emit(cmd_buffer);
3269 }
3270
3271 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3272
3273 return result;
3274 }
3275
3276 void radv_CmdBindVertexBuffers(
3277 VkCommandBuffer commandBuffer,
3278 uint32_t firstBinding,
3279 uint32_t bindingCount,
3280 const VkBuffer* pBuffers,
3281 const VkDeviceSize* pOffsets)
3282 {
3283 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3284 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3285 bool changed = false;
3286
3287 /* We have to defer setting up vertex buffer since we need the buffer
3288 * stride from the pipeline. */
3289
3290 assert(firstBinding + bindingCount <= MAX_VBS);
3291 for (uint32_t i = 0; i < bindingCount; i++) {
3292 uint32_t idx = firstBinding + i;
3293
3294 if (!changed &&
3295 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
3296 vb[idx].offset != pOffsets[i])) {
3297 changed = true;
3298 }
3299
3300 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
3301 vb[idx].offset = pOffsets[i];
3302
3303 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3304 vb[idx].buffer->bo);
3305 }
3306
3307 if (!changed) {
3308 /* No state changes. */
3309 return;
3310 }
3311
3312 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3313 }
3314
3315 static uint32_t
3316 vk_to_index_type(VkIndexType type)
3317 {
3318 switch (type) {
3319 case VK_INDEX_TYPE_UINT8_EXT:
3320 return V_028A7C_VGT_INDEX_8;
3321 case VK_INDEX_TYPE_UINT16:
3322 return V_028A7C_VGT_INDEX_16;
3323 case VK_INDEX_TYPE_UINT32:
3324 return V_028A7C_VGT_INDEX_32;
3325 default:
3326 unreachable("invalid index type");
3327 }
3328 }
3329
3330 static uint32_t
3331 radv_get_vgt_index_size(uint32_t type)
3332 {
3333 switch (type) {
3334 case V_028A7C_VGT_INDEX_8:
3335 return 1;
3336 case V_028A7C_VGT_INDEX_16:
3337 return 2;
3338 case V_028A7C_VGT_INDEX_32:
3339 return 4;
3340 default:
3341 unreachable("invalid index type");
3342 }
3343 }
3344
3345 void radv_CmdBindIndexBuffer(
3346 VkCommandBuffer commandBuffer,
3347 VkBuffer buffer,
3348 VkDeviceSize offset,
3349 VkIndexType indexType)
3350 {
3351 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3352 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3353
3354 if (cmd_buffer->state.index_buffer == index_buffer &&
3355 cmd_buffer->state.index_offset == offset &&
3356 cmd_buffer->state.index_type == indexType) {
3357 /* No state changes. */
3358 return;
3359 }
3360
3361 cmd_buffer->state.index_buffer = index_buffer;
3362 cmd_buffer->state.index_offset = offset;
3363 cmd_buffer->state.index_type = vk_to_index_type(indexType);
3364 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3365 cmd_buffer->state.index_va += index_buffer->offset + offset;
3366
3367 int index_size = radv_get_vgt_index_size(vk_to_index_type(indexType));
3368 cmd_buffer->state.max_index_count = (index_buffer->size - offset) / index_size;
3369 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3370 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3371 }
3372
3373
3374 static void
3375 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3376 VkPipelineBindPoint bind_point,
3377 struct radv_descriptor_set *set, unsigned idx)
3378 {
3379 struct radeon_winsys *ws = cmd_buffer->device->ws;
3380
3381 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3382
3383 assert(set);
3384 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3385
3386 if (!cmd_buffer->device->use_global_bo_list) {
3387 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3388 if (set->descriptors[j])
3389 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3390 }
3391
3392 if(set->bo)
3393 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3394 }
3395
3396 void radv_CmdBindDescriptorSets(
3397 VkCommandBuffer commandBuffer,
3398 VkPipelineBindPoint pipelineBindPoint,
3399 VkPipelineLayout _layout,
3400 uint32_t firstSet,
3401 uint32_t descriptorSetCount,
3402 const VkDescriptorSet* pDescriptorSets,
3403 uint32_t dynamicOffsetCount,
3404 const uint32_t* pDynamicOffsets)
3405 {
3406 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3407 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3408 unsigned dyn_idx = 0;
3409
3410 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3411 struct radv_descriptor_state *descriptors_state =
3412 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3413
3414 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3415 unsigned idx = i + firstSet;
3416 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3417
3418 /* If the set is already bound we only need to update the
3419 * (potentially changed) dynamic offsets. */
3420 if (descriptors_state->sets[idx] != set ||
3421 !(descriptors_state->valid & (1u << idx))) {
3422 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3423 }
3424
3425 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3426 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3427 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3428 assert(dyn_idx < dynamicOffsetCount);
3429
3430 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3431 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3432 dst[0] = va;
3433 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3434 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3435 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3436 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3437 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3438 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3439
3440 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
3441 dst[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3442 S_008F0C_OOB_SELECT(3) |
3443 S_008F0C_RESOURCE_LEVEL(1);
3444 } else {
3445 dst[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3446 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3447 }
3448
3449 cmd_buffer->push_constant_stages |=
3450 set->layout->dynamic_shader_stages;
3451 }
3452 }
3453 }
3454
3455 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3456 struct radv_descriptor_set *set,
3457 struct radv_descriptor_set_layout *layout,
3458 VkPipelineBindPoint bind_point)
3459 {
3460 struct radv_descriptor_state *descriptors_state =
3461 radv_get_descriptors_state(cmd_buffer, bind_point);
3462 set->size = layout->size;
3463 set->layout = layout;
3464
3465 if (descriptors_state->push_set.capacity < set->size) {
3466 size_t new_size = MAX2(set->size, 1024);
3467 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3468 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3469
3470 free(set->mapped_ptr);
3471 set->mapped_ptr = malloc(new_size);
3472
3473 if (!set->mapped_ptr) {
3474 descriptors_state->push_set.capacity = 0;
3475 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3476 return false;
3477 }
3478
3479 descriptors_state->push_set.capacity = new_size;
3480 }
3481
3482 return true;
3483 }
3484
3485 void radv_meta_push_descriptor_set(
3486 struct radv_cmd_buffer* cmd_buffer,
3487 VkPipelineBindPoint pipelineBindPoint,
3488 VkPipelineLayout _layout,
3489 uint32_t set,
3490 uint32_t descriptorWriteCount,
3491 const VkWriteDescriptorSet* pDescriptorWrites)
3492 {
3493 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3494 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3495 unsigned bo_offset;
3496
3497 assert(set == 0);
3498 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3499
3500 push_set->size = layout->set[set].layout->size;
3501 push_set->layout = layout->set[set].layout;
3502
3503 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3504 &bo_offset,
3505 (void**) &push_set->mapped_ptr))
3506 return;
3507
3508 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3509 push_set->va += bo_offset;
3510
3511 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3512 radv_descriptor_set_to_handle(push_set),
3513 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3514
3515 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3516 }
3517
3518 void radv_CmdPushDescriptorSetKHR(
3519 VkCommandBuffer commandBuffer,
3520 VkPipelineBindPoint pipelineBindPoint,
3521 VkPipelineLayout _layout,
3522 uint32_t set,
3523 uint32_t descriptorWriteCount,
3524 const VkWriteDescriptorSet* pDescriptorWrites)
3525 {
3526 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3527 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3528 struct radv_descriptor_state *descriptors_state =
3529 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3530 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3531
3532 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3533
3534 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3535 layout->set[set].layout,
3536 pipelineBindPoint))
3537 return;
3538
3539 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3540 * because it is invalid, according to Vulkan spec.
3541 */
3542 for (int i = 0; i < descriptorWriteCount; i++) {
3543 ASSERTED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
3544 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
3545 }
3546
3547 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3548 radv_descriptor_set_to_handle(push_set),
3549 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3550
3551 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3552 descriptors_state->push_dirty = true;
3553 }
3554
3555 void radv_CmdPushDescriptorSetWithTemplateKHR(
3556 VkCommandBuffer commandBuffer,
3557 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
3558 VkPipelineLayout _layout,
3559 uint32_t set,
3560 const void* pData)
3561 {
3562 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3563 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3564 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
3565 struct radv_descriptor_state *descriptors_state =
3566 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
3567 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3568
3569 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3570
3571 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3572 layout->set[set].layout,
3573 templ->bind_point))
3574 return;
3575
3576 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
3577 descriptorUpdateTemplate, pData);
3578
3579 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
3580 descriptors_state->push_dirty = true;
3581 }
3582
3583 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
3584 VkPipelineLayout layout,
3585 VkShaderStageFlags stageFlags,
3586 uint32_t offset,
3587 uint32_t size,
3588 const void* pValues)
3589 {
3590 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3591 memcpy(cmd_buffer->push_constants + offset, pValues, size);
3592 cmd_buffer->push_constant_stages |= stageFlags;
3593 }
3594
3595 VkResult radv_EndCommandBuffer(
3596 VkCommandBuffer commandBuffer)
3597 {
3598 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3599
3600 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
3601 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
3602 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
3603
3604 /* Make sure to sync all pending active queries at the end of
3605 * command buffer.
3606 */
3607 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
3608
3609 si_emit_cache_flush(cmd_buffer);
3610 }
3611
3612 /* Make sure CP DMA is idle at the end of IBs because the kernel
3613 * doesn't wait for it.
3614 */
3615 si_cp_dma_wait_for_idle(cmd_buffer);
3616
3617 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3618 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
3619
3620 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
3621 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3622
3623 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
3624
3625 return cmd_buffer->record_result;
3626 }
3627
3628 static void
3629 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
3630 {
3631 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3632
3633 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
3634 return;
3635
3636 assert(!pipeline->ctx_cs.cdw);
3637
3638 cmd_buffer->state.emitted_compute_pipeline = pipeline;
3639
3640 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
3641 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
3642
3643 cmd_buffer->compute_scratch_size_needed =
3644 MAX2(cmd_buffer->compute_scratch_size_needed,
3645 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
3646
3647 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3648 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
3649
3650 if (unlikely(cmd_buffer->device->trace_bo))
3651 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
3652 }
3653
3654 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
3655 VkPipelineBindPoint bind_point)
3656 {
3657 struct radv_descriptor_state *descriptors_state =
3658 radv_get_descriptors_state(cmd_buffer, bind_point);
3659
3660 descriptors_state->dirty |= descriptors_state->valid;
3661 }
3662
3663 void radv_CmdBindPipeline(
3664 VkCommandBuffer commandBuffer,
3665 VkPipelineBindPoint pipelineBindPoint,
3666 VkPipeline _pipeline)
3667 {
3668 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3669 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3670
3671 switch (pipelineBindPoint) {
3672 case VK_PIPELINE_BIND_POINT_COMPUTE:
3673 if (cmd_buffer->state.compute_pipeline == pipeline)
3674 return;
3675 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3676
3677 cmd_buffer->state.compute_pipeline = pipeline;
3678 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3679 break;
3680 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3681 if (cmd_buffer->state.pipeline == pipeline)
3682 return;
3683 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3684
3685 cmd_buffer->state.pipeline = pipeline;
3686 if (!pipeline)
3687 break;
3688
3689 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3690 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3691
3692 /* the new vertex shader might not have the same user regs */
3693 cmd_buffer->state.last_first_instance = -1;
3694 cmd_buffer->state.last_vertex_offset = -1;
3695
3696 /* Prefetch all pipeline shaders at first draw time. */
3697 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3698
3699 if ((cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI10 ||
3700 cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI12 ||
3701 cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI14) &&
3702 cmd_buffer->state.emitted_pipeline &&
3703 radv_pipeline_has_ngg(cmd_buffer->state.emitted_pipeline) &&
3704 !radv_pipeline_has_ngg(cmd_buffer->state.pipeline)) {
3705 /* Transitioning from NGG to legacy GS requires
3706 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
3707 * at the beginning of IBs when legacy GS ring pointers
3708 * are set.
3709 */
3710 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
3711 }
3712
3713 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3714 radv_bind_streamout_state(cmd_buffer, pipeline);
3715
3716 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3717 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3718 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3719 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3720
3721 if (radv_pipeline_has_tess(pipeline))
3722 cmd_buffer->tess_rings_needed = true;
3723 break;
3724 default:
3725 assert(!"invalid bind point");
3726 break;
3727 }
3728 }
3729
3730 void radv_CmdSetViewport(
3731 VkCommandBuffer commandBuffer,
3732 uint32_t firstViewport,
3733 uint32_t viewportCount,
3734 const VkViewport* pViewports)
3735 {
3736 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3737 struct radv_cmd_state *state = &cmd_buffer->state;
3738 ASSERTED const uint32_t total_count = firstViewport + viewportCount;
3739
3740 assert(firstViewport < MAX_VIEWPORTS);
3741 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3742
3743 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3744 pViewports, viewportCount * sizeof(*pViewports))) {
3745 return;
3746 }
3747
3748 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3749 viewportCount * sizeof(*pViewports));
3750
3751 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3752 }
3753
3754 void radv_CmdSetScissor(
3755 VkCommandBuffer commandBuffer,
3756 uint32_t firstScissor,
3757 uint32_t scissorCount,
3758 const VkRect2D* pScissors)
3759 {
3760 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3761 struct radv_cmd_state *state = &cmd_buffer->state;
3762 ASSERTED const uint32_t total_count = firstScissor + scissorCount;
3763
3764 assert(firstScissor < MAX_SCISSORS);
3765 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3766
3767 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3768 scissorCount * sizeof(*pScissors))) {
3769 return;
3770 }
3771
3772 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3773 scissorCount * sizeof(*pScissors));
3774
3775 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3776 }
3777
3778 void radv_CmdSetLineWidth(
3779 VkCommandBuffer commandBuffer,
3780 float lineWidth)
3781 {
3782 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3783
3784 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3785 return;
3786
3787 cmd_buffer->state.dynamic.line_width = lineWidth;
3788 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3789 }
3790
3791 void radv_CmdSetDepthBias(
3792 VkCommandBuffer commandBuffer,
3793 float depthBiasConstantFactor,
3794 float depthBiasClamp,
3795 float depthBiasSlopeFactor)
3796 {
3797 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3798 struct radv_cmd_state *state = &cmd_buffer->state;
3799
3800 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3801 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3802 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3803 return;
3804 }
3805
3806 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3807 state->dynamic.depth_bias.clamp = depthBiasClamp;
3808 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3809
3810 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3811 }
3812
3813 void radv_CmdSetBlendConstants(
3814 VkCommandBuffer commandBuffer,
3815 const float blendConstants[4])
3816 {
3817 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3818 struct radv_cmd_state *state = &cmd_buffer->state;
3819
3820 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3821 return;
3822
3823 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
3824
3825 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3826 }
3827
3828 void radv_CmdSetDepthBounds(
3829 VkCommandBuffer commandBuffer,
3830 float minDepthBounds,
3831 float maxDepthBounds)
3832 {
3833 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3834 struct radv_cmd_state *state = &cmd_buffer->state;
3835
3836 if (state->dynamic.depth_bounds.min == minDepthBounds &&
3837 state->dynamic.depth_bounds.max == maxDepthBounds) {
3838 return;
3839 }
3840
3841 state->dynamic.depth_bounds.min = minDepthBounds;
3842 state->dynamic.depth_bounds.max = maxDepthBounds;
3843
3844 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
3845 }
3846
3847 void radv_CmdSetStencilCompareMask(
3848 VkCommandBuffer commandBuffer,
3849 VkStencilFaceFlags faceMask,
3850 uint32_t compareMask)
3851 {
3852 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3853 struct radv_cmd_state *state = &cmd_buffer->state;
3854 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
3855 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
3856
3857 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3858 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3859 return;
3860 }
3861
3862 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3863 state->dynamic.stencil_compare_mask.front = compareMask;
3864 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3865 state->dynamic.stencil_compare_mask.back = compareMask;
3866
3867 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
3868 }
3869
3870 void radv_CmdSetStencilWriteMask(
3871 VkCommandBuffer commandBuffer,
3872 VkStencilFaceFlags faceMask,
3873 uint32_t writeMask)
3874 {
3875 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3876 struct radv_cmd_state *state = &cmd_buffer->state;
3877 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
3878 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
3879
3880 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3881 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3882 return;
3883 }
3884
3885 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3886 state->dynamic.stencil_write_mask.front = writeMask;
3887 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3888 state->dynamic.stencil_write_mask.back = writeMask;
3889
3890 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
3891 }
3892
3893 void radv_CmdSetStencilReference(
3894 VkCommandBuffer commandBuffer,
3895 VkStencilFaceFlags faceMask,
3896 uint32_t reference)
3897 {
3898 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3899 struct radv_cmd_state *state = &cmd_buffer->state;
3900 bool front_same = state->dynamic.stencil_reference.front == reference;
3901 bool back_same = state->dynamic.stencil_reference.back == reference;
3902
3903 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3904 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3905 return;
3906 }
3907
3908 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3909 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3910 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3911 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3912
3913 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3914 }
3915
3916 void radv_CmdSetDiscardRectangleEXT(
3917 VkCommandBuffer commandBuffer,
3918 uint32_t firstDiscardRectangle,
3919 uint32_t discardRectangleCount,
3920 const VkRect2D* pDiscardRectangles)
3921 {
3922 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3923 struct radv_cmd_state *state = &cmd_buffer->state;
3924 ASSERTED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3925
3926 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3927 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3928
3929 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
3930 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
3931 return;
3932 }
3933
3934 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3935 pDiscardRectangles, discardRectangleCount);
3936
3937 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3938 }
3939
3940 void radv_CmdSetSampleLocationsEXT(
3941 VkCommandBuffer commandBuffer,
3942 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
3943 {
3944 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3945 struct radv_cmd_state *state = &cmd_buffer->state;
3946
3947 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
3948
3949 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
3950 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
3951 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
3952 typed_memcpy(&state->dynamic.sample_location.locations[0],
3953 pSampleLocationsInfo->pSampleLocations,
3954 pSampleLocationsInfo->sampleLocationsCount);
3955
3956 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
3957 }
3958
3959 void radv_CmdExecuteCommands(
3960 VkCommandBuffer commandBuffer,
3961 uint32_t commandBufferCount,
3962 const VkCommandBuffer* pCmdBuffers)
3963 {
3964 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3965
3966 assert(commandBufferCount > 0);
3967
3968 /* Emit pending flushes on primary prior to executing secondary */
3969 si_emit_cache_flush(primary);
3970
3971 for (uint32_t i = 0; i < commandBufferCount; i++) {
3972 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3973
3974 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3975 secondary->scratch_size_needed);
3976 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3977 secondary->compute_scratch_size_needed);
3978
3979 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
3980 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
3981 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
3982 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
3983 if (secondary->tess_rings_needed)
3984 primary->tess_rings_needed = true;
3985 if (secondary->sample_positions_needed)
3986 primary->sample_positions_needed = true;
3987
3988 if (!secondary->state.framebuffer &&
3989 (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
3990 /* Emit the framebuffer state from primary if secondary
3991 * has been recorded without a framebuffer, otherwise
3992 * fast color/depth clears can't work.
3993 */
3994 radv_emit_framebuffer_state(primary);
3995 }
3996
3997 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
3998
3999
4000 /* When the secondary command buffer is compute only we don't
4001 * need to re-emit the current graphics pipeline.
4002 */
4003 if (secondary->state.emitted_pipeline) {
4004 primary->state.emitted_pipeline =
4005 secondary->state.emitted_pipeline;
4006 }
4007
4008 /* When the secondary command buffer is graphics only we don't
4009 * need to re-emit the current compute pipeline.
4010 */
4011 if (secondary->state.emitted_compute_pipeline) {
4012 primary->state.emitted_compute_pipeline =
4013 secondary->state.emitted_compute_pipeline;
4014 }
4015
4016 /* Only re-emit the draw packets when needed. */
4017 if (secondary->state.last_primitive_reset_en != -1) {
4018 primary->state.last_primitive_reset_en =
4019 secondary->state.last_primitive_reset_en;
4020 }
4021
4022 if (secondary->state.last_primitive_reset_index) {
4023 primary->state.last_primitive_reset_index =
4024 secondary->state.last_primitive_reset_index;
4025 }
4026
4027 if (secondary->state.last_ia_multi_vgt_param) {
4028 primary->state.last_ia_multi_vgt_param =
4029 secondary->state.last_ia_multi_vgt_param;
4030 }
4031
4032 primary->state.last_first_instance = secondary->state.last_first_instance;
4033 primary->state.last_num_instances = secondary->state.last_num_instances;
4034 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
4035
4036 if (secondary->state.last_index_type != -1) {
4037 primary->state.last_index_type =
4038 secondary->state.last_index_type;
4039 }
4040 }
4041
4042 /* After executing commands from secondary buffers we have to dirty
4043 * some states.
4044 */
4045 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
4046 RADV_CMD_DIRTY_INDEX_BUFFER |
4047 RADV_CMD_DIRTY_DYNAMIC_ALL;
4048 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
4049 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
4050 }
4051
4052 VkResult radv_CreateCommandPool(
4053 VkDevice _device,
4054 const VkCommandPoolCreateInfo* pCreateInfo,
4055 const VkAllocationCallbacks* pAllocator,
4056 VkCommandPool* pCmdPool)
4057 {
4058 RADV_FROM_HANDLE(radv_device, device, _device);
4059 struct radv_cmd_pool *pool;
4060
4061 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
4062 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4063 if (pool == NULL)
4064 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4065
4066 if (pAllocator)
4067 pool->alloc = *pAllocator;
4068 else
4069 pool->alloc = device->alloc;
4070
4071 list_inithead(&pool->cmd_buffers);
4072 list_inithead(&pool->free_cmd_buffers);
4073
4074 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
4075
4076 *pCmdPool = radv_cmd_pool_to_handle(pool);
4077
4078 return VK_SUCCESS;
4079
4080 }
4081
4082 void radv_DestroyCommandPool(
4083 VkDevice _device,
4084 VkCommandPool commandPool,
4085 const VkAllocationCallbacks* pAllocator)
4086 {
4087 RADV_FROM_HANDLE(radv_device, device, _device);
4088 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4089
4090 if (!pool)
4091 return;
4092
4093 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4094 &pool->cmd_buffers, pool_link) {
4095 radv_cmd_buffer_destroy(cmd_buffer);
4096 }
4097
4098 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4099 &pool->free_cmd_buffers, pool_link) {
4100 radv_cmd_buffer_destroy(cmd_buffer);
4101 }
4102
4103 vk_free2(&device->alloc, pAllocator, pool);
4104 }
4105
4106 VkResult radv_ResetCommandPool(
4107 VkDevice device,
4108 VkCommandPool commandPool,
4109 VkCommandPoolResetFlags flags)
4110 {
4111 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4112 VkResult result;
4113
4114 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
4115 &pool->cmd_buffers, pool_link) {
4116 result = radv_reset_cmd_buffer(cmd_buffer);
4117 if (result != VK_SUCCESS)
4118 return result;
4119 }
4120
4121 return VK_SUCCESS;
4122 }
4123
4124 void radv_TrimCommandPool(
4125 VkDevice device,
4126 VkCommandPool commandPool,
4127 VkCommandPoolTrimFlags flags)
4128 {
4129 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4130
4131 if (!pool)
4132 return;
4133
4134 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4135 &pool->free_cmd_buffers, pool_link) {
4136 radv_cmd_buffer_destroy(cmd_buffer);
4137 }
4138 }
4139
4140 static void
4141 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
4142 uint32_t subpass_id)
4143 {
4144 struct radv_cmd_state *state = &cmd_buffer->state;
4145 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
4146
4147 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
4148 cmd_buffer->cs, 4096);
4149
4150 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
4151
4152 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
4153
4154 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4155 const uint32_t a = subpass->attachments[i].attachment;
4156 if (a == VK_ATTACHMENT_UNUSED)
4157 continue;
4158
4159 radv_handle_subpass_image_transition(cmd_buffer,
4160 subpass->attachments[i],
4161 true);
4162 }
4163
4164 radv_cmd_buffer_clear_subpass(cmd_buffer);
4165
4166 assert(cmd_buffer->cs->cdw <= cdw_max);
4167 }
4168
4169 static void
4170 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
4171 {
4172 struct radv_cmd_state *state = &cmd_buffer->state;
4173 const struct radv_subpass *subpass = state->subpass;
4174 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
4175
4176 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4177
4178 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4179 const uint32_t a = subpass->attachments[i].attachment;
4180 if (a == VK_ATTACHMENT_UNUSED)
4181 continue;
4182
4183 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
4184 continue;
4185
4186 VkImageLayout layout = state->pass->attachments[a].final_layout;
4187 struct radv_subpass_attachment att = { a, layout };
4188 radv_handle_subpass_image_transition(cmd_buffer, att, false);
4189 }
4190 }
4191
4192 void radv_CmdBeginRenderPass(
4193 VkCommandBuffer commandBuffer,
4194 const VkRenderPassBeginInfo* pRenderPassBegin,
4195 VkSubpassContents contents)
4196 {
4197 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4198 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
4199 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
4200 VkResult result;
4201
4202 cmd_buffer->state.framebuffer = framebuffer;
4203 cmd_buffer->state.pass = pass;
4204 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
4205
4206 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
4207 if (result != VK_SUCCESS)
4208 return;
4209
4210 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
4211 if (result != VK_SUCCESS)
4212 return;
4213
4214 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
4215 }
4216
4217 void radv_CmdBeginRenderPass2KHR(
4218 VkCommandBuffer commandBuffer,
4219 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
4220 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
4221 {
4222 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
4223 pSubpassBeginInfo->contents);
4224 }
4225
4226 void radv_CmdNextSubpass(
4227 VkCommandBuffer commandBuffer,
4228 VkSubpassContents contents)
4229 {
4230 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4231
4232 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
4233 radv_cmd_buffer_end_subpass(cmd_buffer);
4234 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
4235 }
4236
4237 void radv_CmdNextSubpass2KHR(
4238 VkCommandBuffer commandBuffer,
4239 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
4240 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4241 {
4242 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
4243 }
4244
4245 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
4246 {
4247 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
4248 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
4249 if (!radv_get_shader(pipeline, stage))
4250 continue;
4251
4252 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
4253 if (loc->sgpr_idx == -1)
4254 continue;
4255 uint32_t base_reg = pipeline->user_data_0[stage];
4256 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4257
4258 }
4259 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
4260 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
4261 if (loc->sgpr_idx != -1) {
4262 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
4263 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4264 }
4265 }
4266 }
4267
4268 static void
4269 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4270 uint32_t vertex_count,
4271 bool use_opaque)
4272 {
4273 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
4274 radeon_emit(cmd_buffer->cs, vertex_count);
4275 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
4276 S_0287F0_USE_OPAQUE(use_opaque));
4277 }
4278
4279 static void
4280 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
4281 uint64_t index_va,
4282 uint32_t index_count)
4283 {
4284 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
4285 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
4286 radeon_emit(cmd_buffer->cs, index_va);
4287 radeon_emit(cmd_buffer->cs, index_va >> 32);
4288 radeon_emit(cmd_buffer->cs, index_count);
4289 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
4290 }
4291
4292 static void
4293 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4294 bool indexed,
4295 uint32_t draw_count,
4296 uint64_t count_va,
4297 uint32_t stride)
4298 {
4299 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4300 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
4301 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
4302 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id;
4303 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
4304 bool predicating = cmd_buffer->state.predicating;
4305 assert(base_reg);
4306
4307 /* just reset draw state for vertex data */
4308 cmd_buffer->state.last_first_instance = -1;
4309 cmd_buffer->state.last_num_instances = -1;
4310 cmd_buffer->state.last_vertex_offset = -1;
4311
4312 if (draw_count == 1 && !count_va && !draw_id_enable) {
4313 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
4314 PKT3_DRAW_INDIRECT, 3, predicating));
4315 radeon_emit(cs, 0);
4316 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4317 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4318 radeon_emit(cs, di_src_sel);
4319 } else {
4320 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
4321 PKT3_DRAW_INDIRECT_MULTI,
4322 8, predicating));
4323 radeon_emit(cs, 0);
4324 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4325 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4326 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
4327 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
4328 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
4329 radeon_emit(cs, draw_count); /* count */
4330 radeon_emit(cs, count_va); /* count_addr */
4331 radeon_emit(cs, count_va >> 32);
4332 radeon_emit(cs, stride); /* stride */
4333 radeon_emit(cs, di_src_sel);
4334 }
4335 }
4336
4337 static void
4338 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
4339 const struct radv_draw_info *info)
4340 {
4341 struct radv_cmd_state *state = &cmd_buffer->state;
4342 struct radeon_winsys *ws = cmd_buffer->device->ws;
4343 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4344
4345 if (info->indirect) {
4346 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4347 uint64_t count_va = 0;
4348
4349 va += info->indirect->offset + info->indirect_offset;
4350
4351 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4352
4353 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
4354 radeon_emit(cs, 1);
4355 radeon_emit(cs, va);
4356 radeon_emit(cs, va >> 32);
4357
4358 if (info->count_buffer) {
4359 count_va = radv_buffer_get_va(info->count_buffer->bo);
4360 count_va += info->count_buffer->offset +
4361 info->count_buffer_offset;
4362
4363 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
4364 }
4365
4366 if (!state->subpass->view_mask) {
4367 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4368 info->indexed,
4369 info->count,
4370 count_va,
4371 info->stride);
4372 } else {
4373 unsigned i;
4374 for_each_bit(i, state->subpass->view_mask) {
4375 radv_emit_view_index(cmd_buffer, i);
4376
4377 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4378 info->indexed,
4379 info->count,
4380 count_va,
4381 info->stride);
4382 }
4383 }
4384 } else {
4385 assert(state->pipeline->graphics.vtx_base_sgpr);
4386
4387 if (info->vertex_offset != state->last_vertex_offset ||
4388 info->first_instance != state->last_first_instance) {
4389 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
4390 state->pipeline->graphics.vtx_emit_num);
4391
4392 radeon_emit(cs, info->vertex_offset);
4393 radeon_emit(cs, info->first_instance);
4394 if (state->pipeline->graphics.vtx_emit_num == 3)
4395 radeon_emit(cs, 0);
4396 state->last_first_instance = info->first_instance;
4397 state->last_vertex_offset = info->vertex_offset;
4398 }
4399
4400 if (state->last_num_instances != info->instance_count) {
4401 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
4402 radeon_emit(cs, info->instance_count);
4403 state->last_num_instances = info->instance_count;
4404 }
4405
4406 if (info->indexed) {
4407 int index_size = radv_get_vgt_index_size(state->index_type);
4408 uint64_t index_va;
4409
4410 /* Skip draw calls with 0-sized index buffers. They
4411 * cause a hang on some chips, like Navi10-14.
4412 */
4413 if (!cmd_buffer->state.max_index_count)
4414 return;
4415
4416 index_va = state->index_va;
4417 index_va += info->first_index * index_size;
4418
4419 if (!state->subpass->view_mask) {
4420 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4421 index_va,
4422 info->count);
4423 } else {
4424 unsigned i;
4425 for_each_bit(i, state->subpass->view_mask) {
4426 radv_emit_view_index(cmd_buffer, i);
4427
4428 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4429 index_va,
4430 info->count);
4431 }
4432 }
4433 } else {
4434 if (!state->subpass->view_mask) {
4435 radv_cs_emit_draw_packet(cmd_buffer,
4436 info->count,
4437 !!info->strmout_buffer);
4438 } else {
4439 unsigned i;
4440 for_each_bit(i, state->subpass->view_mask) {
4441 radv_emit_view_index(cmd_buffer, i);
4442
4443 radv_cs_emit_draw_packet(cmd_buffer,
4444 info->count,
4445 !!info->strmout_buffer);
4446 }
4447 }
4448 }
4449 }
4450 }
4451
4452 /*
4453 * Vega and raven have a bug which triggers if there are multiple context
4454 * register contexts active at the same time with different scissor values.
4455 *
4456 * There are two possible workarounds:
4457 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4458 * there is only ever 1 active set of scissor values at the same time.
4459 *
4460 * 2) Whenever the hardware switches contexts we have to set the scissor
4461 * registers again even if it is a noop. That way the new context gets
4462 * the correct scissor values.
4463 *
4464 * This implements option 2. radv_need_late_scissor_emission needs to
4465 * return true on affected HW if radv_emit_all_graphics_states sets
4466 * any context registers.
4467 */
4468 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
4469 const struct radv_draw_info *info)
4470 {
4471 struct radv_cmd_state *state = &cmd_buffer->state;
4472
4473 if (!cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
4474 return false;
4475
4476 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
4477 return true;
4478
4479 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
4480
4481 /* Index, vertex and streamout buffers don't change context regs, and
4482 * pipeline is already handled.
4483 */
4484 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
4485 RADV_CMD_DIRTY_VERTEX_BUFFER |
4486 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
4487 RADV_CMD_DIRTY_PIPELINE);
4488
4489 if (cmd_buffer->state.dirty & used_states)
4490 return true;
4491
4492 uint32_t primitive_reset_index =
4493 radv_get_primitive_reset_index(cmd_buffer);
4494
4495 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
4496 primitive_reset_index != state->last_primitive_reset_index)
4497 return true;
4498
4499 return false;
4500 }
4501
4502 static void
4503 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
4504 const struct radv_draw_info *info)
4505 {
4506 bool late_scissor_emission;
4507
4508 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
4509 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
4510 radv_emit_rbplus_state(cmd_buffer);
4511
4512 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
4513 radv_emit_graphics_pipeline(cmd_buffer);
4514
4515 /* This should be before the cmd_buffer->state.dirty is cleared
4516 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4517 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4518 late_scissor_emission =
4519 radv_need_late_scissor_emission(cmd_buffer, info);
4520
4521 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
4522 radv_emit_framebuffer_state(cmd_buffer);
4523
4524 if (info->indexed) {
4525 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
4526 radv_emit_index_buffer(cmd_buffer);
4527 } else {
4528 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4529 * so the state must be re-emitted before the next indexed
4530 * draw.
4531 */
4532 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
4533 cmd_buffer->state.last_index_type = -1;
4534 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
4535 }
4536 }
4537
4538 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
4539
4540 radv_emit_draw_registers(cmd_buffer, info);
4541
4542 if (late_scissor_emission)
4543 radv_emit_scissor(cmd_buffer);
4544 }
4545
4546 static void
4547 radv_draw(struct radv_cmd_buffer *cmd_buffer,
4548 const struct radv_draw_info *info)
4549 {
4550 struct radeon_info *rad_info =
4551 &cmd_buffer->device->physical_device->rad_info;
4552 bool has_prefetch =
4553 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4554 bool pipeline_is_dirty =
4555 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
4556 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
4557
4558 ASSERTED unsigned cdw_max =
4559 radeon_check_space(cmd_buffer->device->ws,
4560 cmd_buffer->cs, 4096);
4561
4562 if (likely(!info->indirect)) {
4563 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4564 * no workaround for indirect draws, but we can at least skip
4565 * direct draws.
4566 */
4567 if (unlikely(!info->instance_count))
4568 return;
4569
4570 /* Handle count == 0. */
4571 if (unlikely(!info->count && !info->strmout_buffer))
4572 return;
4573 }
4574
4575 /* Use optimal packet order based on whether we need to sync the
4576 * pipeline.
4577 */
4578 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4579 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4580 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4581 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4582 /* If we have to wait for idle, set all states first, so that
4583 * all SET packets are processed in parallel with previous draw
4584 * calls. Then upload descriptors, set shader pointers, and
4585 * draw, and prefetch at the end. This ensures that the time
4586 * the CUs are idle is very short. (there are only SET_SH
4587 * packets between the wait and the draw)
4588 */
4589 radv_emit_all_graphics_states(cmd_buffer, info);
4590 si_emit_cache_flush(cmd_buffer);
4591 /* <-- CUs are idle here --> */
4592
4593 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4594
4595 radv_emit_draw_packets(cmd_buffer, info);
4596 /* <-- CUs are busy here --> */
4597
4598 /* Start prefetches after the draw has been started. Both will
4599 * run in parallel, but starting the draw first is more
4600 * important.
4601 */
4602 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4603 radv_emit_prefetch_L2(cmd_buffer,
4604 cmd_buffer->state.pipeline, false);
4605 }
4606 } else {
4607 /* If we don't wait for idle, start prefetches first, then set
4608 * states, and draw at the end.
4609 */
4610 si_emit_cache_flush(cmd_buffer);
4611
4612 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4613 /* Only prefetch the vertex shader and VBO descriptors
4614 * in order to start the draw as soon as possible.
4615 */
4616 radv_emit_prefetch_L2(cmd_buffer,
4617 cmd_buffer->state.pipeline, true);
4618 }
4619
4620 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4621
4622 radv_emit_all_graphics_states(cmd_buffer, info);
4623 radv_emit_draw_packets(cmd_buffer, info);
4624
4625 /* Prefetch the remaining shaders after the draw has been
4626 * started.
4627 */
4628 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4629 radv_emit_prefetch_L2(cmd_buffer,
4630 cmd_buffer->state.pipeline, false);
4631 }
4632 }
4633
4634 /* Workaround for a VGT hang when streamout is enabled.
4635 * It must be done after drawing.
4636 */
4637 if (cmd_buffer->state.streamout.streamout_enabled &&
4638 (rad_info->family == CHIP_HAWAII ||
4639 rad_info->family == CHIP_TONGA ||
4640 rad_info->family == CHIP_FIJI)) {
4641 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
4642 }
4643
4644 assert(cmd_buffer->cs->cdw <= cdw_max);
4645 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
4646 }
4647
4648 void radv_CmdDraw(
4649 VkCommandBuffer commandBuffer,
4650 uint32_t vertexCount,
4651 uint32_t instanceCount,
4652 uint32_t firstVertex,
4653 uint32_t firstInstance)
4654 {
4655 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4656 struct radv_draw_info info = {};
4657
4658 info.count = vertexCount;
4659 info.instance_count = instanceCount;
4660 info.first_instance = firstInstance;
4661 info.vertex_offset = firstVertex;
4662
4663 radv_draw(cmd_buffer, &info);
4664 }
4665
4666 void radv_CmdDrawIndexed(
4667 VkCommandBuffer commandBuffer,
4668 uint32_t indexCount,
4669 uint32_t instanceCount,
4670 uint32_t firstIndex,
4671 int32_t vertexOffset,
4672 uint32_t firstInstance)
4673 {
4674 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4675 struct radv_draw_info info = {};
4676
4677 info.indexed = true;
4678 info.count = indexCount;
4679 info.instance_count = instanceCount;
4680 info.first_index = firstIndex;
4681 info.vertex_offset = vertexOffset;
4682 info.first_instance = firstInstance;
4683
4684 radv_draw(cmd_buffer, &info);
4685 }
4686
4687 void radv_CmdDrawIndirect(
4688 VkCommandBuffer commandBuffer,
4689 VkBuffer _buffer,
4690 VkDeviceSize offset,
4691 uint32_t drawCount,
4692 uint32_t stride)
4693 {
4694 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4695 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4696 struct radv_draw_info info = {};
4697
4698 info.count = drawCount;
4699 info.indirect = buffer;
4700 info.indirect_offset = offset;
4701 info.stride = stride;
4702
4703 radv_draw(cmd_buffer, &info);
4704 }
4705
4706 void radv_CmdDrawIndexedIndirect(
4707 VkCommandBuffer commandBuffer,
4708 VkBuffer _buffer,
4709 VkDeviceSize offset,
4710 uint32_t drawCount,
4711 uint32_t stride)
4712 {
4713 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4714 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4715 struct radv_draw_info info = {};
4716
4717 info.indexed = true;
4718 info.count = drawCount;
4719 info.indirect = buffer;
4720 info.indirect_offset = offset;
4721 info.stride = stride;
4722
4723 radv_draw(cmd_buffer, &info);
4724 }
4725
4726 void radv_CmdDrawIndirectCountKHR(
4727 VkCommandBuffer commandBuffer,
4728 VkBuffer _buffer,
4729 VkDeviceSize offset,
4730 VkBuffer _countBuffer,
4731 VkDeviceSize countBufferOffset,
4732 uint32_t maxDrawCount,
4733 uint32_t stride)
4734 {
4735 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4736 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4737 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4738 struct radv_draw_info info = {};
4739
4740 info.count = maxDrawCount;
4741 info.indirect = buffer;
4742 info.indirect_offset = offset;
4743 info.count_buffer = count_buffer;
4744 info.count_buffer_offset = countBufferOffset;
4745 info.stride = stride;
4746
4747 radv_draw(cmd_buffer, &info);
4748 }
4749
4750 void radv_CmdDrawIndexedIndirectCountKHR(
4751 VkCommandBuffer commandBuffer,
4752 VkBuffer _buffer,
4753 VkDeviceSize offset,
4754 VkBuffer _countBuffer,
4755 VkDeviceSize countBufferOffset,
4756 uint32_t maxDrawCount,
4757 uint32_t stride)
4758 {
4759 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4760 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4761 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4762 struct radv_draw_info info = {};
4763
4764 info.indexed = true;
4765 info.count = maxDrawCount;
4766 info.indirect = buffer;
4767 info.indirect_offset = offset;
4768 info.count_buffer = count_buffer;
4769 info.count_buffer_offset = countBufferOffset;
4770 info.stride = stride;
4771
4772 radv_draw(cmd_buffer, &info);
4773 }
4774
4775 struct radv_dispatch_info {
4776 /**
4777 * Determine the layout of the grid (in block units) to be used.
4778 */
4779 uint32_t blocks[3];
4780
4781 /**
4782 * A starting offset for the grid. If unaligned is set, the offset
4783 * must still be aligned.
4784 */
4785 uint32_t offsets[3];
4786 /**
4787 * Whether it's an unaligned compute dispatch.
4788 */
4789 bool unaligned;
4790
4791 /**
4792 * Indirect compute parameters resource.
4793 */
4794 struct radv_buffer *indirect;
4795 uint64_t indirect_offset;
4796 };
4797
4798 static void
4799 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
4800 const struct radv_dispatch_info *info)
4801 {
4802 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4803 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4804 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
4805 struct radeon_winsys *ws = cmd_buffer->device->ws;
4806 bool predicating = cmd_buffer->state.predicating;
4807 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4808 struct radv_userdata_info *loc;
4809
4810 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
4811 AC_UD_CS_GRID_SIZE);
4812
4813 ASSERTED unsigned cdw_max = radeon_check_space(ws, cs, 25);
4814
4815 if (info->indirect) {
4816 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4817
4818 va += info->indirect->offset + info->indirect_offset;
4819
4820 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4821
4822 if (loc->sgpr_idx != -1) {
4823 for (unsigned i = 0; i < 3; ++i) {
4824 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4825 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4826 COPY_DATA_DST_SEL(COPY_DATA_REG));
4827 radeon_emit(cs, (va + 4 * i));
4828 radeon_emit(cs, (va + 4 * i) >> 32);
4829 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
4830 + loc->sgpr_idx * 4) >> 2) + i);
4831 radeon_emit(cs, 0);
4832 }
4833 }
4834
4835 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
4836 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
4837 PKT3_SHADER_TYPE_S(1));
4838 radeon_emit(cs, va);
4839 radeon_emit(cs, va >> 32);
4840 radeon_emit(cs, dispatch_initiator);
4841 } else {
4842 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
4843 PKT3_SHADER_TYPE_S(1));
4844 radeon_emit(cs, 1);
4845 radeon_emit(cs, va);
4846 radeon_emit(cs, va >> 32);
4847
4848 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
4849 PKT3_SHADER_TYPE_S(1));
4850 radeon_emit(cs, 0);
4851 radeon_emit(cs, dispatch_initiator);
4852 }
4853 } else {
4854 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
4855 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
4856
4857 if (info->unaligned) {
4858 unsigned *cs_block_size = compute_shader->info.cs.block_size;
4859 unsigned remainder[3];
4860
4861 /* If aligned, these should be an entire block size,
4862 * not 0.
4863 */
4864 remainder[0] = blocks[0] + cs_block_size[0] -
4865 align_u32_npot(blocks[0], cs_block_size[0]);
4866 remainder[1] = blocks[1] + cs_block_size[1] -
4867 align_u32_npot(blocks[1], cs_block_size[1]);
4868 remainder[2] = blocks[2] + cs_block_size[2] -
4869 align_u32_npot(blocks[2], cs_block_size[2]);
4870
4871 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
4872 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
4873 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
4874
4875 for(unsigned i = 0; i < 3; ++i) {
4876 assert(offsets[i] % cs_block_size[i] == 0);
4877 offsets[i] /= cs_block_size[i];
4878 }
4879
4880 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4881 radeon_emit(cs,
4882 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
4883 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4884 radeon_emit(cs,
4885 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4886 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4887 radeon_emit(cs,
4888 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4889 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4890
4891 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4892 }
4893
4894 if (loc->sgpr_idx != -1) {
4895 assert(loc->num_sgprs == 3);
4896
4897 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4898 loc->sgpr_idx * 4, 3);
4899 radeon_emit(cs, blocks[0]);
4900 radeon_emit(cs, blocks[1]);
4901 radeon_emit(cs, blocks[2]);
4902 }
4903
4904 if (offsets[0] || offsets[1] || offsets[2]) {
4905 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4906 radeon_emit(cs, offsets[0]);
4907 radeon_emit(cs, offsets[1]);
4908 radeon_emit(cs, offsets[2]);
4909
4910 /* The blocks in the packet are not counts but end values. */
4911 for (unsigned i = 0; i < 3; ++i)
4912 blocks[i] += offsets[i];
4913 } else {
4914 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4915 }
4916
4917 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4918 PKT3_SHADER_TYPE_S(1));
4919 radeon_emit(cs, blocks[0]);
4920 radeon_emit(cs, blocks[1]);
4921 radeon_emit(cs, blocks[2]);
4922 radeon_emit(cs, dispatch_initiator);
4923 }
4924
4925 assert(cmd_buffer->cs->cdw <= cdw_max);
4926 }
4927
4928 static void
4929 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4930 {
4931 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4932 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4933 }
4934
4935 static void
4936 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4937 const struct radv_dispatch_info *info)
4938 {
4939 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4940 bool has_prefetch =
4941 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4942 bool pipeline_is_dirty = pipeline &&
4943 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4944
4945 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4946 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4947 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4948 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4949 /* If we have to wait for idle, set all states first, so that
4950 * all SET packets are processed in parallel with previous draw
4951 * calls. Then upload descriptors, set shader pointers, and
4952 * dispatch, and prefetch at the end. This ensures that the
4953 * time the CUs are idle is very short. (there are only SET_SH
4954 * packets between the wait and the draw)
4955 */
4956 radv_emit_compute_pipeline(cmd_buffer);
4957 si_emit_cache_flush(cmd_buffer);
4958 /* <-- CUs are idle here --> */
4959
4960 radv_upload_compute_shader_descriptors(cmd_buffer);
4961
4962 radv_emit_dispatch_packets(cmd_buffer, info);
4963 /* <-- CUs are busy here --> */
4964
4965 /* Start prefetches after the dispatch has been started. Both
4966 * will run in parallel, but starting the dispatch first is
4967 * more important.
4968 */
4969 if (has_prefetch && pipeline_is_dirty) {
4970 radv_emit_shader_prefetch(cmd_buffer,
4971 pipeline->shaders[MESA_SHADER_COMPUTE]);
4972 }
4973 } else {
4974 /* If we don't wait for idle, start prefetches first, then set
4975 * states, and dispatch at the end.
4976 */
4977 si_emit_cache_flush(cmd_buffer);
4978
4979 if (has_prefetch && pipeline_is_dirty) {
4980 radv_emit_shader_prefetch(cmd_buffer,
4981 pipeline->shaders[MESA_SHADER_COMPUTE]);
4982 }
4983
4984 radv_upload_compute_shader_descriptors(cmd_buffer);
4985
4986 radv_emit_compute_pipeline(cmd_buffer);
4987 radv_emit_dispatch_packets(cmd_buffer, info);
4988 }
4989
4990 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
4991 }
4992
4993 void radv_CmdDispatchBase(
4994 VkCommandBuffer commandBuffer,
4995 uint32_t base_x,
4996 uint32_t base_y,
4997 uint32_t base_z,
4998 uint32_t x,
4999 uint32_t y,
5000 uint32_t z)
5001 {
5002 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5003 struct radv_dispatch_info info = {};
5004
5005 info.blocks[0] = x;
5006 info.blocks[1] = y;
5007 info.blocks[2] = z;
5008
5009 info.offsets[0] = base_x;
5010 info.offsets[1] = base_y;
5011 info.offsets[2] = base_z;
5012 radv_dispatch(cmd_buffer, &info);
5013 }
5014
5015 void radv_CmdDispatch(
5016 VkCommandBuffer commandBuffer,
5017 uint32_t x,
5018 uint32_t y,
5019 uint32_t z)
5020 {
5021 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
5022 }
5023
5024 void radv_CmdDispatchIndirect(
5025 VkCommandBuffer commandBuffer,
5026 VkBuffer _buffer,
5027 VkDeviceSize offset)
5028 {
5029 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5030 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5031 struct radv_dispatch_info info = {};
5032
5033 info.indirect = buffer;
5034 info.indirect_offset = offset;
5035
5036 radv_dispatch(cmd_buffer, &info);
5037 }
5038
5039 void radv_unaligned_dispatch(
5040 struct radv_cmd_buffer *cmd_buffer,
5041 uint32_t x,
5042 uint32_t y,
5043 uint32_t z)
5044 {
5045 struct radv_dispatch_info info = {};
5046
5047 info.blocks[0] = x;
5048 info.blocks[1] = y;
5049 info.blocks[2] = z;
5050 info.unaligned = 1;
5051
5052 radv_dispatch(cmd_buffer, &info);
5053 }
5054
5055 void radv_CmdEndRenderPass(
5056 VkCommandBuffer commandBuffer)
5057 {
5058 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5059
5060 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
5061
5062 radv_cmd_buffer_end_subpass(cmd_buffer);
5063
5064 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
5065 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
5066
5067 cmd_buffer->state.pass = NULL;
5068 cmd_buffer->state.subpass = NULL;
5069 cmd_buffer->state.attachments = NULL;
5070 cmd_buffer->state.framebuffer = NULL;
5071 cmd_buffer->state.subpass_sample_locs = NULL;
5072 }
5073
5074 void radv_CmdEndRenderPass2KHR(
5075 VkCommandBuffer commandBuffer,
5076 const VkSubpassEndInfoKHR* pSubpassEndInfo)
5077 {
5078 radv_CmdEndRenderPass(commandBuffer);
5079 }
5080
5081 /*
5082 * For HTILE we have the following interesting clear words:
5083 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5084 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5085 * 0xfffffff0: Clear depth to 1.0
5086 * 0x00000000: Clear depth to 0.0
5087 */
5088 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
5089 struct radv_image *image,
5090 const VkImageSubresourceRange *range,
5091 uint32_t clear_word)
5092 {
5093 assert(range->baseMipLevel == 0);
5094 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
5095 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
5096 struct radv_cmd_state *state = &cmd_buffer->state;
5097 VkClearDepthStencilValue value = {};
5098
5099 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5100 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5101
5102 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, clear_word);
5103
5104 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5105
5106 if (vk_format_is_stencil(image->vk_format))
5107 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
5108
5109 radv_set_ds_clear_metadata(cmd_buffer, image, range, value, aspects);
5110
5111 if (radv_image_is_tc_compat_htile(image)) {
5112 /* Initialize the TC-compat metada value to 0 because by
5113 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5114 * need have to conditionally update its value when performing
5115 * a fast depth clear.
5116 */
5117 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, range, 0);
5118 }
5119 }
5120
5121 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
5122 struct radv_image *image,
5123 VkImageLayout src_layout,
5124 bool src_render_loop,
5125 VkImageLayout dst_layout,
5126 bool dst_render_loop,
5127 unsigned src_queue_mask,
5128 unsigned dst_queue_mask,
5129 const VkImageSubresourceRange *range,
5130 struct radv_sample_locations_state *sample_locs)
5131 {
5132 if (!radv_image_has_htile(image))
5133 return;
5134
5135 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5136 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5137
5138 if (radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop,
5139 dst_queue_mask)) {
5140 clear_value = 0;
5141 }
5142
5143 radv_initialize_htile(cmd_buffer, image, range, clear_value);
5144 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5145 radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5146 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5147 radv_initialize_htile(cmd_buffer, image, range, clear_value);
5148 } else if (radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5149 !radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5150 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5151 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5152
5153 radv_decompress_depth_image_inplace(cmd_buffer, image, range,
5154 sample_locs);
5155
5156 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5157 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5158 }
5159 }
5160
5161 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
5162 struct radv_image *image,
5163 const VkImageSubresourceRange *range,
5164 uint32_t value)
5165 {
5166 struct radv_cmd_state *state = &cmd_buffer->state;
5167
5168 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5169 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5170
5171 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
5172
5173 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5174 }
5175
5176 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
5177 struct radv_image *image,
5178 const VkImageSubresourceRange *range)
5179 {
5180 struct radv_cmd_state *state = &cmd_buffer->state;
5181 static const uint32_t fmask_clear_values[4] = {
5182 0x00000000,
5183 0x02020202,
5184 0xE4E4E4E4,
5185 0x76543210
5186 };
5187 uint32_t log2_samples = util_logbase2(image->info.samples);
5188 uint32_t value = fmask_clear_values[log2_samples];
5189
5190 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5191 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5192
5193 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
5194
5195 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5196 }
5197
5198 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
5199 struct radv_image *image,
5200 const VkImageSubresourceRange *range, uint32_t value)
5201 {
5202 struct radv_cmd_state *state = &cmd_buffer->state;
5203 unsigned size = 0;
5204
5205 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5206 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5207
5208 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
5209
5210 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
5211 /* When DCC is enabled with mipmaps, some levels might not
5212 * support fast clears and we have to initialize them as "fully
5213 * expanded".
5214 */
5215 /* Compute the size of all fast clearable DCC levels. */
5216 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
5217 struct legacy_surf_level *surf_level =
5218 &image->planes[0].surface.u.legacy.level[i];
5219 unsigned dcc_fast_clear_size =
5220 surf_level->dcc_slice_fast_clear_size * image->info.array_size;
5221
5222 if (!dcc_fast_clear_size)
5223 break;
5224
5225 size = surf_level->dcc_offset + dcc_fast_clear_size;
5226 }
5227
5228 /* Initialize the mipmap levels without DCC. */
5229 if (size != image->planes[0].surface.dcc_size) {
5230 state->flush_bits |=
5231 radv_fill_buffer(cmd_buffer, image->bo,
5232 image->offset + image->dcc_offset + size,
5233 image->planes[0].surface.dcc_size - size,
5234 0xffffffff);
5235 }
5236 }
5237
5238 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5239 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5240 }
5241
5242 /**
5243 * Initialize DCC/FMASK/CMASK metadata for a color image.
5244 */
5245 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
5246 struct radv_image *image,
5247 VkImageLayout src_layout,
5248 bool src_render_loop,
5249 VkImageLayout dst_layout,
5250 bool dst_render_loop,
5251 unsigned src_queue_mask,
5252 unsigned dst_queue_mask,
5253 const VkImageSubresourceRange *range)
5254 {
5255 if (radv_image_has_cmask(image)) {
5256 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5257
5258 /* TODO: clarify this. */
5259 if (radv_image_has_fmask(image)) {
5260 value = 0xccccccccu;
5261 }
5262
5263 radv_initialise_cmask(cmd_buffer, image, range, value);
5264 }
5265
5266 if (radv_image_has_fmask(image)) {
5267 radv_initialize_fmask(cmd_buffer, image, range);
5268 }
5269
5270 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5271 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5272 bool need_decompress_pass = false;
5273
5274 if (radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout,
5275 dst_render_loop,
5276 dst_queue_mask)) {
5277 value = 0x20202020u;
5278 need_decompress_pass = true;
5279 }
5280
5281 radv_initialize_dcc(cmd_buffer, image, range, value);
5282
5283 radv_update_fce_metadata(cmd_buffer, image, range,
5284 need_decompress_pass);
5285 }
5286
5287 if (radv_image_has_cmask(image) ||
5288 radv_dcc_enabled(image, range->baseMipLevel)) {
5289 uint32_t color_values[2] = {};
5290 radv_set_color_clear_metadata(cmd_buffer, image, range,
5291 color_values);
5292 }
5293 }
5294
5295 /**
5296 * Handle color image transitions for DCC/FMASK/CMASK.
5297 */
5298 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
5299 struct radv_image *image,
5300 VkImageLayout src_layout,
5301 bool src_render_loop,
5302 VkImageLayout dst_layout,
5303 bool dst_render_loop,
5304 unsigned src_queue_mask,
5305 unsigned dst_queue_mask,
5306 const VkImageSubresourceRange *range)
5307 {
5308 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5309 radv_init_color_image_metadata(cmd_buffer, image,
5310 src_layout, src_render_loop,
5311 dst_layout, dst_render_loop,
5312 src_queue_mask, dst_queue_mask,
5313 range);
5314 return;
5315 }
5316
5317 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5318 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
5319 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
5320 } else if (radv_layout_dcc_compressed(cmd_buffer->device, image, src_layout, src_render_loop, src_queue_mask) &&
5321 !radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout, dst_render_loop, dst_queue_mask)) {
5322 radv_decompress_dcc(cmd_buffer, image, range);
5323 } else if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5324 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5325 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5326 }
5327 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
5328 bool fce_eliminate = false, fmask_expand = false;
5329
5330 if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5331 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5332 fce_eliminate = true;
5333 }
5334
5335 if (radv_image_has_fmask(image)) {
5336 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
5337 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
5338 /* A FMASK decompress is required before doing
5339 * a MSAA decompress using FMASK.
5340 */
5341 fmask_expand = true;
5342 }
5343 }
5344
5345 if (fce_eliminate || fmask_expand)
5346 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5347
5348 if (fmask_expand)
5349 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
5350 }
5351 }
5352
5353 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
5354 struct radv_image *image,
5355 VkImageLayout src_layout,
5356 bool src_render_loop,
5357 VkImageLayout dst_layout,
5358 bool dst_render_loop,
5359 uint32_t src_family,
5360 uint32_t dst_family,
5361 const VkImageSubresourceRange *range,
5362 struct radv_sample_locations_state *sample_locs)
5363 {
5364 if (image->exclusive && src_family != dst_family) {
5365 /* This is an acquire or a release operation and there will be
5366 * a corresponding release/acquire. Do the transition in the
5367 * most flexible queue. */
5368
5369 assert(src_family == cmd_buffer->queue_family_index ||
5370 dst_family == cmd_buffer->queue_family_index);
5371
5372 if (src_family == VK_QUEUE_FAMILY_EXTERNAL ||
5373 src_family == VK_QUEUE_FAMILY_FOREIGN_EXT)
5374 return;
5375
5376 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
5377 return;
5378
5379 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
5380 (src_family == RADV_QUEUE_GENERAL ||
5381 dst_family == RADV_QUEUE_GENERAL))
5382 return;
5383 }
5384
5385 if (src_layout == dst_layout)
5386 return;
5387
5388 unsigned src_queue_mask =
5389 radv_image_queue_family_mask(image, src_family,
5390 cmd_buffer->queue_family_index);
5391 unsigned dst_queue_mask =
5392 radv_image_queue_family_mask(image, dst_family,
5393 cmd_buffer->queue_family_index);
5394
5395 if (vk_format_is_depth(image->vk_format)) {
5396 radv_handle_depth_image_transition(cmd_buffer, image,
5397 src_layout, src_render_loop,
5398 dst_layout, dst_render_loop,
5399 src_queue_mask, dst_queue_mask,
5400 range, sample_locs);
5401 } else {
5402 radv_handle_color_image_transition(cmd_buffer, image,
5403 src_layout, src_render_loop,
5404 dst_layout, dst_render_loop,
5405 src_queue_mask, dst_queue_mask,
5406 range);
5407 }
5408 }
5409
5410 struct radv_barrier_info {
5411 uint32_t eventCount;
5412 const VkEvent *pEvents;
5413 VkPipelineStageFlags srcStageMask;
5414 VkPipelineStageFlags dstStageMask;
5415 };
5416
5417 static void
5418 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
5419 uint32_t memoryBarrierCount,
5420 const VkMemoryBarrier *pMemoryBarriers,
5421 uint32_t bufferMemoryBarrierCount,
5422 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
5423 uint32_t imageMemoryBarrierCount,
5424 const VkImageMemoryBarrier *pImageMemoryBarriers,
5425 const struct radv_barrier_info *info)
5426 {
5427 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5428 enum radv_cmd_flush_bits src_flush_bits = 0;
5429 enum radv_cmd_flush_bits dst_flush_bits = 0;
5430
5431 for (unsigned i = 0; i < info->eventCount; ++i) {
5432 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
5433 uint64_t va = radv_buffer_get_va(event->bo);
5434
5435 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5436
5437 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
5438
5439 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
5440 assert(cmd_buffer->cs->cdw <= cdw_max);
5441 }
5442
5443 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
5444 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
5445 NULL);
5446 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
5447 NULL);
5448 }
5449
5450 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
5451 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
5452 NULL);
5453 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
5454 NULL);
5455 }
5456
5457 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5458 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5459
5460 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
5461 image);
5462 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
5463 image);
5464 }
5465
5466 /* The Vulkan spec 1.1.98 says:
5467 *
5468 * "An execution dependency with only
5469 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5470 * will only prevent that stage from executing in subsequently
5471 * submitted commands. As this stage does not perform any actual
5472 * execution, this is not observable - in effect, it does not delay
5473 * processing of subsequent commands. Similarly an execution dependency
5474 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5475 * will effectively not wait for any prior commands to complete."
5476 */
5477 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
5478 radv_stage_flush(cmd_buffer, info->srcStageMask);
5479 cmd_buffer->state.flush_bits |= src_flush_bits;
5480
5481 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5482 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5483
5484 const struct VkSampleLocationsInfoEXT *sample_locs_info =
5485 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
5486 SAMPLE_LOCATIONS_INFO_EXT);
5487 struct radv_sample_locations_state sample_locations = {};
5488
5489 if (sample_locs_info) {
5490 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
5491 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
5492 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
5493 sample_locations.count = sample_locs_info->sampleLocationsCount;
5494 typed_memcpy(&sample_locations.locations[0],
5495 sample_locs_info->pSampleLocations,
5496 sample_locs_info->sampleLocationsCount);
5497 }
5498
5499 radv_handle_image_transition(cmd_buffer, image,
5500 pImageMemoryBarriers[i].oldLayout,
5501 false, /* Outside of a renderpass we are never in a renderloop */
5502 pImageMemoryBarriers[i].newLayout,
5503 false, /* Outside of a renderpass we are never in a renderloop */
5504 pImageMemoryBarriers[i].srcQueueFamilyIndex,
5505 pImageMemoryBarriers[i].dstQueueFamilyIndex,
5506 &pImageMemoryBarriers[i].subresourceRange,
5507 sample_locs_info ? &sample_locations : NULL);
5508 }
5509
5510 /* Make sure CP DMA is idle because the driver might have performed a
5511 * DMA operation for copying or filling buffers/images.
5512 */
5513 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5514 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5515 si_cp_dma_wait_for_idle(cmd_buffer);
5516
5517 cmd_buffer->state.flush_bits |= dst_flush_bits;
5518 }
5519
5520 void radv_CmdPipelineBarrier(
5521 VkCommandBuffer commandBuffer,
5522 VkPipelineStageFlags srcStageMask,
5523 VkPipelineStageFlags destStageMask,
5524 VkBool32 byRegion,
5525 uint32_t memoryBarrierCount,
5526 const VkMemoryBarrier* pMemoryBarriers,
5527 uint32_t bufferMemoryBarrierCount,
5528 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5529 uint32_t imageMemoryBarrierCount,
5530 const VkImageMemoryBarrier* pImageMemoryBarriers)
5531 {
5532 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5533 struct radv_barrier_info info;
5534
5535 info.eventCount = 0;
5536 info.pEvents = NULL;
5537 info.srcStageMask = srcStageMask;
5538 info.dstStageMask = destStageMask;
5539
5540 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5541 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5542 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5543 }
5544
5545
5546 static void write_event(struct radv_cmd_buffer *cmd_buffer,
5547 struct radv_event *event,
5548 VkPipelineStageFlags stageMask,
5549 unsigned value)
5550 {
5551 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5552 uint64_t va = radv_buffer_get_va(event->bo);
5553
5554 si_emit_cache_flush(cmd_buffer);
5555
5556 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5557
5558 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
5559
5560 /* Flags that only require a top-of-pipe event. */
5561 VkPipelineStageFlags top_of_pipe_flags =
5562 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
5563
5564 /* Flags that only require a post-index-fetch event. */
5565 VkPipelineStageFlags post_index_fetch_flags =
5566 top_of_pipe_flags |
5567 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
5568 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
5569
5570 /* Make sure CP DMA is idle because the driver might have performed a
5571 * DMA operation for copying or filling buffers/images.
5572 */
5573 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5574 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5575 si_cp_dma_wait_for_idle(cmd_buffer);
5576
5577 /* TODO: Emit EOS events for syncing PS/CS stages. */
5578
5579 if (!(stageMask & ~top_of_pipe_flags)) {
5580 /* Just need to sync the PFP engine. */
5581 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5582 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5583 S_370_WR_CONFIRM(1) |
5584 S_370_ENGINE_SEL(V_370_PFP));
5585 radeon_emit(cs, va);
5586 radeon_emit(cs, va >> 32);
5587 radeon_emit(cs, value);
5588 } else if (!(stageMask & ~post_index_fetch_flags)) {
5589 /* Sync ME because PFP reads index and indirect buffers. */
5590 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5591 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5592 S_370_WR_CONFIRM(1) |
5593 S_370_ENGINE_SEL(V_370_ME));
5594 radeon_emit(cs, va);
5595 radeon_emit(cs, va >> 32);
5596 radeon_emit(cs, value);
5597 } else {
5598 /* Otherwise, sync all prior GPU work using an EOP event. */
5599 si_cs_emit_write_event_eop(cs,
5600 cmd_buffer->device->physical_device->rad_info.chip_class,
5601 radv_cmd_buffer_uses_mec(cmd_buffer),
5602 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5603 EOP_DST_SEL_MEM,
5604 EOP_DATA_SEL_VALUE_32BIT, va, value,
5605 cmd_buffer->gfx9_eop_bug_va);
5606 }
5607
5608 assert(cmd_buffer->cs->cdw <= cdw_max);
5609 }
5610
5611 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
5612 VkEvent _event,
5613 VkPipelineStageFlags stageMask)
5614 {
5615 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5616 RADV_FROM_HANDLE(radv_event, event, _event);
5617
5618 write_event(cmd_buffer, event, stageMask, 1);
5619 }
5620
5621 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
5622 VkEvent _event,
5623 VkPipelineStageFlags stageMask)
5624 {
5625 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5626 RADV_FROM_HANDLE(radv_event, event, _event);
5627
5628 write_event(cmd_buffer, event, stageMask, 0);
5629 }
5630
5631 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
5632 uint32_t eventCount,
5633 const VkEvent* pEvents,
5634 VkPipelineStageFlags srcStageMask,
5635 VkPipelineStageFlags dstStageMask,
5636 uint32_t memoryBarrierCount,
5637 const VkMemoryBarrier* pMemoryBarriers,
5638 uint32_t bufferMemoryBarrierCount,
5639 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5640 uint32_t imageMemoryBarrierCount,
5641 const VkImageMemoryBarrier* pImageMemoryBarriers)
5642 {
5643 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5644 struct radv_barrier_info info;
5645
5646 info.eventCount = eventCount;
5647 info.pEvents = pEvents;
5648 info.srcStageMask = 0;
5649
5650 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5651 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5652 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5653 }
5654
5655
5656 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
5657 uint32_t deviceMask)
5658 {
5659 /* No-op */
5660 }
5661
5662 /* VK_EXT_conditional_rendering */
5663 void radv_CmdBeginConditionalRenderingEXT(
5664 VkCommandBuffer commandBuffer,
5665 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
5666 {
5667 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5668 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
5669 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5670 bool draw_visible = true;
5671 uint64_t pred_value = 0;
5672 uint64_t va, new_va;
5673 unsigned pred_offset;
5674
5675 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
5676
5677 /* By default, if the 32-bit value at offset in buffer memory is zero,
5678 * then the rendering commands are discarded, otherwise they are
5679 * executed as normal. If the inverted flag is set, all commands are
5680 * discarded if the value is non zero.
5681 */
5682 if (pConditionalRenderingBegin->flags &
5683 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
5684 draw_visible = false;
5685 }
5686
5687 si_emit_cache_flush(cmd_buffer);
5688
5689 /* From the Vulkan spec 1.1.107:
5690 *
5691 * "If the 32-bit value at offset in buffer memory is zero, then the
5692 * rendering commands are discarded, otherwise they are executed as
5693 * normal. If the value of the predicate in buffer memory changes while
5694 * conditional rendering is active, the rendering commands may be
5695 * discarded in an implementation-dependent way. Some implementations
5696 * may latch the value of the predicate upon beginning conditional
5697 * rendering while others may read it before every rendering command."
5698 *
5699 * But, the AMD hardware treats the predicate as a 64-bit value which
5700 * means we need a workaround in the driver. Luckily, it's not required
5701 * to support if the value changes when predication is active.
5702 *
5703 * The workaround is as follows:
5704 * 1) allocate a 64-value in the upload BO and initialize it to 0
5705 * 2) copy the 32-bit predicate value to the upload BO
5706 * 3) use the new allocated VA address for predication
5707 *
5708 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5709 * in ME (+ sync PFP) instead of PFP.
5710 */
5711 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
5712
5713 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
5714
5715 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5716 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5717 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5718 COPY_DATA_WR_CONFIRM);
5719 radeon_emit(cs, va);
5720 radeon_emit(cs, va >> 32);
5721 radeon_emit(cs, new_va);
5722 radeon_emit(cs, new_va >> 32);
5723
5724 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
5725 radeon_emit(cs, 0);
5726
5727 /* Enable predication for this command buffer. */
5728 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
5729 cmd_buffer->state.predicating = true;
5730
5731 /* Store conditional rendering user info. */
5732 cmd_buffer->state.predication_type = draw_visible;
5733 cmd_buffer->state.predication_va = new_va;
5734 }
5735
5736 void radv_CmdEndConditionalRenderingEXT(
5737 VkCommandBuffer commandBuffer)
5738 {
5739 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5740
5741 /* Disable predication for this command buffer. */
5742 si_emit_set_predication_state(cmd_buffer, false, 0);
5743 cmd_buffer->state.predicating = false;
5744
5745 /* Reset conditional rendering user info. */
5746 cmd_buffer->state.predication_type = -1;
5747 cmd_buffer->state.predication_va = 0;
5748 }
5749
5750 /* VK_EXT_transform_feedback */
5751 void radv_CmdBindTransformFeedbackBuffersEXT(
5752 VkCommandBuffer commandBuffer,
5753 uint32_t firstBinding,
5754 uint32_t bindingCount,
5755 const VkBuffer* pBuffers,
5756 const VkDeviceSize* pOffsets,
5757 const VkDeviceSize* pSizes)
5758 {
5759 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5760 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5761 uint8_t enabled_mask = 0;
5762
5763 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
5764 for (uint32_t i = 0; i < bindingCount; i++) {
5765 uint32_t idx = firstBinding + i;
5766
5767 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
5768 sb[idx].offset = pOffsets[i];
5769 sb[idx].size = pSizes[i];
5770
5771 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
5772 sb[idx].buffer->bo);
5773
5774 enabled_mask |= 1 << idx;
5775 }
5776
5777 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
5778
5779 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
5780 }
5781
5782 static void
5783 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
5784 {
5785 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5786 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5787
5788 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
5789 radeon_emit(cs,
5790 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
5791 S_028B94_RAST_STREAM(0) |
5792 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
5793 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
5794 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
5795 radeon_emit(cs, so->hw_enabled_mask &
5796 so->enabled_stream_buffers_mask);
5797
5798 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5799 }
5800
5801 static void
5802 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
5803 {
5804 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5805 bool old_streamout_enabled = so->streamout_enabled;
5806 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
5807
5808 so->streamout_enabled = enable;
5809
5810 so->hw_enabled_mask = so->enabled_mask |
5811 (so->enabled_mask << 4) |
5812 (so->enabled_mask << 8) |
5813 (so->enabled_mask << 12);
5814
5815 if (!cmd_buffer->device->physical_device->use_ngg_streamout &&
5816 ((old_streamout_enabled != so->streamout_enabled) ||
5817 (old_hw_enabled_mask != so->hw_enabled_mask)))
5818 radv_emit_streamout_enable(cmd_buffer);
5819
5820 if (cmd_buffer->device->physical_device->use_ngg_streamout)
5821 cmd_buffer->gds_needed = true;
5822 }
5823
5824 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
5825 {
5826 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5827 unsigned reg_strmout_cntl;
5828
5829 /* The register is at different places on different ASICs. */
5830 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
5831 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
5832 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
5833 } else {
5834 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
5835 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
5836 }
5837
5838 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
5839 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
5840
5841 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
5842 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
5843 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
5844 radeon_emit(cs, 0);
5845 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5846 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5847 radeon_emit(cs, 4); /* poll interval */
5848 }
5849
5850 static void
5851 radv_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
5852 uint32_t firstCounterBuffer,
5853 uint32_t counterBufferCount,
5854 const VkBuffer *pCounterBuffers,
5855 const VkDeviceSize *pCounterBufferOffsets)
5856
5857 {
5858 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5859 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5860 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5861 uint32_t i;
5862
5863 radv_flush_vgt_streamout(cmd_buffer);
5864
5865 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5866 for_each_bit(i, so->enabled_mask) {
5867 int32_t counter_buffer_idx = i - firstCounterBuffer;
5868 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5869 counter_buffer_idx = -1;
5870
5871 /* AMD GCN binds streamout buffers as shader resources.
5872 * VGT only counts primitives and tells the shader through
5873 * SGPRs what to do.
5874 */
5875 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
5876 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
5877 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
5878
5879 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5880
5881 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5882 /* The array of counter buffers is optional. */
5883 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5884 uint64_t va = radv_buffer_get_va(buffer->bo);
5885
5886 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5887
5888 /* Append */
5889 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5890 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5891 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5892 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
5893 radeon_emit(cs, 0); /* unused */
5894 radeon_emit(cs, 0); /* unused */
5895 radeon_emit(cs, va); /* src address lo */
5896 radeon_emit(cs, va >> 32); /* src address hi */
5897
5898 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5899 } else {
5900 /* Start from the beginning. */
5901 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5902 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5903 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5904 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
5905 radeon_emit(cs, 0); /* unused */
5906 radeon_emit(cs, 0); /* unused */
5907 radeon_emit(cs, 0); /* unused */
5908 radeon_emit(cs, 0); /* unused */
5909 }
5910 }
5911
5912 radv_set_streamout_enable(cmd_buffer, true);
5913 }
5914
5915 static void
5916 gfx10_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
5917 uint32_t firstCounterBuffer,
5918 uint32_t counterBufferCount,
5919 const VkBuffer *pCounterBuffers,
5920 const VkDeviceSize *pCounterBufferOffsets)
5921 {
5922 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5923 unsigned last_target = util_last_bit(so->enabled_mask) - 1;
5924 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5925 uint32_t i;
5926
5927 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
5928 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5929
5930 for_each_bit(i, so->enabled_mask) {
5931 int32_t counter_buffer_idx = i - firstCounterBuffer;
5932 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5933 counter_buffer_idx = -1;
5934
5935 bool append = counter_buffer_idx >= 0 &&
5936 pCounterBuffers && pCounterBuffers[counter_buffer_idx];
5937 uint64_t va = 0;
5938
5939 if (append) {
5940 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5941
5942 va += radv_buffer_get_va(buffer->bo);
5943 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5944
5945 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5946 }
5947
5948 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
5949 radeon_emit(cs, S_411_SRC_SEL(append ? V_411_SRC_ADDR_TC_L2 : V_411_DATA) |
5950 S_411_DST_SEL(V_411_GDS) |
5951 S_411_CP_SYNC(i == last_target));
5952 radeon_emit(cs, va);
5953 radeon_emit(cs, va >> 32);
5954 radeon_emit(cs, 4 * i); /* destination in GDS */
5955 radeon_emit(cs, 0);
5956 radeon_emit(cs, S_414_BYTE_COUNT_GFX9(4) |
5957 S_414_DISABLE_WR_CONFIRM_GFX9(i != last_target));
5958 }
5959
5960 radv_set_streamout_enable(cmd_buffer, true);
5961 }
5962
5963 void radv_CmdBeginTransformFeedbackEXT(
5964 VkCommandBuffer commandBuffer,
5965 uint32_t firstCounterBuffer,
5966 uint32_t counterBufferCount,
5967 const VkBuffer* pCounterBuffers,
5968 const VkDeviceSize* pCounterBufferOffsets)
5969 {
5970 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5971
5972 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
5973 gfx10_emit_streamout_begin(cmd_buffer,
5974 firstCounterBuffer, counterBufferCount,
5975 pCounterBuffers, pCounterBufferOffsets);
5976 } else {
5977 radv_emit_streamout_begin(cmd_buffer,
5978 firstCounterBuffer, counterBufferCount,
5979 pCounterBuffers, pCounterBufferOffsets);
5980 }
5981 }
5982
5983 static void
5984 radv_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
5985 uint32_t firstCounterBuffer,
5986 uint32_t counterBufferCount,
5987 const VkBuffer *pCounterBuffers,
5988 const VkDeviceSize *pCounterBufferOffsets)
5989 {
5990 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5991 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5992 uint32_t i;
5993
5994 radv_flush_vgt_streamout(cmd_buffer);
5995
5996 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5997 for_each_bit(i, so->enabled_mask) {
5998 int32_t counter_buffer_idx = i - firstCounterBuffer;
5999 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6000 counter_buffer_idx = -1;
6001
6002 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6003 /* The array of counters buffer is optional. */
6004 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6005 uint64_t va = radv_buffer_get_va(buffer->bo);
6006
6007 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6008
6009 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6010 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6011 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6012 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
6013 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
6014 radeon_emit(cs, va); /* dst address lo */
6015 radeon_emit(cs, va >> 32); /* dst address hi */
6016 radeon_emit(cs, 0); /* unused */
6017 radeon_emit(cs, 0); /* unused */
6018
6019 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6020 }
6021
6022 /* Deactivate transform feedback by zeroing the buffer size.
6023 * The counters (primitives generated, primitives emitted) may
6024 * be enabled even if there is not buffer bound. This ensures
6025 * that the primitives-emitted query won't increment.
6026 */
6027 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
6028
6029 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6030 }
6031
6032 radv_set_streamout_enable(cmd_buffer, false);
6033 }
6034
6035 static void
6036 gfx10_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6037 uint32_t firstCounterBuffer,
6038 uint32_t counterBufferCount,
6039 const VkBuffer *pCounterBuffers,
6040 const VkDeviceSize *pCounterBufferOffsets)
6041 {
6042 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6043 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6044 uint32_t i;
6045
6046 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6047 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6048
6049 for_each_bit(i, so->enabled_mask) {
6050 int32_t counter_buffer_idx = i - firstCounterBuffer;
6051 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6052 counter_buffer_idx = -1;
6053
6054 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6055 /* The array of counters buffer is optional. */
6056 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6057 uint64_t va = radv_buffer_get_va(buffer->bo);
6058
6059 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6060
6061 si_cs_emit_write_event_eop(cs,
6062 cmd_buffer->device->physical_device->rad_info.chip_class,
6063 radv_cmd_buffer_uses_mec(cmd_buffer),
6064 V_028A90_PS_DONE, 0,
6065 EOP_DST_SEL_TC_L2,
6066 EOP_DATA_SEL_GDS,
6067 va, EOP_DATA_GDS(i, 1), 0);
6068 }
6069 }
6070
6071 radv_set_streamout_enable(cmd_buffer, false);
6072 }
6073
6074 void radv_CmdEndTransformFeedbackEXT(
6075 VkCommandBuffer commandBuffer,
6076 uint32_t firstCounterBuffer,
6077 uint32_t counterBufferCount,
6078 const VkBuffer* pCounterBuffers,
6079 const VkDeviceSize* pCounterBufferOffsets)
6080 {
6081 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6082
6083 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6084 gfx10_emit_streamout_end(cmd_buffer,
6085 firstCounterBuffer, counterBufferCount,
6086 pCounterBuffers, pCounterBufferOffsets);
6087 } else {
6088 radv_emit_streamout_end(cmd_buffer,
6089 firstCounterBuffer, counterBufferCount,
6090 pCounterBuffers, pCounterBufferOffsets);
6091 }
6092 }
6093
6094 void radv_CmdDrawIndirectByteCountEXT(
6095 VkCommandBuffer commandBuffer,
6096 uint32_t instanceCount,
6097 uint32_t firstInstance,
6098 VkBuffer _counterBuffer,
6099 VkDeviceSize counterBufferOffset,
6100 uint32_t counterOffset,
6101 uint32_t vertexStride)
6102 {
6103 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6104 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
6105 struct radv_draw_info info = {};
6106
6107 info.instance_count = instanceCount;
6108 info.first_instance = firstInstance;
6109 info.strmout_buffer = counterBuffer;
6110 info.strmout_buffer_offset = counterBufferOffset;
6111 info.stride = vertexStride;
6112
6113 radv_draw(cmd_buffer, &info);
6114 }
6115
6116 /* VK_AMD_buffer_marker */
6117 void radv_CmdWriteBufferMarkerAMD(
6118 VkCommandBuffer commandBuffer,
6119 VkPipelineStageFlagBits pipelineStage,
6120 VkBuffer dstBuffer,
6121 VkDeviceSize dstOffset,
6122 uint32_t marker)
6123 {
6124 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6125 RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
6126 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6127 uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
6128
6129 si_emit_cache_flush(cmd_buffer);
6130
6131 if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
6132 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
6133 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
6134 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
6135 COPY_DATA_WR_CONFIRM);
6136 radeon_emit(cs, marker);
6137 radeon_emit(cs, 0);
6138 radeon_emit(cs, va);
6139 radeon_emit(cs, va >> 32);
6140 } else {
6141 si_cs_emit_write_event_eop(cs,
6142 cmd_buffer->device->physical_device->rad_info.chip_class,
6143 radv_cmd_buffer_uses_mec(cmd_buffer),
6144 V_028A90_BOTTOM_OF_PIPE_TS, 0,
6145 EOP_DST_SEL_MEM,
6146 EOP_DATA_SEL_VALUE_32BIT,
6147 va, marker,
6148 cmd_buffer->gfx9_eop_bug_va);
6149 }
6150 }