2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
41 RADV_PREFETCH_VBO_DESCRIPTORS
= (1 << 0),
42 RADV_PREFETCH_VS
= (1 << 1),
43 RADV_PREFETCH_TCS
= (1 << 2),
44 RADV_PREFETCH_TES
= (1 << 3),
45 RADV_PREFETCH_GS
= (1 << 4),
46 RADV_PREFETCH_PS
= (1 << 5),
47 RADV_PREFETCH_SHADERS
= (RADV_PREFETCH_VS
|
54 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
55 struct radv_image
*image
,
56 VkImageLayout src_layout
,
57 VkImageLayout dst_layout
,
60 const VkImageSubresourceRange
*range
);
62 const struct radv_dynamic_state default_dynamic_state
= {
75 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
80 .stencil_compare_mask
= {
84 .stencil_write_mask
= {
88 .stencil_reference
= {
95 radv_bind_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
,
96 const struct radv_dynamic_state
*src
)
98 struct radv_dynamic_state
*dest
= &cmd_buffer
->state
.dynamic
;
99 uint32_t copy_mask
= src
->mask
;
100 uint32_t dest_mask
= 0;
102 /* Make sure to copy the number of viewports/scissors because they can
103 * only be specified at pipeline creation time.
105 dest
->viewport
.count
= src
->viewport
.count
;
106 dest
->scissor
.count
= src
->scissor
.count
;
107 dest
->discard_rectangle
.count
= src
->discard_rectangle
.count
;
109 if (copy_mask
& RADV_DYNAMIC_VIEWPORT
) {
110 if (memcmp(&dest
->viewport
.viewports
, &src
->viewport
.viewports
,
111 src
->viewport
.count
* sizeof(VkViewport
))) {
112 typed_memcpy(dest
->viewport
.viewports
,
113 src
->viewport
.viewports
,
114 src
->viewport
.count
);
115 dest_mask
|= RADV_DYNAMIC_VIEWPORT
;
119 if (copy_mask
& RADV_DYNAMIC_SCISSOR
) {
120 if (memcmp(&dest
->scissor
.scissors
, &src
->scissor
.scissors
,
121 src
->scissor
.count
* sizeof(VkRect2D
))) {
122 typed_memcpy(dest
->scissor
.scissors
,
123 src
->scissor
.scissors
, src
->scissor
.count
);
124 dest_mask
|= RADV_DYNAMIC_SCISSOR
;
128 if (copy_mask
& RADV_DYNAMIC_LINE_WIDTH
) {
129 if (dest
->line_width
!= src
->line_width
) {
130 dest
->line_width
= src
->line_width
;
131 dest_mask
|= RADV_DYNAMIC_LINE_WIDTH
;
135 if (copy_mask
& RADV_DYNAMIC_DEPTH_BIAS
) {
136 if (memcmp(&dest
->depth_bias
, &src
->depth_bias
,
137 sizeof(src
->depth_bias
))) {
138 dest
->depth_bias
= src
->depth_bias
;
139 dest_mask
|= RADV_DYNAMIC_DEPTH_BIAS
;
143 if (copy_mask
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
144 if (memcmp(&dest
->blend_constants
, &src
->blend_constants
,
145 sizeof(src
->blend_constants
))) {
146 typed_memcpy(dest
->blend_constants
,
147 src
->blend_constants
, 4);
148 dest_mask
|= RADV_DYNAMIC_BLEND_CONSTANTS
;
152 if (copy_mask
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
153 if (memcmp(&dest
->depth_bounds
, &src
->depth_bounds
,
154 sizeof(src
->depth_bounds
))) {
155 dest
->depth_bounds
= src
->depth_bounds
;
156 dest_mask
|= RADV_DYNAMIC_DEPTH_BOUNDS
;
160 if (copy_mask
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
161 if (memcmp(&dest
->stencil_compare_mask
,
162 &src
->stencil_compare_mask
,
163 sizeof(src
->stencil_compare_mask
))) {
164 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
165 dest_mask
|= RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
169 if (copy_mask
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
170 if (memcmp(&dest
->stencil_write_mask
, &src
->stencil_write_mask
,
171 sizeof(src
->stencil_write_mask
))) {
172 dest
->stencil_write_mask
= src
->stencil_write_mask
;
173 dest_mask
|= RADV_DYNAMIC_STENCIL_WRITE_MASK
;
177 if (copy_mask
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
178 if (memcmp(&dest
->stencil_reference
, &src
->stencil_reference
,
179 sizeof(src
->stencil_reference
))) {
180 dest
->stencil_reference
= src
->stencil_reference
;
181 dest_mask
|= RADV_DYNAMIC_STENCIL_REFERENCE
;
185 if (copy_mask
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
186 if (memcmp(&dest
->discard_rectangle
.rectangles
, &src
->discard_rectangle
.rectangles
,
187 src
->discard_rectangle
.count
* sizeof(VkRect2D
))) {
188 typed_memcpy(dest
->discard_rectangle
.rectangles
,
189 src
->discard_rectangle
.rectangles
,
190 src
->discard_rectangle
.count
);
191 dest_mask
|= RADV_DYNAMIC_DISCARD_RECTANGLE
;
195 cmd_buffer
->state
.dirty
|= dest_mask
;
199 radv_bind_streamout_state(struct radv_cmd_buffer
*cmd_buffer
,
200 struct radv_pipeline
*pipeline
)
202 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
203 struct radv_shader_info
*info
;
205 if (!pipeline
->streamout_shader
)
208 info
= &pipeline
->streamout_shader
->info
.info
;
209 for (int i
= 0; i
< MAX_SO_BUFFERS
; i
++)
210 so
->stride_in_dw
[i
] = info
->so
.strides
[i
];
212 so
->enabled_stream_buffers_mask
= info
->so
.enabled_stream_buffers_mask
;
215 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
)
217 return cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
218 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
;
221 enum ring_type
radv_queue_family_to_ring(int f
) {
223 case RADV_QUEUE_GENERAL
:
225 case RADV_QUEUE_COMPUTE
:
227 case RADV_QUEUE_TRANSFER
:
230 unreachable("Unknown queue family");
234 static VkResult
radv_create_cmd_buffer(
235 struct radv_device
* device
,
236 struct radv_cmd_pool
* pool
,
237 VkCommandBufferLevel level
,
238 VkCommandBuffer
* pCommandBuffer
)
240 struct radv_cmd_buffer
*cmd_buffer
;
242 cmd_buffer
= vk_zalloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
243 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
244 if (cmd_buffer
== NULL
)
245 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
247 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
248 cmd_buffer
->device
= device
;
249 cmd_buffer
->pool
= pool
;
250 cmd_buffer
->level
= level
;
253 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
254 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
257 /* Init the pool_link so we can safely call list_del when we destroy
260 list_inithead(&cmd_buffer
->pool_link
);
261 cmd_buffer
->queue_family_index
= RADV_QUEUE_GENERAL
;
264 ring
= radv_queue_family_to_ring(cmd_buffer
->queue_family_index
);
266 cmd_buffer
->cs
= device
->ws
->cs_create(device
->ws
, ring
);
267 if (!cmd_buffer
->cs
) {
268 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
269 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
272 *pCommandBuffer
= radv_cmd_buffer_to_handle(cmd_buffer
);
274 list_inithead(&cmd_buffer
->upload
.list
);
280 radv_cmd_buffer_destroy(struct radv_cmd_buffer
*cmd_buffer
)
282 list_del(&cmd_buffer
->pool_link
);
284 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
285 &cmd_buffer
->upload
.list
, list
) {
286 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
291 if (cmd_buffer
->upload
.upload_bo
)
292 cmd_buffer
->device
->ws
->buffer_destroy(cmd_buffer
->upload
.upload_bo
);
293 cmd_buffer
->device
->ws
->cs_destroy(cmd_buffer
->cs
);
295 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++)
296 free(cmd_buffer
->descriptors
[i
].push_set
.set
.mapped_ptr
);
298 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
302 radv_reset_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
)
305 cmd_buffer
->device
->ws
->cs_reset(cmd_buffer
->cs
);
307 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
308 &cmd_buffer
->upload
.list
, list
) {
309 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
314 cmd_buffer
->push_constant_stages
= 0;
315 cmd_buffer
->scratch_size_needed
= 0;
316 cmd_buffer
->compute_scratch_size_needed
= 0;
317 cmd_buffer
->esgs_ring_size_needed
= 0;
318 cmd_buffer
->gsvs_ring_size_needed
= 0;
319 cmd_buffer
->tess_rings_needed
= false;
320 cmd_buffer
->sample_positions_needed
= false;
322 if (cmd_buffer
->upload
.upload_bo
)
323 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
324 cmd_buffer
->upload
.upload_bo
);
325 cmd_buffer
->upload
.offset
= 0;
327 cmd_buffer
->record_result
= VK_SUCCESS
;
329 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++) {
330 cmd_buffer
->descriptors
[i
].dirty
= 0;
331 cmd_buffer
->descriptors
[i
].valid
= 0;
332 cmd_buffer
->descriptors
[i
].push_dirty
= false;
335 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
336 unsigned num_db
= cmd_buffer
->device
->physical_device
->rad_info
.num_render_backends
;
337 unsigned eop_bug_offset
;
340 radv_cmd_buffer_upload_alloc(cmd_buffer
, 8, 0,
341 &cmd_buffer
->gfx9_fence_offset
,
343 cmd_buffer
->gfx9_fence_bo
= cmd_buffer
->upload
.upload_bo
;
345 /* Allocate a buffer for the EOP bug on GFX9. */
346 radv_cmd_buffer_upload_alloc(cmd_buffer
, 16 * num_db
, 0,
347 &eop_bug_offset
, &fence_ptr
);
348 cmd_buffer
->gfx9_eop_bug_va
=
349 radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
350 cmd_buffer
->gfx9_eop_bug_va
+= eop_bug_offset
;
353 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_INITIAL
;
355 return cmd_buffer
->record_result
;
359 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer
*cmd_buffer
,
363 struct radeon_winsys_bo
*bo
;
364 struct radv_cmd_buffer_upload
*upload
;
365 struct radv_device
*device
= cmd_buffer
->device
;
367 new_size
= MAX2(min_needed
, 16 * 1024);
368 new_size
= MAX2(new_size
, 2 * cmd_buffer
->upload
.size
);
370 bo
= device
->ws
->buffer_create(device
->ws
,
373 RADEON_FLAG_CPU_ACCESS
|
374 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
378 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
382 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
, bo
);
383 if (cmd_buffer
->upload
.upload_bo
) {
384 upload
= malloc(sizeof(*upload
));
387 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
388 device
->ws
->buffer_destroy(bo
);
392 memcpy(upload
, &cmd_buffer
->upload
, sizeof(*upload
));
393 list_add(&upload
->list
, &cmd_buffer
->upload
.list
);
396 cmd_buffer
->upload
.upload_bo
= bo
;
397 cmd_buffer
->upload
.size
= new_size
;
398 cmd_buffer
->upload
.offset
= 0;
399 cmd_buffer
->upload
.map
= device
->ws
->buffer_map(cmd_buffer
->upload
.upload_bo
);
401 if (!cmd_buffer
->upload
.map
) {
402 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
410 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
413 unsigned *out_offset
,
416 uint64_t offset
= align(cmd_buffer
->upload
.offset
, alignment
);
417 if (offset
+ size
> cmd_buffer
->upload
.size
) {
418 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer
, size
))
423 *out_offset
= offset
;
424 *ptr
= cmd_buffer
->upload
.map
+ offset
;
426 cmd_buffer
->upload
.offset
= offset
+ size
;
431 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
432 unsigned size
, unsigned alignment
,
433 const void *data
, unsigned *out_offset
)
437 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
, alignment
,
438 out_offset
, (void **)&ptr
))
442 memcpy(ptr
, data
, size
);
448 radv_emit_write_data_packet(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
449 unsigned count
, const uint32_t *data
)
451 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
453 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 4 + count
);
455 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
456 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
457 S_370_WR_CONFIRM(1) |
458 S_370_ENGINE_SEL(V_370_ME
));
460 radeon_emit(cs
, va
>> 32);
461 radeon_emit_array(cs
, data
, count
);
464 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
)
466 struct radv_device
*device
= cmd_buffer
->device
;
467 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
470 va
= radv_buffer_get_va(device
->trace_bo
);
471 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
)
474 ++cmd_buffer
->state
.trace_id
;
475 radv_emit_write_data_packet(cmd_buffer
, va
, 1,
476 &cmd_buffer
->state
.trace_id
);
478 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 2);
480 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
481 radeon_emit(cs
, AC_ENCODE_TRACE_POINT(cmd_buffer
->state
.trace_id
));
485 radv_cmd_buffer_after_draw(struct radv_cmd_buffer
*cmd_buffer
,
486 enum radv_cmd_flush_bits flags
)
488 if (cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_SYNC_SHADERS
) {
489 uint32_t *ptr
= NULL
;
492 assert(flags
& (RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
493 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
));
495 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
496 va
= radv_buffer_get_va(cmd_buffer
->gfx9_fence_bo
) +
497 cmd_buffer
->gfx9_fence_offset
;
498 ptr
= &cmd_buffer
->gfx9_fence_idx
;
501 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 4);
503 /* Force wait for graphics or compute engines to be idle. */
504 si_cs_emit_cache_flush(cmd_buffer
->cs
,
505 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
507 radv_cmd_buffer_uses_mec(cmd_buffer
),
508 flags
, cmd_buffer
->gfx9_eop_bug_va
);
511 if (unlikely(cmd_buffer
->device
->trace_bo
))
512 radv_cmd_buffer_trace_emit(cmd_buffer
);
516 radv_save_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
517 struct radv_pipeline
*pipeline
, enum ring_type ring
)
519 struct radv_device
*device
= cmd_buffer
->device
;
523 va
= radv_buffer_get_va(device
->trace_bo
);
533 assert(!"invalid ring type");
536 data
[0] = (uintptr_t)pipeline
;
537 data
[1] = (uintptr_t)pipeline
>> 32;
539 radv_emit_write_data_packet(cmd_buffer
, va
, 2, data
);
542 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
543 VkPipelineBindPoint bind_point
,
544 struct radv_descriptor_set
*set
,
547 struct radv_descriptor_state
*descriptors_state
=
548 radv_get_descriptors_state(cmd_buffer
, bind_point
);
550 descriptors_state
->sets
[idx
] = set
;
552 descriptors_state
->valid
|= (1u << idx
); /* active descriptors */
553 descriptors_state
->dirty
|= (1u << idx
);
557 radv_save_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
558 VkPipelineBindPoint bind_point
)
560 struct radv_descriptor_state
*descriptors_state
=
561 radv_get_descriptors_state(cmd_buffer
, bind_point
);
562 struct radv_device
*device
= cmd_buffer
->device
;
563 uint32_t data
[MAX_SETS
* 2] = {};
566 va
= radv_buffer_get_va(device
->trace_bo
) + 24;
568 for_each_bit(i
, descriptors_state
->valid
) {
569 struct radv_descriptor_set
*set
= descriptors_state
->sets
[i
];
570 data
[i
* 2] = (uintptr_t)set
;
571 data
[i
* 2 + 1] = (uintptr_t)set
>> 32;
574 radv_emit_write_data_packet(cmd_buffer
, va
, MAX_SETS
* 2, data
);
577 struct radv_userdata_info
*
578 radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
579 gl_shader_stage stage
,
582 struct radv_shader_variant
*shader
= radv_get_shader(pipeline
, stage
);
583 return &shader
->info
.user_sgprs_locs
.shader_data
[idx
];
587 radv_emit_userdata_address(struct radv_cmd_buffer
*cmd_buffer
,
588 struct radv_pipeline
*pipeline
,
589 gl_shader_stage stage
,
590 int idx
, uint64_t va
)
592 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
593 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
594 if (loc
->sgpr_idx
== -1)
597 assert(loc
->num_sgprs
== 1);
598 assert(!loc
->indirect
);
600 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
601 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
605 radv_emit_descriptor_pointers(struct radv_cmd_buffer
*cmd_buffer
,
606 struct radv_pipeline
*pipeline
,
607 struct radv_descriptor_state
*descriptors_state
,
608 gl_shader_stage stage
)
610 struct radv_device
*device
= cmd_buffer
->device
;
611 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
612 uint32_t sh_base
= pipeline
->user_data_0
[stage
];
613 struct radv_userdata_locations
*locs
=
614 &pipeline
->shaders
[stage
]->info
.user_sgprs_locs
;
615 unsigned mask
= locs
->descriptor_sets_enabled
;
617 mask
&= descriptors_state
->dirty
& descriptors_state
->valid
;
622 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
624 struct radv_userdata_info
*loc
= &locs
->descriptor_sets
[start
];
625 unsigned sh_offset
= sh_base
+ loc
->sgpr_idx
* 4;
627 radv_emit_shader_pointer_head(cs
, sh_offset
, count
, true);
628 for (int i
= 0; i
< count
; i
++) {
629 struct radv_descriptor_set
*set
=
630 descriptors_state
->sets
[start
+ i
];
632 radv_emit_shader_pointer_body(device
, cs
, set
->va
, true);
638 radv_update_multisample_state(struct radv_cmd_buffer
*cmd_buffer
,
639 struct radv_pipeline
*pipeline
)
641 int num_samples
= pipeline
->graphics
.ms
.num_samples
;
642 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
643 struct radv_pipeline
*old_pipeline
= cmd_buffer
->state
.emitted_pipeline
;
645 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.needs_sample_positions
)
646 cmd_buffer
->sample_positions_needed
= true;
648 if (old_pipeline
&& num_samples
== old_pipeline
->graphics
.ms
.num_samples
)
651 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028BDC_PA_SC_LINE_CNTL
, 2);
652 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_line_cntl
);
653 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_config
);
655 radeon_set_context_reg(cmd_buffer
->cs
, R_028A48_PA_SC_MODE_CNTL_0
, ms
->pa_sc_mode_cntl_0
);
657 radv_cayman_emit_msaa_sample_locs(cmd_buffer
->cs
, num_samples
);
659 /* GFX9: Flush DFSM when the AA mode changes. */
660 if (cmd_buffer
->device
->dfsm_allowed
) {
661 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
662 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
665 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
669 radv_emit_shader_prefetch(struct radv_cmd_buffer
*cmd_buffer
,
670 struct radv_shader_variant
*shader
)
677 va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
679 si_cp_dma_prefetch(cmd_buffer
, va
, shader
->code_size
);
683 radv_emit_prefetch_L2(struct radv_cmd_buffer
*cmd_buffer
,
684 struct radv_pipeline
*pipeline
,
685 bool vertex_stage_only
)
687 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
688 uint32_t mask
= state
->prefetch_L2_mask
;
690 if (vertex_stage_only
) {
691 /* Fast prefetch path for starting draws as soon as possible.
693 mask
= state
->prefetch_L2_mask
& (RADV_PREFETCH_VS
|
694 RADV_PREFETCH_VBO_DESCRIPTORS
);
697 if (mask
& RADV_PREFETCH_VS
)
698 radv_emit_shader_prefetch(cmd_buffer
,
699 pipeline
->shaders
[MESA_SHADER_VERTEX
]);
701 if (mask
& RADV_PREFETCH_VBO_DESCRIPTORS
)
702 si_cp_dma_prefetch(cmd_buffer
, state
->vb_va
, state
->vb_size
);
704 if (mask
& RADV_PREFETCH_TCS
)
705 radv_emit_shader_prefetch(cmd_buffer
,
706 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]);
708 if (mask
& RADV_PREFETCH_TES
)
709 radv_emit_shader_prefetch(cmd_buffer
,
710 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]);
712 if (mask
& RADV_PREFETCH_GS
) {
713 radv_emit_shader_prefetch(cmd_buffer
,
714 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]);
715 radv_emit_shader_prefetch(cmd_buffer
, pipeline
->gs_copy_shader
);
718 if (mask
& RADV_PREFETCH_PS
)
719 radv_emit_shader_prefetch(cmd_buffer
,
720 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
722 state
->prefetch_L2_mask
&= ~mask
;
726 radv_emit_rbplus_state(struct radv_cmd_buffer
*cmd_buffer
)
728 if (!cmd_buffer
->device
->physical_device
->rbplus_allowed
)
731 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
732 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
733 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
735 unsigned sx_ps_downconvert
= 0;
736 unsigned sx_blend_opt_epsilon
= 0;
737 unsigned sx_blend_opt_control
= 0;
739 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
740 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
741 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
742 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
746 int idx
= subpass
->color_attachments
[i
].attachment
;
747 struct radv_color_buffer_info
*cb
= &framebuffer
->attachments
[idx
].cb
;
749 unsigned format
= G_028C70_FORMAT(cb
->cb_color_info
);
750 unsigned swap
= G_028C70_COMP_SWAP(cb
->cb_color_info
);
751 uint32_t spi_format
= (pipeline
->graphics
.col_format
>> (i
* 4)) & 0xf;
752 uint32_t colormask
= (pipeline
->graphics
.cb_target_mask
>> (i
* 4)) & 0xf;
754 bool has_alpha
, has_rgb
;
756 /* Set if RGB and A are present. */
757 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(cb
->cb_color_attrib
);
759 if (format
== V_028C70_COLOR_8
||
760 format
== V_028C70_COLOR_16
||
761 format
== V_028C70_COLOR_32
)
762 has_rgb
= !has_alpha
;
766 /* Check the colormask and export format. */
767 if (!(colormask
& 0x7))
769 if (!(colormask
& 0x8))
772 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
777 /* Disable value checking for disabled channels. */
779 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
781 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
783 /* Enable down-conversion for 32bpp and smaller formats. */
785 case V_028C70_COLOR_8
:
786 case V_028C70_COLOR_8_8
:
787 case V_028C70_COLOR_8_8_8_8
:
788 /* For 1 and 2-channel formats, use the superset thereof. */
789 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
790 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
791 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
792 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
793 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
797 case V_028C70_COLOR_5_6_5
:
798 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
799 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
800 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
804 case V_028C70_COLOR_1_5_5_5
:
805 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
806 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
807 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
811 case V_028C70_COLOR_4_4_4_4
:
812 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
813 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
814 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
818 case V_028C70_COLOR_32
:
819 if (swap
== V_028C70_SWAP_STD
&&
820 spi_format
== V_028714_SPI_SHADER_32_R
)
821 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
822 else if (swap
== V_028C70_SWAP_ALT_REV
&&
823 spi_format
== V_028714_SPI_SHADER_32_AR
)
824 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
827 case V_028C70_COLOR_16
:
828 case V_028C70_COLOR_16_16
:
829 /* For 1-channel formats, use the superset thereof. */
830 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
831 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
832 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
833 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
834 if (swap
== V_028C70_SWAP_STD
||
835 swap
== V_028C70_SWAP_STD_REV
)
836 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
838 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
842 case V_028C70_COLOR_10_11_11
:
843 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
844 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
845 sx_blend_opt_epsilon
|= V_028758_11BIT_FORMAT
<< (i
* 4);
849 case V_028C70_COLOR_2_10_10_10
:
850 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
851 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
852 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
858 for (unsigned i
= subpass
->color_count
; i
< 8; ++i
) {
859 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
860 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
862 /* TODO: avoid redundantly setting context registers */
863 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
864 radeon_emit(cmd_buffer
->cs
, sx_ps_downconvert
);
865 radeon_emit(cmd_buffer
->cs
, sx_blend_opt_epsilon
);
866 radeon_emit(cmd_buffer
->cs
, sx_blend_opt_control
);
868 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
872 radv_emit_graphics_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
874 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
876 if (!pipeline
|| cmd_buffer
->state
.emitted_pipeline
== pipeline
)
879 radv_update_multisample_state(cmd_buffer
, pipeline
);
881 cmd_buffer
->scratch_size_needed
=
882 MAX2(cmd_buffer
->scratch_size_needed
,
883 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
885 if (!cmd_buffer
->state
.emitted_pipeline
||
886 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
!=
887 pipeline
->graphics
.can_use_guardband
)
888 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
890 radeon_emit_array(cmd_buffer
->cs
, pipeline
->cs
.buf
, pipeline
->cs
.cdw
);
892 if (!cmd_buffer
->state
.emitted_pipeline
||
893 cmd_buffer
->state
.emitted_pipeline
->ctx_cs
.cdw
!= pipeline
->ctx_cs
.cdw
||
894 cmd_buffer
->state
.emitted_pipeline
->ctx_cs_hash
!= pipeline
->ctx_cs_hash
||
895 memcmp(cmd_buffer
->state
.emitted_pipeline
->ctx_cs
.buf
,
896 pipeline
->ctx_cs
.buf
, pipeline
->ctx_cs
.cdw
* 4)) {
897 radeon_emit_array(cmd_buffer
->cs
, pipeline
->ctx_cs
.buf
, pipeline
->ctx_cs
.cdw
);
898 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
901 for (unsigned i
= 0; i
< MESA_SHADER_COMPUTE
; i
++) {
902 if (!pipeline
->shaders
[i
])
905 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
906 pipeline
->shaders
[i
]->bo
);
909 if (radv_pipeline_has_gs(pipeline
))
910 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
911 pipeline
->gs_copy_shader
->bo
);
913 if (unlikely(cmd_buffer
->device
->trace_bo
))
914 radv_save_pipeline(cmd_buffer
, pipeline
, RING_GFX
);
916 cmd_buffer
->state
.emitted_pipeline
= pipeline
;
918 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_PIPELINE
;
922 radv_emit_viewport(struct radv_cmd_buffer
*cmd_buffer
)
924 si_write_viewport(cmd_buffer
->cs
, 0, cmd_buffer
->state
.dynamic
.viewport
.count
,
925 cmd_buffer
->state
.dynamic
.viewport
.viewports
);
929 radv_emit_scissor(struct radv_cmd_buffer
*cmd_buffer
)
931 uint32_t count
= cmd_buffer
->state
.dynamic
.scissor
.count
;
933 si_write_scissors(cmd_buffer
->cs
, 0, count
,
934 cmd_buffer
->state
.dynamic
.scissor
.scissors
,
935 cmd_buffer
->state
.dynamic
.viewport
.viewports
,
936 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
);
938 cmd_buffer
->state
.context_roll_without_scissor_emitted
= false;
942 radv_emit_discard_rectangle(struct radv_cmd_buffer
*cmd_buffer
)
944 if (!cmd_buffer
->state
.dynamic
.discard_rectangle
.count
)
947 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028210_PA_SC_CLIPRECT_0_TL
,
948 cmd_buffer
->state
.dynamic
.discard_rectangle
.count
* 2);
949 for (unsigned i
= 0; i
< cmd_buffer
->state
.dynamic
.discard_rectangle
.count
; ++i
) {
950 VkRect2D rect
= cmd_buffer
->state
.dynamic
.discard_rectangle
.rectangles
[i
];
951 radeon_emit(cmd_buffer
->cs
, S_028210_TL_X(rect
.offset
.x
) | S_028210_TL_Y(rect
.offset
.y
));
952 radeon_emit(cmd_buffer
->cs
, S_028214_BR_X(rect
.offset
.x
+ rect
.extent
.width
) |
953 S_028214_BR_Y(rect
.offset
.y
+ rect
.extent
.height
));
958 radv_emit_line_width(struct radv_cmd_buffer
*cmd_buffer
)
960 unsigned width
= cmd_buffer
->state
.dynamic
.line_width
* 8;
962 radeon_set_context_reg(cmd_buffer
->cs
, R_028A08_PA_SU_LINE_CNTL
,
963 S_028A08_WIDTH(CLAMP(width
, 0, 0xFFF)));
967 radv_emit_blend_constants(struct radv_cmd_buffer
*cmd_buffer
)
969 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
971 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028414_CB_BLEND_RED
, 4);
972 radeon_emit_array(cmd_buffer
->cs
, (uint32_t *)d
->blend_constants
, 4);
976 radv_emit_stencil(struct radv_cmd_buffer
*cmd_buffer
)
978 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
980 radeon_set_context_reg_seq(cmd_buffer
->cs
,
981 R_028430_DB_STENCILREFMASK
, 2);
982 radeon_emit(cmd_buffer
->cs
,
983 S_028430_STENCILTESTVAL(d
->stencil_reference
.front
) |
984 S_028430_STENCILMASK(d
->stencil_compare_mask
.front
) |
985 S_028430_STENCILWRITEMASK(d
->stencil_write_mask
.front
) |
986 S_028430_STENCILOPVAL(1));
987 radeon_emit(cmd_buffer
->cs
,
988 S_028434_STENCILTESTVAL_BF(d
->stencil_reference
.back
) |
989 S_028434_STENCILMASK_BF(d
->stencil_compare_mask
.back
) |
990 S_028434_STENCILWRITEMASK_BF(d
->stencil_write_mask
.back
) |
991 S_028434_STENCILOPVAL_BF(1));
995 radv_emit_depth_bounds(struct radv_cmd_buffer
*cmd_buffer
)
997 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
999 radeon_set_context_reg(cmd_buffer
->cs
, R_028020_DB_DEPTH_BOUNDS_MIN
,
1000 fui(d
->depth_bounds
.min
));
1001 radeon_set_context_reg(cmd_buffer
->cs
, R_028024_DB_DEPTH_BOUNDS_MAX
,
1002 fui(d
->depth_bounds
.max
));
1006 radv_emit_depth_bias(struct radv_cmd_buffer
*cmd_buffer
)
1008 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1009 unsigned slope
= fui(d
->depth_bias
.slope
* 16.0f
);
1010 unsigned bias
= fui(d
->depth_bias
.bias
* cmd_buffer
->state
.offset_scale
);
1013 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1014 R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, 5);
1015 radeon_emit(cmd_buffer
->cs
, fui(d
->depth_bias
.clamp
)); /* CLAMP */
1016 radeon_emit(cmd_buffer
->cs
, slope
); /* FRONT SCALE */
1017 radeon_emit(cmd_buffer
->cs
, bias
); /* FRONT OFFSET */
1018 radeon_emit(cmd_buffer
->cs
, slope
); /* BACK SCALE */
1019 radeon_emit(cmd_buffer
->cs
, bias
); /* BACK OFFSET */
1023 radv_emit_fb_color_state(struct radv_cmd_buffer
*cmd_buffer
,
1025 struct radv_attachment_info
*att
,
1026 struct radv_image
*image
,
1027 VkImageLayout layout
)
1029 bool is_vi
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= VI
;
1030 struct radv_color_buffer_info
*cb
= &att
->cb
;
1031 uint32_t cb_color_info
= cb
->cb_color_info
;
1033 if (!radv_layout_dcc_compressed(image
, layout
,
1034 radv_image_queue_family_mask(image
,
1035 cmd_buffer
->queue_family_index
,
1036 cmd_buffer
->queue_family_index
))) {
1037 cb_color_info
&= C_028C70_DCC_ENABLE
;
1040 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1041 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1042 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1043 radeon_emit(cmd_buffer
->cs
, S_028C64_BASE_256B(cb
->cb_color_base
>> 32));
1044 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib2
);
1045 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1046 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1047 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1048 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1049 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1050 radeon_emit(cmd_buffer
->cs
, S_028C80_BASE_256B(cb
->cb_color_cmask
>> 32));
1051 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1052 radeon_emit(cmd_buffer
->cs
, S_028C88_BASE_256B(cb
->cb_color_fmask
>> 32));
1054 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, 2);
1055 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
);
1056 radeon_emit(cmd_buffer
->cs
, S_028C98_BASE_256B(cb
->cb_dcc_base
>> 32));
1058 radeon_set_context_reg(cmd_buffer
->cs
, R_0287A0_CB_MRT0_EPITCH
+ index
* 4,
1059 S_0287A0_EPITCH(att
->attachment
->image
->surface
.u
.gfx9
.surf
.epitch
));
1061 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1062 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1063 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_pitch
);
1064 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_slice
);
1065 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1066 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1067 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1068 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1069 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1070 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask_slice
);
1071 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1072 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask_slice
);
1074 if (is_vi
) { /* DCC BASE */
1075 radeon_set_context_reg(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, cb
->cb_dcc_base
);
1079 if (radv_image_has_dcc(image
)) {
1080 /* Drawing with DCC enabled also compresses colorbuffers. */
1081 radv_update_dcc_metadata(cmd_buffer
, image
, true);
1086 radv_update_zrange_precision(struct radv_cmd_buffer
*cmd_buffer
,
1087 struct radv_ds_buffer_info
*ds
,
1088 struct radv_image
*image
, VkImageLayout layout
,
1089 bool requires_cond_exec
)
1091 uint32_t db_z_info
= ds
->db_z_info
;
1092 uint32_t db_z_info_reg
;
1094 if (!radv_image_is_tc_compat_htile(image
))
1097 if (!radv_layout_has_htile(image
, layout
,
1098 radv_image_queue_family_mask(image
,
1099 cmd_buffer
->queue_family_index
,
1100 cmd_buffer
->queue_family_index
))) {
1101 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1104 db_z_info
&= C_028040_ZRANGE_PRECISION
;
1106 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1107 db_z_info_reg
= R_028038_DB_Z_INFO
;
1109 db_z_info_reg
= R_028040_DB_Z_INFO
;
1112 /* When we don't know the last fast clear value we need to emit a
1113 * conditional packet that will eventually skip the following
1114 * SET_CONTEXT_REG packet.
1116 if (requires_cond_exec
) {
1117 uint64_t va
= radv_buffer_get_va(image
->bo
);
1118 va
+= image
->offset
+ image
->tc_compat_zrange_offset
;
1120 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COND_EXEC
, 3, 0));
1121 radeon_emit(cmd_buffer
->cs
, va
);
1122 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1123 radeon_emit(cmd_buffer
->cs
, 0);
1124 radeon_emit(cmd_buffer
->cs
, 3); /* SET_CONTEXT_REG size */
1127 radeon_set_context_reg(cmd_buffer
->cs
, db_z_info_reg
, db_z_info
);
1131 radv_emit_fb_ds_state(struct radv_cmd_buffer
*cmd_buffer
,
1132 struct radv_ds_buffer_info
*ds
,
1133 struct radv_image
*image
,
1134 VkImageLayout layout
)
1136 uint32_t db_z_info
= ds
->db_z_info
;
1137 uint32_t db_stencil_info
= ds
->db_stencil_info
;
1139 if (!radv_layout_has_htile(image
, layout
,
1140 radv_image_queue_family_mask(image
,
1141 cmd_buffer
->queue_family_index
,
1142 cmd_buffer
->queue_family_index
))) {
1143 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1144 db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
1147 radeon_set_context_reg(cmd_buffer
->cs
, R_028008_DB_DEPTH_VIEW
, ds
->db_depth_view
);
1148 radeon_set_context_reg(cmd_buffer
->cs
, R_028ABC_DB_HTILE_SURFACE
, ds
->db_htile_surface
);
1151 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1152 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
1153 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
);
1154 radeon_emit(cmd_buffer
->cs
, S_028018_BASE_HI(ds
->db_htile_data_base
>> 32));
1155 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
);
1157 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 10);
1158 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* DB_Z_INFO */
1159 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* DB_STENCIL_INFO */
1160 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* DB_Z_READ_BASE */
1161 radeon_emit(cmd_buffer
->cs
, S_028044_BASE_HI(ds
->db_z_read_base
>> 32)); /* DB_Z_READ_BASE_HI */
1162 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* DB_STENCIL_READ_BASE */
1163 radeon_emit(cmd_buffer
->cs
, S_02804C_BASE_HI(ds
->db_stencil_read_base
>> 32)); /* DB_STENCIL_READ_BASE_HI */
1164 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* DB_Z_WRITE_BASE */
1165 radeon_emit(cmd_buffer
->cs
, S_028054_BASE_HI(ds
->db_z_write_base
>> 32)); /* DB_Z_WRITE_BASE_HI */
1166 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* DB_STENCIL_WRITE_BASE */
1167 radeon_emit(cmd_buffer
->cs
, S_02805C_BASE_HI(ds
->db_stencil_write_base
>> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1169 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028068_DB_Z_INFO2
, 2);
1170 radeon_emit(cmd_buffer
->cs
, ds
->db_z_info2
);
1171 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_info2
);
1173 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
1175 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 9);
1176 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_info
); /* R_02803C_DB_DEPTH_INFO */
1177 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* R_028040_DB_Z_INFO */
1178 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
1179 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* R_028048_DB_Z_READ_BASE */
1180 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* R_02804C_DB_STENCIL_READ_BASE */
1181 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* R_028050_DB_Z_WRITE_BASE */
1182 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
1183 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
1184 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
1188 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1189 radv_update_zrange_precision(cmd_buffer
, ds
, image
, layout
, true);
1191 radeon_set_context_reg(cmd_buffer
->cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1192 ds
->pa_su_poly_offset_db_fmt_cntl
);
1196 * Update the fast clear depth/stencil values if the image is bound as a
1197 * depth/stencil buffer.
1200 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer
*cmd_buffer
,
1201 struct radv_image
*image
,
1202 VkClearDepthStencilValue ds_clear_value
,
1203 VkImageAspectFlags aspects
)
1205 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1206 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1207 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1208 struct radv_attachment_info
*att
;
1211 if (!framebuffer
|| !subpass
)
1214 att_idx
= subpass
->depth_stencil_attachment
.attachment
;
1215 if (att_idx
== VK_ATTACHMENT_UNUSED
)
1218 att
= &framebuffer
->attachments
[att_idx
];
1219 if (att
->attachment
->image
!= image
)
1222 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
1223 radeon_emit(cs
, ds_clear_value
.stencil
);
1224 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1226 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1227 * only needed when clearing Z to 0.0.
1229 if ((aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
1230 ds_clear_value
.depth
== 0.0) {
1231 VkImageLayout layout
= subpass
->depth_stencil_attachment
.layout
;
1233 radv_update_zrange_precision(cmd_buffer
, &att
->ds
, image
,
1237 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1241 * Set the clear depth/stencil values to the image's metadata.
1244 radv_set_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1245 struct radv_image
*image
,
1246 VkClearDepthStencilValue ds_clear_value
,
1247 VkImageAspectFlags aspects
)
1249 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1250 uint64_t va
= radv_buffer_get_va(image
->bo
);
1251 unsigned reg_offset
= 0, reg_count
= 0;
1253 va
+= image
->offset
+ image
->clear_value_offset
;
1255 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1261 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1264 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + reg_count
, 0));
1265 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1266 S_370_WR_CONFIRM(1) |
1267 S_370_ENGINE_SEL(V_370_PFP
));
1268 radeon_emit(cs
, va
);
1269 radeon_emit(cs
, va
>> 32);
1270 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)
1271 radeon_emit(cs
, ds_clear_value
.stencil
);
1272 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1273 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1277 * Update the TC-compat metadata value for this image.
1280 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1281 struct radv_image
*image
,
1284 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1285 uint64_t va
= radv_buffer_get_va(image
->bo
);
1286 va
+= image
->offset
+ image
->tc_compat_zrange_offset
;
1288 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
1289 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1290 S_370_WR_CONFIRM(1) |
1291 S_370_ENGINE_SEL(V_370_PFP
));
1292 radeon_emit(cs
, va
);
1293 radeon_emit(cs
, va
>> 32);
1294 radeon_emit(cs
, value
);
1298 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1299 struct radv_image
*image
,
1300 VkClearDepthStencilValue ds_clear_value
)
1302 uint64_t va
= radv_buffer_get_va(image
->bo
);
1303 va
+= image
->offset
+ image
->tc_compat_zrange_offset
;
1306 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1307 * depth clear value is 0.0f.
1309 cond_val
= ds_clear_value
.depth
== 0.0f
? UINT_MAX
: 0;
1311 radv_set_tc_compat_zrange_metadata(cmd_buffer
, image
, cond_val
);
1315 * Update the clear depth/stencil values for this image.
1318 radv_update_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1319 struct radv_image
*image
,
1320 VkClearDepthStencilValue ds_clear_value
,
1321 VkImageAspectFlags aspects
)
1323 assert(radv_image_has_htile(image
));
1325 radv_set_ds_clear_metadata(cmd_buffer
, image
, ds_clear_value
, aspects
);
1327 if (radv_image_is_tc_compat_htile(image
) &&
1328 (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
1329 radv_update_tc_compat_zrange_metadata(cmd_buffer
, image
,
1333 radv_update_bound_fast_clear_ds(cmd_buffer
, image
, ds_clear_value
,
1338 * Load the clear depth/stencil values from the image's metadata.
1341 radv_load_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1342 struct radv_image
*image
)
1344 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1345 VkImageAspectFlags aspects
= vk_format_aspects(image
->vk_format
);
1346 uint64_t va
= radv_buffer_get_va(image
->bo
);
1347 unsigned reg_offset
= 0, reg_count
= 0;
1349 va
+= image
->offset
+ image
->clear_value_offset
;
1351 if (!radv_image_has_htile(image
))
1354 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1360 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1363 uint32_t reg
= R_028028_DB_STENCIL_CLEAR
+ 4 * reg_offset
;
1365 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= VI
) {
1366 radeon_emit(cs
, PKT3(PKT3_LOAD_CONTEXT_REG
, 3, 0));
1367 radeon_emit(cs
, va
);
1368 radeon_emit(cs
, va
>> 32);
1369 radeon_emit(cs
, (reg
- SI_CONTEXT_REG_OFFSET
) >> 2);
1370 radeon_emit(cs
, reg_count
);
1372 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
1373 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
1374 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1375 (reg_count
== 2 ? COPY_DATA_COUNT_SEL
: 0));
1376 radeon_emit(cs
, va
);
1377 radeon_emit(cs
, va
>> 32);
1378 radeon_emit(cs
, reg
>> 2);
1381 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1387 * With DCC some colors don't require CMASK elimination before being
1388 * used as a texture. This sets a predicate value to determine if the
1389 * cmask eliminate is required.
1392 radv_update_fce_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1393 struct radv_image
*image
, bool value
)
1395 uint64_t pred_val
= value
;
1396 uint64_t va
= radv_buffer_get_va(image
->bo
);
1397 va
+= image
->offset
+ image
->fce_pred_offset
;
1399 assert(radv_image_has_dcc(image
));
1401 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1402 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1403 S_370_WR_CONFIRM(1) |
1404 S_370_ENGINE_SEL(V_370_PFP
));
1405 radeon_emit(cmd_buffer
->cs
, va
);
1406 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1407 radeon_emit(cmd_buffer
->cs
, pred_val
);
1408 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1412 * Update the DCC predicate to reflect the compression state.
1415 radv_update_dcc_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1416 struct radv_image
*image
, bool value
)
1418 uint64_t pred_val
= value
;
1419 uint64_t va
= radv_buffer_get_va(image
->bo
);
1420 va
+= image
->offset
+ image
->dcc_pred_offset
;
1422 assert(radv_image_has_dcc(image
));
1424 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1425 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1426 S_370_WR_CONFIRM(1) |
1427 S_370_ENGINE_SEL(V_370_PFP
));
1428 radeon_emit(cmd_buffer
->cs
, va
);
1429 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1430 radeon_emit(cmd_buffer
->cs
, pred_val
);
1431 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1435 * Update the fast clear color values if the image is bound as a color buffer.
1438 radv_update_bound_fast_clear_color(struct radv_cmd_buffer
*cmd_buffer
,
1439 struct radv_image
*image
,
1441 uint32_t color_values
[2])
1443 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1444 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1445 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1446 struct radv_attachment_info
*att
;
1449 if (!framebuffer
|| !subpass
)
1452 att_idx
= subpass
->color_attachments
[cb_idx
].attachment
;
1453 if (att_idx
== VK_ATTACHMENT_UNUSED
)
1456 att
= &framebuffer
->attachments
[att_idx
];
1457 if (att
->attachment
->image
!= image
)
1460 radeon_set_context_reg_seq(cs
, R_028C8C_CB_COLOR0_CLEAR_WORD0
+ cb_idx
* 0x3c, 2);
1461 radeon_emit(cs
, color_values
[0]);
1462 radeon_emit(cs
, color_values
[1]);
1464 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1468 * Set the clear color values to the image's metadata.
1471 radv_set_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1472 struct radv_image
*image
,
1473 uint32_t color_values
[2])
1475 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1476 uint64_t va
= radv_buffer_get_va(image
->bo
);
1478 va
+= image
->offset
+ image
->clear_value_offset
;
1480 assert(radv_image_has_cmask(image
) || radv_image_has_dcc(image
));
1482 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1483 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1484 S_370_WR_CONFIRM(1) |
1485 S_370_ENGINE_SEL(V_370_PFP
));
1486 radeon_emit(cs
, va
);
1487 radeon_emit(cs
, va
>> 32);
1488 radeon_emit(cs
, color_values
[0]);
1489 radeon_emit(cs
, color_values
[1]);
1493 * Update the clear color values for this image.
1496 radv_update_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1497 struct radv_image
*image
,
1499 uint32_t color_values
[2])
1501 assert(radv_image_has_cmask(image
) || radv_image_has_dcc(image
));
1503 radv_set_color_clear_metadata(cmd_buffer
, image
, color_values
);
1505 radv_update_bound_fast_clear_color(cmd_buffer
, image
, cb_idx
,
1510 * Load the clear color values from the image's metadata.
1513 radv_load_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1514 struct radv_image
*image
,
1517 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1518 uint64_t va
= radv_buffer_get_va(image
->bo
);
1520 va
+= image
->offset
+ image
->clear_value_offset
;
1522 if (!radv_image_has_cmask(image
) && !radv_image_has_dcc(image
))
1525 uint32_t reg
= R_028C8C_CB_COLOR0_CLEAR_WORD0
+ cb_idx
* 0x3c;
1527 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= VI
) {
1528 radeon_emit(cs
, PKT3(PKT3_LOAD_CONTEXT_REG
, 3, cmd_buffer
->state
.predicating
));
1529 radeon_emit(cs
, va
);
1530 radeon_emit(cs
, va
>> 32);
1531 radeon_emit(cs
, (reg
- SI_CONTEXT_REG_OFFSET
) >> 2);
1534 /* TODO: Figure out how to use LOAD_CONTEXT_REG on SI/CIK. */
1535 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, cmd_buffer
->state
.predicating
));
1536 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
1537 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1538 COPY_DATA_COUNT_SEL
);
1539 radeon_emit(cs
, va
);
1540 radeon_emit(cs
, va
>> 32);
1541 radeon_emit(cs
, reg
>> 2);
1544 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, cmd_buffer
->state
.predicating
));
1550 radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer
)
1553 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1554 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1555 unsigned num_bpp64_colorbufs
= 0;
1557 /* this may happen for inherited secondary recording */
1561 for (i
= 0; i
< 8; ++i
) {
1562 if (i
>= subpass
->color_count
|| subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
1563 radeon_set_context_reg(cmd_buffer
->cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
1564 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
1568 int idx
= subpass
->color_attachments
[i
].attachment
;
1569 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1570 struct radv_image
*image
= att
->attachment
->image
;
1571 VkImageLayout layout
= subpass
->color_attachments
[i
].layout
;
1573 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, att
->attachment
->bo
);
1575 assert(att
->attachment
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
);
1576 radv_emit_fb_color_state(cmd_buffer
, i
, att
, image
, layout
);
1578 radv_load_color_clear_metadata(cmd_buffer
, image
, i
);
1580 if (image
->surface
.bpe
>= 8)
1581 num_bpp64_colorbufs
++;
1584 if(subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1585 int idx
= subpass
->depth_stencil_attachment
.attachment
;
1586 VkImageLayout layout
= subpass
->depth_stencil_attachment
.layout
;
1587 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1588 struct radv_image
*image
= att
->attachment
->image
;
1589 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, att
->attachment
->bo
);
1590 MAYBE_UNUSED
uint32_t queue_mask
= radv_image_queue_family_mask(image
,
1591 cmd_buffer
->queue_family_index
,
1592 cmd_buffer
->queue_family_index
);
1593 /* We currently don't support writing decompressed HTILE */
1594 assert(radv_layout_has_htile(image
, layout
, queue_mask
) ==
1595 radv_layout_is_htile_compressed(image
, layout
, queue_mask
));
1597 radv_emit_fb_ds_state(cmd_buffer
, &att
->ds
, image
, layout
);
1599 if (att
->ds
.offset_scale
!= cmd_buffer
->state
.offset_scale
) {
1600 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
1601 cmd_buffer
->state
.offset_scale
= att
->ds
.offset_scale
;
1603 radv_load_ds_clear_metadata(cmd_buffer
, image
);
1605 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1606 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 2);
1608 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028040_DB_Z_INFO
, 2);
1610 radeon_emit(cmd_buffer
->cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
1611 radeon_emit(cmd_buffer
->cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
1613 radeon_set_context_reg(cmd_buffer
->cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
1614 S_028208_BR_X(framebuffer
->width
) |
1615 S_028208_BR_Y(framebuffer
->height
));
1617 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= VI
) {
1618 uint8_t watermark
= 4; /* Default value for VI. */
1620 /* For optimal DCC performance. */
1621 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1622 if (num_bpp64_colorbufs
>= 5) {
1629 radeon_set_context_reg(cmd_buffer
->cs
, R_028424_CB_DCC_CONTROL
,
1630 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
1631 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark
));
1634 if (cmd_buffer
->device
->dfsm_allowed
) {
1635 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1636 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
1639 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_FRAMEBUFFER
;
1643 radv_emit_index_buffer(struct radv_cmd_buffer
*cmd_buffer
)
1645 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1646 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
1648 if (state
->index_type
!= state
->last_index_type
) {
1649 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1650 radeon_set_uconfig_reg_idx(cs
, R_03090C_VGT_INDEX_TYPE
,
1651 2, state
->index_type
);
1653 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
1654 radeon_emit(cs
, state
->index_type
);
1657 state
->last_index_type
= state
->index_type
;
1660 radeon_emit(cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
1661 radeon_emit(cs
, state
->index_va
);
1662 radeon_emit(cs
, state
->index_va
>> 32);
1664 radeon_emit(cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
1665 radeon_emit(cs
, state
->max_index_count
);
1667 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_INDEX_BUFFER
;
1670 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
)
1672 bool has_perfect_queries
= cmd_buffer
->state
.perfect_occlusion_queries_enabled
;
1673 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1674 uint32_t pa_sc_mode_cntl_1
=
1675 pipeline
? pipeline
->graphics
.ms
.pa_sc_mode_cntl_1
: 0;
1676 uint32_t db_count_control
;
1678 if(!cmd_buffer
->state
.active_occlusion_queries
) {
1679 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1680 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1
) &&
1681 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
&&
1682 has_perfect_queries
) {
1683 /* Re-enable out-of-order rasterization if the
1684 * bound pipeline supports it and if it's has
1685 * been disabled before starting any perfect
1686 * occlusion queries.
1688 radeon_set_context_reg(cmd_buffer
->cs
,
1689 R_028A4C_PA_SC_MODE_CNTL_1
,
1693 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
1695 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1696 uint32_t sample_rate
= subpass
? util_logbase2(subpass
->max_sample_count
) : 0;
1698 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1700 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries
) |
1701 S_028004_SAMPLE_RATE(sample_rate
) |
1702 S_028004_ZPASS_ENABLE(1) |
1703 S_028004_SLICE_EVEN_ENABLE(1) |
1704 S_028004_SLICE_ODD_ENABLE(1);
1706 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1
) &&
1707 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
&&
1708 has_perfect_queries
) {
1709 /* If the bound pipeline has enabled
1710 * out-of-order rasterization, we should
1711 * disable it before starting any perfect
1712 * occlusion queries.
1714 pa_sc_mode_cntl_1
&= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE
;
1716 radeon_set_context_reg(cmd_buffer
->cs
,
1717 R_028A4C_PA_SC_MODE_CNTL_1
,
1721 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
1722 S_028004_SAMPLE_RATE(sample_rate
);
1726 radeon_set_context_reg(cmd_buffer
->cs
, R_028004_DB_COUNT_CONTROL
, db_count_control
);
1728 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1732 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
)
1734 uint32_t states
= cmd_buffer
->state
.dirty
& cmd_buffer
->state
.emitted_pipeline
->graphics
.needed_dynamic_state
;
1736 if (states
& (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
1737 radv_emit_viewport(cmd_buffer
);
1739 if (states
& (RADV_CMD_DIRTY_DYNAMIC_SCISSOR
| RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
) &&
1740 !cmd_buffer
->device
->physical_device
->has_scissor_bug
)
1741 radv_emit_scissor(cmd_buffer
);
1743 if (states
& RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
)
1744 radv_emit_line_width(cmd_buffer
);
1746 if (states
& RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
)
1747 radv_emit_blend_constants(cmd_buffer
);
1749 if (states
& (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
|
1750 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
|
1751 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
))
1752 radv_emit_stencil(cmd_buffer
);
1754 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
)
1755 radv_emit_depth_bounds(cmd_buffer
);
1757 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
)
1758 radv_emit_depth_bias(cmd_buffer
);
1760 if (states
& RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
)
1761 radv_emit_discard_rectangle(cmd_buffer
);
1763 cmd_buffer
->state
.dirty
&= ~states
;
1767 radv_flush_push_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
1768 VkPipelineBindPoint bind_point
)
1770 struct radv_descriptor_state
*descriptors_state
=
1771 radv_get_descriptors_state(cmd_buffer
, bind_point
);
1772 struct radv_descriptor_set
*set
= &descriptors_state
->push_set
.set
;
1775 if (!radv_cmd_buffer_upload_data(cmd_buffer
, set
->size
, 32,
1780 set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1781 set
->va
+= bo_offset
;
1785 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer
*cmd_buffer
,
1786 VkPipelineBindPoint bind_point
)
1788 struct radv_descriptor_state
*descriptors_state
=
1789 radv_get_descriptors_state(cmd_buffer
, bind_point
);
1790 uint32_t size
= MAX_SETS
* 4;
1794 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
,
1795 256, &offset
, &ptr
))
1798 for (unsigned i
= 0; i
< MAX_SETS
; i
++) {
1799 uint32_t *uptr
= ((uint32_t *)ptr
) + i
;
1800 uint64_t set_va
= 0;
1801 struct radv_descriptor_set
*set
= descriptors_state
->sets
[i
];
1802 if (descriptors_state
->valid
& (1u << i
))
1804 uptr
[0] = set_va
& 0xffffffff;
1807 uint64_t va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1810 if (cmd_buffer
->state
.pipeline
) {
1811 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
])
1812 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
1813 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1815 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_FRAGMENT
])
1816 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_FRAGMENT
,
1817 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1819 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
))
1820 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
1821 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1823 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
1824 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_CTRL
,
1825 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1827 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
1828 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_EVAL
,
1829 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1832 if (cmd_buffer
->state
.compute_pipeline
)
1833 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
, MESA_SHADER_COMPUTE
,
1834 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1838 radv_flush_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
1839 VkShaderStageFlags stages
)
1841 VkPipelineBindPoint bind_point
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
?
1842 VK_PIPELINE_BIND_POINT_COMPUTE
:
1843 VK_PIPELINE_BIND_POINT_GRAPHICS
;
1844 struct radv_descriptor_state
*descriptors_state
=
1845 radv_get_descriptors_state(cmd_buffer
, bind_point
);
1846 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
1847 bool flush_indirect_descriptors
;
1849 if (!descriptors_state
->dirty
)
1852 if (descriptors_state
->push_dirty
)
1853 radv_flush_push_descriptors(cmd_buffer
, bind_point
);
1855 flush_indirect_descriptors
=
1856 (bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
&&
1857 state
->pipeline
&& state
->pipeline
->need_indirect_descriptor_sets
) ||
1858 (bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
&&
1859 state
->compute_pipeline
&& state
->compute_pipeline
->need_indirect_descriptor_sets
);
1861 if (flush_indirect_descriptors
)
1862 radv_flush_indirect_descriptor_sets(cmd_buffer
, bind_point
);
1864 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
1866 MAX_SETS
* MESA_SHADER_STAGES
* 4);
1868 if (cmd_buffer
->state
.pipeline
) {
1869 radv_foreach_stage(stage
, stages
) {
1870 if (!cmd_buffer
->state
.pipeline
->shaders
[stage
])
1873 radv_emit_descriptor_pointers(cmd_buffer
,
1874 cmd_buffer
->state
.pipeline
,
1875 descriptors_state
, stage
);
1879 if (cmd_buffer
->state
.compute_pipeline
&&
1880 (stages
& VK_SHADER_STAGE_COMPUTE_BIT
)) {
1881 radv_emit_descriptor_pointers(cmd_buffer
,
1882 cmd_buffer
->state
.compute_pipeline
,
1884 MESA_SHADER_COMPUTE
);
1887 descriptors_state
->dirty
= 0;
1888 descriptors_state
->push_dirty
= false;
1890 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1892 if (unlikely(cmd_buffer
->device
->trace_bo
))
1893 radv_save_descriptors(cmd_buffer
, bind_point
);
1897 radv_flush_constants(struct radv_cmd_buffer
*cmd_buffer
,
1898 VkShaderStageFlags stages
)
1900 struct radv_pipeline
*pipeline
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
1901 ? cmd_buffer
->state
.compute_pipeline
1902 : cmd_buffer
->state
.pipeline
;
1903 VkPipelineBindPoint bind_point
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
?
1904 VK_PIPELINE_BIND_POINT_COMPUTE
:
1905 VK_PIPELINE_BIND_POINT_GRAPHICS
;
1906 struct radv_descriptor_state
*descriptors_state
=
1907 radv_get_descriptors_state(cmd_buffer
, bind_point
);
1908 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
1909 struct radv_shader_variant
*shader
, *prev_shader
;
1914 stages
&= cmd_buffer
->push_constant_stages
;
1916 (!layout
->push_constant_size
&& !layout
->dynamic_offset_count
))
1919 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, layout
->push_constant_size
+
1920 16 * layout
->dynamic_offset_count
,
1921 256, &offset
, &ptr
))
1924 memcpy(ptr
, cmd_buffer
->push_constants
, layout
->push_constant_size
);
1925 memcpy((char*)ptr
+ layout
->push_constant_size
,
1926 descriptors_state
->dynamic_buffers
,
1927 16 * layout
->dynamic_offset_count
);
1929 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1932 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
1933 cmd_buffer
->cs
, MESA_SHADER_STAGES
* 4);
1936 radv_foreach_stage(stage
, stages
) {
1937 shader
= radv_get_shader(pipeline
, stage
);
1939 /* Avoid redundantly emitting the address for merged stages. */
1940 if (shader
&& shader
!= prev_shader
) {
1941 radv_emit_userdata_address(cmd_buffer
, pipeline
, stage
,
1942 AC_UD_PUSH_CONSTANTS
, va
);
1944 prev_shader
= shader
;
1948 cmd_buffer
->push_constant_stages
&= ~stages
;
1949 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1953 radv_flush_vertex_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
1954 bool pipeline_is_dirty
)
1956 if ((pipeline_is_dirty
||
1957 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_VERTEX_BUFFER
)) &&
1958 cmd_buffer
->state
.pipeline
->vertex_elements
.count
&&
1959 radv_get_shader(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
)->info
.info
.vs
.has_vertex_buffers
) {
1960 struct radv_vertex_elements_info
*velems
= &cmd_buffer
->state
.pipeline
->vertex_elements
;
1964 uint32_t count
= velems
->count
;
1967 /* allocate some descriptor state for vertex buffers */
1968 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, count
* 16, 256,
1969 &vb_offset
, &vb_ptr
))
1972 for (i
= 0; i
< count
; i
++) {
1973 uint32_t *desc
= &((uint32_t *)vb_ptr
)[i
* 4];
1975 int vb
= velems
->binding
[i
];
1976 struct radv_buffer
*buffer
= cmd_buffer
->vertex_bindings
[vb
].buffer
;
1977 uint32_t stride
= cmd_buffer
->state
.pipeline
->binding_stride
[vb
];
1979 va
= radv_buffer_get_va(buffer
->bo
);
1981 offset
= cmd_buffer
->vertex_bindings
[vb
].offset
+ velems
->offset
[i
];
1982 va
+= offset
+ buffer
->offset
;
1984 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(stride
);
1985 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
<= CIK
&& stride
)
1986 desc
[2] = (buffer
->size
- offset
- velems
->format_size
[i
]) / stride
+ 1;
1988 desc
[2] = buffer
->size
- offset
;
1989 desc
[3] = velems
->rsrc_word3
[i
];
1992 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1995 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
1996 AC_UD_VS_VERTEX_BUFFERS
, va
);
1998 cmd_buffer
->state
.vb_va
= va
;
1999 cmd_buffer
->state
.vb_size
= count
* 16;
2000 cmd_buffer
->state
.prefetch_L2_mask
|= RADV_PREFETCH_VBO_DESCRIPTORS
;
2002 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_VERTEX_BUFFER
;
2006 radv_emit_streamout_buffers(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
)
2008 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2009 struct radv_userdata_info
*loc
;
2012 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
2013 if (!radv_get_shader(pipeline
, stage
))
2016 loc
= radv_lookup_user_sgpr(pipeline
, stage
,
2017 AC_UD_STREAMOUT_BUFFERS
);
2018 if (loc
->sgpr_idx
== -1)
2021 base_reg
= pipeline
->user_data_0
[stage
];
2023 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
2024 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
2027 if (pipeline
->gs_copy_shader
) {
2028 loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_STREAMOUT_BUFFERS
];
2029 if (loc
->sgpr_idx
!= -1) {
2030 base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2032 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
2033 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
2039 radv_flush_streamout_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
2041 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_STREAMOUT_BUFFER
) {
2042 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
2043 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
2048 /* Allocate some descriptor state for streamout buffers. */
2049 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
,
2050 MAX_SO_BUFFERS
* 16, 256,
2051 &so_offset
, &so_ptr
))
2054 for (uint32_t i
= 0; i
< MAX_SO_BUFFERS
; i
++) {
2055 struct radv_buffer
*buffer
= sb
[i
].buffer
;
2056 uint32_t *desc
= &((uint32_t *)so_ptr
)[i
* 4];
2058 if (!(so
->enabled_mask
& (1 << i
)))
2061 va
= radv_buffer_get_va(buffer
->bo
) + buffer
->offset
;
2065 /* Set the descriptor.
2067 * On VI, the format must be non-INVALID, otherwise
2068 * the buffer will be considered not bound and store
2069 * instructions will be no-ops.
2072 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
2073 desc
[2] = 0xffffffff;
2074 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2075 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2076 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2077 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2078 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2081 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2084 radv_emit_streamout_buffers(cmd_buffer
, va
);
2087 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER
;
2091 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
, bool pipeline_is_dirty
)
2093 radv_flush_vertex_descriptors(cmd_buffer
, pipeline_is_dirty
);
2094 radv_flush_streamout_descriptors(cmd_buffer
);
2095 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
2096 radv_flush_constants(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
2099 struct radv_draw_info
{
2101 * Number of vertices.
2106 * Index of the first vertex.
2108 int32_t vertex_offset
;
2111 * First instance id.
2113 uint32_t first_instance
;
2116 * Number of instances.
2118 uint32_t instance_count
;
2121 * First index (indexed draws only).
2123 uint32_t first_index
;
2126 * Whether it's an indexed draw.
2131 * Indirect draw parameters resource.
2133 struct radv_buffer
*indirect
;
2134 uint64_t indirect_offset
;
2138 * Draw count parameters resource.
2140 struct radv_buffer
*count_buffer
;
2141 uint64_t count_buffer_offset
;
2144 * Stream output parameters resource.
2146 struct radv_buffer
*strmout_buffer
;
2147 uint64_t strmout_buffer_offset
;
2151 radv_emit_draw_registers(struct radv_cmd_buffer
*cmd_buffer
,
2152 const struct radv_draw_info
*draw_info
)
2154 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
2155 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2156 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
2157 uint32_t ia_multi_vgt_param
;
2158 int32_t primitive_reset_en
;
2161 ia_multi_vgt_param
=
2162 si_get_ia_multi_vgt_param(cmd_buffer
, draw_info
->instance_count
> 1,
2163 draw_info
->indirect
,
2164 draw_info
->indirect
? 0 : draw_info
->count
);
2166 if (state
->last_ia_multi_vgt_param
!= ia_multi_vgt_param
) {
2167 if (info
->chip_class
>= GFX9
) {
2168 radeon_set_uconfig_reg_idx(cs
,
2169 R_030960_IA_MULTI_VGT_PARAM
,
2170 4, ia_multi_vgt_param
);
2171 } else if (info
->chip_class
>= CIK
) {
2172 radeon_set_context_reg_idx(cs
,
2173 R_028AA8_IA_MULTI_VGT_PARAM
,
2174 1, ia_multi_vgt_param
);
2176 radeon_set_context_reg(cs
, R_028AA8_IA_MULTI_VGT_PARAM
,
2177 ia_multi_vgt_param
);
2179 state
->last_ia_multi_vgt_param
= ia_multi_vgt_param
;
2182 /* Primitive restart. */
2183 primitive_reset_en
=
2184 draw_info
->indexed
&& state
->pipeline
->graphics
.prim_restart_enable
;
2186 if (primitive_reset_en
!= state
->last_primitive_reset_en
) {
2187 state
->last_primitive_reset_en
= primitive_reset_en
;
2188 if (info
->chip_class
>= GFX9
) {
2189 radeon_set_uconfig_reg(cs
,
2190 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN
,
2191 primitive_reset_en
);
2193 radeon_set_context_reg(cs
,
2194 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
,
2195 primitive_reset_en
);
2199 if (primitive_reset_en
) {
2200 uint32_t primitive_reset_index
=
2201 state
->index_type
? 0xffffffffu
: 0xffffu
;
2203 if (primitive_reset_index
!= state
->last_primitive_reset_index
) {
2204 radeon_set_context_reg(cs
,
2205 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
2206 primitive_reset_index
);
2207 state
->last_primitive_reset_index
= primitive_reset_index
;
2211 if (draw_info
->strmout_buffer
) {
2212 uint64_t va
= radv_buffer_get_va(draw_info
->strmout_buffer
->bo
);
2214 va
+= draw_info
->strmout_buffer
->offset
+
2215 draw_info
->strmout_buffer_offset
;
2217 radeon_set_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
,
2220 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
2221 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
2222 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
2223 COPY_DATA_WR_CONFIRM
);
2224 radeon_emit(cs
, va
);
2225 radeon_emit(cs
, va
>> 32);
2226 radeon_emit(cs
, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2);
2227 radeon_emit(cs
, 0); /* unused */
2229 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, draw_info
->strmout_buffer
->bo
);
2233 static void radv_stage_flush(struct radv_cmd_buffer
*cmd_buffer
,
2234 VkPipelineStageFlags src_stage_mask
)
2236 if (src_stage_mask
& (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT
|
2237 VK_PIPELINE_STAGE_TRANSFER_BIT
|
2238 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
2239 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
2240 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
;
2243 if (src_stage_mask
& (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT
|
2244 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT
|
2245 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT
|
2246 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
|
2247 VK_PIPELINE_STAGE_TRANSFER_BIT
|
2248 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
2249 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT
|
2250 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
2251 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
2252 } else if (src_stage_mask
& (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
2253 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
|
2254 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT
|
2255 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT
|
2256 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT
|
2257 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT
|
2258 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT
)) {
2259 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VS_PARTIAL_FLUSH
;
2263 static enum radv_cmd_flush_bits
2264 radv_src_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
2265 VkAccessFlags src_flags
,
2266 struct radv_image
*image
)
2268 bool flush_CB_meta
= true, flush_DB_meta
= true;
2269 enum radv_cmd_flush_bits flush_bits
= 0;
2273 if (!radv_image_has_CB_metadata(image
))
2274 flush_CB_meta
= false;
2275 if (!radv_image_has_htile(image
))
2276 flush_DB_meta
= false;
2279 for_each_bit(b
, src_flags
) {
2280 switch ((VkAccessFlagBits
)(1 << b
)) {
2281 case VK_ACCESS_SHADER_WRITE_BIT
:
2282 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT
:
2283 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
:
2284 flush_bits
|= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
2286 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2287 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
2289 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2291 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2292 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
2294 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2296 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2297 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
2298 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
2299 RADV_CMD_FLAG_INV_GLOBAL_L2
;
2302 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2304 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2313 static enum radv_cmd_flush_bits
2314 radv_dst_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
2315 VkAccessFlags dst_flags
,
2316 struct radv_image
*image
)
2318 bool flush_CB_meta
= true, flush_DB_meta
= true;
2319 enum radv_cmd_flush_bits flush_bits
= 0;
2320 bool flush_CB
= true, flush_DB
= true;
2321 bool image_is_coherent
= false;
2325 if (!(image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
)) {
2330 if (!radv_image_has_CB_metadata(image
))
2331 flush_CB_meta
= false;
2332 if (!radv_image_has_htile(image
))
2333 flush_DB_meta
= false;
2335 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2336 if (image
->info
.samples
== 1 &&
2337 (image
->usage
& (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
|
2338 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
)) &&
2339 !vk_format_is_stencil(image
->vk_format
)) {
2340 /* Single-sample color and single-sample depth
2341 * (not stencil) are coherent with shaders on
2344 image_is_coherent
= true;
2349 for_each_bit(b
, dst_flags
) {
2350 switch ((VkAccessFlagBits
)(1 << b
)) {
2351 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2352 case VK_ACCESS_INDEX_READ_BIT
:
2353 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
:
2355 case VK_ACCESS_UNIFORM_READ_BIT
:
2356 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
| RADV_CMD_FLAG_INV_SMEM_L1
;
2358 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2359 case VK_ACCESS_TRANSFER_READ_BIT
:
2360 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2361 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
|
2362 RADV_CMD_FLAG_INV_GLOBAL_L2
;
2364 case VK_ACCESS_SHADER_READ_BIT
:
2365 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
;
2367 if (!image_is_coherent
)
2368 flush_bits
|= RADV_CMD_FLAG_INV_GLOBAL_L2
;
2370 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
:
2372 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
2374 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2376 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
:
2378 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
2380 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2389 void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
,
2390 const struct radv_subpass_barrier
*barrier
)
2392 cmd_buffer
->state
.flush_bits
|= radv_src_access_flush(cmd_buffer
, barrier
->src_access_mask
,
2394 radv_stage_flush(cmd_buffer
, barrier
->src_stage_mask
);
2395 cmd_buffer
->state
.flush_bits
|= radv_dst_access_flush(cmd_buffer
, barrier
->dst_access_mask
,
2399 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
2400 struct radv_subpass_attachment att
)
2402 unsigned idx
= att
.attachment
;
2403 struct radv_image_view
*view
= cmd_buffer
->state
.framebuffer
->attachments
[idx
].attachment
;
2404 VkImageSubresourceRange range
;
2405 range
.aspectMask
= 0;
2406 range
.baseMipLevel
= view
->base_mip
;
2407 range
.levelCount
= 1;
2408 range
.baseArrayLayer
= view
->base_layer
;
2409 range
.layerCount
= cmd_buffer
->state
.framebuffer
->layers
;
2411 if (cmd_buffer
->state
.subpass
&& cmd_buffer
->state
.subpass
->view_mask
) {
2412 /* If the current subpass uses multiview, the driver might have
2413 * performed a fast color/depth clear to the whole image
2414 * (including all layers). To make sure the driver will
2415 * decompress the image correctly (if needed), we have to
2416 * account for the "real" number of layers. If the view mask is
2417 * sparse, this will decompress more layers than needed.
2419 range
.layerCount
= util_last_bit(cmd_buffer
->state
.subpass
->view_mask
);
2422 radv_handle_image_transition(cmd_buffer
,
2424 cmd_buffer
->state
.attachments
[idx
].current_layout
,
2425 att
.layout
, 0, 0, &range
);
2427 cmd_buffer
->state
.attachments
[idx
].current_layout
= att
.layout
;
2433 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
2434 const struct radv_subpass
*subpass
, bool transitions
)
2437 radv_subpass_barrier(cmd_buffer
, &subpass
->start_barrier
);
2439 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
2440 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
2441 radv_handle_subpass_image_transition(cmd_buffer
,
2442 subpass
->color_attachments
[i
]);
2445 for (unsigned i
= 0; i
< subpass
->input_count
; ++i
) {
2446 radv_handle_subpass_image_transition(cmd_buffer
,
2447 subpass
->input_attachments
[i
]);
2450 if (subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
2451 radv_handle_subpass_image_transition(cmd_buffer
,
2452 subpass
->depth_stencil_attachment
);
2456 cmd_buffer
->state
.subpass
= subpass
;
2458 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_FRAMEBUFFER
;
2462 radv_cmd_state_setup_attachments(struct radv_cmd_buffer
*cmd_buffer
,
2463 struct radv_render_pass
*pass
,
2464 const VkRenderPassBeginInfo
*info
)
2466 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2468 if (pass
->attachment_count
== 0) {
2469 state
->attachments
= NULL
;
2473 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
2474 pass
->attachment_count
*
2475 sizeof(state
->attachments
[0]),
2476 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2477 if (state
->attachments
== NULL
) {
2478 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2479 return cmd_buffer
->record_result
;
2482 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
2483 struct radv_render_pass_attachment
*att
= &pass
->attachments
[i
];
2484 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
2485 VkImageAspectFlags clear_aspects
= 0;
2487 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
2488 /* color attachment */
2489 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2490 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
2493 /* depthstencil attachment */
2494 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
2495 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2496 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
2497 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
2498 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_DONT_CARE
)
2499 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
2501 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
2502 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2503 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
2507 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
2508 state
->attachments
[i
].cleared_views
= 0;
2509 if (clear_aspects
&& info
) {
2510 assert(info
->clearValueCount
> i
);
2511 state
->attachments
[i
].clear_value
= info
->pClearValues
[i
];
2514 state
->attachments
[i
].current_layout
= att
->initial_layout
;
2520 VkResult
radv_AllocateCommandBuffers(
2522 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
2523 VkCommandBuffer
*pCommandBuffers
)
2525 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2526 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
2528 VkResult result
= VK_SUCCESS
;
2531 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
2533 if (!list_empty(&pool
->free_cmd_buffers
)) {
2534 struct radv_cmd_buffer
*cmd_buffer
= list_first_entry(&pool
->free_cmd_buffers
, struct radv_cmd_buffer
, pool_link
);
2536 list_del(&cmd_buffer
->pool_link
);
2537 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
2539 result
= radv_reset_cmd_buffer(cmd_buffer
);
2540 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
2541 cmd_buffer
->level
= pAllocateInfo
->level
;
2543 pCommandBuffers
[i
] = radv_cmd_buffer_to_handle(cmd_buffer
);
2545 result
= radv_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
2546 &pCommandBuffers
[i
]);
2548 if (result
!= VK_SUCCESS
)
2552 if (result
!= VK_SUCCESS
) {
2553 radv_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
,
2554 i
, pCommandBuffers
);
2556 /* From the Vulkan 1.0.66 spec:
2558 * "vkAllocateCommandBuffers can be used to create multiple
2559 * command buffers. If the creation of any of those command
2560 * buffers fails, the implementation must destroy all
2561 * successfully created command buffer objects from this
2562 * command, set all entries of the pCommandBuffers array to
2563 * NULL and return the error."
2565 memset(pCommandBuffers
, 0,
2566 sizeof(*pCommandBuffers
) * pAllocateInfo
->commandBufferCount
);
2572 void radv_FreeCommandBuffers(
2574 VkCommandPool commandPool
,
2575 uint32_t commandBufferCount
,
2576 const VkCommandBuffer
*pCommandBuffers
)
2578 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2579 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
2582 if (cmd_buffer
->pool
) {
2583 list_del(&cmd_buffer
->pool_link
);
2584 list_addtail(&cmd_buffer
->pool_link
, &cmd_buffer
->pool
->free_cmd_buffers
);
2586 radv_cmd_buffer_destroy(cmd_buffer
);
2592 VkResult
radv_ResetCommandBuffer(
2593 VkCommandBuffer commandBuffer
,
2594 VkCommandBufferResetFlags flags
)
2596 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2597 return radv_reset_cmd_buffer(cmd_buffer
);
2600 VkResult
radv_BeginCommandBuffer(
2601 VkCommandBuffer commandBuffer
,
2602 const VkCommandBufferBeginInfo
*pBeginInfo
)
2604 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2605 VkResult result
= VK_SUCCESS
;
2607 if (cmd_buffer
->status
!= RADV_CMD_BUFFER_STATUS_INITIAL
) {
2608 /* If the command buffer has already been resetted with
2609 * vkResetCommandBuffer, no need to do it again.
2611 result
= radv_reset_cmd_buffer(cmd_buffer
);
2612 if (result
!= VK_SUCCESS
)
2616 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
2617 cmd_buffer
->state
.last_primitive_reset_en
= -1;
2618 cmd_buffer
->state
.last_index_type
= -1;
2619 cmd_buffer
->state
.last_num_instances
= -1;
2620 cmd_buffer
->state
.last_vertex_offset
= -1;
2621 cmd_buffer
->state
.last_first_instance
= -1;
2622 cmd_buffer
->state
.predication_type
= -1;
2623 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
2625 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
&&
2626 (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
)) {
2627 assert(pBeginInfo
->pInheritanceInfo
);
2628 cmd_buffer
->state
.framebuffer
= radv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
2629 cmd_buffer
->state
.pass
= radv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
2631 struct radv_subpass
*subpass
=
2632 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
2634 result
= radv_cmd_state_setup_attachments(cmd_buffer
, cmd_buffer
->state
.pass
, NULL
);
2635 if (result
!= VK_SUCCESS
)
2638 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
, false);
2641 if (unlikely(cmd_buffer
->device
->trace_bo
)) {
2642 struct radv_device
*device
= cmd_buffer
->device
;
2644 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
,
2647 radv_cmd_buffer_trace_emit(cmd_buffer
);
2650 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_RECORDING
;
2655 void radv_CmdBindVertexBuffers(
2656 VkCommandBuffer commandBuffer
,
2657 uint32_t firstBinding
,
2658 uint32_t bindingCount
,
2659 const VkBuffer
* pBuffers
,
2660 const VkDeviceSize
* pOffsets
)
2662 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2663 struct radv_vertex_binding
*vb
= cmd_buffer
->vertex_bindings
;
2664 bool changed
= false;
2666 /* We have to defer setting up vertex buffer since we need the buffer
2667 * stride from the pipeline. */
2669 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
2670 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
2671 uint32_t idx
= firstBinding
+ i
;
2674 (vb
[idx
].buffer
!= radv_buffer_from_handle(pBuffers
[i
]) ||
2675 vb
[idx
].offset
!= pOffsets
[i
])) {
2679 vb
[idx
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
2680 vb
[idx
].offset
= pOffsets
[i
];
2682 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
2683 vb
[idx
].buffer
->bo
);
2687 /* No state changes. */
2691 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_VERTEX_BUFFER
;
2694 void radv_CmdBindIndexBuffer(
2695 VkCommandBuffer commandBuffer
,
2697 VkDeviceSize offset
,
2698 VkIndexType indexType
)
2700 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2701 RADV_FROM_HANDLE(radv_buffer
, index_buffer
, buffer
);
2703 if (cmd_buffer
->state
.index_buffer
== index_buffer
&&
2704 cmd_buffer
->state
.index_offset
== offset
&&
2705 cmd_buffer
->state
.index_type
== indexType
) {
2706 /* No state changes. */
2710 cmd_buffer
->state
.index_buffer
= index_buffer
;
2711 cmd_buffer
->state
.index_offset
= offset
;
2712 cmd_buffer
->state
.index_type
= indexType
; /* vk matches hw */
2713 cmd_buffer
->state
.index_va
= radv_buffer_get_va(index_buffer
->bo
);
2714 cmd_buffer
->state
.index_va
+= index_buffer
->offset
+ offset
;
2716 int index_size_shift
= cmd_buffer
->state
.index_type
? 2 : 1;
2717 cmd_buffer
->state
.max_index_count
= (index_buffer
->size
- offset
) >> index_size_shift
;
2718 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
2719 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, index_buffer
->bo
);
2724 radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2725 VkPipelineBindPoint bind_point
,
2726 struct radv_descriptor_set
*set
, unsigned idx
)
2728 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
2730 radv_set_descriptor_set(cmd_buffer
, bind_point
, set
, idx
);
2733 assert(!(set
->layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
));
2735 if (!cmd_buffer
->device
->use_global_bo_list
) {
2736 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
)
2737 if (set
->descriptors
[j
])
2738 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->descriptors
[j
]);
2742 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->bo
);
2745 void radv_CmdBindDescriptorSets(
2746 VkCommandBuffer commandBuffer
,
2747 VkPipelineBindPoint pipelineBindPoint
,
2748 VkPipelineLayout _layout
,
2750 uint32_t descriptorSetCount
,
2751 const VkDescriptorSet
* pDescriptorSets
,
2752 uint32_t dynamicOffsetCount
,
2753 const uint32_t* pDynamicOffsets
)
2755 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2756 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2757 unsigned dyn_idx
= 0;
2759 const bool no_dynamic_bounds
= cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
2760 struct radv_descriptor_state
*descriptors_state
=
2761 radv_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
2763 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
2764 unsigned idx
= i
+ firstSet
;
2765 RADV_FROM_HANDLE(radv_descriptor_set
, set
, pDescriptorSets
[i
]);
2766 radv_bind_descriptor_set(cmd_buffer
, pipelineBindPoint
, set
, idx
);
2768 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
2769 unsigned idx
= j
+ layout
->set
[i
+ firstSet
].dynamic_offset_start
;
2770 uint32_t *dst
= descriptors_state
->dynamic_buffers
+ idx
* 4;
2771 assert(dyn_idx
< dynamicOffsetCount
);
2773 struct radv_descriptor_range
*range
= set
->dynamic_descriptors
+ j
;
2774 uint64_t va
= range
->va
+ pDynamicOffsets
[dyn_idx
];
2776 dst
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
2777 dst
[2] = no_dynamic_bounds
? 0xffffffffu
: range
->size
;
2778 dst
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2779 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2780 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2781 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2782 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2783 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2784 cmd_buffer
->push_constant_stages
|=
2785 set
->layout
->dynamic_shader_stages
;
2790 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2791 struct radv_descriptor_set
*set
,
2792 struct radv_descriptor_set_layout
*layout
,
2793 VkPipelineBindPoint bind_point
)
2795 struct radv_descriptor_state
*descriptors_state
=
2796 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2797 set
->size
= layout
->size
;
2798 set
->layout
= layout
;
2800 if (descriptors_state
->push_set
.capacity
< set
->size
) {
2801 size_t new_size
= MAX2(set
->size
, 1024);
2802 new_size
= MAX2(new_size
, 2 * descriptors_state
->push_set
.capacity
);
2803 new_size
= MIN2(new_size
, 96 * MAX_PUSH_DESCRIPTORS
);
2805 free(set
->mapped_ptr
);
2806 set
->mapped_ptr
= malloc(new_size
);
2808 if (!set
->mapped_ptr
) {
2809 descriptors_state
->push_set
.capacity
= 0;
2810 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2814 descriptors_state
->push_set
.capacity
= new_size
;
2820 void radv_meta_push_descriptor_set(
2821 struct radv_cmd_buffer
* cmd_buffer
,
2822 VkPipelineBindPoint pipelineBindPoint
,
2823 VkPipelineLayout _layout
,
2825 uint32_t descriptorWriteCount
,
2826 const VkWriteDescriptorSet
* pDescriptorWrites
)
2828 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2829 struct radv_descriptor_set
*push_set
= &cmd_buffer
->meta_push_descriptors
;
2833 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2835 push_set
->size
= layout
->set
[set
].layout
->size
;
2836 push_set
->layout
= layout
->set
[set
].layout
;
2838 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, push_set
->size
, 32,
2840 (void**) &push_set
->mapped_ptr
))
2843 push_set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2844 push_set
->va
+= bo_offset
;
2846 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
2847 radv_descriptor_set_to_handle(push_set
),
2848 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
2850 radv_set_descriptor_set(cmd_buffer
, pipelineBindPoint
, push_set
, set
);
2853 void radv_CmdPushDescriptorSetKHR(
2854 VkCommandBuffer commandBuffer
,
2855 VkPipelineBindPoint pipelineBindPoint
,
2856 VkPipelineLayout _layout
,
2858 uint32_t descriptorWriteCount
,
2859 const VkWriteDescriptorSet
* pDescriptorWrites
)
2861 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2862 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2863 struct radv_descriptor_state
*descriptors_state
=
2864 radv_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
2865 struct radv_descriptor_set
*push_set
= &descriptors_state
->push_set
.set
;
2867 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2869 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
,
2870 layout
->set
[set
].layout
,
2874 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
2875 radv_descriptor_set_to_handle(push_set
),
2876 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
2878 radv_set_descriptor_set(cmd_buffer
, pipelineBindPoint
, push_set
, set
);
2879 descriptors_state
->push_dirty
= true;
2882 void radv_CmdPushDescriptorSetWithTemplateKHR(
2883 VkCommandBuffer commandBuffer
,
2884 VkDescriptorUpdateTemplate descriptorUpdateTemplate
,
2885 VkPipelineLayout _layout
,
2889 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2890 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2891 RADV_FROM_HANDLE(radv_descriptor_update_template
, templ
, descriptorUpdateTemplate
);
2892 struct radv_descriptor_state
*descriptors_state
=
2893 radv_get_descriptors_state(cmd_buffer
, templ
->bind_point
);
2894 struct radv_descriptor_set
*push_set
= &descriptors_state
->push_set
.set
;
2896 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2898 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
,
2899 layout
->set
[set
].layout
,
2903 radv_update_descriptor_set_with_template(cmd_buffer
->device
, cmd_buffer
, push_set
,
2904 descriptorUpdateTemplate
, pData
);
2906 radv_set_descriptor_set(cmd_buffer
, templ
->bind_point
, push_set
, set
);
2907 descriptors_state
->push_dirty
= true;
2910 void radv_CmdPushConstants(VkCommandBuffer commandBuffer
,
2911 VkPipelineLayout layout
,
2912 VkShaderStageFlags stageFlags
,
2915 const void* pValues
)
2917 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2918 memcpy(cmd_buffer
->push_constants
+ offset
, pValues
, size
);
2919 cmd_buffer
->push_constant_stages
|= stageFlags
;
2922 VkResult
radv_EndCommandBuffer(
2923 VkCommandBuffer commandBuffer
)
2925 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2927 if (cmd_buffer
->queue_family_index
!= RADV_QUEUE_TRANSFER
) {
2928 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== SI
)
2929 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
| RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
2930 si_emit_cache_flush(cmd_buffer
);
2933 /* Make sure CP DMA is idle at the end of IBs because the kernel
2934 * doesn't wait for it.
2936 si_cp_dma_wait_for_idle(cmd_buffer
);
2938 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
2940 if (!cmd_buffer
->device
->ws
->cs_finalize(cmd_buffer
->cs
))
2941 return vk_error(cmd_buffer
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2943 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_EXECUTABLE
;
2945 return cmd_buffer
->record_result
;
2949 radv_emit_compute_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
2951 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
2953 if (!pipeline
|| pipeline
== cmd_buffer
->state
.emitted_compute_pipeline
)
2956 assert(!pipeline
->ctx_cs
.cdw
);
2958 cmd_buffer
->state
.emitted_compute_pipeline
= pipeline
;
2960 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, pipeline
->cs
.cdw
);
2961 radeon_emit_array(cmd_buffer
->cs
, pipeline
->cs
.buf
, pipeline
->cs
.cdw
);
2963 cmd_buffer
->compute_scratch_size_needed
=
2964 MAX2(cmd_buffer
->compute_scratch_size_needed
,
2965 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
2967 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
2968 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->bo
);
2970 if (unlikely(cmd_buffer
->device
->trace_bo
))
2971 radv_save_pipeline(cmd_buffer
, pipeline
, RING_COMPUTE
);
2974 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer
*cmd_buffer
,
2975 VkPipelineBindPoint bind_point
)
2977 struct radv_descriptor_state
*descriptors_state
=
2978 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2980 descriptors_state
->dirty
|= descriptors_state
->valid
;
2983 void radv_CmdBindPipeline(
2984 VkCommandBuffer commandBuffer
,
2985 VkPipelineBindPoint pipelineBindPoint
,
2986 VkPipeline _pipeline
)
2988 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2989 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
2991 switch (pipelineBindPoint
) {
2992 case VK_PIPELINE_BIND_POINT_COMPUTE
:
2993 if (cmd_buffer
->state
.compute_pipeline
== pipeline
)
2995 radv_mark_descriptor_sets_dirty(cmd_buffer
, pipelineBindPoint
);
2997 cmd_buffer
->state
.compute_pipeline
= pipeline
;
2998 cmd_buffer
->push_constant_stages
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3000 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
3001 if (cmd_buffer
->state
.pipeline
== pipeline
)
3003 radv_mark_descriptor_sets_dirty(cmd_buffer
, pipelineBindPoint
);
3005 cmd_buffer
->state
.pipeline
= pipeline
;
3009 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
;
3010 cmd_buffer
->push_constant_stages
|= pipeline
->active_stages
;
3012 /* the new vertex shader might not have the same user regs */
3013 cmd_buffer
->state
.last_first_instance
= -1;
3014 cmd_buffer
->state
.last_vertex_offset
= -1;
3016 /* Prefetch all pipeline shaders at first draw time. */
3017 cmd_buffer
->state
.prefetch_L2_mask
|= RADV_PREFETCH_SHADERS
;
3019 radv_bind_dynamic_state(cmd_buffer
, &pipeline
->dynamic_state
);
3020 radv_bind_streamout_state(cmd_buffer
, pipeline
);
3022 if (pipeline
->graphics
.esgs_ring_size
> cmd_buffer
->esgs_ring_size_needed
)
3023 cmd_buffer
->esgs_ring_size_needed
= pipeline
->graphics
.esgs_ring_size
;
3024 if (pipeline
->graphics
.gsvs_ring_size
> cmd_buffer
->gsvs_ring_size_needed
)
3025 cmd_buffer
->gsvs_ring_size_needed
= pipeline
->graphics
.gsvs_ring_size
;
3027 if (radv_pipeline_has_tess(pipeline
))
3028 cmd_buffer
->tess_rings_needed
= true;
3031 assert(!"invalid bind point");
3036 void radv_CmdSetViewport(
3037 VkCommandBuffer commandBuffer
,
3038 uint32_t firstViewport
,
3039 uint32_t viewportCount
,
3040 const VkViewport
* pViewports
)
3042 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3043 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3044 MAYBE_UNUSED
const uint32_t total_count
= firstViewport
+ viewportCount
;
3046 assert(firstViewport
< MAX_VIEWPORTS
);
3047 assert(total_count
>= 1 && total_count
<= MAX_VIEWPORTS
);
3049 memcpy(state
->dynamic
.viewport
.viewports
+ firstViewport
, pViewports
,
3050 viewportCount
* sizeof(*pViewports
));
3052 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
3055 void radv_CmdSetScissor(
3056 VkCommandBuffer commandBuffer
,
3057 uint32_t firstScissor
,
3058 uint32_t scissorCount
,
3059 const VkRect2D
* pScissors
)
3061 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3062 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3063 MAYBE_UNUSED
const uint32_t total_count
= firstScissor
+ scissorCount
;
3065 assert(firstScissor
< MAX_SCISSORS
);
3066 assert(total_count
>= 1 && total_count
<= MAX_SCISSORS
);
3068 memcpy(state
->dynamic
.scissor
.scissors
+ firstScissor
, pScissors
,
3069 scissorCount
* sizeof(*pScissors
));
3071 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
3074 void radv_CmdSetLineWidth(
3075 VkCommandBuffer commandBuffer
,
3078 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3079 cmd_buffer
->state
.dynamic
.line_width
= lineWidth
;
3080 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
3083 void radv_CmdSetDepthBias(
3084 VkCommandBuffer commandBuffer
,
3085 float depthBiasConstantFactor
,
3086 float depthBiasClamp
,
3087 float depthBiasSlopeFactor
)
3089 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3091 cmd_buffer
->state
.dynamic
.depth_bias
.bias
= depthBiasConstantFactor
;
3092 cmd_buffer
->state
.dynamic
.depth_bias
.clamp
= depthBiasClamp
;
3093 cmd_buffer
->state
.dynamic
.depth_bias
.slope
= depthBiasSlopeFactor
;
3095 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
3098 void radv_CmdSetBlendConstants(
3099 VkCommandBuffer commandBuffer
,
3100 const float blendConstants
[4])
3102 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3104 memcpy(cmd_buffer
->state
.dynamic
.blend_constants
,
3105 blendConstants
, sizeof(float) * 4);
3107 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
3110 void radv_CmdSetDepthBounds(
3111 VkCommandBuffer commandBuffer
,
3112 float minDepthBounds
,
3113 float maxDepthBounds
)
3115 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3117 cmd_buffer
->state
.dynamic
.depth_bounds
.min
= minDepthBounds
;
3118 cmd_buffer
->state
.dynamic
.depth_bounds
.max
= maxDepthBounds
;
3120 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
3123 void radv_CmdSetStencilCompareMask(
3124 VkCommandBuffer commandBuffer
,
3125 VkStencilFaceFlags faceMask
,
3126 uint32_t compareMask
)
3128 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3130 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
3131 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.front
= compareMask
;
3132 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
3133 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.back
= compareMask
;
3135 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
3138 void radv_CmdSetStencilWriteMask(
3139 VkCommandBuffer commandBuffer
,
3140 VkStencilFaceFlags faceMask
,
3143 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3145 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
3146 cmd_buffer
->state
.dynamic
.stencil_write_mask
.front
= writeMask
;
3147 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
3148 cmd_buffer
->state
.dynamic
.stencil_write_mask
.back
= writeMask
;
3150 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
3153 void radv_CmdSetStencilReference(
3154 VkCommandBuffer commandBuffer
,
3155 VkStencilFaceFlags faceMask
,
3158 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3160 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
3161 cmd_buffer
->state
.dynamic
.stencil_reference
.front
= reference
;
3162 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
3163 cmd_buffer
->state
.dynamic
.stencil_reference
.back
= reference
;
3165 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
3168 void radv_CmdSetDiscardRectangleEXT(
3169 VkCommandBuffer commandBuffer
,
3170 uint32_t firstDiscardRectangle
,
3171 uint32_t discardRectangleCount
,
3172 const VkRect2D
* pDiscardRectangles
)
3174 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3175 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3176 MAYBE_UNUSED
const uint32_t total_count
= firstDiscardRectangle
+ discardRectangleCount
;
3178 assert(firstDiscardRectangle
< MAX_DISCARD_RECTANGLES
);
3179 assert(total_count
>= 1 && total_count
<= MAX_DISCARD_RECTANGLES
);
3181 typed_memcpy(&state
->dynamic
.discard_rectangle
.rectangles
[firstDiscardRectangle
],
3182 pDiscardRectangles
, discardRectangleCount
);
3184 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
;
3187 void radv_CmdExecuteCommands(
3188 VkCommandBuffer commandBuffer
,
3189 uint32_t commandBufferCount
,
3190 const VkCommandBuffer
* pCmdBuffers
)
3192 RADV_FROM_HANDLE(radv_cmd_buffer
, primary
, commandBuffer
);
3194 assert(commandBufferCount
> 0);
3196 /* Emit pending flushes on primary prior to executing secondary */
3197 si_emit_cache_flush(primary
);
3199 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
3200 RADV_FROM_HANDLE(radv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
3202 primary
->scratch_size_needed
= MAX2(primary
->scratch_size_needed
,
3203 secondary
->scratch_size_needed
);
3204 primary
->compute_scratch_size_needed
= MAX2(primary
->compute_scratch_size_needed
,
3205 secondary
->compute_scratch_size_needed
);
3207 if (secondary
->esgs_ring_size_needed
> primary
->esgs_ring_size_needed
)
3208 primary
->esgs_ring_size_needed
= secondary
->esgs_ring_size_needed
;
3209 if (secondary
->gsvs_ring_size_needed
> primary
->gsvs_ring_size_needed
)
3210 primary
->gsvs_ring_size_needed
= secondary
->gsvs_ring_size_needed
;
3211 if (secondary
->tess_rings_needed
)
3212 primary
->tess_rings_needed
= true;
3213 if (secondary
->sample_positions_needed
)
3214 primary
->sample_positions_needed
= true;
3216 primary
->device
->ws
->cs_execute_secondary(primary
->cs
, secondary
->cs
);
3219 /* When the secondary command buffer is compute only we don't
3220 * need to re-emit the current graphics pipeline.
3222 if (secondary
->state
.emitted_pipeline
) {
3223 primary
->state
.emitted_pipeline
=
3224 secondary
->state
.emitted_pipeline
;
3227 /* When the secondary command buffer is graphics only we don't
3228 * need to re-emit the current compute pipeline.
3230 if (secondary
->state
.emitted_compute_pipeline
) {
3231 primary
->state
.emitted_compute_pipeline
=
3232 secondary
->state
.emitted_compute_pipeline
;
3235 /* Only re-emit the draw packets when needed. */
3236 if (secondary
->state
.last_primitive_reset_en
!= -1) {
3237 primary
->state
.last_primitive_reset_en
=
3238 secondary
->state
.last_primitive_reset_en
;
3241 if (secondary
->state
.last_primitive_reset_index
) {
3242 primary
->state
.last_primitive_reset_index
=
3243 secondary
->state
.last_primitive_reset_index
;
3246 if (secondary
->state
.last_ia_multi_vgt_param
) {
3247 primary
->state
.last_ia_multi_vgt_param
=
3248 secondary
->state
.last_ia_multi_vgt_param
;
3251 primary
->state
.last_first_instance
= secondary
->state
.last_first_instance
;
3252 primary
->state
.last_num_instances
= secondary
->state
.last_num_instances
;
3253 primary
->state
.last_vertex_offset
= secondary
->state
.last_vertex_offset
;
3255 if (secondary
->state
.last_index_type
!= -1) {
3256 primary
->state
.last_index_type
=
3257 secondary
->state
.last_index_type
;
3261 /* After executing commands from secondary buffers we have to dirty
3264 primary
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
|
3265 RADV_CMD_DIRTY_INDEX_BUFFER
|
3266 RADV_CMD_DIRTY_DYNAMIC_ALL
;
3267 radv_mark_descriptor_sets_dirty(primary
, VK_PIPELINE_BIND_POINT_GRAPHICS
);
3268 radv_mark_descriptor_sets_dirty(primary
, VK_PIPELINE_BIND_POINT_COMPUTE
);
3271 VkResult
radv_CreateCommandPool(
3273 const VkCommandPoolCreateInfo
* pCreateInfo
,
3274 const VkAllocationCallbacks
* pAllocator
,
3275 VkCommandPool
* pCmdPool
)
3277 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3278 struct radv_cmd_pool
*pool
;
3280 pool
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
3281 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3283 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3286 pool
->alloc
= *pAllocator
;
3288 pool
->alloc
= device
->alloc
;
3290 list_inithead(&pool
->cmd_buffers
);
3291 list_inithead(&pool
->free_cmd_buffers
);
3293 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
3295 *pCmdPool
= radv_cmd_pool_to_handle(pool
);
3301 void radv_DestroyCommandPool(
3303 VkCommandPool commandPool
,
3304 const VkAllocationCallbacks
* pAllocator
)
3306 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3307 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
3312 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
3313 &pool
->cmd_buffers
, pool_link
) {
3314 radv_cmd_buffer_destroy(cmd_buffer
);
3317 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
3318 &pool
->free_cmd_buffers
, pool_link
) {
3319 radv_cmd_buffer_destroy(cmd_buffer
);
3322 vk_free2(&device
->alloc
, pAllocator
, pool
);
3325 VkResult
radv_ResetCommandPool(
3327 VkCommandPool commandPool
,
3328 VkCommandPoolResetFlags flags
)
3330 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
3333 list_for_each_entry(struct radv_cmd_buffer
, cmd_buffer
,
3334 &pool
->cmd_buffers
, pool_link
) {
3335 result
= radv_reset_cmd_buffer(cmd_buffer
);
3336 if (result
!= VK_SUCCESS
)
3343 void radv_TrimCommandPool(
3345 VkCommandPool commandPool
,
3346 VkCommandPoolTrimFlags flags
)
3348 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
3353 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
3354 &pool
->free_cmd_buffers
, pool_link
) {
3355 radv_cmd_buffer_destroy(cmd_buffer
);
3359 void radv_CmdBeginRenderPass(
3360 VkCommandBuffer commandBuffer
,
3361 const VkRenderPassBeginInfo
* pRenderPassBegin
,
3362 VkSubpassContents contents
)
3364 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3365 RADV_FROM_HANDLE(radv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
3366 RADV_FROM_HANDLE(radv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
3368 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
3369 cmd_buffer
->cs
, 2048);
3370 MAYBE_UNUSED VkResult result
;
3372 cmd_buffer
->state
.framebuffer
= framebuffer
;
3373 cmd_buffer
->state
.pass
= pass
;
3374 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
3376 result
= radv_cmd_state_setup_attachments(cmd_buffer
, pass
, pRenderPassBegin
);
3377 if (result
!= VK_SUCCESS
)
3380 radv_cmd_buffer_set_subpass(cmd_buffer
, pass
->subpasses
, true);
3381 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3383 radv_cmd_buffer_clear_subpass(cmd_buffer
);
3386 void radv_CmdBeginRenderPass2KHR(
3387 VkCommandBuffer commandBuffer
,
3388 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
3389 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
3391 radv_CmdBeginRenderPass(commandBuffer
, pRenderPassBeginInfo
,
3392 pSubpassBeginInfo
->contents
);
3395 void radv_CmdNextSubpass(
3396 VkCommandBuffer commandBuffer
,
3397 VkSubpassContents contents
)
3399 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3401 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
3403 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
3406 radv_cmd_buffer_set_subpass(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1, true);
3407 radv_cmd_buffer_clear_subpass(cmd_buffer
);
3410 void radv_CmdNextSubpass2KHR(
3411 VkCommandBuffer commandBuffer
,
3412 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
3413 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
3415 radv_CmdNextSubpass(commandBuffer
, pSubpassBeginInfo
->contents
);
3418 static void radv_emit_view_index(struct radv_cmd_buffer
*cmd_buffer
, unsigned index
)
3420 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
3421 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
3422 if (!radv_get_shader(pipeline
, stage
))
3425 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, AC_UD_VIEW_INDEX
);
3426 if (loc
->sgpr_idx
== -1)
3428 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
3429 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
3432 if (pipeline
->gs_copy_shader
) {
3433 struct radv_userdata_info
*loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_VIEW_INDEX
];
3434 if (loc
->sgpr_idx
!= -1) {
3435 uint32_t base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3436 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
3442 radv_cs_emit_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
3443 uint32_t vertex_count
,
3446 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, cmd_buffer
->state
.predicating
));
3447 radeon_emit(cmd_buffer
->cs
, vertex_count
);
3448 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
3449 S_0287F0_USE_OPAQUE(use_opaque
));
3453 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer
*cmd_buffer
,
3455 uint32_t index_count
)
3457 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, cmd_buffer
->state
.predicating
));
3458 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.max_index_count
);
3459 radeon_emit(cmd_buffer
->cs
, index_va
);
3460 radeon_emit(cmd_buffer
->cs
, index_va
>> 32);
3461 radeon_emit(cmd_buffer
->cs
, index_count
);
3462 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_DMA
);
3466 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
3468 uint32_t draw_count
,
3472 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
3473 unsigned di_src_sel
= indexed
? V_0287F0_DI_SRC_SEL_DMA
3474 : V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
3475 bool draw_id_enable
= radv_get_shader(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
)->info
.info
.vs
.needs_draw_id
;
3476 uint32_t base_reg
= cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
;
3477 bool predicating
= cmd_buffer
->state
.predicating
;
3480 /* just reset draw state for vertex data */
3481 cmd_buffer
->state
.last_first_instance
= -1;
3482 cmd_buffer
->state
.last_num_instances
= -1;
3483 cmd_buffer
->state
.last_vertex_offset
= -1;
3485 if (draw_count
== 1 && !count_va
&& !draw_id_enable
) {
3486 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT
:
3487 PKT3_DRAW_INDIRECT
, 3, predicating
));
3489 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
3490 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
3491 radeon_emit(cs
, di_src_sel
);
3493 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT_MULTI
:
3494 PKT3_DRAW_INDIRECT_MULTI
,
3497 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
3498 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
3499 radeon_emit(cs
, (((base_reg
+ 8) - SI_SH_REG_OFFSET
) >> 2) |
3500 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable
) |
3501 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va
));
3502 radeon_emit(cs
, draw_count
); /* count */
3503 radeon_emit(cs
, count_va
); /* count_addr */
3504 radeon_emit(cs
, count_va
>> 32);
3505 radeon_emit(cs
, stride
); /* stride */
3506 radeon_emit(cs
, di_src_sel
);
3511 radv_emit_draw_packets(struct radv_cmd_buffer
*cmd_buffer
,
3512 const struct radv_draw_info
*info
)
3514 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3515 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
3516 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
3518 if (info
->indirect
) {
3519 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
3520 uint64_t count_va
= 0;
3522 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
3524 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
);
3526 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
3528 radeon_emit(cs
, va
);
3529 radeon_emit(cs
, va
>> 32);
3531 if (info
->count_buffer
) {
3532 count_va
= radv_buffer_get_va(info
->count_buffer
->bo
);
3533 count_va
+= info
->count_buffer
->offset
+
3534 info
->count_buffer_offset
;
3536 radv_cs_add_buffer(ws
, cs
, info
->count_buffer
->bo
);
3539 if (!state
->subpass
->view_mask
) {
3540 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
3547 for_each_bit(i
, state
->subpass
->view_mask
) {
3548 radv_emit_view_index(cmd_buffer
, i
);
3550 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
3558 assert(state
->pipeline
->graphics
.vtx_base_sgpr
);
3560 if (info
->vertex_offset
!= state
->last_vertex_offset
||
3561 info
->first_instance
!= state
->last_first_instance
) {
3562 radeon_set_sh_reg_seq(cs
, state
->pipeline
->graphics
.vtx_base_sgpr
,
3563 state
->pipeline
->graphics
.vtx_emit_num
);
3565 radeon_emit(cs
, info
->vertex_offset
);
3566 radeon_emit(cs
, info
->first_instance
);
3567 if (state
->pipeline
->graphics
.vtx_emit_num
== 3)
3569 state
->last_first_instance
= info
->first_instance
;
3570 state
->last_vertex_offset
= info
->vertex_offset
;
3573 if (state
->last_num_instances
!= info
->instance_count
) {
3574 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, false));
3575 radeon_emit(cs
, info
->instance_count
);
3576 state
->last_num_instances
= info
->instance_count
;
3579 if (info
->indexed
) {
3580 int index_size
= state
->index_type
? 4 : 2;
3583 index_va
= state
->index_va
;
3584 index_va
+= info
->first_index
* index_size
;
3586 if (!state
->subpass
->view_mask
) {
3587 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
3592 for_each_bit(i
, state
->subpass
->view_mask
) {
3593 radv_emit_view_index(cmd_buffer
, i
);
3595 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
3601 if (!state
->subpass
->view_mask
) {
3602 radv_cs_emit_draw_packet(cmd_buffer
,
3604 !!info
->strmout_buffer
);
3607 for_each_bit(i
, state
->subpass
->view_mask
) {
3608 radv_emit_view_index(cmd_buffer
, i
);
3610 radv_cs_emit_draw_packet(cmd_buffer
,
3612 !!info
->strmout_buffer
);
3620 * Vega and raven have a bug which triggers if there are multiple context
3621 * register contexts active at the same time with different scissor values.
3623 * There are two possible workarounds:
3624 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3625 * there is only ever 1 active set of scissor values at the same time.
3627 * 2) Whenever the hardware switches contexts we have to set the scissor
3628 * registers again even if it is a noop. That way the new context gets
3629 * the correct scissor values.
3631 * This implements option 2. radv_need_late_scissor_emission needs to
3632 * return true on affected HW if radv_emit_all_graphics_states sets
3633 * any context registers.
3635 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer
*cmd_buffer
,
3636 const struct radv_draw_info
*info
)
3638 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3640 if (!cmd_buffer
->device
->physical_device
->has_scissor_bug
)
3643 if (cmd_buffer
->state
.context_roll_without_scissor_emitted
|| info
->strmout_buffer
)
3646 uint32_t used_states
= cmd_buffer
->state
.pipeline
->graphics
.needed_dynamic_state
| ~RADV_CMD_DIRTY_DYNAMIC_ALL
;
3648 /* Index, vertex and streamout buffers don't change context regs, and
3649 * pipeline is already handled.
3651 used_states
&= ~(RADV_CMD_DIRTY_INDEX_BUFFER
|
3652 RADV_CMD_DIRTY_VERTEX_BUFFER
|
3653 RADV_CMD_DIRTY_STREAMOUT_BUFFER
|
3654 RADV_CMD_DIRTY_PIPELINE
);
3656 if (cmd_buffer
->state
.dirty
& used_states
)
3659 if (info
->indexed
&& state
->pipeline
->graphics
.prim_restart_enable
&&
3660 (state
->index_type
? 0xffffffffu
: 0xffffu
) != state
->last_primitive_reset_index
)
3667 radv_emit_all_graphics_states(struct radv_cmd_buffer
*cmd_buffer
,
3668 const struct radv_draw_info
*info
)
3670 bool late_scissor_emission
;
3672 if ((cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
) ||
3673 cmd_buffer
->state
.emitted_pipeline
!= cmd_buffer
->state
.pipeline
)
3674 radv_emit_rbplus_state(cmd_buffer
);
3676 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
)
3677 radv_emit_graphics_pipeline(cmd_buffer
);
3679 /* This should be before the cmd_buffer->state.dirty is cleared
3680 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
3681 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
3682 late_scissor_emission
=
3683 radv_need_late_scissor_emission(cmd_buffer
, info
);
3685 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
)
3686 radv_emit_framebuffer_state(cmd_buffer
);
3688 if (info
->indexed
) {
3689 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_INDEX_BUFFER
)
3690 radv_emit_index_buffer(cmd_buffer
);
3692 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3693 * so the state must be re-emitted before the next indexed
3696 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
3697 cmd_buffer
->state
.last_index_type
= -1;
3698 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
3702 radv_cmd_buffer_flush_dynamic_state(cmd_buffer
);
3704 radv_emit_draw_registers(cmd_buffer
, info
);
3706 if (late_scissor_emission
)
3707 radv_emit_scissor(cmd_buffer
);
3711 radv_draw(struct radv_cmd_buffer
*cmd_buffer
,
3712 const struct radv_draw_info
*info
)
3714 struct radeon_info
*rad_info
=
3715 &cmd_buffer
->device
->physical_device
->rad_info
;
3717 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
;
3718 bool pipeline_is_dirty
=
3719 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
) &&
3720 cmd_buffer
->state
.pipeline
!= cmd_buffer
->state
.emitted_pipeline
;
3722 MAYBE_UNUSED
unsigned cdw_max
=
3723 radeon_check_space(cmd_buffer
->device
->ws
,
3724 cmd_buffer
->cs
, 4096);
3726 if (likely(!info
->indirect
)) {
3727 /* SI-CI treat instance_count==0 as instance_count==1. There is
3728 * no workaround for indirect draws, but we can at least skip
3731 if (unlikely(!info
->instance_count
))
3734 /* Handle count == 0. */
3735 if (unlikely(!info
->count
&& !info
->strmout_buffer
))
3739 /* Use optimal packet order based on whether we need to sync the
3742 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3743 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3744 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
3745 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
3746 /* If we have to wait for idle, set all states first, so that
3747 * all SET packets are processed in parallel with previous draw
3748 * calls. Then upload descriptors, set shader pointers, and
3749 * draw, and prefetch at the end. This ensures that the time
3750 * the CUs are idle is very short. (there are only SET_SH
3751 * packets between the wait and the draw)
3753 radv_emit_all_graphics_states(cmd_buffer
, info
);
3754 si_emit_cache_flush(cmd_buffer
);
3755 /* <-- CUs are idle here --> */
3757 radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
);
3759 radv_emit_draw_packets(cmd_buffer
, info
);
3760 /* <-- CUs are busy here --> */
3762 /* Start prefetches after the draw has been started. Both will
3763 * run in parallel, but starting the draw first is more
3766 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
3767 radv_emit_prefetch_L2(cmd_buffer
,
3768 cmd_buffer
->state
.pipeline
, false);
3771 /* If we don't wait for idle, start prefetches first, then set
3772 * states, and draw at the end.
3774 si_emit_cache_flush(cmd_buffer
);
3776 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
3777 /* Only prefetch the vertex shader and VBO descriptors
3778 * in order to start the draw as soon as possible.
3780 radv_emit_prefetch_L2(cmd_buffer
,
3781 cmd_buffer
->state
.pipeline
, true);
3784 radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
);
3786 radv_emit_all_graphics_states(cmd_buffer
, info
);
3787 radv_emit_draw_packets(cmd_buffer
, info
);
3789 /* Prefetch the remaining shaders after the draw has been
3792 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
3793 radv_emit_prefetch_L2(cmd_buffer
,
3794 cmd_buffer
->state
.pipeline
, false);
3798 /* Workaround for a VGT hang when streamout is enabled.
3799 * It must be done after drawing.
3801 if (cmd_buffer
->state
.streamout
.streamout_enabled
&&
3802 (rad_info
->family
== CHIP_HAWAII
||
3803 rad_info
->family
== CHIP_TONGA
||
3804 rad_info
->family
== CHIP_FIJI
)) {
3805 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
;
3808 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3809 radv_cmd_buffer_after_draw(cmd_buffer
, RADV_CMD_FLAG_PS_PARTIAL_FLUSH
);
3813 VkCommandBuffer commandBuffer
,
3814 uint32_t vertexCount
,
3815 uint32_t instanceCount
,
3816 uint32_t firstVertex
,
3817 uint32_t firstInstance
)
3819 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3820 struct radv_draw_info info
= {};
3822 info
.count
= vertexCount
;
3823 info
.instance_count
= instanceCount
;
3824 info
.first_instance
= firstInstance
;
3825 info
.vertex_offset
= firstVertex
;
3827 radv_draw(cmd_buffer
, &info
);
3830 void radv_CmdDrawIndexed(
3831 VkCommandBuffer commandBuffer
,
3832 uint32_t indexCount
,
3833 uint32_t instanceCount
,
3834 uint32_t firstIndex
,
3835 int32_t vertexOffset
,
3836 uint32_t firstInstance
)
3838 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3839 struct radv_draw_info info
= {};
3841 info
.indexed
= true;
3842 info
.count
= indexCount
;
3843 info
.instance_count
= instanceCount
;
3844 info
.first_index
= firstIndex
;
3845 info
.vertex_offset
= vertexOffset
;
3846 info
.first_instance
= firstInstance
;
3848 radv_draw(cmd_buffer
, &info
);
3851 void radv_CmdDrawIndirect(
3852 VkCommandBuffer commandBuffer
,
3854 VkDeviceSize offset
,
3858 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3859 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3860 struct radv_draw_info info
= {};
3862 info
.count
= drawCount
;
3863 info
.indirect
= buffer
;
3864 info
.indirect_offset
= offset
;
3865 info
.stride
= stride
;
3867 radv_draw(cmd_buffer
, &info
);
3870 void radv_CmdDrawIndexedIndirect(
3871 VkCommandBuffer commandBuffer
,
3873 VkDeviceSize offset
,
3877 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3878 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3879 struct radv_draw_info info
= {};
3881 info
.indexed
= true;
3882 info
.count
= drawCount
;
3883 info
.indirect
= buffer
;
3884 info
.indirect_offset
= offset
;
3885 info
.stride
= stride
;
3887 radv_draw(cmd_buffer
, &info
);
3890 void radv_CmdDrawIndirectCountAMD(
3891 VkCommandBuffer commandBuffer
,
3893 VkDeviceSize offset
,
3894 VkBuffer _countBuffer
,
3895 VkDeviceSize countBufferOffset
,
3896 uint32_t maxDrawCount
,
3899 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3900 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3901 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
3902 struct radv_draw_info info
= {};
3904 info
.count
= maxDrawCount
;
3905 info
.indirect
= buffer
;
3906 info
.indirect_offset
= offset
;
3907 info
.count_buffer
= count_buffer
;
3908 info
.count_buffer_offset
= countBufferOffset
;
3909 info
.stride
= stride
;
3911 radv_draw(cmd_buffer
, &info
);
3914 void radv_CmdDrawIndexedIndirectCountAMD(
3915 VkCommandBuffer commandBuffer
,
3917 VkDeviceSize offset
,
3918 VkBuffer _countBuffer
,
3919 VkDeviceSize countBufferOffset
,
3920 uint32_t maxDrawCount
,
3923 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3924 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3925 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
3926 struct radv_draw_info info
= {};
3928 info
.indexed
= true;
3929 info
.count
= maxDrawCount
;
3930 info
.indirect
= buffer
;
3931 info
.indirect_offset
= offset
;
3932 info
.count_buffer
= count_buffer
;
3933 info
.count_buffer_offset
= countBufferOffset
;
3934 info
.stride
= stride
;
3936 radv_draw(cmd_buffer
, &info
);
3939 void radv_CmdDrawIndirectCountKHR(
3940 VkCommandBuffer commandBuffer
,
3942 VkDeviceSize offset
,
3943 VkBuffer _countBuffer
,
3944 VkDeviceSize countBufferOffset
,
3945 uint32_t maxDrawCount
,
3948 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3949 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3950 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
3951 struct radv_draw_info info
= {};
3953 info
.count
= maxDrawCount
;
3954 info
.indirect
= buffer
;
3955 info
.indirect_offset
= offset
;
3956 info
.count_buffer
= count_buffer
;
3957 info
.count_buffer_offset
= countBufferOffset
;
3958 info
.stride
= stride
;
3960 radv_draw(cmd_buffer
, &info
);
3963 void radv_CmdDrawIndexedIndirectCountKHR(
3964 VkCommandBuffer commandBuffer
,
3966 VkDeviceSize offset
,
3967 VkBuffer _countBuffer
,
3968 VkDeviceSize countBufferOffset
,
3969 uint32_t maxDrawCount
,
3972 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3973 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3974 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
3975 struct radv_draw_info info
= {};
3977 info
.indexed
= true;
3978 info
.count
= maxDrawCount
;
3979 info
.indirect
= buffer
;
3980 info
.indirect_offset
= offset
;
3981 info
.count_buffer
= count_buffer
;
3982 info
.count_buffer_offset
= countBufferOffset
;
3983 info
.stride
= stride
;
3985 radv_draw(cmd_buffer
, &info
);
3988 struct radv_dispatch_info
{
3990 * Determine the layout of the grid (in block units) to be used.
3995 * A starting offset for the grid. If unaligned is set, the offset
3996 * must still be aligned.
3998 uint32_t offsets
[3];
4000 * Whether it's an unaligned compute dispatch.
4005 * Indirect compute parameters resource.
4007 struct radv_buffer
*indirect
;
4008 uint64_t indirect_offset
;
4012 radv_emit_dispatch_packets(struct radv_cmd_buffer
*cmd_buffer
,
4013 const struct radv_dispatch_info
*info
)
4015 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
4016 struct radv_shader_variant
*compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
4017 unsigned dispatch_initiator
= cmd_buffer
->device
->dispatch_initiator
;
4018 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
4019 bool predicating
= cmd_buffer
->state
.predicating
;
4020 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4021 struct radv_userdata_info
*loc
;
4023 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_COMPUTE
,
4024 AC_UD_CS_GRID_SIZE
);
4026 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(ws
, cs
, 25);
4028 if (info
->indirect
) {
4029 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
4031 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
4033 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
);
4035 if (loc
->sgpr_idx
!= -1) {
4036 for (unsigned i
= 0; i
< 3; ++i
) {
4037 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
4038 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
4039 COPY_DATA_DST_SEL(COPY_DATA_REG
));
4040 radeon_emit(cs
, (va
+ 4 * i
));
4041 radeon_emit(cs
, (va
+ 4 * i
) >> 32);
4042 radeon_emit(cs
, ((R_00B900_COMPUTE_USER_DATA_0
4043 + loc
->sgpr_idx
* 4) >> 2) + i
);
4048 if (radv_cmd_buffer_uses_mec(cmd_buffer
)) {
4049 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 2, predicating
) |
4050 PKT3_SHADER_TYPE_S(1));
4051 radeon_emit(cs
, va
);
4052 radeon_emit(cs
, va
>> 32);
4053 radeon_emit(cs
, dispatch_initiator
);
4055 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0) |
4056 PKT3_SHADER_TYPE_S(1));
4058 radeon_emit(cs
, va
);
4059 radeon_emit(cs
, va
>> 32);
4061 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 1, predicating
) |
4062 PKT3_SHADER_TYPE_S(1));
4064 radeon_emit(cs
, dispatch_initiator
);
4067 unsigned blocks
[3] = { info
->blocks
[0], info
->blocks
[1], info
->blocks
[2] };
4068 unsigned offsets
[3] = { info
->offsets
[0], info
->offsets
[1], info
->offsets
[2] };
4070 if (info
->unaligned
) {
4071 unsigned *cs_block_size
= compute_shader
->info
.cs
.block_size
;
4072 unsigned remainder
[3];
4074 /* If aligned, these should be an entire block size,
4077 remainder
[0] = blocks
[0] + cs_block_size
[0] -
4078 align_u32_npot(blocks
[0], cs_block_size
[0]);
4079 remainder
[1] = blocks
[1] + cs_block_size
[1] -
4080 align_u32_npot(blocks
[1], cs_block_size
[1]);
4081 remainder
[2] = blocks
[2] + cs_block_size
[2] -
4082 align_u32_npot(blocks
[2], cs_block_size
[2]);
4084 blocks
[0] = round_up_u32(blocks
[0], cs_block_size
[0]);
4085 blocks
[1] = round_up_u32(blocks
[1], cs_block_size
[1]);
4086 blocks
[2] = round_up_u32(blocks
[2], cs_block_size
[2]);
4088 for(unsigned i
= 0; i
< 3; ++i
) {
4089 assert(offsets
[i
] % cs_block_size
[i
] == 0);
4090 offsets
[i
] /= cs_block_size
[i
];
4093 radeon_set_sh_reg_seq(cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
4095 S_00B81C_NUM_THREAD_FULL(cs_block_size
[0]) |
4096 S_00B81C_NUM_THREAD_PARTIAL(remainder
[0]));
4098 S_00B81C_NUM_THREAD_FULL(cs_block_size
[1]) |
4099 S_00B81C_NUM_THREAD_PARTIAL(remainder
[1]));
4101 S_00B81C_NUM_THREAD_FULL(cs_block_size
[2]) |
4102 S_00B81C_NUM_THREAD_PARTIAL(remainder
[2]));
4104 dispatch_initiator
|= S_00B800_PARTIAL_TG_EN(1);
4107 if (loc
->sgpr_idx
!= -1) {
4108 assert(!loc
->indirect
);
4109 assert(loc
->num_sgprs
== 3);
4111 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
4112 loc
->sgpr_idx
* 4, 3);
4113 radeon_emit(cs
, blocks
[0]);
4114 radeon_emit(cs
, blocks
[1]);
4115 radeon_emit(cs
, blocks
[2]);
4118 if (offsets
[0] || offsets
[1] || offsets
[2]) {
4119 radeon_set_sh_reg_seq(cs
, R_00B810_COMPUTE_START_X
, 3);
4120 radeon_emit(cs
, offsets
[0]);
4121 radeon_emit(cs
, offsets
[1]);
4122 radeon_emit(cs
, offsets
[2]);
4124 /* The blocks in the packet are not counts but end values. */
4125 for (unsigned i
= 0; i
< 3; ++i
)
4126 blocks
[i
] += offsets
[i
];
4128 dispatch_initiator
|= S_00B800_FORCE_START_AT_000(1);
4131 radeon_emit(cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, predicating
) |
4132 PKT3_SHADER_TYPE_S(1));
4133 radeon_emit(cs
, blocks
[0]);
4134 radeon_emit(cs
, blocks
[1]);
4135 radeon_emit(cs
, blocks
[2]);
4136 radeon_emit(cs
, dispatch_initiator
);
4139 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4143 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
4145 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
4146 radv_flush_constants(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
4150 radv_dispatch(struct radv_cmd_buffer
*cmd_buffer
,
4151 const struct radv_dispatch_info
*info
)
4153 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
4155 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
;
4156 bool pipeline_is_dirty
= pipeline
&&
4157 pipeline
!= cmd_buffer
->state
.emitted_compute_pipeline
;
4159 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4160 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4161 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
4162 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
4163 /* If we have to wait for idle, set all states first, so that
4164 * all SET packets are processed in parallel with previous draw
4165 * calls. Then upload descriptors, set shader pointers, and
4166 * dispatch, and prefetch at the end. This ensures that the
4167 * time the CUs are idle is very short. (there are only SET_SH
4168 * packets between the wait and the draw)
4170 radv_emit_compute_pipeline(cmd_buffer
);
4171 si_emit_cache_flush(cmd_buffer
);
4172 /* <-- CUs are idle here --> */
4174 radv_upload_compute_shader_descriptors(cmd_buffer
);
4176 radv_emit_dispatch_packets(cmd_buffer
, info
);
4177 /* <-- CUs are busy here --> */
4179 /* Start prefetches after the dispatch has been started. Both
4180 * will run in parallel, but starting the dispatch first is
4183 if (has_prefetch
&& pipeline_is_dirty
) {
4184 radv_emit_shader_prefetch(cmd_buffer
,
4185 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
4188 /* If we don't wait for idle, start prefetches first, then set
4189 * states, and dispatch at the end.
4191 si_emit_cache_flush(cmd_buffer
);
4193 if (has_prefetch
&& pipeline_is_dirty
) {
4194 radv_emit_shader_prefetch(cmd_buffer
,
4195 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
4198 radv_upload_compute_shader_descriptors(cmd_buffer
);
4200 radv_emit_compute_pipeline(cmd_buffer
);
4201 radv_emit_dispatch_packets(cmd_buffer
, info
);
4204 radv_cmd_buffer_after_draw(cmd_buffer
, RADV_CMD_FLAG_CS_PARTIAL_FLUSH
);
4207 void radv_CmdDispatchBase(
4208 VkCommandBuffer commandBuffer
,
4216 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4217 struct radv_dispatch_info info
= {};
4223 info
.offsets
[0] = base_x
;
4224 info
.offsets
[1] = base_y
;
4225 info
.offsets
[2] = base_z
;
4226 radv_dispatch(cmd_buffer
, &info
);
4229 void radv_CmdDispatch(
4230 VkCommandBuffer commandBuffer
,
4235 radv_CmdDispatchBase(commandBuffer
, 0, 0, 0, x
, y
, z
);
4238 void radv_CmdDispatchIndirect(
4239 VkCommandBuffer commandBuffer
,
4241 VkDeviceSize offset
)
4243 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4244 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4245 struct radv_dispatch_info info
= {};
4247 info
.indirect
= buffer
;
4248 info
.indirect_offset
= offset
;
4250 radv_dispatch(cmd_buffer
, &info
);
4253 void radv_unaligned_dispatch(
4254 struct radv_cmd_buffer
*cmd_buffer
,
4259 struct radv_dispatch_info info
= {};
4266 radv_dispatch(cmd_buffer
, &info
);
4269 void radv_CmdEndRenderPass(
4270 VkCommandBuffer commandBuffer
)
4272 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4274 radv_subpass_barrier(cmd_buffer
, &cmd_buffer
->state
.pass
->end_barrier
);
4276 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
4278 for (unsigned i
= 0; i
< cmd_buffer
->state
.framebuffer
->attachment_count
; ++i
) {
4279 VkImageLayout layout
= cmd_buffer
->state
.pass
->attachments
[i
].final_layout
;
4280 radv_handle_subpass_image_transition(cmd_buffer
,
4281 (struct radv_subpass_attachment
){i
, layout
});
4284 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
4286 cmd_buffer
->state
.pass
= NULL
;
4287 cmd_buffer
->state
.subpass
= NULL
;
4288 cmd_buffer
->state
.attachments
= NULL
;
4289 cmd_buffer
->state
.framebuffer
= NULL
;
4292 void radv_CmdEndRenderPass2KHR(
4293 VkCommandBuffer commandBuffer
,
4294 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4296 radv_CmdEndRenderPass(commandBuffer
);
4300 * For HTILE we have the following interesting clear words:
4301 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4302 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4303 * 0xfffffff0: Clear depth to 1.0
4304 * 0x00000000: Clear depth to 0.0
4306 static void radv_initialize_htile(struct radv_cmd_buffer
*cmd_buffer
,
4307 struct radv_image
*image
,
4308 const VkImageSubresourceRange
*range
,
4309 uint32_t clear_word
)
4311 assert(range
->baseMipLevel
== 0);
4312 assert(range
->levelCount
== 1 || range
->levelCount
== VK_REMAINING_ARRAY_LAYERS
);
4313 unsigned layer_count
= radv_get_layerCount(image
, range
);
4314 uint64_t size
= image
->surface
.htile_slice_size
* layer_count
;
4315 VkImageAspectFlags aspects
= VK_IMAGE_ASPECT_DEPTH_BIT
;
4316 uint64_t offset
= image
->offset
+ image
->htile_offset
+
4317 image
->surface
.htile_slice_size
* range
->baseArrayLayer
;
4318 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4319 VkClearDepthStencilValue value
= {};
4321 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4322 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4324 state
->flush_bits
|= radv_fill_buffer(cmd_buffer
, image
->bo
, offset
,
4327 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4329 if (vk_format_is_stencil(image
->vk_format
))
4330 aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
4332 radv_set_ds_clear_metadata(cmd_buffer
, image
, value
, aspects
);
4334 if (radv_image_is_tc_compat_htile(image
)) {
4335 /* Initialize the TC-compat metada value to 0 because by
4336 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
4337 * need have to conditionally update its value when performing
4338 * a fast depth clear.
4340 radv_set_tc_compat_zrange_metadata(cmd_buffer
, image
, 0);
4344 static void radv_handle_depth_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
4345 struct radv_image
*image
,
4346 VkImageLayout src_layout
,
4347 VkImageLayout dst_layout
,
4348 unsigned src_queue_mask
,
4349 unsigned dst_queue_mask
,
4350 const VkImageSubresourceRange
*range
)
4352 if (!radv_image_has_htile(image
))
4355 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
&&
4356 radv_layout_has_htile(image
, dst_layout
, dst_queue_mask
)) {
4357 /* TODO: merge with the clear if applicable */
4358 radv_initialize_htile(cmd_buffer
, image
, range
, 0);
4359 } else if (!radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
4360 radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
4361 uint32_t clear_value
= vk_format_is_stencil(image
->vk_format
) ? 0xfffff30f : 0xfffc000f;
4362 radv_initialize_htile(cmd_buffer
, image
, range
, clear_value
);
4363 } else if (radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
4364 !radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
4365 VkImageSubresourceRange local_range
= *range
;
4366 local_range
.aspectMask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
4367 local_range
.baseMipLevel
= 0;
4368 local_range
.levelCount
= 1;
4370 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4371 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4373 radv_decompress_depth_image_inplace(cmd_buffer
, image
, &local_range
);
4375 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4376 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4380 static void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
4381 struct radv_image
*image
, uint32_t value
)
4383 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4385 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4386 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4388 state
->flush_bits
|= radv_clear_cmask(cmd_buffer
, image
, value
);
4390 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4393 void radv_initialize_fmask(struct radv_cmd_buffer
*cmd_buffer
,
4394 struct radv_image
*image
)
4396 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4397 static const uint32_t fmask_clear_values
[4] = {
4403 uint32_t log2_samples
= util_logbase2(image
->info
.samples
);
4404 uint32_t value
= fmask_clear_values
[log2_samples
];
4406 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4407 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4409 state
->flush_bits
|= radv_clear_fmask(cmd_buffer
, image
, value
);
4411 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4414 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
4415 struct radv_image
*image
, uint32_t value
)
4417 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4419 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4420 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4422 state
->flush_bits
|= radv_clear_dcc(cmd_buffer
, image
, value
);
4424 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4425 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4429 * Initialize DCC/FMASK/CMASK metadata for a color image.
4431 static void radv_init_color_image_metadata(struct radv_cmd_buffer
*cmd_buffer
,
4432 struct radv_image
*image
,
4433 VkImageLayout src_layout
,
4434 VkImageLayout dst_layout
,
4435 unsigned src_queue_mask
,
4436 unsigned dst_queue_mask
)
4438 if (radv_image_has_cmask(image
)) {
4439 uint32_t value
= 0xffffffffu
; /* Fully expanded mode. */
4441 /* TODO: clarify this. */
4442 if (radv_image_has_fmask(image
)) {
4443 value
= 0xccccccccu
;
4446 radv_initialise_cmask(cmd_buffer
, image
, value
);
4449 if (radv_image_has_fmask(image
)) {
4450 radv_initialize_fmask(cmd_buffer
, image
);
4453 if (radv_image_has_dcc(image
)) {
4454 uint32_t value
= 0xffffffffu
; /* Fully expanded mode. */
4455 bool need_decompress_pass
= false;
4457 if (radv_layout_dcc_compressed(image
, dst_layout
,
4459 value
= 0x20202020u
;
4460 need_decompress_pass
= true;
4463 radv_initialize_dcc(cmd_buffer
, image
, value
);
4465 radv_update_fce_metadata(cmd_buffer
, image
,
4466 need_decompress_pass
);
4469 if (radv_image_has_cmask(image
) || radv_image_has_dcc(image
)) {
4470 uint32_t color_values
[2] = {};
4471 radv_set_color_clear_metadata(cmd_buffer
, image
, color_values
);
4476 * Handle color image transitions for DCC/FMASK/CMASK.
4478 static void radv_handle_color_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
4479 struct radv_image
*image
,
4480 VkImageLayout src_layout
,
4481 VkImageLayout dst_layout
,
4482 unsigned src_queue_mask
,
4483 unsigned dst_queue_mask
,
4484 const VkImageSubresourceRange
*range
)
4486 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
4487 radv_init_color_image_metadata(cmd_buffer
, image
,
4488 src_layout
, dst_layout
,
4489 src_queue_mask
, dst_queue_mask
);
4493 if (radv_image_has_dcc(image
)) {
4494 if (src_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
4495 radv_initialize_dcc(cmd_buffer
, image
, 0xffffffffu
);
4496 } else if (radv_layout_dcc_compressed(image
, src_layout
, src_queue_mask
) &&
4497 !radv_layout_dcc_compressed(image
, dst_layout
, dst_queue_mask
)) {
4498 radv_decompress_dcc(cmd_buffer
, image
, range
);
4499 } else if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
4500 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
4501 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
4503 } else if (radv_image_has_cmask(image
) || radv_image_has_fmask(image
)) {
4504 if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
4505 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
4506 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
4509 if (radv_image_has_fmask(image
)) {
4510 if (src_layout
!= VK_IMAGE_LAYOUT_GENERAL
&&
4511 dst_layout
== VK_IMAGE_LAYOUT_GENERAL
) {
4512 radv_expand_fmask_image_inplace(cmd_buffer
, image
, range
);
4518 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
4519 struct radv_image
*image
,
4520 VkImageLayout src_layout
,
4521 VkImageLayout dst_layout
,
4522 uint32_t src_family
,
4523 uint32_t dst_family
,
4524 const VkImageSubresourceRange
*range
)
4526 if (image
->exclusive
&& src_family
!= dst_family
) {
4527 /* This is an acquire or a release operation and there will be
4528 * a corresponding release/acquire. Do the transition in the
4529 * most flexible queue. */
4531 assert(src_family
== cmd_buffer
->queue_family_index
||
4532 dst_family
== cmd_buffer
->queue_family_index
);
4534 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_TRANSFER
)
4537 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
4538 (src_family
== RADV_QUEUE_GENERAL
||
4539 dst_family
== RADV_QUEUE_GENERAL
))
4543 unsigned src_queue_mask
=
4544 radv_image_queue_family_mask(image
, src_family
,
4545 cmd_buffer
->queue_family_index
);
4546 unsigned dst_queue_mask
=
4547 radv_image_queue_family_mask(image
, dst_family
,
4548 cmd_buffer
->queue_family_index
);
4550 if (vk_format_is_depth(image
->vk_format
)) {
4551 radv_handle_depth_image_transition(cmd_buffer
, image
,
4552 src_layout
, dst_layout
,
4553 src_queue_mask
, dst_queue_mask
,
4556 radv_handle_color_image_transition(cmd_buffer
, image
,
4557 src_layout
, dst_layout
,
4558 src_queue_mask
, dst_queue_mask
,
4563 struct radv_barrier_info
{
4564 uint32_t eventCount
;
4565 const VkEvent
*pEvents
;
4566 VkPipelineStageFlags srcStageMask
;
4570 radv_barrier(struct radv_cmd_buffer
*cmd_buffer
,
4571 uint32_t memoryBarrierCount
,
4572 const VkMemoryBarrier
*pMemoryBarriers
,
4573 uint32_t bufferMemoryBarrierCount
,
4574 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
4575 uint32_t imageMemoryBarrierCount
,
4576 const VkImageMemoryBarrier
*pImageMemoryBarriers
,
4577 const struct radv_barrier_info
*info
)
4579 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4580 enum radv_cmd_flush_bits src_flush_bits
= 0;
4581 enum radv_cmd_flush_bits dst_flush_bits
= 0;
4583 for (unsigned i
= 0; i
< info
->eventCount
; ++i
) {
4584 RADV_FROM_HANDLE(radv_event
, event
, info
->pEvents
[i
]);
4585 uint64_t va
= radv_buffer_get_va(event
->bo
);
4587 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
);
4589 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 7);
4591 radv_cp_wait_mem(cs
, WAIT_REG_MEM_EQUAL
, va
, 1, 0xffffffff);
4592 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4595 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
4596 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pMemoryBarriers
[i
].srcAccessMask
,
4598 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pMemoryBarriers
[i
].dstAccessMask
,
4602 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
4603 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].srcAccessMask
,
4605 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].dstAccessMask
,
4609 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
4610 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
4612 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].srcAccessMask
,
4614 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].dstAccessMask
,
4618 radv_stage_flush(cmd_buffer
, info
->srcStageMask
);
4619 cmd_buffer
->state
.flush_bits
|= src_flush_bits
;
4621 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
4622 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
4623 radv_handle_image_transition(cmd_buffer
, image
,
4624 pImageMemoryBarriers
[i
].oldLayout
,
4625 pImageMemoryBarriers
[i
].newLayout
,
4626 pImageMemoryBarriers
[i
].srcQueueFamilyIndex
,
4627 pImageMemoryBarriers
[i
].dstQueueFamilyIndex
,
4628 &pImageMemoryBarriers
[i
].subresourceRange
);
4631 /* Make sure CP DMA is idle because the driver might have performed a
4632 * DMA operation for copying or filling buffers/images.
4634 if (info
->srcStageMask
& (VK_PIPELINE_STAGE_TRANSFER_BIT
|
4635 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
))
4636 si_cp_dma_wait_for_idle(cmd_buffer
);
4638 cmd_buffer
->state
.flush_bits
|= dst_flush_bits
;
4641 void radv_CmdPipelineBarrier(
4642 VkCommandBuffer commandBuffer
,
4643 VkPipelineStageFlags srcStageMask
,
4644 VkPipelineStageFlags destStageMask
,
4646 uint32_t memoryBarrierCount
,
4647 const VkMemoryBarrier
* pMemoryBarriers
,
4648 uint32_t bufferMemoryBarrierCount
,
4649 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
4650 uint32_t imageMemoryBarrierCount
,
4651 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
4653 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4654 struct radv_barrier_info info
;
4656 info
.eventCount
= 0;
4657 info
.pEvents
= NULL
;
4658 info
.srcStageMask
= srcStageMask
;
4660 radv_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
4661 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
4662 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
4666 static void write_event(struct radv_cmd_buffer
*cmd_buffer
,
4667 struct radv_event
*event
,
4668 VkPipelineStageFlags stageMask
,
4671 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4672 uint64_t va
= radv_buffer_get_va(event
->bo
);
4674 si_emit_cache_flush(cmd_buffer
);
4676 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
);
4678 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 18);
4680 /* Flags that only require a top-of-pipe event. */
4681 VkPipelineStageFlags top_of_pipe_flags
=
4682 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
;
4684 /* Flags that only require a post-index-fetch event. */
4685 VkPipelineStageFlags post_index_fetch_flags
=
4687 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
4688 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
;
4690 /* Make sure CP DMA is idle because the driver might have performed a
4691 * DMA operation for copying or filling buffers/images.
4693 if (stageMask
& (VK_PIPELINE_STAGE_TRANSFER_BIT
|
4694 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
))
4695 si_cp_dma_wait_for_idle(cmd_buffer
);
4697 /* TODO: Emit EOS events for syncing PS/CS stages. */
4699 if (!(stageMask
& ~top_of_pipe_flags
)) {
4700 /* Just need to sync the PFP engine. */
4701 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
4702 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
4703 S_370_WR_CONFIRM(1) |
4704 S_370_ENGINE_SEL(V_370_PFP
));
4705 radeon_emit(cs
, va
);
4706 radeon_emit(cs
, va
>> 32);
4707 radeon_emit(cs
, value
);
4708 } else if (!(stageMask
& ~post_index_fetch_flags
)) {
4709 /* Sync ME because PFP reads index and indirect buffers. */
4710 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
4711 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
4712 S_370_WR_CONFIRM(1) |
4713 S_370_ENGINE_SEL(V_370_ME
));
4714 radeon_emit(cs
, va
);
4715 radeon_emit(cs
, va
>> 32);
4716 radeon_emit(cs
, value
);
4718 /* Otherwise, sync all prior GPU work using an EOP event. */
4719 si_cs_emit_write_event_eop(cs
,
4720 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
4721 radv_cmd_buffer_uses_mec(cmd_buffer
),
4722 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
4723 EOP_DATA_SEL_VALUE_32BIT
, va
, 2, value
,
4724 cmd_buffer
->gfx9_eop_bug_va
);
4727 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4730 void radv_CmdSetEvent(VkCommandBuffer commandBuffer
,
4732 VkPipelineStageFlags stageMask
)
4734 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4735 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4737 write_event(cmd_buffer
, event
, stageMask
, 1);
4740 void radv_CmdResetEvent(VkCommandBuffer commandBuffer
,
4742 VkPipelineStageFlags stageMask
)
4744 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4745 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4747 write_event(cmd_buffer
, event
, stageMask
, 0);
4750 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer
,
4751 uint32_t eventCount
,
4752 const VkEvent
* pEvents
,
4753 VkPipelineStageFlags srcStageMask
,
4754 VkPipelineStageFlags dstStageMask
,
4755 uint32_t memoryBarrierCount
,
4756 const VkMemoryBarrier
* pMemoryBarriers
,
4757 uint32_t bufferMemoryBarrierCount
,
4758 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
4759 uint32_t imageMemoryBarrierCount
,
4760 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
4762 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4763 struct radv_barrier_info info
;
4765 info
.eventCount
= eventCount
;
4766 info
.pEvents
= pEvents
;
4767 info
.srcStageMask
= 0;
4769 radv_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
4770 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
4771 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
4775 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer
,
4776 uint32_t deviceMask
)
4781 /* VK_EXT_conditional_rendering */
4782 void radv_CmdBeginConditionalRenderingEXT(
4783 VkCommandBuffer commandBuffer
,
4784 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
4786 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4787 RADV_FROM_HANDLE(radv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
4788 bool draw_visible
= true;
4791 va
= radv_buffer_get_va(buffer
->bo
) + pConditionalRenderingBegin
->offset
;
4793 /* By default, if the 32-bit value at offset in buffer memory is zero,
4794 * then the rendering commands are discarded, otherwise they are
4795 * executed as normal. If the inverted flag is set, all commands are
4796 * discarded if the value is non zero.
4798 if (pConditionalRenderingBegin
->flags
&
4799 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
) {
4800 draw_visible
= false;
4803 si_emit_cache_flush(cmd_buffer
);
4805 /* Enable predication for this command buffer. */
4806 si_emit_set_predication_state(cmd_buffer
, draw_visible
, va
);
4807 cmd_buffer
->state
.predicating
= true;
4809 /* Store conditional rendering user info. */
4810 cmd_buffer
->state
.predication_type
= draw_visible
;
4811 cmd_buffer
->state
.predication_va
= va
;
4814 void radv_CmdEndConditionalRenderingEXT(
4815 VkCommandBuffer commandBuffer
)
4817 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4819 /* Disable predication for this command buffer. */
4820 si_emit_set_predication_state(cmd_buffer
, false, 0);
4821 cmd_buffer
->state
.predicating
= false;
4823 /* Reset conditional rendering user info. */
4824 cmd_buffer
->state
.predication_type
= -1;
4825 cmd_buffer
->state
.predication_va
= 0;
4828 /* VK_EXT_transform_feedback */
4829 void radv_CmdBindTransformFeedbackBuffersEXT(
4830 VkCommandBuffer commandBuffer
,
4831 uint32_t firstBinding
,
4832 uint32_t bindingCount
,
4833 const VkBuffer
* pBuffers
,
4834 const VkDeviceSize
* pOffsets
,
4835 const VkDeviceSize
* pSizes
)
4837 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4838 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
4839 uint8_t enabled_mask
= 0;
4841 assert(firstBinding
+ bindingCount
<= MAX_SO_BUFFERS
);
4842 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
4843 uint32_t idx
= firstBinding
+ i
;
4845 sb
[idx
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
4846 sb
[idx
].offset
= pOffsets
[i
];
4847 sb
[idx
].size
= pSizes
[i
];
4849 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
4850 sb
[idx
].buffer
->bo
);
4852 enabled_mask
|= 1 << idx
;
4855 cmd_buffer
->state
.streamout
.enabled_mask
= enabled_mask
;
4857 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_STREAMOUT_BUFFER
;
4861 radv_emit_streamout_enable(struct radv_cmd_buffer
*cmd_buffer
)
4863 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
4864 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4866 radeon_set_context_reg_seq(cs
, R_028B94_VGT_STRMOUT_CONFIG
, 2);
4868 S_028B94_STREAMOUT_0_EN(so
->streamout_enabled
) |
4869 S_028B94_RAST_STREAM(0) |
4870 S_028B94_STREAMOUT_1_EN(so
->streamout_enabled
) |
4871 S_028B94_STREAMOUT_2_EN(so
->streamout_enabled
) |
4872 S_028B94_STREAMOUT_3_EN(so
->streamout_enabled
));
4873 radeon_emit(cs
, so
->hw_enabled_mask
&
4874 so
->enabled_stream_buffers_mask
);
4876 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
4880 radv_set_streamout_enable(struct radv_cmd_buffer
*cmd_buffer
, bool enable
)
4882 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
4883 bool old_streamout_enabled
= so
->streamout_enabled
;
4884 uint32_t old_hw_enabled_mask
= so
->hw_enabled_mask
;
4886 so
->streamout_enabled
= enable
;
4888 so
->hw_enabled_mask
= so
->enabled_mask
|
4889 (so
->enabled_mask
<< 4) |
4890 (so
->enabled_mask
<< 8) |
4891 (so
->enabled_mask
<< 12);
4893 if ((old_streamout_enabled
!= so
->streamout_enabled
) ||
4894 (old_hw_enabled_mask
!= so
->hw_enabled_mask
))
4895 radv_emit_streamout_enable(cmd_buffer
);
4898 static void radv_flush_vgt_streamout(struct radv_cmd_buffer
*cmd_buffer
)
4900 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4901 unsigned reg_strmout_cntl
;
4903 /* The register is at different places on different ASICs. */
4904 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
4905 reg_strmout_cntl
= R_0300FC_CP_STRMOUT_CNTL
;
4906 radeon_set_uconfig_reg(cs
, reg_strmout_cntl
, 0);
4908 reg_strmout_cntl
= R_0084FC_CP_STRMOUT_CNTL
;
4909 radeon_set_config_reg(cs
, reg_strmout_cntl
, 0);
4912 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
4913 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH
) | EVENT_INDEX(0));
4915 radeon_emit(cs
, PKT3(PKT3_WAIT_REG_MEM
, 5, 0));
4916 radeon_emit(cs
, WAIT_REG_MEM_EQUAL
); /* wait until the register is equal to the reference value */
4917 radeon_emit(cs
, reg_strmout_cntl
>> 2); /* register */
4919 radeon_emit(cs
, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
4920 radeon_emit(cs
, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
4921 radeon_emit(cs
, 4); /* poll interval */
4924 void radv_CmdBeginTransformFeedbackEXT(
4925 VkCommandBuffer commandBuffer
,
4926 uint32_t firstCounterBuffer
,
4927 uint32_t counterBufferCount
,
4928 const VkBuffer
* pCounterBuffers
,
4929 const VkDeviceSize
* pCounterBufferOffsets
)
4931 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4932 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
4933 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
4934 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4937 radv_flush_vgt_streamout(cmd_buffer
);
4939 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
4940 for_each_bit(i
, so
->enabled_mask
) {
4941 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
4942 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
4943 counter_buffer_idx
= -1;
4945 /* SI binds streamout buffers as shader resources.
4946 * VGT only counts primitives and tells the shader through
4949 radeon_set_context_reg_seq(cs
, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0
+ 16*i
, 2);
4950 radeon_emit(cs
, sb
[i
].size
>> 2); /* BUFFER_SIZE (in DW) */
4951 radeon_emit(cs
, so
->stride_in_dw
[i
]); /* VTX_STRIDE (in DW) */
4953 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
4955 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
4956 /* The array of counter buffers is optional. */
4957 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
4958 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
4960 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
4963 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
4964 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
4965 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4966 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM
)); /* control */
4967 radeon_emit(cs
, 0); /* unused */
4968 radeon_emit(cs
, 0); /* unused */
4969 radeon_emit(cs
, va
); /* src address lo */
4970 radeon_emit(cs
, va
>> 32); /* src address hi */
4972 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
4974 /* Start from the beginning. */
4975 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
4976 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
4977 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4978 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET
)); /* control */
4979 radeon_emit(cs
, 0); /* unused */
4980 radeon_emit(cs
, 0); /* unused */
4981 radeon_emit(cs
, 0); /* unused */
4982 radeon_emit(cs
, 0); /* unused */
4986 radv_set_streamout_enable(cmd_buffer
, true);
4989 void radv_CmdEndTransformFeedbackEXT(
4990 VkCommandBuffer commandBuffer
,
4991 uint32_t firstCounterBuffer
,
4992 uint32_t counterBufferCount
,
4993 const VkBuffer
* pCounterBuffers
,
4994 const VkDeviceSize
* pCounterBufferOffsets
)
4996 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4997 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
4998 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5001 radv_flush_vgt_streamout(cmd_buffer
);
5003 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
5004 for_each_bit(i
, so
->enabled_mask
) {
5005 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
5006 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
5007 counter_buffer_idx
= -1;
5009 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
5010 /* The array of counters buffer is optional. */
5011 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
5012 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
5014 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
5016 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
5017 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
5018 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5019 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE
) |
5020 STRMOUT_STORE_BUFFER_FILLED_SIZE
); /* control */
5021 radeon_emit(cs
, va
); /* dst address lo */
5022 radeon_emit(cs
, va
>> 32); /* dst address hi */
5023 radeon_emit(cs
, 0); /* unused */
5024 radeon_emit(cs
, 0); /* unused */
5026 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
5029 /* Deactivate transform feedback by zeroing the buffer size.
5030 * The counters (primitives generated, primitives emitted) may
5031 * be enabled even if there is not buffer bound. This ensures
5032 * that the primitives-emitted query won't increment.
5034 radeon_set_context_reg(cs
, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0
+ 16*i
, 0);
5036 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
5039 radv_set_streamout_enable(cmd_buffer
, false);
5042 void radv_CmdDrawIndirectByteCountEXT(
5043 VkCommandBuffer commandBuffer
,
5044 uint32_t instanceCount
,
5045 uint32_t firstInstance
,
5046 VkBuffer _counterBuffer
,
5047 VkDeviceSize counterBufferOffset
,
5048 uint32_t counterOffset
,
5049 uint32_t vertexStride
)
5051 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5052 RADV_FROM_HANDLE(radv_buffer
, counterBuffer
, _counterBuffer
);
5053 struct radv_draw_info info
= {};
5055 info
.instance_count
= instanceCount
;
5056 info
.first_instance
= firstInstance
;
5057 info
.strmout_buffer
= counterBuffer
;
5058 info
.strmout_buffer_offset
= counterBufferOffset
;
5059 info
.stride
= vertexStride
;
5061 radv_draw(cmd_buffer
, &info
);