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Revert "radv: execute external subpass barriers after ending subpasses"
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range);
61
62 const struct radv_dynamic_state default_dynamic_state = {
63 .viewport = {
64 .count = 0,
65 },
66 .scissor = {
67 .count = 0,
68 },
69 .line_width = 1.0f,
70 .depth_bias = {
71 .bias = 0.0f,
72 .clamp = 0.0f,
73 .slope = 0.0f,
74 },
75 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
76 .depth_bounds = {
77 .min = 0.0f,
78 .max = 1.0f,
79 },
80 .stencil_compare_mask = {
81 .front = ~0u,
82 .back = ~0u,
83 },
84 .stencil_write_mask = {
85 .front = ~0u,
86 .back = ~0u,
87 },
88 .stencil_reference = {
89 .front = 0u,
90 .back = 0u,
91 },
92 };
93
94 static void
95 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
96 const struct radv_dynamic_state *src)
97 {
98 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
99 uint32_t copy_mask = src->mask;
100 uint32_t dest_mask = 0;
101
102 /* Make sure to copy the number of viewports/scissors because they can
103 * only be specified at pipeline creation time.
104 */
105 dest->viewport.count = src->viewport.count;
106 dest->scissor.count = src->scissor.count;
107 dest->discard_rectangle.count = src->discard_rectangle.count;
108
109 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
110 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
111 src->viewport.count * sizeof(VkViewport))) {
112 typed_memcpy(dest->viewport.viewports,
113 src->viewport.viewports,
114 src->viewport.count);
115 dest_mask |= RADV_DYNAMIC_VIEWPORT;
116 }
117 }
118
119 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
120 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
121 src->scissor.count * sizeof(VkRect2D))) {
122 typed_memcpy(dest->scissor.scissors,
123 src->scissor.scissors, src->scissor.count);
124 dest_mask |= RADV_DYNAMIC_SCISSOR;
125 }
126 }
127
128 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
129 if (dest->line_width != src->line_width) {
130 dest->line_width = src->line_width;
131 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
132 }
133 }
134
135 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
136 if (memcmp(&dest->depth_bias, &src->depth_bias,
137 sizeof(src->depth_bias))) {
138 dest->depth_bias = src->depth_bias;
139 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
140 }
141 }
142
143 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
144 if (memcmp(&dest->blend_constants, &src->blend_constants,
145 sizeof(src->blend_constants))) {
146 typed_memcpy(dest->blend_constants,
147 src->blend_constants, 4);
148 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
149 }
150 }
151
152 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
153 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
154 sizeof(src->depth_bounds))) {
155 dest->depth_bounds = src->depth_bounds;
156 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
157 }
158 }
159
160 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
161 if (memcmp(&dest->stencil_compare_mask,
162 &src->stencil_compare_mask,
163 sizeof(src->stencil_compare_mask))) {
164 dest->stencil_compare_mask = src->stencil_compare_mask;
165 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
166 }
167 }
168
169 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
170 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
171 sizeof(src->stencil_write_mask))) {
172 dest->stencil_write_mask = src->stencil_write_mask;
173 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
174 }
175 }
176
177 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
178 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
179 sizeof(src->stencil_reference))) {
180 dest->stencil_reference = src->stencil_reference;
181 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
182 }
183 }
184
185 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
186 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
187 src->discard_rectangle.count * sizeof(VkRect2D))) {
188 typed_memcpy(dest->discard_rectangle.rectangles,
189 src->discard_rectangle.rectangles,
190 src->discard_rectangle.count);
191 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
192 }
193 }
194
195 cmd_buffer->state.dirty |= dest_mask;
196 }
197
198 static void
199 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
200 struct radv_pipeline *pipeline)
201 {
202 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
203 struct radv_shader_info *info;
204
205 if (!pipeline->streamout_shader)
206 return;
207
208 info = &pipeline->streamout_shader->info.info;
209 for (int i = 0; i < MAX_SO_BUFFERS; i++)
210 so->stride_in_dw[i] = info->so.strides[i];
211
212 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
213 }
214
215 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
216 {
217 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
218 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
219 }
220
221 enum ring_type radv_queue_family_to_ring(int f) {
222 switch (f) {
223 case RADV_QUEUE_GENERAL:
224 return RING_GFX;
225 case RADV_QUEUE_COMPUTE:
226 return RING_COMPUTE;
227 case RADV_QUEUE_TRANSFER:
228 return RING_DMA;
229 default:
230 unreachable("Unknown queue family");
231 }
232 }
233
234 static VkResult radv_create_cmd_buffer(
235 struct radv_device * device,
236 struct radv_cmd_pool * pool,
237 VkCommandBufferLevel level,
238 VkCommandBuffer* pCommandBuffer)
239 {
240 struct radv_cmd_buffer *cmd_buffer;
241 unsigned ring;
242 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
243 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
244 if (cmd_buffer == NULL)
245 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
246
247 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
248 cmd_buffer->device = device;
249 cmd_buffer->pool = pool;
250 cmd_buffer->level = level;
251
252 if (pool) {
253 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
254 cmd_buffer->queue_family_index = pool->queue_family_index;
255
256 } else {
257 /* Init the pool_link so we can safely call list_del when we destroy
258 * the command buffer
259 */
260 list_inithead(&cmd_buffer->pool_link);
261 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
262 }
263
264 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
265
266 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
267 if (!cmd_buffer->cs) {
268 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
269 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
270 }
271
272 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
273
274 list_inithead(&cmd_buffer->upload.list);
275
276 return VK_SUCCESS;
277 }
278
279 static void
280 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
281 {
282 list_del(&cmd_buffer->pool_link);
283
284 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
285 &cmd_buffer->upload.list, list) {
286 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
287 list_del(&up->list);
288 free(up);
289 }
290
291 if (cmd_buffer->upload.upload_bo)
292 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
293 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
294
295 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
296 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
297
298 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
299 }
300
301 static VkResult
302 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
303 {
304
305 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
306
307 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
308 &cmd_buffer->upload.list, list) {
309 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
310 list_del(&up->list);
311 free(up);
312 }
313
314 cmd_buffer->push_constant_stages = 0;
315 cmd_buffer->scratch_size_needed = 0;
316 cmd_buffer->compute_scratch_size_needed = 0;
317 cmd_buffer->esgs_ring_size_needed = 0;
318 cmd_buffer->gsvs_ring_size_needed = 0;
319 cmd_buffer->tess_rings_needed = false;
320 cmd_buffer->sample_positions_needed = false;
321
322 if (cmd_buffer->upload.upload_bo)
323 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
324 cmd_buffer->upload.upload_bo);
325 cmd_buffer->upload.offset = 0;
326
327 cmd_buffer->record_result = VK_SUCCESS;
328
329 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
330 cmd_buffer->descriptors[i].dirty = 0;
331 cmd_buffer->descriptors[i].valid = 0;
332 cmd_buffer->descriptors[i].push_dirty = false;
333 }
334
335 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
336 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
337 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
338 unsigned fence_offset, eop_bug_offset;
339 void *fence_ptr;
340
341 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
342 &fence_ptr);
343
344 cmd_buffer->gfx9_fence_va =
345 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
346 cmd_buffer->gfx9_fence_va += fence_offset;
347
348 /* Allocate a buffer for the EOP bug on GFX9. */
349 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
350 &eop_bug_offset, &fence_ptr);
351 cmd_buffer->gfx9_eop_bug_va =
352 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
353 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
354 }
355
356 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
357
358 return cmd_buffer->record_result;
359 }
360
361 static bool
362 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
363 uint64_t min_needed)
364 {
365 uint64_t new_size;
366 struct radeon_winsys_bo *bo;
367 struct radv_cmd_buffer_upload *upload;
368 struct radv_device *device = cmd_buffer->device;
369
370 new_size = MAX2(min_needed, 16 * 1024);
371 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
372
373 bo = device->ws->buffer_create(device->ws,
374 new_size, 4096,
375 RADEON_DOMAIN_GTT,
376 RADEON_FLAG_CPU_ACCESS|
377 RADEON_FLAG_NO_INTERPROCESS_SHARING |
378 RADEON_FLAG_32BIT,
379 RADV_BO_PRIORITY_UPLOAD_BUFFER);
380
381 if (!bo) {
382 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
383 return false;
384 }
385
386 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
387 if (cmd_buffer->upload.upload_bo) {
388 upload = malloc(sizeof(*upload));
389
390 if (!upload) {
391 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
392 device->ws->buffer_destroy(bo);
393 return false;
394 }
395
396 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
397 list_add(&upload->list, &cmd_buffer->upload.list);
398 }
399
400 cmd_buffer->upload.upload_bo = bo;
401 cmd_buffer->upload.size = new_size;
402 cmd_buffer->upload.offset = 0;
403 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
404
405 if (!cmd_buffer->upload.map) {
406 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
407 return false;
408 }
409
410 return true;
411 }
412
413 bool
414 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
415 unsigned size,
416 unsigned alignment,
417 unsigned *out_offset,
418 void **ptr)
419 {
420 assert(util_is_power_of_two_nonzero(alignment));
421
422 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
423 if (offset + size > cmd_buffer->upload.size) {
424 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
425 return false;
426 offset = 0;
427 }
428
429 *out_offset = offset;
430 *ptr = cmd_buffer->upload.map + offset;
431
432 cmd_buffer->upload.offset = offset + size;
433 return true;
434 }
435
436 bool
437 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
438 unsigned size, unsigned alignment,
439 const void *data, unsigned *out_offset)
440 {
441 uint8_t *ptr;
442
443 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
444 out_offset, (void **)&ptr))
445 return false;
446
447 if (ptr)
448 memcpy(ptr, data, size);
449
450 return true;
451 }
452
453 static void
454 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
455 unsigned count, const uint32_t *data)
456 {
457 struct radeon_cmdbuf *cs = cmd_buffer->cs;
458
459 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
460
461 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
462 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
463 S_370_WR_CONFIRM(1) |
464 S_370_ENGINE_SEL(V_370_ME));
465 radeon_emit(cs, va);
466 radeon_emit(cs, va >> 32);
467 radeon_emit_array(cs, data, count);
468 }
469
470 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
471 {
472 struct radv_device *device = cmd_buffer->device;
473 struct radeon_cmdbuf *cs = cmd_buffer->cs;
474 uint64_t va;
475
476 va = radv_buffer_get_va(device->trace_bo);
477 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
478 va += 4;
479
480 ++cmd_buffer->state.trace_id;
481 radv_emit_write_data_packet(cmd_buffer, va, 1,
482 &cmd_buffer->state.trace_id);
483
484 radeon_check_space(cmd_buffer->device->ws, cs, 2);
485
486 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
487 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
488 }
489
490 static void
491 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
492 enum radv_cmd_flush_bits flags)
493 {
494 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
495 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
496 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
497
498 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
499
500 /* Force wait for graphics or compute engines to be idle. */
501 si_cs_emit_cache_flush(cmd_buffer->cs,
502 cmd_buffer->device->physical_device->rad_info.chip_class,
503 &cmd_buffer->gfx9_fence_idx,
504 cmd_buffer->gfx9_fence_va,
505 radv_cmd_buffer_uses_mec(cmd_buffer),
506 flags, cmd_buffer->gfx9_eop_bug_va);
507 }
508
509 if (unlikely(cmd_buffer->device->trace_bo))
510 radv_cmd_buffer_trace_emit(cmd_buffer);
511 }
512
513 static void
514 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
515 struct radv_pipeline *pipeline, enum ring_type ring)
516 {
517 struct radv_device *device = cmd_buffer->device;
518 uint32_t data[2];
519 uint64_t va;
520
521 va = radv_buffer_get_va(device->trace_bo);
522
523 switch (ring) {
524 case RING_GFX:
525 va += 8;
526 break;
527 case RING_COMPUTE:
528 va += 16;
529 break;
530 default:
531 assert(!"invalid ring type");
532 }
533
534 data[0] = (uintptr_t)pipeline;
535 data[1] = (uintptr_t)pipeline >> 32;
536
537 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
538 }
539
540 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
541 VkPipelineBindPoint bind_point,
542 struct radv_descriptor_set *set,
543 unsigned idx)
544 {
545 struct radv_descriptor_state *descriptors_state =
546 radv_get_descriptors_state(cmd_buffer, bind_point);
547
548 descriptors_state->sets[idx] = set;
549
550 descriptors_state->valid |= (1u << idx); /* active descriptors */
551 descriptors_state->dirty |= (1u << idx);
552 }
553
554 static void
555 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
556 VkPipelineBindPoint bind_point)
557 {
558 struct radv_descriptor_state *descriptors_state =
559 radv_get_descriptors_state(cmd_buffer, bind_point);
560 struct radv_device *device = cmd_buffer->device;
561 uint32_t data[MAX_SETS * 2] = {};
562 uint64_t va;
563 unsigned i;
564 va = radv_buffer_get_va(device->trace_bo) + 24;
565
566 for_each_bit(i, descriptors_state->valid) {
567 struct radv_descriptor_set *set = descriptors_state->sets[i];
568 data[i * 2] = (uintptr_t)set;
569 data[i * 2 + 1] = (uintptr_t)set >> 32;
570 }
571
572 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
573 }
574
575 struct radv_userdata_info *
576 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
577 gl_shader_stage stage,
578 int idx)
579 {
580 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
581 return &shader->info.user_sgprs_locs.shader_data[idx];
582 }
583
584 static void
585 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
586 struct radv_pipeline *pipeline,
587 gl_shader_stage stage,
588 int idx, uint64_t va)
589 {
590 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
591 uint32_t base_reg = pipeline->user_data_0[stage];
592 if (loc->sgpr_idx == -1)
593 return;
594
595 assert(loc->num_sgprs == 1);
596
597 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
598 base_reg + loc->sgpr_idx * 4, va, false);
599 }
600
601 static void
602 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
603 struct radv_pipeline *pipeline,
604 struct radv_descriptor_state *descriptors_state,
605 gl_shader_stage stage)
606 {
607 struct radv_device *device = cmd_buffer->device;
608 struct radeon_cmdbuf *cs = cmd_buffer->cs;
609 uint32_t sh_base = pipeline->user_data_0[stage];
610 struct radv_userdata_locations *locs =
611 &pipeline->shaders[stage]->info.user_sgprs_locs;
612 unsigned mask = locs->descriptor_sets_enabled;
613
614 mask &= descriptors_state->dirty & descriptors_state->valid;
615
616 while (mask) {
617 int start, count;
618
619 u_bit_scan_consecutive_range(&mask, &start, &count);
620
621 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
622 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
623
624 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
625 for (int i = 0; i < count; i++) {
626 struct radv_descriptor_set *set =
627 descriptors_state->sets[start + i];
628
629 radv_emit_shader_pointer_body(device, cs, set->va, true);
630 }
631 }
632 }
633
634 static void
635 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
636 struct radv_pipeline *pipeline,
637 gl_shader_stage stage,
638 int idx, int count, uint32_t *values)
639 {
640 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
641 uint32_t base_reg = pipeline->user_data_0[stage];
642 if (loc->sgpr_idx == -1)
643 return;
644
645 assert(loc->num_sgprs == count);
646
647 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
648 radeon_emit_array(cmd_buffer->cs, values, count);
649 }
650
651 static void
652 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
653 struct radv_pipeline *pipeline)
654 {
655 int num_samples = pipeline->graphics.ms.num_samples;
656 struct radv_multisample_state *ms = &pipeline->graphics.ms;
657 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
658
659 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
660 cmd_buffer->sample_positions_needed = true;
661
662 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
663 return;
664
665 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
666 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
667 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
668
669 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
670
671 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
672
673 /* GFX9: Flush DFSM when the AA mode changes. */
674 if (cmd_buffer->device->dfsm_allowed) {
675 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
676 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
677 }
678
679 cmd_buffer->state.context_roll_without_scissor_emitted = true;
680 }
681
682 static void
683 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
684 struct radv_shader_variant *shader)
685 {
686 uint64_t va;
687
688 if (!shader)
689 return;
690
691 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
692
693 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
694 }
695
696 static void
697 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
698 struct radv_pipeline *pipeline,
699 bool vertex_stage_only)
700 {
701 struct radv_cmd_state *state = &cmd_buffer->state;
702 uint32_t mask = state->prefetch_L2_mask;
703
704 if (vertex_stage_only) {
705 /* Fast prefetch path for starting draws as soon as possible.
706 */
707 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
708 RADV_PREFETCH_VBO_DESCRIPTORS);
709 }
710
711 if (mask & RADV_PREFETCH_VS)
712 radv_emit_shader_prefetch(cmd_buffer,
713 pipeline->shaders[MESA_SHADER_VERTEX]);
714
715 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
716 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
717
718 if (mask & RADV_PREFETCH_TCS)
719 radv_emit_shader_prefetch(cmd_buffer,
720 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
721
722 if (mask & RADV_PREFETCH_TES)
723 radv_emit_shader_prefetch(cmd_buffer,
724 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
725
726 if (mask & RADV_PREFETCH_GS) {
727 radv_emit_shader_prefetch(cmd_buffer,
728 pipeline->shaders[MESA_SHADER_GEOMETRY]);
729 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
730 }
731
732 if (mask & RADV_PREFETCH_PS)
733 radv_emit_shader_prefetch(cmd_buffer,
734 pipeline->shaders[MESA_SHADER_FRAGMENT]);
735
736 state->prefetch_L2_mask &= ~mask;
737 }
738
739 static void
740 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
741 {
742 if (!cmd_buffer->device->physical_device->rbplus_allowed)
743 return;
744
745 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
746 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
747 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
748
749 unsigned sx_ps_downconvert = 0;
750 unsigned sx_blend_opt_epsilon = 0;
751 unsigned sx_blend_opt_control = 0;
752
753 for (unsigned i = 0; i < subpass->color_count; ++i) {
754 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
755 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
756 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
757 continue;
758 }
759
760 int idx = subpass->color_attachments[i].attachment;
761 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
762
763 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
764 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
765 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
766 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
767
768 bool has_alpha, has_rgb;
769
770 /* Set if RGB and A are present. */
771 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
772
773 if (format == V_028C70_COLOR_8 ||
774 format == V_028C70_COLOR_16 ||
775 format == V_028C70_COLOR_32)
776 has_rgb = !has_alpha;
777 else
778 has_rgb = true;
779
780 /* Check the colormask and export format. */
781 if (!(colormask & 0x7))
782 has_rgb = false;
783 if (!(colormask & 0x8))
784 has_alpha = false;
785
786 if (spi_format == V_028714_SPI_SHADER_ZERO) {
787 has_rgb = false;
788 has_alpha = false;
789 }
790
791 /* Disable value checking for disabled channels. */
792 if (!has_rgb)
793 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
794 if (!has_alpha)
795 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
796
797 /* Enable down-conversion for 32bpp and smaller formats. */
798 switch (format) {
799 case V_028C70_COLOR_8:
800 case V_028C70_COLOR_8_8:
801 case V_028C70_COLOR_8_8_8_8:
802 /* For 1 and 2-channel formats, use the superset thereof. */
803 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
804 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
805 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
806 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
807 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
808 }
809 break;
810
811 case V_028C70_COLOR_5_6_5:
812 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
813 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
814 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
815 }
816 break;
817
818 case V_028C70_COLOR_1_5_5_5:
819 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
820 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
821 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
822 }
823 break;
824
825 case V_028C70_COLOR_4_4_4_4:
826 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
827 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
828 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
829 }
830 break;
831
832 case V_028C70_COLOR_32:
833 if (swap == V_028C70_SWAP_STD &&
834 spi_format == V_028714_SPI_SHADER_32_R)
835 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
836 else if (swap == V_028C70_SWAP_ALT_REV &&
837 spi_format == V_028714_SPI_SHADER_32_AR)
838 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
839 break;
840
841 case V_028C70_COLOR_16:
842 case V_028C70_COLOR_16_16:
843 /* For 1-channel formats, use the superset thereof. */
844 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
845 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
846 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
847 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
848 if (swap == V_028C70_SWAP_STD ||
849 swap == V_028C70_SWAP_STD_REV)
850 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
851 else
852 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
853 }
854 break;
855
856 case V_028C70_COLOR_10_11_11:
857 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
858 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
859 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
860 }
861 break;
862
863 case V_028C70_COLOR_2_10_10_10:
864 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
865 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
866 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
867 }
868 break;
869 }
870 }
871
872 for (unsigned i = subpass->color_count; i < 8; ++i) {
873 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
874 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
875 }
876 /* TODO: avoid redundantly setting context registers */
877 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
878 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
879 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
880 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
881
882 cmd_buffer->state.context_roll_without_scissor_emitted = true;
883 }
884
885 static void
886 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
887 {
888 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
889
890 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
891 return;
892
893 radv_update_multisample_state(cmd_buffer, pipeline);
894
895 cmd_buffer->scratch_size_needed =
896 MAX2(cmd_buffer->scratch_size_needed,
897 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
898
899 if (!cmd_buffer->state.emitted_pipeline ||
900 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
901 pipeline->graphics.can_use_guardband)
902 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
903
904 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
905
906 if (!cmd_buffer->state.emitted_pipeline ||
907 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
908 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
909 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
910 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
911 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
912 cmd_buffer->state.context_roll_without_scissor_emitted = true;
913 }
914
915 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
916 if (!pipeline->shaders[i])
917 continue;
918
919 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
920 pipeline->shaders[i]->bo);
921 }
922
923 if (radv_pipeline_has_gs(pipeline))
924 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
925 pipeline->gs_copy_shader->bo);
926
927 if (unlikely(cmd_buffer->device->trace_bo))
928 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
929
930 cmd_buffer->state.emitted_pipeline = pipeline;
931
932 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
933 }
934
935 static void
936 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
937 {
938 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
939 cmd_buffer->state.dynamic.viewport.viewports);
940 }
941
942 static void
943 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
944 {
945 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
946
947 si_write_scissors(cmd_buffer->cs, 0, count,
948 cmd_buffer->state.dynamic.scissor.scissors,
949 cmd_buffer->state.dynamic.viewport.viewports,
950 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
951
952 cmd_buffer->state.context_roll_without_scissor_emitted = false;
953 }
954
955 static void
956 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
957 {
958 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
959 return;
960
961 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
962 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
963 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
964 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
965 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
966 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
967 S_028214_BR_Y(rect.offset.y + rect.extent.height));
968 }
969 }
970
971 static void
972 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
973 {
974 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
975
976 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
977 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
978 }
979
980 static void
981 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
982 {
983 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
984
985 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
986 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
987 }
988
989 static void
990 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
991 {
992 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
993
994 radeon_set_context_reg_seq(cmd_buffer->cs,
995 R_028430_DB_STENCILREFMASK, 2);
996 radeon_emit(cmd_buffer->cs,
997 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
998 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
999 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1000 S_028430_STENCILOPVAL(1));
1001 radeon_emit(cmd_buffer->cs,
1002 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1003 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1004 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1005 S_028434_STENCILOPVAL_BF(1));
1006 }
1007
1008 static void
1009 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1010 {
1011 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1012
1013 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1014 fui(d->depth_bounds.min));
1015 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1016 fui(d->depth_bounds.max));
1017 }
1018
1019 static void
1020 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1021 {
1022 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1023 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1024 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1025
1026
1027 radeon_set_context_reg_seq(cmd_buffer->cs,
1028 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1029 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1030 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1031 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1032 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1033 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1034 }
1035
1036 static void
1037 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1038 int index,
1039 struct radv_attachment_info *att,
1040 struct radv_image *image,
1041 VkImageLayout layout)
1042 {
1043 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1044 struct radv_color_buffer_info *cb = &att->cb;
1045 uint32_t cb_color_info = cb->cb_color_info;
1046
1047 if (!radv_layout_dcc_compressed(image, layout,
1048 radv_image_queue_family_mask(image,
1049 cmd_buffer->queue_family_index,
1050 cmd_buffer->queue_family_index))) {
1051 cb_color_info &= C_028C70_DCC_ENABLE;
1052 }
1053
1054 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1055 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1056 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1057 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1058 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1059 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1060 radeon_emit(cmd_buffer->cs, cb_color_info);
1061 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1062 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1063 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1064 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1065 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1066 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1067
1068 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1069 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1070 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1071
1072 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1073 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1074 } else {
1075 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1076 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1077 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1078 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1079 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1080 radeon_emit(cmd_buffer->cs, cb_color_info);
1081 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1082 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1083 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1084 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1085 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1086 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1087
1088 if (is_vi) { /* DCC BASE */
1089 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1090 }
1091 }
1092
1093 if (radv_image_has_dcc(image)) {
1094 /* Drawing with DCC enabled also compresses colorbuffers. */
1095 radv_update_dcc_metadata(cmd_buffer, image, true);
1096 }
1097 }
1098
1099 static void
1100 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1101 struct radv_ds_buffer_info *ds,
1102 struct radv_image *image, VkImageLayout layout,
1103 bool requires_cond_exec)
1104 {
1105 uint32_t db_z_info = ds->db_z_info;
1106 uint32_t db_z_info_reg;
1107
1108 if (!radv_image_is_tc_compat_htile(image))
1109 return;
1110
1111 if (!radv_layout_has_htile(image, layout,
1112 radv_image_queue_family_mask(image,
1113 cmd_buffer->queue_family_index,
1114 cmd_buffer->queue_family_index))) {
1115 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1116 }
1117
1118 db_z_info &= C_028040_ZRANGE_PRECISION;
1119
1120 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1121 db_z_info_reg = R_028038_DB_Z_INFO;
1122 } else {
1123 db_z_info_reg = R_028040_DB_Z_INFO;
1124 }
1125
1126 /* When we don't know the last fast clear value we need to emit a
1127 * conditional packet that will eventually skip the following
1128 * SET_CONTEXT_REG packet.
1129 */
1130 if (requires_cond_exec) {
1131 uint64_t va = radv_buffer_get_va(image->bo);
1132 va += image->offset + image->tc_compat_zrange_offset;
1133
1134 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1135 radeon_emit(cmd_buffer->cs, va);
1136 radeon_emit(cmd_buffer->cs, va >> 32);
1137 radeon_emit(cmd_buffer->cs, 0);
1138 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1139 }
1140
1141 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1142 }
1143
1144 static void
1145 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1146 struct radv_ds_buffer_info *ds,
1147 struct radv_image *image,
1148 VkImageLayout layout)
1149 {
1150 uint32_t db_z_info = ds->db_z_info;
1151 uint32_t db_stencil_info = ds->db_stencil_info;
1152
1153 if (!radv_layout_has_htile(image, layout,
1154 radv_image_queue_family_mask(image,
1155 cmd_buffer->queue_family_index,
1156 cmd_buffer->queue_family_index))) {
1157 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1158 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1159 }
1160
1161 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1162 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1163
1164
1165 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1166 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1167 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1168 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1169 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1170
1171 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1172 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1173 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1174 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1175 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1176 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1177 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1178 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1179 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1180 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1181 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1182
1183 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1184 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1185 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1186 } else {
1187 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1188
1189 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1190 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1191 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1192 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1193 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1194 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1195 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1196 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1197 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1198 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1199
1200 }
1201
1202 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1203 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1204
1205 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1206 ds->pa_su_poly_offset_db_fmt_cntl);
1207 }
1208
1209 /**
1210 * Update the fast clear depth/stencil values if the image is bound as a
1211 * depth/stencil buffer.
1212 */
1213 static void
1214 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1215 struct radv_image *image,
1216 VkClearDepthStencilValue ds_clear_value,
1217 VkImageAspectFlags aspects)
1218 {
1219 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1220 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1221 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1222 struct radv_attachment_info *att;
1223 uint32_t att_idx;
1224
1225 if (!framebuffer || !subpass)
1226 return;
1227
1228 if (!subpass->depth_stencil_attachment)
1229 return;
1230
1231 att_idx = subpass->depth_stencil_attachment->attachment;
1232 att = &framebuffer->attachments[att_idx];
1233 if (att->attachment->image != image)
1234 return;
1235
1236 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1237 radeon_emit(cs, ds_clear_value.stencil);
1238 radeon_emit(cs, fui(ds_clear_value.depth));
1239
1240 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1241 * only needed when clearing Z to 0.0.
1242 */
1243 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1244 ds_clear_value.depth == 0.0) {
1245 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1246
1247 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1248 layout, false);
1249 }
1250
1251 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1252 }
1253
1254 /**
1255 * Set the clear depth/stencil values to the image's metadata.
1256 */
1257 static void
1258 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1259 struct radv_image *image,
1260 VkClearDepthStencilValue ds_clear_value,
1261 VkImageAspectFlags aspects)
1262 {
1263 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1264 uint64_t va = radv_buffer_get_va(image->bo);
1265 unsigned reg_offset = 0, reg_count = 0;
1266
1267 va += image->offset + image->clear_value_offset;
1268
1269 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1270 ++reg_count;
1271 } else {
1272 ++reg_offset;
1273 va += 4;
1274 }
1275 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1276 ++reg_count;
1277
1278 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1279 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1280 S_370_WR_CONFIRM(1) |
1281 S_370_ENGINE_SEL(V_370_PFP));
1282 radeon_emit(cs, va);
1283 radeon_emit(cs, va >> 32);
1284 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1285 radeon_emit(cs, ds_clear_value.stencil);
1286 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1287 radeon_emit(cs, fui(ds_clear_value.depth));
1288 }
1289
1290 /**
1291 * Update the TC-compat metadata value for this image.
1292 */
1293 static void
1294 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1295 struct radv_image *image,
1296 uint32_t value)
1297 {
1298 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1299 uint64_t va = radv_buffer_get_va(image->bo);
1300 va += image->offset + image->tc_compat_zrange_offset;
1301
1302 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1303 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1304 S_370_WR_CONFIRM(1) |
1305 S_370_ENGINE_SEL(V_370_PFP));
1306 radeon_emit(cs, va);
1307 radeon_emit(cs, va >> 32);
1308 radeon_emit(cs, value);
1309 }
1310
1311 static void
1312 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1313 struct radv_image *image,
1314 VkClearDepthStencilValue ds_clear_value)
1315 {
1316 uint64_t va = radv_buffer_get_va(image->bo);
1317 va += image->offset + image->tc_compat_zrange_offset;
1318 uint32_t cond_val;
1319
1320 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1321 * depth clear value is 0.0f.
1322 */
1323 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1324
1325 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, cond_val);
1326 }
1327
1328 /**
1329 * Update the clear depth/stencil values for this image.
1330 */
1331 void
1332 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1333 struct radv_image *image,
1334 VkClearDepthStencilValue ds_clear_value,
1335 VkImageAspectFlags aspects)
1336 {
1337 assert(radv_image_has_htile(image));
1338
1339 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1340
1341 if (radv_image_is_tc_compat_htile(image) &&
1342 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1343 radv_update_tc_compat_zrange_metadata(cmd_buffer, image,
1344 ds_clear_value);
1345 }
1346
1347 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1348 aspects);
1349 }
1350
1351 /**
1352 * Load the clear depth/stencil values from the image's metadata.
1353 */
1354 static void
1355 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1356 struct radv_image *image)
1357 {
1358 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1359 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1360 uint64_t va = radv_buffer_get_va(image->bo);
1361 unsigned reg_offset = 0, reg_count = 0;
1362
1363 va += image->offset + image->clear_value_offset;
1364
1365 if (!radv_image_has_htile(image))
1366 return;
1367
1368 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1369 ++reg_count;
1370 } else {
1371 ++reg_offset;
1372 va += 4;
1373 }
1374 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1375 ++reg_count;
1376
1377 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1378
1379 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1380 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1381 radeon_emit(cs, va);
1382 radeon_emit(cs, va >> 32);
1383 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1384 radeon_emit(cs, reg_count);
1385 } else {
1386 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1387 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1388 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1389 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1390 radeon_emit(cs, va);
1391 radeon_emit(cs, va >> 32);
1392 radeon_emit(cs, reg >> 2);
1393 radeon_emit(cs, 0);
1394
1395 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1396 radeon_emit(cs, 0);
1397 }
1398 }
1399
1400 /*
1401 * With DCC some colors don't require CMASK elimination before being
1402 * used as a texture. This sets a predicate value to determine if the
1403 * cmask eliminate is required.
1404 */
1405 void
1406 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1407 struct radv_image *image, bool value)
1408 {
1409 uint64_t pred_val = value;
1410 uint64_t va = radv_buffer_get_va(image->bo);
1411 va += image->offset + image->fce_pred_offset;
1412
1413 assert(radv_image_has_dcc(image));
1414
1415 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1416 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1417 S_370_WR_CONFIRM(1) |
1418 S_370_ENGINE_SEL(V_370_PFP));
1419 radeon_emit(cmd_buffer->cs, va);
1420 radeon_emit(cmd_buffer->cs, va >> 32);
1421 radeon_emit(cmd_buffer->cs, pred_val);
1422 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1423 }
1424
1425 /**
1426 * Update the DCC predicate to reflect the compression state.
1427 */
1428 void
1429 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1430 struct radv_image *image, bool value)
1431 {
1432 uint64_t pred_val = value;
1433 uint64_t va = radv_buffer_get_va(image->bo);
1434 va += image->offset + image->dcc_pred_offset;
1435
1436 assert(radv_image_has_dcc(image));
1437
1438 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1439 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1440 S_370_WR_CONFIRM(1) |
1441 S_370_ENGINE_SEL(V_370_PFP));
1442 radeon_emit(cmd_buffer->cs, va);
1443 radeon_emit(cmd_buffer->cs, va >> 32);
1444 radeon_emit(cmd_buffer->cs, pred_val);
1445 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1446 }
1447
1448 /**
1449 * Update the fast clear color values if the image is bound as a color buffer.
1450 */
1451 static void
1452 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1453 struct radv_image *image,
1454 int cb_idx,
1455 uint32_t color_values[2])
1456 {
1457 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1458 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1459 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1460 struct radv_attachment_info *att;
1461 uint32_t att_idx;
1462
1463 if (!framebuffer || !subpass)
1464 return;
1465
1466 att_idx = subpass->color_attachments[cb_idx].attachment;
1467 if (att_idx == VK_ATTACHMENT_UNUSED)
1468 return;
1469
1470 att = &framebuffer->attachments[att_idx];
1471 if (att->attachment->image != image)
1472 return;
1473
1474 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1475 radeon_emit(cs, color_values[0]);
1476 radeon_emit(cs, color_values[1]);
1477
1478 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1479 }
1480
1481 /**
1482 * Set the clear color values to the image's metadata.
1483 */
1484 static void
1485 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1486 struct radv_image *image,
1487 uint32_t color_values[2])
1488 {
1489 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1490 uint64_t va = radv_buffer_get_va(image->bo);
1491
1492 va += image->offset + image->clear_value_offset;
1493
1494 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1495
1496 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1497 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1498 S_370_WR_CONFIRM(1) |
1499 S_370_ENGINE_SEL(V_370_PFP));
1500 radeon_emit(cs, va);
1501 radeon_emit(cs, va >> 32);
1502 radeon_emit(cs, color_values[0]);
1503 radeon_emit(cs, color_values[1]);
1504 }
1505
1506 /**
1507 * Update the clear color values for this image.
1508 */
1509 void
1510 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1511 struct radv_image *image,
1512 int cb_idx,
1513 uint32_t color_values[2])
1514 {
1515 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1516
1517 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
1518
1519 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1520 color_values);
1521 }
1522
1523 /**
1524 * Load the clear color values from the image's metadata.
1525 */
1526 static void
1527 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1528 struct radv_image *image,
1529 int cb_idx)
1530 {
1531 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1532 uint64_t va = radv_buffer_get_va(image->bo);
1533
1534 va += image->offset + image->clear_value_offset;
1535
1536 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1537 return;
1538
1539 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1540
1541 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1542 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1543 radeon_emit(cs, va);
1544 radeon_emit(cs, va >> 32);
1545 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1546 radeon_emit(cs, 2);
1547 } else {
1548 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1549 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1550 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1551 COPY_DATA_COUNT_SEL);
1552 radeon_emit(cs, va);
1553 radeon_emit(cs, va >> 32);
1554 radeon_emit(cs, reg >> 2);
1555 radeon_emit(cs, 0);
1556
1557 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1558 radeon_emit(cs, 0);
1559 }
1560 }
1561
1562 static void
1563 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1564 {
1565 int i;
1566 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1567 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1568 unsigned num_bpp64_colorbufs = 0;
1569
1570 /* this may happen for inherited secondary recording */
1571 if (!framebuffer)
1572 return;
1573
1574 for (i = 0; i < 8; ++i) {
1575 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1576 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1577 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1578 continue;
1579 }
1580
1581 int idx = subpass->color_attachments[i].attachment;
1582 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1583 struct radv_image *image = att->attachment->image;
1584 VkImageLayout layout = subpass->color_attachments[i].layout;
1585
1586 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1587
1588 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1589 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1590
1591 radv_load_color_clear_metadata(cmd_buffer, image, i);
1592
1593 if (image->surface.bpe >= 8)
1594 num_bpp64_colorbufs++;
1595 }
1596
1597 if (subpass->depth_stencil_attachment) {
1598 int idx = subpass->depth_stencil_attachment->attachment;
1599 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1600 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1601 struct radv_image *image = att->attachment->image;
1602 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1603 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1604 cmd_buffer->queue_family_index,
1605 cmd_buffer->queue_family_index);
1606 /* We currently don't support writing decompressed HTILE */
1607 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1608 radv_layout_is_htile_compressed(image, layout, queue_mask));
1609
1610 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1611
1612 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1613 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1614 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1615 }
1616 radv_load_ds_clear_metadata(cmd_buffer, image);
1617 } else {
1618 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1619 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1620 else
1621 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1622
1623 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1624 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1625 }
1626 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1627 S_028208_BR_X(framebuffer->width) |
1628 S_028208_BR_Y(framebuffer->height));
1629
1630 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1631 uint8_t watermark = 4; /* Default value for VI. */
1632
1633 /* For optimal DCC performance. */
1634 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1635 if (num_bpp64_colorbufs >= 5) {
1636 watermark = 8;
1637 } else {
1638 watermark = 6;
1639 }
1640 }
1641
1642 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
1643 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
1644 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark));
1645 }
1646
1647 if (cmd_buffer->device->dfsm_allowed) {
1648 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1649 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1650 }
1651
1652 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1653 }
1654
1655 static void
1656 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1657 {
1658 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1659 struct radv_cmd_state *state = &cmd_buffer->state;
1660
1661 if (state->index_type != state->last_index_type) {
1662 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1663 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1664 2, state->index_type);
1665 } else {
1666 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1667 radeon_emit(cs, state->index_type);
1668 }
1669
1670 state->last_index_type = state->index_type;
1671 }
1672
1673 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1674 radeon_emit(cs, state->index_va);
1675 radeon_emit(cs, state->index_va >> 32);
1676
1677 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1678 radeon_emit(cs, state->max_index_count);
1679
1680 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1681 }
1682
1683 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1684 {
1685 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1686 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1687 uint32_t pa_sc_mode_cntl_1 =
1688 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1689 uint32_t db_count_control;
1690
1691 if(!cmd_buffer->state.active_occlusion_queries) {
1692 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1693 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1694 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1695 has_perfect_queries) {
1696 /* Re-enable out-of-order rasterization if the
1697 * bound pipeline supports it and if it's has
1698 * been disabled before starting any perfect
1699 * occlusion queries.
1700 */
1701 radeon_set_context_reg(cmd_buffer->cs,
1702 R_028A4C_PA_SC_MODE_CNTL_1,
1703 pa_sc_mode_cntl_1);
1704 }
1705 }
1706 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1707 } else {
1708 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1709 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1710
1711 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1712 db_count_control =
1713 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1714 S_028004_SAMPLE_RATE(sample_rate) |
1715 S_028004_ZPASS_ENABLE(1) |
1716 S_028004_SLICE_EVEN_ENABLE(1) |
1717 S_028004_SLICE_ODD_ENABLE(1);
1718
1719 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1720 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1721 has_perfect_queries) {
1722 /* If the bound pipeline has enabled
1723 * out-of-order rasterization, we should
1724 * disable it before starting any perfect
1725 * occlusion queries.
1726 */
1727 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1728
1729 radeon_set_context_reg(cmd_buffer->cs,
1730 R_028A4C_PA_SC_MODE_CNTL_1,
1731 pa_sc_mode_cntl_1);
1732 }
1733 } else {
1734 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1735 S_028004_SAMPLE_RATE(sample_rate);
1736 }
1737 }
1738
1739 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1740
1741 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1742 }
1743
1744 static void
1745 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1746 {
1747 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1748
1749 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1750 radv_emit_viewport(cmd_buffer);
1751
1752 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1753 !cmd_buffer->device->physical_device->has_scissor_bug)
1754 radv_emit_scissor(cmd_buffer);
1755
1756 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1757 radv_emit_line_width(cmd_buffer);
1758
1759 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1760 radv_emit_blend_constants(cmd_buffer);
1761
1762 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1763 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1764 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1765 radv_emit_stencil(cmd_buffer);
1766
1767 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1768 radv_emit_depth_bounds(cmd_buffer);
1769
1770 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1771 radv_emit_depth_bias(cmd_buffer);
1772
1773 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1774 radv_emit_discard_rectangle(cmd_buffer);
1775
1776 cmd_buffer->state.dirty &= ~states;
1777 }
1778
1779 static void
1780 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1781 VkPipelineBindPoint bind_point)
1782 {
1783 struct radv_descriptor_state *descriptors_state =
1784 radv_get_descriptors_state(cmd_buffer, bind_point);
1785 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1786 unsigned bo_offset;
1787
1788 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1789 set->mapped_ptr,
1790 &bo_offset))
1791 return;
1792
1793 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1794 set->va += bo_offset;
1795 }
1796
1797 static void
1798 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1799 VkPipelineBindPoint bind_point)
1800 {
1801 struct radv_descriptor_state *descriptors_state =
1802 radv_get_descriptors_state(cmd_buffer, bind_point);
1803 uint32_t size = MAX_SETS * 4;
1804 uint32_t offset;
1805 void *ptr;
1806
1807 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1808 256, &offset, &ptr))
1809 return;
1810
1811 for (unsigned i = 0; i < MAX_SETS; i++) {
1812 uint32_t *uptr = ((uint32_t *)ptr) + i;
1813 uint64_t set_va = 0;
1814 struct radv_descriptor_set *set = descriptors_state->sets[i];
1815 if (descriptors_state->valid & (1u << i))
1816 set_va = set->va;
1817 uptr[0] = set_va & 0xffffffff;
1818 }
1819
1820 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1821 va += offset;
1822
1823 if (cmd_buffer->state.pipeline) {
1824 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1825 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1826 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1827
1828 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1829 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1830 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1831
1832 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1833 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1834 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1835
1836 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1837 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1838 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1839
1840 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1841 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1842 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1843 }
1844
1845 if (cmd_buffer->state.compute_pipeline)
1846 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1847 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1848 }
1849
1850 static void
1851 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1852 VkShaderStageFlags stages)
1853 {
1854 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1855 VK_PIPELINE_BIND_POINT_COMPUTE :
1856 VK_PIPELINE_BIND_POINT_GRAPHICS;
1857 struct radv_descriptor_state *descriptors_state =
1858 radv_get_descriptors_state(cmd_buffer, bind_point);
1859 struct radv_cmd_state *state = &cmd_buffer->state;
1860 bool flush_indirect_descriptors;
1861
1862 if (!descriptors_state->dirty)
1863 return;
1864
1865 if (descriptors_state->push_dirty)
1866 radv_flush_push_descriptors(cmd_buffer, bind_point);
1867
1868 flush_indirect_descriptors =
1869 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
1870 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
1871 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
1872 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
1873
1874 if (flush_indirect_descriptors)
1875 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1876
1877 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1878 cmd_buffer->cs,
1879 MAX_SETS * MESA_SHADER_STAGES * 4);
1880
1881 if (cmd_buffer->state.pipeline) {
1882 radv_foreach_stage(stage, stages) {
1883 if (!cmd_buffer->state.pipeline->shaders[stage])
1884 continue;
1885
1886 radv_emit_descriptor_pointers(cmd_buffer,
1887 cmd_buffer->state.pipeline,
1888 descriptors_state, stage);
1889 }
1890 }
1891
1892 if (cmd_buffer->state.compute_pipeline &&
1893 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
1894 radv_emit_descriptor_pointers(cmd_buffer,
1895 cmd_buffer->state.compute_pipeline,
1896 descriptors_state,
1897 MESA_SHADER_COMPUTE);
1898 }
1899
1900 descriptors_state->dirty = 0;
1901 descriptors_state->push_dirty = false;
1902
1903 assert(cmd_buffer->cs->cdw <= cdw_max);
1904
1905 if (unlikely(cmd_buffer->device->trace_bo))
1906 radv_save_descriptors(cmd_buffer, bind_point);
1907 }
1908
1909 static void
1910 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1911 VkShaderStageFlags stages)
1912 {
1913 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1914 ? cmd_buffer->state.compute_pipeline
1915 : cmd_buffer->state.pipeline;
1916 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1917 VK_PIPELINE_BIND_POINT_COMPUTE :
1918 VK_PIPELINE_BIND_POINT_GRAPHICS;
1919 struct radv_descriptor_state *descriptors_state =
1920 radv_get_descriptors_state(cmd_buffer, bind_point);
1921 struct radv_pipeline_layout *layout = pipeline->layout;
1922 struct radv_shader_variant *shader, *prev_shader;
1923 bool need_push_constants = false;
1924 unsigned offset;
1925 void *ptr;
1926 uint64_t va;
1927
1928 stages &= cmd_buffer->push_constant_stages;
1929 if (!stages ||
1930 (!layout->push_constant_size && !layout->dynamic_offset_count))
1931 return;
1932
1933 radv_foreach_stage(stage, stages) {
1934 if (!pipeline->shaders[stage])
1935 continue;
1936
1937 need_push_constants |= pipeline->shaders[stage]->info.info.loads_push_constants;
1938 need_push_constants |= pipeline->shaders[stage]->info.info.loads_dynamic_offsets;
1939
1940 uint8_t base = pipeline->shaders[stage]->info.info.base_inline_push_consts;
1941 uint8_t count = pipeline->shaders[stage]->info.info.num_inline_push_consts;
1942
1943 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
1944 AC_UD_INLINE_PUSH_CONSTANTS,
1945 count,
1946 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
1947 }
1948
1949 if (need_push_constants) {
1950 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1951 16 * layout->dynamic_offset_count,
1952 256, &offset, &ptr))
1953 return;
1954
1955 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1956 memcpy((char*)ptr + layout->push_constant_size,
1957 descriptors_state->dynamic_buffers,
1958 16 * layout->dynamic_offset_count);
1959
1960 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1961 va += offset;
1962
1963 MAYBE_UNUSED unsigned cdw_max =
1964 radeon_check_space(cmd_buffer->device->ws,
1965 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1966
1967 prev_shader = NULL;
1968 radv_foreach_stage(stage, stages) {
1969 shader = radv_get_shader(pipeline, stage);
1970
1971 /* Avoid redundantly emitting the address for merged stages. */
1972 if (shader && shader != prev_shader) {
1973 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1974 AC_UD_PUSH_CONSTANTS, va);
1975
1976 prev_shader = shader;
1977 }
1978 }
1979 assert(cmd_buffer->cs->cdw <= cdw_max);
1980 }
1981
1982 cmd_buffer->push_constant_stages &= ~stages;
1983 }
1984
1985 static void
1986 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1987 bool pipeline_is_dirty)
1988 {
1989 if ((pipeline_is_dirty ||
1990 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1991 cmd_buffer->state.pipeline->vertex_elements.count &&
1992 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
1993 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1994 unsigned vb_offset;
1995 void *vb_ptr;
1996 uint32_t i = 0;
1997 uint32_t count = velems->count;
1998 uint64_t va;
1999
2000 /* allocate some descriptor state for vertex buffers */
2001 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2002 &vb_offset, &vb_ptr))
2003 return;
2004
2005 for (i = 0; i < count; i++) {
2006 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2007 uint32_t offset;
2008 int vb = velems->binding[i];
2009 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
2010 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
2011
2012 va = radv_buffer_get_va(buffer->bo);
2013
2014 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
2015 va += offset + buffer->offset;
2016 desc[0] = va;
2017 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2018 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
2019 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
2020 else
2021 desc[2] = buffer->size - offset;
2022 desc[3] = velems->rsrc_word3[i];
2023 }
2024
2025 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2026 va += vb_offset;
2027
2028 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2029 AC_UD_VS_VERTEX_BUFFERS, va);
2030
2031 cmd_buffer->state.vb_va = va;
2032 cmd_buffer->state.vb_size = count * 16;
2033 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2034 }
2035 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2036 }
2037
2038 static void
2039 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2040 {
2041 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2042 struct radv_userdata_info *loc;
2043 uint32_t base_reg;
2044
2045 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2046 if (!radv_get_shader(pipeline, stage))
2047 continue;
2048
2049 loc = radv_lookup_user_sgpr(pipeline, stage,
2050 AC_UD_STREAMOUT_BUFFERS);
2051 if (loc->sgpr_idx == -1)
2052 continue;
2053
2054 base_reg = pipeline->user_data_0[stage];
2055
2056 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2057 base_reg + loc->sgpr_idx * 4, va, false);
2058 }
2059
2060 if (pipeline->gs_copy_shader) {
2061 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2062 if (loc->sgpr_idx != -1) {
2063 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2064
2065 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2066 base_reg + loc->sgpr_idx * 4, va, false);
2067 }
2068 }
2069 }
2070
2071 static void
2072 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2073 {
2074 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2075 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2076 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2077 unsigned so_offset;
2078 void *so_ptr;
2079 uint64_t va;
2080
2081 /* Allocate some descriptor state for streamout buffers. */
2082 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2083 MAX_SO_BUFFERS * 16, 256,
2084 &so_offset, &so_ptr))
2085 return;
2086
2087 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2088 struct radv_buffer *buffer = sb[i].buffer;
2089 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2090
2091 if (!(so->enabled_mask & (1 << i)))
2092 continue;
2093
2094 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2095
2096 va += sb[i].offset;
2097
2098 /* Set the descriptor.
2099 *
2100 * On VI, the format must be non-INVALID, otherwise
2101 * the buffer will be considered not bound and store
2102 * instructions will be no-ops.
2103 */
2104 desc[0] = va;
2105 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2106 desc[2] = 0xffffffff;
2107 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2108 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2109 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2110 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2111 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2112 }
2113
2114 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2115 va += so_offset;
2116
2117 radv_emit_streamout_buffers(cmd_buffer, va);
2118 }
2119
2120 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2121 }
2122
2123 static void
2124 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2125 {
2126 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2127 radv_flush_streamout_descriptors(cmd_buffer);
2128 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2129 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2130 }
2131
2132 struct radv_draw_info {
2133 /**
2134 * Number of vertices.
2135 */
2136 uint32_t count;
2137
2138 /**
2139 * Index of the first vertex.
2140 */
2141 int32_t vertex_offset;
2142
2143 /**
2144 * First instance id.
2145 */
2146 uint32_t first_instance;
2147
2148 /**
2149 * Number of instances.
2150 */
2151 uint32_t instance_count;
2152
2153 /**
2154 * First index (indexed draws only).
2155 */
2156 uint32_t first_index;
2157
2158 /**
2159 * Whether it's an indexed draw.
2160 */
2161 bool indexed;
2162
2163 /**
2164 * Indirect draw parameters resource.
2165 */
2166 struct radv_buffer *indirect;
2167 uint64_t indirect_offset;
2168 uint32_t stride;
2169
2170 /**
2171 * Draw count parameters resource.
2172 */
2173 struct radv_buffer *count_buffer;
2174 uint64_t count_buffer_offset;
2175
2176 /**
2177 * Stream output parameters resource.
2178 */
2179 struct radv_buffer *strmout_buffer;
2180 uint64_t strmout_buffer_offset;
2181 };
2182
2183 static void
2184 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2185 const struct radv_draw_info *draw_info)
2186 {
2187 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2188 struct radv_cmd_state *state = &cmd_buffer->state;
2189 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2190 uint32_t ia_multi_vgt_param;
2191 int32_t primitive_reset_en;
2192
2193 /* Draw state. */
2194 ia_multi_vgt_param =
2195 si_get_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2196 draw_info->indirect,
2197 draw_info->indirect ? 0 : draw_info->count);
2198
2199 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2200 if (info->chip_class >= GFX9) {
2201 radeon_set_uconfig_reg_idx(cs,
2202 R_030960_IA_MULTI_VGT_PARAM,
2203 4, ia_multi_vgt_param);
2204 } else if (info->chip_class >= CIK) {
2205 radeon_set_context_reg_idx(cs,
2206 R_028AA8_IA_MULTI_VGT_PARAM,
2207 1, ia_multi_vgt_param);
2208 } else {
2209 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2210 ia_multi_vgt_param);
2211 }
2212 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2213 }
2214
2215 /* Primitive restart. */
2216 primitive_reset_en =
2217 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2218
2219 if (primitive_reset_en != state->last_primitive_reset_en) {
2220 state->last_primitive_reset_en = primitive_reset_en;
2221 if (info->chip_class >= GFX9) {
2222 radeon_set_uconfig_reg(cs,
2223 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2224 primitive_reset_en);
2225 } else {
2226 radeon_set_context_reg(cs,
2227 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2228 primitive_reset_en);
2229 }
2230 }
2231
2232 if (primitive_reset_en) {
2233 uint32_t primitive_reset_index =
2234 state->index_type ? 0xffffffffu : 0xffffu;
2235
2236 if (primitive_reset_index != state->last_primitive_reset_index) {
2237 radeon_set_context_reg(cs,
2238 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2239 primitive_reset_index);
2240 state->last_primitive_reset_index = primitive_reset_index;
2241 }
2242 }
2243
2244 if (draw_info->strmout_buffer) {
2245 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2246
2247 va += draw_info->strmout_buffer->offset +
2248 draw_info->strmout_buffer_offset;
2249
2250 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2251 draw_info->stride);
2252
2253 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2254 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2255 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2256 COPY_DATA_WR_CONFIRM);
2257 radeon_emit(cs, va);
2258 radeon_emit(cs, va >> 32);
2259 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2260 radeon_emit(cs, 0); /* unused */
2261
2262 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2263 }
2264 }
2265
2266 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2267 VkPipelineStageFlags src_stage_mask)
2268 {
2269 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2270 VK_PIPELINE_STAGE_TRANSFER_BIT |
2271 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2272 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2273 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2274 }
2275
2276 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2277 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2278 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2279 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2280 VK_PIPELINE_STAGE_TRANSFER_BIT |
2281 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2282 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2283 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2284 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2285 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2286 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2287 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2288 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2289 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2290 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2291 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2292 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2293 }
2294 }
2295
2296 static enum radv_cmd_flush_bits
2297 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2298 VkAccessFlags src_flags,
2299 struct radv_image *image)
2300 {
2301 bool flush_CB_meta = true, flush_DB_meta = true;
2302 enum radv_cmd_flush_bits flush_bits = 0;
2303 uint32_t b;
2304
2305 if (image) {
2306 if (!radv_image_has_CB_metadata(image))
2307 flush_CB_meta = false;
2308 if (!radv_image_has_htile(image))
2309 flush_DB_meta = false;
2310 }
2311
2312 for_each_bit(b, src_flags) {
2313 switch ((VkAccessFlagBits)(1 << b)) {
2314 case VK_ACCESS_SHADER_WRITE_BIT:
2315 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2316 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2317 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2318 break;
2319 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2320 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2321 if (flush_CB_meta)
2322 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2323 break;
2324 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2325 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2326 if (flush_DB_meta)
2327 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2328 break;
2329 case VK_ACCESS_TRANSFER_WRITE_BIT:
2330 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2331 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2332 RADV_CMD_FLAG_INV_GLOBAL_L2;
2333
2334 if (flush_CB_meta)
2335 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2336 if (flush_DB_meta)
2337 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2338 break;
2339 default:
2340 break;
2341 }
2342 }
2343 return flush_bits;
2344 }
2345
2346 static enum radv_cmd_flush_bits
2347 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2348 VkAccessFlags dst_flags,
2349 struct radv_image *image)
2350 {
2351 bool flush_CB_meta = true, flush_DB_meta = true;
2352 enum radv_cmd_flush_bits flush_bits = 0;
2353 bool flush_CB = true, flush_DB = true;
2354 bool image_is_coherent = false;
2355 uint32_t b;
2356
2357 if (image) {
2358 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2359 flush_CB = false;
2360 flush_DB = false;
2361 }
2362
2363 if (!radv_image_has_CB_metadata(image))
2364 flush_CB_meta = false;
2365 if (!radv_image_has_htile(image))
2366 flush_DB_meta = false;
2367
2368 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2369 if (image->info.samples == 1 &&
2370 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2371 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2372 !vk_format_is_stencil(image->vk_format)) {
2373 /* Single-sample color and single-sample depth
2374 * (not stencil) are coherent with shaders on
2375 * GFX9.
2376 */
2377 image_is_coherent = true;
2378 }
2379 }
2380 }
2381
2382 for_each_bit(b, dst_flags) {
2383 switch ((VkAccessFlagBits)(1 << b)) {
2384 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2385 case VK_ACCESS_INDEX_READ_BIT:
2386 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2387 break;
2388 case VK_ACCESS_UNIFORM_READ_BIT:
2389 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2390 break;
2391 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2392 case VK_ACCESS_TRANSFER_READ_BIT:
2393 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2394 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2395 RADV_CMD_FLAG_INV_GLOBAL_L2;
2396 break;
2397 case VK_ACCESS_SHADER_READ_BIT:
2398 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2399
2400 if (!image_is_coherent)
2401 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2402 break;
2403 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2404 if (flush_CB)
2405 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2406 if (flush_CB_meta)
2407 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2408 break;
2409 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2410 if (flush_DB)
2411 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2412 if (flush_DB_meta)
2413 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2414 break;
2415 default:
2416 break;
2417 }
2418 }
2419 return flush_bits;
2420 }
2421
2422 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2423 const struct radv_subpass_barrier *barrier)
2424 {
2425 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2426 NULL);
2427 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2428 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2429 NULL);
2430 }
2431
2432 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2433 struct radv_subpass_attachment att)
2434 {
2435 unsigned idx = att.attachment;
2436 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2437 VkImageSubresourceRange range;
2438 range.aspectMask = 0;
2439 range.baseMipLevel = view->base_mip;
2440 range.levelCount = 1;
2441 range.baseArrayLayer = view->base_layer;
2442 range.layerCount = cmd_buffer->state.framebuffer->layers;
2443
2444 if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask) {
2445 /* If the current subpass uses multiview, the driver might have
2446 * performed a fast color/depth clear to the whole image
2447 * (including all layers). To make sure the driver will
2448 * decompress the image correctly (if needed), we have to
2449 * account for the "real" number of layers. If the view mask is
2450 * sparse, this will decompress more layers than needed.
2451 */
2452 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
2453 }
2454
2455 radv_handle_image_transition(cmd_buffer,
2456 view->image,
2457 cmd_buffer->state.attachments[idx].current_layout,
2458 att.layout, 0, 0, &range);
2459
2460 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2461
2462
2463 }
2464
2465 void
2466 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2467 const struct radv_subpass *subpass)
2468 {
2469 cmd_buffer->state.subpass = subpass;
2470
2471 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2472 }
2473
2474 static VkResult
2475 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2476 struct radv_render_pass *pass,
2477 const VkRenderPassBeginInfo *info)
2478 {
2479 struct radv_cmd_state *state = &cmd_buffer->state;
2480
2481 if (pass->attachment_count == 0) {
2482 state->attachments = NULL;
2483 return VK_SUCCESS;
2484 }
2485
2486 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2487 pass->attachment_count *
2488 sizeof(state->attachments[0]),
2489 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2490 if (state->attachments == NULL) {
2491 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2492 return cmd_buffer->record_result;
2493 }
2494
2495 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2496 struct radv_render_pass_attachment *att = &pass->attachments[i];
2497 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2498 VkImageAspectFlags clear_aspects = 0;
2499
2500 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2501 /* color attachment */
2502 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2503 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2504 }
2505 } else {
2506 /* depthstencil attachment */
2507 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2508 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2509 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2510 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2511 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2512 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2513 }
2514 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2515 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2516 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2517 }
2518 }
2519
2520 state->attachments[i].pending_clear_aspects = clear_aspects;
2521 state->attachments[i].cleared_views = 0;
2522 if (clear_aspects && info) {
2523 assert(info->clearValueCount > i);
2524 state->attachments[i].clear_value = info->pClearValues[i];
2525 }
2526
2527 state->attachments[i].current_layout = att->initial_layout;
2528 }
2529
2530 return VK_SUCCESS;
2531 }
2532
2533 VkResult radv_AllocateCommandBuffers(
2534 VkDevice _device,
2535 const VkCommandBufferAllocateInfo *pAllocateInfo,
2536 VkCommandBuffer *pCommandBuffers)
2537 {
2538 RADV_FROM_HANDLE(radv_device, device, _device);
2539 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2540
2541 VkResult result = VK_SUCCESS;
2542 uint32_t i;
2543
2544 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2545
2546 if (!list_empty(&pool->free_cmd_buffers)) {
2547 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2548
2549 list_del(&cmd_buffer->pool_link);
2550 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2551
2552 result = radv_reset_cmd_buffer(cmd_buffer);
2553 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2554 cmd_buffer->level = pAllocateInfo->level;
2555
2556 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2557 } else {
2558 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2559 &pCommandBuffers[i]);
2560 }
2561 if (result != VK_SUCCESS)
2562 break;
2563 }
2564
2565 if (result != VK_SUCCESS) {
2566 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2567 i, pCommandBuffers);
2568
2569 /* From the Vulkan 1.0.66 spec:
2570 *
2571 * "vkAllocateCommandBuffers can be used to create multiple
2572 * command buffers. If the creation of any of those command
2573 * buffers fails, the implementation must destroy all
2574 * successfully created command buffer objects from this
2575 * command, set all entries of the pCommandBuffers array to
2576 * NULL and return the error."
2577 */
2578 memset(pCommandBuffers, 0,
2579 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2580 }
2581
2582 return result;
2583 }
2584
2585 void radv_FreeCommandBuffers(
2586 VkDevice device,
2587 VkCommandPool commandPool,
2588 uint32_t commandBufferCount,
2589 const VkCommandBuffer *pCommandBuffers)
2590 {
2591 for (uint32_t i = 0; i < commandBufferCount; i++) {
2592 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2593
2594 if (cmd_buffer) {
2595 if (cmd_buffer->pool) {
2596 list_del(&cmd_buffer->pool_link);
2597 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2598 } else
2599 radv_cmd_buffer_destroy(cmd_buffer);
2600
2601 }
2602 }
2603 }
2604
2605 VkResult radv_ResetCommandBuffer(
2606 VkCommandBuffer commandBuffer,
2607 VkCommandBufferResetFlags flags)
2608 {
2609 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2610 return radv_reset_cmd_buffer(cmd_buffer);
2611 }
2612
2613 VkResult radv_BeginCommandBuffer(
2614 VkCommandBuffer commandBuffer,
2615 const VkCommandBufferBeginInfo *pBeginInfo)
2616 {
2617 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2618 VkResult result = VK_SUCCESS;
2619
2620 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2621 /* If the command buffer has already been resetted with
2622 * vkResetCommandBuffer, no need to do it again.
2623 */
2624 result = radv_reset_cmd_buffer(cmd_buffer);
2625 if (result != VK_SUCCESS)
2626 return result;
2627 }
2628
2629 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2630 cmd_buffer->state.last_primitive_reset_en = -1;
2631 cmd_buffer->state.last_index_type = -1;
2632 cmd_buffer->state.last_num_instances = -1;
2633 cmd_buffer->state.last_vertex_offset = -1;
2634 cmd_buffer->state.last_first_instance = -1;
2635 cmd_buffer->state.predication_type = -1;
2636 cmd_buffer->usage_flags = pBeginInfo->flags;
2637
2638 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
2639 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
2640 assert(pBeginInfo->pInheritanceInfo);
2641 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2642 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2643
2644 struct radv_subpass *subpass =
2645 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2646
2647 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2648 if (result != VK_SUCCESS)
2649 return result;
2650
2651 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
2652 }
2653
2654 if (unlikely(cmd_buffer->device->trace_bo)) {
2655 struct radv_device *device = cmd_buffer->device;
2656
2657 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
2658 device->trace_bo);
2659
2660 radv_cmd_buffer_trace_emit(cmd_buffer);
2661 }
2662
2663 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2664
2665 return result;
2666 }
2667
2668 void radv_CmdBindVertexBuffers(
2669 VkCommandBuffer commandBuffer,
2670 uint32_t firstBinding,
2671 uint32_t bindingCount,
2672 const VkBuffer* pBuffers,
2673 const VkDeviceSize* pOffsets)
2674 {
2675 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2676 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2677 bool changed = false;
2678
2679 /* We have to defer setting up vertex buffer since we need the buffer
2680 * stride from the pipeline. */
2681
2682 assert(firstBinding + bindingCount <= MAX_VBS);
2683 for (uint32_t i = 0; i < bindingCount; i++) {
2684 uint32_t idx = firstBinding + i;
2685
2686 if (!changed &&
2687 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2688 vb[idx].offset != pOffsets[i])) {
2689 changed = true;
2690 }
2691
2692 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2693 vb[idx].offset = pOffsets[i];
2694
2695 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2696 vb[idx].buffer->bo);
2697 }
2698
2699 if (!changed) {
2700 /* No state changes. */
2701 return;
2702 }
2703
2704 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2705 }
2706
2707 void radv_CmdBindIndexBuffer(
2708 VkCommandBuffer commandBuffer,
2709 VkBuffer buffer,
2710 VkDeviceSize offset,
2711 VkIndexType indexType)
2712 {
2713 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2714 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2715
2716 if (cmd_buffer->state.index_buffer == index_buffer &&
2717 cmd_buffer->state.index_offset == offset &&
2718 cmd_buffer->state.index_type == indexType) {
2719 /* No state changes. */
2720 return;
2721 }
2722
2723 cmd_buffer->state.index_buffer = index_buffer;
2724 cmd_buffer->state.index_offset = offset;
2725 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2726 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2727 cmd_buffer->state.index_va += index_buffer->offset + offset;
2728
2729 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2730 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2731 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2732 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
2733 }
2734
2735
2736 static void
2737 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2738 VkPipelineBindPoint bind_point,
2739 struct radv_descriptor_set *set, unsigned idx)
2740 {
2741 struct radeon_winsys *ws = cmd_buffer->device->ws;
2742
2743 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2744
2745 assert(set);
2746 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2747
2748 if (!cmd_buffer->device->use_global_bo_list) {
2749 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2750 if (set->descriptors[j])
2751 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
2752 }
2753
2754 if(set->bo)
2755 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
2756 }
2757
2758 void radv_CmdBindDescriptorSets(
2759 VkCommandBuffer commandBuffer,
2760 VkPipelineBindPoint pipelineBindPoint,
2761 VkPipelineLayout _layout,
2762 uint32_t firstSet,
2763 uint32_t descriptorSetCount,
2764 const VkDescriptorSet* pDescriptorSets,
2765 uint32_t dynamicOffsetCount,
2766 const uint32_t* pDynamicOffsets)
2767 {
2768 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2769 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2770 unsigned dyn_idx = 0;
2771
2772 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2773 struct radv_descriptor_state *descriptors_state =
2774 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2775
2776 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2777 unsigned idx = i + firstSet;
2778 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2779 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2780
2781 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2782 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2783 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
2784 assert(dyn_idx < dynamicOffsetCount);
2785
2786 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2787 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2788 dst[0] = va;
2789 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2790 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2791 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2792 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2793 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2794 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2795 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2796 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2797 cmd_buffer->push_constant_stages |=
2798 set->layout->dynamic_shader_stages;
2799 }
2800 }
2801 }
2802
2803 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2804 struct radv_descriptor_set *set,
2805 struct radv_descriptor_set_layout *layout,
2806 VkPipelineBindPoint bind_point)
2807 {
2808 struct radv_descriptor_state *descriptors_state =
2809 radv_get_descriptors_state(cmd_buffer, bind_point);
2810 set->size = layout->size;
2811 set->layout = layout;
2812
2813 if (descriptors_state->push_set.capacity < set->size) {
2814 size_t new_size = MAX2(set->size, 1024);
2815 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2816 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2817
2818 free(set->mapped_ptr);
2819 set->mapped_ptr = malloc(new_size);
2820
2821 if (!set->mapped_ptr) {
2822 descriptors_state->push_set.capacity = 0;
2823 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2824 return false;
2825 }
2826
2827 descriptors_state->push_set.capacity = new_size;
2828 }
2829
2830 return true;
2831 }
2832
2833 void radv_meta_push_descriptor_set(
2834 struct radv_cmd_buffer* cmd_buffer,
2835 VkPipelineBindPoint pipelineBindPoint,
2836 VkPipelineLayout _layout,
2837 uint32_t set,
2838 uint32_t descriptorWriteCount,
2839 const VkWriteDescriptorSet* pDescriptorWrites)
2840 {
2841 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2842 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2843 unsigned bo_offset;
2844
2845 assert(set == 0);
2846 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2847
2848 push_set->size = layout->set[set].layout->size;
2849 push_set->layout = layout->set[set].layout;
2850
2851 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2852 &bo_offset,
2853 (void**) &push_set->mapped_ptr))
2854 return;
2855
2856 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2857 push_set->va += bo_offset;
2858
2859 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2860 radv_descriptor_set_to_handle(push_set),
2861 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2862
2863 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2864 }
2865
2866 void radv_CmdPushDescriptorSetKHR(
2867 VkCommandBuffer commandBuffer,
2868 VkPipelineBindPoint pipelineBindPoint,
2869 VkPipelineLayout _layout,
2870 uint32_t set,
2871 uint32_t descriptorWriteCount,
2872 const VkWriteDescriptorSet* pDescriptorWrites)
2873 {
2874 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2875 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2876 struct radv_descriptor_state *descriptors_state =
2877 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2878 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2879
2880 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2881
2882 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2883 layout->set[set].layout,
2884 pipelineBindPoint))
2885 return;
2886
2887 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2888 radv_descriptor_set_to_handle(push_set),
2889 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2890
2891 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2892 descriptors_state->push_dirty = true;
2893 }
2894
2895 void radv_CmdPushDescriptorSetWithTemplateKHR(
2896 VkCommandBuffer commandBuffer,
2897 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
2898 VkPipelineLayout _layout,
2899 uint32_t set,
2900 const void* pData)
2901 {
2902 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2903 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2904 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2905 struct radv_descriptor_state *descriptors_state =
2906 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2907 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2908
2909 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2910
2911 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2912 layout->set[set].layout,
2913 templ->bind_point))
2914 return;
2915
2916 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2917 descriptorUpdateTemplate, pData);
2918
2919 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2920 descriptors_state->push_dirty = true;
2921 }
2922
2923 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2924 VkPipelineLayout layout,
2925 VkShaderStageFlags stageFlags,
2926 uint32_t offset,
2927 uint32_t size,
2928 const void* pValues)
2929 {
2930 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2931 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2932 cmd_buffer->push_constant_stages |= stageFlags;
2933 }
2934
2935 VkResult radv_EndCommandBuffer(
2936 VkCommandBuffer commandBuffer)
2937 {
2938 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2939
2940 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2941 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2942 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2943 si_emit_cache_flush(cmd_buffer);
2944 }
2945
2946 /* Make sure CP DMA is idle at the end of IBs because the kernel
2947 * doesn't wait for it.
2948 */
2949 si_cp_dma_wait_for_idle(cmd_buffer);
2950
2951 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2952
2953 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2954 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2955
2956 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2957
2958 return cmd_buffer->record_result;
2959 }
2960
2961 static void
2962 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2963 {
2964 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2965
2966 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2967 return;
2968
2969 assert(!pipeline->ctx_cs.cdw);
2970
2971 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2972
2973 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2974 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2975
2976 cmd_buffer->compute_scratch_size_needed =
2977 MAX2(cmd_buffer->compute_scratch_size_needed,
2978 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2979
2980 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2981 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
2982
2983 if (unlikely(cmd_buffer->device->trace_bo))
2984 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2985 }
2986
2987 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2988 VkPipelineBindPoint bind_point)
2989 {
2990 struct radv_descriptor_state *descriptors_state =
2991 radv_get_descriptors_state(cmd_buffer, bind_point);
2992
2993 descriptors_state->dirty |= descriptors_state->valid;
2994 }
2995
2996 void radv_CmdBindPipeline(
2997 VkCommandBuffer commandBuffer,
2998 VkPipelineBindPoint pipelineBindPoint,
2999 VkPipeline _pipeline)
3000 {
3001 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3002 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3003
3004 switch (pipelineBindPoint) {
3005 case VK_PIPELINE_BIND_POINT_COMPUTE:
3006 if (cmd_buffer->state.compute_pipeline == pipeline)
3007 return;
3008 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3009
3010 cmd_buffer->state.compute_pipeline = pipeline;
3011 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3012 break;
3013 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3014 if (cmd_buffer->state.pipeline == pipeline)
3015 return;
3016 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3017
3018 cmd_buffer->state.pipeline = pipeline;
3019 if (!pipeline)
3020 break;
3021
3022 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3023 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3024
3025 /* the new vertex shader might not have the same user regs */
3026 cmd_buffer->state.last_first_instance = -1;
3027 cmd_buffer->state.last_vertex_offset = -1;
3028
3029 /* Prefetch all pipeline shaders at first draw time. */
3030 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3031
3032 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3033 radv_bind_streamout_state(cmd_buffer, pipeline);
3034
3035 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3036 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3037 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3038 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3039
3040 if (radv_pipeline_has_tess(pipeline))
3041 cmd_buffer->tess_rings_needed = true;
3042 break;
3043 default:
3044 assert(!"invalid bind point");
3045 break;
3046 }
3047 }
3048
3049 void radv_CmdSetViewport(
3050 VkCommandBuffer commandBuffer,
3051 uint32_t firstViewport,
3052 uint32_t viewportCount,
3053 const VkViewport* pViewports)
3054 {
3055 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3056 struct radv_cmd_state *state = &cmd_buffer->state;
3057 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
3058
3059 assert(firstViewport < MAX_VIEWPORTS);
3060 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3061
3062 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3063 pViewports, viewportCount * sizeof(*pViewports))) {
3064 return;
3065 }
3066
3067 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3068 viewportCount * sizeof(*pViewports));
3069
3070 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3071 }
3072
3073 void radv_CmdSetScissor(
3074 VkCommandBuffer commandBuffer,
3075 uint32_t firstScissor,
3076 uint32_t scissorCount,
3077 const VkRect2D* pScissors)
3078 {
3079 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3080 struct radv_cmd_state *state = &cmd_buffer->state;
3081 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
3082
3083 assert(firstScissor < MAX_SCISSORS);
3084 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3085
3086 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3087 scissorCount * sizeof(*pScissors))) {
3088 return;
3089 }
3090
3091 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3092 scissorCount * sizeof(*pScissors));
3093
3094 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3095 }
3096
3097 void radv_CmdSetLineWidth(
3098 VkCommandBuffer commandBuffer,
3099 float lineWidth)
3100 {
3101 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3102
3103 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3104 return;
3105
3106 cmd_buffer->state.dynamic.line_width = lineWidth;
3107 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3108 }
3109
3110 void radv_CmdSetDepthBias(
3111 VkCommandBuffer commandBuffer,
3112 float depthBiasConstantFactor,
3113 float depthBiasClamp,
3114 float depthBiasSlopeFactor)
3115 {
3116 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3117 struct radv_cmd_state *state = &cmd_buffer->state;
3118
3119 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3120 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3121 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3122 return;
3123 }
3124
3125 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3126 state->dynamic.depth_bias.clamp = depthBiasClamp;
3127 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3128
3129 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3130 }
3131
3132 void radv_CmdSetBlendConstants(
3133 VkCommandBuffer commandBuffer,
3134 const float blendConstants[4])
3135 {
3136 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3137 struct radv_cmd_state *state = &cmd_buffer->state;
3138
3139 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3140 return;
3141
3142 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
3143
3144 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3145 }
3146
3147 void radv_CmdSetDepthBounds(
3148 VkCommandBuffer commandBuffer,
3149 float minDepthBounds,
3150 float maxDepthBounds)
3151 {
3152 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3153 struct radv_cmd_state *state = &cmd_buffer->state;
3154
3155 if (state->dynamic.depth_bounds.min == minDepthBounds &&
3156 state->dynamic.depth_bounds.max == maxDepthBounds) {
3157 return;
3158 }
3159
3160 state->dynamic.depth_bounds.min = minDepthBounds;
3161 state->dynamic.depth_bounds.max = maxDepthBounds;
3162
3163 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
3164 }
3165
3166 void radv_CmdSetStencilCompareMask(
3167 VkCommandBuffer commandBuffer,
3168 VkStencilFaceFlags faceMask,
3169 uint32_t compareMask)
3170 {
3171 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3172 struct radv_cmd_state *state = &cmd_buffer->state;
3173 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
3174 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
3175
3176 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3177 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3178 return;
3179 }
3180
3181 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3182 state->dynamic.stencil_compare_mask.front = compareMask;
3183 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3184 state->dynamic.stencil_compare_mask.back = compareMask;
3185
3186 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
3187 }
3188
3189 void radv_CmdSetStencilWriteMask(
3190 VkCommandBuffer commandBuffer,
3191 VkStencilFaceFlags faceMask,
3192 uint32_t writeMask)
3193 {
3194 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3195 struct radv_cmd_state *state = &cmd_buffer->state;
3196 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
3197 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
3198
3199 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3200 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3201 return;
3202 }
3203
3204 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3205 state->dynamic.stencil_write_mask.front = writeMask;
3206 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3207 state->dynamic.stencil_write_mask.back = writeMask;
3208
3209 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
3210 }
3211
3212 void radv_CmdSetStencilReference(
3213 VkCommandBuffer commandBuffer,
3214 VkStencilFaceFlags faceMask,
3215 uint32_t reference)
3216 {
3217 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3218 struct radv_cmd_state *state = &cmd_buffer->state;
3219 bool front_same = state->dynamic.stencil_reference.front == reference;
3220 bool back_same = state->dynamic.stencil_reference.back == reference;
3221
3222 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3223 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3224 return;
3225 }
3226
3227 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3228 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3229 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3230 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3231
3232 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3233 }
3234
3235 void radv_CmdSetDiscardRectangleEXT(
3236 VkCommandBuffer commandBuffer,
3237 uint32_t firstDiscardRectangle,
3238 uint32_t discardRectangleCount,
3239 const VkRect2D* pDiscardRectangles)
3240 {
3241 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3242 struct radv_cmd_state *state = &cmd_buffer->state;
3243 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3244
3245 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3246 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3247
3248 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
3249 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
3250 return;
3251 }
3252
3253 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3254 pDiscardRectangles, discardRectangleCount);
3255
3256 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3257 }
3258
3259 void radv_CmdExecuteCommands(
3260 VkCommandBuffer commandBuffer,
3261 uint32_t commandBufferCount,
3262 const VkCommandBuffer* pCmdBuffers)
3263 {
3264 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3265
3266 assert(commandBufferCount > 0);
3267
3268 /* Emit pending flushes on primary prior to executing secondary */
3269 si_emit_cache_flush(primary);
3270
3271 for (uint32_t i = 0; i < commandBufferCount; i++) {
3272 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3273
3274 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3275 secondary->scratch_size_needed);
3276 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3277 secondary->compute_scratch_size_needed);
3278
3279 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
3280 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
3281 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
3282 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
3283 if (secondary->tess_rings_needed)
3284 primary->tess_rings_needed = true;
3285 if (secondary->sample_positions_needed)
3286 primary->sample_positions_needed = true;
3287
3288 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
3289
3290
3291 /* When the secondary command buffer is compute only we don't
3292 * need to re-emit the current graphics pipeline.
3293 */
3294 if (secondary->state.emitted_pipeline) {
3295 primary->state.emitted_pipeline =
3296 secondary->state.emitted_pipeline;
3297 }
3298
3299 /* When the secondary command buffer is graphics only we don't
3300 * need to re-emit the current compute pipeline.
3301 */
3302 if (secondary->state.emitted_compute_pipeline) {
3303 primary->state.emitted_compute_pipeline =
3304 secondary->state.emitted_compute_pipeline;
3305 }
3306
3307 /* Only re-emit the draw packets when needed. */
3308 if (secondary->state.last_primitive_reset_en != -1) {
3309 primary->state.last_primitive_reset_en =
3310 secondary->state.last_primitive_reset_en;
3311 }
3312
3313 if (secondary->state.last_primitive_reset_index) {
3314 primary->state.last_primitive_reset_index =
3315 secondary->state.last_primitive_reset_index;
3316 }
3317
3318 if (secondary->state.last_ia_multi_vgt_param) {
3319 primary->state.last_ia_multi_vgt_param =
3320 secondary->state.last_ia_multi_vgt_param;
3321 }
3322
3323 primary->state.last_first_instance = secondary->state.last_first_instance;
3324 primary->state.last_num_instances = secondary->state.last_num_instances;
3325 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
3326
3327 if (secondary->state.last_index_type != -1) {
3328 primary->state.last_index_type =
3329 secondary->state.last_index_type;
3330 }
3331 }
3332
3333 /* After executing commands from secondary buffers we have to dirty
3334 * some states.
3335 */
3336 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
3337 RADV_CMD_DIRTY_INDEX_BUFFER |
3338 RADV_CMD_DIRTY_DYNAMIC_ALL;
3339 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
3340 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
3341 }
3342
3343 VkResult radv_CreateCommandPool(
3344 VkDevice _device,
3345 const VkCommandPoolCreateInfo* pCreateInfo,
3346 const VkAllocationCallbacks* pAllocator,
3347 VkCommandPool* pCmdPool)
3348 {
3349 RADV_FROM_HANDLE(radv_device, device, _device);
3350 struct radv_cmd_pool *pool;
3351
3352 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3353 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3354 if (pool == NULL)
3355 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3356
3357 if (pAllocator)
3358 pool->alloc = *pAllocator;
3359 else
3360 pool->alloc = device->alloc;
3361
3362 list_inithead(&pool->cmd_buffers);
3363 list_inithead(&pool->free_cmd_buffers);
3364
3365 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3366
3367 *pCmdPool = radv_cmd_pool_to_handle(pool);
3368
3369 return VK_SUCCESS;
3370
3371 }
3372
3373 void radv_DestroyCommandPool(
3374 VkDevice _device,
3375 VkCommandPool commandPool,
3376 const VkAllocationCallbacks* pAllocator)
3377 {
3378 RADV_FROM_HANDLE(radv_device, device, _device);
3379 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3380
3381 if (!pool)
3382 return;
3383
3384 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3385 &pool->cmd_buffers, pool_link) {
3386 radv_cmd_buffer_destroy(cmd_buffer);
3387 }
3388
3389 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3390 &pool->free_cmd_buffers, pool_link) {
3391 radv_cmd_buffer_destroy(cmd_buffer);
3392 }
3393
3394 vk_free2(&device->alloc, pAllocator, pool);
3395 }
3396
3397 VkResult radv_ResetCommandPool(
3398 VkDevice device,
3399 VkCommandPool commandPool,
3400 VkCommandPoolResetFlags flags)
3401 {
3402 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3403 VkResult result;
3404
3405 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3406 &pool->cmd_buffers, pool_link) {
3407 result = radv_reset_cmd_buffer(cmd_buffer);
3408 if (result != VK_SUCCESS)
3409 return result;
3410 }
3411
3412 return VK_SUCCESS;
3413 }
3414
3415 void radv_TrimCommandPool(
3416 VkDevice device,
3417 VkCommandPool commandPool,
3418 VkCommandPoolTrimFlags flags)
3419 {
3420 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3421
3422 if (!pool)
3423 return;
3424
3425 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3426 &pool->free_cmd_buffers, pool_link) {
3427 radv_cmd_buffer_destroy(cmd_buffer);
3428 }
3429 }
3430
3431 static uint32_t
3432 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
3433 {
3434 struct radv_cmd_state *state = &cmd_buffer->state;
3435 uint32_t subpass_id = state->subpass - state->pass->subpasses;
3436
3437 /* The id of this subpass shouldn't exceed the number of subpasses in
3438 * this render pass minus 1.
3439 */
3440 assert(subpass_id < state->pass->subpass_count);
3441 return subpass_id;
3442 }
3443
3444 static void
3445 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
3446 uint32_t subpass_id)
3447 {
3448 struct radv_cmd_state *state = &cmd_buffer->state;
3449 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
3450
3451 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3452 cmd_buffer->cs, 4096);
3453
3454 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
3455
3456 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
3457 const uint32_t a = subpass->attachments[i].attachment;
3458 if (a == VK_ATTACHMENT_UNUSED)
3459 continue;
3460
3461 radv_handle_subpass_image_transition(cmd_buffer,
3462 subpass->attachments[i]);
3463 }
3464
3465 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3466 radv_cmd_buffer_clear_subpass(cmd_buffer);
3467
3468 assert(cmd_buffer->cs->cdw <= cdw_max);
3469 }
3470
3471 static void
3472 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
3473 {
3474 struct radv_cmd_state *state = &cmd_buffer->state;
3475 const struct radv_subpass *subpass = state->subpass;
3476 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
3477
3478 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3479
3480 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
3481 const uint32_t a = subpass->attachments[i].attachment;
3482 if (a == VK_ATTACHMENT_UNUSED)
3483 continue;
3484
3485 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
3486 continue;
3487
3488 VkImageLayout layout = state->pass->attachments[a].final_layout;
3489 radv_handle_subpass_image_transition(cmd_buffer,
3490 (struct radv_subpass_attachment){a, layout});
3491 }
3492 }
3493
3494 void radv_CmdBeginRenderPass(
3495 VkCommandBuffer commandBuffer,
3496 const VkRenderPassBeginInfo* pRenderPassBegin,
3497 VkSubpassContents contents)
3498 {
3499 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3500 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3501 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3502 VkResult result;
3503
3504 cmd_buffer->state.framebuffer = framebuffer;
3505 cmd_buffer->state.pass = pass;
3506 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3507
3508 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3509 if (result != VK_SUCCESS)
3510 return;
3511
3512 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
3513 }
3514
3515 void radv_CmdBeginRenderPass2KHR(
3516 VkCommandBuffer commandBuffer,
3517 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
3518 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
3519 {
3520 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
3521 pSubpassBeginInfo->contents);
3522 }
3523
3524 void radv_CmdNextSubpass(
3525 VkCommandBuffer commandBuffer,
3526 VkSubpassContents contents)
3527 {
3528 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3529
3530 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
3531 radv_cmd_buffer_end_subpass(cmd_buffer);
3532 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
3533 }
3534
3535 void radv_CmdNextSubpass2KHR(
3536 VkCommandBuffer commandBuffer,
3537 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
3538 const VkSubpassEndInfoKHR* pSubpassEndInfo)
3539 {
3540 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
3541 }
3542
3543 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3544 {
3545 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3546 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3547 if (!radv_get_shader(pipeline, stage))
3548 continue;
3549
3550 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3551 if (loc->sgpr_idx == -1)
3552 continue;
3553 uint32_t base_reg = pipeline->user_data_0[stage];
3554 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3555
3556 }
3557 if (pipeline->gs_copy_shader) {
3558 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3559 if (loc->sgpr_idx != -1) {
3560 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3561 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3562 }
3563 }
3564 }
3565
3566 static void
3567 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3568 uint32_t vertex_count,
3569 bool use_opaque)
3570 {
3571 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3572 radeon_emit(cmd_buffer->cs, vertex_count);
3573 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3574 S_0287F0_USE_OPAQUE(use_opaque));
3575 }
3576
3577 static void
3578 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3579 uint64_t index_va,
3580 uint32_t index_count)
3581 {
3582 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
3583 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3584 radeon_emit(cmd_buffer->cs, index_va);
3585 radeon_emit(cmd_buffer->cs, index_va >> 32);
3586 radeon_emit(cmd_buffer->cs, index_count);
3587 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3588 }
3589
3590 static void
3591 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3592 bool indexed,
3593 uint32_t draw_count,
3594 uint64_t count_va,
3595 uint32_t stride)
3596 {
3597 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3598 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3599 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3600 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
3601 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3602 bool predicating = cmd_buffer->state.predicating;
3603 assert(base_reg);
3604
3605 /* just reset draw state for vertex data */
3606 cmd_buffer->state.last_first_instance = -1;
3607 cmd_buffer->state.last_num_instances = -1;
3608 cmd_buffer->state.last_vertex_offset = -1;
3609
3610 if (draw_count == 1 && !count_va && !draw_id_enable) {
3611 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3612 PKT3_DRAW_INDIRECT, 3, predicating));
3613 radeon_emit(cs, 0);
3614 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3615 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3616 radeon_emit(cs, di_src_sel);
3617 } else {
3618 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3619 PKT3_DRAW_INDIRECT_MULTI,
3620 8, predicating));
3621 radeon_emit(cs, 0);
3622 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3623 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3624 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3625 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3626 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3627 radeon_emit(cs, draw_count); /* count */
3628 radeon_emit(cs, count_va); /* count_addr */
3629 radeon_emit(cs, count_va >> 32);
3630 radeon_emit(cs, stride); /* stride */
3631 radeon_emit(cs, di_src_sel);
3632 }
3633 }
3634
3635 static void
3636 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3637 const struct radv_draw_info *info)
3638 {
3639 struct radv_cmd_state *state = &cmd_buffer->state;
3640 struct radeon_winsys *ws = cmd_buffer->device->ws;
3641 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3642
3643 if (info->indirect) {
3644 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3645 uint64_t count_va = 0;
3646
3647 va += info->indirect->offset + info->indirect_offset;
3648
3649 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3650
3651 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3652 radeon_emit(cs, 1);
3653 radeon_emit(cs, va);
3654 radeon_emit(cs, va >> 32);
3655
3656 if (info->count_buffer) {
3657 count_va = radv_buffer_get_va(info->count_buffer->bo);
3658 count_va += info->count_buffer->offset +
3659 info->count_buffer_offset;
3660
3661 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
3662 }
3663
3664 if (!state->subpass->view_mask) {
3665 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3666 info->indexed,
3667 info->count,
3668 count_va,
3669 info->stride);
3670 } else {
3671 unsigned i;
3672 for_each_bit(i, state->subpass->view_mask) {
3673 radv_emit_view_index(cmd_buffer, i);
3674
3675 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3676 info->indexed,
3677 info->count,
3678 count_va,
3679 info->stride);
3680 }
3681 }
3682 } else {
3683 assert(state->pipeline->graphics.vtx_base_sgpr);
3684
3685 if (info->vertex_offset != state->last_vertex_offset ||
3686 info->first_instance != state->last_first_instance) {
3687 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3688 state->pipeline->graphics.vtx_emit_num);
3689
3690 radeon_emit(cs, info->vertex_offset);
3691 radeon_emit(cs, info->first_instance);
3692 if (state->pipeline->graphics.vtx_emit_num == 3)
3693 radeon_emit(cs, 0);
3694 state->last_first_instance = info->first_instance;
3695 state->last_vertex_offset = info->vertex_offset;
3696 }
3697
3698 if (state->last_num_instances != info->instance_count) {
3699 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3700 radeon_emit(cs, info->instance_count);
3701 state->last_num_instances = info->instance_count;
3702 }
3703
3704 if (info->indexed) {
3705 int index_size = state->index_type ? 4 : 2;
3706 uint64_t index_va;
3707
3708 index_va = state->index_va;
3709 index_va += info->first_index * index_size;
3710
3711 if (!state->subpass->view_mask) {
3712 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3713 index_va,
3714 info->count);
3715 } else {
3716 unsigned i;
3717 for_each_bit(i, state->subpass->view_mask) {
3718 radv_emit_view_index(cmd_buffer, i);
3719
3720 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3721 index_va,
3722 info->count);
3723 }
3724 }
3725 } else {
3726 if (!state->subpass->view_mask) {
3727 radv_cs_emit_draw_packet(cmd_buffer,
3728 info->count,
3729 !!info->strmout_buffer);
3730 } else {
3731 unsigned i;
3732 for_each_bit(i, state->subpass->view_mask) {
3733 radv_emit_view_index(cmd_buffer, i);
3734
3735 radv_cs_emit_draw_packet(cmd_buffer,
3736 info->count,
3737 !!info->strmout_buffer);
3738 }
3739 }
3740 }
3741 }
3742 }
3743
3744 /*
3745 * Vega and raven have a bug which triggers if there are multiple context
3746 * register contexts active at the same time with different scissor values.
3747 *
3748 * There are two possible workarounds:
3749 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3750 * there is only ever 1 active set of scissor values at the same time.
3751 *
3752 * 2) Whenever the hardware switches contexts we have to set the scissor
3753 * registers again even if it is a noop. That way the new context gets
3754 * the correct scissor values.
3755 *
3756 * This implements option 2. radv_need_late_scissor_emission needs to
3757 * return true on affected HW if radv_emit_all_graphics_states sets
3758 * any context registers.
3759 */
3760 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
3761 const struct radv_draw_info *info)
3762 {
3763 struct radv_cmd_state *state = &cmd_buffer->state;
3764
3765 if (!cmd_buffer->device->physical_device->has_scissor_bug)
3766 return false;
3767
3768 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
3769 return true;
3770
3771 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
3772
3773 /* Index, vertex and streamout buffers don't change context regs, and
3774 * pipeline is already handled.
3775 */
3776 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
3777 RADV_CMD_DIRTY_VERTEX_BUFFER |
3778 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
3779 RADV_CMD_DIRTY_PIPELINE);
3780
3781 if (cmd_buffer->state.dirty & used_states)
3782 return true;
3783
3784 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
3785 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
3786 return true;
3787
3788 return false;
3789 }
3790
3791 static void
3792 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3793 const struct radv_draw_info *info)
3794 {
3795 bool late_scissor_emission;
3796
3797 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3798 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3799 radv_emit_rbplus_state(cmd_buffer);
3800
3801 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3802 radv_emit_graphics_pipeline(cmd_buffer);
3803
3804 /* This should be before the cmd_buffer->state.dirty is cleared
3805 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
3806 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
3807 late_scissor_emission =
3808 radv_need_late_scissor_emission(cmd_buffer, info);
3809
3810 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3811 radv_emit_framebuffer_state(cmd_buffer);
3812
3813 if (info->indexed) {
3814 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3815 radv_emit_index_buffer(cmd_buffer);
3816 } else {
3817 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3818 * so the state must be re-emitted before the next indexed
3819 * draw.
3820 */
3821 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3822 cmd_buffer->state.last_index_type = -1;
3823 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3824 }
3825 }
3826
3827 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3828
3829 radv_emit_draw_registers(cmd_buffer, info);
3830
3831 if (late_scissor_emission)
3832 radv_emit_scissor(cmd_buffer);
3833 }
3834
3835 static void
3836 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3837 const struct radv_draw_info *info)
3838 {
3839 struct radeon_info *rad_info =
3840 &cmd_buffer->device->physical_device->rad_info;
3841 bool has_prefetch =
3842 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3843 bool pipeline_is_dirty =
3844 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3845 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3846
3847 MAYBE_UNUSED unsigned cdw_max =
3848 radeon_check_space(cmd_buffer->device->ws,
3849 cmd_buffer->cs, 4096);
3850
3851 if (likely(!info->indirect)) {
3852 /* SI-CI treat instance_count==0 as instance_count==1. There is
3853 * no workaround for indirect draws, but we can at least skip
3854 * direct draws.
3855 */
3856 if (unlikely(!info->instance_count))
3857 return;
3858
3859 /* Handle count == 0. */
3860 if (unlikely(!info->count && !info->strmout_buffer))
3861 return;
3862 }
3863
3864 /* Use optimal packet order based on whether we need to sync the
3865 * pipeline.
3866 */
3867 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3868 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3869 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3870 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3871 /* If we have to wait for idle, set all states first, so that
3872 * all SET packets are processed in parallel with previous draw
3873 * calls. Then upload descriptors, set shader pointers, and
3874 * draw, and prefetch at the end. This ensures that the time
3875 * the CUs are idle is very short. (there are only SET_SH
3876 * packets between the wait and the draw)
3877 */
3878 radv_emit_all_graphics_states(cmd_buffer, info);
3879 si_emit_cache_flush(cmd_buffer);
3880 /* <-- CUs are idle here --> */
3881
3882 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3883
3884 radv_emit_draw_packets(cmd_buffer, info);
3885 /* <-- CUs are busy here --> */
3886
3887 /* Start prefetches after the draw has been started. Both will
3888 * run in parallel, but starting the draw first is more
3889 * important.
3890 */
3891 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3892 radv_emit_prefetch_L2(cmd_buffer,
3893 cmd_buffer->state.pipeline, false);
3894 }
3895 } else {
3896 /* If we don't wait for idle, start prefetches first, then set
3897 * states, and draw at the end.
3898 */
3899 si_emit_cache_flush(cmd_buffer);
3900
3901 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3902 /* Only prefetch the vertex shader and VBO descriptors
3903 * in order to start the draw as soon as possible.
3904 */
3905 radv_emit_prefetch_L2(cmd_buffer,
3906 cmd_buffer->state.pipeline, true);
3907 }
3908
3909 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3910
3911 radv_emit_all_graphics_states(cmd_buffer, info);
3912 radv_emit_draw_packets(cmd_buffer, info);
3913
3914 /* Prefetch the remaining shaders after the draw has been
3915 * started.
3916 */
3917 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3918 radv_emit_prefetch_L2(cmd_buffer,
3919 cmd_buffer->state.pipeline, false);
3920 }
3921 }
3922
3923 /* Workaround for a VGT hang when streamout is enabled.
3924 * It must be done after drawing.
3925 */
3926 if (cmd_buffer->state.streamout.streamout_enabled &&
3927 (rad_info->family == CHIP_HAWAII ||
3928 rad_info->family == CHIP_TONGA ||
3929 rad_info->family == CHIP_FIJI)) {
3930 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
3931 }
3932
3933 assert(cmd_buffer->cs->cdw <= cdw_max);
3934 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3935 }
3936
3937 void radv_CmdDraw(
3938 VkCommandBuffer commandBuffer,
3939 uint32_t vertexCount,
3940 uint32_t instanceCount,
3941 uint32_t firstVertex,
3942 uint32_t firstInstance)
3943 {
3944 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3945 struct radv_draw_info info = {};
3946
3947 info.count = vertexCount;
3948 info.instance_count = instanceCount;
3949 info.first_instance = firstInstance;
3950 info.vertex_offset = firstVertex;
3951
3952 radv_draw(cmd_buffer, &info);
3953 }
3954
3955 void radv_CmdDrawIndexed(
3956 VkCommandBuffer commandBuffer,
3957 uint32_t indexCount,
3958 uint32_t instanceCount,
3959 uint32_t firstIndex,
3960 int32_t vertexOffset,
3961 uint32_t firstInstance)
3962 {
3963 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3964 struct radv_draw_info info = {};
3965
3966 info.indexed = true;
3967 info.count = indexCount;
3968 info.instance_count = instanceCount;
3969 info.first_index = firstIndex;
3970 info.vertex_offset = vertexOffset;
3971 info.first_instance = firstInstance;
3972
3973 radv_draw(cmd_buffer, &info);
3974 }
3975
3976 void radv_CmdDrawIndirect(
3977 VkCommandBuffer commandBuffer,
3978 VkBuffer _buffer,
3979 VkDeviceSize offset,
3980 uint32_t drawCount,
3981 uint32_t stride)
3982 {
3983 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3984 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3985 struct radv_draw_info info = {};
3986
3987 info.count = drawCount;
3988 info.indirect = buffer;
3989 info.indirect_offset = offset;
3990 info.stride = stride;
3991
3992 radv_draw(cmd_buffer, &info);
3993 }
3994
3995 void radv_CmdDrawIndexedIndirect(
3996 VkCommandBuffer commandBuffer,
3997 VkBuffer _buffer,
3998 VkDeviceSize offset,
3999 uint32_t drawCount,
4000 uint32_t stride)
4001 {
4002 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4003 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4004 struct radv_draw_info info = {};
4005
4006 info.indexed = true;
4007 info.count = drawCount;
4008 info.indirect = buffer;
4009 info.indirect_offset = offset;
4010 info.stride = stride;
4011
4012 radv_draw(cmd_buffer, &info);
4013 }
4014
4015 void radv_CmdDrawIndirectCountAMD(
4016 VkCommandBuffer commandBuffer,
4017 VkBuffer _buffer,
4018 VkDeviceSize offset,
4019 VkBuffer _countBuffer,
4020 VkDeviceSize countBufferOffset,
4021 uint32_t maxDrawCount,
4022 uint32_t stride)
4023 {
4024 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4025 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4026 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4027 struct radv_draw_info info = {};
4028
4029 info.count = maxDrawCount;
4030 info.indirect = buffer;
4031 info.indirect_offset = offset;
4032 info.count_buffer = count_buffer;
4033 info.count_buffer_offset = countBufferOffset;
4034 info.stride = stride;
4035
4036 radv_draw(cmd_buffer, &info);
4037 }
4038
4039 void radv_CmdDrawIndexedIndirectCountAMD(
4040 VkCommandBuffer commandBuffer,
4041 VkBuffer _buffer,
4042 VkDeviceSize offset,
4043 VkBuffer _countBuffer,
4044 VkDeviceSize countBufferOffset,
4045 uint32_t maxDrawCount,
4046 uint32_t stride)
4047 {
4048 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4049 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4050 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4051 struct radv_draw_info info = {};
4052
4053 info.indexed = true;
4054 info.count = maxDrawCount;
4055 info.indirect = buffer;
4056 info.indirect_offset = offset;
4057 info.count_buffer = count_buffer;
4058 info.count_buffer_offset = countBufferOffset;
4059 info.stride = stride;
4060
4061 radv_draw(cmd_buffer, &info);
4062 }
4063
4064 void radv_CmdDrawIndirectCountKHR(
4065 VkCommandBuffer commandBuffer,
4066 VkBuffer _buffer,
4067 VkDeviceSize offset,
4068 VkBuffer _countBuffer,
4069 VkDeviceSize countBufferOffset,
4070 uint32_t maxDrawCount,
4071 uint32_t stride)
4072 {
4073 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4074 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4075 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4076 struct radv_draw_info info = {};
4077
4078 info.count = maxDrawCount;
4079 info.indirect = buffer;
4080 info.indirect_offset = offset;
4081 info.count_buffer = count_buffer;
4082 info.count_buffer_offset = countBufferOffset;
4083 info.stride = stride;
4084
4085 radv_draw(cmd_buffer, &info);
4086 }
4087
4088 void radv_CmdDrawIndexedIndirectCountKHR(
4089 VkCommandBuffer commandBuffer,
4090 VkBuffer _buffer,
4091 VkDeviceSize offset,
4092 VkBuffer _countBuffer,
4093 VkDeviceSize countBufferOffset,
4094 uint32_t maxDrawCount,
4095 uint32_t stride)
4096 {
4097 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4098 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4099 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4100 struct radv_draw_info info = {};
4101
4102 info.indexed = true;
4103 info.count = maxDrawCount;
4104 info.indirect = buffer;
4105 info.indirect_offset = offset;
4106 info.count_buffer = count_buffer;
4107 info.count_buffer_offset = countBufferOffset;
4108 info.stride = stride;
4109
4110 radv_draw(cmd_buffer, &info);
4111 }
4112
4113 struct radv_dispatch_info {
4114 /**
4115 * Determine the layout of the grid (in block units) to be used.
4116 */
4117 uint32_t blocks[3];
4118
4119 /**
4120 * A starting offset for the grid. If unaligned is set, the offset
4121 * must still be aligned.
4122 */
4123 uint32_t offsets[3];
4124 /**
4125 * Whether it's an unaligned compute dispatch.
4126 */
4127 bool unaligned;
4128
4129 /**
4130 * Indirect compute parameters resource.
4131 */
4132 struct radv_buffer *indirect;
4133 uint64_t indirect_offset;
4134 };
4135
4136 static void
4137 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
4138 const struct radv_dispatch_info *info)
4139 {
4140 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4141 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4142 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
4143 struct radeon_winsys *ws = cmd_buffer->device->ws;
4144 bool predicating = cmd_buffer->state.predicating;
4145 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4146 struct radv_userdata_info *loc;
4147
4148 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
4149 AC_UD_CS_GRID_SIZE);
4150
4151 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
4152
4153 if (info->indirect) {
4154 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4155
4156 va += info->indirect->offset + info->indirect_offset;
4157
4158 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4159
4160 if (loc->sgpr_idx != -1) {
4161 for (unsigned i = 0; i < 3; ++i) {
4162 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4163 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4164 COPY_DATA_DST_SEL(COPY_DATA_REG));
4165 radeon_emit(cs, (va + 4 * i));
4166 radeon_emit(cs, (va + 4 * i) >> 32);
4167 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
4168 + loc->sgpr_idx * 4) >> 2) + i);
4169 radeon_emit(cs, 0);
4170 }
4171 }
4172
4173 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
4174 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
4175 PKT3_SHADER_TYPE_S(1));
4176 radeon_emit(cs, va);
4177 radeon_emit(cs, va >> 32);
4178 radeon_emit(cs, dispatch_initiator);
4179 } else {
4180 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
4181 PKT3_SHADER_TYPE_S(1));
4182 radeon_emit(cs, 1);
4183 radeon_emit(cs, va);
4184 radeon_emit(cs, va >> 32);
4185
4186 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
4187 PKT3_SHADER_TYPE_S(1));
4188 radeon_emit(cs, 0);
4189 radeon_emit(cs, dispatch_initiator);
4190 }
4191 } else {
4192 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
4193 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
4194
4195 if (info->unaligned) {
4196 unsigned *cs_block_size = compute_shader->info.cs.block_size;
4197 unsigned remainder[3];
4198
4199 /* If aligned, these should be an entire block size,
4200 * not 0.
4201 */
4202 remainder[0] = blocks[0] + cs_block_size[0] -
4203 align_u32_npot(blocks[0], cs_block_size[0]);
4204 remainder[1] = blocks[1] + cs_block_size[1] -
4205 align_u32_npot(blocks[1], cs_block_size[1]);
4206 remainder[2] = blocks[2] + cs_block_size[2] -
4207 align_u32_npot(blocks[2], cs_block_size[2]);
4208
4209 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
4210 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
4211 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
4212
4213 for(unsigned i = 0; i < 3; ++i) {
4214 assert(offsets[i] % cs_block_size[i] == 0);
4215 offsets[i] /= cs_block_size[i];
4216 }
4217
4218 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4219 radeon_emit(cs,
4220 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
4221 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4222 radeon_emit(cs,
4223 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4224 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4225 radeon_emit(cs,
4226 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4227 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4228
4229 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4230 }
4231
4232 if (loc->sgpr_idx != -1) {
4233 assert(loc->num_sgprs == 3);
4234
4235 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4236 loc->sgpr_idx * 4, 3);
4237 radeon_emit(cs, blocks[0]);
4238 radeon_emit(cs, blocks[1]);
4239 radeon_emit(cs, blocks[2]);
4240 }
4241
4242 if (offsets[0] || offsets[1] || offsets[2]) {
4243 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4244 radeon_emit(cs, offsets[0]);
4245 radeon_emit(cs, offsets[1]);
4246 radeon_emit(cs, offsets[2]);
4247
4248 /* The blocks in the packet are not counts but end values. */
4249 for (unsigned i = 0; i < 3; ++i)
4250 blocks[i] += offsets[i];
4251 } else {
4252 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4253 }
4254
4255 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4256 PKT3_SHADER_TYPE_S(1));
4257 radeon_emit(cs, blocks[0]);
4258 radeon_emit(cs, blocks[1]);
4259 radeon_emit(cs, blocks[2]);
4260 radeon_emit(cs, dispatch_initiator);
4261 }
4262
4263 assert(cmd_buffer->cs->cdw <= cdw_max);
4264 }
4265
4266 static void
4267 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4268 {
4269 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4270 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4271 }
4272
4273 static void
4274 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4275 const struct radv_dispatch_info *info)
4276 {
4277 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4278 bool has_prefetch =
4279 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
4280 bool pipeline_is_dirty = pipeline &&
4281 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4282
4283 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4284 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4285 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4286 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4287 /* If we have to wait for idle, set all states first, so that
4288 * all SET packets are processed in parallel with previous draw
4289 * calls. Then upload descriptors, set shader pointers, and
4290 * dispatch, and prefetch at the end. This ensures that the
4291 * time the CUs are idle is very short. (there are only SET_SH
4292 * packets between the wait and the draw)
4293 */
4294 radv_emit_compute_pipeline(cmd_buffer);
4295 si_emit_cache_flush(cmd_buffer);
4296 /* <-- CUs are idle here --> */
4297
4298 radv_upload_compute_shader_descriptors(cmd_buffer);
4299
4300 radv_emit_dispatch_packets(cmd_buffer, info);
4301 /* <-- CUs are busy here --> */
4302
4303 /* Start prefetches after the dispatch has been started. Both
4304 * will run in parallel, but starting the dispatch first is
4305 * more important.
4306 */
4307 if (has_prefetch && pipeline_is_dirty) {
4308 radv_emit_shader_prefetch(cmd_buffer,
4309 pipeline->shaders[MESA_SHADER_COMPUTE]);
4310 }
4311 } else {
4312 /* If we don't wait for idle, start prefetches first, then set
4313 * states, and dispatch at the end.
4314 */
4315 si_emit_cache_flush(cmd_buffer);
4316
4317 if (has_prefetch && pipeline_is_dirty) {
4318 radv_emit_shader_prefetch(cmd_buffer,
4319 pipeline->shaders[MESA_SHADER_COMPUTE]);
4320 }
4321
4322 radv_upload_compute_shader_descriptors(cmd_buffer);
4323
4324 radv_emit_compute_pipeline(cmd_buffer);
4325 radv_emit_dispatch_packets(cmd_buffer, info);
4326 }
4327
4328 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
4329 }
4330
4331 void radv_CmdDispatchBase(
4332 VkCommandBuffer commandBuffer,
4333 uint32_t base_x,
4334 uint32_t base_y,
4335 uint32_t base_z,
4336 uint32_t x,
4337 uint32_t y,
4338 uint32_t z)
4339 {
4340 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4341 struct radv_dispatch_info info = {};
4342
4343 info.blocks[0] = x;
4344 info.blocks[1] = y;
4345 info.blocks[2] = z;
4346
4347 info.offsets[0] = base_x;
4348 info.offsets[1] = base_y;
4349 info.offsets[2] = base_z;
4350 radv_dispatch(cmd_buffer, &info);
4351 }
4352
4353 void radv_CmdDispatch(
4354 VkCommandBuffer commandBuffer,
4355 uint32_t x,
4356 uint32_t y,
4357 uint32_t z)
4358 {
4359 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4360 }
4361
4362 void radv_CmdDispatchIndirect(
4363 VkCommandBuffer commandBuffer,
4364 VkBuffer _buffer,
4365 VkDeviceSize offset)
4366 {
4367 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4368 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4369 struct radv_dispatch_info info = {};
4370
4371 info.indirect = buffer;
4372 info.indirect_offset = offset;
4373
4374 radv_dispatch(cmd_buffer, &info);
4375 }
4376
4377 void radv_unaligned_dispatch(
4378 struct radv_cmd_buffer *cmd_buffer,
4379 uint32_t x,
4380 uint32_t y,
4381 uint32_t z)
4382 {
4383 struct radv_dispatch_info info = {};
4384
4385 info.blocks[0] = x;
4386 info.blocks[1] = y;
4387 info.blocks[2] = z;
4388 info.unaligned = 1;
4389
4390 radv_dispatch(cmd_buffer, &info);
4391 }
4392
4393 void radv_CmdEndRenderPass(
4394 VkCommandBuffer commandBuffer)
4395 {
4396 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4397
4398 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
4399
4400 radv_cmd_buffer_end_subpass(cmd_buffer);
4401
4402 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4403
4404 cmd_buffer->state.pass = NULL;
4405 cmd_buffer->state.subpass = NULL;
4406 cmd_buffer->state.attachments = NULL;
4407 cmd_buffer->state.framebuffer = NULL;
4408 }
4409
4410 void radv_CmdEndRenderPass2KHR(
4411 VkCommandBuffer commandBuffer,
4412 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4413 {
4414 radv_CmdEndRenderPass(commandBuffer);
4415 }
4416
4417 /*
4418 * For HTILE we have the following interesting clear words:
4419 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4420 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4421 * 0xfffffff0: Clear depth to 1.0
4422 * 0x00000000: Clear depth to 0.0
4423 */
4424 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
4425 struct radv_image *image,
4426 const VkImageSubresourceRange *range,
4427 uint32_t clear_word)
4428 {
4429 assert(range->baseMipLevel == 0);
4430 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
4431 unsigned layer_count = radv_get_layerCount(image, range);
4432 uint64_t size = image->surface.htile_slice_size * layer_count;
4433 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
4434 uint64_t offset = image->offset + image->htile_offset +
4435 image->surface.htile_slice_size * range->baseArrayLayer;
4436 struct radv_cmd_state *state = &cmd_buffer->state;
4437 VkClearDepthStencilValue value = {};
4438
4439 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4440 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4441
4442 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
4443 size, clear_word);
4444
4445 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4446
4447 if (vk_format_is_stencil(image->vk_format))
4448 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4449
4450 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4451
4452 if (radv_image_is_tc_compat_htile(image)) {
4453 /* Initialize the TC-compat metada value to 0 because by
4454 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
4455 * need have to conditionally update its value when performing
4456 * a fast depth clear.
4457 */
4458 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, 0);
4459 }
4460 }
4461
4462 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4463 struct radv_image *image,
4464 VkImageLayout src_layout,
4465 VkImageLayout dst_layout,
4466 unsigned src_queue_mask,
4467 unsigned dst_queue_mask,
4468 const VkImageSubresourceRange *range)
4469 {
4470 if (!radv_image_has_htile(image))
4471 return;
4472
4473 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
4474 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
4475 /* TODO: merge with the clear if applicable */
4476 radv_initialize_htile(cmd_buffer, image, range, 0);
4477 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4478 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4479 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4480 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4481 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4482 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4483 VkImageSubresourceRange local_range = *range;
4484 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4485 local_range.baseMipLevel = 0;
4486 local_range.levelCount = 1;
4487
4488 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4489 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4490
4491 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
4492
4493 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4494 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4495 }
4496 }
4497
4498 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4499 struct radv_image *image, uint32_t value)
4500 {
4501 struct radv_cmd_state *state = &cmd_buffer->state;
4502
4503 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4504 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4505
4506 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
4507
4508 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4509 }
4510
4511 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
4512 struct radv_image *image)
4513 {
4514 struct radv_cmd_state *state = &cmd_buffer->state;
4515 static const uint32_t fmask_clear_values[4] = {
4516 0x00000000,
4517 0x02020202,
4518 0xE4E4E4E4,
4519 0x76543210
4520 };
4521 uint32_t log2_samples = util_logbase2(image->info.samples);
4522 uint32_t value = fmask_clear_values[log2_samples];
4523
4524 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4525 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4526
4527 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, value);
4528
4529 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4530 }
4531
4532 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4533 struct radv_image *image, uint32_t value)
4534 {
4535 struct radv_cmd_state *state = &cmd_buffer->state;
4536
4537 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4538 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4539
4540 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
4541
4542 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4543 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4544 }
4545
4546 /**
4547 * Initialize DCC/FMASK/CMASK metadata for a color image.
4548 */
4549 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4550 struct radv_image *image,
4551 VkImageLayout src_layout,
4552 VkImageLayout dst_layout,
4553 unsigned src_queue_mask,
4554 unsigned dst_queue_mask)
4555 {
4556 if (radv_image_has_cmask(image)) {
4557 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4558
4559 /* TODO: clarify this. */
4560 if (radv_image_has_fmask(image)) {
4561 value = 0xccccccccu;
4562 }
4563
4564 radv_initialise_cmask(cmd_buffer, image, value);
4565 }
4566
4567 if (radv_image_has_fmask(image)) {
4568 radv_initialize_fmask(cmd_buffer, image);
4569 }
4570
4571 if (radv_image_has_dcc(image)) {
4572 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4573 bool need_decompress_pass = false;
4574
4575 if (radv_layout_dcc_compressed(image, dst_layout,
4576 dst_queue_mask)) {
4577 value = 0x20202020u;
4578 need_decompress_pass = true;
4579 }
4580
4581 radv_initialize_dcc(cmd_buffer, image, value);
4582
4583 radv_update_fce_metadata(cmd_buffer, image,
4584 need_decompress_pass);
4585 }
4586
4587 if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
4588 uint32_t color_values[2] = {};
4589 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
4590 }
4591 }
4592
4593 /**
4594 * Handle color image transitions for DCC/FMASK/CMASK.
4595 */
4596 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4597 struct radv_image *image,
4598 VkImageLayout src_layout,
4599 VkImageLayout dst_layout,
4600 unsigned src_queue_mask,
4601 unsigned dst_queue_mask,
4602 const VkImageSubresourceRange *range)
4603 {
4604 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4605 radv_init_color_image_metadata(cmd_buffer, image,
4606 src_layout, dst_layout,
4607 src_queue_mask, dst_queue_mask);
4608 return;
4609 }
4610
4611 if (radv_image_has_dcc(image)) {
4612 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4613 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4614 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4615 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4616 radv_decompress_dcc(cmd_buffer, image, range);
4617 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4618 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4619 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4620 }
4621 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
4622 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4623 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4624 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4625 }
4626
4627 if (radv_image_has_fmask(image)) {
4628 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
4629 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
4630 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
4631 }
4632 }
4633 }
4634 }
4635
4636 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4637 struct radv_image *image,
4638 VkImageLayout src_layout,
4639 VkImageLayout dst_layout,
4640 uint32_t src_family,
4641 uint32_t dst_family,
4642 const VkImageSubresourceRange *range)
4643 {
4644 if (image->exclusive && src_family != dst_family) {
4645 /* This is an acquire or a release operation and there will be
4646 * a corresponding release/acquire. Do the transition in the
4647 * most flexible queue. */
4648
4649 assert(src_family == cmd_buffer->queue_family_index ||
4650 dst_family == cmd_buffer->queue_family_index);
4651
4652 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4653 return;
4654
4655 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4656 (src_family == RADV_QUEUE_GENERAL ||
4657 dst_family == RADV_QUEUE_GENERAL))
4658 return;
4659 }
4660
4661 if (src_layout == dst_layout)
4662 return;
4663
4664 unsigned src_queue_mask =
4665 radv_image_queue_family_mask(image, src_family,
4666 cmd_buffer->queue_family_index);
4667 unsigned dst_queue_mask =
4668 radv_image_queue_family_mask(image, dst_family,
4669 cmd_buffer->queue_family_index);
4670
4671 if (vk_format_is_depth(image->vk_format)) {
4672 radv_handle_depth_image_transition(cmd_buffer, image,
4673 src_layout, dst_layout,
4674 src_queue_mask, dst_queue_mask,
4675 range);
4676 } else {
4677 radv_handle_color_image_transition(cmd_buffer, image,
4678 src_layout, dst_layout,
4679 src_queue_mask, dst_queue_mask,
4680 range);
4681 }
4682 }
4683
4684 struct radv_barrier_info {
4685 uint32_t eventCount;
4686 const VkEvent *pEvents;
4687 VkPipelineStageFlags srcStageMask;
4688 VkPipelineStageFlags dstStageMask;
4689 };
4690
4691 static void
4692 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
4693 uint32_t memoryBarrierCount,
4694 const VkMemoryBarrier *pMemoryBarriers,
4695 uint32_t bufferMemoryBarrierCount,
4696 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4697 uint32_t imageMemoryBarrierCount,
4698 const VkImageMemoryBarrier *pImageMemoryBarriers,
4699 const struct radv_barrier_info *info)
4700 {
4701 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4702 enum radv_cmd_flush_bits src_flush_bits = 0;
4703 enum radv_cmd_flush_bits dst_flush_bits = 0;
4704
4705 for (unsigned i = 0; i < info->eventCount; ++i) {
4706 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
4707 uint64_t va = radv_buffer_get_va(event->bo);
4708
4709 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4710
4711 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4712
4713 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
4714 assert(cmd_buffer->cs->cdw <= cdw_max);
4715 }
4716
4717 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4718 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
4719 NULL);
4720 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4721 NULL);
4722 }
4723
4724 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4725 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
4726 NULL);
4727 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4728 NULL);
4729 }
4730
4731 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4732 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4733
4734 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
4735 image);
4736 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4737 image);
4738 }
4739
4740 /* The Vulkan spec 1.1.98 says:
4741 *
4742 * "An execution dependency with only
4743 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
4744 * will only prevent that stage from executing in subsequently
4745 * submitted commands. As this stage does not perform any actual
4746 * execution, this is not observable - in effect, it does not delay
4747 * processing of subsequent commands. Similarly an execution dependency
4748 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
4749 * will effectively not wait for any prior commands to complete."
4750 */
4751 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
4752 radv_stage_flush(cmd_buffer, info->srcStageMask);
4753 cmd_buffer->state.flush_bits |= src_flush_bits;
4754
4755 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4756 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4757 radv_handle_image_transition(cmd_buffer, image,
4758 pImageMemoryBarriers[i].oldLayout,
4759 pImageMemoryBarriers[i].newLayout,
4760 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4761 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4762 &pImageMemoryBarriers[i].subresourceRange);
4763 }
4764
4765 /* Make sure CP DMA is idle because the driver might have performed a
4766 * DMA operation for copying or filling buffers/images.
4767 */
4768 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
4769 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
4770 si_cp_dma_wait_for_idle(cmd_buffer);
4771
4772 cmd_buffer->state.flush_bits |= dst_flush_bits;
4773 }
4774
4775 void radv_CmdPipelineBarrier(
4776 VkCommandBuffer commandBuffer,
4777 VkPipelineStageFlags srcStageMask,
4778 VkPipelineStageFlags destStageMask,
4779 VkBool32 byRegion,
4780 uint32_t memoryBarrierCount,
4781 const VkMemoryBarrier* pMemoryBarriers,
4782 uint32_t bufferMemoryBarrierCount,
4783 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4784 uint32_t imageMemoryBarrierCount,
4785 const VkImageMemoryBarrier* pImageMemoryBarriers)
4786 {
4787 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4788 struct radv_barrier_info info;
4789
4790 info.eventCount = 0;
4791 info.pEvents = NULL;
4792 info.srcStageMask = srcStageMask;
4793 info.dstStageMask = destStageMask;
4794
4795 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4796 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4797 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4798 }
4799
4800
4801 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4802 struct radv_event *event,
4803 VkPipelineStageFlags stageMask,
4804 unsigned value)
4805 {
4806 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4807 uint64_t va = radv_buffer_get_va(event->bo);
4808
4809 si_emit_cache_flush(cmd_buffer);
4810
4811 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4812
4813 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4814
4815 /* Flags that only require a top-of-pipe event. */
4816 VkPipelineStageFlags top_of_pipe_flags =
4817 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
4818
4819 /* Flags that only require a post-index-fetch event. */
4820 VkPipelineStageFlags post_index_fetch_flags =
4821 top_of_pipe_flags |
4822 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
4823 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
4824
4825 /* Make sure CP DMA is idle because the driver might have performed a
4826 * DMA operation for copying or filling buffers/images.
4827 */
4828 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
4829 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
4830 si_cp_dma_wait_for_idle(cmd_buffer);
4831
4832 /* TODO: Emit EOS events for syncing PS/CS stages. */
4833
4834 if (!(stageMask & ~top_of_pipe_flags)) {
4835 /* Just need to sync the PFP engine. */
4836 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4837 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
4838 S_370_WR_CONFIRM(1) |
4839 S_370_ENGINE_SEL(V_370_PFP));
4840 radeon_emit(cs, va);
4841 radeon_emit(cs, va >> 32);
4842 radeon_emit(cs, value);
4843 } else if (!(stageMask & ~post_index_fetch_flags)) {
4844 /* Sync ME because PFP reads index and indirect buffers. */
4845 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4846 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
4847 S_370_WR_CONFIRM(1) |
4848 S_370_ENGINE_SEL(V_370_ME));
4849 radeon_emit(cs, va);
4850 radeon_emit(cs, va >> 32);
4851 radeon_emit(cs, value);
4852 } else {
4853 /* Otherwise, sync all prior GPU work using an EOP event. */
4854 si_cs_emit_write_event_eop(cs,
4855 cmd_buffer->device->physical_device->rad_info.chip_class,
4856 radv_cmd_buffer_uses_mec(cmd_buffer),
4857 V_028A90_BOTTOM_OF_PIPE_TS, 0,
4858 EOP_DATA_SEL_VALUE_32BIT, va, value,
4859 cmd_buffer->gfx9_eop_bug_va);
4860 }
4861
4862 assert(cmd_buffer->cs->cdw <= cdw_max);
4863 }
4864
4865 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4866 VkEvent _event,
4867 VkPipelineStageFlags stageMask)
4868 {
4869 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4870 RADV_FROM_HANDLE(radv_event, event, _event);
4871
4872 write_event(cmd_buffer, event, stageMask, 1);
4873 }
4874
4875 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4876 VkEvent _event,
4877 VkPipelineStageFlags stageMask)
4878 {
4879 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4880 RADV_FROM_HANDLE(radv_event, event, _event);
4881
4882 write_event(cmd_buffer, event, stageMask, 0);
4883 }
4884
4885 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4886 uint32_t eventCount,
4887 const VkEvent* pEvents,
4888 VkPipelineStageFlags srcStageMask,
4889 VkPipelineStageFlags dstStageMask,
4890 uint32_t memoryBarrierCount,
4891 const VkMemoryBarrier* pMemoryBarriers,
4892 uint32_t bufferMemoryBarrierCount,
4893 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4894 uint32_t imageMemoryBarrierCount,
4895 const VkImageMemoryBarrier* pImageMemoryBarriers)
4896 {
4897 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4898 struct radv_barrier_info info;
4899
4900 info.eventCount = eventCount;
4901 info.pEvents = pEvents;
4902 info.srcStageMask = 0;
4903
4904 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4905 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4906 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4907 }
4908
4909
4910 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4911 uint32_t deviceMask)
4912 {
4913 /* No-op */
4914 }
4915
4916 /* VK_EXT_conditional_rendering */
4917 void radv_CmdBeginConditionalRenderingEXT(
4918 VkCommandBuffer commandBuffer,
4919 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
4920 {
4921 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4922 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
4923 bool draw_visible = true;
4924 uint64_t va;
4925
4926 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
4927
4928 /* By default, if the 32-bit value at offset in buffer memory is zero,
4929 * then the rendering commands are discarded, otherwise they are
4930 * executed as normal. If the inverted flag is set, all commands are
4931 * discarded if the value is non zero.
4932 */
4933 if (pConditionalRenderingBegin->flags &
4934 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
4935 draw_visible = false;
4936 }
4937
4938 si_emit_cache_flush(cmd_buffer);
4939
4940 /* Enable predication for this command buffer. */
4941 si_emit_set_predication_state(cmd_buffer, draw_visible, va);
4942 cmd_buffer->state.predicating = true;
4943
4944 /* Store conditional rendering user info. */
4945 cmd_buffer->state.predication_type = draw_visible;
4946 cmd_buffer->state.predication_va = va;
4947 }
4948
4949 void radv_CmdEndConditionalRenderingEXT(
4950 VkCommandBuffer commandBuffer)
4951 {
4952 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4953
4954 /* Disable predication for this command buffer. */
4955 si_emit_set_predication_state(cmd_buffer, false, 0);
4956 cmd_buffer->state.predicating = false;
4957
4958 /* Reset conditional rendering user info. */
4959 cmd_buffer->state.predication_type = -1;
4960 cmd_buffer->state.predication_va = 0;
4961 }
4962
4963 /* VK_EXT_transform_feedback */
4964 void radv_CmdBindTransformFeedbackBuffersEXT(
4965 VkCommandBuffer commandBuffer,
4966 uint32_t firstBinding,
4967 uint32_t bindingCount,
4968 const VkBuffer* pBuffers,
4969 const VkDeviceSize* pOffsets,
4970 const VkDeviceSize* pSizes)
4971 {
4972 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4973 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
4974 uint8_t enabled_mask = 0;
4975
4976 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
4977 for (uint32_t i = 0; i < bindingCount; i++) {
4978 uint32_t idx = firstBinding + i;
4979
4980 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
4981 sb[idx].offset = pOffsets[i];
4982 sb[idx].size = pSizes[i];
4983
4984 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
4985 sb[idx].buffer->bo);
4986
4987 enabled_mask |= 1 << idx;
4988 }
4989
4990 cmd_buffer->state.streamout.enabled_mask = enabled_mask;
4991
4992 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
4993 }
4994
4995 static void
4996 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
4997 {
4998 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4999 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5000
5001 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
5002 radeon_emit(cs,
5003 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
5004 S_028B94_RAST_STREAM(0) |
5005 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
5006 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
5007 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
5008 radeon_emit(cs, so->hw_enabled_mask &
5009 so->enabled_stream_buffers_mask);
5010
5011 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5012 }
5013
5014 static void
5015 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
5016 {
5017 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5018 bool old_streamout_enabled = so->streamout_enabled;
5019 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
5020
5021 so->streamout_enabled = enable;
5022
5023 so->hw_enabled_mask = so->enabled_mask |
5024 (so->enabled_mask << 4) |
5025 (so->enabled_mask << 8) |
5026 (so->enabled_mask << 12);
5027
5028 if ((old_streamout_enabled != so->streamout_enabled) ||
5029 (old_hw_enabled_mask != so->hw_enabled_mask))
5030 radv_emit_streamout_enable(cmd_buffer);
5031 }
5032
5033 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
5034 {
5035 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5036 unsigned reg_strmout_cntl;
5037
5038 /* The register is at different places on different ASICs. */
5039 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
5040 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
5041 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
5042 } else {
5043 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
5044 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
5045 }
5046
5047 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
5048 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
5049
5050 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
5051 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
5052 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
5053 radeon_emit(cs, 0);
5054 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5055 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5056 radeon_emit(cs, 4); /* poll interval */
5057 }
5058
5059 void radv_CmdBeginTransformFeedbackEXT(
5060 VkCommandBuffer commandBuffer,
5061 uint32_t firstCounterBuffer,
5062 uint32_t counterBufferCount,
5063 const VkBuffer* pCounterBuffers,
5064 const VkDeviceSize* pCounterBufferOffsets)
5065 {
5066 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5067 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5068 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5069 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5070 uint32_t i;
5071
5072 radv_flush_vgt_streamout(cmd_buffer);
5073
5074 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5075 for_each_bit(i, so->enabled_mask) {
5076 int32_t counter_buffer_idx = i - firstCounterBuffer;
5077 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5078 counter_buffer_idx = -1;
5079
5080 /* SI binds streamout buffers as shader resources.
5081 * VGT only counts primitives and tells the shader through
5082 * SGPRs what to do.
5083 */
5084 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
5085 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
5086 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
5087
5088 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5089
5090 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5091 /* The array of counter buffers is optional. */
5092 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5093 uint64_t va = radv_buffer_get_va(buffer->bo);
5094
5095 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5096
5097 /* Append */
5098 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5099 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5100 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5101 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
5102 radeon_emit(cs, 0); /* unused */
5103 radeon_emit(cs, 0); /* unused */
5104 radeon_emit(cs, va); /* src address lo */
5105 radeon_emit(cs, va >> 32); /* src address hi */
5106
5107 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5108 } else {
5109 /* Start from the beginning. */
5110 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5111 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5112 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5113 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
5114 radeon_emit(cs, 0); /* unused */
5115 radeon_emit(cs, 0); /* unused */
5116 radeon_emit(cs, 0); /* unused */
5117 radeon_emit(cs, 0); /* unused */
5118 }
5119 }
5120
5121 radv_set_streamout_enable(cmd_buffer, true);
5122 }
5123
5124 void radv_CmdEndTransformFeedbackEXT(
5125 VkCommandBuffer commandBuffer,
5126 uint32_t firstCounterBuffer,
5127 uint32_t counterBufferCount,
5128 const VkBuffer* pCounterBuffers,
5129 const VkDeviceSize* pCounterBufferOffsets)
5130 {
5131 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5132 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5133 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5134 uint32_t i;
5135
5136 radv_flush_vgt_streamout(cmd_buffer);
5137
5138 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5139 for_each_bit(i, so->enabled_mask) {
5140 int32_t counter_buffer_idx = i - firstCounterBuffer;
5141 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5142 counter_buffer_idx = -1;
5143
5144 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5145 /* The array of counters buffer is optional. */
5146 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5147 uint64_t va = radv_buffer_get_va(buffer->bo);
5148
5149 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5150
5151 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5152 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5153 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5154 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
5155 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
5156 radeon_emit(cs, va); /* dst address lo */
5157 radeon_emit(cs, va >> 32); /* dst address hi */
5158 radeon_emit(cs, 0); /* unused */
5159 radeon_emit(cs, 0); /* unused */
5160
5161 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5162 }
5163
5164 /* Deactivate transform feedback by zeroing the buffer size.
5165 * The counters (primitives generated, primitives emitted) may
5166 * be enabled even if there is not buffer bound. This ensures
5167 * that the primitives-emitted query won't increment.
5168 */
5169 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
5170
5171 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5172 }
5173
5174 radv_set_streamout_enable(cmd_buffer, false);
5175 }
5176
5177 void radv_CmdDrawIndirectByteCountEXT(
5178 VkCommandBuffer commandBuffer,
5179 uint32_t instanceCount,
5180 uint32_t firstInstance,
5181 VkBuffer _counterBuffer,
5182 VkDeviceSize counterBufferOffset,
5183 uint32_t counterOffset,
5184 uint32_t vertexStride)
5185 {
5186 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5187 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
5188 struct radv_draw_info info = {};
5189
5190 info.instance_count = instanceCount;
5191 info.first_instance = firstInstance;
5192 info.strmout_buffer = counterBuffer;
5193 info.strmout_buffer_offset = counterBufferOffset;
5194 info.stride = vertexStride;
5195
5196 radv_draw(cmd_buffer, &info);
5197 }