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radv: only allocate the GFX9 fence and EOP BOs for the gfx queue
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range);
61
62 const struct radv_dynamic_state default_dynamic_state = {
63 .viewport = {
64 .count = 0,
65 },
66 .scissor = {
67 .count = 0,
68 },
69 .line_width = 1.0f,
70 .depth_bias = {
71 .bias = 0.0f,
72 .clamp = 0.0f,
73 .slope = 0.0f,
74 },
75 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
76 .depth_bounds = {
77 .min = 0.0f,
78 .max = 1.0f,
79 },
80 .stencil_compare_mask = {
81 .front = ~0u,
82 .back = ~0u,
83 },
84 .stencil_write_mask = {
85 .front = ~0u,
86 .back = ~0u,
87 },
88 .stencil_reference = {
89 .front = 0u,
90 .back = 0u,
91 },
92 };
93
94 static void
95 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
96 const struct radv_dynamic_state *src)
97 {
98 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
99 uint32_t copy_mask = src->mask;
100 uint32_t dest_mask = 0;
101
102 /* Make sure to copy the number of viewports/scissors because they can
103 * only be specified at pipeline creation time.
104 */
105 dest->viewport.count = src->viewport.count;
106 dest->scissor.count = src->scissor.count;
107 dest->discard_rectangle.count = src->discard_rectangle.count;
108
109 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
110 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
111 src->viewport.count * sizeof(VkViewport))) {
112 typed_memcpy(dest->viewport.viewports,
113 src->viewport.viewports,
114 src->viewport.count);
115 dest_mask |= RADV_DYNAMIC_VIEWPORT;
116 }
117 }
118
119 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
120 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
121 src->scissor.count * sizeof(VkRect2D))) {
122 typed_memcpy(dest->scissor.scissors,
123 src->scissor.scissors, src->scissor.count);
124 dest_mask |= RADV_DYNAMIC_SCISSOR;
125 }
126 }
127
128 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
129 if (dest->line_width != src->line_width) {
130 dest->line_width = src->line_width;
131 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
132 }
133 }
134
135 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
136 if (memcmp(&dest->depth_bias, &src->depth_bias,
137 sizeof(src->depth_bias))) {
138 dest->depth_bias = src->depth_bias;
139 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
140 }
141 }
142
143 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
144 if (memcmp(&dest->blend_constants, &src->blend_constants,
145 sizeof(src->blend_constants))) {
146 typed_memcpy(dest->blend_constants,
147 src->blend_constants, 4);
148 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
149 }
150 }
151
152 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
153 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
154 sizeof(src->depth_bounds))) {
155 dest->depth_bounds = src->depth_bounds;
156 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
157 }
158 }
159
160 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
161 if (memcmp(&dest->stencil_compare_mask,
162 &src->stencil_compare_mask,
163 sizeof(src->stencil_compare_mask))) {
164 dest->stencil_compare_mask = src->stencil_compare_mask;
165 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
166 }
167 }
168
169 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
170 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
171 sizeof(src->stencil_write_mask))) {
172 dest->stencil_write_mask = src->stencil_write_mask;
173 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
174 }
175 }
176
177 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
178 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
179 sizeof(src->stencil_reference))) {
180 dest->stencil_reference = src->stencil_reference;
181 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
182 }
183 }
184
185 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
186 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
187 src->discard_rectangle.count * sizeof(VkRect2D))) {
188 typed_memcpy(dest->discard_rectangle.rectangles,
189 src->discard_rectangle.rectangles,
190 src->discard_rectangle.count);
191 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
192 }
193 }
194
195 cmd_buffer->state.dirty |= dest_mask;
196 }
197
198 static void
199 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
200 struct radv_pipeline *pipeline)
201 {
202 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
203 struct radv_shader_info *info;
204
205 if (!pipeline->streamout_shader)
206 return;
207
208 info = &pipeline->streamout_shader->info.info;
209 for (int i = 0; i < MAX_SO_BUFFERS; i++)
210 so->stride_in_dw[i] = info->so.strides[i];
211
212 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
213 }
214
215 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
216 {
217 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
218 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
219 }
220
221 enum ring_type radv_queue_family_to_ring(int f) {
222 switch (f) {
223 case RADV_QUEUE_GENERAL:
224 return RING_GFX;
225 case RADV_QUEUE_COMPUTE:
226 return RING_COMPUTE;
227 case RADV_QUEUE_TRANSFER:
228 return RING_DMA;
229 default:
230 unreachable("Unknown queue family");
231 }
232 }
233
234 static VkResult radv_create_cmd_buffer(
235 struct radv_device * device,
236 struct radv_cmd_pool * pool,
237 VkCommandBufferLevel level,
238 VkCommandBuffer* pCommandBuffer)
239 {
240 struct radv_cmd_buffer *cmd_buffer;
241 unsigned ring;
242 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
243 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
244 if (cmd_buffer == NULL)
245 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
246
247 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
248 cmd_buffer->device = device;
249 cmd_buffer->pool = pool;
250 cmd_buffer->level = level;
251
252 if (pool) {
253 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
254 cmd_buffer->queue_family_index = pool->queue_family_index;
255
256 } else {
257 /* Init the pool_link so we can safely call list_del when we destroy
258 * the command buffer
259 */
260 list_inithead(&cmd_buffer->pool_link);
261 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
262 }
263
264 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
265
266 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
267 if (!cmd_buffer->cs) {
268 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
269 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
270 }
271
272 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
273
274 list_inithead(&cmd_buffer->upload.list);
275
276 return VK_SUCCESS;
277 }
278
279 static void
280 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
281 {
282 list_del(&cmd_buffer->pool_link);
283
284 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
285 &cmd_buffer->upload.list, list) {
286 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
287 list_del(&up->list);
288 free(up);
289 }
290
291 if (cmd_buffer->upload.upload_bo)
292 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
293 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
294
295 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
296 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
297
298 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
299 }
300
301 static VkResult
302 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
303 {
304
305 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
306
307 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
308 &cmd_buffer->upload.list, list) {
309 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
310 list_del(&up->list);
311 free(up);
312 }
313
314 cmd_buffer->push_constant_stages = 0;
315 cmd_buffer->scratch_size_needed = 0;
316 cmd_buffer->compute_scratch_size_needed = 0;
317 cmd_buffer->esgs_ring_size_needed = 0;
318 cmd_buffer->gsvs_ring_size_needed = 0;
319 cmd_buffer->tess_rings_needed = false;
320 cmd_buffer->sample_positions_needed = false;
321
322 if (cmd_buffer->upload.upload_bo)
323 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
324 cmd_buffer->upload.upload_bo);
325 cmd_buffer->upload.offset = 0;
326
327 cmd_buffer->record_result = VK_SUCCESS;
328
329 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
330 cmd_buffer->descriptors[i].dirty = 0;
331 cmd_buffer->descriptors[i].valid = 0;
332 cmd_buffer->descriptors[i].push_dirty = false;
333 }
334
335 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
336 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
337 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
338 unsigned eop_bug_offset;
339 void *fence_ptr;
340
341 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
342 &cmd_buffer->gfx9_fence_offset,
343 &fence_ptr);
344 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
345
346 /* Allocate a buffer for the EOP bug on GFX9. */
347 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 0,
348 &eop_bug_offset, &fence_ptr);
349 cmd_buffer->gfx9_eop_bug_va =
350 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
351 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
352 }
353
354 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
355
356 return cmd_buffer->record_result;
357 }
358
359 static bool
360 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
361 uint64_t min_needed)
362 {
363 uint64_t new_size;
364 struct radeon_winsys_bo *bo;
365 struct radv_cmd_buffer_upload *upload;
366 struct radv_device *device = cmd_buffer->device;
367
368 new_size = MAX2(min_needed, 16 * 1024);
369 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
370
371 bo = device->ws->buffer_create(device->ws,
372 new_size, 4096,
373 RADEON_DOMAIN_GTT,
374 RADEON_FLAG_CPU_ACCESS|
375 RADEON_FLAG_NO_INTERPROCESS_SHARING |
376 RADEON_FLAG_32BIT);
377
378 if (!bo) {
379 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
380 return false;
381 }
382
383 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
384 if (cmd_buffer->upload.upload_bo) {
385 upload = malloc(sizeof(*upload));
386
387 if (!upload) {
388 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
389 device->ws->buffer_destroy(bo);
390 return false;
391 }
392
393 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
394 list_add(&upload->list, &cmd_buffer->upload.list);
395 }
396
397 cmd_buffer->upload.upload_bo = bo;
398 cmd_buffer->upload.size = new_size;
399 cmd_buffer->upload.offset = 0;
400 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
401
402 if (!cmd_buffer->upload.map) {
403 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
404 return false;
405 }
406
407 return true;
408 }
409
410 bool
411 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
412 unsigned size,
413 unsigned alignment,
414 unsigned *out_offset,
415 void **ptr)
416 {
417 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
418 if (offset + size > cmd_buffer->upload.size) {
419 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
420 return false;
421 offset = 0;
422 }
423
424 *out_offset = offset;
425 *ptr = cmd_buffer->upload.map + offset;
426
427 cmd_buffer->upload.offset = offset + size;
428 return true;
429 }
430
431 bool
432 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
433 unsigned size, unsigned alignment,
434 const void *data, unsigned *out_offset)
435 {
436 uint8_t *ptr;
437
438 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
439 out_offset, (void **)&ptr))
440 return false;
441
442 if (ptr)
443 memcpy(ptr, data, size);
444
445 return true;
446 }
447
448 static void
449 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
450 unsigned count, const uint32_t *data)
451 {
452 struct radeon_cmdbuf *cs = cmd_buffer->cs;
453
454 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
455
456 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
457 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
458 S_370_WR_CONFIRM(1) |
459 S_370_ENGINE_SEL(V_370_ME));
460 radeon_emit(cs, va);
461 radeon_emit(cs, va >> 32);
462 radeon_emit_array(cs, data, count);
463 }
464
465 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
466 {
467 struct radv_device *device = cmd_buffer->device;
468 struct radeon_cmdbuf *cs = cmd_buffer->cs;
469 uint64_t va;
470
471 va = radv_buffer_get_va(device->trace_bo);
472 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
473 va += 4;
474
475 ++cmd_buffer->state.trace_id;
476 radv_emit_write_data_packet(cmd_buffer, va, 1,
477 &cmd_buffer->state.trace_id);
478
479 radeon_check_space(cmd_buffer->device->ws, cs, 2);
480
481 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
482 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
483 }
484
485 static void
486 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
487 enum radv_cmd_flush_bits flags)
488 {
489 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
490 uint32_t *ptr = NULL;
491 uint64_t va = 0;
492
493 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
494 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
495
496 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
497 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
498 cmd_buffer->gfx9_fence_offset;
499 ptr = &cmd_buffer->gfx9_fence_idx;
500 }
501
502 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
503
504 /* Force wait for graphics or compute engines to be idle. */
505 si_cs_emit_cache_flush(cmd_buffer->cs,
506 cmd_buffer->device->physical_device->rad_info.chip_class,
507 ptr, va,
508 radv_cmd_buffer_uses_mec(cmd_buffer),
509 flags, cmd_buffer->gfx9_eop_bug_va);
510 }
511
512 if (unlikely(cmd_buffer->device->trace_bo))
513 radv_cmd_buffer_trace_emit(cmd_buffer);
514 }
515
516 static void
517 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
518 struct radv_pipeline *pipeline, enum ring_type ring)
519 {
520 struct radv_device *device = cmd_buffer->device;
521 uint32_t data[2];
522 uint64_t va;
523
524 va = radv_buffer_get_va(device->trace_bo);
525
526 switch (ring) {
527 case RING_GFX:
528 va += 8;
529 break;
530 case RING_COMPUTE:
531 va += 16;
532 break;
533 default:
534 assert(!"invalid ring type");
535 }
536
537 data[0] = (uintptr_t)pipeline;
538 data[1] = (uintptr_t)pipeline >> 32;
539
540 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
541 }
542
543 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
544 VkPipelineBindPoint bind_point,
545 struct radv_descriptor_set *set,
546 unsigned idx)
547 {
548 struct radv_descriptor_state *descriptors_state =
549 radv_get_descriptors_state(cmd_buffer, bind_point);
550
551 descriptors_state->sets[idx] = set;
552
553 descriptors_state->valid |= (1u << idx); /* active descriptors */
554 descriptors_state->dirty |= (1u << idx);
555 }
556
557 static void
558 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
559 VkPipelineBindPoint bind_point)
560 {
561 struct radv_descriptor_state *descriptors_state =
562 radv_get_descriptors_state(cmd_buffer, bind_point);
563 struct radv_device *device = cmd_buffer->device;
564 uint32_t data[MAX_SETS * 2] = {};
565 uint64_t va;
566 unsigned i;
567 va = radv_buffer_get_va(device->trace_bo) + 24;
568
569 for_each_bit(i, descriptors_state->valid) {
570 struct radv_descriptor_set *set = descriptors_state->sets[i];
571 data[i * 2] = (uintptr_t)set;
572 data[i * 2 + 1] = (uintptr_t)set >> 32;
573 }
574
575 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
576 }
577
578 struct radv_userdata_info *
579 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
580 gl_shader_stage stage,
581 int idx)
582 {
583 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
584 return &shader->info.user_sgprs_locs.shader_data[idx];
585 }
586
587 static void
588 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
589 struct radv_pipeline *pipeline,
590 gl_shader_stage stage,
591 int idx, uint64_t va)
592 {
593 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
594 uint32_t base_reg = pipeline->user_data_0[stage];
595 if (loc->sgpr_idx == -1)
596 return;
597
598 assert(loc->num_sgprs == 1);
599 assert(!loc->indirect);
600
601 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
602 base_reg + loc->sgpr_idx * 4, va, false);
603 }
604
605 static void
606 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
607 struct radv_pipeline *pipeline,
608 struct radv_descriptor_state *descriptors_state,
609 gl_shader_stage stage)
610 {
611 struct radv_device *device = cmd_buffer->device;
612 struct radeon_cmdbuf *cs = cmd_buffer->cs;
613 uint32_t sh_base = pipeline->user_data_0[stage];
614 struct radv_userdata_locations *locs =
615 &pipeline->shaders[stage]->info.user_sgprs_locs;
616 unsigned mask = locs->descriptor_sets_enabled;
617
618 mask &= descriptors_state->dirty & descriptors_state->valid;
619
620 while (mask) {
621 int start, count;
622
623 u_bit_scan_consecutive_range(&mask, &start, &count);
624
625 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
626 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
627
628 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
629 for (int i = 0; i < count; i++) {
630 struct radv_descriptor_set *set =
631 descriptors_state->sets[start + i];
632
633 radv_emit_shader_pointer_body(device, cs, set->va, true);
634 }
635 }
636 }
637
638 static void
639 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
640 struct radv_pipeline *pipeline)
641 {
642 int num_samples = pipeline->graphics.ms.num_samples;
643 struct radv_multisample_state *ms = &pipeline->graphics.ms;
644 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
645
646 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
647 cmd_buffer->sample_positions_needed = true;
648
649 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
650 return;
651
652 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
653 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
654 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
655
656 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
657
658 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
659
660 /* GFX9: Flush DFSM when the AA mode changes. */
661 if (cmd_buffer->device->dfsm_allowed) {
662 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
663 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
664 }
665
666 cmd_buffer->state.context_roll_without_scissor_emitted = true;
667 }
668
669 static void
670 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
671 struct radv_shader_variant *shader)
672 {
673 uint64_t va;
674
675 if (!shader)
676 return;
677
678 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
679
680 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
681 }
682
683 static void
684 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
685 struct radv_pipeline *pipeline,
686 bool vertex_stage_only)
687 {
688 struct radv_cmd_state *state = &cmd_buffer->state;
689 uint32_t mask = state->prefetch_L2_mask;
690
691 if (vertex_stage_only) {
692 /* Fast prefetch path for starting draws as soon as possible.
693 */
694 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
695 RADV_PREFETCH_VBO_DESCRIPTORS);
696 }
697
698 if (mask & RADV_PREFETCH_VS)
699 radv_emit_shader_prefetch(cmd_buffer,
700 pipeline->shaders[MESA_SHADER_VERTEX]);
701
702 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
703 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
704
705 if (mask & RADV_PREFETCH_TCS)
706 radv_emit_shader_prefetch(cmd_buffer,
707 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
708
709 if (mask & RADV_PREFETCH_TES)
710 radv_emit_shader_prefetch(cmd_buffer,
711 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
712
713 if (mask & RADV_PREFETCH_GS) {
714 radv_emit_shader_prefetch(cmd_buffer,
715 pipeline->shaders[MESA_SHADER_GEOMETRY]);
716 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
717 }
718
719 if (mask & RADV_PREFETCH_PS)
720 radv_emit_shader_prefetch(cmd_buffer,
721 pipeline->shaders[MESA_SHADER_FRAGMENT]);
722
723 state->prefetch_L2_mask &= ~mask;
724 }
725
726 static void
727 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
728 {
729 if (!cmd_buffer->device->physical_device->rbplus_allowed)
730 return;
731
732 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
733 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
734 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
735
736 unsigned sx_ps_downconvert = 0;
737 unsigned sx_blend_opt_epsilon = 0;
738 unsigned sx_blend_opt_control = 0;
739
740 for (unsigned i = 0; i < subpass->color_count; ++i) {
741 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
742 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
743 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
744 continue;
745 }
746
747 int idx = subpass->color_attachments[i].attachment;
748 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
749
750 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
751 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
752 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
753 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
754
755 bool has_alpha, has_rgb;
756
757 /* Set if RGB and A are present. */
758 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
759
760 if (format == V_028C70_COLOR_8 ||
761 format == V_028C70_COLOR_16 ||
762 format == V_028C70_COLOR_32)
763 has_rgb = !has_alpha;
764 else
765 has_rgb = true;
766
767 /* Check the colormask and export format. */
768 if (!(colormask & 0x7))
769 has_rgb = false;
770 if (!(colormask & 0x8))
771 has_alpha = false;
772
773 if (spi_format == V_028714_SPI_SHADER_ZERO) {
774 has_rgb = false;
775 has_alpha = false;
776 }
777
778 /* Disable value checking for disabled channels. */
779 if (!has_rgb)
780 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
781 if (!has_alpha)
782 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
783
784 /* Enable down-conversion for 32bpp and smaller formats. */
785 switch (format) {
786 case V_028C70_COLOR_8:
787 case V_028C70_COLOR_8_8:
788 case V_028C70_COLOR_8_8_8_8:
789 /* For 1 and 2-channel formats, use the superset thereof. */
790 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
791 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
792 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
793 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
794 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
795 }
796 break;
797
798 case V_028C70_COLOR_5_6_5:
799 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
800 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
801 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
802 }
803 break;
804
805 case V_028C70_COLOR_1_5_5_5:
806 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
807 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
808 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
809 }
810 break;
811
812 case V_028C70_COLOR_4_4_4_4:
813 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
814 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
815 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
816 }
817 break;
818
819 case V_028C70_COLOR_32:
820 if (swap == V_028C70_SWAP_STD &&
821 spi_format == V_028714_SPI_SHADER_32_R)
822 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
823 else if (swap == V_028C70_SWAP_ALT_REV &&
824 spi_format == V_028714_SPI_SHADER_32_AR)
825 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
826 break;
827
828 case V_028C70_COLOR_16:
829 case V_028C70_COLOR_16_16:
830 /* For 1-channel formats, use the superset thereof. */
831 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
832 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
833 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
834 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
835 if (swap == V_028C70_SWAP_STD ||
836 swap == V_028C70_SWAP_STD_REV)
837 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
838 else
839 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
840 }
841 break;
842
843 case V_028C70_COLOR_10_11_11:
844 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
845 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
846 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
847 }
848 break;
849
850 case V_028C70_COLOR_2_10_10_10:
851 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
852 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
853 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
854 }
855 break;
856 }
857 }
858
859 for (unsigned i = subpass->color_count; i < 8; ++i) {
860 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
861 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
862 }
863 /* TODO: avoid redundantly setting context registers */
864 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
865 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
866 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
867 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
868
869 cmd_buffer->state.context_roll_without_scissor_emitted = true;
870 }
871
872 static void
873 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
874 {
875 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
876
877 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
878 return;
879
880 radv_update_multisample_state(cmd_buffer, pipeline);
881
882 cmd_buffer->scratch_size_needed =
883 MAX2(cmd_buffer->scratch_size_needed,
884 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
885
886 if (!cmd_buffer->state.emitted_pipeline ||
887 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
888 pipeline->graphics.can_use_guardband)
889 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
890
891 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
892
893 if (!cmd_buffer->state.emitted_pipeline ||
894 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
895 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
896 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
897 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
898 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
899 cmd_buffer->state.context_roll_without_scissor_emitted = true;
900 }
901
902 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
903 if (!pipeline->shaders[i])
904 continue;
905
906 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
907 pipeline->shaders[i]->bo);
908 }
909
910 if (radv_pipeline_has_gs(pipeline))
911 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
912 pipeline->gs_copy_shader->bo);
913
914 if (unlikely(cmd_buffer->device->trace_bo))
915 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
916
917 cmd_buffer->state.emitted_pipeline = pipeline;
918
919 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
920 }
921
922 static void
923 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
924 {
925 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
926 cmd_buffer->state.dynamic.viewport.viewports);
927 }
928
929 static void
930 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
931 {
932 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
933
934 si_write_scissors(cmd_buffer->cs, 0, count,
935 cmd_buffer->state.dynamic.scissor.scissors,
936 cmd_buffer->state.dynamic.viewport.viewports,
937 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
938
939 cmd_buffer->state.context_roll_without_scissor_emitted = false;
940 }
941
942 static void
943 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
944 {
945 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
946 return;
947
948 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
949 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
950 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
951 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
952 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
953 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
954 S_028214_BR_Y(rect.offset.y + rect.extent.height));
955 }
956 }
957
958 static void
959 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
960 {
961 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
962
963 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
964 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
965 }
966
967 static void
968 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
969 {
970 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
971
972 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
973 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
974 }
975
976 static void
977 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
978 {
979 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
980
981 radeon_set_context_reg_seq(cmd_buffer->cs,
982 R_028430_DB_STENCILREFMASK, 2);
983 radeon_emit(cmd_buffer->cs,
984 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
985 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
986 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
987 S_028430_STENCILOPVAL(1));
988 radeon_emit(cmd_buffer->cs,
989 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
990 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
991 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
992 S_028434_STENCILOPVAL_BF(1));
993 }
994
995 static void
996 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
997 {
998 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
999
1000 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1001 fui(d->depth_bounds.min));
1002 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1003 fui(d->depth_bounds.max));
1004 }
1005
1006 static void
1007 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1008 {
1009 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1010 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1011 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1012
1013
1014 radeon_set_context_reg_seq(cmd_buffer->cs,
1015 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1016 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1017 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1018 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1019 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1020 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1021 }
1022
1023 static void
1024 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1025 int index,
1026 struct radv_attachment_info *att,
1027 struct radv_image *image,
1028 VkImageLayout layout)
1029 {
1030 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1031 struct radv_color_buffer_info *cb = &att->cb;
1032 uint32_t cb_color_info = cb->cb_color_info;
1033
1034 if (!radv_layout_dcc_compressed(image, layout,
1035 radv_image_queue_family_mask(image,
1036 cmd_buffer->queue_family_index,
1037 cmd_buffer->queue_family_index))) {
1038 cb_color_info &= C_028C70_DCC_ENABLE;
1039 }
1040
1041 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1042 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1043 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1044 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1045 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1046 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1047 radeon_emit(cmd_buffer->cs, cb_color_info);
1048 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1049 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1050 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1051 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1052 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1053 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1054
1055 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1056 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1057 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1058
1059 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1060 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1061 } else {
1062 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1063 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1064 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1065 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1066 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1067 radeon_emit(cmd_buffer->cs, cb_color_info);
1068 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1069 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1070 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1071 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1072 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1073 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1074
1075 if (is_vi) { /* DCC BASE */
1076 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1077 }
1078 }
1079
1080 if (radv_image_has_dcc(image)) {
1081 /* Drawing with DCC enabled also compresses colorbuffers. */
1082 radv_update_dcc_metadata(cmd_buffer, image, true);
1083 }
1084 }
1085
1086 static void
1087 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1088 struct radv_ds_buffer_info *ds,
1089 struct radv_image *image, VkImageLayout layout,
1090 bool requires_cond_exec)
1091 {
1092 uint32_t db_z_info = ds->db_z_info;
1093 uint32_t db_z_info_reg;
1094
1095 if (!radv_image_is_tc_compat_htile(image))
1096 return;
1097
1098 if (!radv_layout_has_htile(image, layout,
1099 radv_image_queue_family_mask(image,
1100 cmd_buffer->queue_family_index,
1101 cmd_buffer->queue_family_index))) {
1102 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1103 }
1104
1105 db_z_info &= C_028040_ZRANGE_PRECISION;
1106
1107 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1108 db_z_info_reg = R_028038_DB_Z_INFO;
1109 } else {
1110 db_z_info_reg = R_028040_DB_Z_INFO;
1111 }
1112
1113 /* When we don't know the last fast clear value we need to emit a
1114 * conditional packet that will eventually skip the following
1115 * SET_CONTEXT_REG packet.
1116 */
1117 if (requires_cond_exec) {
1118 uint64_t va = radv_buffer_get_va(image->bo);
1119 va += image->offset + image->tc_compat_zrange_offset;
1120
1121 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1122 radeon_emit(cmd_buffer->cs, va);
1123 radeon_emit(cmd_buffer->cs, va >> 32);
1124 radeon_emit(cmd_buffer->cs, 0);
1125 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1126 }
1127
1128 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1129 }
1130
1131 static void
1132 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1133 struct radv_ds_buffer_info *ds,
1134 struct radv_image *image,
1135 VkImageLayout layout)
1136 {
1137 uint32_t db_z_info = ds->db_z_info;
1138 uint32_t db_stencil_info = ds->db_stencil_info;
1139
1140 if (!radv_layout_has_htile(image, layout,
1141 radv_image_queue_family_mask(image,
1142 cmd_buffer->queue_family_index,
1143 cmd_buffer->queue_family_index))) {
1144 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1145 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1146 }
1147
1148 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1149 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1150
1151
1152 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1153 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1154 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1155 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1156 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1157
1158 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1159 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1160 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1161 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1162 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1163 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1164 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1165 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1166 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1167 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1168 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1169
1170 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1171 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1172 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1173 } else {
1174 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1175
1176 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1177 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1178 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1179 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1180 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1181 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1182 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1183 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1184 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1185 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1186
1187 }
1188
1189 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1190 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1191
1192 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1193 ds->pa_su_poly_offset_db_fmt_cntl);
1194 }
1195
1196 /**
1197 * Update the fast clear depth/stencil values if the image is bound as a
1198 * depth/stencil buffer.
1199 */
1200 static void
1201 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1202 struct radv_image *image,
1203 VkClearDepthStencilValue ds_clear_value,
1204 VkImageAspectFlags aspects)
1205 {
1206 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1207 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1208 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1209 struct radv_attachment_info *att;
1210 uint32_t att_idx;
1211
1212 if (!framebuffer || !subpass)
1213 return;
1214
1215 att_idx = subpass->depth_stencil_attachment.attachment;
1216 if (att_idx == VK_ATTACHMENT_UNUSED)
1217 return;
1218
1219 att = &framebuffer->attachments[att_idx];
1220 if (att->attachment->image != image)
1221 return;
1222
1223 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1224 radeon_emit(cs, ds_clear_value.stencil);
1225 radeon_emit(cs, fui(ds_clear_value.depth));
1226
1227 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1228 * only needed when clearing Z to 0.0.
1229 */
1230 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1231 ds_clear_value.depth == 0.0) {
1232 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1233
1234 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1235 layout, false);
1236 }
1237
1238 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1239 }
1240
1241 /**
1242 * Set the clear depth/stencil values to the image's metadata.
1243 */
1244 static void
1245 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1246 struct radv_image *image,
1247 VkClearDepthStencilValue ds_clear_value,
1248 VkImageAspectFlags aspects)
1249 {
1250 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1251 uint64_t va = radv_buffer_get_va(image->bo);
1252 unsigned reg_offset = 0, reg_count = 0;
1253
1254 va += image->offset + image->clear_value_offset;
1255
1256 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1257 ++reg_count;
1258 } else {
1259 ++reg_offset;
1260 va += 4;
1261 }
1262 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1263 ++reg_count;
1264
1265 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1266 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1267 S_370_WR_CONFIRM(1) |
1268 S_370_ENGINE_SEL(V_370_PFP));
1269 radeon_emit(cs, va);
1270 radeon_emit(cs, va >> 32);
1271 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1272 radeon_emit(cs, ds_clear_value.stencil);
1273 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1274 radeon_emit(cs, fui(ds_clear_value.depth));
1275 }
1276
1277 /**
1278 * Update the TC-compat metadata value for this image.
1279 */
1280 static void
1281 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1282 struct radv_image *image,
1283 uint32_t value)
1284 {
1285 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1286 uint64_t va = radv_buffer_get_va(image->bo);
1287 va += image->offset + image->tc_compat_zrange_offset;
1288
1289 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1290 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1291 S_370_WR_CONFIRM(1) |
1292 S_370_ENGINE_SEL(V_370_PFP));
1293 radeon_emit(cs, va);
1294 radeon_emit(cs, va >> 32);
1295 radeon_emit(cs, value);
1296 }
1297
1298 static void
1299 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1300 struct radv_image *image,
1301 VkClearDepthStencilValue ds_clear_value)
1302 {
1303 uint64_t va = radv_buffer_get_va(image->bo);
1304 va += image->offset + image->tc_compat_zrange_offset;
1305 uint32_t cond_val;
1306
1307 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1308 * depth clear value is 0.0f.
1309 */
1310 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1311
1312 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, cond_val);
1313 }
1314
1315 /**
1316 * Update the clear depth/stencil values for this image.
1317 */
1318 void
1319 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1320 struct radv_image *image,
1321 VkClearDepthStencilValue ds_clear_value,
1322 VkImageAspectFlags aspects)
1323 {
1324 assert(radv_image_has_htile(image));
1325
1326 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1327
1328 if (radv_image_is_tc_compat_htile(image) &&
1329 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1330 radv_update_tc_compat_zrange_metadata(cmd_buffer, image,
1331 ds_clear_value);
1332 }
1333
1334 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1335 aspects);
1336 }
1337
1338 /**
1339 * Load the clear depth/stencil values from the image's metadata.
1340 */
1341 static void
1342 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1343 struct radv_image *image)
1344 {
1345 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1346 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1347 uint64_t va = radv_buffer_get_va(image->bo);
1348 unsigned reg_offset = 0, reg_count = 0;
1349
1350 va += image->offset + image->clear_value_offset;
1351
1352 if (!radv_image_has_htile(image))
1353 return;
1354
1355 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1356 ++reg_count;
1357 } else {
1358 ++reg_offset;
1359 va += 4;
1360 }
1361 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1362 ++reg_count;
1363
1364 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1365
1366 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1367 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1368 radeon_emit(cs, va);
1369 radeon_emit(cs, va >> 32);
1370 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1371 radeon_emit(cs, reg_count);
1372 } else {
1373 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1374 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1375 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1376 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1377 radeon_emit(cs, va);
1378 radeon_emit(cs, va >> 32);
1379 radeon_emit(cs, reg >> 2);
1380 radeon_emit(cs, 0);
1381
1382 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1383 radeon_emit(cs, 0);
1384 }
1385 }
1386
1387 /*
1388 * With DCC some colors don't require CMASK elimination before being
1389 * used as a texture. This sets a predicate value to determine if the
1390 * cmask eliminate is required.
1391 */
1392 void
1393 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1394 struct radv_image *image, bool value)
1395 {
1396 uint64_t pred_val = value;
1397 uint64_t va = radv_buffer_get_va(image->bo);
1398 va += image->offset + image->fce_pred_offset;
1399
1400 assert(radv_image_has_dcc(image));
1401
1402 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1403 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1404 S_370_WR_CONFIRM(1) |
1405 S_370_ENGINE_SEL(V_370_PFP));
1406 radeon_emit(cmd_buffer->cs, va);
1407 radeon_emit(cmd_buffer->cs, va >> 32);
1408 radeon_emit(cmd_buffer->cs, pred_val);
1409 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1410 }
1411
1412 /**
1413 * Update the DCC predicate to reflect the compression state.
1414 */
1415 void
1416 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1417 struct radv_image *image, bool value)
1418 {
1419 uint64_t pred_val = value;
1420 uint64_t va = radv_buffer_get_va(image->bo);
1421 va += image->offset + image->dcc_pred_offset;
1422
1423 assert(radv_image_has_dcc(image));
1424
1425 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1426 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1427 S_370_WR_CONFIRM(1) |
1428 S_370_ENGINE_SEL(V_370_PFP));
1429 radeon_emit(cmd_buffer->cs, va);
1430 radeon_emit(cmd_buffer->cs, va >> 32);
1431 radeon_emit(cmd_buffer->cs, pred_val);
1432 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1433 }
1434
1435 /**
1436 * Update the fast clear color values if the image is bound as a color buffer.
1437 */
1438 static void
1439 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1440 struct radv_image *image,
1441 int cb_idx,
1442 uint32_t color_values[2])
1443 {
1444 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1445 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1446 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1447 struct radv_attachment_info *att;
1448 uint32_t att_idx;
1449
1450 if (!framebuffer || !subpass)
1451 return;
1452
1453 att_idx = subpass->color_attachments[cb_idx].attachment;
1454 if (att_idx == VK_ATTACHMENT_UNUSED)
1455 return;
1456
1457 att = &framebuffer->attachments[att_idx];
1458 if (att->attachment->image != image)
1459 return;
1460
1461 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1462 radeon_emit(cs, color_values[0]);
1463 radeon_emit(cs, color_values[1]);
1464
1465 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1466 }
1467
1468 /**
1469 * Set the clear color values to the image's metadata.
1470 */
1471 static void
1472 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1473 struct radv_image *image,
1474 uint32_t color_values[2])
1475 {
1476 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1477 uint64_t va = radv_buffer_get_va(image->bo);
1478
1479 va += image->offset + image->clear_value_offset;
1480
1481 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1482
1483 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1484 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1485 S_370_WR_CONFIRM(1) |
1486 S_370_ENGINE_SEL(V_370_PFP));
1487 radeon_emit(cs, va);
1488 radeon_emit(cs, va >> 32);
1489 radeon_emit(cs, color_values[0]);
1490 radeon_emit(cs, color_values[1]);
1491 }
1492
1493 /**
1494 * Update the clear color values for this image.
1495 */
1496 void
1497 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1498 struct radv_image *image,
1499 int cb_idx,
1500 uint32_t color_values[2])
1501 {
1502 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1503
1504 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
1505
1506 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1507 color_values);
1508 }
1509
1510 /**
1511 * Load the clear color values from the image's metadata.
1512 */
1513 static void
1514 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1515 struct radv_image *image,
1516 int cb_idx)
1517 {
1518 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1519 uint64_t va = radv_buffer_get_va(image->bo);
1520
1521 va += image->offset + image->clear_value_offset;
1522
1523 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1524 return;
1525
1526 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1527
1528 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1529 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1530 radeon_emit(cs, va);
1531 radeon_emit(cs, va >> 32);
1532 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1533 radeon_emit(cs, 2);
1534 } else {
1535 /* TODO: Figure out how to use LOAD_CONTEXT_REG on SI/CIK. */
1536 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1537 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1538 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1539 COPY_DATA_COUNT_SEL);
1540 radeon_emit(cs, va);
1541 radeon_emit(cs, va >> 32);
1542 radeon_emit(cs, reg >> 2);
1543 radeon_emit(cs, 0);
1544
1545 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1546 radeon_emit(cs, 0);
1547 }
1548 }
1549
1550 static void
1551 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1552 {
1553 int i;
1554 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1555 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1556 unsigned num_bpp64_colorbufs = 0;
1557
1558 /* this may happen for inherited secondary recording */
1559 if (!framebuffer)
1560 return;
1561
1562 for (i = 0; i < 8; ++i) {
1563 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1564 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1565 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1566 continue;
1567 }
1568
1569 int idx = subpass->color_attachments[i].attachment;
1570 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1571 struct radv_image *image = att->attachment->image;
1572 VkImageLayout layout = subpass->color_attachments[i].layout;
1573
1574 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1575
1576 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1577 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1578
1579 radv_load_color_clear_metadata(cmd_buffer, image, i);
1580
1581 if (image->surface.bpe >= 8)
1582 num_bpp64_colorbufs++;
1583 }
1584
1585 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1586 int idx = subpass->depth_stencil_attachment.attachment;
1587 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1588 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1589 struct radv_image *image = att->attachment->image;
1590 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1591 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1592 cmd_buffer->queue_family_index,
1593 cmd_buffer->queue_family_index);
1594 /* We currently don't support writing decompressed HTILE */
1595 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1596 radv_layout_is_htile_compressed(image, layout, queue_mask));
1597
1598 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1599
1600 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1601 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1602 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1603 }
1604 radv_load_ds_clear_metadata(cmd_buffer, image);
1605 } else {
1606 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1607 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1608 else
1609 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1610
1611 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1612 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1613 }
1614 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1615 S_028208_BR_X(framebuffer->width) |
1616 S_028208_BR_Y(framebuffer->height));
1617
1618 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1619 uint8_t watermark = 4; /* Default value for VI. */
1620
1621 /* For optimal DCC performance. */
1622 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1623 if (num_bpp64_colorbufs >= 5) {
1624 watermark = 8;
1625 } else {
1626 watermark = 6;
1627 }
1628 }
1629
1630 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
1631 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
1632 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark));
1633 }
1634
1635 if (cmd_buffer->device->dfsm_allowed) {
1636 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1637 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1638 }
1639
1640 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1641 }
1642
1643 static void
1644 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1645 {
1646 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1647 struct radv_cmd_state *state = &cmd_buffer->state;
1648
1649 if (state->index_type != state->last_index_type) {
1650 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1651 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1652 2, state->index_type);
1653 } else {
1654 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1655 radeon_emit(cs, state->index_type);
1656 }
1657
1658 state->last_index_type = state->index_type;
1659 }
1660
1661 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1662 radeon_emit(cs, state->index_va);
1663 radeon_emit(cs, state->index_va >> 32);
1664
1665 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1666 radeon_emit(cs, state->max_index_count);
1667
1668 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1669 }
1670
1671 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1672 {
1673 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1674 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1675 uint32_t pa_sc_mode_cntl_1 =
1676 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1677 uint32_t db_count_control;
1678
1679 if(!cmd_buffer->state.active_occlusion_queries) {
1680 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1681 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1682 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1683 has_perfect_queries) {
1684 /* Re-enable out-of-order rasterization if the
1685 * bound pipeline supports it and if it's has
1686 * been disabled before starting any perfect
1687 * occlusion queries.
1688 */
1689 radeon_set_context_reg(cmd_buffer->cs,
1690 R_028A4C_PA_SC_MODE_CNTL_1,
1691 pa_sc_mode_cntl_1);
1692 }
1693 }
1694 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1695 } else {
1696 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1697 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1698
1699 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1700 db_count_control =
1701 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1702 S_028004_SAMPLE_RATE(sample_rate) |
1703 S_028004_ZPASS_ENABLE(1) |
1704 S_028004_SLICE_EVEN_ENABLE(1) |
1705 S_028004_SLICE_ODD_ENABLE(1);
1706
1707 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1708 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1709 has_perfect_queries) {
1710 /* If the bound pipeline has enabled
1711 * out-of-order rasterization, we should
1712 * disable it before starting any perfect
1713 * occlusion queries.
1714 */
1715 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1716
1717 radeon_set_context_reg(cmd_buffer->cs,
1718 R_028A4C_PA_SC_MODE_CNTL_1,
1719 pa_sc_mode_cntl_1);
1720 }
1721 } else {
1722 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1723 S_028004_SAMPLE_RATE(sample_rate);
1724 }
1725 }
1726
1727 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1728
1729 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1730 }
1731
1732 static void
1733 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1734 {
1735 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1736
1737 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1738 radv_emit_viewport(cmd_buffer);
1739
1740 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1741 !cmd_buffer->device->physical_device->has_scissor_bug)
1742 radv_emit_scissor(cmd_buffer);
1743
1744 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1745 radv_emit_line_width(cmd_buffer);
1746
1747 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1748 radv_emit_blend_constants(cmd_buffer);
1749
1750 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1751 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1752 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1753 radv_emit_stencil(cmd_buffer);
1754
1755 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1756 radv_emit_depth_bounds(cmd_buffer);
1757
1758 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1759 radv_emit_depth_bias(cmd_buffer);
1760
1761 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1762 radv_emit_discard_rectangle(cmd_buffer);
1763
1764 cmd_buffer->state.dirty &= ~states;
1765 }
1766
1767 static void
1768 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1769 VkPipelineBindPoint bind_point)
1770 {
1771 struct radv_descriptor_state *descriptors_state =
1772 radv_get_descriptors_state(cmd_buffer, bind_point);
1773 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1774 unsigned bo_offset;
1775
1776 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1777 set->mapped_ptr,
1778 &bo_offset))
1779 return;
1780
1781 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1782 set->va += bo_offset;
1783 }
1784
1785 static void
1786 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1787 VkPipelineBindPoint bind_point)
1788 {
1789 struct radv_descriptor_state *descriptors_state =
1790 radv_get_descriptors_state(cmd_buffer, bind_point);
1791 uint32_t size = MAX_SETS * 4;
1792 uint32_t offset;
1793 void *ptr;
1794
1795 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1796 256, &offset, &ptr))
1797 return;
1798
1799 for (unsigned i = 0; i < MAX_SETS; i++) {
1800 uint32_t *uptr = ((uint32_t *)ptr) + i;
1801 uint64_t set_va = 0;
1802 struct radv_descriptor_set *set = descriptors_state->sets[i];
1803 if (descriptors_state->valid & (1u << i))
1804 set_va = set->va;
1805 uptr[0] = set_va & 0xffffffff;
1806 }
1807
1808 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1809 va += offset;
1810
1811 if (cmd_buffer->state.pipeline) {
1812 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1813 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1814 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1815
1816 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1817 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1818 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1819
1820 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1821 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1822 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1823
1824 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1825 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1826 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1827
1828 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1829 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1830 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1831 }
1832
1833 if (cmd_buffer->state.compute_pipeline)
1834 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1835 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1836 }
1837
1838 static void
1839 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1840 VkShaderStageFlags stages)
1841 {
1842 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1843 VK_PIPELINE_BIND_POINT_COMPUTE :
1844 VK_PIPELINE_BIND_POINT_GRAPHICS;
1845 struct radv_descriptor_state *descriptors_state =
1846 radv_get_descriptors_state(cmd_buffer, bind_point);
1847 struct radv_cmd_state *state = &cmd_buffer->state;
1848 bool flush_indirect_descriptors;
1849
1850 if (!descriptors_state->dirty)
1851 return;
1852
1853 if (descriptors_state->push_dirty)
1854 radv_flush_push_descriptors(cmd_buffer, bind_point);
1855
1856 flush_indirect_descriptors =
1857 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
1858 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
1859 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
1860 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
1861
1862 if (flush_indirect_descriptors)
1863 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1864
1865 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1866 cmd_buffer->cs,
1867 MAX_SETS * MESA_SHADER_STAGES * 4);
1868
1869 if (cmd_buffer->state.pipeline) {
1870 radv_foreach_stage(stage, stages) {
1871 if (!cmd_buffer->state.pipeline->shaders[stage])
1872 continue;
1873
1874 radv_emit_descriptor_pointers(cmd_buffer,
1875 cmd_buffer->state.pipeline,
1876 descriptors_state, stage);
1877 }
1878 }
1879
1880 if (cmd_buffer->state.compute_pipeline &&
1881 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
1882 radv_emit_descriptor_pointers(cmd_buffer,
1883 cmd_buffer->state.compute_pipeline,
1884 descriptors_state,
1885 MESA_SHADER_COMPUTE);
1886 }
1887
1888 descriptors_state->dirty = 0;
1889 descriptors_state->push_dirty = false;
1890
1891 assert(cmd_buffer->cs->cdw <= cdw_max);
1892
1893 if (unlikely(cmd_buffer->device->trace_bo))
1894 radv_save_descriptors(cmd_buffer, bind_point);
1895 }
1896
1897 static void
1898 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1899 VkShaderStageFlags stages)
1900 {
1901 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1902 ? cmd_buffer->state.compute_pipeline
1903 : cmd_buffer->state.pipeline;
1904 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1905 VK_PIPELINE_BIND_POINT_COMPUTE :
1906 VK_PIPELINE_BIND_POINT_GRAPHICS;
1907 struct radv_descriptor_state *descriptors_state =
1908 radv_get_descriptors_state(cmd_buffer, bind_point);
1909 struct radv_pipeline_layout *layout = pipeline->layout;
1910 struct radv_shader_variant *shader, *prev_shader;
1911 unsigned offset;
1912 void *ptr;
1913 uint64_t va;
1914
1915 stages &= cmd_buffer->push_constant_stages;
1916 if (!stages ||
1917 (!layout->push_constant_size && !layout->dynamic_offset_count))
1918 return;
1919
1920 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1921 16 * layout->dynamic_offset_count,
1922 256, &offset, &ptr))
1923 return;
1924
1925 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1926 memcpy((char*)ptr + layout->push_constant_size,
1927 descriptors_state->dynamic_buffers,
1928 16 * layout->dynamic_offset_count);
1929
1930 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1931 va += offset;
1932
1933 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1934 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1935
1936 prev_shader = NULL;
1937 radv_foreach_stage(stage, stages) {
1938 shader = radv_get_shader(pipeline, stage);
1939
1940 /* Avoid redundantly emitting the address for merged stages. */
1941 if (shader && shader != prev_shader) {
1942 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1943 AC_UD_PUSH_CONSTANTS, va);
1944
1945 prev_shader = shader;
1946 }
1947 }
1948
1949 cmd_buffer->push_constant_stages &= ~stages;
1950 assert(cmd_buffer->cs->cdw <= cdw_max);
1951 }
1952
1953 static void
1954 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1955 bool pipeline_is_dirty)
1956 {
1957 if ((pipeline_is_dirty ||
1958 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1959 cmd_buffer->state.pipeline->vertex_elements.count &&
1960 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
1961 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1962 unsigned vb_offset;
1963 void *vb_ptr;
1964 uint32_t i = 0;
1965 uint32_t count = velems->count;
1966 uint64_t va;
1967
1968 /* allocate some descriptor state for vertex buffers */
1969 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1970 &vb_offset, &vb_ptr))
1971 return;
1972
1973 for (i = 0; i < count; i++) {
1974 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1975 uint32_t offset;
1976 int vb = velems->binding[i];
1977 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1978 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1979
1980 va = radv_buffer_get_va(buffer->bo);
1981
1982 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1983 va += offset + buffer->offset;
1984 desc[0] = va;
1985 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1986 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1987 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1988 else
1989 desc[2] = buffer->size - offset;
1990 desc[3] = velems->rsrc_word3[i];
1991 }
1992
1993 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1994 va += vb_offset;
1995
1996 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1997 AC_UD_VS_VERTEX_BUFFERS, va);
1998
1999 cmd_buffer->state.vb_va = va;
2000 cmd_buffer->state.vb_size = count * 16;
2001 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2002 }
2003 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2004 }
2005
2006 static void
2007 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2008 {
2009 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2010 struct radv_userdata_info *loc;
2011 uint32_t base_reg;
2012
2013 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2014 if (!radv_get_shader(pipeline, stage))
2015 continue;
2016
2017 loc = radv_lookup_user_sgpr(pipeline, stage,
2018 AC_UD_STREAMOUT_BUFFERS);
2019 if (loc->sgpr_idx == -1)
2020 continue;
2021
2022 base_reg = pipeline->user_data_0[stage];
2023
2024 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2025 base_reg + loc->sgpr_idx * 4, va, false);
2026 }
2027
2028 if (pipeline->gs_copy_shader) {
2029 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2030 if (loc->sgpr_idx != -1) {
2031 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2032
2033 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2034 base_reg + loc->sgpr_idx * 4, va, false);
2035 }
2036 }
2037 }
2038
2039 static void
2040 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2041 {
2042 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2043 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2044 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2045 unsigned so_offset;
2046 void *so_ptr;
2047 uint64_t va;
2048
2049 /* Allocate some descriptor state for streamout buffers. */
2050 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2051 MAX_SO_BUFFERS * 16, 256,
2052 &so_offset, &so_ptr))
2053 return;
2054
2055 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2056 struct radv_buffer *buffer = sb[i].buffer;
2057 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2058
2059 if (!(so->enabled_mask & (1 << i)))
2060 continue;
2061
2062 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2063
2064 va += sb[i].offset;
2065
2066 /* Set the descriptor.
2067 *
2068 * On VI, the format must be non-INVALID, otherwise
2069 * the buffer will be considered not bound and store
2070 * instructions will be no-ops.
2071 */
2072 desc[0] = va;
2073 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2074 desc[2] = 0xffffffff;
2075 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2076 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2077 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2078 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2079 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2080 }
2081
2082 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2083 va += so_offset;
2084
2085 radv_emit_streamout_buffers(cmd_buffer, va);
2086 }
2087
2088 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2089 }
2090
2091 static void
2092 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2093 {
2094 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2095 radv_flush_streamout_descriptors(cmd_buffer);
2096 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2097 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2098 }
2099
2100 struct radv_draw_info {
2101 /**
2102 * Number of vertices.
2103 */
2104 uint32_t count;
2105
2106 /**
2107 * Index of the first vertex.
2108 */
2109 int32_t vertex_offset;
2110
2111 /**
2112 * First instance id.
2113 */
2114 uint32_t first_instance;
2115
2116 /**
2117 * Number of instances.
2118 */
2119 uint32_t instance_count;
2120
2121 /**
2122 * First index (indexed draws only).
2123 */
2124 uint32_t first_index;
2125
2126 /**
2127 * Whether it's an indexed draw.
2128 */
2129 bool indexed;
2130
2131 /**
2132 * Indirect draw parameters resource.
2133 */
2134 struct radv_buffer *indirect;
2135 uint64_t indirect_offset;
2136 uint32_t stride;
2137
2138 /**
2139 * Draw count parameters resource.
2140 */
2141 struct radv_buffer *count_buffer;
2142 uint64_t count_buffer_offset;
2143
2144 /**
2145 * Stream output parameters resource.
2146 */
2147 struct radv_buffer *strmout_buffer;
2148 uint64_t strmout_buffer_offset;
2149 };
2150
2151 static void
2152 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2153 const struct radv_draw_info *draw_info)
2154 {
2155 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2156 struct radv_cmd_state *state = &cmd_buffer->state;
2157 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2158 uint32_t ia_multi_vgt_param;
2159 int32_t primitive_reset_en;
2160
2161 /* Draw state. */
2162 ia_multi_vgt_param =
2163 si_get_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2164 draw_info->indirect,
2165 draw_info->indirect ? 0 : draw_info->count);
2166
2167 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2168 if (info->chip_class >= GFX9) {
2169 radeon_set_uconfig_reg_idx(cs,
2170 R_030960_IA_MULTI_VGT_PARAM,
2171 4, ia_multi_vgt_param);
2172 } else if (info->chip_class >= CIK) {
2173 radeon_set_context_reg_idx(cs,
2174 R_028AA8_IA_MULTI_VGT_PARAM,
2175 1, ia_multi_vgt_param);
2176 } else {
2177 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2178 ia_multi_vgt_param);
2179 }
2180 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2181 }
2182
2183 /* Primitive restart. */
2184 primitive_reset_en =
2185 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2186
2187 if (primitive_reset_en != state->last_primitive_reset_en) {
2188 state->last_primitive_reset_en = primitive_reset_en;
2189 if (info->chip_class >= GFX9) {
2190 radeon_set_uconfig_reg(cs,
2191 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2192 primitive_reset_en);
2193 } else {
2194 radeon_set_context_reg(cs,
2195 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2196 primitive_reset_en);
2197 }
2198 }
2199
2200 if (primitive_reset_en) {
2201 uint32_t primitive_reset_index =
2202 state->index_type ? 0xffffffffu : 0xffffu;
2203
2204 if (primitive_reset_index != state->last_primitive_reset_index) {
2205 radeon_set_context_reg(cs,
2206 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2207 primitive_reset_index);
2208 state->last_primitive_reset_index = primitive_reset_index;
2209 }
2210 }
2211
2212 if (draw_info->strmout_buffer) {
2213 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2214
2215 va += draw_info->strmout_buffer->offset +
2216 draw_info->strmout_buffer_offset;
2217
2218 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2219 draw_info->stride);
2220
2221 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2222 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2223 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2224 COPY_DATA_WR_CONFIRM);
2225 radeon_emit(cs, va);
2226 radeon_emit(cs, va >> 32);
2227 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2228 radeon_emit(cs, 0); /* unused */
2229
2230 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2231 }
2232 }
2233
2234 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2235 VkPipelineStageFlags src_stage_mask)
2236 {
2237 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2238 VK_PIPELINE_STAGE_TRANSFER_BIT |
2239 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2240 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2241 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2242 }
2243
2244 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2245 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2246 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2247 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2248 VK_PIPELINE_STAGE_TRANSFER_BIT |
2249 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2250 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2251 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2252 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2253 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2254 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2255 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2256 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2257 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2258 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2259 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2260 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2261 }
2262 }
2263
2264 static enum radv_cmd_flush_bits
2265 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2266 VkAccessFlags src_flags,
2267 struct radv_image *image)
2268 {
2269 bool flush_CB_meta = true, flush_DB_meta = true;
2270 enum radv_cmd_flush_bits flush_bits = 0;
2271 uint32_t b;
2272
2273 if (image) {
2274 if (!radv_image_has_CB_metadata(image))
2275 flush_CB_meta = false;
2276 if (!radv_image_has_htile(image))
2277 flush_DB_meta = false;
2278 }
2279
2280 for_each_bit(b, src_flags) {
2281 switch ((VkAccessFlagBits)(1 << b)) {
2282 case VK_ACCESS_SHADER_WRITE_BIT:
2283 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2284 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2285 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2286 break;
2287 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2288 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2289 if (flush_CB_meta)
2290 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2291 break;
2292 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2293 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2294 if (flush_DB_meta)
2295 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2296 break;
2297 case VK_ACCESS_TRANSFER_WRITE_BIT:
2298 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2299 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2300 RADV_CMD_FLAG_INV_GLOBAL_L2;
2301
2302 if (flush_CB_meta)
2303 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2304 if (flush_DB_meta)
2305 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2306 break;
2307 default:
2308 break;
2309 }
2310 }
2311 return flush_bits;
2312 }
2313
2314 static enum radv_cmd_flush_bits
2315 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2316 VkAccessFlags dst_flags,
2317 struct radv_image *image)
2318 {
2319 bool flush_CB_meta = true, flush_DB_meta = true;
2320 enum radv_cmd_flush_bits flush_bits = 0;
2321 bool flush_CB = true, flush_DB = true;
2322 bool image_is_coherent = false;
2323 uint32_t b;
2324
2325 if (image) {
2326 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2327 flush_CB = false;
2328 flush_DB = false;
2329 }
2330
2331 if (!radv_image_has_CB_metadata(image))
2332 flush_CB_meta = false;
2333 if (!radv_image_has_htile(image))
2334 flush_DB_meta = false;
2335
2336 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2337 if (image->info.samples == 1 &&
2338 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2339 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2340 !vk_format_is_stencil(image->vk_format)) {
2341 /* Single-sample color and single-sample depth
2342 * (not stencil) are coherent with shaders on
2343 * GFX9.
2344 */
2345 image_is_coherent = true;
2346 }
2347 }
2348 }
2349
2350 for_each_bit(b, dst_flags) {
2351 switch ((VkAccessFlagBits)(1 << b)) {
2352 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2353 case VK_ACCESS_INDEX_READ_BIT:
2354 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2355 break;
2356 case VK_ACCESS_UNIFORM_READ_BIT:
2357 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2358 break;
2359 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2360 case VK_ACCESS_TRANSFER_READ_BIT:
2361 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2362 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2363 RADV_CMD_FLAG_INV_GLOBAL_L2;
2364 break;
2365 case VK_ACCESS_SHADER_READ_BIT:
2366 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2367
2368 if (!image_is_coherent)
2369 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2370 break;
2371 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2372 if (flush_CB)
2373 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2374 if (flush_CB_meta)
2375 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2376 break;
2377 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2378 if (flush_DB)
2379 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2380 if (flush_DB_meta)
2381 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2382 break;
2383 default:
2384 break;
2385 }
2386 }
2387 return flush_bits;
2388 }
2389
2390 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2391 const struct radv_subpass_barrier *barrier)
2392 {
2393 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2394 NULL);
2395 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2396 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2397 NULL);
2398 }
2399
2400 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2401 struct radv_subpass_attachment att)
2402 {
2403 unsigned idx = att.attachment;
2404 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2405 VkImageSubresourceRange range;
2406 range.aspectMask = 0;
2407 range.baseMipLevel = view->base_mip;
2408 range.levelCount = 1;
2409 range.baseArrayLayer = view->base_layer;
2410 range.layerCount = cmd_buffer->state.framebuffer->layers;
2411
2412 if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask) {
2413 /* If the current subpass uses multiview, the driver might have
2414 * performed a fast color/depth clear to the whole image
2415 * (including all layers). To make sure the driver will
2416 * decompress the image correctly (if needed), we have to
2417 * account for the "real" number of layers. If the view mask is
2418 * sparse, this will decompress more layers than needed.
2419 */
2420 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
2421 }
2422
2423 radv_handle_image_transition(cmd_buffer,
2424 view->image,
2425 cmd_buffer->state.attachments[idx].current_layout,
2426 att.layout, 0, 0, &range);
2427
2428 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2429
2430
2431 }
2432
2433 void
2434 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2435 const struct radv_subpass *subpass, bool transitions)
2436 {
2437 if (transitions) {
2438 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2439
2440 for (unsigned i = 0; i < subpass->color_count; ++i) {
2441 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2442 radv_handle_subpass_image_transition(cmd_buffer,
2443 subpass->color_attachments[i]);
2444 }
2445
2446 for (unsigned i = 0; i < subpass->input_count; ++i) {
2447 radv_handle_subpass_image_transition(cmd_buffer,
2448 subpass->input_attachments[i]);
2449 }
2450
2451 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2452 radv_handle_subpass_image_transition(cmd_buffer,
2453 subpass->depth_stencil_attachment);
2454 }
2455 }
2456
2457 cmd_buffer->state.subpass = subpass;
2458
2459 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2460 }
2461
2462 static VkResult
2463 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2464 struct radv_render_pass *pass,
2465 const VkRenderPassBeginInfo *info)
2466 {
2467 struct radv_cmd_state *state = &cmd_buffer->state;
2468
2469 if (pass->attachment_count == 0) {
2470 state->attachments = NULL;
2471 return VK_SUCCESS;
2472 }
2473
2474 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2475 pass->attachment_count *
2476 sizeof(state->attachments[0]),
2477 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2478 if (state->attachments == NULL) {
2479 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2480 return cmd_buffer->record_result;
2481 }
2482
2483 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2484 struct radv_render_pass_attachment *att = &pass->attachments[i];
2485 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2486 VkImageAspectFlags clear_aspects = 0;
2487
2488 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2489 /* color attachment */
2490 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2491 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2492 }
2493 } else {
2494 /* depthstencil attachment */
2495 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2496 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2497 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2498 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2499 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2500 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2501 }
2502 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2503 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2504 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2505 }
2506 }
2507
2508 state->attachments[i].pending_clear_aspects = clear_aspects;
2509 state->attachments[i].cleared_views = 0;
2510 if (clear_aspects && info) {
2511 assert(info->clearValueCount > i);
2512 state->attachments[i].clear_value = info->pClearValues[i];
2513 }
2514
2515 state->attachments[i].current_layout = att->initial_layout;
2516 }
2517
2518 return VK_SUCCESS;
2519 }
2520
2521 VkResult radv_AllocateCommandBuffers(
2522 VkDevice _device,
2523 const VkCommandBufferAllocateInfo *pAllocateInfo,
2524 VkCommandBuffer *pCommandBuffers)
2525 {
2526 RADV_FROM_HANDLE(radv_device, device, _device);
2527 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2528
2529 VkResult result = VK_SUCCESS;
2530 uint32_t i;
2531
2532 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2533
2534 if (!list_empty(&pool->free_cmd_buffers)) {
2535 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2536
2537 list_del(&cmd_buffer->pool_link);
2538 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2539
2540 result = radv_reset_cmd_buffer(cmd_buffer);
2541 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2542 cmd_buffer->level = pAllocateInfo->level;
2543
2544 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2545 } else {
2546 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2547 &pCommandBuffers[i]);
2548 }
2549 if (result != VK_SUCCESS)
2550 break;
2551 }
2552
2553 if (result != VK_SUCCESS) {
2554 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2555 i, pCommandBuffers);
2556
2557 /* From the Vulkan 1.0.66 spec:
2558 *
2559 * "vkAllocateCommandBuffers can be used to create multiple
2560 * command buffers. If the creation of any of those command
2561 * buffers fails, the implementation must destroy all
2562 * successfully created command buffer objects from this
2563 * command, set all entries of the pCommandBuffers array to
2564 * NULL and return the error."
2565 */
2566 memset(pCommandBuffers, 0,
2567 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2568 }
2569
2570 return result;
2571 }
2572
2573 void radv_FreeCommandBuffers(
2574 VkDevice device,
2575 VkCommandPool commandPool,
2576 uint32_t commandBufferCount,
2577 const VkCommandBuffer *pCommandBuffers)
2578 {
2579 for (uint32_t i = 0; i < commandBufferCount; i++) {
2580 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2581
2582 if (cmd_buffer) {
2583 if (cmd_buffer->pool) {
2584 list_del(&cmd_buffer->pool_link);
2585 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2586 } else
2587 radv_cmd_buffer_destroy(cmd_buffer);
2588
2589 }
2590 }
2591 }
2592
2593 VkResult radv_ResetCommandBuffer(
2594 VkCommandBuffer commandBuffer,
2595 VkCommandBufferResetFlags flags)
2596 {
2597 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2598 return radv_reset_cmd_buffer(cmd_buffer);
2599 }
2600
2601 VkResult radv_BeginCommandBuffer(
2602 VkCommandBuffer commandBuffer,
2603 const VkCommandBufferBeginInfo *pBeginInfo)
2604 {
2605 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2606 VkResult result = VK_SUCCESS;
2607
2608 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2609 /* If the command buffer has already been resetted with
2610 * vkResetCommandBuffer, no need to do it again.
2611 */
2612 result = radv_reset_cmd_buffer(cmd_buffer);
2613 if (result != VK_SUCCESS)
2614 return result;
2615 }
2616
2617 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2618 cmd_buffer->state.last_primitive_reset_en = -1;
2619 cmd_buffer->state.last_index_type = -1;
2620 cmd_buffer->state.last_num_instances = -1;
2621 cmd_buffer->state.last_vertex_offset = -1;
2622 cmd_buffer->state.last_first_instance = -1;
2623 cmd_buffer->state.predication_type = -1;
2624 cmd_buffer->usage_flags = pBeginInfo->flags;
2625
2626 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
2627 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
2628 assert(pBeginInfo->pInheritanceInfo);
2629 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2630 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2631
2632 struct radv_subpass *subpass =
2633 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2634
2635 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2636 if (result != VK_SUCCESS)
2637 return result;
2638
2639 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2640 }
2641
2642 if (unlikely(cmd_buffer->device->trace_bo)) {
2643 struct radv_device *device = cmd_buffer->device;
2644
2645 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
2646 device->trace_bo);
2647
2648 radv_cmd_buffer_trace_emit(cmd_buffer);
2649 }
2650
2651 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2652
2653 return result;
2654 }
2655
2656 void radv_CmdBindVertexBuffers(
2657 VkCommandBuffer commandBuffer,
2658 uint32_t firstBinding,
2659 uint32_t bindingCount,
2660 const VkBuffer* pBuffers,
2661 const VkDeviceSize* pOffsets)
2662 {
2663 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2664 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2665 bool changed = false;
2666
2667 /* We have to defer setting up vertex buffer since we need the buffer
2668 * stride from the pipeline. */
2669
2670 assert(firstBinding + bindingCount <= MAX_VBS);
2671 for (uint32_t i = 0; i < bindingCount; i++) {
2672 uint32_t idx = firstBinding + i;
2673
2674 if (!changed &&
2675 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2676 vb[idx].offset != pOffsets[i])) {
2677 changed = true;
2678 }
2679
2680 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2681 vb[idx].offset = pOffsets[i];
2682
2683 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2684 vb[idx].buffer->bo);
2685 }
2686
2687 if (!changed) {
2688 /* No state changes. */
2689 return;
2690 }
2691
2692 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2693 }
2694
2695 void radv_CmdBindIndexBuffer(
2696 VkCommandBuffer commandBuffer,
2697 VkBuffer buffer,
2698 VkDeviceSize offset,
2699 VkIndexType indexType)
2700 {
2701 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2702 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2703
2704 if (cmd_buffer->state.index_buffer == index_buffer &&
2705 cmd_buffer->state.index_offset == offset &&
2706 cmd_buffer->state.index_type == indexType) {
2707 /* No state changes. */
2708 return;
2709 }
2710
2711 cmd_buffer->state.index_buffer = index_buffer;
2712 cmd_buffer->state.index_offset = offset;
2713 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2714 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2715 cmd_buffer->state.index_va += index_buffer->offset + offset;
2716
2717 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2718 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2719 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2720 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
2721 }
2722
2723
2724 static void
2725 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2726 VkPipelineBindPoint bind_point,
2727 struct radv_descriptor_set *set, unsigned idx)
2728 {
2729 struct radeon_winsys *ws = cmd_buffer->device->ws;
2730
2731 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2732
2733 assert(set);
2734 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2735
2736 if (!cmd_buffer->device->use_global_bo_list) {
2737 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2738 if (set->descriptors[j])
2739 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
2740 }
2741
2742 if(set->bo)
2743 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
2744 }
2745
2746 void radv_CmdBindDescriptorSets(
2747 VkCommandBuffer commandBuffer,
2748 VkPipelineBindPoint pipelineBindPoint,
2749 VkPipelineLayout _layout,
2750 uint32_t firstSet,
2751 uint32_t descriptorSetCount,
2752 const VkDescriptorSet* pDescriptorSets,
2753 uint32_t dynamicOffsetCount,
2754 const uint32_t* pDynamicOffsets)
2755 {
2756 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2757 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2758 unsigned dyn_idx = 0;
2759
2760 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2761 struct radv_descriptor_state *descriptors_state =
2762 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2763
2764 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2765 unsigned idx = i + firstSet;
2766 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2767 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2768
2769 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2770 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2771 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
2772 assert(dyn_idx < dynamicOffsetCount);
2773
2774 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2775 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2776 dst[0] = va;
2777 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2778 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2779 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2780 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2781 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2782 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2783 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2784 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2785 cmd_buffer->push_constant_stages |=
2786 set->layout->dynamic_shader_stages;
2787 }
2788 }
2789 }
2790
2791 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2792 struct radv_descriptor_set *set,
2793 struct radv_descriptor_set_layout *layout,
2794 VkPipelineBindPoint bind_point)
2795 {
2796 struct radv_descriptor_state *descriptors_state =
2797 radv_get_descriptors_state(cmd_buffer, bind_point);
2798 set->size = layout->size;
2799 set->layout = layout;
2800
2801 if (descriptors_state->push_set.capacity < set->size) {
2802 size_t new_size = MAX2(set->size, 1024);
2803 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2804 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2805
2806 free(set->mapped_ptr);
2807 set->mapped_ptr = malloc(new_size);
2808
2809 if (!set->mapped_ptr) {
2810 descriptors_state->push_set.capacity = 0;
2811 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2812 return false;
2813 }
2814
2815 descriptors_state->push_set.capacity = new_size;
2816 }
2817
2818 return true;
2819 }
2820
2821 void radv_meta_push_descriptor_set(
2822 struct radv_cmd_buffer* cmd_buffer,
2823 VkPipelineBindPoint pipelineBindPoint,
2824 VkPipelineLayout _layout,
2825 uint32_t set,
2826 uint32_t descriptorWriteCount,
2827 const VkWriteDescriptorSet* pDescriptorWrites)
2828 {
2829 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2830 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2831 unsigned bo_offset;
2832
2833 assert(set == 0);
2834 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2835
2836 push_set->size = layout->set[set].layout->size;
2837 push_set->layout = layout->set[set].layout;
2838
2839 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2840 &bo_offset,
2841 (void**) &push_set->mapped_ptr))
2842 return;
2843
2844 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2845 push_set->va += bo_offset;
2846
2847 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2848 radv_descriptor_set_to_handle(push_set),
2849 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2850
2851 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2852 }
2853
2854 void radv_CmdPushDescriptorSetKHR(
2855 VkCommandBuffer commandBuffer,
2856 VkPipelineBindPoint pipelineBindPoint,
2857 VkPipelineLayout _layout,
2858 uint32_t set,
2859 uint32_t descriptorWriteCount,
2860 const VkWriteDescriptorSet* pDescriptorWrites)
2861 {
2862 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2863 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2864 struct radv_descriptor_state *descriptors_state =
2865 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2866 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2867
2868 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2869
2870 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2871 layout->set[set].layout,
2872 pipelineBindPoint))
2873 return;
2874
2875 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2876 radv_descriptor_set_to_handle(push_set),
2877 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2878
2879 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2880 descriptors_state->push_dirty = true;
2881 }
2882
2883 void radv_CmdPushDescriptorSetWithTemplateKHR(
2884 VkCommandBuffer commandBuffer,
2885 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
2886 VkPipelineLayout _layout,
2887 uint32_t set,
2888 const void* pData)
2889 {
2890 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2891 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2892 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2893 struct radv_descriptor_state *descriptors_state =
2894 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2895 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2896
2897 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2898
2899 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2900 layout->set[set].layout,
2901 templ->bind_point))
2902 return;
2903
2904 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2905 descriptorUpdateTemplate, pData);
2906
2907 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2908 descriptors_state->push_dirty = true;
2909 }
2910
2911 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2912 VkPipelineLayout layout,
2913 VkShaderStageFlags stageFlags,
2914 uint32_t offset,
2915 uint32_t size,
2916 const void* pValues)
2917 {
2918 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2919 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2920 cmd_buffer->push_constant_stages |= stageFlags;
2921 }
2922
2923 VkResult radv_EndCommandBuffer(
2924 VkCommandBuffer commandBuffer)
2925 {
2926 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2927
2928 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2929 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2930 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2931 si_emit_cache_flush(cmd_buffer);
2932 }
2933
2934 /* Make sure CP DMA is idle at the end of IBs because the kernel
2935 * doesn't wait for it.
2936 */
2937 si_cp_dma_wait_for_idle(cmd_buffer);
2938
2939 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2940
2941 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2942 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2943
2944 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2945
2946 return cmd_buffer->record_result;
2947 }
2948
2949 static void
2950 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2951 {
2952 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2953
2954 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2955 return;
2956
2957 assert(!pipeline->ctx_cs.cdw);
2958
2959 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2960
2961 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2962 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2963
2964 cmd_buffer->compute_scratch_size_needed =
2965 MAX2(cmd_buffer->compute_scratch_size_needed,
2966 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2967
2968 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2969 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
2970
2971 if (unlikely(cmd_buffer->device->trace_bo))
2972 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2973 }
2974
2975 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2976 VkPipelineBindPoint bind_point)
2977 {
2978 struct radv_descriptor_state *descriptors_state =
2979 radv_get_descriptors_state(cmd_buffer, bind_point);
2980
2981 descriptors_state->dirty |= descriptors_state->valid;
2982 }
2983
2984 void radv_CmdBindPipeline(
2985 VkCommandBuffer commandBuffer,
2986 VkPipelineBindPoint pipelineBindPoint,
2987 VkPipeline _pipeline)
2988 {
2989 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2990 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2991
2992 switch (pipelineBindPoint) {
2993 case VK_PIPELINE_BIND_POINT_COMPUTE:
2994 if (cmd_buffer->state.compute_pipeline == pipeline)
2995 return;
2996 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2997
2998 cmd_buffer->state.compute_pipeline = pipeline;
2999 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3000 break;
3001 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3002 if (cmd_buffer->state.pipeline == pipeline)
3003 return;
3004 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3005
3006 cmd_buffer->state.pipeline = pipeline;
3007 if (!pipeline)
3008 break;
3009
3010 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3011 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3012
3013 /* the new vertex shader might not have the same user regs */
3014 cmd_buffer->state.last_first_instance = -1;
3015 cmd_buffer->state.last_vertex_offset = -1;
3016
3017 /* Prefetch all pipeline shaders at first draw time. */
3018 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3019
3020 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3021 radv_bind_streamout_state(cmd_buffer, pipeline);
3022
3023 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3024 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3025 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3026 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3027
3028 if (radv_pipeline_has_tess(pipeline))
3029 cmd_buffer->tess_rings_needed = true;
3030 break;
3031 default:
3032 assert(!"invalid bind point");
3033 break;
3034 }
3035 }
3036
3037 void radv_CmdSetViewport(
3038 VkCommandBuffer commandBuffer,
3039 uint32_t firstViewport,
3040 uint32_t viewportCount,
3041 const VkViewport* pViewports)
3042 {
3043 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3044 struct radv_cmd_state *state = &cmd_buffer->state;
3045 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
3046
3047 assert(firstViewport < MAX_VIEWPORTS);
3048 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3049
3050 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3051 pViewports, viewportCount * sizeof(*pViewports))) {
3052 return;
3053 }
3054
3055 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3056 viewportCount * sizeof(*pViewports));
3057
3058 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3059 }
3060
3061 void radv_CmdSetScissor(
3062 VkCommandBuffer commandBuffer,
3063 uint32_t firstScissor,
3064 uint32_t scissorCount,
3065 const VkRect2D* pScissors)
3066 {
3067 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3068 struct radv_cmd_state *state = &cmd_buffer->state;
3069 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
3070
3071 assert(firstScissor < MAX_SCISSORS);
3072 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3073
3074 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3075 scissorCount * sizeof(*pScissors))) {
3076 return;
3077 }
3078
3079 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3080 scissorCount * sizeof(*pScissors));
3081
3082 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3083 }
3084
3085 void radv_CmdSetLineWidth(
3086 VkCommandBuffer commandBuffer,
3087 float lineWidth)
3088 {
3089 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3090
3091 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3092 return;
3093
3094 cmd_buffer->state.dynamic.line_width = lineWidth;
3095 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3096 }
3097
3098 void radv_CmdSetDepthBias(
3099 VkCommandBuffer commandBuffer,
3100 float depthBiasConstantFactor,
3101 float depthBiasClamp,
3102 float depthBiasSlopeFactor)
3103 {
3104 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3105 struct radv_cmd_state *state = &cmd_buffer->state;
3106
3107 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3108 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3109 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3110 return;
3111 }
3112
3113 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3114 state->dynamic.depth_bias.clamp = depthBiasClamp;
3115 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3116
3117 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3118 }
3119
3120 void radv_CmdSetBlendConstants(
3121 VkCommandBuffer commandBuffer,
3122 const float blendConstants[4])
3123 {
3124 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3125 struct radv_cmd_state *state = &cmd_buffer->state;
3126
3127 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3128 return;
3129
3130 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
3131
3132 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3133 }
3134
3135 void radv_CmdSetDepthBounds(
3136 VkCommandBuffer commandBuffer,
3137 float minDepthBounds,
3138 float maxDepthBounds)
3139 {
3140 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3141 struct radv_cmd_state *state = &cmd_buffer->state;
3142
3143 if (state->dynamic.depth_bounds.min == minDepthBounds &&
3144 state->dynamic.depth_bounds.max == maxDepthBounds) {
3145 return;
3146 }
3147
3148 state->dynamic.depth_bounds.min = minDepthBounds;
3149 state->dynamic.depth_bounds.max = maxDepthBounds;
3150
3151 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
3152 }
3153
3154 void radv_CmdSetStencilCompareMask(
3155 VkCommandBuffer commandBuffer,
3156 VkStencilFaceFlags faceMask,
3157 uint32_t compareMask)
3158 {
3159 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3160 struct radv_cmd_state *state = &cmd_buffer->state;
3161 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
3162 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
3163
3164 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3165 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3166 return;
3167 }
3168
3169 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3170 state->dynamic.stencil_compare_mask.front = compareMask;
3171 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3172 state->dynamic.stencil_compare_mask.back = compareMask;
3173
3174 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
3175 }
3176
3177 void radv_CmdSetStencilWriteMask(
3178 VkCommandBuffer commandBuffer,
3179 VkStencilFaceFlags faceMask,
3180 uint32_t writeMask)
3181 {
3182 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3183 struct radv_cmd_state *state = &cmd_buffer->state;
3184 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
3185 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
3186
3187 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3188 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3189 return;
3190 }
3191
3192 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3193 state->dynamic.stencil_write_mask.front = writeMask;
3194 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3195 state->dynamic.stencil_write_mask.back = writeMask;
3196
3197 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
3198 }
3199
3200 void radv_CmdSetStencilReference(
3201 VkCommandBuffer commandBuffer,
3202 VkStencilFaceFlags faceMask,
3203 uint32_t reference)
3204 {
3205 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3206 struct radv_cmd_state *state = &cmd_buffer->state;
3207 bool front_same = state->dynamic.stencil_reference.front == reference;
3208 bool back_same = state->dynamic.stencil_reference.back == reference;
3209
3210 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3211 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3212 return;
3213 }
3214
3215 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3216 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3217 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3218 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3219
3220 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3221 }
3222
3223 void radv_CmdSetDiscardRectangleEXT(
3224 VkCommandBuffer commandBuffer,
3225 uint32_t firstDiscardRectangle,
3226 uint32_t discardRectangleCount,
3227 const VkRect2D* pDiscardRectangles)
3228 {
3229 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3230 struct radv_cmd_state *state = &cmd_buffer->state;
3231 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3232
3233 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3234 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3235
3236 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
3237 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
3238 return;
3239 }
3240
3241 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3242 pDiscardRectangles, discardRectangleCount);
3243
3244 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3245 }
3246
3247 void radv_CmdExecuteCommands(
3248 VkCommandBuffer commandBuffer,
3249 uint32_t commandBufferCount,
3250 const VkCommandBuffer* pCmdBuffers)
3251 {
3252 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3253
3254 assert(commandBufferCount > 0);
3255
3256 /* Emit pending flushes on primary prior to executing secondary */
3257 si_emit_cache_flush(primary);
3258
3259 for (uint32_t i = 0; i < commandBufferCount; i++) {
3260 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3261
3262 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3263 secondary->scratch_size_needed);
3264 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3265 secondary->compute_scratch_size_needed);
3266
3267 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
3268 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
3269 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
3270 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
3271 if (secondary->tess_rings_needed)
3272 primary->tess_rings_needed = true;
3273 if (secondary->sample_positions_needed)
3274 primary->sample_positions_needed = true;
3275
3276 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
3277
3278
3279 /* When the secondary command buffer is compute only we don't
3280 * need to re-emit the current graphics pipeline.
3281 */
3282 if (secondary->state.emitted_pipeline) {
3283 primary->state.emitted_pipeline =
3284 secondary->state.emitted_pipeline;
3285 }
3286
3287 /* When the secondary command buffer is graphics only we don't
3288 * need to re-emit the current compute pipeline.
3289 */
3290 if (secondary->state.emitted_compute_pipeline) {
3291 primary->state.emitted_compute_pipeline =
3292 secondary->state.emitted_compute_pipeline;
3293 }
3294
3295 /* Only re-emit the draw packets when needed. */
3296 if (secondary->state.last_primitive_reset_en != -1) {
3297 primary->state.last_primitive_reset_en =
3298 secondary->state.last_primitive_reset_en;
3299 }
3300
3301 if (secondary->state.last_primitive_reset_index) {
3302 primary->state.last_primitive_reset_index =
3303 secondary->state.last_primitive_reset_index;
3304 }
3305
3306 if (secondary->state.last_ia_multi_vgt_param) {
3307 primary->state.last_ia_multi_vgt_param =
3308 secondary->state.last_ia_multi_vgt_param;
3309 }
3310
3311 primary->state.last_first_instance = secondary->state.last_first_instance;
3312 primary->state.last_num_instances = secondary->state.last_num_instances;
3313 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
3314
3315 if (secondary->state.last_index_type != -1) {
3316 primary->state.last_index_type =
3317 secondary->state.last_index_type;
3318 }
3319 }
3320
3321 /* After executing commands from secondary buffers we have to dirty
3322 * some states.
3323 */
3324 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
3325 RADV_CMD_DIRTY_INDEX_BUFFER |
3326 RADV_CMD_DIRTY_DYNAMIC_ALL;
3327 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
3328 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
3329 }
3330
3331 VkResult radv_CreateCommandPool(
3332 VkDevice _device,
3333 const VkCommandPoolCreateInfo* pCreateInfo,
3334 const VkAllocationCallbacks* pAllocator,
3335 VkCommandPool* pCmdPool)
3336 {
3337 RADV_FROM_HANDLE(radv_device, device, _device);
3338 struct radv_cmd_pool *pool;
3339
3340 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3341 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3342 if (pool == NULL)
3343 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3344
3345 if (pAllocator)
3346 pool->alloc = *pAllocator;
3347 else
3348 pool->alloc = device->alloc;
3349
3350 list_inithead(&pool->cmd_buffers);
3351 list_inithead(&pool->free_cmd_buffers);
3352
3353 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3354
3355 *pCmdPool = radv_cmd_pool_to_handle(pool);
3356
3357 return VK_SUCCESS;
3358
3359 }
3360
3361 void radv_DestroyCommandPool(
3362 VkDevice _device,
3363 VkCommandPool commandPool,
3364 const VkAllocationCallbacks* pAllocator)
3365 {
3366 RADV_FROM_HANDLE(radv_device, device, _device);
3367 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3368
3369 if (!pool)
3370 return;
3371
3372 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3373 &pool->cmd_buffers, pool_link) {
3374 radv_cmd_buffer_destroy(cmd_buffer);
3375 }
3376
3377 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3378 &pool->free_cmd_buffers, pool_link) {
3379 radv_cmd_buffer_destroy(cmd_buffer);
3380 }
3381
3382 vk_free2(&device->alloc, pAllocator, pool);
3383 }
3384
3385 VkResult radv_ResetCommandPool(
3386 VkDevice device,
3387 VkCommandPool commandPool,
3388 VkCommandPoolResetFlags flags)
3389 {
3390 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3391 VkResult result;
3392
3393 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3394 &pool->cmd_buffers, pool_link) {
3395 result = radv_reset_cmd_buffer(cmd_buffer);
3396 if (result != VK_SUCCESS)
3397 return result;
3398 }
3399
3400 return VK_SUCCESS;
3401 }
3402
3403 void radv_TrimCommandPool(
3404 VkDevice device,
3405 VkCommandPool commandPool,
3406 VkCommandPoolTrimFlags flags)
3407 {
3408 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3409
3410 if (!pool)
3411 return;
3412
3413 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3414 &pool->free_cmd_buffers, pool_link) {
3415 radv_cmd_buffer_destroy(cmd_buffer);
3416 }
3417 }
3418
3419 void radv_CmdBeginRenderPass(
3420 VkCommandBuffer commandBuffer,
3421 const VkRenderPassBeginInfo* pRenderPassBegin,
3422 VkSubpassContents contents)
3423 {
3424 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3425 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3426 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3427
3428 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3429 cmd_buffer->cs, 2048);
3430 MAYBE_UNUSED VkResult result;
3431
3432 cmd_buffer->state.framebuffer = framebuffer;
3433 cmd_buffer->state.pass = pass;
3434 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3435
3436 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3437 if (result != VK_SUCCESS)
3438 return;
3439
3440 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
3441 assert(cmd_buffer->cs->cdw <= cdw_max);
3442
3443 radv_cmd_buffer_clear_subpass(cmd_buffer);
3444 }
3445
3446 void radv_CmdBeginRenderPass2KHR(
3447 VkCommandBuffer commandBuffer,
3448 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
3449 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
3450 {
3451 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
3452 pSubpassBeginInfo->contents);
3453 }
3454
3455 void radv_CmdNextSubpass(
3456 VkCommandBuffer commandBuffer,
3457 VkSubpassContents contents)
3458 {
3459 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3460
3461 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3462
3463 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
3464 2048);
3465
3466 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
3467 radv_cmd_buffer_clear_subpass(cmd_buffer);
3468 }
3469
3470 void radv_CmdNextSubpass2KHR(
3471 VkCommandBuffer commandBuffer,
3472 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
3473 const VkSubpassEndInfoKHR* pSubpassEndInfo)
3474 {
3475 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
3476 }
3477
3478 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3479 {
3480 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3481 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3482 if (!radv_get_shader(pipeline, stage))
3483 continue;
3484
3485 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3486 if (loc->sgpr_idx == -1)
3487 continue;
3488 uint32_t base_reg = pipeline->user_data_0[stage];
3489 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3490
3491 }
3492 if (pipeline->gs_copy_shader) {
3493 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3494 if (loc->sgpr_idx != -1) {
3495 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3496 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3497 }
3498 }
3499 }
3500
3501 static void
3502 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3503 uint32_t vertex_count,
3504 bool use_opaque)
3505 {
3506 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3507 radeon_emit(cmd_buffer->cs, vertex_count);
3508 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3509 S_0287F0_USE_OPAQUE(use_opaque));
3510 }
3511
3512 static void
3513 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3514 uint64_t index_va,
3515 uint32_t index_count)
3516 {
3517 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
3518 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3519 radeon_emit(cmd_buffer->cs, index_va);
3520 radeon_emit(cmd_buffer->cs, index_va >> 32);
3521 radeon_emit(cmd_buffer->cs, index_count);
3522 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3523 }
3524
3525 static void
3526 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3527 bool indexed,
3528 uint32_t draw_count,
3529 uint64_t count_va,
3530 uint32_t stride)
3531 {
3532 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3533 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3534 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3535 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
3536 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3537 bool predicating = cmd_buffer->state.predicating;
3538 assert(base_reg);
3539
3540 /* just reset draw state for vertex data */
3541 cmd_buffer->state.last_first_instance = -1;
3542 cmd_buffer->state.last_num_instances = -1;
3543 cmd_buffer->state.last_vertex_offset = -1;
3544
3545 if (draw_count == 1 && !count_va && !draw_id_enable) {
3546 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3547 PKT3_DRAW_INDIRECT, 3, predicating));
3548 radeon_emit(cs, 0);
3549 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3550 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3551 radeon_emit(cs, di_src_sel);
3552 } else {
3553 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3554 PKT3_DRAW_INDIRECT_MULTI,
3555 8, predicating));
3556 radeon_emit(cs, 0);
3557 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3558 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3559 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3560 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3561 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3562 radeon_emit(cs, draw_count); /* count */
3563 radeon_emit(cs, count_va); /* count_addr */
3564 radeon_emit(cs, count_va >> 32);
3565 radeon_emit(cs, stride); /* stride */
3566 radeon_emit(cs, di_src_sel);
3567 }
3568 }
3569
3570 static void
3571 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3572 const struct radv_draw_info *info)
3573 {
3574 struct radv_cmd_state *state = &cmd_buffer->state;
3575 struct radeon_winsys *ws = cmd_buffer->device->ws;
3576 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3577
3578 if (info->indirect) {
3579 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3580 uint64_t count_va = 0;
3581
3582 va += info->indirect->offset + info->indirect_offset;
3583
3584 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3585
3586 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3587 radeon_emit(cs, 1);
3588 radeon_emit(cs, va);
3589 radeon_emit(cs, va >> 32);
3590
3591 if (info->count_buffer) {
3592 count_va = radv_buffer_get_va(info->count_buffer->bo);
3593 count_va += info->count_buffer->offset +
3594 info->count_buffer_offset;
3595
3596 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
3597 }
3598
3599 if (!state->subpass->view_mask) {
3600 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3601 info->indexed,
3602 info->count,
3603 count_va,
3604 info->stride);
3605 } else {
3606 unsigned i;
3607 for_each_bit(i, state->subpass->view_mask) {
3608 radv_emit_view_index(cmd_buffer, i);
3609
3610 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3611 info->indexed,
3612 info->count,
3613 count_va,
3614 info->stride);
3615 }
3616 }
3617 } else {
3618 assert(state->pipeline->graphics.vtx_base_sgpr);
3619
3620 if (info->vertex_offset != state->last_vertex_offset ||
3621 info->first_instance != state->last_first_instance) {
3622 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3623 state->pipeline->graphics.vtx_emit_num);
3624
3625 radeon_emit(cs, info->vertex_offset);
3626 radeon_emit(cs, info->first_instance);
3627 if (state->pipeline->graphics.vtx_emit_num == 3)
3628 radeon_emit(cs, 0);
3629 state->last_first_instance = info->first_instance;
3630 state->last_vertex_offset = info->vertex_offset;
3631 }
3632
3633 if (state->last_num_instances != info->instance_count) {
3634 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3635 radeon_emit(cs, info->instance_count);
3636 state->last_num_instances = info->instance_count;
3637 }
3638
3639 if (info->indexed) {
3640 int index_size = state->index_type ? 4 : 2;
3641 uint64_t index_va;
3642
3643 index_va = state->index_va;
3644 index_va += info->first_index * index_size;
3645
3646 if (!state->subpass->view_mask) {
3647 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3648 index_va,
3649 info->count);
3650 } else {
3651 unsigned i;
3652 for_each_bit(i, state->subpass->view_mask) {
3653 radv_emit_view_index(cmd_buffer, i);
3654
3655 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3656 index_va,
3657 info->count);
3658 }
3659 }
3660 } else {
3661 if (!state->subpass->view_mask) {
3662 radv_cs_emit_draw_packet(cmd_buffer,
3663 info->count,
3664 !!info->strmout_buffer);
3665 } else {
3666 unsigned i;
3667 for_each_bit(i, state->subpass->view_mask) {
3668 radv_emit_view_index(cmd_buffer, i);
3669
3670 radv_cs_emit_draw_packet(cmd_buffer,
3671 info->count,
3672 !!info->strmout_buffer);
3673 }
3674 }
3675 }
3676 }
3677 }
3678
3679 /*
3680 * Vega and raven have a bug which triggers if there are multiple context
3681 * register contexts active at the same time with different scissor values.
3682 *
3683 * There are two possible workarounds:
3684 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3685 * there is only ever 1 active set of scissor values at the same time.
3686 *
3687 * 2) Whenever the hardware switches contexts we have to set the scissor
3688 * registers again even if it is a noop. That way the new context gets
3689 * the correct scissor values.
3690 *
3691 * This implements option 2. radv_need_late_scissor_emission needs to
3692 * return true on affected HW if radv_emit_all_graphics_states sets
3693 * any context registers.
3694 */
3695 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
3696 const struct radv_draw_info *info)
3697 {
3698 struct radv_cmd_state *state = &cmd_buffer->state;
3699
3700 if (!cmd_buffer->device->physical_device->has_scissor_bug)
3701 return false;
3702
3703 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
3704 return true;
3705
3706 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
3707
3708 /* Index, vertex and streamout buffers don't change context regs, and
3709 * pipeline is already handled.
3710 */
3711 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
3712 RADV_CMD_DIRTY_VERTEX_BUFFER |
3713 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
3714 RADV_CMD_DIRTY_PIPELINE);
3715
3716 if (cmd_buffer->state.dirty & used_states)
3717 return true;
3718
3719 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
3720 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
3721 return true;
3722
3723 return false;
3724 }
3725
3726 static void
3727 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3728 const struct radv_draw_info *info)
3729 {
3730 bool late_scissor_emission;
3731
3732 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3733 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3734 radv_emit_rbplus_state(cmd_buffer);
3735
3736 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3737 radv_emit_graphics_pipeline(cmd_buffer);
3738
3739 /* This should be before the cmd_buffer->state.dirty is cleared
3740 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
3741 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
3742 late_scissor_emission =
3743 radv_need_late_scissor_emission(cmd_buffer, info);
3744
3745 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3746 radv_emit_framebuffer_state(cmd_buffer);
3747
3748 if (info->indexed) {
3749 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3750 radv_emit_index_buffer(cmd_buffer);
3751 } else {
3752 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3753 * so the state must be re-emitted before the next indexed
3754 * draw.
3755 */
3756 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3757 cmd_buffer->state.last_index_type = -1;
3758 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3759 }
3760 }
3761
3762 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3763
3764 radv_emit_draw_registers(cmd_buffer, info);
3765
3766 if (late_scissor_emission)
3767 radv_emit_scissor(cmd_buffer);
3768 }
3769
3770 static void
3771 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3772 const struct radv_draw_info *info)
3773 {
3774 struct radeon_info *rad_info =
3775 &cmd_buffer->device->physical_device->rad_info;
3776 bool has_prefetch =
3777 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3778 bool pipeline_is_dirty =
3779 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3780 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3781
3782 MAYBE_UNUSED unsigned cdw_max =
3783 radeon_check_space(cmd_buffer->device->ws,
3784 cmd_buffer->cs, 4096);
3785
3786 if (likely(!info->indirect)) {
3787 /* SI-CI treat instance_count==0 as instance_count==1. There is
3788 * no workaround for indirect draws, but we can at least skip
3789 * direct draws.
3790 */
3791 if (unlikely(!info->instance_count))
3792 return;
3793
3794 /* Handle count == 0. */
3795 if (unlikely(!info->count && !info->strmout_buffer))
3796 return;
3797 }
3798
3799 /* Use optimal packet order based on whether we need to sync the
3800 * pipeline.
3801 */
3802 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3803 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3804 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3805 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3806 /* If we have to wait for idle, set all states first, so that
3807 * all SET packets are processed in parallel with previous draw
3808 * calls. Then upload descriptors, set shader pointers, and
3809 * draw, and prefetch at the end. This ensures that the time
3810 * the CUs are idle is very short. (there are only SET_SH
3811 * packets between the wait and the draw)
3812 */
3813 radv_emit_all_graphics_states(cmd_buffer, info);
3814 si_emit_cache_flush(cmd_buffer);
3815 /* <-- CUs are idle here --> */
3816
3817 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3818
3819 radv_emit_draw_packets(cmd_buffer, info);
3820 /* <-- CUs are busy here --> */
3821
3822 /* Start prefetches after the draw has been started. Both will
3823 * run in parallel, but starting the draw first is more
3824 * important.
3825 */
3826 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3827 radv_emit_prefetch_L2(cmd_buffer,
3828 cmd_buffer->state.pipeline, false);
3829 }
3830 } else {
3831 /* If we don't wait for idle, start prefetches first, then set
3832 * states, and draw at the end.
3833 */
3834 si_emit_cache_flush(cmd_buffer);
3835
3836 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3837 /* Only prefetch the vertex shader and VBO descriptors
3838 * in order to start the draw as soon as possible.
3839 */
3840 radv_emit_prefetch_L2(cmd_buffer,
3841 cmd_buffer->state.pipeline, true);
3842 }
3843
3844 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3845
3846 radv_emit_all_graphics_states(cmd_buffer, info);
3847 radv_emit_draw_packets(cmd_buffer, info);
3848
3849 /* Prefetch the remaining shaders after the draw has been
3850 * started.
3851 */
3852 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3853 radv_emit_prefetch_L2(cmd_buffer,
3854 cmd_buffer->state.pipeline, false);
3855 }
3856 }
3857
3858 /* Workaround for a VGT hang when streamout is enabled.
3859 * It must be done after drawing.
3860 */
3861 if (cmd_buffer->state.streamout.streamout_enabled &&
3862 (rad_info->family == CHIP_HAWAII ||
3863 rad_info->family == CHIP_TONGA ||
3864 rad_info->family == CHIP_FIJI)) {
3865 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
3866 }
3867
3868 assert(cmd_buffer->cs->cdw <= cdw_max);
3869 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3870 }
3871
3872 void radv_CmdDraw(
3873 VkCommandBuffer commandBuffer,
3874 uint32_t vertexCount,
3875 uint32_t instanceCount,
3876 uint32_t firstVertex,
3877 uint32_t firstInstance)
3878 {
3879 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3880 struct radv_draw_info info = {};
3881
3882 info.count = vertexCount;
3883 info.instance_count = instanceCount;
3884 info.first_instance = firstInstance;
3885 info.vertex_offset = firstVertex;
3886
3887 radv_draw(cmd_buffer, &info);
3888 }
3889
3890 void radv_CmdDrawIndexed(
3891 VkCommandBuffer commandBuffer,
3892 uint32_t indexCount,
3893 uint32_t instanceCount,
3894 uint32_t firstIndex,
3895 int32_t vertexOffset,
3896 uint32_t firstInstance)
3897 {
3898 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3899 struct radv_draw_info info = {};
3900
3901 info.indexed = true;
3902 info.count = indexCount;
3903 info.instance_count = instanceCount;
3904 info.first_index = firstIndex;
3905 info.vertex_offset = vertexOffset;
3906 info.first_instance = firstInstance;
3907
3908 radv_draw(cmd_buffer, &info);
3909 }
3910
3911 void radv_CmdDrawIndirect(
3912 VkCommandBuffer commandBuffer,
3913 VkBuffer _buffer,
3914 VkDeviceSize offset,
3915 uint32_t drawCount,
3916 uint32_t stride)
3917 {
3918 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3919 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3920 struct radv_draw_info info = {};
3921
3922 info.count = drawCount;
3923 info.indirect = buffer;
3924 info.indirect_offset = offset;
3925 info.stride = stride;
3926
3927 radv_draw(cmd_buffer, &info);
3928 }
3929
3930 void radv_CmdDrawIndexedIndirect(
3931 VkCommandBuffer commandBuffer,
3932 VkBuffer _buffer,
3933 VkDeviceSize offset,
3934 uint32_t drawCount,
3935 uint32_t stride)
3936 {
3937 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3938 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3939 struct radv_draw_info info = {};
3940
3941 info.indexed = true;
3942 info.count = drawCount;
3943 info.indirect = buffer;
3944 info.indirect_offset = offset;
3945 info.stride = stride;
3946
3947 radv_draw(cmd_buffer, &info);
3948 }
3949
3950 void radv_CmdDrawIndirectCountAMD(
3951 VkCommandBuffer commandBuffer,
3952 VkBuffer _buffer,
3953 VkDeviceSize offset,
3954 VkBuffer _countBuffer,
3955 VkDeviceSize countBufferOffset,
3956 uint32_t maxDrawCount,
3957 uint32_t stride)
3958 {
3959 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3960 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3961 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3962 struct radv_draw_info info = {};
3963
3964 info.count = maxDrawCount;
3965 info.indirect = buffer;
3966 info.indirect_offset = offset;
3967 info.count_buffer = count_buffer;
3968 info.count_buffer_offset = countBufferOffset;
3969 info.stride = stride;
3970
3971 radv_draw(cmd_buffer, &info);
3972 }
3973
3974 void radv_CmdDrawIndexedIndirectCountAMD(
3975 VkCommandBuffer commandBuffer,
3976 VkBuffer _buffer,
3977 VkDeviceSize offset,
3978 VkBuffer _countBuffer,
3979 VkDeviceSize countBufferOffset,
3980 uint32_t maxDrawCount,
3981 uint32_t stride)
3982 {
3983 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3984 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3985 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3986 struct radv_draw_info info = {};
3987
3988 info.indexed = true;
3989 info.count = maxDrawCount;
3990 info.indirect = buffer;
3991 info.indirect_offset = offset;
3992 info.count_buffer = count_buffer;
3993 info.count_buffer_offset = countBufferOffset;
3994 info.stride = stride;
3995
3996 radv_draw(cmd_buffer, &info);
3997 }
3998
3999 void radv_CmdDrawIndirectCountKHR(
4000 VkCommandBuffer commandBuffer,
4001 VkBuffer _buffer,
4002 VkDeviceSize offset,
4003 VkBuffer _countBuffer,
4004 VkDeviceSize countBufferOffset,
4005 uint32_t maxDrawCount,
4006 uint32_t stride)
4007 {
4008 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4009 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4010 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4011 struct radv_draw_info info = {};
4012
4013 info.count = maxDrawCount;
4014 info.indirect = buffer;
4015 info.indirect_offset = offset;
4016 info.count_buffer = count_buffer;
4017 info.count_buffer_offset = countBufferOffset;
4018 info.stride = stride;
4019
4020 radv_draw(cmd_buffer, &info);
4021 }
4022
4023 void radv_CmdDrawIndexedIndirectCountKHR(
4024 VkCommandBuffer commandBuffer,
4025 VkBuffer _buffer,
4026 VkDeviceSize offset,
4027 VkBuffer _countBuffer,
4028 VkDeviceSize countBufferOffset,
4029 uint32_t maxDrawCount,
4030 uint32_t stride)
4031 {
4032 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4033 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4034 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4035 struct radv_draw_info info = {};
4036
4037 info.indexed = true;
4038 info.count = maxDrawCount;
4039 info.indirect = buffer;
4040 info.indirect_offset = offset;
4041 info.count_buffer = count_buffer;
4042 info.count_buffer_offset = countBufferOffset;
4043 info.stride = stride;
4044
4045 radv_draw(cmd_buffer, &info);
4046 }
4047
4048 struct radv_dispatch_info {
4049 /**
4050 * Determine the layout of the grid (in block units) to be used.
4051 */
4052 uint32_t blocks[3];
4053
4054 /**
4055 * A starting offset for the grid. If unaligned is set, the offset
4056 * must still be aligned.
4057 */
4058 uint32_t offsets[3];
4059 /**
4060 * Whether it's an unaligned compute dispatch.
4061 */
4062 bool unaligned;
4063
4064 /**
4065 * Indirect compute parameters resource.
4066 */
4067 struct radv_buffer *indirect;
4068 uint64_t indirect_offset;
4069 };
4070
4071 static void
4072 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
4073 const struct radv_dispatch_info *info)
4074 {
4075 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4076 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4077 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
4078 struct radeon_winsys *ws = cmd_buffer->device->ws;
4079 bool predicating = cmd_buffer->state.predicating;
4080 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4081 struct radv_userdata_info *loc;
4082
4083 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
4084 AC_UD_CS_GRID_SIZE);
4085
4086 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
4087
4088 if (info->indirect) {
4089 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4090
4091 va += info->indirect->offset + info->indirect_offset;
4092
4093 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4094
4095 if (loc->sgpr_idx != -1) {
4096 for (unsigned i = 0; i < 3; ++i) {
4097 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4098 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4099 COPY_DATA_DST_SEL(COPY_DATA_REG));
4100 radeon_emit(cs, (va + 4 * i));
4101 radeon_emit(cs, (va + 4 * i) >> 32);
4102 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
4103 + loc->sgpr_idx * 4) >> 2) + i);
4104 radeon_emit(cs, 0);
4105 }
4106 }
4107
4108 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
4109 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
4110 PKT3_SHADER_TYPE_S(1));
4111 radeon_emit(cs, va);
4112 radeon_emit(cs, va >> 32);
4113 radeon_emit(cs, dispatch_initiator);
4114 } else {
4115 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
4116 PKT3_SHADER_TYPE_S(1));
4117 radeon_emit(cs, 1);
4118 radeon_emit(cs, va);
4119 radeon_emit(cs, va >> 32);
4120
4121 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
4122 PKT3_SHADER_TYPE_S(1));
4123 radeon_emit(cs, 0);
4124 radeon_emit(cs, dispatch_initiator);
4125 }
4126 } else {
4127 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
4128 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
4129
4130 if (info->unaligned) {
4131 unsigned *cs_block_size = compute_shader->info.cs.block_size;
4132 unsigned remainder[3];
4133
4134 /* If aligned, these should be an entire block size,
4135 * not 0.
4136 */
4137 remainder[0] = blocks[0] + cs_block_size[0] -
4138 align_u32_npot(blocks[0], cs_block_size[0]);
4139 remainder[1] = blocks[1] + cs_block_size[1] -
4140 align_u32_npot(blocks[1], cs_block_size[1]);
4141 remainder[2] = blocks[2] + cs_block_size[2] -
4142 align_u32_npot(blocks[2], cs_block_size[2]);
4143
4144 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
4145 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
4146 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
4147
4148 for(unsigned i = 0; i < 3; ++i) {
4149 assert(offsets[i] % cs_block_size[i] == 0);
4150 offsets[i] /= cs_block_size[i];
4151 }
4152
4153 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4154 radeon_emit(cs,
4155 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
4156 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4157 radeon_emit(cs,
4158 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4159 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4160 radeon_emit(cs,
4161 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4162 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4163
4164 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4165 }
4166
4167 if (loc->sgpr_idx != -1) {
4168 assert(!loc->indirect);
4169 assert(loc->num_sgprs == 3);
4170
4171 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4172 loc->sgpr_idx * 4, 3);
4173 radeon_emit(cs, blocks[0]);
4174 radeon_emit(cs, blocks[1]);
4175 radeon_emit(cs, blocks[2]);
4176 }
4177
4178 if (offsets[0] || offsets[1] || offsets[2]) {
4179 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4180 radeon_emit(cs, offsets[0]);
4181 radeon_emit(cs, offsets[1]);
4182 radeon_emit(cs, offsets[2]);
4183
4184 /* The blocks in the packet are not counts but end values. */
4185 for (unsigned i = 0; i < 3; ++i)
4186 blocks[i] += offsets[i];
4187 } else {
4188 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4189 }
4190
4191 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4192 PKT3_SHADER_TYPE_S(1));
4193 radeon_emit(cs, blocks[0]);
4194 radeon_emit(cs, blocks[1]);
4195 radeon_emit(cs, blocks[2]);
4196 radeon_emit(cs, dispatch_initiator);
4197 }
4198
4199 assert(cmd_buffer->cs->cdw <= cdw_max);
4200 }
4201
4202 static void
4203 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4204 {
4205 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4206 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4207 }
4208
4209 static void
4210 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4211 const struct radv_dispatch_info *info)
4212 {
4213 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4214 bool has_prefetch =
4215 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
4216 bool pipeline_is_dirty = pipeline &&
4217 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4218
4219 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4220 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4221 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4222 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4223 /* If we have to wait for idle, set all states first, so that
4224 * all SET packets are processed in parallel with previous draw
4225 * calls. Then upload descriptors, set shader pointers, and
4226 * dispatch, and prefetch at the end. This ensures that the
4227 * time the CUs are idle is very short. (there are only SET_SH
4228 * packets between the wait and the draw)
4229 */
4230 radv_emit_compute_pipeline(cmd_buffer);
4231 si_emit_cache_flush(cmd_buffer);
4232 /* <-- CUs are idle here --> */
4233
4234 radv_upload_compute_shader_descriptors(cmd_buffer);
4235
4236 radv_emit_dispatch_packets(cmd_buffer, info);
4237 /* <-- CUs are busy here --> */
4238
4239 /* Start prefetches after the dispatch has been started. Both
4240 * will run in parallel, but starting the dispatch first is
4241 * more important.
4242 */
4243 if (has_prefetch && pipeline_is_dirty) {
4244 radv_emit_shader_prefetch(cmd_buffer,
4245 pipeline->shaders[MESA_SHADER_COMPUTE]);
4246 }
4247 } else {
4248 /* If we don't wait for idle, start prefetches first, then set
4249 * states, and dispatch at the end.
4250 */
4251 si_emit_cache_flush(cmd_buffer);
4252
4253 if (has_prefetch && pipeline_is_dirty) {
4254 radv_emit_shader_prefetch(cmd_buffer,
4255 pipeline->shaders[MESA_SHADER_COMPUTE]);
4256 }
4257
4258 radv_upload_compute_shader_descriptors(cmd_buffer);
4259
4260 radv_emit_compute_pipeline(cmd_buffer);
4261 radv_emit_dispatch_packets(cmd_buffer, info);
4262 }
4263
4264 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
4265 }
4266
4267 void radv_CmdDispatchBase(
4268 VkCommandBuffer commandBuffer,
4269 uint32_t base_x,
4270 uint32_t base_y,
4271 uint32_t base_z,
4272 uint32_t x,
4273 uint32_t y,
4274 uint32_t z)
4275 {
4276 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4277 struct radv_dispatch_info info = {};
4278
4279 info.blocks[0] = x;
4280 info.blocks[1] = y;
4281 info.blocks[2] = z;
4282
4283 info.offsets[0] = base_x;
4284 info.offsets[1] = base_y;
4285 info.offsets[2] = base_z;
4286 radv_dispatch(cmd_buffer, &info);
4287 }
4288
4289 void radv_CmdDispatch(
4290 VkCommandBuffer commandBuffer,
4291 uint32_t x,
4292 uint32_t y,
4293 uint32_t z)
4294 {
4295 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4296 }
4297
4298 void radv_CmdDispatchIndirect(
4299 VkCommandBuffer commandBuffer,
4300 VkBuffer _buffer,
4301 VkDeviceSize offset)
4302 {
4303 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4304 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4305 struct radv_dispatch_info info = {};
4306
4307 info.indirect = buffer;
4308 info.indirect_offset = offset;
4309
4310 radv_dispatch(cmd_buffer, &info);
4311 }
4312
4313 void radv_unaligned_dispatch(
4314 struct radv_cmd_buffer *cmd_buffer,
4315 uint32_t x,
4316 uint32_t y,
4317 uint32_t z)
4318 {
4319 struct radv_dispatch_info info = {};
4320
4321 info.blocks[0] = x;
4322 info.blocks[1] = y;
4323 info.blocks[2] = z;
4324 info.unaligned = 1;
4325
4326 radv_dispatch(cmd_buffer, &info);
4327 }
4328
4329 void radv_CmdEndRenderPass(
4330 VkCommandBuffer commandBuffer)
4331 {
4332 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4333
4334 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
4335
4336 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4337
4338 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
4339 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
4340 radv_handle_subpass_image_transition(cmd_buffer,
4341 (struct radv_subpass_attachment){i, layout});
4342 }
4343
4344 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4345
4346 cmd_buffer->state.pass = NULL;
4347 cmd_buffer->state.subpass = NULL;
4348 cmd_buffer->state.attachments = NULL;
4349 cmd_buffer->state.framebuffer = NULL;
4350 }
4351
4352 void radv_CmdEndRenderPass2KHR(
4353 VkCommandBuffer commandBuffer,
4354 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4355 {
4356 radv_CmdEndRenderPass(commandBuffer);
4357 }
4358
4359 /*
4360 * For HTILE we have the following interesting clear words:
4361 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4362 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4363 * 0xfffffff0: Clear depth to 1.0
4364 * 0x00000000: Clear depth to 0.0
4365 */
4366 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
4367 struct radv_image *image,
4368 const VkImageSubresourceRange *range,
4369 uint32_t clear_word)
4370 {
4371 assert(range->baseMipLevel == 0);
4372 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
4373 unsigned layer_count = radv_get_layerCount(image, range);
4374 uint64_t size = image->surface.htile_slice_size * layer_count;
4375 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
4376 uint64_t offset = image->offset + image->htile_offset +
4377 image->surface.htile_slice_size * range->baseArrayLayer;
4378 struct radv_cmd_state *state = &cmd_buffer->state;
4379 VkClearDepthStencilValue value = {};
4380
4381 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4382 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4383
4384 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
4385 size, clear_word);
4386
4387 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4388
4389 if (vk_format_is_stencil(image->vk_format))
4390 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4391
4392 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4393
4394 if (radv_image_is_tc_compat_htile(image)) {
4395 /* Initialize the TC-compat metada value to 0 because by
4396 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
4397 * need have to conditionally update its value when performing
4398 * a fast depth clear.
4399 */
4400 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, 0);
4401 }
4402 }
4403
4404 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4405 struct radv_image *image,
4406 VkImageLayout src_layout,
4407 VkImageLayout dst_layout,
4408 unsigned src_queue_mask,
4409 unsigned dst_queue_mask,
4410 const VkImageSubresourceRange *range)
4411 {
4412 if (!radv_image_has_htile(image))
4413 return;
4414
4415 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
4416 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
4417 /* TODO: merge with the clear if applicable */
4418 radv_initialize_htile(cmd_buffer, image, range, 0);
4419 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4420 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4421 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4422 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4423 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4424 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4425 VkImageSubresourceRange local_range = *range;
4426 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4427 local_range.baseMipLevel = 0;
4428 local_range.levelCount = 1;
4429
4430 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4431 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4432
4433 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
4434
4435 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4436 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4437 }
4438 }
4439
4440 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4441 struct radv_image *image, uint32_t value)
4442 {
4443 struct radv_cmd_state *state = &cmd_buffer->state;
4444
4445 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4446 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4447
4448 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
4449
4450 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4451 }
4452
4453 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
4454 struct radv_image *image)
4455 {
4456 struct radv_cmd_state *state = &cmd_buffer->state;
4457 static const uint32_t fmask_clear_values[4] = {
4458 0x00000000,
4459 0x02020202,
4460 0xE4E4E4E4,
4461 0x76543210
4462 };
4463 uint32_t log2_samples = util_logbase2(image->info.samples);
4464 uint32_t value = fmask_clear_values[log2_samples];
4465
4466 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4467 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4468
4469 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, value);
4470
4471 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4472 }
4473
4474 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4475 struct radv_image *image, uint32_t value)
4476 {
4477 struct radv_cmd_state *state = &cmd_buffer->state;
4478
4479 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4480 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4481
4482 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
4483
4484 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4485 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4486 }
4487
4488 /**
4489 * Initialize DCC/FMASK/CMASK metadata for a color image.
4490 */
4491 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4492 struct radv_image *image,
4493 VkImageLayout src_layout,
4494 VkImageLayout dst_layout,
4495 unsigned src_queue_mask,
4496 unsigned dst_queue_mask)
4497 {
4498 if (radv_image_has_cmask(image)) {
4499 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4500
4501 /* TODO: clarify this. */
4502 if (radv_image_has_fmask(image)) {
4503 value = 0xccccccccu;
4504 }
4505
4506 radv_initialise_cmask(cmd_buffer, image, value);
4507 }
4508
4509 if (radv_image_has_fmask(image)) {
4510 radv_initialize_fmask(cmd_buffer, image);
4511 }
4512
4513 if (radv_image_has_dcc(image)) {
4514 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4515 bool need_decompress_pass = false;
4516
4517 if (radv_layout_dcc_compressed(image, dst_layout,
4518 dst_queue_mask)) {
4519 value = 0x20202020u;
4520 need_decompress_pass = true;
4521 }
4522
4523 radv_initialize_dcc(cmd_buffer, image, value);
4524
4525 radv_update_fce_metadata(cmd_buffer, image,
4526 need_decompress_pass);
4527 }
4528
4529 if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
4530 uint32_t color_values[2] = {};
4531 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
4532 }
4533 }
4534
4535 /**
4536 * Handle color image transitions for DCC/FMASK/CMASK.
4537 */
4538 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4539 struct radv_image *image,
4540 VkImageLayout src_layout,
4541 VkImageLayout dst_layout,
4542 unsigned src_queue_mask,
4543 unsigned dst_queue_mask,
4544 const VkImageSubresourceRange *range)
4545 {
4546 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4547 radv_init_color_image_metadata(cmd_buffer, image,
4548 src_layout, dst_layout,
4549 src_queue_mask, dst_queue_mask);
4550 return;
4551 }
4552
4553 if (radv_image_has_dcc(image)) {
4554 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4555 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4556 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4557 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4558 radv_decompress_dcc(cmd_buffer, image, range);
4559 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4560 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4561 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4562 }
4563 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
4564 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4565 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4566 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4567 }
4568
4569 if (radv_image_has_fmask(image)) {
4570 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
4571 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
4572 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
4573 }
4574 }
4575 }
4576 }
4577
4578 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4579 struct radv_image *image,
4580 VkImageLayout src_layout,
4581 VkImageLayout dst_layout,
4582 uint32_t src_family,
4583 uint32_t dst_family,
4584 const VkImageSubresourceRange *range)
4585 {
4586 if (image->exclusive && src_family != dst_family) {
4587 /* This is an acquire or a release operation and there will be
4588 * a corresponding release/acquire. Do the transition in the
4589 * most flexible queue. */
4590
4591 assert(src_family == cmd_buffer->queue_family_index ||
4592 dst_family == cmd_buffer->queue_family_index);
4593
4594 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4595 return;
4596
4597 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4598 (src_family == RADV_QUEUE_GENERAL ||
4599 dst_family == RADV_QUEUE_GENERAL))
4600 return;
4601 }
4602
4603 unsigned src_queue_mask =
4604 radv_image_queue_family_mask(image, src_family,
4605 cmd_buffer->queue_family_index);
4606 unsigned dst_queue_mask =
4607 radv_image_queue_family_mask(image, dst_family,
4608 cmd_buffer->queue_family_index);
4609
4610 if (vk_format_is_depth(image->vk_format)) {
4611 radv_handle_depth_image_transition(cmd_buffer, image,
4612 src_layout, dst_layout,
4613 src_queue_mask, dst_queue_mask,
4614 range);
4615 } else {
4616 radv_handle_color_image_transition(cmd_buffer, image,
4617 src_layout, dst_layout,
4618 src_queue_mask, dst_queue_mask,
4619 range);
4620 }
4621 }
4622
4623 struct radv_barrier_info {
4624 uint32_t eventCount;
4625 const VkEvent *pEvents;
4626 VkPipelineStageFlags srcStageMask;
4627 };
4628
4629 static void
4630 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
4631 uint32_t memoryBarrierCount,
4632 const VkMemoryBarrier *pMemoryBarriers,
4633 uint32_t bufferMemoryBarrierCount,
4634 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4635 uint32_t imageMemoryBarrierCount,
4636 const VkImageMemoryBarrier *pImageMemoryBarriers,
4637 const struct radv_barrier_info *info)
4638 {
4639 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4640 enum radv_cmd_flush_bits src_flush_bits = 0;
4641 enum radv_cmd_flush_bits dst_flush_bits = 0;
4642
4643 for (unsigned i = 0; i < info->eventCount; ++i) {
4644 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
4645 uint64_t va = radv_buffer_get_va(event->bo);
4646
4647 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4648
4649 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4650
4651 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
4652 assert(cmd_buffer->cs->cdw <= cdw_max);
4653 }
4654
4655 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4656 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
4657 NULL);
4658 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4659 NULL);
4660 }
4661
4662 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4663 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
4664 NULL);
4665 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4666 NULL);
4667 }
4668
4669 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4670 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4671
4672 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
4673 image);
4674 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4675 image);
4676 }
4677
4678 radv_stage_flush(cmd_buffer, info->srcStageMask);
4679 cmd_buffer->state.flush_bits |= src_flush_bits;
4680
4681 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4682 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4683 radv_handle_image_transition(cmd_buffer, image,
4684 pImageMemoryBarriers[i].oldLayout,
4685 pImageMemoryBarriers[i].newLayout,
4686 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4687 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4688 &pImageMemoryBarriers[i].subresourceRange);
4689 }
4690
4691 /* Make sure CP DMA is idle because the driver might have performed a
4692 * DMA operation for copying or filling buffers/images.
4693 */
4694 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
4695 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
4696 si_cp_dma_wait_for_idle(cmd_buffer);
4697
4698 cmd_buffer->state.flush_bits |= dst_flush_bits;
4699 }
4700
4701 void radv_CmdPipelineBarrier(
4702 VkCommandBuffer commandBuffer,
4703 VkPipelineStageFlags srcStageMask,
4704 VkPipelineStageFlags destStageMask,
4705 VkBool32 byRegion,
4706 uint32_t memoryBarrierCount,
4707 const VkMemoryBarrier* pMemoryBarriers,
4708 uint32_t bufferMemoryBarrierCount,
4709 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4710 uint32_t imageMemoryBarrierCount,
4711 const VkImageMemoryBarrier* pImageMemoryBarriers)
4712 {
4713 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4714 struct radv_barrier_info info;
4715
4716 info.eventCount = 0;
4717 info.pEvents = NULL;
4718 info.srcStageMask = srcStageMask;
4719
4720 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4721 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4722 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4723 }
4724
4725
4726 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4727 struct radv_event *event,
4728 VkPipelineStageFlags stageMask,
4729 unsigned value)
4730 {
4731 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4732 uint64_t va = radv_buffer_get_va(event->bo);
4733
4734 si_emit_cache_flush(cmd_buffer);
4735
4736 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4737
4738 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4739
4740 /* Flags that only require a top-of-pipe event. */
4741 VkPipelineStageFlags top_of_pipe_flags =
4742 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
4743
4744 /* Flags that only require a post-index-fetch event. */
4745 VkPipelineStageFlags post_index_fetch_flags =
4746 top_of_pipe_flags |
4747 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
4748 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
4749
4750 /* Make sure CP DMA is idle because the driver might have performed a
4751 * DMA operation for copying or filling buffers/images.
4752 */
4753 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
4754 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
4755 si_cp_dma_wait_for_idle(cmd_buffer);
4756
4757 /* TODO: Emit EOS events for syncing PS/CS stages. */
4758
4759 if (!(stageMask & ~top_of_pipe_flags)) {
4760 /* Just need to sync the PFP engine. */
4761 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4762 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
4763 S_370_WR_CONFIRM(1) |
4764 S_370_ENGINE_SEL(V_370_PFP));
4765 radeon_emit(cs, va);
4766 radeon_emit(cs, va >> 32);
4767 radeon_emit(cs, value);
4768 } else if (!(stageMask & ~post_index_fetch_flags)) {
4769 /* Sync ME because PFP reads index and indirect buffers. */
4770 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4771 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
4772 S_370_WR_CONFIRM(1) |
4773 S_370_ENGINE_SEL(V_370_ME));
4774 radeon_emit(cs, va);
4775 radeon_emit(cs, va >> 32);
4776 radeon_emit(cs, value);
4777 } else {
4778 /* Otherwise, sync all prior GPU work using an EOP event. */
4779 si_cs_emit_write_event_eop(cs,
4780 cmd_buffer->device->physical_device->rad_info.chip_class,
4781 radv_cmd_buffer_uses_mec(cmd_buffer),
4782 V_028A90_BOTTOM_OF_PIPE_TS, 0,
4783 EOP_DATA_SEL_VALUE_32BIT, va, value,
4784 cmd_buffer->gfx9_eop_bug_va);
4785 }
4786
4787 assert(cmd_buffer->cs->cdw <= cdw_max);
4788 }
4789
4790 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4791 VkEvent _event,
4792 VkPipelineStageFlags stageMask)
4793 {
4794 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4795 RADV_FROM_HANDLE(radv_event, event, _event);
4796
4797 write_event(cmd_buffer, event, stageMask, 1);
4798 }
4799
4800 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4801 VkEvent _event,
4802 VkPipelineStageFlags stageMask)
4803 {
4804 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4805 RADV_FROM_HANDLE(radv_event, event, _event);
4806
4807 write_event(cmd_buffer, event, stageMask, 0);
4808 }
4809
4810 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4811 uint32_t eventCount,
4812 const VkEvent* pEvents,
4813 VkPipelineStageFlags srcStageMask,
4814 VkPipelineStageFlags dstStageMask,
4815 uint32_t memoryBarrierCount,
4816 const VkMemoryBarrier* pMemoryBarriers,
4817 uint32_t bufferMemoryBarrierCount,
4818 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4819 uint32_t imageMemoryBarrierCount,
4820 const VkImageMemoryBarrier* pImageMemoryBarriers)
4821 {
4822 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4823 struct radv_barrier_info info;
4824
4825 info.eventCount = eventCount;
4826 info.pEvents = pEvents;
4827 info.srcStageMask = 0;
4828
4829 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4830 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4831 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4832 }
4833
4834
4835 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4836 uint32_t deviceMask)
4837 {
4838 /* No-op */
4839 }
4840
4841 /* VK_EXT_conditional_rendering */
4842 void radv_CmdBeginConditionalRenderingEXT(
4843 VkCommandBuffer commandBuffer,
4844 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
4845 {
4846 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4847 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
4848 bool draw_visible = true;
4849 uint64_t va;
4850
4851 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
4852
4853 /* By default, if the 32-bit value at offset in buffer memory is zero,
4854 * then the rendering commands are discarded, otherwise they are
4855 * executed as normal. If the inverted flag is set, all commands are
4856 * discarded if the value is non zero.
4857 */
4858 if (pConditionalRenderingBegin->flags &
4859 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
4860 draw_visible = false;
4861 }
4862
4863 si_emit_cache_flush(cmd_buffer);
4864
4865 /* Enable predication for this command buffer. */
4866 si_emit_set_predication_state(cmd_buffer, draw_visible, va);
4867 cmd_buffer->state.predicating = true;
4868
4869 /* Store conditional rendering user info. */
4870 cmd_buffer->state.predication_type = draw_visible;
4871 cmd_buffer->state.predication_va = va;
4872 }
4873
4874 void radv_CmdEndConditionalRenderingEXT(
4875 VkCommandBuffer commandBuffer)
4876 {
4877 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4878
4879 /* Disable predication for this command buffer. */
4880 si_emit_set_predication_state(cmd_buffer, false, 0);
4881 cmd_buffer->state.predicating = false;
4882
4883 /* Reset conditional rendering user info. */
4884 cmd_buffer->state.predication_type = -1;
4885 cmd_buffer->state.predication_va = 0;
4886 }
4887
4888 /* VK_EXT_transform_feedback */
4889 void radv_CmdBindTransformFeedbackBuffersEXT(
4890 VkCommandBuffer commandBuffer,
4891 uint32_t firstBinding,
4892 uint32_t bindingCount,
4893 const VkBuffer* pBuffers,
4894 const VkDeviceSize* pOffsets,
4895 const VkDeviceSize* pSizes)
4896 {
4897 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4898 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
4899 uint8_t enabled_mask = 0;
4900
4901 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
4902 for (uint32_t i = 0; i < bindingCount; i++) {
4903 uint32_t idx = firstBinding + i;
4904
4905 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
4906 sb[idx].offset = pOffsets[i];
4907 sb[idx].size = pSizes[i];
4908
4909 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
4910 sb[idx].buffer->bo);
4911
4912 enabled_mask |= 1 << idx;
4913 }
4914
4915 cmd_buffer->state.streamout.enabled_mask = enabled_mask;
4916
4917 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
4918 }
4919
4920 static void
4921 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
4922 {
4923 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4924 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4925
4926 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
4927 radeon_emit(cs,
4928 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
4929 S_028B94_RAST_STREAM(0) |
4930 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
4931 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
4932 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
4933 radeon_emit(cs, so->hw_enabled_mask &
4934 so->enabled_stream_buffers_mask);
4935
4936 cmd_buffer->state.context_roll_without_scissor_emitted = true;
4937 }
4938
4939 static void
4940 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
4941 {
4942 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4943 bool old_streamout_enabled = so->streamout_enabled;
4944 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
4945
4946 so->streamout_enabled = enable;
4947
4948 so->hw_enabled_mask = so->enabled_mask |
4949 (so->enabled_mask << 4) |
4950 (so->enabled_mask << 8) |
4951 (so->enabled_mask << 12);
4952
4953 if ((old_streamout_enabled != so->streamout_enabled) ||
4954 (old_hw_enabled_mask != so->hw_enabled_mask))
4955 radv_emit_streamout_enable(cmd_buffer);
4956 }
4957
4958 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
4959 {
4960 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4961 unsigned reg_strmout_cntl;
4962
4963 /* The register is at different places on different ASICs. */
4964 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
4965 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
4966 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
4967 } else {
4968 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
4969 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
4970 }
4971
4972 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4973 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
4974
4975 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
4976 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
4977 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
4978 radeon_emit(cs, 0);
4979 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
4980 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
4981 radeon_emit(cs, 4); /* poll interval */
4982 }
4983
4984 void radv_CmdBeginTransformFeedbackEXT(
4985 VkCommandBuffer commandBuffer,
4986 uint32_t firstCounterBuffer,
4987 uint32_t counterBufferCount,
4988 const VkBuffer* pCounterBuffers,
4989 const VkDeviceSize* pCounterBufferOffsets)
4990 {
4991 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4992 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
4993 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4994 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4995 uint32_t i;
4996
4997 radv_flush_vgt_streamout(cmd_buffer);
4998
4999 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5000 for_each_bit(i, so->enabled_mask) {
5001 int32_t counter_buffer_idx = i - firstCounterBuffer;
5002 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5003 counter_buffer_idx = -1;
5004
5005 /* SI binds streamout buffers as shader resources.
5006 * VGT only counts primitives and tells the shader through
5007 * SGPRs what to do.
5008 */
5009 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
5010 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
5011 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
5012
5013 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5014
5015 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5016 /* The array of counter buffers is optional. */
5017 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5018 uint64_t va = radv_buffer_get_va(buffer->bo);
5019
5020 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5021
5022 /* Append */
5023 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5024 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5025 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5026 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
5027 radeon_emit(cs, 0); /* unused */
5028 radeon_emit(cs, 0); /* unused */
5029 radeon_emit(cs, va); /* src address lo */
5030 radeon_emit(cs, va >> 32); /* src address hi */
5031
5032 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5033 } else {
5034 /* Start from the beginning. */
5035 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5036 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5037 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5038 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
5039 radeon_emit(cs, 0); /* unused */
5040 radeon_emit(cs, 0); /* unused */
5041 radeon_emit(cs, 0); /* unused */
5042 radeon_emit(cs, 0); /* unused */
5043 }
5044 }
5045
5046 radv_set_streamout_enable(cmd_buffer, true);
5047 }
5048
5049 void radv_CmdEndTransformFeedbackEXT(
5050 VkCommandBuffer commandBuffer,
5051 uint32_t firstCounterBuffer,
5052 uint32_t counterBufferCount,
5053 const VkBuffer* pCounterBuffers,
5054 const VkDeviceSize* pCounterBufferOffsets)
5055 {
5056 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5057 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5058 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5059 uint32_t i;
5060
5061 radv_flush_vgt_streamout(cmd_buffer);
5062
5063 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5064 for_each_bit(i, so->enabled_mask) {
5065 int32_t counter_buffer_idx = i - firstCounterBuffer;
5066 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5067 counter_buffer_idx = -1;
5068
5069 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5070 /* The array of counters buffer is optional. */
5071 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5072 uint64_t va = radv_buffer_get_va(buffer->bo);
5073
5074 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5075
5076 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5077 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5078 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5079 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
5080 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
5081 radeon_emit(cs, va); /* dst address lo */
5082 radeon_emit(cs, va >> 32); /* dst address hi */
5083 radeon_emit(cs, 0); /* unused */
5084 radeon_emit(cs, 0); /* unused */
5085
5086 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5087 }
5088
5089 /* Deactivate transform feedback by zeroing the buffer size.
5090 * The counters (primitives generated, primitives emitted) may
5091 * be enabled even if there is not buffer bound. This ensures
5092 * that the primitives-emitted query won't increment.
5093 */
5094 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
5095
5096 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5097 }
5098
5099 radv_set_streamout_enable(cmd_buffer, false);
5100 }
5101
5102 void radv_CmdDrawIndirectByteCountEXT(
5103 VkCommandBuffer commandBuffer,
5104 uint32_t instanceCount,
5105 uint32_t firstInstance,
5106 VkBuffer _counterBuffer,
5107 VkDeviceSize counterBufferOffset,
5108 uint32_t counterOffset,
5109 uint32_t vertexStride)
5110 {
5111 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5112 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
5113 struct radv_draw_info info = {};
5114
5115 info.instance_count = instanceCount;
5116 info.first_instance = firstInstance;
5117 info.strmout_buffer = counterBuffer;
5118 info.strmout_buffer_offset = counterBufferOffset;
5119 info.stride = vertexStride;
5120
5121 radv_draw(cmd_buffer, &info);
5122 }