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radv: add support for dynamic and scissor count
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 bool src_render_loop,
58 VkImageLayout dst_layout,
59 bool dst_render_loop,
60 uint32_t src_family,
61 uint32_t dst_family,
62 const VkImageSubresourceRange *range,
63 struct radv_sample_locations_state *sample_locs);
64
65 const struct radv_dynamic_state default_dynamic_state = {
66 .viewport = {
67 .count = 0,
68 },
69 .scissor = {
70 .count = 0,
71 },
72 .line_width = 1.0f,
73 .depth_bias = {
74 .bias = 0.0f,
75 .clamp = 0.0f,
76 .slope = 0.0f,
77 },
78 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
79 .depth_bounds = {
80 .min = 0.0f,
81 .max = 1.0f,
82 },
83 .stencil_compare_mask = {
84 .front = ~0u,
85 .back = ~0u,
86 },
87 .stencil_write_mask = {
88 .front = ~0u,
89 .back = ~0u,
90 },
91 .stencil_reference = {
92 .front = 0u,
93 .back = 0u,
94 },
95 .line_stipple = {
96 .factor = 0u,
97 .pattern = 0u,
98 },
99 .cull_mode = 0u,
100 .front_face = 0u,
101 .primitive_topology = 0u,
102 };
103
104 static void
105 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
106 const struct radv_dynamic_state *src)
107 {
108 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
109 uint32_t copy_mask = src->mask;
110 uint32_t dest_mask = 0;
111
112 dest->discard_rectangle.count = src->discard_rectangle.count;
113 dest->sample_location.count = src->sample_location.count;
114
115 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
116 if (dest->viewport.count != src->viewport.count) {
117 dest->viewport.count = src->viewport.count;
118 dest_mask |= RADV_DYNAMIC_VIEWPORT;
119 }
120
121 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
122 src->viewport.count * sizeof(VkViewport))) {
123 typed_memcpy(dest->viewport.viewports,
124 src->viewport.viewports,
125 src->viewport.count);
126 dest_mask |= RADV_DYNAMIC_VIEWPORT;
127 }
128 }
129
130 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
131 if (dest->scissor.count != src->scissor.count) {
132 dest->scissor.count = src->scissor.count;
133 dest_mask |= RADV_DYNAMIC_SCISSOR;
134 }
135
136 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
137 src->scissor.count * sizeof(VkRect2D))) {
138 typed_memcpy(dest->scissor.scissors,
139 src->scissor.scissors, src->scissor.count);
140 dest_mask |= RADV_DYNAMIC_SCISSOR;
141 }
142 }
143
144 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
145 if (dest->line_width != src->line_width) {
146 dest->line_width = src->line_width;
147 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
148 }
149 }
150
151 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
152 if (memcmp(&dest->depth_bias, &src->depth_bias,
153 sizeof(src->depth_bias))) {
154 dest->depth_bias = src->depth_bias;
155 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
156 }
157 }
158
159 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
160 if (memcmp(&dest->blend_constants, &src->blend_constants,
161 sizeof(src->blend_constants))) {
162 typed_memcpy(dest->blend_constants,
163 src->blend_constants, 4);
164 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
165 }
166 }
167
168 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
169 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
170 sizeof(src->depth_bounds))) {
171 dest->depth_bounds = src->depth_bounds;
172 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
173 }
174 }
175
176 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
177 if (memcmp(&dest->stencil_compare_mask,
178 &src->stencil_compare_mask,
179 sizeof(src->stencil_compare_mask))) {
180 dest->stencil_compare_mask = src->stencil_compare_mask;
181 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
182 }
183 }
184
185 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
186 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
187 sizeof(src->stencil_write_mask))) {
188 dest->stencil_write_mask = src->stencil_write_mask;
189 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
190 }
191 }
192
193 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
194 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
195 sizeof(src->stencil_reference))) {
196 dest->stencil_reference = src->stencil_reference;
197 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
198 }
199 }
200
201 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
202 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
203 src->discard_rectangle.count * sizeof(VkRect2D))) {
204 typed_memcpy(dest->discard_rectangle.rectangles,
205 src->discard_rectangle.rectangles,
206 src->discard_rectangle.count);
207 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
208 }
209 }
210
211 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
212 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
213 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
214 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
215 memcmp(&dest->sample_location.locations,
216 &src->sample_location.locations,
217 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
218 dest->sample_location.per_pixel = src->sample_location.per_pixel;
219 dest->sample_location.grid_size = src->sample_location.grid_size;
220 typed_memcpy(dest->sample_location.locations,
221 src->sample_location.locations,
222 src->sample_location.count);
223 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
224 }
225 }
226
227 if (copy_mask & RADV_DYNAMIC_LINE_STIPPLE) {
228 if (memcmp(&dest->line_stipple, &src->line_stipple,
229 sizeof(src->line_stipple))) {
230 dest->line_stipple = src->line_stipple;
231 dest_mask |= RADV_DYNAMIC_LINE_STIPPLE;
232 }
233 }
234
235 if (copy_mask & RADV_DYNAMIC_CULL_MODE) {
236 if (dest->cull_mode != src->cull_mode) {
237 dest->cull_mode = src->cull_mode;
238 dest_mask |= RADV_DYNAMIC_CULL_MODE;
239 }
240 }
241
242 if (copy_mask & RADV_DYNAMIC_FRONT_FACE) {
243 if (dest->front_face != src->front_face) {
244 dest->front_face = src->front_face;
245 dest_mask |= RADV_DYNAMIC_FRONT_FACE;
246 }
247 }
248
249 if (copy_mask & RADV_DYNAMIC_PRIMITIVE_TOPOLOGY) {
250 if (dest->primitive_topology != src->primitive_topology) {
251 dest->primitive_topology = src->primitive_topology;
252 dest_mask |= RADV_DYNAMIC_PRIMITIVE_TOPOLOGY;
253 }
254 }
255
256 cmd_buffer->state.dirty |= dest_mask;
257 }
258
259 static void
260 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
261 struct radv_pipeline *pipeline)
262 {
263 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
264 struct radv_shader_info *info;
265
266 if (!pipeline->streamout_shader ||
267 cmd_buffer->device->physical_device->use_ngg_streamout)
268 return;
269
270 info = &pipeline->streamout_shader->info;
271 for (int i = 0; i < MAX_SO_BUFFERS; i++)
272 so->stride_in_dw[i] = info->so.strides[i];
273
274 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
275 }
276
277 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
278 {
279 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
280 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
281 }
282
283 enum ring_type radv_queue_family_to_ring(int f) {
284 switch (f) {
285 case RADV_QUEUE_GENERAL:
286 return RING_GFX;
287 case RADV_QUEUE_COMPUTE:
288 return RING_COMPUTE;
289 case RADV_QUEUE_TRANSFER:
290 return RING_DMA;
291 default:
292 unreachable("Unknown queue family");
293 }
294 }
295
296 static VkResult radv_create_cmd_buffer(
297 struct radv_device * device,
298 struct radv_cmd_pool * pool,
299 VkCommandBufferLevel level,
300 VkCommandBuffer* pCommandBuffer)
301 {
302 struct radv_cmd_buffer *cmd_buffer;
303 unsigned ring;
304 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
305 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
306 if (cmd_buffer == NULL)
307 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
308
309 vk_object_base_init(&device->vk, &cmd_buffer->base,
310 VK_OBJECT_TYPE_COMMAND_BUFFER);
311
312 cmd_buffer->device = device;
313 cmd_buffer->pool = pool;
314 cmd_buffer->level = level;
315
316 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
317 cmd_buffer->queue_family_index = pool->queue_family_index;
318
319 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
320
321 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
322 if (!cmd_buffer->cs) {
323 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
324 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
325 }
326
327 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
328
329 list_inithead(&cmd_buffer->upload.list);
330
331 return VK_SUCCESS;
332 }
333
334 static void
335 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
336 {
337 list_del(&cmd_buffer->pool_link);
338
339 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
340 &cmd_buffer->upload.list, list) {
341 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
342 list_del(&up->list);
343 free(up);
344 }
345
346 if (cmd_buffer->upload.upload_bo)
347 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
348 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
349
350 for (unsigned i = 0; i < MAX_BIND_POINTS; i++)
351 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
352
353 vk_object_base_finish(&cmd_buffer->base);
354
355 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
356 }
357
358 static VkResult
359 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
360 {
361 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
362
363 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
364 &cmd_buffer->upload.list, list) {
365 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
366 list_del(&up->list);
367 free(up);
368 }
369
370 cmd_buffer->push_constant_stages = 0;
371 cmd_buffer->scratch_size_per_wave_needed = 0;
372 cmd_buffer->scratch_waves_wanted = 0;
373 cmd_buffer->compute_scratch_size_per_wave_needed = 0;
374 cmd_buffer->compute_scratch_waves_wanted = 0;
375 cmd_buffer->esgs_ring_size_needed = 0;
376 cmd_buffer->gsvs_ring_size_needed = 0;
377 cmd_buffer->tess_rings_needed = false;
378 cmd_buffer->gds_needed = false;
379 cmd_buffer->gds_oa_needed = false;
380 cmd_buffer->sample_positions_needed = false;
381
382 if (cmd_buffer->upload.upload_bo)
383 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
384 cmd_buffer->upload.upload_bo);
385 cmd_buffer->upload.offset = 0;
386
387 cmd_buffer->record_result = VK_SUCCESS;
388
389 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
390
391 for (unsigned i = 0; i < MAX_BIND_POINTS; i++) {
392 cmd_buffer->descriptors[i].dirty = 0;
393 cmd_buffer->descriptors[i].valid = 0;
394 cmd_buffer->descriptors[i].push_dirty = false;
395 }
396
397 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
398 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
399 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
400 unsigned fence_offset, eop_bug_offset;
401 void *fence_ptr;
402
403 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
404 &fence_ptr);
405
406 cmd_buffer->gfx9_fence_va =
407 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
408 cmd_buffer->gfx9_fence_va += fence_offset;
409
410 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
411 /* Allocate a buffer for the EOP bug on GFX9. */
412 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
413 &eop_bug_offset, &fence_ptr);
414 cmd_buffer->gfx9_eop_bug_va =
415 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
416 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
417 }
418 }
419
420 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
421
422 return cmd_buffer->record_result;
423 }
424
425 static bool
426 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
427 uint64_t min_needed)
428 {
429 uint64_t new_size;
430 struct radeon_winsys_bo *bo;
431 struct radv_cmd_buffer_upload *upload;
432 struct radv_device *device = cmd_buffer->device;
433
434 new_size = MAX2(min_needed, 16 * 1024);
435 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
436
437 bo = device->ws->buffer_create(device->ws,
438 new_size, 4096,
439 RADEON_DOMAIN_GTT,
440 RADEON_FLAG_CPU_ACCESS|
441 RADEON_FLAG_NO_INTERPROCESS_SHARING |
442 RADEON_FLAG_32BIT,
443 RADV_BO_PRIORITY_UPLOAD_BUFFER);
444
445 if (!bo) {
446 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
447 return false;
448 }
449
450 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
451 if (cmd_buffer->upload.upload_bo) {
452 upload = malloc(sizeof(*upload));
453
454 if (!upload) {
455 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
456 device->ws->buffer_destroy(bo);
457 return false;
458 }
459
460 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
461 list_add(&upload->list, &cmd_buffer->upload.list);
462 }
463
464 cmd_buffer->upload.upload_bo = bo;
465 cmd_buffer->upload.size = new_size;
466 cmd_buffer->upload.offset = 0;
467 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
468
469 if (!cmd_buffer->upload.map) {
470 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
471 return false;
472 }
473
474 return true;
475 }
476
477 bool
478 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
479 unsigned size,
480 unsigned alignment,
481 unsigned *out_offset,
482 void **ptr)
483 {
484 assert(util_is_power_of_two_nonzero(alignment));
485
486 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
487 if (offset + size > cmd_buffer->upload.size) {
488 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
489 return false;
490 offset = 0;
491 }
492
493 *out_offset = offset;
494 *ptr = cmd_buffer->upload.map + offset;
495
496 cmd_buffer->upload.offset = offset + size;
497 return true;
498 }
499
500 bool
501 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
502 unsigned size, unsigned alignment,
503 const void *data, unsigned *out_offset)
504 {
505 uint8_t *ptr;
506
507 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
508 out_offset, (void **)&ptr))
509 return false;
510
511 if (ptr)
512 memcpy(ptr, data, size);
513
514 return true;
515 }
516
517 static void
518 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
519 unsigned count, const uint32_t *data)
520 {
521 struct radeon_cmdbuf *cs = cmd_buffer->cs;
522
523 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
524
525 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
526 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
527 S_370_WR_CONFIRM(1) |
528 S_370_ENGINE_SEL(V_370_ME));
529 radeon_emit(cs, va);
530 radeon_emit(cs, va >> 32);
531 radeon_emit_array(cs, data, count);
532 }
533
534 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
535 {
536 struct radv_device *device = cmd_buffer->device;
537 struct radeon_cmdbuf *cs = cmd_buffer->cs;
538 uint64_t va;
539
540 va = radv_buffer_get_va(device->trace_bo);
541 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
542 va += 4;
543
544 ++cmd_buffer->state.trace_id;
545 radv_emit_write_data_packet(cmd_buffer, va, 1,
546 &cmd_buffer->state.trace_id);
547
548 radeon_check_space(cmd_buffer->device->ws, cs, 2);
549
550 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
551 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
552 }
553
554 static void
555 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
556 enum radv_cmd_flush_bits flags)
557 {
558 if (unlikely(cmd_buffer->device->thread_trace_bo)) {
559 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
560 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_THREAD_TRACE_MARKER) | EVENT_INDEX(0));
561 }
562
563 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
564 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
565 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
566
567 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
568
569 /* Force wait for graphics or compute engines to be idle. */
570 si_cs_emit_cache_flush(cmd_buffer->cs,
571 cmd_buffer->device->physical_device->rad_info.chip_class,
572 &cmd_buffer->gfx9_fence_idx,
573 cmd_buffer->gfx9_fence_va,
574 radv_cmd_buffer_uses_mec(cmd_buffer),
575 flags, cmd_buffer->gfx9_eop_bug_va);
576 }
577
578 if (unlikely(cmd_buffer->device->trace_bo))
579 radv_cmd_buffer_trace_emit(cmd_buffer);
580 }
581
582 static void
583 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
584 struct radv_pipeline *pipeline, enum ring_type ring)
585 {
586 struct radv_device *device = cmd_buffer->device;
587 uint32_t data[2];
588 uint64_t va;
589
590 va = radv_buffer_get_va(device->trace_bo);
591
592 switch (ring) {
593 case RING_GFX:
594 va += 8;
595 break;
596 case RING_COMPUTE:
597 va += 16;
598 break;
599 default:
600 assert(!"invalid ring type");
601 }
602
603 uint64_t pipeline_address = (uintptr_t)pipeline;
604 data[0] = pipeline_address;
605 data[1] = pipeline_address >> 32;
606
607 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
608 }
609
610 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
611 VkPipelineBindPoint bind_point,
612 struct radv_descriptor_set *set,
613 unsigned idx)
614 {
615 struct radv_descriptor_state *descriptors_state =
616 radv_get_descriptors_state(cmd_buffer, bind_point);
617
618 descriptors_state->sets[idx] = set;
619
620 descriptors_state->valid |= (1u << idx); /* active descriptors */
621 descriptors_state->dirty |= (1u << idx);
622 }
623
624 static void
625 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
626 VkPipelineBindPoint bind_point)
627 {
628 struct radv_descriptor_state *descriptors_state =
629 radv_get_descriptors_state(cmd_buffer, bind_point);
630 struct radv_device *device = cmd_buffer->device;
631 uint32_t data[MAX_SETS * 2] = {};
632 uint64_t va;
633 unsigned i;
634 va = radv_buffer_get_va(device->trace_bo) + 24;
635
636 for_each_bit(i, descriptors_state->valid) {
637 struct radv_descriptor_set *set = descriptors_state->sets[i];
638 data[i * 2] = (uint64_t)(uintptr_t)set;
639 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
640 }
641
642 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
643 }
644
645 struct radv_userdata_info *
646 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
647 gl_shader_stage stage,
648 int idx)
649 {
650 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
651 return &shader->info.user_sgprs_locs.shader_data[idx];
652 }
653
654 static void
655 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
656 struct radv_pipeline *pipeline,
657 gl_shader_stage stage,
658 int idx, uint64_t va)
659 {
660 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
661 uint32_t base_reg = pipeline->user_data_0[stage];
662 if (loc->sgpr_idx == -1)
663 return;
664
665 assert(loc->num_sgprs == 1);
666
667 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
668 base_reg + loc->sgpr_idx * 4, va, false);
669 }
670
671 static void
672 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
673 struct radv_pipeline *pipeline,
674 struct radv_descriptor_state *descriptors_state,
675 gl_shader_stage stage)
676 {
677 struct radv_device *device = cmd_buffer->device;
678 struct radeon_cmdbuf *cs = cmd_buffer->cs;
679 uint32_t sh_base = pipeline->user_data_0[stage];
680 struct radv_userdata_locations *locs =
681 &pipeline->shaders[stage]->info.user_sgprs_locs;
682 unsigned mask = locs->descriptor_sets_enabled;
683
684 mask &= descriptors_state->dirty & descriptors_state->valid;
685
686 while (mask) {
687 int start, count;
688
689 u_bit_scan_consecutive_range(&mask, &start, &count);
690
691 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
692 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
693
694 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
695 for (int i = 0; i < count; i++) {
696 struct radv_descriptor_set *set =
697 descriptors_state->sets[start + i];
698
699 radv_emit_shader_pointer_body(device, cs, set->va, true);
700 }
701 }
702 }
703
704 /**
705 * Convert the user sample locations to hardware sample locations (the values
706 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
707 */
708 static void
709 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
710 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
711 {
712 uint32_t x_offset = x % state->grid_size.width;
713 uint32_t y_offset = y % state->grid_size.height;
714 uint32_t num_samples = (uint32_t)state->per_pixel;
715 VkSampleLocationEXT *user_locs;
716 uint32_t pixel_offset;
717
718 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
719
720 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
721 user_locs = &state->locations[pixel_offset];
722
723 for (uint32_t i = 0; i < num_samples; i++) {
724 float shifted_pos_x = user_locs[i].x - 0.5;
725 float shifted_pos_y = user_locs[i].y - 0.5;
726
727 int32_t scaled_pos_x = floorf(shifted_pos_x * 16);
728 int32_t scaled_pos_y = floorf(shifted_pos_y * 16);
729
730 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
731 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
732 }
733 }
734
735 /**
736 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
737 * locations.
738 */
739 static void
740 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
741 uint32_t *sample_locs_pixel)
742 {
743 for (uint32_t i = 0; i < num_samples; i++) {
744 uint32_t sample_reg_idx = i / 4;
745 uint32_t sample_loc_idx = i % 4;
746 int32_t pos_x = sample_locs[i].x;
747 int32_t pos_y = sample_locs[i].y;
748
749 uint32_t shift_x = 8 * sample_loc_idx;
750 uint32_t shift_y = shift_x + 4;
751
752 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
753 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
754 }
755 }
756
757 /**
758 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
759 * sample locations.
760 */
761 static uint64_t
762 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
763 VkOffset2D *sample_locs,
764 uint32_t num_samples)
765 {
766 uint32_t centroid_priorities[num_samples];
767 uint32_t sample_mask = num_samples - 1;
768 uint32_t distances[num_samples];
769 uint64_t centroid_priority = 0;
770
771 /* Compute the distances from center for each sample. */
772 for (int i = 0; i < num_samples; i++) {
773 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
774 (sample_locs[i].y * sample_locs[i].y);
775 }
776
777 /* Compute the centroid priorities by looking at the distances array. */
778 for (int i = 0; i < num_samples; i++) {
779 uint32_t min_idx = 0;
780
781 for (int j = 1; j < num_samples; j++) {
782 if (distances[j] < distances[min_idx])
783 min_idx = j;
784 }
785
786 centroid_priorities[i] = min_idx;
787 distances[min_idx] = 0xffffffff;
788 }
789
790 /* Compute the final centroid priority. */
791 for (int i = 0; i < 8; i++) {
792 centroid_priority |=
793 centroid_priorities[i & sample_mask] << (i * 4);
794 }
795
796 return centroid_priority << 32 | centroid_priority;
797 }
798
799 /**
800 * Emit the sample locations that are specified with VK_EXT_sample_locations.
801 */
802 static void
803 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
804 {
805 struct radv_sample_locations_state *sample_location =
806 &cmd_buffer->state.dynamic.sample_location;
807 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
808 struct radeon_cmdbuf *cs = cmd_buffer->cs;
809 uint32_t sample_locs_pixel[4][2] = {};
810 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
811 uint32_t max_sample_dist = 0;
812 uint64_t centroid_priority;
813
814 if (!cmd_buffer->state.dynamic.sample_location.count)
815 return;
816
817 /* Convert the user sample locations to hardware sample locations. */
818 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
819 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
820 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
821 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
822
823 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
824 for (uint32_t i = 0; i < 4; i++) {
825 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
826 sample_locs_pixel[i]);
827 }
828
829 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
830 centroid_priority =
831 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
832 num_samples);
833
834 /* Compute the maximum sample distance from the specified locations. */
835 for (unsigned i = 0; i < 4; ++i) {
836 for (uint32_t j = 0; j < num_samples; j++) {
837 VkOffset2D offset = sample_locs[i][j];
838 max_sample_dist = MAX2(max_sample_dist,
839 MAX2(abs(offset.x), abs(offset.y)));
840 }
841 }
842
843 /* Emit the specified user sample locations. */
844 switch (num_samples) {
845 case 2:
846 case 4:
847 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
848 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
849 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
850 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
851 break;
852 case 8:
853 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
854 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
855 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
856 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
857 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
858 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
859 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
860 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
861 break;
862 default:
863 unreachable("invalid number of samples");
864 }
865
866 /* Emit the maximum sample distance and the centroid priority. */
867 radeon_set_context_reg_rmw(cs, R_028BE0_PA_SC_AA_CONFIG,
868 S_028BE0_MAX_SAMPLE_DIST(max_sample_dist),
869 ~C_028BE0_MAX_SAMPLE_DIST);
870
871 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
872 radeon_emit(cs, centroid_priority);
873 radeon_emit(cs, centroid_priority >> 32);
874
875 /* GFX9: Flush DFSM when the AA mode changes. */
876 if (cmd_buffer->device->dfsm_allowed) {
877 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
878 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
879 }
880
881 cmd_buffer->state.context_roll_without_scissor_emitted = true;
882 }
883
884 static void
885 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
886 struct radv_pipeline *pipeline,
887 gl_shader_stage stage,
888 int idx, int count, uint32_t *values)
889 {
890 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
891 uint32_t base_reg = pipeline->user_data_0[stage];
892 if (loc->sgpr_idx == -1)
893 return;
894
895 assert(loc->num_sgprs == count);
896
897 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
898 radeon_emit_array(cmd_buffer->cs, values, count);
899 }
900
901 static void
902 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
903 struct radv_pipeline *pipeline)
904 {
905 int num_samples = pipeline->graphics.ms.num_samples;
906 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
907
908 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.needs_sample_positions)
909 cmd_buffer->sample_positions_needed = true;
910
911 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
912 return;
913
914 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
915
916 cmd_buffer->state.context_roll_without_scissor_emitted = true;
917 }
918
919 static void
920 radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer,
921 struct radv_pipeline *pipeline)
922 {
923 const struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
924
925
926 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
927 return;
928
929 if (old_pipeline &&
930 old_pipeline->graphics.binning.pa_sc_binner_cntl_0 == pipeline->graphics.binning.pa_sc_binner_cntl_0 &&
931 old_pipeline->graphics.binning.db_dfsm_control == pipeline->graphics.binning.db_dfsm_control)
932 return;
933
934 bool binning_flush = false;
935 if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 ||
936 cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 ||
937 cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 ||
938 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
939 binning_flush = !old_pipeline ||
940 G_028C44_BINNING_MODE(old_pipeline->graphics.binning.pa_sc_binner_cntl_0) !=
941 G_028C44_BINNING_MODE(pipeline->graphics.binning.pa_sc_binner_cntl_0);
942 }
943
944 radeon_set_context_reg(cmd_buffer->cs, R_028C44_PA_SC_BINNER_CNTL_0,
945 pipeline->graphics.binning.pa_sc_binner_cntl_0 |
946 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush));
947
948 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
949 radeon_set_context_reg(cmd_buffer->cs, R_028038_DB_DFSM_CONTROL,
950 pipeline->graphics.binning.db_dfsm_control);
951 } else {
952 radeon_set_context_reg(cmd_buffer->cs, R_028060_DB_DFSM_CONTROL,
953 pipeline->graphics.binning.db_dfsm_control);
954 }
955
956 cmd_buffer->state.context_roll_without_scissor_emitted = true;
957 }
958
959
960 static void
961 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
962 struct radv_shader_variant *shader)
963 {
964 uint64_t va;
965
966 if (!shader)
967 return;
968
969 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
970
971 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
972 }
973
974 static void
975 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
976 struct radv_pipeline *pipeline,
977 bool vertex_stage_only)
978 {
979 struct radv_cmd_state *state = &cmd_buffer->state;
980 uint32_t mask = state->prefetch_L2_mask;
981
982 if (vertex_stage_only) {
983 /* Fast prefetch path for starting draws as soon as possible.
984 */
985 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
986 RADV_PREFETCH_VBO_DESCRIPTORS);
987 }
988
989 if (mask & RADV_PREFETCH_VS)
990 radv_emit_shader_prefetch(cmd_buffer,
991 pipeline->shaders[MESA_SHADER_VERTEX]);
992
993 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
994 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
995
996 if (mask & RADV_PREFETCH_TCS)
997 radv_emit_shader_prefetch(cmd_buffer,
998 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
999
1000 if (mask & RADV_PREFETCH_TES)
1001 radv_emit_shader_prefetch(cmd_buffer,
1002 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
1003
1004 if (mask & RADV_PREFETCH_GS) {
1005 radv_emit_shader_prefetch(cmd_buffer,
1006 pipeline->shaders[MESA_SHADER_GEOMETRY]);
1007 if (radv_pipeline_has_gs_copy_shader(pipeline))
1008 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
1009 }
1010
1011 if (mask & RADV_PREFETCH_PS)
1012 radv_emit_shader_prefetch(cmd_buffer,
1013 pipeline->shaders[MESA_SHADER_FRAGMENT]);
1014
1015 state->prefetch_L2_mask &= ~mask;
1016 }
1017
1018 static void
1019 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
1020 {
1021 if (!cmd_buffer->device->physical_device->rad_info.rbplus_allowed)
1022 return;
1023
1024 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1025 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1026
1027 unsigned sx_ps_downconvert = 0;
1028 unsigned sx_blend_opt_epsilon = 0;
1029 unsigned sx_blend_opt_control = 0;
1030
1031 if (!cmd_buffer->state.attachments || !subpass)
1032 return;
1033
1034 for (unsigned i = 0; i < subpass->color_count; ++i) {
1035 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1036 /* We don't set the DISABLE bits, because the HW can't have holes,
1037 * so the SPI color format is set to 32-bit 1-component. */
1038 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1039 continue;
1040 }
1041
1042 int idx = subpass->color_attachments[i].attachment;
1043 struct radv_color_buffer_info *cb = &cmd_buffer->state.attachments[idx].cb;
1044
1045 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
1046 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
1047 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
1048 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
1049
1050 bool has_alpha, has_rgb;
1051
1052 /* Set if RGB and A are present. */
1053 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
1054
1055 if (format == V_028C70_COLOR_8 ||
1056 format == V_028C70_COLOR_16 ||
1057 format == V_028C70_COLOR_32)
1058 has_rgb = !has_alpha;
1059 else
1060 has_rgb = true;
1061
1062 /* Check the colormask and export format. */
1063 if (!(colormask & 0x7))
1064 has_rgb = false;
1065 if (!(colormask & 0x8))
1066 has_alpha = false;
1067
1068 if (spi_format == V_028714_SPI_SHADER_ZERO) {
1069 has_rgb = false;
1070 has_alpha = false;
1071 }
1072
1073 /* Disable value checking for disabled channels. */
1074 if (!has_rgb)
1075 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1076 if (!has_alpha)
1077 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1078
1079 /* Enable down-conversion for 32bpp and smaller formats. */
1080 switch (format) {
1081 case V_028C70_COLOR_8:
1082 case V_028C70_COLOR_8_8:
1083 case V_028C70_COLOR_8_8_8_8:
1084 /* For 1 and 2-channel formats, use the superset thereof. */
1085 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1086 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1087 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1088 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1089 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1090 }
1091 break;
1092
1093 case V_028C70_COLOR_5_6_5:
1094 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1095 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1096 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1097 }
1098 break;
1099
1100 case V_028C70_COLOR_1_5_5_5:
1101 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1102 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1103 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1104 }
1105 break;
1106
1107 case V_028C70_COLOR_4_4_4_4:
1108 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1109 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1110 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1111 }
1112 break;
1113
1114 case V_028C70_COLOR_32:
1115 if (swap == V_028C70_SWAP_STD &&
1116 spi_format == V_028714_SPI_SHADER_32_R)
1117 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1118 else if (swap == V_028C70_SWAP_ALT_REV &&
1119 spi_format == V_028714_SPI_SHADER_32_AR)
1120 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1121 break;
1122
1123 case V_028C70_COLOR_16:
1124 case V_028C70_COLOR_16_16:
1125 /* For 1-channel formats, use the superset thereof. */
1126 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1127 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1128 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1129 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1130 if (swap == V_028C70_SWAP_STD ||
1131 swap == V_028C70_SWAP_STD_REV)
1132 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1133 else
1134 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1135 }
1136 break;
1137
1138 case V_028C70_COLOR_10_11_11:
1139 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1140 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1141 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1142 }
1143 break;
1144
1145 case V_028C70_COLOR_2_10_10_10:
1146 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1147 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1148 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1149 }
1150 break;
1151 }
1152 }
1153
1154 /* Do not set the DISABLE bits for the unused attachments, as that
1155 * breaks dual source blending in SkQP and does not seem to improve
1156 * performance. */
1157
1158 if (sx_ps_downconvert == cmd_buffer->state.last_sx_ps_downconvert &&
1159 sx_blend_opt_epsilon == cmd_buffer->state.last_sx_blend_opt_epsilon &&
1160 sx_blend_opt_control == cmd_buffer->state.last_sx_blend_opt_control)
1161 return;
1162
1163 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1164 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1165 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1166 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1167
1168 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1169
1170 cmd_buffer->state.last_sx_ps_downconvert = sx_ps_downconvert;
1171 cmd_buffer->state.last_sx_blend_opt_epsilon = sx_blend_opt_epsilon;
1172 cmd_buffer->state.last_sx_blend_opt_control = sx_blend_opt_control;
1173 }
1174
1175 static void
1176 radv_emit_batch_break_on_new_ps(struct radv_cmd_buffer *cmd_buffer)
1177 {
1178 if (!cmd_buffer->device->pbb_allowed)
1179 return;
1180
1181 struct radv_binning_settings settings =
1182 radv_get_binning_settings(cmd_buffer->device->physical_device);
1183 bool break_for_new_ps =
1184 (!cmd_buffer->state.emitted_pipeline ||
1185 cmd_buffer->state.emitted_pipeline->shaders[MESA_SHADER_FRAGMENT] !=
1186 cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT]) &&
1187 (settings.context_states_per_bin > 1 ||
1188 settings.persistent_states_per_bin > 1);
1189 bool break_for_new_cb_target_mask =
1190 (!cmd_buffer->state.emitted_pipeline ||
1191 cmd_buffer->state.emitted_pipeline->graphics.cb_target_mask !=
1192 cmd_buffer->state.pipeline->graphics.cb_target_mask) &&
1193 settings.context_states_per_bin > 1;
1194
1195 if (!break_for_new_ps && !break_for_new_cb_target_mask)
1196 return;
1197
1198 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1199 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1200 }
1201
1202 static void
1203 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1204 {
1205 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1206
1207 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1208 return;
1209
1210 radv_update_multisample_state(cmd_buffer, pipeline);
1211 radv_update_binning_state(cmd_buffer, pipeline);
1212
1213 cmd_buffer->scratch_size_per_wave_needed = MAX2(cmd_buffer->scratch_size_per_wave_needed,
1214 pipeline->scratch_bytes_per_wave);
1215 cmd_buffer->scratch_waves_wanted = MAX2(cmd_buffer->scratch_waves_wanted,
1216 pipeline->max_waves);
1217
1218 if (!cmd_buffer->state.emitted_pipeline ||
1219 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1220 pipeline->graphics.can_use_guardband)
1221 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1222
1223 if (!cmd_buffer->state.emitted_pipeline ||
1224 cmd_buffer->state.emitted_pipeline->graphics.pa_su_sc_mode_cntl !=
1225 pipeline->graphics.pa_su_sc_mode_cntl)
1226 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_CULL_MODE |
1227 RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE;
1228
1229 if (!cmd_buffer->state.emitted_pipeline)
1230 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY;
1231
1232 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1233
1234 if (!cmd_buffer->state.emitted_pipeline ||
1235 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1236 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1237 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1238 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1239 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1240 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1241 }
1242
1243 radv_emit_batch_break_on_new_ps(cmd_buffer);
1244
1245 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1246 if (!pipeline->shaders[i])
1247 continue;
1248
1249 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1250 pipeline->shaders[i]->bo);
1251 }
1252
1253 if (radv_pipeline_has_gs_copy_shader(pipeline))
1254 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1255 pipeline->gs_copy_shader->bo);
1256
1257 if (unlikely(cmd_buffer->device->trace_bo))
1258 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1259
1260 cmd_buffer->state.emitted_pipeline = pipeline;
1261
1262 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1263 }
1264
1265 static void
1266 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1267 {
1268 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1269 cmd_buffer->state.dynamic.viewport.viewports);
1270 }
1271
1272 static void
1273 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1274 {
1275 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1276
1277 si_write_scissors(cmd_buffer->cs, 0, count,
1278 cmd_buffer->state.dynamic.scissor.scissors,
1279 cmd_buffer->state.dynamic.viewport.viewports,
1280 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1281
1282 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1283 }
1284
1285 static void
1286 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1287 {
1288 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1289 return;
1290
1291 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1292 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1293 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1294 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1295 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1296 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1297 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1298 }
1299 }
1300
1301 static void
1302 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1303 {
1304 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1305
1306 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1307 S_028A08_WIDTH(CLAMP(width, 0, 0xFFFF)));
1308 }
1309
1310 static void
1311 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1312 {
1313 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1314
1315 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1316 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1317 }
1318
1319 static void
1320 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1321 {
1322 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1323
1324 radeon_set_context_reg_seq(cmd_buffer->cs,
1325 R_028430_DB_STENCILREFMASK, 2);
1326 radeon_emit(cmd_buffer->cs,
1327 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1328 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1329 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1330 S_028430_STENCILOPVAL(1));
1331 radeon_emit(cmd_buffer->cs,
1332 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1333 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1334 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1335 S_028434_STENCILOPVAL_BF(1));
1336 }
1337
1338 static void
1339 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1340 {
1341 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1342
1343 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1344 fui(d->depth_bounds.min));
1345 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1346 fui(d->depth_bounds.max));
1347 }
1348
1349 static void
1350 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1351 {
1352 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1353 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1354 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1355
1356
1357 radeon_set_context_reg_seq(cmd_buffer->cs,
1358 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1359 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1360 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1361 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1362 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1363 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1364 }
1365
1366 static void
1367 radv_emit_line_stipple(struct radv_cmd_buffer *cmd_buffer)
1368 {
1369 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1370 uint32_t auto_reset_cntl = 1;
1371
1372 if (d->primitive_topology == V_008958_DI_PT_LINESTRIP)
1373 auto_reset_cntl = 2;
1374
1375 radeon_set_context_reg(cmd_buffer->cs, R_028A0C_PA_SC_LINE_STIPPLE,
1376 S_028A0C_LINE_PATTERN(d->line_stipple.pattern) |
1377 S_028A0C_REPEAT_COUNT(d->line_stipple.factor - 1) |
1378 S_028A0C_AUTO_RESET_CNTL(auto_reset_cntl));
1379 }
1380
1381 static void
1382 radv_emit_culling(struct radv_cmd_buffer *cmd_buffer, uint32_t states)
1383 {
1384 unsigned pa_su_sc_mode_cntl = cmd_buffer->state.pipeline->graphics.pa_su_sc_mode_cntl;
1385 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1386
1387 if (states & RADV_CMD_DIRTY_DYNAMIC_CULL_MODE) {
1388 pa_su_sc_mode_cntl &= C_028814_CULL_FRONT;
1389 pa_su_sc_mode_cntl |= S_028814_CULL_FRONT(!!(d->cull_mode & VK_CULL_MODE_FRONT_BIT));
1390
1391 pa_su_sc_mode_cntl &= C_028814_CULL_BACK;
1392 pa_su_sc_mode_cntl |= S_028814_CULL_BACK(!!(d->cull_mode & VK_CULL_MODE_BACK_BIT));
1393 }
1394
1395 if (states & RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE) {
1396 pa_su_sc_mode_cntl &= C_028814_FACE;
1397 pa_su_sc_mode_cntl |= S_028814_FACE(d->front_face);
1398 }
1399
1400 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
1401 pa_su_sc_mode_cntl);
1402 }
1403
1404 static void
1405 radv_emit_primitive_topology(struct radv_cmd_buffer *cmd_buffer)
1406 {
1407 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1408
1409 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1410 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
1411 cmd_buffer->cs,
1412 R_030908_VGT_PRIMITIVE_TYPE, 1,
1413 d->primitive_topology);
1414 } else {
1415 radeon_set_config_reg(cmd_buffer->cs,
1416 R_008958_VGT_PRIMITIVE_TYPE,
1417 d->primitive_topology);
1418 }
1419 }
1420
1421 static void
1422 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1423 int index,
1424 struct radv_color_buffer_info *cb,
1425 struct radv_image_view *iview,
1426 VkImageLayout layout,
1427 bool in_render_loop)
1428 {
1429 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1430 uint32_t cb_color_info = cb->cb_color_info;
1431 struct radv_image *image = iview->image;
1432
1433 if (!radv_layout_dcc_compressed(cmd_buffer->device, image, layout, in_render_loop,
1434 radv_image_queue_family_mask(image,
1435 cmd_buffer->queue_family_index,
1436 cmd_buffer->queue_family_index))) {
1437 cb_color_info &= C_028C70_DCC_ENABLE;
1438 }
1439
1440 if (!radv_layout_can_fast_clear(image, layout, in_render_loop,
1441 radv_image_queue_family_mask(image,
1442 cmd_buffer->queue_family_index,
1443 cmd_buffer->queue_family_index))) {
1444 cb_color_info &= C_028C70_COMPRESSION;
1445 }
1446
1447 if (radv_image_is_tc_compat_cmask(image) &&
1448 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1449 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1450 /* If this bit is set, the FMASK decompression operation
1451 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1452 */
1453 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1454 }
1455
1456 if (radv_image_has_fmask(image) &&
1457 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1458 radv_is_hw_resolve_pipeline(cmd_buffer))) {
1459 /* Make sure FMASK is enabled if it has been cleared because:
1460 *
1461 * 1) it's required for FMASK_DECOMPRESS operations to avoid
1462 * GPU hangs
1463 * 2) it's necessary for CB_RESOLVE which can read compressed
1464 * FMASK data anyways.
1465 */
1466 cb_color_info |= S_028C70_COMPRESSION(1);
1467 }
1468
1469 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1470 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1471 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1472 radeon_emit(cmd_buffer->cs, 0);
1473 radeon_emit(cmd_buffer->cs, 0);
1474 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1475 radeon_emit(cmd_buffer->cs, cb_color_info);
1476 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1477 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1478 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1479 radeon_emit(cmd_buffer->cs, 0);
1480 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1481 radeon_emit(cmd_buffer->cs, 0);
1482
1483 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1484 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1485
1486 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1487 cb->cb_color_base >> 32);
1488 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1489 cb->cb_color_cmask >> 32);
1490 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1491 cb->cb_color_fmask >> 32);
1492 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1493 cb->cb_dcc_base >> 32);
1494 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1495 cb->cb_color_attrib2);
1496 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1497 cb->cb_color_attrib3);
1498 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1499 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1500 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1501 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1502 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1503 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1504 radeon_emit(cmd_buffer->cs, cb_color_info);
1505 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1506 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1507 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1508 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1509 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1510 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1511
1512 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1513 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1514 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1515
1516 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1517 cb->cb_mrt_epitch);
1518 } else {
1519 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1520 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1521 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1522 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1523 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1524 radeon_emit(cmd_buffer->cs, cb_color_info);
1525 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1526 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1527 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1528 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1529 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1530 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1531
1532 if (is_vi) { /* DCC BASE */
1533 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1534 }
1535 }
1536
1537 if (radv_dcc_enabled(image, iview->base_mip)) {
1538 /* Drawing with DCC enabled also compresses colorbuffers. */
1539 VkImageSubresourceRange range = {
1540 .aspectMask = iview->aspect_mask,
1541 .baseMipLevel = iview->base_mip,
1542 .levelCount = iview->level_count,
1543 .baseArrayLayer = iview->base_layer,
1544 .layerCount = iview->layer_count,
1545 };
1546
1547 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1548 }
1549 }
1550
1551 static void
1552 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1553 struct radv_ds_buffer_info *ds,
1554 const struct radv_image_view *iview,
1555 VkImageLayout layout,
1556 bool in_render_loop, bool requires_cond_exec)
1557 {
1558 const struct radv_image *image = iview->image;
1559 uint32_t db_z_info = ds->db_z_info;
1560 uint32_t db_z_info_reg;
1561
1562 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug ||
1563 !radv_image_is_tc_compat_htile(image))
1564 return;
1565
1566 if (!radv_layout_is_htile_compressed(image, layout, in_render_loop,
1567 radv_image_queue_family_mask(image,
1568 cmd_buffer->queue_family_index,
1569 cmd_buffer->queue_family_index))) {
1570 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1571 }
1572
1573 db_z_info &= C_028040_ZRANGE_PRECISION;
1574
1575 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1576 db_z_info_reg = R_028038_DB_Z_INFO;
1577 } else {
1578 db_z_info_reg = R_028040_DB_Z_INFO;
1579 }
1580
1581 /* When we don't know the last fast clear value we need to emit a
1582 * conditional packet that will eventually skip the following
1583 * SET_CONTEXT_REG packet.
1584 */
1585 if (requires_cond_exec) {
1586 uint64_t va = radv_get_tc_compat_zrange_va(image, iview->base_mip);
1587
1588 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1589 radeon_emit(cmd_buffer->cs, va);
1590 radeon_emit(cmd_buffer->cs, va >> 32);
1591 radeon_emit(cmd_buffer->cs, 0);
1592 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1593 }
1594
1595 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1596 }
1597
1598 static void
1599 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1600 struct radv_ds_buffer_info *ds,
1601 struct radv_image_view *iview,
1602 VkImageLayout layout,
1603 bool in_render_loop)
1604 {
1605 const struct radv_image *image = iview->image;
1606 uint32_t db_z_info = ds->db_z_info;
1607 uint32_t db_stencil_info = ds->db_stencil_info;
1608
1609 if (!radv_layout_is_htile_compressed(image, layout, in_render_loop,
1610 radv_image_queue_family_mask(image,
1611 cmd_buffer->queue_family_index,
1612 cmd_buffer->queue_family_index))) {
1613 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1614 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1615 }
1616
1617 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1618 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1619
1620 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1621 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1622 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1623
1624 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1625 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1626 radeon_emit(cmd_buffer->cs, db_z_info);
1627 radeon_emit(cmd_buffer->cs, db_stencil_info);
1628 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1629 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1630 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1631 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1632
1633 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 5);
1634 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1635 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1636 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1637 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1638 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1639 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1640 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1641 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1642 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1643 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1644
1645 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1646 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1647 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1648 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1649 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1650 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1651 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1652 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1653 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1654 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1655 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1656
1657 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1658 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1659 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1660 } else {
1661 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1662
1663 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1664 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1665 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1666 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1667 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1668 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1669 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1670 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1671 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1672 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1673
1674 }
1675
1676 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1677 radv_update_zrange_precision(cmd_buffer, ds, iview, layout,
1678 in_render_loop, true);
1679
1680 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1681 ds->pa_su_poly_offset_db_fmt_cntl);
1682 }
1683
1684 /**
1685 * Update the fast clear depth/stencil values if the image is bound as a
1686 * depth/stencil buffer.
1687 */
1688 static void
1689 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1690 const struct radv_image_view *iview,
1691 VkClearDepthStencilValue ds_clear_value,
1692 VkImageAspectFlags aspects)
1693 {
1694 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1695 const struct radv_image *image = iview->image;
1696 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1697 uint32_t att_idx;
1698
1699 if (!cmd_buffer->state.attachments || !subpass)
1700 return;
1701
1702 if (!subpass->depth_stencil_attachment)
1703 return;
1704
1705 att_idx = subpass->depth_stencil_attachment->attachment;
1706 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1707 return;
1708
1709 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1710 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1711 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1712 radeon_emit(cs, ds_clear_value.stencil);
1713 radeon_emit(cs, fui(ds_clear_value.depth));
1714 } else if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1715 radeon_set_context_reg_seq(cs, R_02802C_DB_DEPTH_CLEAR, 1);
1716 radeon_emit(cs, fui(ds_clear_value.depth));
1717 } else {
1718 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1719 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 1);
1720 radeon_emit(cs, ds_clear_value.stencil);
1721 }
1722
1723 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1724 * only needed when clearing Z to 0.0.
1725 */
1726 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1727 ds_clear_value.depth == 0.0) {
1728 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1729 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1730
1731 radv_update_zrange_precision(cmd_buffer, &cmd_buffer->state.attachments[att_idx].ds,
1732 iview, layout, in_render_loop, false);
1733 }
1734
1735 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1736 }
1737
1738 /**
1739 * Set the clear depth/stencil values to the image's metadata.
1740 */
1741 static void
1742 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1743 struct radv_image *image,
1744 const VkImageSubresourceRange *range,
1745 VkClearDepthStencilValue ds_clear_value,
1746 VkImageAspectFlags aspects)
1747 {
1748 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1749 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel);
1750 uint32_t level_count = radv_get_levelCount(image, range);
1751
1752 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1753 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1754 /* Use the fastest way when both aspects are used. */
1755 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + 2 * level_count, cmd_buffer->state.predicating));
1756 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1757 S_370_WR_CONFIRM(1) |
1758 S_370_ENGINE_SEL(V_370_PFP));
1759 radeon_emit(cs, va);
1760 radeon_emit(cs, va >> 32);
1761
1762 for (uint32_t l = 0; l < level_count; l++) {
1763 radeon_emit(cs, ds_clear_value.stencil);
1764 radeon_emit(cs, fui(ds_clear_value.depth));
1765 }
1766 } else {
1767 /* Otherwise we need one WRITE_DATA packet per level. */
1768 for (uint32_t l = 0; l < level_count; l++) {
1769 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel + l);
1770 unsigned value;
1771
1772 if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1773 value = fui(ds_clear_value.depth);
1774 va += 4;
1775 } else {
1776 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1777 value = ds_clear_value.stencil;
1778 }
1779
1780 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1781 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1782 S_370_WR_CONFIRM(1) |
1783 S_370_ENGINE_SEL(V_370_PFP));
1784 radeon_emit(cs, va);
1785 radeon_emit(cs, va >> 32);
1786 radeon_emit(cs, value);
1787 }
1788 }
1789 }
1790
1791 /**
1792 * Update the TC-compat metadata value for this image.
1793 */
1794 static void
1795 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1796 struct radv_image *image,
1797 const VkImageSubresourceRange *range,
1798 uint32_t value)
1799 {
1800 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1801
1802 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug)
1803 return;
1804
1805 uint64_t va = radv_get_tc_compat_zrange_va(image, range->baseMipLevel);
1806 uint32_t level_count = radv_get_levelCount(image, range);
1807
1808 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + level_count, cmd_buffer->state.predicating));
1809 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1810 S_370_WR_CONFIRM(1) |
1811 S_370_ENGINE_SEL(V_370_PFP));
1812 radeon_emit(cs, va);
1813 radeon_emit(cs, va >> 32);
1814
1815 for (uint32_t l = 0; l < level_count; l++)
1816 radeon_emit(cs, value);
1817 }
1818
1819 static void
1820 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1821 const struct radv_image_view *iview,
1822 VkClearDepthStencilValue ds_clear_value)
1823 {
1824 VkImageSubresourceRange range = {
1825 .aspectMask = iview->aspect_mask,
1826 .baseMipLevel = iview->base_mip,
1827 .levelCount = iview->level_count,
1828 .baseArrayLayer = iview->base_layer,
1829 .layerCount = iview->layer_count,
1830 };
1831 uint32_t cond_val;
1832
1833 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1834 * depth clear value is 0.0f.
1835 */
1836 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1837
1838 radv_set_tc_compat_zrange_metadata(cmd_buffer, iview->image, &range,
1839 cond_val);
1840 }
1841
1842 /**
1843 * Update the clear depth/stencil values for this image.
1844 */
1845 void
1846 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1847 const struct radv_image_view *iview,
1848 VkClearDepthStencilValue ds_clear_value,
1849 VkImageAspectFlags aspects)
1850 {
1851 VkImageSubresourceRange range = {
1852 .aspectMask = iview->aspect_mask,
1853 .baseMipLevel = iview->base_mip,
1854 .levelCount = iview->level_count,
1855 .baseArrayLayer = iview->base_layer,
1856 .layerCount = iview->layer_count,
1857 };
1858 struct radv_image *image = iview->image;
1859
1860 assert(radv_image_has_htile(image));
1861
1862 radv_set_ds_clear_metadata(cmd_buffer, iview->image, &range,
1863 ds_clear_value, aspects);
1864
1865 if (radv_image_is_tc_compat_htile(image) &&
1866 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1867 radv_update_tc_compat_zrange_metadata(cmd_buffer, iview,
1868 ds_clear_value);
1869 }
1870
1871 radv_update_bound_fast_clear_ds(cmd_buffer, iview, ds_clear_value,
1872 aspects);
1873 }
1874
1875 /**
1876 * Load the clear depth/stencil values from the image's metadata.
1877 */
1878 static void
1879 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1880 const struct radv_image_view *iview)
1881 {
1882 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1883 const struct radv_image *image = iview->image;
1884 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1885 uint64_t va = radv_get_ds_clear_value_va(image, iview->base_mip);
1886 unsigned reg_offset = 0, reg_count = 0;
1887
1888 if (!radv_image_has_htile(image))
1889 return;
1890
1891 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1892 ++reg_count;
1893 } else {
1894 ++reg_offset;
1895 va += 4;
1896 }
1897 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1898 ++reg_count;
1899
1900 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1901
1902 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1903 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, 0));
1904 radeon_emit(cs, va);
1905 radeon_emit(cs, va >> 32);
1906 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1907 radeon_emit(cs, reg_count);
1908 } else {
1909 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1910 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1911 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1912 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1913 radeon_emit(cs, va);
1914 radeon_emit(cs, va >> 32);
1915 radeon_emit(cs, reg >> 2);
1916 radeon_emit(cs, 0);
1917
1918 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1919 radeon_emit(cs, 0);
1920 }
1921 }
1922
1923 /*
1924 * With DCC some colors don't require CMASK elimination before being
1925 * used as a texture. This sets a predicate value to determine if the
1926 * cmask eliminate is required.
1927 */
1928 void
1929 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1930 struct radv_image *image,
1931 const VkImageSubresourceRange *range, bool value)
1932 {
1933 uint64_t pred_val = value;
1934 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
1935 uint32_t level_count = radv_get_levelCount(image, range);
1936 uint32_t count = 2 * level_count;
1937
1938 assert(radv_dcc_enabled(image, range->baseMipLevel));
1939
1940 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1941 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1942 S_370_WR_CONFIRM(1) |
1943 S_370_ENGINE_SEL(V_370_PFP));
1944 radeon_emit(cmd_buffer->cs, va);
1945 radeon_emit(cmd_buffer->cs, va >> 32);
1946
1947 for (uint32_t l = 0; l < level_count; l++) {
1948 radeon_emit(cmd_buffer->cs, pred_val);
1949 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1950 }
1951 }
1952
1953 /**
1954 * Update the DCC predicate to reflect the compression state.
1955 */
1956 void
1957 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1958 struct radv_image *image,
1959 const VkImageSubresourceRange *range, bool value)
1960 {
1961 uint64_t pred_val = value;
1962 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
1963 uint32_t level_count = radv_get_levelCount(image, range);
1964 uint32_t count = 2 * level_count;
1965
1966 assert(radv_dcc_enabled(image, range->baseMipLevel));
1967
1968 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1969 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1970 S_370_WR_CONFIRM(1) |
1971 S_370_ENGINE_SEL(V_370_PFP));
1972 radeon_emit(cmd_buffer->cs, va);
1973 radeon_emit(cmd_buffer->cs, va >> 32);
1974
1975 for (uint32_t l = 0; l < level_count; l++) {
1976 radeon_emit(cmd_buffer->cs, pred_val);
1977 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1978 }
1979 }
1980
1981 /**
1982 * Update the fast clear color values if the image is bound as a color buffer.
1983 */
1984 static void
1985 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1986 struct radv_image *image,
1987 int cb_idx,
1988 uint32_t color_values[2])
1989 {
1990 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1991 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1992 uint32_t att_idx;
1993
1994 if (!cmd_buffer->state.attachments || !subpass)
1995 return;
1996
1997 att_idx = subpass->color_attachments[cb_idx].attachment;
1998 if (att_idx == VK_ATTACHMENT_UNUSED)
1999 return;
2000
2001 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
2002 return;
2003
2004 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
2005 radeon_emit(cs, color_values[0]);
2006 radeon_emit(cs, color_values[1]);
2007
2008 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2009 }
2010
2011 /**
2012 * Set the clear color values to the image's metadata.
2013 */
2014 static void
2015 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
2016 struct radv_image *image,
2017 const VkImageSubresourceRange *range,
2018 uint32_t color_values[2])
2019 {
2020 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2021 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
2022 uint32_t level_count = radv_get_levelCount(image, range);
2023 uint32_t count = 2 * level_count;
2024
2025 assert(radv_image_has_cmask(image) ||
2026 radv_dcc_enabled(image, range->baseMipLevel));
2027
2028 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
2029 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
2030 S_370_WR_CONFIRM(1) |
2031 S_370_ENGINE_SEL(V_370_PFP));
2032 radeon_emit(cs, va);
2033 radeon_emit(cs, va >> 32);
2034
2035 for (uint32_t l = 0; l < level_count; l++) {
2036 radeon_emit(cs, color_values[0]);
2037 radeon_emit(cs, color_values[1]);
2038 }
2039 }
2040
2041 /**
2042 * Update the clear color values for this image.
2043 */
2044 void
2045 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
2046 const struct radv_image_view *iview,
2047 int cb_idx,
2048 uint32_t color_values[2])
2049 {
2050 struct radv_image *image = iview->image;
2051 VkImageSubresourceRange range = {
2052 .aspectMask = iview->aspect_mask,
2053 .baseMipLevel = iview->base_mip,
2054 .levelCount = iview->level_count,
2055 .baseArrayLayer = iview->base_layer,
2056 .layerCount = iview->layer_count,
2057 };
2058
2059 assert(radv_image_has_cmask(image) ||
2060 radv_dcc_enabled(image, iview->base_mip));
2061
2062 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
2063
2064 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
2065 color_values);
2066 }
2067
2068 /**
2069 * Load the clear color values from the image's metadata.
2070 */
2071 static void
2072 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
2073 struct radv_image_view *iview,
2074 int cb_idx)
2075 {
2076 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2077 struct radv_image *image = iview->image;
2078 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
2079
2080 if (!radv_image_has_cmask(image) &&
2081 !radv_dcc_enabled(image, iview->base_mip))
2082 return;
2083
2084 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
2085
2086 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
2087 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, cmd_buffer->state.predicating));
2088 radeon_emit(cs, va);
2089 radeon_emit(cs, va >> 32);
2090 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
2091 radeon_emit(cs, 2);
2092 } else {
2093 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
2094 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2095 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2096 COPY_DATA_COUNT_SEL);
2097 radeon_emit(cs, va);
2098 radeon_emit(cs, va >> 32);
2099 radeon_emit(cs, reg >> 2);
2100 radeon_emit(cs, 0);
2101
2102 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
2103 radeon_emit(cs, 0);
2104 }
2105 }
2106
2107 static void
2108 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
2109 {
2110 int i;
2111 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
2112 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2113
2114 /* this may happen for inherited secondary recording */
2115 if (!framebuffer)
2116 return;
2117
2118 for (i = 0; i < 8; ++i) {
2119 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
2120 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2121 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2122 continue;
2123 }
2124
2125 int idx = subpass->color_attachments[i].attachment;
2126 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2127 VkImageLayout layout = subpass->color_attachments[i].layout;
2128 bool in_render_loop = subpass->color_attachments[i].in_render_loop;
2129
2130 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->bo);
2131
2132 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
2133 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
2134 radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout, in_render_loop);
2135
2136 radv_load_color_clear_metadata(cmd_buffer, iview, i);
2137 }
2138
2139 if (subpass->depth_stencil_attachment) {
2140 int idx = subpass->depth_stencil_attachment->attachment;
2141 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
2142 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
2143 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2144 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->state.attachments[idx].iview->bo);
2145
2146 radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, iview, layout, in_render_loop);
2147
2148 if (cmd_buffer->state.attachments[idx].ds.offset_scale != cmd_buffer->state.offset_scale) {
2149 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2150 cmd_buffer->state.offset_scale = cmd_buffer->state.attachments[idx].ds.offset_scale;
2151 }
2152 radv_load_ds_clear_metadata(cmd_buffer, iview);
2153 } else {
2154 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
2155 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
2156 else
2157 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
2158
2159 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2160 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2161 }
2162 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2163 S_028208_BR_X(framebuffer->width) |
2164 S_028208_BR_Y(framebuffer->height));
2165
2166 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
2167 bool disable_constant_encode =
2168 cmd_buffer->device->physical_device->rad_info.has_dcc_constant_encode;
2169 enum chip_class chip_class =
2170 cmd_buffer->device->physical_device->rad_info.chip_class;
2171 uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
2172
2173 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
2174 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
2175 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
2176 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
2177 }
2178
2179 if (cmd_buffer->device->dfsm_allowed) {
2180 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2181 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2182 }
2183
2184 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
2185 }
2186
2187 static void
2188 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer, bool indirect)
2189 {
2190 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2191 struct radv_cmd_state *state = &cmd_buffer->state;
2192
2193 if (state->index_type != state->last_index_type) {
2194 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2195 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2196 cs, R_03090C_VGT_INDEX_TYPE,
2197 2, state->index_type);
2198 } else {
2199 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2200 radeon_emit(cs, state->index_type);
2201 }
2202
2203 state->last_index_type = state->index_type;
2204 }
2205
2206 /* For the direct indexed draws we use DRAW_INDEX_2, which includes
2207 * the index_va and max_index_count already. */
2208 if (!indirect)
2209 return;
2210
2211 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2212 radeon_emit(cs, state->index_va);
2213 radeon_emit(cs, state->index_va >> 32);
2214
2215 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2216 radeon_emit(cs, state->max_index_count);
2217
2218 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
2219 }
2220
2221 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
2222 {
2223 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
2224 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2225 uint32_t pa_sc_mode_cntl_1 =
2226 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
2227 uint32_t db_count_control;
2228
2229 if(!cmd_buffer->state.active_occlusion_queries) {
2230 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2231 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2232 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2233 has_perfect_queries) {
2234 /* Re-enable out-of-order rasterization if the
2235 * bound pipeline supports it and if it's has
2236 * been disabled before starting any perfect
2237 * occlusion queries.
2238 */
2239 radeon_set_context_reg(cmd_buffer->cs,
2240 R_028A4C_PA_SC_MODE_CNTL_1,
2241 pa_sc_mode_cntl_1);
2242 }
2243 }
2244 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
2245 } else {
2246 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2247 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
2248 bool gfx10_perfect = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries;
2249
2250 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2251 /* Always enable PERFECT_ZPASS_COUNTS due to issues with partially
2252 * covered tiles, discards, and early depth testing. For more details,
2253 * see https://gitlab.freedesktop.org/mesa/mesa/-/issues/3218 */
2254 db_count_control =
2255 S_028004_PERFECT_ZPASS_COUNTS(1) |
2256 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
2257 S_028004_SAMPLE_RATE(sample_rate) |
2258 S_028004_ZPASS_ENABLE(1) |
2259 S_028004_SLICE_EVEN_ENABLE(1) |
2260 S_028004_SLICE_ODD_ENABLE(1);
2261
2262 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2263 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2264 has_perfect_queries) {
2265 /* If the bound pipeline has enabled
2266 * out-of-order rasterization, we should
2267 * disable it before starting any perfect
2268 * occlusion queries.
2269 */
2270 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2271
2272 radeon_set_context_reg(cmd_buffer->cs,
2273 R_028A4C_PA_SC_MODE_CNTL_1,
2274 pa_sc_mode_cntl_1);
2275 }
2276 } else {
2277 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2278 S_028004_SAMPLE_RATE(sample_rate);
2279 }
2280 }
2281
2282 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2283
2284 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2285 }
2286
2287 static void
2288 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2289 {
2290 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2291
2292 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2293 radv_emit_viewport(cmd_buffer);
2294
2295 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2296 !cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
2297 radv_emit_scissor(cmd_buffer);
2298
2299 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2300 radv_emit_line_width(cmd_buffer);
2301
2302 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2303 radv_emit_blend_constants(cmd_buffer);
2304
2305 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2306 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2307 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2308 radv_emit_stencil(cmd_buffer);
2309
2310 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2311 radv_emit_depth_bounds(cmd_buffer);
2312
2313 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2314 radv_emit_depth_bias(cmd_buffer);
2315
2316 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2317 radv_emit_discard_rectangle(cmd_buffer);
2318
2319 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2320 radv_emit_sample_locations(cmd_buffer);
2321
2322 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2323 radv_emit_line_stipple(cmd_buffer);
2324
2325 if (states & (RADV_CMD_DIRTY_DYNAMIC_CULL_MODE |
2326 RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE))
2327 radv_emit_culling(cmd_buffer, states);
2328
2329 if (states & RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY)
2330 radv_emit_primitive_topology(cmd_buffer);
2331
2332 cmd_buffer->state.dirty &= ~states;
2333 }
2334
2335 static void
2336 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2337 VkPipelineBindPoint bind_point)
2338 {
2339 struct radv_descriptor_state *descriptors_state =
2340 radv_get_descriptors_state(cmd_buffer, bind_point);
2341 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2342 unsigned bo_offset;
2343
2344 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2345 set->mapped_ptr,
2346 &bo_offset))
2347 return;
2348
2349 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2350 set->va += bo_offset;
2351 }
2352
2353 static void
2354 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2355 VkPipelineBindPoint bind_point)
2356 {
2357 struct radv_descriptor_state *descriptors_state =
2358 radv_get_descriptors_state(cmd_buffer, bind_point);
2359 uint32_t size = MAX_SETS * 4;
2360 uint32_t offset;
2361 void *ptr;
2362
2363 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2364 256, &offset, &ptr))
2365 return;
2366
2367 for (unsigned i = 0; i < MAX_SETS; i++) {
2368 uint32_t *uptr = ((uint32_t *)ptr) + i;
2369 uint64_t set_va = 0;
2370 struct radv_descriptor_set *set = descriptors_state->sets[i];
2371 if (descriptors_state->valid & (1u << i))
2372 set_va = set->va;
2373 uptr[0] = set_va & 0xffffffff;
2374 }
2375
2376 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2377 va += offset;
2378
2379 if (cmd_buffer->state.pipeline) {
2380 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2381 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2382 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2383
2384 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2385 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2386 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2387
2388 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2389 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2390 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2391
2392 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2393 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2394 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2395
2396 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2397 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2398 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2399 }
2400
2401 if (cmd_buffer->state.compute_pipeline)
2402 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2403 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2404 }
2405
2406 static void
2407 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2408 VkShaderStageFlags stages)
2409 {
2410 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2411 VK_PIPELINE_BIND_POINT_COMPUTE :
2412 VK_PIPELINE_BIND_POINT_GRAPHICS;
2413 struct radv_descriptor_state *descriptors_state =
2414 radv_get_descriptors_state(cmd_buffer, bind_point);
2415 struct radv_cmd_state *state = &cmd_buffer->state;
2416 bool flush_indirect_descriptors;
2417
2418 if (!descriptors_state->dirty)
2419 return;
2420
2421 if (descriptors_state->push_dirty)
2422 radv_flush_push_descriptors(cmd_buffer, bind_point);
2423
2424 flush_indirect_descriptors =
2425 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2426 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2427 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2428 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2429
2430 if (flush_indirect_descriptors)
2431 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2432
2433 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2434 cmd_buffer->cs,
2435 MAX_SETS * MESA_SHADER_STAGES * 4);
2436
2437 if (cmd_buffer->state.pipeline) {
2438 radv_foreach_stage(stage, stages) {
2439 if (!cmd_buffer->state.pipeline->shaders[stage])
2440 continue;
2441
2442 radv_emit_descriptor_pointers(cmd_buffer,
2443 cmd_buffer->state.pipeline,
2444 descriptors_state, stage);
2445 }
2446 }
2447
2448 if (cmd_buffer->state.compute_pipeline &&
2449 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2450 radv_emit_descriptor_pointers(cmd_buffer,
2451 cmd_buffer->state.compute_pipeline,
2452 descriptors_state,
2453 MESA_SHADER_COMPUTE);
2454 }
2455
2456 descriptors_state->dirty = 0;
2457 descriptors_state->push_dirty = false;
2458
2459 assert(cmd_buffer->cs->cdw <= cdw_max);
2460
2461 if (unlikely(cmd_buffer->device->trace_bo))
2462 radv_save_descriptors(cmd_buffer, bind_point);
2463 }
2464
2465 static void
2466 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2467 VkShaderStageFlags stages)
2468 {
2469 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2470 ? cmd_buffer->state.compute_pipeline
2471 : cmd_buffer->state.pipeline;
2472 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2473 VK_PIPELINE_BIND_POINT_COMPUTE :
2474 VK_PIPELINE_BIND_POINT_GRAPHICS;
2475 struct radv_descriptor_state *descriptors_state =
2476 radv_get_descriptors_state(cmd_buffer, bind_point);
2477 struct radv_pipeline_layout *layout = pipeline->layout;
2478 struct radv_shader_variant *shader, *prev_shader;
2479 bool need_push_constants = false;
2480 unsigned offset;
2481 void *ptr;
2482 uint64_t va;
2483
2484 stages &= cmd_buffer->push_constant_stages;
2485 if (!stages ||
2486 (!layout->push_constant_size && !layout->dynamic_offset_count))
2487 return;
2488
2489 radv_foreach_stage(stage, stages) {
2490 shader = radv_get_shader(pipeline, stage);
2491 if (!shader)
2492 continue;
2493
2494 need_push_constants |= shader->info.loads_push_constants;
2495 need_push_constants |= shader->info.loads_dynamic_offsets;
2496
2497 uint8_t base = shader->info.base_inline_push_consts;
2498 uint8_t count = shader->info.num_inline_push_consts;
2499
2500 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2501 AC_UD_INLINE_PUSH_CONSTANTS,
2502 count,
2503 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2504 }
2505
2506 if (need_push_constants) {
2507 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2508 16 * layout->dynamic_offset_count,
2509 256, &offset, &ptr))
2510 return;
2511
2512 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2513 memcpy((char*)ptr + layout->push_constant_size,
2514 descriptors_state->dynamic_buffers,
2515 16 * layout->dynamic_offset_count);
2516
2517 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2518 va += offset;
2519
2520 ASSERTED unsigned cdw_max =
2521 radeon_check_space(cmd_buffer->device->ws,
2522 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2523
2524 prev_shader = NULL;
2525 radv_foreach_stage(stage, stages) {
2526 shader = radv_get_shader(pipeline, stage);
2527
2528 /* Avoid redundantly emitting the address for merged stages. */
2529 if (shader && shader != prev_shader) {
2530 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2531 AC_UD_PUSH_CONSTANTS, va);
2532
2533 prev_shader = shader;
2534 }
2535 }
2536 assert(cmd_buffer->cs->cdw <= cdw_max);
2537 }
2538
2539 cmd_buffer->push_constant_stages &= ~stages;
2540 }
2541
2542 static void
2543 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2544 bool pipeline_is_dirty)
2545 {
2546 if ((pipeline_is_dirty ||
2547 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2548 cmd_buffer->state.pipeline->num_vertex_bindings &&
2549 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.has_vertex_buffers) {
2550 unsigned vb_offset;
2551 void *vb_ptr;
2552 uint32_t i = 0;
2553 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2554 uint64_t va;
2555
2556 /* allocate some descriptor state for vertex buffers */
2557 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2558 &vb_offset, &vb_ptr))
2559 return;
2560
2561 for (i = 0; i < count; i++) {
2562 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2563 uint32_t offset;
2564 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2565 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2566 unsigned num_records;
2567
2568 if (!buffer)
2569 continue;
2570
2571 va = radv_buffer_get_va(buffer->bo);
2572
2573 offset = cmd_buffer->vertex_bindings[i].offset;
2574 va += offset + buffer->offset;
2575
2576 num_records = buffer->size - offset;
2577 if (cmd_buffer->device->physical_device->rad_info.chip_class != GFX8 && stride)
2578 num_records /= stride;
2579
2580 desc[0] = va;
2581 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2582 desc[2] = num_records;
2583 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2584 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2585 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2586 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2587
2588 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2589 /* OOB_SELECT chooses the out-of-bounds check:
2590 * - 1: index >= NUM_RECORDS (Structured)
2591 * - 3: offset >= NUM_RECORDS (Raw)
2592 */
2593 int oob_select = stride ? V_008F0C_OOB_SELECT_STRUCTURED : V_008F0C_OOB_SELECT_RAW;
2594
2595 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
2596 S_008F0C_OOB_SELECT(oob_select) |
2597 S_008F0C_RESOURCE_LEVEL(1);
2598 } else {
2599 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2600 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2601 }
2602 }
2603
2604 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2605 va += vb_offset;
2606
2607 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2608 AC_UD_VS_VERTEX_BUFFERS, va);
2609
2610 cmd_buffer->state.vb_va = va;
2611 cmd_buffer->state.vb_size = count * 16;
2612 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2613 }
2614 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2615 }
2616
2617 static void
2618 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2619 {
2620 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2621 struct radv_userdata_info *loc;
2622 uint32_t base_reg;
2623
2624 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2625 if (!radv_get_shader(pipeline, stage))
2626 continue;
2627
2628 loc = radv_lookup_user_sgpr(pipeline, stage,
2629 AC_UD_STREAMOUT_BUFFERS);
2630 if (loc->sgpr_idx == -1)
2631 continue;
2632
2633 base_reg = pipeline->user_data_0[stage];
2634
2635 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2636 base_reg + loc->sgpr_idx * 4, va, false);
2637 }
2638
2639 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
2640 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2641 if (loc->sgpr_idx != -1) {
2642 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2643
2644 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2645 base_reg + loc->sgpr_idx * 4, va, false);
2646 }
2647 }
2648 }
2649
2650 static void
2651 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2652 {
2653 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2654 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2655 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2656 unsigned so_offset;
2657 void *so_ptr;
2658 uint64_t va;
2659
2660 /* Allocate some descriptor state for streamout buffers. */
2661 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2662 MAX_SO_BUFFERS * 16, 256,
2663 &so_offset, &so_ptr))
2664 return;
2665
2666 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2667 struct radv_buffer *buffer = sb[i].buffer;
2668 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2669
2670 if (!(so->enabled_mask & (1 << i)))
2671 continue;
2672
2673 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2674
2675 va += sb[i].offset;
2676
2677 /* Set the descriptor.
2678 *
2679 * On GFX8, the format must be non-INVALID, otherwise
2680 * the buffer will be considered not bound and store
2681 * instructions will be no-ops.
2682 */
2683 uint32_t size = 0xffffffff;
2684
2685 /* Compute the correct buffer size for NGG streamout
2686 * because it's used to determine the max emit per
2687 * buffer.
2688 */
2689 if (cmd_buffer->device->physical_device->use_ngg_streamout)
2690 size = buffer->size - sb[i].offset;
2691
2692 desc[0] = va;
2693 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2694 desc[2] = size;
2695 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2696 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2697 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2698 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2699
2700 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2701 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2702 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
2703 S_008F0C_RESOURCE_LEVEL(1);
2704 } else {
2705 desc[3] |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2706 }
2707 }
2708
2709 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2710 va += so_offset;
2711
2712 radv_emit_streamout_buffers(cmd_buffer, va);
2713 }
2714
2715 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2716 }
2717
2718 static void
2719 radv_flush_ngg_gs_state(struct radv_cmd_buffer *cmd_buffer)
2720 {
2721 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2722 struct radv_userdata_info *loc;
2723 uint32_t ngg_gs_state = 0;
2724 uint32_t base_reg;
2725
2726 if (!radv_pipeline_has_gs(pipeline) ||
2727 !radv_pipeline_has_ngg(pipeline))
2728 return;
2729
2730 /* By default NGG GS queries are disabled but they are enabled if the
2731 * command buffer has active GDS queries or if it's a secondary command
2732 * buffer that inherits the number of generated primitives.
2733 */
2734 if (cmd_buffer->state.active_pipeline_gds_queries ||
2735 (cmd_buffer->state.inherited_pipeline_statistics & VK_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_PRIMITIVES_BIT))
2736 ngg_gs_state = 1;
2737
2738 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_GEOMETRY,
2739 AC_UD_NGG_GS_STATE);
2740 base_reg = pipeline->user_data_0[MESA_SHADER_GEOMETRY];
2741 assert(loc->sgpr_idx != -1);
2742
2743 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
2744 ngg_gs_state);
2745 }
2746
2747 static void
2748 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2749 {
2750 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2751 radv_flush_streamout_descriptors(cmd_buffer);
2752 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2753 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2754 radv_flush_ngg_gs_state(cmd_buffer);
2755 }
2756
2757 struct radv_draw_info {
2758 /**
2759 * Number of vertices.
2760 */
2761 uint32_t count;
2762
2763 /**
2764 * Index of the first vertex.
2765 */
2766 int32_t vertex_offset;
2767
2768 /**
2769 * First instance id.
2770 */
2771 uint32_t first_instance;
2772
2773 /**
2774 * Number of instances.
2775 */
2776 uint32_t instance_count;
2777
2778 /**
2779 * First index (indexed draws only).
2780 */
2781 uint32_t first_index;
2782
2783 /**
2784 * Whether it's an indexed draw.
2785 */
2786 bool indexed;
2787
2788 /**
2789 * Indirect draw parameters resource.
2790 */
2791 struct radv_buffer *indirect;
2792 uint64_t indirect_offset;
2793 uint32_t stride;
2794
2795 /**
2796 * Draw count parameters resource.
2797 */
2798 struct radv_buffer *count_buffer;
2799 uint64_t count_buffer_offset;
2800
2801 /**
2802 * Stream output parameters resource.
2803 */
2804 struct radv_buffer *strmout_buffer;
2805 uint64_t strmout_buffer_offset;
2806 };
2807
2808 static uint32_t
2809 radv_get_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2810 {
2811 switch (cmd_buffer->state.index_type) {
2812 case V_028A7C_VGT_INDEX_8:
2813 return 0xffu;
2814 case V_028A7C_VGT_INDEX_16:
2815 return 0xffffu;
2816 case V_028A7C_VGT_INDEX_32:
2817 return 0xffffffffu;
2818 default:
2819 unreachable("invalid index type");
2820 }
2821 }
2822
2823 static void
2824 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
2825 bool instanced_draw, bool indirect_draw,
2826 bool count_from_stream_output,
2827 uint32_t draw_vertex_count)
2828 {
2829 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2830 struct radv_cmd_state *state = &cmd_buffer->state;
2831 unsigned topology = state->dynamic.primitive_topology;
2832 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2833 unsigned ia_multi_vgt_param;
2834
2835 ia_multi_vgt_param =
2836 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2837 indirect_draw,
2838 count_from_stream_output,
2839 draw_vertex_count,
2840 topology);
2841
2842 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2843 if (info->chip_class == GFX9) {
2844 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2845 cs,
2846 R_030960_IA_MULTI_VGT_PARAM,
2847 4, ia_multi_vgt_param);
2848 } else if (info->chip_class >= GFX7) {
2849 radeon_set_context_reg_idx(cs,
2850 R_028AA8_IA_MULTI_VGT_PARAM,
2851 1, ia_multi_vgt_param);
2852 } else {
2853 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2854 ia_multi_vgt_param);
2855 }
2856 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2857 }
2858 }
2859
2860 static void
2861 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2862 const struct radv_draw_info *draw_info)
2863 {
2864 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2865 struct radv_cmd_state *state = &cmd_buffer->state;
2866 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2867 int32_t primitive_reset_en;
2868
2869 /* Draw state. */
2870 if (info->chip_class < GFX10) {
2871 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2872 draw_info->indirect,
2873 !!draw_info->strmout_buffer,
2874 draw_info->indirect ? 0 : draw_info->count);
2875 }
2876
2877 /* Primitive restart. */
2878 primitive_reset_en =
2879 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2880
2881 if (primitive_reset_en != state->last_primitive_reset_en) {
2882 state->last_primitive_reset_en = primitive_reset_en;
2883 if (info->chip_class >= GFX9) {
2884 radeon_set_uconfig_reg(cs,
2885 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2886 primitive_reset_en);
2887 } else {
2888 radeon_set_context_reg(cs,
2889 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2890 primitive_reset_en);
2891 }
2892 }
2893
2894 if (primitive_reset_en) {
2895 uint32_t primitive_reset_index =
2896 radv_get_primitive_reset_index(cmd_buffer);
2897
2898 if (primitive_reset_index != state->last_primitive_reset_index) {
2899 radeon_set_context_reg(cs,
2900 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2901 primitive_reset_index);
2902 state->last_primitive_reset_index = primitive_reset_index;
2903 }
2904 }
2905
2906 if (draw_info->strmout_buffer) {
2907 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2908
2909 va += draw_info->strmout_buffer->offset +
2910 draw_info->strmout_buffer_offset;
2911
2912 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2913 draw_info->stride);
2914
2915 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2916 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2917 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2918 COPY_DATA_WR_CONFIRM);
2919 radeon_emit(cs, va);
2920 radeon_emit(cs, va >> 32);
2921 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2922 radeon_emit(cs, 0); /* unused */
2923
2924 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2925 }
2926 }
2927
2928 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2929 VkPipelineStageFlags src_stage_mask)
2930 {
2931 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2932 VK_PIPELINE_STAGE_TRANSFER_BIT |
2933 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2934 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2935 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2936 }
2937
2938 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2939 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2940 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2941 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2942 VK_PIPELINE_STAGE_TRANSFER_BIT |
2943 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2944 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2945 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2946 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2947 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2948 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2949 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2950 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2951 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2952 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2953 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2954 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2955 }
2956 }
2957
2958 static enum radv_cmd_flush_bits
2959 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2960 VkAccessFlags src_flags,
2961 struct radv_image *image)
2962 {
2963 bool flush_CB_meta = true, flush_DB_meta = true;
2964 enum radv_cmd_flush_bits flush_bits = 0;
2965 uint32_t b;
2966
2967 if (image) {
2968 if (!radv_image_has_CB_metadata(image))
2969 flush_CB_meta = false;
2970 if (!radv_image_has_htile(image))
2971 flush_DB_meta = false;
2972 }
2973
2974 for_each_bit(b, src_flags) {
2975 switch ((VkAccessFlagBits)(1 << b)) {
2976 case VK_ACCESS_SHADER_WRITE_BIT:
2977 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2978 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2979 flush_bits |= RADV_CMD_FLAG_WB_L2;
2980 break;
2981 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2982 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2983 if (flush_CB_meta)
2984 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2985 break;
2986 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2987 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2988 if (flush_DB_meta)
2989 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2990 break;
2991 case VK_ACCESS_TRANSFER_WRITE_BIT:
2992 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2993 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2994 RADV_CMD_FLAG_INV_L2;
2995
2996 if (flush_CB_meta)
2997 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2998 if (flush_DB_meta)
2999 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3000 break;
3001 case VK_ACCESS_MEMORY_WRITE_BIT:
3002 flush_bits |= RADV_CMD_FLAG_INV_L2 |
3003 RADV_CMD_FLAG_WB_L2 |
3004 RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3005 RADV_CMD_FLAG_FLUSH_AND_INV_DB;
3006
3007 if (flush_CB_meta)
3008 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3009 if (flush_DB_meta)
3010 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3011 break;
3012 default:
3013 break;
3014 }
3015 }
3016 return flush_bits;
3017 }
3018
3019 static enum radv_cmd_flush_bits
3020 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
3021 VkAccessFlags dst_flags,
3022 struct radv_image *image)
3023 {
3024 bool flush_CB_meta = true, flush_DB_meta = true;
3025 enum radv_cmd_flush_bits flush_bits = 0;
3026 bool flush_CB = true, flush_DB = true;
3027 bool image_is_coherent = false;
3028 uint32_t b;
3029
3030 if (image) {
3031 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
3032 flush_CB = false;
3033 flush_DB = false;
3034 }
3035
3036 if (!radv_image_has_CB_metadata(image))
3037 flush_CB_meta = false;
3038 if (!radv_image_has_htile(image))
3039 flush_DB_meta = false;
3040
3041 /* TODO: implement shader coherent for GFX10 */
3042
3043 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
3044 if (image->info.samples == 1 &&
3045 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
3046 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
3047 !vk_format_is_stencil(image->vk_format)) {
3048 /* Single-sample color and single-sample depth
3049 * (not stencil) are coherent with shaders on
3050 * GFX9.
3051 */
3052 image_is_coherent = true;
3053 }
3054 }
3055 }
3056
3057 for_each_bit(b, dst_flags) {
3058 switch ((VkAccessFlagBits)(1 << b)) {
3059 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
3060 case VK_ACCESS_INDEX_READ_BIT:
3061 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
3062 break;
3063 case VK_ACCESS_UNIFORM_READ_BIT:
3064 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
3065 break;
3066 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
3067 case VK_ACCESS_TRANSFER_READ_BIT:
3068 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
3069 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
3070 RADV_CMD_FLAG_INV_L2;
3071 break;
3072 case VK_ACCESS_SHADER_READ_BIT:
3073 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
3074 /* Unlike LLVM, ACO uses SMEM for SSBOs and we have to
3075 * invalidate the scalar cache. */
3076 if (!cmd_buffer->device->physical_device->use_llvm)
3077 flush_bits |= RADV_CMD_FLAG_INV_SCACHE;
3078
3079 if (!image_is_coherent)
3080 flush_bits |= RADV_CMD_FLAG_INV_L2;
3081 break;
3082 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
3083 if (flush_CB)
3084 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
3085 if (flush_CB_meta)
3086 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3087 break;
3088 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
3089 if (flush_DB)
3090 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
3091 if (flush_DB_meta)
3092 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3093 break;
3094 case VK_ACCESS_MEMORY_READ_BIT:
3095 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
3096 RADV_CMD_FLAG_INV_SCACHE |
3097 RADV_CMD_FLAG_INV_L2;
3098 if (flush_CB)
3099 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
3100 if (flush_CB_meta)
3101 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3102 if (flush_DB)
3103 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
3104 if (flush_DB_meta)
3105 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3106 break;
3107 default:
3108 break;
3109 }
3110 }
3111 return flush_bits;
3112 }
3113
3114 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
3115 const struct radv_subpass_barrier *barrier)
3116 {
3117 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
3118 NULL);
3119 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
3120 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
3121 NULL);
3122 }
3123
3124 uint32_t
3125 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
3126 {
3127 struct radv_cmd_state *state = &cmd_buffer->state;
3128 uint32_t subpass_id = state->subpass - state->pass->subpasses;
3129
3130 /* The id of this subpass shouldn't exceed the number of subpasses in
3131 * this render pass minus 1.
3132 */
3133 assert(subpass_id < state->pass->subpass_count);
3134 return subpass_id;
3135 }
3136
3137 static struct radv_sample_locations_state *
3138 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3139 uint32_t att_idx,
3140 bool begin_subpass)
3141 {
3142 struct radv_cmd_state *state = &cmd_buffer->state;
3143 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
3144 struct radv_image_view *view = state->attachments[att_idx].iview;
3145
3146 if (view->image->info.samples == 1)
3147 return NULL;
3148
3149 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
3150 /* Return the initial sample locations if this is the initial
3151 * layout transition of the given subpass attachemnt.
3152 */
3153 if (state->attachments[att_idx].sample_location.count > 0)
3154 return &state->attachments[att_idx].sample_location;
3155 } else {
3156 /* Otherwise return the subpass sample locations if defined. */
3157 if (state->subpass_sample_locs) {
3158 /* Because the driver sets the current subpass before
3159 * initial layout transitions, we should use the sample
3160 * locations from the previous subpass to avoid an
3161 * off-by-one problem. Otherwise, use the sample
3162 * locations for the current subpass for final layout
3163 * transitions.
3164 */
3165 if (begin_subpass)
3166 subpass_id--;
3167
3168 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
3169 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
3170 return &state->subpass_sample_locs[i].sample_location;
3171 }
3172 }
3173 }
3174
3175 return NULL;
3176 }
3177
3178 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
3179 struct radv_subpass_attachment att,
3180 bool begin_subpass)
3181 {
3182 unsigned idx = att.attachment;
3183 struct radv_image_view *view = cmd_buffer->state.attachments[idx].iview;
3184 struct radv_sample_locations_state *sample_locs;
3185 VkImageSubresourceRange range;
3186 range.aspectMask = view->aspect_mask;
3187 range.baseMipLevel = view->base_mip;
3188 range.levelCount = 1;
3189 range.baseArrayLayer = view->base_layer;
3190 range.layerCount = cmd_buffer->state.framebuffer->layers;
3191
3192 if (cmd_buffer->state.subpass->view_mask) {
3193 /* If the current subpass uses multiview, the driver might have
3194 * performed a fast color/depth clear to the whole image
3195 * (including all layers). To make sure the driver will
3196 * decompress the image correctly (if needed), we have to
3197 * account for the "real" number of layers. If the view mask is
3198 * sparse, this will decompress more layers than needed.
3199 */
3200 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
3201 }
3202
3203 /* Get the subpass sample locations for the given attachment, if NULL
3204 * is returned the driver will use the default HW locations.
3205 */
3206 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
3207 begin_subpass);
3208
3209 /* Determine if the subpass uses separate depth/stencil layouts. */
3210 bool uses_separate_depth_stencil_layouts = false;
3211 if ((cmd_buffer->state.attachments[idx].current_layout !=
3212 cmd_buffer->state.attachments[idx].current_stencil_layout) ||
3213 (att.layout != att.stencil_layout)) {
3214 uses_separate_depth_stencil_layouts = true;
3215 }
3216
3217 /* For separate layouts, perform depth and stencil transitions
3218 * separately.
3219 */
3220 if (uses_separate_depth_stencil_layouts &&
3221 (range.aspectMask == (VK_IMAGE_ASPECT_DEPTH_BIT |
3222 VK_IMAGE_ASPECT_STENCIL_BIT))) {
3223 /* Depth-only transitions. */
3224 range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3225 radv_handle_image_transition(cmd_buffer,
3226 view->image,
3227 cmd_buffer->state.attachments[idx].current_layout,
3228 cmd_buffer->state.attachments[idx].current_in_render_loop,
3229 att.layout, att.in_render_loop,
3230 0, 0, &range, sample_locs);
3231
3232 /* Stencil-only transitions. */
3233 range.aspectMask = VK_IMAGE_ASPECT_STENCIL_BIT;
3234 radv_handle_image_transition(cmd_buffer,
3235 view->image,
3236 cmd_buffer->state.attachments[idx].current_stencil_layout,
3237 cmd_buffer->state.attachments[idx].current_in_render_loop,
3238 att.stencil_layout, att.in_render_loop,
3239 0, 0, &range, sample_locs);
3240 } else {
3241 radv_handle_image_transition(cmd_buffer,
3242 view->image,
3243 cmd_buffer->state.attachments[idx].current_layout,
3244 cmd_buffer->state.attachments[idx].current_in_render_loop,
3245 att.layout, att.in_render_loop,
3246 0, 0, &range, sample_locs);
3247 }
3248
3249 cmd_buffer->state.attachments[idx].current_layout = att.layout;
3250 cmd_buffer->state.attachments[idx].current_stencil_layout = att.stencil_layout;
3251 cmd_buffer->state.attachments[idx].current_in_render_loop = att.in_render_loop;
3252
3253
3254 }
3255
3256 void
3257 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
3258 const struct radv_subpass *subpass)
3259 {
3260 cmd_buffer->state.subpass = subpass;
3261
3262 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
3263 }
3264
3265 static VkResult
3266 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3267 struct radv_render_pass *pass,
3268 const VkRenderPassBeginInfo *info)
3269 {
3270 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
3271 vk_find_struct_const(info->pNext,
3272 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
3273 struct radv_cmd_state *state = &cmd_buffer->state;
3274
3275 if (!sample_locs) {
3276 state->subpass_sample_locs = NULL;
3277 return VK_SUCCESS;
3278 }
3279
3280 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
3281 const VkAttachmentSampleLocationsEXT *att_sample_locs =
3282 &sample_locs->pAttachmentInitialSampleLocations[i];
3283 uint32_t att_idx = att_sample_locs->attachmentIndex;
3284 struct radv_image *image = cmd_buffer->state.attachments[att_idx].iview->image;
3285
3286 assert(vk_format_is_depth_or_stencil(image->vk_format));
3287
3288 /* From the Vulkan spec 1.1.108:
3289 *
3290 * "If the image referenced by the framebuffer attachment at
3291 * index attachmentIndex was not created with
3292 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
3293 * then the values specified in sampleLocationsInfo are
3294 * ignored."
3295 */
3296 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
3297 continue;
3298
3299 const VkSampleLocationsInfoEXT *sample_locs_info =
3300 &att_sample_locs->sampleLocationsInfo;
3301
3302 state->attachments[att_idx].sample_location.per_pixel =
3303 sample_locs_info->sampleLocationsPerPixel;
3304 state->attachments[att_idx].sample_location.grid_size =
3305 sample_locs_info->sampleLocationGridSize;
3306 state->attachments[att_idx].sample_location.count =
3307 sample_locs_info->sampleLocationsCount;
3308 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
3309 sample_locs_info->pSampleLocations,
3310 sample_locs_info->sampleLocationsCount);
3311 }
3312
3313 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
3314 sample_locs->postSubpassSampleLocationsCount *
3315 sizeof(state->subpass_sample_locs[0]),
3316 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3317 if (state->subpass_sample_locs == NULL) {
3318 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3319 return cmd_buffer->record_result;
3320 }
3321
3322 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
3323
3324 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
3325 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
3326 &sample_locs->pPostSubpassSampleLocations[i];
3327 const VkSampleLocationsInfoEXT *sample_locs_info =
3328 &subpass_sample_locs_info->sampleLocationsInfo;
3329
3330 state->subpass_sample_locs[i].subpass_idx =
3331 subpass_sample_locs_info->subpassIndex;
3332 state->subpass_sample_locs[i].sample_location.per_pixel =
3333 sample_locs_info->sampleLocationsPerPixel;
3334 state->subpass_sample_locs[i].sample_location.grid_size =
3335 sample_locs_info->sampleLocationGridSize;
3336 state->subpass_sample_locs[i].sample_location.count =
3337 sample_locs_info->sampleLocationsCount;
3338 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
3339 sample_locs_info->pSampleLocations,
3340 sample_locs_info->sampleLocationsCount);
3341 }
3342
3343 return VK_SUCCESS;
3344 }
3345
3346 static VkResult
3347 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
3348 struct radv_render_pass *pass,
3349 const VkRenderPassBeginInfo *info)
3350 {
3351 struct radv_cmd_state *state = &cmd_buffer->state;
3352 const struct VkRenderPassAttachmentBeginInfo *attachment_info = NULL;
3353
3354 if (info) {
3355 attachment_info = vk_find_struct_const(info->pNext,
3356 RENDER_PASS_ATTACHMENT_BEGIN_INFO);
3357 }
3358
3359
3360 if (pass->attachment_count == 0) {
3361 state->attachments = NULL;
3362 return VK_SUCCESS;
3363 }
3364
3365 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
3366 pass->attachment_count *
3367 sizeof(state->attachments[0]),
3368 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3369 if (state->attachments == NULL) {
3370 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3371 return cmd_buffer->record_result;
3372 }
3373
3374 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
3375 struct radv_render_pass_attachment *att = &pass->attachments[i];
3376 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
3377 VkImageAspectFlags clear_aspects = 0;
3378
3379 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
3380 /* color attachment */
3381 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3382 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
3383 }
3384 } else {
3385 /* depthstencil attachment */
3386 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
3387 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3388 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
3389 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3390 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
3391 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3392 }
3393 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3394 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3395 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3396 }
3397 }
3398
3399 state->attachments[i].pending_clear_aspects = clear_aspects;
3400 state->attachments[i].cleared_views = 0;
3401 if (clear_aspects && info) {
3402 assert(info->clearValueCount > i);
3403 state->attachments[i].clear_value = info->pClearValues[i];
3404 }
3405
3406 state->attachments[i].current_layout = att->initial_layout;
3407 state->attachments[i].current_stencil_layout = att->stencil_initial_layout;
3408 state->attachments[i].sample_location.count = 0;
3409
3410 struct radv_image_view *iview;
3411 if (attachment_info && attachment_info->attachmentCount > i) {
3412 iview = radv_image_view_from_handle(attachment_info->pAttachments[i]);
3413 } else {
3414 iview = state->framebuffer->attachments[i];
3415 }
3416
3417 state->attachments[i].iview = iview;
3418 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3419 radv_initialise_ds_surface(cmd_buffer->device, &state->attachments[i].ds, iview);
3420 } else {
3421 radv_initialise_color_surface(cmd_buffer->device, &state->attachments[i].cb, iview);
3422 }
3423 }
3424
3425 return VK_SUCCESS;
3426 }
3427
3428 VkResult radv_AllocateCommandBuffers(
3429 VkDevice _device,
3430 const VkCommandBufferAllocateInfo *pAllocateInfo,
3431 VkCommandBuffer *pCommandBuffers)
3432 {
3433 RADV_FROM_HANDLE(radv_device, device, _device);
3434 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
3435
3436 VkResult result = VK_SUCCESS;
3437 uint32_t i;
3438
3439 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
3440
3441 if (!list_is_empty(&pool->free_cmd_buffers)) {
3442 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
3443
3444 list_del(&cmd_buffer->pool_link);
3445 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
3446
3447 result = radv_reset_cmd_buffer(cmd_buffer);
3448 cmd_buffer->level = pAllocateInfo->level;
3449
3450 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
3451 } else {
3452 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
3453 &pCommandBuffers[i]);
3454 }
3455 if (result != VK_SUCCESS)
3456 break;
3457 }
3458
3459 if (result != VK_SUCCESS) {
3460 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
3461 i, pCommandBuffers);
3462
3463 /* From the Vulkan 1.0.66 spec:
3464 *
3465 * "vkAllocateCommandBuffers can be used to create multiple
3466 * command buffers. If the creation of any of those command
3467 * buffers fails, the implementation must destroy all
3468 * successfully created command buffer objects from this
3469 * command, set all entries of the pCommandBuffers array to
3470 * NULL and return the error."
3471 */
3472 memset(pCommandBuffers, 0,
3473 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
3474 }
3475
3476 return result;
3477 }
3478
3479 void radv_FreeCommandBuffers(
3480 VkDevice device,
3481 VkCommandPool commandPool,
3482 uint32_t commandBufferCount,
3483 const VkCommandBuffer *pCommandBuffers)
3484 {
3485 for (uint32_t i = 0; i < commandBufferCount; i++) {
3486 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
3487
3488 if (cmd_buffer) {
3489 if (cmd_buffer->pool) {
3490 list_del(&cmd_buffer->pool_link);
3491 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3492 } else
3493 radv_cmd_buffer_destroy(cmd_buffer);
3494
3495 }
3496 }
3497 }
3498
3499 VkResult radv_ResetCommandBuffer(
3500 VkCommandBuffer commandBuffer,
3501 VkCommandBufferResetFlags flags)
3502 {
3503 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3504 return radv_reset_cmd_buffer(cmd_buffer);
3505 }
3506
3507 VkResult radv_BeginCommandBuffer(
3508 VkCommandBuffer commandBuffer,
3509 const VkCommandBufferBeginInfo *pBeginInfo)
3510 {
3511 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3512 VkResult result = VK_SUCCESS;
3513
3514 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3515 /* If the command buffer has already been resetted with
3516 * vkResetCommandBuffer, no need to do it again.
3517 */
3518 result = radv_reset_cmd_buffer(cmd_buffer);
3519 if (result != VK_SUCCESS)
3520 return result;
3521 }
3522
3523 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3524 cmd_buffer->state.last_primitive_reset_en = -1;
3525 cmd_buffer->state.last_index_type = -1;
3526 cmd_buffer->state.last_num_instances = -1;
3527 cmd_buffer->state.last_vertex_offset = -1;
3528 cmd_buffer->state.last_first_instance = -1;
3529 cmd_buffer->state.predication_type = -1;
3530 cmd_buffer->state.last_sx_ps_downconvert = -1;
3531 cmd_buffer->state.last_sx_blend_opt_epsilon = -1;
3532 cmd_buffer->state.last_sx_blend_opt_control = -1;
3533 cmd_buffer->usage_flags = pBeginInfo->flags;
3534
3535 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3536 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3537 assert(pBeginInfo->pInheritanceInfo);
3538 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3539 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3540
3541 struct radv_subpass *subpass =
3542 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3543
3544 if (cmd_buffer->state.framebuffer) {
3545 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3546 if (result != VK_SUCCESS)
3547 return result;
3548 }
3549
3550 cmd_buffer->state.inherited_pipeline_statistics =
3551 pBeginInfo->pInheritanceInfo->pipelineStatistics;
3552
3553 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3554 }
3555
3556 if (unlikely(cmd_buffer->device->trace_bo))
3557 radv_cmd_buffer_trace_emit(cmd_buffer);
3558
3559 radv_describe_begin_cmd_buffer(cmd_buffer);
3560
3561 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3562
3563 return result;
3564 }
3565
3566 void radv_CmdBindVertexBuffers(
3567 VkCommandBuffer commandBuffer,
3568 uint32_t firstBinding,
3569 uint32_t bindingCount,
3570 const VkBuffer* pBuffers,
3571 const VkDeviceSize* pOffsets)
3572 {
3573 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3574 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3575 bool changed = false;
3576
3577 /* We have to defer setting up vertex buffer since we need the buffer
3578 * stride from the pipeline. */
3579
3580 assert(firstBinding + bindingCount <= MAX_VBS);
3581 for (uint32_t i = 0; i < bindingCount; i++) {
3582 RADV_FROM_HANDLE(radv_buffer, buffer, pBuffers[i]);
3583 uint32_t idx = firstBinding + i;
3584
3585 if (!changed &&
3586 (vb[idx].buffer != buffer ||
3587 vb[idx].offset != pOffsets[i])) {
3588 changed = true;
3589 }
3590
3591 vb[idx].buffer = buffer;
3592 vb[idx].offset = pOffsets[i];
3593
3594 if (buffer) {
3595 radv_cs_add_buffer(cmd_buffer->device->ws,
3596 cmd_buffer->cs, vb[idx].buffer->bo);
3597 }
3598 }
3599
3600 if (!changed) {
3601 /* No state changes. */
3602 return;
3603 }
3604
3605 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3606 }
3607
3608 static uint32_t
3609 vk_to_index_type(VkIndexType type)
3610 {
3611 switch (type) {
3612 case VK_INDEX_TYPE_UINT8_EXT:
3613 return V_028A7C_VGT_INDEX_8;
3614 case VK_INDEX_TYPE_UINT16:
3615 return V_028A7C_VGT_INDEX_16;
3616 case VK_INDEX_TYPE_UINT32:
3617 return V_028A7C_VGT_INDEX_32;
3618 default:
3619 unreachable("invalid index type");
3620 }
3621 }
3622
3623 static uint32_t
3624 radv_get_vgt_index_size(uint32_t type)
3625 {
3626 switch (type) {
3627 case V_028A7C_VGT_INDEX_8:
3628 return 1;
3629 case V_028A7C_VGT_INDEX_16:
3630 return 2;
3631 case V_028A7C_VGT_INDEX_32:
3632 return 4;
3633 default:
3634 unreachable("invalid index type");
3635 }
3636 }
3637
3638 void radv_CmdBindIndexBuffer(
3639 VkCommandBuffer commandBuffer,
3640 VkBuffer buffer,
3641 VkDeviceSize offset,
3642 VkIndexType indexType)
3643 {
3644 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3645 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3646
3647 if (cmd_buffer->state.index_buffer == index_buffer &&
3648 cmd_buffer->state.index_offset == offset &&
3649 cmd_buffer->state.index_type == indexType) {
3650 /* No state changes. */
3651 return;
3652 }
3653
3654 cmd_buffer->state.index_buffer = index_buffer;
3655 cmd_buffer->state.index_offset = offset;
3656 cmd_buffer->state.index_type = vk_to_index_type(indexType);
3657 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3658 cmd_buffer->state.index_va += index_buffer->offset + offset;
3659
3660 int index_size = radv_get_vgt_index_size(vk_to_index_type(indexType));
3661 cmd_buffer->state.max_index_count = (index_buffer->size - offset) / index_size;
3662 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3663 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3664 }
3665
3666
3667 static void
3668 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3669 VkPipelineBindPoint bind_point,
3670 struct radv_descriptor_set *set, unsigned idx)
3671 {
3672 struct radeon_winsys *ws = cmd_buffer->device->ws;
3673
3674 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3675
3676 assert(set);
3677 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3678
3679 if (!cmd_buffer->device->use_global_bo_list) {
3680 for (unsigned j = 0; j < set->buffer_count; ++j)
3681 if (set->descriptors[j])
3682 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3683 }
3684
3685 if(set->bo)
3686 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3687 }
3688
3689 void radv_CmdBindDescriptorSets(
3690 VkCommandBuffer commandBuffer,
3691 VkPipelineBindPoint pipelineBindPoint,
3692 VkPipelineLayout _layout,
3693 uint32_t firstSet,
3694 uint32_t descriptorSetCount,
3695 const VkDescriptorSet* pDescriptorSets,
3696 uint32_t dynamicOffsetCount,
3697 const uint32_t* pDynamicOffsets)
3698 {
3699 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3700 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3701 unsigned dyn_idx = 0;
3702
3703 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3704 struct radv_descriptor_state *descriptors_state =
3705 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3706
3707 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3708 unsigned idx = i + firstSet;
3709 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3710
3711 /* If the set is already bound we only need to update the
3712 * (potentially changed) dynamic offsets. */
3713 if (descriptors_state->sets[idx] != set ||
3714 !(descriptors_state->valid & (1u << idx))) {
3715 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3716 }
3717
3718 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3719 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3720 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3721 assert(dyn_idx < dynamicOffsetCount);
3722
3723 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3724 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3725 dst[0] = va;
3726 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3727 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3728 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3729 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3730 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3731 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3732
3733 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
3734 dst[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3735 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3736 S_008F0C_RESOURCE_LEVEL(1);
3737 } else {
3738 dst[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3739 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3740 }
3741
3742 cmd_buffer->push_constant_stages |=
3743 set->layout->dynamic_shader_stages;
3744 }
3745 }
3746 }
3747
3748 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3749 struct radv_descriptor_set *set,
3750 struct radv_descriptor_set_layout *layout,
3751 VkPipelineBindPoint bind_point)
3752 {
3753 struct radv_descriptor_state *descriptors_state =
3754 radv_get_descriptors_state(cmd_buffer, bind_point);
3755 set->size = layout->size;
3756 set->layout = layout;
3757
3758 if (descriptors_state->push_set.capacity < set->size) {
3759 size_t new_size = MAX2(set->size, 1024);
3760 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3761 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3762
3763 free(set->mapped_ptr);
3764 set->mapped_ptr = malloc(new_size);
3765
3766 if (!set->mapped_ptr) {
3767 descriptors_state->push_set.capacity = 0;
3768 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3769 return false;
3770 }
3771
3772 descriptors_state->push_set.capacity = new_size;
3773 }
3774
3775 return true;
3776 }
3777
3778 void radv_meta_push_descriptor_set(
3779 struct radv_cmd_buffer* cmd_buffer,
3780 VkPipelineBindPoint pipelineBindPoint,
3781 VkPipelineLayout _layout,
3782 uint32_t set,
3783 uint32_t descriptorWriteCount,
3784 const VkWriteDescriptorSet* pDescriptorWrites)
3785 {
3786 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3787 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3788 unsigned bo_offset;
3789
3790 assert(set == 0);
3791 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3792
3793 push_set->size = layout->set[set].layout->size;
3794 push_set->layout = layout->set[set].layout;
3795
3796 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3797 &bo_offset,
3798 (void**) &push_set->mapped_ptr))
3799 return;
3800
3801 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3802 push_set->va += bo_offset;
3803
3804 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3805 radv_descriptor_set_to_handle(push_set),
3806 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3807
3808 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3809 }
3810
3811 void radv_CmdPushDescriptorSetKHR(
3812 VkCommandBuffer commandBuffer,
3813 VkPipelineBindPoint pipelineBindPoint,
3814 VkPipelineLayout _layout,
3815 uint32_t set,
3816 uint32_t descriptorWriteCount,
3817 const VkWriteDescriptorSet* pDescriptorWrites)
3818 {
3819 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3820 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3821 struct radv_descriptor_state *descriptors_state =
3822 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3823 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3824
3825 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3826
3827 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3828 layout->set[set].layout,
3829 pipelineBindPoint))
3830 return;
3831
3832 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3833 * because it is invalid, according to Vulkan spec.
3834 */
3835 for (int i = 0; i < descriptorWriteCount; i++) {
3836 ASSERTED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
3837 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
3838 }
3839
3840 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3841 radv_descriptor_set_to_handle(push_set),
3842 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3843
3844 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3845 descriptors_state->push_dirty = true;
3846 }
3847
3848 void radv_CmdPushDescriptorSetWithTemplateKHR(
3849 VkCommandBuffer commandBuffer,
3850 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
3851 VkPipelineLayout _layout,
3852 uint32_t set,
3853 const void* pData)
3854 {
3855 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3856 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3857 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
3858 struct radv_descriptor_state *descriptors_state =
3859 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
3860 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3861
3862 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3863
3864 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3865 layout->set[set].layout,
3866 templ->bind_point))
3867 return;
3868
3869 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
3870 descriptorUpdateTemplate, pData);
3871
3872 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
3873 descriptors_state->push_dirty = true;
3874 }
3875
3876 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
3877 VkPipelineLayout layout,
3878 VkShaderStageFlags stageFlags,
3879 uint32_t offset,
3880 uint32_t size,
3881 const void* pValues)
3882 {
3883 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3884 memcpy(cmd_buffer->push_constants + offset, pValues, size);
3885 cmd_buffer->push_constant_stages |= stageFlags;
3886 }
3887
3888 VkResult radv_EndCommandBuffer(
3889 VkCommandBuffer commandBuffer)
3890 {
3891 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3892
3893 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
3894 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
3895 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
3896
3897 /* Make sure to sync all pending active queries at the end of
3898 * command buffer.
3899 */
3900 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
3901
3902 /* Since NGG streamout uses GDS, we need to make GDS idle when
3903 * we leave the IB, otherwise another process might overwrite
3904 * it while our shaders are busy.
3905 */
3906 if (cmd_buffer->gds_needed)
3907 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
3908
3909 si_emit_cache_flush(cmd_buffer);
3910 }
3911
3912 /* Make sure CP DMA is idle at the end of IBs because the kernel
3913 * doesn't wait for it.
3914 */
3915 si_cp_dma_wait_for_idle(cmd_buffer);
3916
3917 radv_describe_end_cmd_buffer(cmd_buffer);
3918
3919 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3920 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
3921
3922 VkResult result = cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs);
3923 if (result != VK_SUCCESS)
3924 return vk_error(cmd_buffer->device->instance, result);
3925
3926 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
3927
3928 return cmd_buffer->record_result;
3929 }
3930
3931 static void
3932 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
3933 {
3934 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3935
3936 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
3937 return;
3938
3939 assert(!pipeline->ctx_cs.cdw);
3940
3941 cmd_buffer->state.emitted_compute_pipeline = pipeline;
3942
3943 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
3944 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
3945
3946 cmd_buffer->compute_scratch_size_per_wave_needed = MAX2(cmd_buffer->compute_scratch_size_per_wave_needed,
3947 pipeline->scratch_bytes_per_wave);
3948 cmd_buffer->compute_scratch_waves_wanted = MAX2(cmd_buffer->compute_scratch_waves_wanted,
3949 pipeline->max_waves);
3950
3951 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3952 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
3953
3954 if (unlikely(cmd_buffer->device->trace_bo))
3955 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
3956 }
3957
3958 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
3959 VkPipelineBindPoint bind_point)
3960 {
3961 struct radv_descriptor_state *descriptors_state =
3962 radv_get_descriptors_state(cmd_buffer, bind_point);
3963
3964 descriptors_state->dirty |= descriptors_state->valid;
3965 }
3966
3967 void radv_CmdBindPipeline(
3968 VkCommandBuffer commandBuffer,
3969 VkPipelineBindPoint pipelineBindPoint,
3970 VkPipeline _pipeline)
3971 {
3972 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3973 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3974
3975 switch (pipelineBindPoint) {
3976 case VK_PIPELINE_BIND_POINT_COMPUTE:
3977 if (cmd_buffer->state.compute_pipeline == pipeline)
3978 return;
3979 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3980
3981 cmd_buffer->state.compute_pipeline = pipeline;
3982 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3983 break;
3984 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3985 if (cmd_buffer->state.pipeline == pipeline)
3986 return;
3987 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3988
3989 cmd_buffer->state.pipeline = pipeline;
3990 if (!pipeline)
3991 break;
3992
3993 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3994 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3995
3996 /* the new vertex shader might not have the same user regs */
3997 cmd_buffer->state.last_first_instance = -1;
3998 cmd_buffer->state.last_vertex_offset = -1;
3999
4000 /* Prefetch all pipeline shaders at first draw time. */
4001 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
4002
4003 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX10 &&
4004 cmd_buffer->state.emitted_pipeline &&
4005 radv_pipeline_has_ngg(cmd_buffer->state.emitted_pipeline) &&
4006 !radv_pipeline_has_ngg(cmd_buffer->state.pipeline)) {
4007 /* Transitioning from NGG to legacy GS requires
4008 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
4009 * at the beginning of IBs when legacy GS ring pointers
4010 * are set.
4011 */
4012 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
4013 }
4014
4015 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
4016 radv_bind_streamout_state(cmd_buffer, pipeline);
4017
4018 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
4019 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
4020 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
4021 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
4022
4023 if (radv_pipeline_has_tess(pipeline))
4024 cmd_buffer->tess_rings_needed = true;
4025 break;
4026 default:
4027 assert(!"invalid bind point");
4028 break;
4029 }
4030 }
4031
4032 void radv_CmdSetViewport(
4033 VkCommandBuffer commandBuffer,
4034 uint32_t firstViewport,
4035 uint32_t viewportCount,
4036 const VkViewport* pViewports)
4037 {
4038 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4039 struct radv_cmd_state *state = &cmd_buffer->state;
4040 ASSERTED const uint32_t total_count = firstViewport + viewportCount;
4041
4042 assert(firstViewport < MAX_VIEWPORTS);
4043 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
4044
4045 if (total_count <= state->dynamic.viewport.count &&
4046 !memcmp(state->dynamic.viewport.viewports + firstViewport,
4047 pViewports, viewportCount * sizeof(*pViewports))) {
4048 return;
4049 }
4050
4051 if (state->dynamic.viewport.count < total_count)
4052 state->dynamic.viewport.count = total_count;
4053
4054 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
4055 viewportCount * sizeof(*pViewports));
4056
4057 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
4058 }
4059
4060 void radv_CmdSetScissor(
4061 VkCommandBuffer commandBuffer,
4062 uint32_t firstScissor,
4063 uint32_t scissorCount,
4064 const VkRect2D* pScissors)
4065 {
4066 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4067 struct radv_cmd_state *state = &cmd_buffer->state;
4068 ASSERTED const uint32_t total_count = firstScissor + scissorCount;
4069
4070 assert(firstScissor < MAX_SCISSORS);
4071 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
4072
4073 if (total_count <= state->dynamic.scissor.count &&
4074 !memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
4075 scissorCount * sizeof(*pScissors))) {
4076 return;
4077 }
4078
4079 if (state->dynamic.scissor.count < total_count)
4080 state->dynamic.scissor.count = total_count;
4081
4082 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
4083 scissorCount * sizeof(*pScissors));
4084
4085 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
4086 }
4087
4088 void radv_CmdSetLineWidth(
4089 VkCommandBuffer commandBuffer,
4090 float lineWidth)
4091 {
4092 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4093
4094 if (cmd_buffer->state.dynamic.line_width == lineWidth)
4095 return;
4096
4097 cmd_buffer->state.dynamic.line_width = lineWidth;
4098 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
4099 }
4100
4101 void radv_CmdSetDepthBias(
4102 VkCommandBuffer commandBuffer,
4103 float depthBiasConstantFactor,
4104 float depthBiasClamp,
4105 float depthBiasSlopeFactor)
4106 {
4107 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4108 struct radv_cmd_state *state = &cmd_buffer->state;
4109
4110 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
4111 state->dynamic.depth_bias.clamp == depthBiasClamp &&
4112 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
4113 return;
4114 }
4115
4116 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
4117 state->dynamic.depth_bias.clamp = depthBiasClamp;
4118 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
4119
4120 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
4121 }
4122
4123 void radv_CmdSetBlendConstants(
4124 VkCommandBuffer commandBuffer,
4125 const float blendConstants[4])
4126 {
4127 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4128 struct radv_cmd_state *state = &cmd_buffer->state;
4129
4130 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
4131 return;
4132
4133 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
4134
4135 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
4136 }
4137
4138 void radv_CmdSetDepthBounds(
4139 VkCommandBuffer commandBuffer,
4140 float minDepthBounds,
4141 float maxDepthBounds)
4142 {
4143 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4144 struct radv_cmd_state *state = &cmd_buffer->state;
4145
4146 if (state->dynamic.depth_bounds.min == minDepthBounds &&
4147 state->dynamic.depth_bounds.max == maxDepthBounds) {
4148 return;
4149 }
4150
4151 state->dynamic.depth_bounds.min = minDepthBounds;
4152 state->dynamic.depth_bounds.max = maxDepthBounds;
4153
4154 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
4155 }
4156
4157 void radv_CmdSetStencilCompareMask(
4158 VkCommandBuffer commandBuffer,
4159 VkStencilFaceFlags faceMask,
4160 uint32_t compareMask)
4161 {
4162 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4163 struct radv_cmd_state *state = &cmd_buffer->state;
4164 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
4165 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
4166
4167 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4168 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4169 return;
4170 }
4171
4172 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4173 state->dynamic.stencil_compare_mask.front = compareMask;
4174 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4175 state->dynamic.stencil_compare_mask.back = compareMask;
4176
4177 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
4178 }
4179
4180 void radv_CmdSetStencilWriteMask(
4181 VkCommandBuffer commandBuffer,
4182 VkStencilFaceFlags faceMask,
4183 uint32_t writeMask)
4184 {
4185 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4186 struct radv_cmd_state *state = &cmd_buffer->state;
4187 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
4188 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
4189
4190 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4191 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4192 return;
4193 }
4194
4195 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4196 state->dynamic.stencil_write_mask.front = writeMask;
4197 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4198 state->dynamic.stencil_write_mask.back = writeMask;
4199
4200 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
4201 }
4202
4203 void radv_CmdSetStencilReference(
4204 VkCommandBuffer commandBuffer,
4205 VkStencilFaceFlags faceMask,
4206 uint32_t reference)
4207 {
4208 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4209 struct radv_cmd_state *state = &cmd_buffer->state;
4210 bool front_same = state->dynamic.stencil_reference.front == reference;
4211 bool back_same = state->dynamic.stencil_reference.back == reference;
4212
4213 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4214 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4215 return;
4216 }
4217
4218 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4219 cmd_buffer->state.dynamic.stencil_reference.front = reference;
4220 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4221 cmd_buffer->state.dynamic.stencil_reference.back = reference;
4222
4223 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
4224 }
4225
4226 void radv_CmdSetDiscardRectangleEXT(
4227 VkCommandBuffer commandBuffer,
4228 uint32_t firstDiscardRectangle,
4229 uint32_t discardRectangleCount,
4230 const VkRect2D* pDiscardRectangles)
4231 {
4232 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4233 struct radv_cmd_state *state = &cmd_buffer->state;
4234 ASSERTED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
4235
4236 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
4237 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
4238
4239 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
4240 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
4241 return;
4242 }
4243
4244 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
4245 pDiscardRectangles, discardRectangleCount);
4246
4247 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
4248 }
4249
4250 void radv_CmdSetSampleLocationsEXT(
4251 VkCommandBuffer commandBuffer,
4252 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
4253 {
4254 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4255 struct radv_cmd_state *state = &cmd_buffer->state;
4256
4257 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
4258
4259 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
4260 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
4261 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
4262 typed_memcpy(&state->dynamic.sample_location.locations[0],
4263 pSampleLocationsInfo->pSampleLocations,
4264 pSampleLocationsInfo->sampleLocationsCount);
4265
4266 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
4267 }
4268
4269 void radv_CmdSetLineStippleEXT(
4270 VkCommandBuffer commandBuffer,
4271 uint32_t lineStippleFactor,
4272 uint16_t lineStipplePattern)
4273 {
4274 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4275 struct radv_cmd_state *state = &cmd_buffer->state;
4276
4277 state->dynamic.line_stipple.factor = lineStippleFactor;
4278 state->dynamic.line_stipple.pattern = lineStipplePattern;
4279
4280 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE;
4281 }
4282
4283 void radv_CmdSetCullModeEXT(
4284 VkCommandBuffer commandBuffer,
4285 VkCullModeFlags cullMode)
4286 {
4287 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4288 struct radv_cmd_state *state = &cmd_buffer->state;
4289
4290 if (state->dynamic.cull_mode == cullMode)
4291 return;
4292
4293 state->dynamic.cull_mode = cullMode;
4294
4295 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_CULL_MODE;
4296 }
4297
4298 void radv_CmdSetFrontFaceEXT(
4299 VkCommandBuffer commandBuffer,
4300 VkFrontFace frontFace)
4301 {
4302 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4303 struct radv_cmd_state *state = &cmd_buffer->state;
4304
4305 if (state->dynamic.front_face == frontFace)
4306 return;
4307
4308 state->dynamic.front_face = frontFace;
4309
4310 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE;
4311 }
4312
4313 void radv_CmdSetPrimitiveTopologyEXT(
4314 VkCommandBuffer commandBuffer,
4315 VkPrimitiveTopology primitiveTopology)
4316 {
4317 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4318 struct radv_cmd_state *state = &cmd_buffer->state;
4319 unsigned primitive_topology = si_translate_prim(primitiveTopology);
4320
4321 if (state->dynamic.primitive_topology == primitive_topology)
4322 return;
4323
4324 state->dynamic.primitive_topology = primitive_topology;
4325
4326 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY;
4327 }
4328
4329 void radv_CmdSetViewportWithCountEXT(
4330 VkCommandBuffer commandBuffer,
4331 uint32_t viewportCount,
4332 const VkViewport* pViewports)
4333 {
4334 radv_CmdSetViewport(commandBuffer, 0, viewportCount, pViewports);
4335 }
4336
4337 void radv_CmdSetScissorWithCountEXT(
4338 VkCommandBuffer commandBuffer,
4339 uint32_t scissorCount,
4340 const VkRect2D* pScissors)
4341 {
4342 radv_CmdSetScissor(commandBuffer, 0, scissorCount, pScissors);
4343 }
4344
4345 void radv_CmdExecuteCommands(
4346 VkCommandBuffer commandBuffer,
4347 uint32_t commandBufferCount,
4348 const VkCommandBuffer* pCmdBuffers)
4349 {
4350 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
4351
4352 assert(commandBufferCount > 0);
4353
4354 /* Emit pending flushes on primary prior to executing secondary */
4355 si_emit_cache_flush(primary);
4356
4357 for (uint32_t i = 0; i < commandBufferCount; i++) {
4358 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
4359
4360 primary->scratch_size_per_wave_needed = MAX2(primary->scratch_size_per_wave_needed,
4361 secondary->scratch_size_per_wave_needed);
4362 primary->scratch_waves_wanted = MAX2(primary->scratch_waves_wanted,
4363 secondary->scratch_waves_wanted);
4364 primary->compute_scratch_size_per_wave_needed = MAX2(primary->compute_scratch_size_per_wave_needed,
4365 secondary->compute_scratch_size_per_wave_needed);
4366 primary->compute_scratch_waves_wanted = MAX2(primary->compute_scratch_waves_wanted,
4367 secondary->compute_scratch_waves_wanted);
4368
4369 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
4370 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
4371 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
4372 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
4373 if (secondary->tess_rings_needed)
4374 primary->tess_rings_needed = true;
4375 if (secondary->sample_positions_needed)
4376 primary->sample_positions_needed = true;
4377 if (secondary->gds_needed)
4378 primary->gds_needed = true;
4379
4380 if (!secondary->state.framebuffer &&
4381 (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
4382 /* Emit the framebuffer state from primary if secondary
4383 * has been recorded without a framebuffer, otherwise
4384 * fast color/depth clears can't work.
4385 */
4386 radv_emit_framebuffer_state(primary);
4387 }
4388
4389 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
4390
4391
4392 /* When the secondary command buffer is compute only we don't
4393 * need to re-emit the current graphics pipeline.
4394 */
4395 if (secondary->state.emitted_pipeline) {
4396 primary->state.emitted_pipeline =
4397 secondary->state.emitted_pipeline;
4398 }
4399
4400 /* When the secondary command buffer is graphics only we don't
4401 * need to re-emit the current compute pipeline.
4402 */
4403 if (secondary->state.emitted_compute_pipeline) {
4404 primary->state.emitted_compute_pipeline =
4405 secondary->state.emitted_compute_pipeline;
4406 }
4407
4408 /* Only re-emit the draw packets when needed. */
4409 if (secondary->state.last_primitive_reset_en != -1) {
4410 primary->state.last_primitive_reset_en =
4411 secondary->state.last_primitive_reset_en;
4412 }
4413
4414 if (secondary->state.last_primitive_reset_index) {
4415 primary->state.last_primitive_reset_index =
4416 secondary->state.last_primitive_reset_index;
4417 }
4418
4419 if (secondary->state.last_ia_multi_vgt_param) {
4420 primary->state.last_ia_multi_vgt_param =
4421 secondary->state.last_ia_multi_vgt_param;
4422 }
4423
4424 primary->state.last_first_instance = secondary->state.last_first_instance;
4425 primary->state.last_num_instances = secondary->state.last_num_instances;
4426 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
4427 primary->state.last_sx_ps_downconvert = secondary->state.last_sx_ps_downconvert;
4428 primary->state.last_sx_blend_opt_epsilon = secondary->state.last_sx_blend_opt_epsilon;
4429 primary->state.last_sx_blend_opt_control = secondary->state.last_sx_blend_opt_control;
4430
4431 if (secondary->state.last_index_type != -1) {
4432 primary->state.last_index_type =
4433 secondary->state.last_index_type;
4434 }
4435 }
4436
4437 /* After executing commands from secondary buffers we have to dirty
4438 * some states.
4439 */
4440 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
4441 RADV_CMD_DIRTY_INDEX_BUFFER |
4442 RADV_CMD_DIRTY_DYNAMIC_ALL;
4443 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
4444 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
4445 }
4446
4447 VkResult radv_CreateCommandPool(
4448 VkDevice _device,
4449 const VkCommandPoolCreateInfo* pCreateInfo,
4450 const VkAllocationCallbacks* pAllocator,
4451 VkCommandPool* pCmdPool)
4452 {
4453 RADV_FROM_HANDLE(radv_device, device, _device);
4454 struct radv_cmd_pool *pool;
4455
4456 pool = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*pool), 8,
4457 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4458 if (pool == NULL)
4459 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4460
4461 vk_object_base_init(&device->vk, &pool->base,
4462 VK_OBJECT_TYPE_COMMAND_POOL);
4463
4464 if (pAllocator)
4465 pool->alloc = *pAllocator;
4466 else
4467 pool->alloc = device->vk.alloc;
4468
4469 list_inithead(&pool->cmd_buffers);
4470 list_inithead(&pool->free_cmd_buffers);
4471
4472 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
4473
4474 *pCmdPool = radv_cmd_pool_to_handle(pool);
4475
4476 return VK_SUCCESS;
4477
4478 }
4479
4480 void radv_DestroyCommandPool(
4481 VkDevice _device,
4482 VkCommandPool commandPool,
4483 const VkAllocationCallbacks* pAllocator)
4484 {
4485 RADV_FROM_HANDLE(radv_device, device, _device);
4486 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4487
4488 if (!pool)
4489 return;
4490
4491 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4492 &pool->cmd_buffers, pool_link) {
4493 radv_cmd_buffer_destroy(cmd_buffer);
4494 }
4495
4496 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4497 &pool->free_cmd_buffers, pool_link) {
4498 radv_cmd_buffer_destroy(cmd_buffer);
4499 }
4500
4501 vk_object_base_finish(&pool->base);
4502 vk_free2(&device->vk.alloc, pAllocator, pool);
4503 }
4504
4505 VkResult radv_ResetCommandPool(
4506 VkDevice device,
4507 VkCommandPool commandPool,
4508 VkCommandPoolResetFlags flags)
4509 {
4510 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4511 VkResult result;
4512
4513 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
4514 &pool->cmd_buffers, pool_link) {
4515 result = radv_reset_cmd_buffer(cmd_buffer);
4516 if (result != VK_SUCCESS)
4517 return result;
4518 }
4519
4520 return VK_SUCCESS;
4521 }
4522
4523 void radv_TrimCommandPool(
4524 VkDevice device,
4525 VkCommandPool commandPool,
4526 VkCommandPoolTrimFlags flags)
4527 {
4528 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4529
4530 if (!pool)
4531 return;
4532
4533 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4534 &pool->free_cmd_buffers, pool_link) {
4535 radv_cmd_buffer_destroy(cmd_buffer);
4536 }
4537 }
4538
4539 static void
4540 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
4541 uint32_t subpass_id)
4542 {
4543 struct radv_cmd_state *state = &cmd_buffer->state;
4544 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
4545
4546 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
4547 cmd_buffer->cs, 4096);
4548
4549 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
4550
4551 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
4552
4553 radv_describe_barrier_start(cmd_buffer, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC);
4554
4555 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4556 const uint32_t a = subpass->attachments[i].attachment;
4557 if (a == VK_ATTACHMENT_UNUSED)
4558 continue;
4559
4560 radv_handle_subpass_image_transition(cmd_buffer,
4561 subpass->attachments[i],
4562 true);
4563 }
4564
4565 radv_describe_barrier_end(cmd_buffer);
4566
4567 radv_cmd_buffer_clear_subpass(cmd_buffer);
4568
4569 assert(cmd_buffer->cs->cdw <= cdw_max);
4570 }
4571
4572 static void
4573 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
4574 {
4575 struct radv_cmd_state *state = &cmd_buffer->state;
4576 const struct radv_subpass *subpass = state->subpass;
4577 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
4578
4579 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4580
4581 radv_describe_barrier_start(cmd_buffer, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC);
4582
4583 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4584 const uint32_t a = subpass->attachments[i].attachment;
4585 if (a == VK_ATTACHMENT_UNUSED)
4586 continue;
4587
4588 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
4589 continue;
4590
4591 VkImageLayout layout = state->pass->attachments[a].final_layout;
4592 VkImageLayout stencil_layout = state->pass->attachments[a].stencil_final_layout;
4593 struct radv_subpass_attachment att = { a, layout, stencil_layout };
4594 radv_handle_subpass_image_transition(cmd_buffer, att, false);
4595 }
4596
4597 radv_describe_barrier_end(cmd_buffer);
4598 }
4599
4600 void
4601 radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer *cmd_buffer,
4602 const VkRenderPassBeginInfo *pRenderPassBegin)
4603 {
4604 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
4605 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
4606 VkResult result;
4607
4608 cmd_buffer->state.framebuffer = framebuffer;
4609 cmd_buffer->state.pass = pass;
4610 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
4611
4612 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
4613 if (result != VK_SUCCESS)
4614 return;
4615
4616 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
4617 if (result != VK_SUCCESS)
4618 return;
4619 }
4620
4621 void radv_CmdBeginRenderPass(
4622 VkCommandBuffer commandBuffer,
4623 const VkRenderPassBeginInfo* pRenderPassBegin,
4624 VkSubpassContents contents)
4625 {
4626 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4627
4628 radv_cmd_buffer_begin_render_pass(cmd_buffer, pRenderPassBegin);
4629
4630 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
4631 }
4632
4633 void radv_CmdBeginRenderPass2(
4634 VkCommandBuffer commandBuffer,
4635 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
4636 const VkSubpassBeginInfo* pSubpassBeginInfo)
4637 {
4638 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
4639 pSubpassBeginInfo->contents);
4640 }
4641
4642 void radv_CmdNextSubpass(
4643 VkCommandBuffer commandBuffer,
4644 VkSubpassContents contents)
4645 {
4646 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4647
4648 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
4649 radv_cmd_buffer_end_subpass(cmd_buffer);
4650 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
4651 }
4652
4653 void radv_CmdNextSubpass2(
4654 VkCommandBuffer commandBuffer,
4655 const VkSubpassBeginInfo* pSubpassBeginInfo,
4656 const VkSubpassEndInfo* pSubpassEndInfo)
4657 {
4658 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
4659 }
4660
4661 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
4662 {
4663 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
4664 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
4665 if (!radv_get_shader(pipeline, stage))
4666 continue;
4667
4668 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
4669 if (loc->sgpr_idx == -1)
4670 continue;
4671 uint32_t base_reg = pipeline->user_data_0[stage];
4672 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4673
4674 }
4675 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
4676 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
4677 if (loc->sgpr_idx != -1) {
4678 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
4679 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4680 }
4681 }
4682 }
4683
4684 static void
4685 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4686 uint32_t vertex_count,
4687 bool use_opaque)
4688 {
4689 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
4690 radeon_emit(cmd_buffer->cs, vertex_count);
4691 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
4692 S_0287F0_USE_OPAQUE(use_opaque));
4693 }
4694
4695 static void
4696 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
4697 uint64_t index_va,
4698 uint32_t index_count)
4699 {
4700 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
4701 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
4702 radeon_emit(cmd_buffer->cs, index_va);
4703 radeon_emit(cmd_buffer->cs, index_va >> 32);
4704 radeon_emit(cmd_buffer->cs, index_count);
4705 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
4706 }
4707
4708 static void
4709 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4710 bool indexed,
4711 uint32_t draw_count,
4712 uint64_t count_va,
4713 uint32_t stride)
4714 {
4715 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4716 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
4717 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
4718 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id;
4719 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
4720 bool predicating = cmd_buffer->state.predicating;
4721 assert(base_reg);
4722
4723 /* just reset draw state for vertex data */
4724 cmd_buffer->state.last_first_instance = -1;
4725 cmd_buffer->state.last_num_instances = -1;
4726 cmd_buffer->state.last_vertex_offset = -1;
4727
4728 if (draw_count == 1 && !count_va && !draw_id_enable) {
4729 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
4730 PKT3_DRAW_INDIRECT, 3, predicating));
4731 radeon_emit(cs, 0);
4732 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4733 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4734 radeon_emit(cs, di_src_sel);
4735 } else {
4736 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
4737 PKT3_DRAW_INDIRECT_MULTI,
4738 8, predicating));
4739 radeon_emit(cs, 0);
4740 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4741 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4742 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
4743 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
4744 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
4745 radeon_emit(cs, draw_count); /* count */
4746 radeon_emit(cs, count_va); /* count_addr */
4747 radeon_emit(cs, count_va >> 32);
4748 radeon_emit(cs, stride); /* stride */
4749 radeon_emit(cs, di_src_sel);
4750 }
4751 }
4752
4753 static void
4754 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
4755 const struct radv_draw_info *info)
4756 {
4757 struct radv_cmd_state *state = &cmd_buffer->state;
4758 struct radeon_winsys *ws = cmd_buffer->device->ws;
4759 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4760
4761 if (info->indirect) {
4762 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4763 uint64_t count_va = 0;
4764
4765 va += info->indirect->offset + info->indirect_offset;
4766
4767 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4768
4769 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
4770 radeon_emit(cs, 1);
4771 radeon_emit(cs, va);
4772 radeon_emit(cs, va >> 32);
4773
4774 if (info->count_buffer) {
4775 count_va = radv_buffer_get_va(info->count_buffer->bo);
4776 count_va += info->count_buffer->offset +
4777 info->count_buffer_offset;
4778
4779 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
4780 }
4781
4782 if (!state->subpass->view_mask) {
4783 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4784 info->indexed,
4785 info->count,
4786 count_va,
4787 info->stride);
4788 } else {
4789 unsigned i;
4790 for_each_bit(i, state->subpass->view_mask) {
4791 radv_emit_view_index(cmd_buffer, i);
4792
4793 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4794 info->indexed,
4795 info->count,
4796 count_va,
4797 info->stride);
4798 }
4799 }
4800 } else {
4801 assert(state->pipeline->graphics.vtx_base_sgpr);
4802
4803 if (info->vertex_offset != state->last_vertex_offset ||
4804 info->first_instance != state->last_first_instance) {
4805 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
4806 state->pipeline->graphics.vtx_emit_num);
4807
4808 radeon_emit(cs, info->vertex_offset);
4809 radeon_emit(cs, info->first_instance);
4810 if (state->pipeline->graphics.vtx_emit_num == 3)
4811 radeon_emit(cs, 0);
4812 state->last_first_instance = info->first_instance;
4813 state->last_vertex_offset = info->vertex_offset;
4814 }
4815
4816 if (state->last_num_instances != info->instance_count) {
4817 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
4818 radeon_emit(cs, info->instance_count);
4819 state->last_num_instances = info->instance_count;
4820 }
4821
4822 if (info->indexed) {
4823 int index_size = radv_get_vgt_index_size(state->index_type);
4824 uint64_t index_va;
4825
4826 /* Skip draw calls with 0-sized index buffers. They
4827 * cause a hang on some chips, like Navi10-14.
4828 */
4829 if (!cmd_buffer->state.max_index_count)
4830 return;
4831
4832 index_va = state->index_va;
4833 index_va += info->first_index * index_size;
4834
4835 if (!state->subpass->view_mask) {
4836 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4837 index_va,
4838 info->count);
4839 } else {
4840 unsigned i;
4841 for_each_bit(i, state->subpass->view_mask) {
4842 radv_emit_view_index(cmd_buffer, i);
4843
4844 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4845 index_va,
4846 info->count);
4847 }
4848 }
4849 } else {
4850 if (!state->subpass->view_mask) {
4851 radv_cs_emit_draw_packet(cmd_buffer,
4852 info->count,
4853 !!info->strmout_buffer);
4854 } else {
4855 unsigned i;
4856 for_each_bit(i, state->subpass->view_mask) {
4857 radv_emit_view_index(cmd_buffer, i);
4858
4859 radv_cs_emit_draw_packet(cmd_buffer,
4860 info->count,
4861 !!info->strmout_buffer);
4862 }
4863 }
4864 }
4865 }
4866 }
4867
4868 /*
4869 * Vega and raven have a bug which triggers if there are multiple context
4870 * register contexts active at the same time with different scissor values.
4871 *
4872 * There are two possible workarounds:
4873 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4874 * there is only ever 1 active set of scissor values at the same time.
4875 *
4876 * 2) Whenever the hardware switches contexts we have to set the scissor
4877 * registers again even if it is a noop. That way the new context gets
4878 * the correct scissor values.
4879 *
4880 * This implements option 2. radv_need_late_scissor_emission needs to
4881 * return true on affected HW if radv_emit_all_graphics_states sets
4882 * any context registers.
4883 */
4884 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
4885 const struct radv_draw_info *info)
4886 {
4887 struct radv_cmd_state *state = &cmd_buffer->state;
4888
4889 if (!cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
4890 return false;
4891
4892 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
4893 return true;
4894
4895 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
4896
4897 /* Index, vertex and streamout buffers don't change context regs, and
4898 * pipeline is already handled.
4899 */
4900 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
4901 RADV_CMD_DIRTY_VERTEX_BUFFER |
4902 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
4903 RADV_CMD_DIRTY_PIPELINE);
4904
4905 if (cmd_buffer->state.dirty & used_states)
4906 return true;
4907
4908 uint32_t primitive_reset_index =
4909 radv_get_primitive_reset_index(cmd_buffer);
4910
4911 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
4912 primitive_reset_index != state->last_primitive_reset_index)
4913 return true;
4914
4915 return false;
4916 }
4917
4918 static void
4919 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
4920 const struct radv_draw_info *info)
4921 {
4922 bool late_scissor_emission;
4923
4924 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
4925 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
4926 radv_emit_rbplus_state(cmd_buffer);
4927
4928 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
4929 radv_emit_graphics_pipeline(cmd_buffer);
4930
4931 /* This should be before the cmd_buffer->state.dirty is cleared
4932 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4933 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4934 late_scissor_emission =
4935 radv_need_late_scissor_emission(cmd_buffer, info);
4936
4937 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
4938 radv_emit_framebuffer_state(cmd_buffer);
4939
4940 if (info->indexed) {
4941 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
4942 radv_emit_index_buffer(cmd_buffer, info->indirect);
4943 } else {
4944 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4945 * so the state must be re-emitted before the next indexed
4946 * draw.
4947 */
4948 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
4949 cmd_buffer->state.last_index_type = -1;
4950 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
4951 }
4952 }
4953
4954 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
4955
4956 radv_emit_draw_registers(cmd_buffer, info);
4957
4958 if (late_scissor_emission)
4959 radv_emit_scissor(cmd_buffer);
4960 }
4961
4962 static void
4963 radv_draw(struct radv_cmd_buffer *cmd_buffer,
4964 const struct radv_draw_info *info)
4965 {
4966 struct radeon_info *rad_info =
4967 &cmd_buffer->device->physical_device->rad_info;
4968 bool has_prefetch =
4969 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4970 bool pipeline_is_dirty =
4971 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
4972 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
4973
4974 ASSERTED unsigned cdw_max =
4975 radeon_check_space(cmd_buffer->device->ws,
4976 cmd_buffer->cs, 4096);
4977
4978 if (likely(!info->indirect)) {
4979 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4980 * no workaround for indirect draws, but we can at least skip
4981 * direct draws.
4982 */
4983 if (unlikely(!info->instance_count))
4984 return;
4985
4986 /* Handle count == 0. */
4987 if (unlikely(!info->count && !info->strmout_buffer))
4988 return;
4989 }
4990
4991 radv_describe_draw(cmd_buffer);
4992
4993 /* Use optimal packet order based on whether we need to sync the
4994 * pipeline.
4995 */
4996 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4997 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4998 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4999 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
5000 /* If we have to wait for idle, set all states first, so that
5001 * all SET packets are processed in parallel with previous draw
5002 * calls. Then upload descriptors, set shader pointers, and
5003 * draw, and prefetch at the end. This ensures that the time
5004 * the CUs are idle is very short. (there are only SET_SH
5005 * packets between the wait and the draw)
5006 */
5007 radv_emit_all_graphics_states(cmd_buffer, info);
5008 si_emit_cache_flush(cmd_buffer);
5009 /* <-- CUs are idle here --> */
5010
5011 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
5012
5013 radv_emit_draw_packets(cmd_buffer, info);
5014 /* <-- CUs are busy here --> */
5015
5016 /* Start prefetches after the draw has been started. Both will
5017 * run in parallel, but starting the draw first is more
5018 * important.
5019 */
5020 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
5021 radv_emit_prefetch_L2(cmd_buffer,
5022 cmd_buffer->state.pipeline, false);
5023 }
5024 } else {
5025 /* If we don't wait for idle, start prefetches first, then set
5026 * states, and draw at the end.
5027 */
5028 si_emit_cache_flush(cmd_buffer);
5029
5030 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
5031 /* Only prefetch the vertex shader and VBO descriptors
5032 * in order to start the draw as soon as possible.
5033 */
5034 radv_emit_prefetch_L2(cmd_buffer,
5035 cmd_buffer->state.pipeline, true);
5036 }
5037
5038 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
5039
5040 radv_emit_all_graphics_states(cmd_buffer, info);
5041 radv_emit_draw_packets(cmd_buffer, info);
5042
5043 /* Prefetch the remaining shaders after the draw has been
5044 * started.
5045 */
5046 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
5047 radv_emit_prefetch_L2(cmd_buffer,
5048 cmd_buffer->state.pipeline, false);
5049 }
5050 }
5051
5052 /* Workaround for a VGT hang when streamout is enabled.
5053 * It must be done after drawing.
5054 */
5055 if (cmd_buffer->state.streamout.streamout_enabled &&
5056 (rad_info->family == CHIP_HAWAII ||
5057 rad_info->family == CHIP_TONGA ||
5058 rad_info->family == CHIP_FIJI)) {
5059 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
5060 }
5061
5062 assert(cmd_buffer->cs->cdw <= cdw_max);
5063 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
5064 }
5065
5066 void radv_CmdDraw(
5067 VkCommandBuffer commandBuffer,
5068 uint32_t vertexCount,
5069 uint32_t instanceCount,
5070 uint32_t firstVertex,
5071 uint32_t firstInstance)
5072 {
5073 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5074 struct radv_draw_info info = {};
5075
5076 info.count = vertexCount;
5077 info.instance_count = instanceCount;
5078 info.first_instance = firstInstance;
5079 info.vertex_offset = firstVertex;
5080
5081 radv_draw(cmd_buffer, &info);
5082 }
5083
5084 void radv_CmdDrawIndexed(
5085 VkCommandBuffer commandBuffer,
5086 uint32_t indexCount,
5087 uint32_t instanceCount,
5088 uint32_t firstIndex,
5089 int32_t vertexOffset,
5090 uint32_t firstInstance)
5091 {
5092 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5093 struct radv_draw_info info = {};
5094
5095 info.indexed = true;
5096 info.count = indexCount;
5097 info.instance_count = instanceCount;
5098 info.first_index = firstIndex;
5099 info.vertex_offset = vertexOffset;
5100 info.first_instance = firstInstance;
5101
5102 radv_draw(cmd_buffer, &info);
5103 }
5104
5105 void radv_CmdDrawIndirect(
5106 VkCommandBuffer commandBuffer,
5107 VkBuffer _buffer,
5108 VkDeviceSize offset,
5109 uint32_t drawCount,
5110 uint32_t stride)
5111 {
5112 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5113 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5114 struct radv_draw_info info = {};
5115
5116 info.count = drawCount;
5117 info.indirect = buffer;
5118 info.indirect_offset = offset;
5119 info.stride = stride;
5120
5121 radv_draw(cmd_buffer, &info);
5122 }
5123
5124 void radv_CmdDrawIndexedIndirect(
5125 VkCommandBuffer commandBuffer,
5126 VkBuffer _buffer,
5127 VkDeviceSize offset,
5128 uint32_t drawCount,
5129 uint32_t stride)
5130 {
5131 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5132 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5133 struct radv_draw_info info = {};
5134
5135 info.indexed = true;
5136 info.count = drawCount;
5137 info.indirect = buffer;
5138 info.indirect_offset = offset;
5139 info.stride = stride;
5140
5141 radv_draw(cmd_buffer, &info);
5142 }
5143
5144 void radv_CmdDrawIndirectCount(
5145 VkCommandBuffer commandBuffer,
5146 VkBuffer _buffer,
5147 VkDeviceSize offset,
5148 VkBuffer _countBuffer,
5149 VkDeviceSize countBufferOffset,
5150 uint32_t maxDrawCount,
5151 uint32_t stride)
5152 {
5153 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5154 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5155 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
5156 struct radv_draw_info info = {};
5157
5158 info.count = maxDrawCount;
5159 info.indirect = buffer;
5160 info.indirect_offset = offset;
5161 info.count_buffer = count_buffer;
5162 info.count_buffer_offset = countBufferOffset;
5163 info.stride = stride;
5164
5165 radv_draw(cmd_buffer, &info);
5166 }
5167
5168 void radv_CmdDrawIndexedIndirectCount(
5169 VkCommandBuffer commandBuffer,
5170 VkBuffer _buffer,
5171 VkDeviceSize offset,
5172 VkBuffer _countBuffer,
5173 VkDeviceSize countBufferOffset,
5174 uint32_t maxDrawCount,
5175 uint32_t stride)
5176 {
5177 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5178 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5179 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
5180 struct radv_draw_info info = {};
5181
5182 info.indexed = true;
5183 info.count = maxDrawCount;
5184 info.indirect = buffer;
5185 info.indirect_offset = offset;
5186 info.count_buffer = count_buffer;
5187 info.count_buffer_offset = countBufferOffset;
5188 info.stride = stride;
5189
5190 radv_draw(cmd_buffer, &info);
5191 }
5192
5193 struct radv_dispatch_info {
5194 /**
5195 * Determine the layout of the grid (in block units) to be used.
5196 */
5197 uint32_t blocks[3];
5198
5199 /**
5200 * A starting offset for the grid. If unaligned is set, the offset
5201 * must still be aligned.
5202 */
5203 uint32_t offsets[3];
5204 /**
5205 * Whether it's an unaligned compute dispatch.
5206 */
5207 bool unaligned;
5208
5209 /**
5210 * Indirect compute parameters resource.
5211 */
5212 struct radv_buffer *indirect;
5213 uint64_t indirect_offset;
5214 };
5215
5216 static void
5217 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
5218 const struct radv_dispatch_info *info)
5219 {
5220 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
5221 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5222 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
5223 struct radeon_winsys *ws = cmd_buffer->device->ws;
5224 bool predicating = cmd_buffer->state.predicating;
5225 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5226 struct radv_userdata_info *loc;
5227
5228 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
5229 AC_UD_CS_GRID_SIZE);
5230
5231 ASSERTED unsigned cdw_max = radeon_check_space(ws, cs, 25);
5232
5233 if (compute_shader->info.wave_size == 32) {
5234 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
5235 dispatch_initiator |= S_00B800_CS_W32_EN(1);
5236 }
5237
5238 if (info->indirect) {
5239 uint64_t va = radv_buffer_get_va(info->indirect->bo);
5240
5241 va += info->indirect->offset + info->indirect_offset;
5242
5243 radv_cs_add_buffer(ws, cs, info->indirect->bo);
5244
5245 if (loc->sgpr_idx != -1) {
5246 for (unsigned i = 0; i < 3; ++i) {
5247 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5248 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5249 COPY_DATA_DST_SEL(COPY_DATA_REG));
5250 radeon_emit(cs, (va + 4 * i));
5251 radeon_emit(cs, (va + 4 * i) >> 32);
5252 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
5253 + loc->sgpr_idx * 4) >> 2) + i);
5254 radeon_emit(cs, 0);
5255 }
5256 }
5257
5258 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
5259 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
5260 PKT3_SHADER_TYPE_S(1));
5261 radeon_emit(cs, va);
5262 radeon_emit(cs, va >> 32);
5263 radeon_emit(cs, dispatch_initiator);
5264 } else {
5265 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
5266 PKT3_SHADER_TYPE_S(1));
5267 radeon_emit(cs, 1);
5268 radeon_emit(cs, va);
5269 radeon_emit(cs, va >> 32);
5270
5271 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
5272 PKT3_SHADER_TYPE_S(1));
5273 radeon_emit(cs, 0);
5274 radeon_emit(cs, dispatch_initiator);
5275 }
5276 } else {
5277 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
5278 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
5279
5280 if (info->unaligned) {
5281 unsigned *cs_block_size = compute_shader->info.cs.block_size;
5282 unsigned remainder[3];
5283
5284 /* If aligned, these should be an entire block size,
5285 * not 0.
5286 */
5287 remainder[0] = blocks[0] + cs_block_size[0] -
5288 align_u32_npot(blocks[0], cs_block_size[0]);
5289 remainder[1] = blocks[1] + cs_block_size[1] -
5290 align_u32_npot(blocks[1], cs_block_size[1]);
5291 remainder[2] = blocks[2] + cs_block_size[2] -
5292 align_u32_npot(blocks[2], cs_block_size[2]);
5293
5294 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
5295 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
5296 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
5297
5298 for(unsigned i = 0; i < 3; ++i) {
5299 assert(offsets[i] % cs_block_size[i] == 0);
5300 offsets[i] /= cs_block_size[i];
5301 }
5302
5303 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5304 radeon_emit(cs,
5305 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
5306 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
5307 radeon_emit(cs,
5308 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
5309 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
5310 radeon_emit(cs,
5311 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
5312 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
5313
5314 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
5315 }
5316
5317 if (loc->sgpr_idx != -1) {
5318 assert(loc->num_sgprs == 3);
5319
5320 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
5321 loc->sgpr_idx * 4, 3);
5322 radeon_emit(cs, blocks[0]);
5323 radeon_emit(cs, blocks[1]);
5324 radeon_emit(cs, blocks[2]);
5325 }
5326
5327 if (offsets[0] || offsets[1] || offsets[2]) {
5328 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
5329 radeon_emit(cs, offsets[0]);
5330 radeon_emit(cs, offsets[1]);
5331 radeon_emit(cs, offsets[2]);
5332
5333 /* The blocks in the packet are not counts but end values. */
5334 for (unsigned i = 0; i < 3; ++i)
5335 blocks[i] += offsets[i];
5336 } else {
5337 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
5338 }
5339
5340 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
5341 PKT3_SHADER_TYPE_S(1));
5342 radeon_emit(cs, blocks[0]);
5343 radeon_emit(cs, blocks[1]);
5344 radeon_emit(cs, blocks[2]);
5345 radeon_emit(cs, dispatch_initiator);
5346 }
5347
5348 assert(cmd_buffer->cs->cdw <= cdw_max);
5349 }
5350
5351 static void
5352 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
5353 {
5354 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5355 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5356 }
5357
5358 static void
5359 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
5360 const struct radv_dispatch_info *info)
5361 {
5362 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
5363 bool has_prefetch =
5364 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
5365 bool pipeline_is_dirty = pipeline &&
5366 pipeline != cmd_buffer->state.emitted_compute_pipeline;
5367
5368 radv_describe_dispatch(cmd_buffer, 8, 8, 8);
5369
5370 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5371 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5372 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
5373 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
5374 /* If we have to wait for idle, set all states first, so that
5375 * all SET packets are processed in parallel with previous draw
5376 * calls. Then upload descriptors, set shader pointers, and
5377 * dispatch, and prefetch at the end. This ensures that the
5378 * time the CUs are idle is very short. (there are only SET_SH
5379 * packets between the wait and the draw)
5380 */
5381 radv_emit_compute_pipeline(cmd_buffer);
5382 si_emit_cache_flush(cmd_buffer);
5383 /* <-- CUs are idle here --> */
5384
5385 radv_upload_compute_shader_descriptors(cmd_buffer);
5386
5387 radv_emit_dispatch_packets(cmd_buffer, info);
5388 /* <-- CUs are busy here --> */
5389
5390 /* Start prefetches after the dispatch has been started. Both
5391 * will run in parallel, but starting the dispatch first is
5392 * more important.
5393 */
5394 if (has_prefetch && pipeline_is_dirty) {
5395 radv_emit_shader_prefetch(cmd_buffer,
5396 pipeline->shaders[MESA_SHADER_COMPUTE]);
5397 }
5398 } else {
5399 /* If we don't wait for idle, start prefetches first, then set
5400 * states, and dispatch at the end.
5401 */
5402 si_emit_cache_flush(cmd_buffer);
5403
5404 if (has_prefetch && pipeline_is_dirty) {
5405 radv_emit_shader_prefetch(cmd_buffer,
5406 pipeline->shaders[MESA_SHADER_COMPUTE]);
5407 }
5408
5409 radv_upload_compute_shader_descriptors(cmd_buffer);
5410
5411 radv_emit_compute_pipeline(cmd_buffer);
5412 radv_emit_dispatch_packets(cmd_buffer, info);
5413 }
5414
5415 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
5416 }
5417
5418 void radv_CmdDispatchBase(
5419 VkCommandBuffer commandBuffer,
5420 uint32_t base_x,
5421 uint32_t base_y,
5422 uint32_t base_z,
5423 uint32_t x,
5424 uint32_t y,
5425 uint32_t z)
5426 {
5427 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5428 struct radv_dispatch_info info = {};
5429
5430 info.blocks[0] = x;
5431 info.blocks[1] = y;
5432 info.blocks[2] = z;
5433
5434 info.offsets[0] = base_x;
5435 info.offsets[1] = base_y;
5436 info.offsets[2] = base_z;
5437 radv_dispatch(cmd_buffer, &info);
5438 }
5439
5440 void radv_CmdDispatch(
5441 VkCommandBuffer commandBuffer,
5442 uint32_t x,
5443 uint32_t y,
5444 uint32_t z)
5445 {
5446 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
5447 }
5448
5449 void radv_CmdDispatchIndirect(
5450 VkCommandBuffer commandBuffer,
5451 VkBuffer _buffer,
5452 VkDeviceSize offset)
5453 {
5454 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5455 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5456 struct radv_dispatch_info info = {};
5457
5458 info.indirect = buffer;
5459 info.indirect_offset = offset;
5460
5461 radv_dispatch(cmd_buffer, &info);
5462 }
5463
5464 void radv_unaligned_dispatch(
5465 struct radv_cmd_buffer *cmd_buffer,
5466 uint32_t x,
5467 uint32_t y,
5468 uint32_t z)
5469 {
5470 struct radv_dispatch_info info = {};
5471
5472 info.blocks[0] = x;
5473 info.blocks[1] = y;
5474 info.blocks[2] = z;
5475 info.unaligned = 1;
5476
5477 radv_dispatch(cmd_buffer, &info);
5478 }
5479
5480 void
5481 radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer *cmd_buffer)
5482 {
5483 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
5484 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
5485
5486 cmd_buffer->state.pass = NULL;
5487 cmd_buffer->state.subpass = NULL;
5488 cmd_buffer->state.attachments = NULL;
5489 cmd_buffer->state.framebuffer = NULL;
5490 cmd_buffer->state.subpass_sample_locs = NULL;
5491 }
5492
5493 void radv_CmdEndRenderPass(
5494 VkCommandBuffer commandBuffer)
5495 {
5496 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5497
5498 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
5499
5500 radv_cmd_buffer_end_subpass(cmd_buffer);
5501
5502 radv_cmd_buffer_end_render_pass(cmd_buffer);
5503 }
5504
5505 void radv_CmdEndRenderPass2(
5506 VkCommandBuffer commandBuffer,
5507 const VkSubpassEndInfo* pSubpassEndInfo)
5508 {
5509 radv_CmdEndRenderPass(commandBuffer);
5510 }
5511
5512 /*
5513 * For HTILE we have the following interesting clear words:
5514 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5515 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5516 * 0xfffffff0: Clear depth to 1.0
5517 * 0x00000000: Clear depth to 0.0
5518 */
5519 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
5520 struct radv_image *image,
5521 const VkImageSubresourceRange *range)
5522 {
5523 assert(range->baseMipLevel == 0);
5524 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
5525 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
5526 struct radv_cmd_state *state = &cmd_buffer->state;
5527 uint32_t htile_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5528 VkClearDepthStencilValue value = {};
5529 struct radv_barrier_data barrier = {};
5530
5531 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5532 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5533
5534 barrier.layout_transitions.init_mask_ram = 1;
5535 radv_describe_layout_transition(cmd_buffer, &barrier);
5536
5537 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, htile_value);
5538
5539 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5540
5541 if (vk_format_is_stencil(image->vk_format))
5542 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
5543
5544 radv_set_ds_clear_metadata(cmd_buffer, image, range, value, aspects);
5545
5546 if (radv_image_is_tc_compat_htile(image)) {
5547 /* Initialize the TC-compat metada value to 0 because by
5548 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5549 * need have to conditionally update its value when performing
5550 * a fast depth clear.
5551 */
5552 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, range, 0);
5553 }
5554 }
5555
5556 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
5557 struct radv_image *image,
5558 VkImageLayout src_layout,
5559 bool src_render_loop,
5560 VkImageLayout dst_layout,
5561 bool dst_render_loop,
5562 unsigned src_queue_mask,
5563 unsigned dst_queue_mask,
5564 const VkImageSubresourceRange *range,
5565 struct radv_sample_locations_state *sample_locs)
5566 {
5567 if (!radv_image_has_htile(image))
5568 return;
5569
5570 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5571 radv_initialize_htile(cmd_buffer, image, range);
5572 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5573 radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5574 radv_initialize_htile(cmd_buffer, image, range);
5575 } else if (radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5576 !radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5577 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5578 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5579
5580 radv_decompress_depth_stencil(cmd_buffer, image, range,
5581 sample_locs);
5582
5583 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5584 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5585 }
5586 }
5587
5588 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
5589 struct radv_image *image,
5590 const VkImageSubresourceRange *range,
5591 uint32_t value)
5592 {
5593 struct radv_cmd_state *state = &cmd_buffer->state;
5594 struct radv_barrier_data barrier = {};
5595
5596 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5597 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5598
5599 barrier.layout_transitions.init_mask_ram = 1;
5600 radv_describe_layout_transition(cmd_buffer, &barrier);
5601
5602 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
5603
5604 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5605 }
5606
5607 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
5608 struct radv_image *image,
5609 const VkImageSubresourceRange *range)
5610 {
5611 struct radv_cmd_state *state = &cmd_buffer->state;
5612 static const uint32_t fmask_clear_values[4] = {
5613 0x00000000,
5614 0x02020202,
5615 0xE4E4E4E4,
5616 0x76543210
5617 };
5618 uint32_t log2_samples = util_logbase2(image->info.samples);
5619 uint32_t value = fmask_clear_values[log2_samples];
5620 struct radv_barrier_data barrier = {};
5621
5622 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5623 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5624
5625 barrier.layout_transitions.init_mask_ram = 1;
5626 radv_describe_layout_transition(cmd_buffer, &barrier);
5627
5628 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
5629
5630 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5631 }
5632
5633 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
5634 struct radv_image *image,
5635 const VkImageSubresourceRange *range, uint32_t value)
5636 {
5637 struct radv_cmd_state *state = &cmd_buffer->state;
5638 struct radv_barrier_data barrier = {};
5639 unsigned size = 0;
5640
5641 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5642 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5643
5644 barrier.layout_transitions.init_mask_ram = 1;
5645 radv_describe_layout_transition(cmd_buffer, &barrier);
5646
5647 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
5648
5649 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
5650 /* When DCC is enabled with mipmaps, some levels might not
5651 * support fast clears and we have to initialize them as "fully
5652 * expanded".
5653 */
5654 /* Compute the size of all fast clearable DCC levels. */
5655 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
5656 struct legacy_surf_level *surf_level =
5657 &image->planes[0].surface.u.legacy.level[i];
5658 unsigned dcc_fast_clear_size =
5659 surf_level->dcc_slice_fast_clear_size * image->info.array_size;
5660
5661 if (!dcc_fast_clear_size)
5662 break;
5663
5664 size = surf_level->dcc_offset + dcc_fast_clear_size;
5665 }
5666
5667 /* Initialize the mipmap levels without DCC. */
5668 if (size != image->planes[0].surface.dcc_size) {
5669 state->flush_bits |=
5670 radv_fill_buffer(cmd_buffer, image->bo,
5671 image->offset + image->planes[0].surface.dcc_offset + size,
5672 image->planes[0].surface.dcc_size - size,
5673 0xffffffff);
5674 }
5675 }
5676
5677 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5678 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5679 }
5680
5681 /**
5682 * Initialize DCC/FMASK/CMASK metadata for a color image.
5683 */
5684 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
5685 struct radv_image *image,
5686 VkImageLayout src_layout,
5687 bool src_render_loop,
5688 VkImageLayout dst_layout,
5689 bool dst_render_loop,
5690 unsigned src_queue_mask,
5691 unsigned dst_queue_mask,
5692 const VkImageSubresourceRange *range)
5693 {
5694 if (radv_image_has_cmask(image)) {
5695 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5696
5697 /* TODO: clarify this. */
5698 if (radv_image_has_fmask(image)) {
5699 value = 0xccccccccu;
5700 }
5701
5702 radv_initialise_cmask(cmd_buffer, image, range, value);
5703 }
5704
5705 if (radv_image_has_fmask(image)) {
5706 radv_initialize_fmask(cmd_buffer, image, range);
5707 }
5708
5709 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5710 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5711 bool need_decompress_pass = false;
5712
5713 if (radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout,
5714 dst_render_loop,
5715 dst_queue_mask)) {
5716 value = 0x20202020u;
5717 need_decompress_pass = true;
5718 }
5719
5720 radv_initialize_dcc(cmd_buffer, image, range, value);
5721
5722 radv_update_fce_metadata(cmd_buffer, image, range,
5723 need_decompress_pass);
5724 }
5725
5726 if (radv_image_has_cmask(image) ||
5727 radv_dcc_enabled(image, range->baseMipLevel)) {
5728 uint32_t color_values[2] = {};
5729 radv_set_color_clear_metadata(cmd_buffer, image, range,
5730 color_values);
5731 }
5732 }
5733
5734 /**
5735 * Handle color image transitions for DCC/FMASK/CMASK.
5736 */
5737 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
5738 struct radv_image *image,
5739 VkImageLayout src_layout,
5740 bool src_render_loop,
5741 VkImageLayout dst_layout,
5742 bool dst_render_loop,
5743 unsigned src_queue_mask,
5744 unsigned dst_queue_mask,
5745 const VkImageSubresourceRange *range)
5746 {
5747 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5748 radv_init_color_image_metadata(cmd_buffer, image,
5749 src_layout, src_render_loop,
5750 dst_layout, dst_render_loop,
5751 src_queue_mask, dst_queue_mask,
5752 range);
5753 return;
5754 }
5755
5756 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5757 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
5758 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
5759 } else if (radv_layout_dcc_compressed(cmd_buffer->device, image, src_layout, src_render_loop, src_queue_mask) &&
5760 !radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout, dst_render_loop, dst_queue_mask)) {
5761 radv_decompress_dcc(cmd_buffer, image, range);
5762 } else if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5763 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5764 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5765 }
5766 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
5767 bool fce_eliminate = false, fmask_expand = false;
5768
5769 if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5770 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5771 fce_eliminate = true;
5772 }
5773
5774 if (radv_image_has_fmask(image)) {
5775 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
5776 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
5777 /* A FMASK decompress is required before doing
5778 * a MSAA decompress using FMASK.
5779 */
5780 fmask_expand = true;
5781 }
5782 }
5783
5784 if (fce_eliminate || fmask_expand)
5785 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5786
5787 if (fmask_expand) {
5788 struct radv_barrier_data barrier = {};
5789 barrier.layout_transitions.fmask_color_expand = 1;
5790 radv_describe_layout_transition(cmd_buffer, &barrier);
5791
5792 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
5793 }
5794 }
5795 }
5796
5797 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
5798 struct radv_image *image,
5799 VkImageLayout src_layout,
5800 bool src_render_loop,
5801 VkImageLayout dst_layout,
5802 bool dst_render_loop,
5803 uint32_t src_family,
5804 uint32_t dst_family,
5805 const VkImageSubresourceRange *range,
5806 struct radv_sample_locations_state *sample_locs)
5807 {
5808 if (image->exclusive && src_family != dst_family) {
5809 /* This is an acquire or a release operation and there will be
5810 * a corresponding release/acquire. Do the transition in the
5811 * most flexible queue. */
5812
5813 assert(src_family == cmd_buffer->queue_family_index ||
5814 dst_family == cmd_buffer->queue_family_index);
5815
5816 if (src_family == VK_QUEUE_FAMILY_EXTERNAL ||
5817 src_family == VK_QUEUE_FAMILY_FOREIGN_EXT)
5818 return;
5819
5820 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
5821 return;
5822
5823 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
5824 (src_family == RADV_QUEUE_GENERAL ||
5825 dst_family == RADV_QUEUE_GENERAL))
5826 return;
5827 }
5828
5829 if (src_layout == dst_layout)
5830 return;
5831
5832 unsigned src_queue_mask =
5833 radv_image_queue_family_mask(image, src_family,
5834 cmd_buffer->queue_family_index);
5835 unsigned dst_queue_mask =
5836 radv_image_queue_family_mask(image, dst_family,
5837 cmd_buffer->queue_family_index);
5838
5839 if (vk_format_is_depth(image->vk_format)) {
5840 radv_handle_depth_image_transition(cmd_buffer, image,
5841 src_layout, src_render_loop,
5842 dst_layout, dst_render_loop,
5843 src_queue_mask, dst_queue_mask,
5844 range, sample_locs);
5845 } else {
5846 radv_handle_color_image_transition(cmd_buffer, image,
5847 src_layout, src_render_loop,
5848 dst_layout, dst_render_loop,
5849 src_queue_mask, dst_queue_mask,
5850 range);
5851 }
5852 }
5853
5854 struct radv_barrier_info {
5855 enum rgp_barrier_reason reason;
5856 uint32_t eventCount;
5857 const VkEvent *pEvents;
5858 VkPipelineStageFlags srcStageMask;
5859 VkPipelineStageFlags dstStageMask;
5860 };
5861
5862 static void
5863 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
5864 uint32_t memoryBarrierCount,
5865 const VkMemoryBarrier *pMemoryBarriers,
5866 uint32_t bufferMemoryBarrierCount,
5867 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
5868 uint32_t imageMemoryBarrierCount,
5869 const VkImageMemoryBarrier *pImageMemoryBarriers,
5870 const struct radv_barrier_info *info)
5871 {
5872 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5873 enum radv_cmd_flush_bits src_flush_bits = 0;
5874 enum radv_cmd_flush_bits dst_flush_bits = 0;
5875
5876 radv_describe_barrier_start(cmd_buffer, info->reason);
5877
5878 for (unsigned i = 0; i < info->eventCount; ++i) {
5879 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
5880 uint64_t va = radv_buffer_get_va(event->bo);
5881
5882 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5883
5884 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
5885
5886 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
5887 assert(cmd_buffer->cs->cdw <= cdw_max);
5888 }
5889
5890 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
5891 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
5892 NULL);
5893 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
5894 NULL);
5895 }
5896
5897 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
5898 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
5899 NULL);
5900 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
5901 NULL);
5902 }
5903
5904 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5905 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5906
5907 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
5908 image);
5909 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
5910 image);
5911 }
5912
5913 /* The Vulkan spec 1.1.98 says:
5914 *
5915 * "An execution dependency with only
5916 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5917 * will only prevent that stage from executing in subsequently
5918 * submitted commands. As this stage does not perform any actual
5919 * execution, this is not observable - in effect, it does not delay
5920 * processing of subsequent commands. Similarly an execution dependency
5921 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5922 * will effectively not wait for any prior commands to complete."
5923 */
5924 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
5925 radv_stage_flush(cmd_buffer, info->srcStageMask);
5926 cmd_buffer->state.flush_bits |= src_flush_bits;
5927
5928 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5929 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5930
5931 const struct VkSampleLocationsInfoEXT *sample_locs_info =
5932 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
5933 SAMPLE_LOCATIONS_INFO_EXT);
5934 struct radv_sample_locations_state sample_locations = {};
5935
5936 if (sample_locs_info) {
5937 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
5938 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
5939 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
5940 sample_locations.count = sample_locs_info->sampleLocationsCount;
5941 typed_memcpy(&sample_locations.locations[0],
5942 sample_locs_info->pSampleLocations,
5943 sample_locs_info->sampleLocationsCount);
5944 }
5945
5946 radv_handle_image_transition(cmd_buffer, image,
5947 pImageMemoryBarriers[i].oldLayout,
5948 false, /* Outside of a renderpass we are never in a renderloop */
5949 pImageMemoryBarriers[i].newLayout,
5950 false, /* Outside of a renderpass we are never in a renderloop */
5951 pImageMemoryBarriers[i].srcQueueFamilyIndex,
5952 pImageMemoryBarriers[i].dstQueueFamilyIndex,
5953 &pImageMemoryBarriers[i].subresourceRange,
5954 sample_locs_info ? &sample_locations : NULL);
5955 }
5956
5957 /* Make sure CP DMA is idle because the driver might have performed a
5958 * DMA operation for copying or filling buffers/images.
5959 */
5960 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5961 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5962 si_cp_dma_wait_for_idle(cmd_buffer);
5963
5964 cmd_buffer->state.flush_bits |= dst_flush_bits;
5965
5966 radv_describe_barrier_end(cmd_buffer);
5967 }
5968
5969 void radv_CmdPipelineBarrier(
5970 VkCommandBuffer commandBuffer,
5971 VkPipelineStageFlags srcStageMask,
5972 VkPipelineStageFlags destStageMask,
5973 VkBool32 byRegion,
5974 uint32_t memoryBarrierCount,
5975 const VkMemoryBarrier* pMemoryBarriers,
5976 uint32_t bufferMemoryBarrierCount,
5977 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5978 uint32_t imageMemoryBarrierCount,
5979 const VkImageMemoryBarrier* pImageMemoryBarriers)
5980 {
5981 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5982 struct radv_barrier_info info;
5983
5984 info.reason = RGP_BARRIER_EXTERNAL_CMD_PIPELINE_BARRIER;
5985 info.eventCount = 0;
5986 info.pEvents = NULL;
5987 info.srcStageMask = srcStageMask;
5988 info.dstStageMask = destStageMask;
5989
5990 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5991 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5992 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5993 }
5994
5995
5996 static void write_event(struct radv_cmd_buffer *cmd_buffer,
5997 struct radv_event *event,
5998 VkPipelineStageFlags stageMask,
5999 unsigned value)
6000 {
6001 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6002 uint64_t va = radv_buffer_get_va(event->bo);
6003
6004 si_emit_cache_flush(cmd_buffer);
6005
6006 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
6007
6008 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
6009
6010 /* Flags that only require a top-of-pipe event. */
6011 VkPipelineStageFlags top_of_pipe_flags =
6012 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
6013
6014 /* Flags that only require a post-index-fetch event. */
6015 VkPipelineStageFlags post_index_fetch_flags =
6016 top_of_pipe_flags |
6017 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
6018 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
6019
6020 /* Make sure CP DMA is idle because the driver might have performed a
6021 * DMA operation for copying or filling buffers/images.
6022 */
6023 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
6024 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
6025 si_cp_dma_wait_for_idle(cmd_buffer);
6026
6027 /* TODO: Emit EOS events for syncing PS/CS stages. */
6028
6029 if (!(stageMask & ~top_of_pipe_flags)) {
6030 /* Just need to sync the PFP engine. */
6031 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
6032 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
6033 S_370_WR_CONFIRM(1) |
6034 S_370_ENGINE_SEL(V_370_PFP));
6035 radeon_emit(cs, va);
6036 radeon_emit(cs, va >> 32);
6037 radeon_emit(cs, value);
6038 } else if (!(stageMask & ~post_index_fetch_flags)) {
6039 /* Sync ME because PFP reads index and indirect buffers. */
6040 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
6041 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
6042 S_370_WR_CONFIRM(1) |
6043 S_370_ENGINE_SEL(V_370_ME));
6044 radeon_emit(cs, va);
6045 radeon_emit(cs, va >> 32);
6046 radeon_emit(cs, value);
6047 } else {
6048 /* Otherwise, sync all prior GPU work using an EOP event. */
6049 si_cs_emit_write_event_eop(cs,
6050 cmd_buffer->device->physical_device->rad_info.chip_class,
6051 radv_cmd_buffer_uses_mec(cmd_buffer),
6052 V_028A90_BOTTOM_OF_PIPE_TS, 0,
6053 EOP_DST_SEL_MEM,
6054 EOP_DATA_SEL_VALUE_32BIT, va, value,
6055 cmd_buffer->gfx9_eop_bug_va);
6056 }
6057
6058 assert(cmd_buffer->cs->cdw <= cdw_max);
6059 }
6060
6061 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
6062 VkEvent _event,
6063 VkPipelineStageFlags stageMask)
6064 {
6065 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6066 RADV_FROM_HANDLE(radv_event, event, _event);
6067
6068 write_event(cmd_buffer, event, stageMask, 1);
6069 }
6070
6071 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
6072 VkEvent _event,
6073 VkPipelineStageFlags stageMask)
6074 {
6075 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6076 RADV_FROM_HANDLE(radv_event, event, _event);
6077
6078 write_event(cmd_buffer, event, stageMask, 0);
6079 }
6080
6081 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
6082 uint32_t eventCount,
6083 const VkEvent* pEvents,
6084 VkPipelineStageFlags srcStageMask,
6085 VkPipelineStageFlags dstStageMask,
6086 uint32_t memoryBarrierCount,
6087 const VkMemoryBarrier* pMemoryBarriers,
6088 uint32_t bufferMemoryBarrierCount,
6089 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
6090 uint32_t imageMemoryBarrierCount,
6091 const VkImageMemoryBarrier* pImageMemoryBarriers)
6092 {
6093 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6094 struct radv_barrier_info info;
6095
6096 info.reason = RGP_BARRIER_EXTERNAL_CMD_WAIT_EVENTS;
6097 info.eventCount = eventCount;
6098 info.pEvents = pEvents;
6099 info.srcStageMask = 0;
6100
6101 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
6102 bufferMemoryBarrierCount, pBufferMemoryBarriers,
6103 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
6104 }
6105
6106
6107 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
6108 uint32_t deviceMask)
6109 {
6110 /* No-op */
6111 }
6112
6113 /* VK_EXT_conditional_rendering */
6114 void radv_CmdBeginConditionalRenderingEXT(
6115 VkCommandBuffer commandBuffer,
6116 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
6117 {
6118 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6119 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
6120 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6121 bool draw_visible = true;
6122 uint64_t pred_value = 0;
6123 uint64_t va, new_va;
6124 unsigned pred_offset;
6125
6126 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
6127
6128 /* By default, if the 32-bit value at offset in buffer memory is zero,
6129 * then the rendering commands are discarded, otherwise they are
6130 * executed as normal. If the inverted flag is set, all commands are
6131 * discarded if the value is non zero.
6132 */
6133 if (pConditionalRenderingBegin->flags &
6134 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
6135 draw_visible = false;
6136 }
6137
6138 si_emit_cache_flush(cmd_buffer);
6139
6140 /* From the Vulkan spec 1.1.107:
6141 *
6142 * "If the 32-bit value at offset in buffer memory is zero, then the
6143 * rendering commands are discarded, otherwise they are executed as
6144 * normal. If the value of the predicate in buffer memory changes while
6145 * conditional rendering is active, the rendering commands may be
6146 * discarded in an implementation-dependent way. Some implementations
6147 * may latch the value of the predicate upon beginning conditional
6148 * rendering while others may read it before every rendering command."
6149 *
6150 * But, the AMD hardware treats the predicate as a 64-bit value which
6151 * means we need a workaround in the driver. Luckily, it's not required
6152 * to support if the value changes when predication is active.
6153 *
6154 * The workaround is as follows:
6155 * 1) allocate a 64-value in the upload BO and initialize it to 0
6156 * 2) copy the 32-bit predicate value to the upload BO
6157 * 3) use the new allocated VA address for predication
6158 *
6159 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
6160 * in ME (+ sync PFP) instead of PFP.
6161 */
6162 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
6163
6164 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
6165
6166 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
6167 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
6168 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
6169 COPY_DATA_WR_CONFIRM);
6170 radeon_emit(cs, va);
6171 radeon_emit(cs, va >> 32);
6172 radeon_emit(cs, new_va);
6173 radeon_emit(cs, new_va >> 32);
6174
6175 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
6176 radeon_emit(cs, 0);
6177
6178 /* Enable predication for this command buffer. */
6179 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
6180 cmd_buffer->state.predicating = true;
6181
6182 /* Store conditional rendering user info. */
6183 cmd_buffer->state.predication_type = draw_visible;
6184 cmd_buffer->state.predication_va = new_va;
6185 }
6186
6187 void radv_CmdEndConditionalRenderingEXT(
6188 VkCommandBuffer commandBuffer)
6189 {
6190 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6191
6192 /* Disable predication for this command buffer. */
6193 si_emit_set_predication_state(cmd_buffer, false, 0);
6194 cmd_buffer->state.predicating = false;
6195
6196 /* Reset conditional rendering user info. */
6197 cmd_buffer->state.predication_type = -1;
6198 cmd_buffer->state.predication_va = 0;
6199 }
6200
6201 /* VK_EXT_transform_feedback */
6202 void radv_CmdBindTransformFeedbackBuffersEXT(
6203 VkCommandBuffer commandBuffer,
6204 uint32_t firstBinding,
6205 uint32_t bindingCount,
6206 const VkBuffer* pBuffers,
6207 const VkDeviceSize* pOffsets,
6208 const VkDeviceSize* pSizes)
6209 {
6210 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6211 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
6212 uint8_t enabled_mask = 0;
6213
6214 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
6215 for (uint32_t i = 0; i < bindingCount; i++) {
6216 uint32_t idx = firstBinding + i;
6217
6218 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
6219 sb[idx].offset = pOffsets[i];
6220
6221 if (!pSizes || pSizes[i] == VK_WHOLE_SIZE) {
6222 sb[idx].size = sb[idx].buffer->size - sb[idx].offset;
6223 } else {
6224 sb[idx].size = pSizes[i];
6225 }
6226
6227 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
6228 sb[idx].buffer->bo);
6229
6230 enabled_mask |= 1 << idx;
6231 }
6232
6233 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
6234
6235 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
6236 }
6237
6238 static void
6239 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
6240 {
6241 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6242 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6243
6244 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
6245 radeon_emit(cs,
6246 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
6247 S_028B94_RAST_STREAM(0) |
6248 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
6249 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
6250 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
6251 radeon_emit(cs, so->hw_enabled_mask &
6252 so->enabled_stream_buffers_mask);
6253
6254 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6255 }
6256
6257 static void
6258 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
6259 {
6260 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6261 bool old_streamout_enabled = so->streamout_enabled;
6262 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
6263
6264 so->streamout_enabled = enable;
6265
6266 so->hw_enabled_mask = so->enabled_mask |
6267 (so->enabled_mask << 4) |
6268 (so->enabled_mask << 8) |
6269 (so->enabled_mask << 12);
6270
6271 if (!cmd_buffer->device->physical_device->use_ngg_streamout &&
6272 ((old_streamout_enabled != so->streamout_enabled) ||
6273 (old_hw_enabled_mask != so->hw_enabled_mask)))
6274 radv_emit_streamout_enable(cmd_buffer);
6275
6276 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6277 cmd_buffer->gds_needed = true;
6278 cmd_buffer->gds_oa_needed = true;
6279 }
6280 }
6281
6282 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
6283 {
6284 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6285 unsigned reg_strmout_cntl;
6286
6287 /* The register is at different places on different ASICs. */
6288 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
6289 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
6290 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
6291 } else {
6292 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
6293 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
6294 }
6295
6296 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
6297 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
6298
6299 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
6300 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
6301 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
6302 radeon_emit(cs, 0);
6303 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
6304 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
6305 radeon_emit(cs, 4); /* poll interval */
6306 }
6307
6308 static void
6309 radv_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6310 uint32_t firstCounterBuffer,
6311 uint32_t counterBufferCount,
6312 const VkBuffer *pCounterBuffers,
6313 const VkDeviceSize *pCounterBufferOffsets)
6314
6315 {
6316 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
6317 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6318 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6319 uint32_t i;
6320
6321 radv_flush_vgt_streamout(cmd_buffer);
6322
6323 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6324 for_each_bit(i, so->enabled_mask) {
6325 int32_t counter_buffer_idx = i - firstCounterBuffer;
6326 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6327 counter_buffer_idx = -1;
6328
6329 /* AMD GCN binds streamout buffers as shader resources.
6330 * VGT only counts primitives and tells the shader through
6331 * SGPRs what to do.
6332 */
6333 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
6334 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
6335 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
6336
6337 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6338
6339 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6340 /* The array of counter buffers is optional. */
6341 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6342 uint64_t va = radv_buffer_get_va(buffer->bo);
6343
6344 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6345
6346 /* Append */
6347 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6348 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6349 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6350 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
6351 radeon_emit(cs, 0); /* unused */
6352 radeon_emit(cs, 0); /* unused */
6353 radeon_emit(cs, va); /* src address lo */
6354 radeon_emit(cs, va >> 32); /* src address hi */
6355
6356 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6357 } else {
6358 /* Start from the beginning. */
6359 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6360 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6361 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6362 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
6363 radeon_emit(cs, 0); /* unused */
6364 radeon_emit(cs, 0); /* unused */
6365 radeon_emit(cs, 0); /* unused */
6366 radeon_emit(cs, 0); /* unused */
6367 }
6368 }
6369
6370 radv_set_streamout_enable(cmd_buffer, true);
6371 }
6372
6373 static void
6374 gfx10_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6375 uint32_t firstCounterBuffer,
6376 uint32_t counterBufferCount,
6377 const VkBuffer *pCounterBuffers,
6378 const VkDeviceSize *pCounterBufferOffsets)
6379 {
6380 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6381 unsigned last_target = util_last_bit(so->enabled_mask) - 1;
6382 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6383 uint32_t i;
6384
6385 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6386 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6387
6388 /* Sync because the next streamout operation will overwrite GDS and we
6389 * have to make sure it's idle.
6390 * TODO: Improve by tracking if there is a streamout operation in
6391 * flight.
6392 */
6393 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
6394 si_emit_cache_flush(cmd_buffer);
6395
6396 for_each_bit(i, so->enabled_mask) {
6397 int32_t counter_buffer_idx = i - firstCounterBuffer;
6398 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6399 counter_buffer_idx = -1;
6400
6401 bool append = counter_buffer_idx >= 0 &&
6402 pCounterBuffers && pCounterBuffers[counter_buffer_idx];
6403 uint64_t va = 0;
6404
6405 if (append) {
6406 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6407
6408 va += radv_buffer_get_va(buffer->bo);
6409 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6410
6411 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6412 }
6413
6414 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
6415 radeon_emit(cs, S_411_SRC_SEL(append ? V_411_SRC_ADDR_TC_L2 : V_411_DATA) |
6416 S_411_DST_SEL(V_411_GDS) |
6417 S_411_CP_SYNC(i == last_target));
6418 radeon_emit(cs, va);
6419 radeon_emit(cs, va >> 32);
6420 radeon_emit(cs, 4 * i); /* destination in GDS */
6421 radeon_emit(cs, 0);
6422 radeon_emit(cs, S_414_BYTE_COUNT_GFX9(4) |
6423 S_414_DISABLE_WR_CONFIRM_GFX9(i != last_target));
6424 }
6425
6426 radv_set_streamout_enable(cmd_buffer, true);
6427 }
6428
6429 void radv_CmdBeginTransformFeedbackEXT(
6430 VkCommandBuffer commandBuffer,
6431 uint32_t firstCounterBuffer,
6432 uint32_t counterBufferCount,
6433 const VkBuffer* pCounterBuffers,
6434 const VkDeviceSize* pCounterBufferOffsets)
6435 {
6436 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6437
6438 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6439 gfx10_emit_streamout_begin(cmd_buffer,
6440 firstCounterBuffer, counterBufferCount,
6441 pCounterBuffers, pCounterBufferOffsets);
6442 } else {
6443 radv_emit_streamout_begin(cmd_buffer,
6444 firstCounterBuffer, counterBufferCount,
6445 pCounterBuffers, pCounterBufferOffsets);
6446 }
6447 }
6448
6449 static void
6450 radv_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6451 uint32_t firstCounterBuffer,
6452 uint32_t counterBufferCount,
6453 const VkBuffer *pCounterBuffers,
6454 const VkDeviceSize *pCounterBufferOffsets)
6455 {
6456 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6457 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6458 uint32_t i;
6459
6460 radv_flush_vgt_streamout(cmd_buffer);
6461
6462 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6463 for_each_bit(i, so->enabled_mask) {
6464 int32_t counter_buffer_idx = i - firstCounterBuffer;
6465 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6466 counter_buffer_idx = -1;
6467
6468 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6469 /* The array of counters buffer is optional. */
6470 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6471 uint64_t va = radv_buffer_get_va(buffer->bo);
6472
6473 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6474
6475 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6476 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6477 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6478 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
6479 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
6480 radeon_emit(cs, va); /* dst address lo */
6481 radeon_emit(cs, va >> 32); /* dst address hi */
6482 radeon_emit(cs, 0); /* unused */
6483 radeon_emit(cs, 0); /* unused */
6484
6485 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6486 }
6487
6488 /* Deactivate transform feedback by zeroing the buffer size.
6489 * The counters (primitives generated, primitives emitted) may
6490 * be enabled even if there is not buffer bound. This ensures
6491 * that the primitives-emitted query won't increment.
6492 */
6493 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
6494
6495 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6496 }
6497
6498 radv_set_streamout_enable(cmd_buffer, false);
6499 }
6500
6501 static void
6502 gfx10_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6503 uint32_t firstCounterBuffer,
6504 uint32_t counterBufferCount,
6505 const VkBuffer *pCounterBuffers,
6506 const VkDeviceSize *pCounterBufferOffsets)
6507 {
6508 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6509 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6510 uint32_t i;
6511
6512 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6513 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6514
6515 for_each_bit(i, so->enabled_mask) {
6516 int32_t counter_buffer_idx = i - firstCounterBuffer;
6517 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6518 counter_buffer_idx = -1;
6519
6520 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6521 /* The array of counters buffer is optional. */
6522 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6523 uint64_t va = radv_buffer_get_va(buffer->bo);
6524
6525 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6526
6527 si_cs_emit_write_event_eop(cs,
6528 cmd_buffer->device->physical_device->rad_info.chip_class,
6529 radv_cmd_buffer_uses_mec(cmd_buffer),
6530 V_028A90_PS_DONE, 0,
6531 EOP_DST_SEL_TC_L2,
6532 EOP_DATA_SEL_GDS,
6533 va, EOP_DATA_GDS(i, 1), 0);
6534
6535 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6536 }
6537 }
6538
6539 radv_set_streamout_enable(cmd_buffer, false);
6540 }
6541
6542 void radv_CmdEndTransformFeedbackEXT(
6543 VkCommandBuffer commandBuffer,
6544 uint32_t firstCounterBuffer,
6545 uint32_t counterBufferCount,
6546 const VkBuffer* pCounterBuffers,
6547 const VkDeviceSize* pCounterBufferOffsets)
6548 {
6549 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6550
6551 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6552 gfx10_emit_streamout_end(cmd_buffer,
6553 firstCounterBuffer, counterBufferCount,
6554 pCounterBuffers, pCounterBufferOffsets);
6555 } else {
6556 radv_emit_streamout_end(cmd_buffer,
6557 firstCounterBuffer, counterBufferCount,
6558 pCounterBuffers, pCounterBufferOffsets);
6559 }
6560 }
6561
6562 void radv_CmdDrawIndirectByteCountEXT(
6563 VkCommandBuffer commandBuffer,
6564 uint32_t instanceCount,
6565 uint32_t firstInstance,
6566 VkBuffer _counterBuffer,
6567 VkDeviceSize counterBufferOffset,
6568 uint32_t counterOffset,
6569 uint32_t vertexStride)
6570 {
6571 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6572 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
6573 struct radv_draw_info info = {};
6574
6575 info.instance_count = instanceCount;
6576 info.first_instance = firstInstance;
6577 info.strmout_buffer = counterBuffer;
6578 info.strmout_buffer_offset = counterBufferOffset;
6579 info.stride = vertexStride;
6580
6581 radv_draw(cmd_buffer, &info);
6582 }
6583
6584 /* VK_AMD_buffer_marker */
6585 void radv_CmdWriteBufferMarkerAMD(
6586 VkCommandBuffer commandBuffer,
6587 VkPipelineStageFlagBits pipelineStage,
6588 VkBuffer dstBuffer,
6589 VkDeviceSize dstOffset,
6590 uint32_t marker)
6591 {
6592 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6593 RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
6594 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6595 uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
6596
6597 si_emit_cache_flush(cmd_buffer);
6598
6599 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 12);
6600
6601 if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
6602 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
6603 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
6604 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
6605 COPY_DATA_WR_CONFIRM);
6606 radeon_emit(cs, marker);
6607 radeon_emit(cs, 0);
6608 radeon_emit(cs, va);
6609 radeon_emit(cs, va >> 32);
6610 } else {
6611 si_cs_emit_write_event_eop(cs,
6612 cmd_buffer->device->physical_device->rad_info.chip_class,
6613 radv_cmd_buffer_uses_mec(cmd_buffer),
6614 V_028A90_BOTTOM_OF_PIPE_TS, 0,
6615 EOP_DST_SEL_MEM,
6616 EOP_DATA_SEL_VALUE_32BIT,
6617 va, marker,
6618 cmd_buffer->gfx9_eop_bug_va);
6619 }
6620
6621 assert(cmd_buffer->cs->cdw <= cdw_max);
6622 }