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radv/gfx10: disable the TC compat zrange workaround
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range,
61 struct radv_sample_locations_state *sample_locs);
62
63 const struct radv_dynamic_state default_dynamic_state = {
64 .viewport = {
65 .count = 0,
66 },
67 .scissor = {
68 .count = 0,
69 },
70 .line_width = 1.0f,
71 .depth_bias = {
72 .bias = 0.0f,
73 .clamp = 0.0f,
74 .slope = 0.0f,
75 },
76 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
77 .depth_bounds = {
78 .min = 0.0f,
79 .max = 1.0f,
80 },
81 .stencil_compare_mask = {
82 .front = ~0u,
83 .back = ~0u,
84 },
85 .stencil_write_mask = {
86 .front = ~0u,
87 .back = ~0u,
88 },
89 .stencil_reference = {
90 .front = 0u,
91 .back = 0u,
92 },
93 };
94
95 static void
96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
97 const struct radv_dynamic_state *src)
98 {
99 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
100 uint32_t copy_mask = src->mask;
101 uint32_t dest_mask = 0;
102
103 /* Make sure to copy the number of viewports/scissors because they can
104 * only be specified at pipeline creation time.
105 */
106 dest->viewport.count = src->viewport.count;
107 dest->scissor.count = src->scissor.count;
108 dest->discard_rectangle.count = src->discard_rectangle.count;
109 dest->sample_location.count = src->sample_location.count;
110
111 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
112 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
113 src->viewport.count * sizeof(VkViewport))) {
114 typed_memcpy(dest->viewport.viewports,
115 src->viewport.viewports,
116 src->viewport.count);
117 dest_mask |= RADV_DYNAMIC_VIEWPORT;
118 }
119 }
120
121 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
122 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
123 src->scissor.count * sizeof(VkRect2D))) {
124 typed_memcpy(dest->scissor.scissors,
125 src->scissor.scissors, src->scissor.count);
126 dest_mask |= RADV_DYNAMIC_SCISSOR;
127 }
128 }
129
130 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
131 if (dest->line_width != src->line_width) {
132 dest->line_width = src->line_width;
133 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
134 }
135 }
136
137 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
138 if (memcmp(&dest->depth_bias, &src->depth_bias,
139 sizeof(src->depth_bias))) {
140 dest->depth_bias = src->depth_bias;
141 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
142 }
143 }
144
145 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
146 if (memcmp(&dest->blend_constants, &src->blend_constants,
147 sizeof(src->blend_constants))) {
148 typed_memcpy(dest->blend_constants,
149 src->blend_constants, 4);
150 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
151 }
152 }
153
154 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
155 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
156 sizeof(src->depth_bounds))) {
157 dest->depth_bounds = src->depth_bounds;
158 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
159 }
160 }
161
162 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
163 if (memcmp(&dest->stencil_compare_mask,
164 &src->stencil_compare_mask,
165 sizeof(src->stencil_compare_mask))) {
166 dest->stencil_compare_mask = src->stencil_compare_mask;
167 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
168 }
169 }
170
171 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
172 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
173 sizeof(src->stencil_write_mask))) {
174 dest->stencil_write_mask = src->stencil_write_mask;
175 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
176 }
177 }
178
179 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
180 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
181 sizeof(src->stencil_reference))) {
182 dest->stencil_reference = src->stencil_reference;
183 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
184 }
185 }
186
187 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
188 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
189 src->discard_rectangle.count * sizeof(VkRect2D))) {
190 typed_memcpy(dest->discard_rectangle.rectangles,
191 src->discard_rectangle.rectangles,
192 src->discard_rectangle.count);
193 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
194 }
195 }
196
197 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
198 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
199 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
200 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
201 memcmp(&dest->sample_location.locations,
202 &src->sample_location.locations,
203 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
204 dest->sample_location.per_pixel = src->sample_location.per_pixel;
205 dest->sample_location.grid_size = src->sample_location.grid_size;
206 typed_memcpy(dest->sample_location.locations,
207 src->sample_location.locations,
208 src->sample_location.count);
209 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
210 }
211 }
212
213 cmd_buffer->state.dirty |= dest_mask;
214 }
215
216 static void
217 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
218 struct radv_pipeline *pipeline)
219 {
220 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
221 struct radv_shader_info *info;
222
223 if (!pipeline->streamout_shader)
224 return;
225
226 info = &pipeline->streamout_shader->info.info;
227 for (int i = 0; i < MAX_SO_BUFFERS; i++)
228 so->stride_in_dw[i] = info->so.strides[i];
229
230 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
231 }
232
233 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
234 {
235 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
236 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
237 }
238
239 enum ring_type radv_queue_family_to_ring(int f) {
240 switch (f) {
241 case RADV_QUEUE_GENERAL:
242 return RING_GFX;
243 case RADV_QUEUE_COMPUTE:
244 return RING_COMPUTE;
245 case RADV_QUEUE_TRANSFER:
246 return RING_DMA;
247 default:
248 unreachable("Unknown queue family");
249 }
250 }
251
252 static VkResult radv_create_cmd_buffer(
253 struct radv_device * device,
254 struct radv_cmd_pool * pool,
255 VkCommandBufferLevel level,
256 VkCommandBuffer* pCommandBuffer)
257 {
258 struct radv_cmd_buffer *cmd_buffer;
259 unsigned ring;
260 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
261 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
262 if (cmd_buffer == NULL)
263 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
264
265 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
266 cmd_buffer->device = device;
267 cmd_buffer->pool = pool;
268 cmd_buffer->level = level;
269
270 if (pool) {
271 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
272 cmd_buffer->queue_family_index = pool->queue_family_index;
273
274 } else {
275 /* Init the pool_link so we can safely call list_del when we destroy
276 * the command buffer
277 */
278 list_inithead(&cmd_buffer->pool_link);
279 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
280 }
281
282 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
283
284 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
285 if (!cmd_buffer->cs) {
286 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
287 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
288 }
289
290 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
291
292 list_inithead(&cmd_buffer->upload.list);
293
294 return VK_SUCCESS;
295 }
296
297 static void
298 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
299 {
300 list_del(&cmd_buffer->pool_link);
301
302 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
303 &cmd_buffer->upload.list, list) {
304 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
305 list_del(&up->list);
306 free(up);
307 }
308
309 if (cmd_buffer->upload.upload_bo)
310 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
311 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
312
313 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
314 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
315
316 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
317 }
318
319 static VkResult
320 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
321 {
322 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
323
324 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
325 &cmd_buffer->upload.list, list) {
326 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
327 list_del(&up->list);
328 free(up);
329 }
330
331 cmd_buffer->push_constant_stages = 0;
332 cmd_buffer->scratch_size_needed = 0;
333 cmd_buffer->compute_scratch_size_needed = 0;
334 cmd_buffer->esgs_ring_size_needed = 0;
335 cmd_buffer->gsvs_ring_size_needed = 0;
336 cmd_buffer->tess_rings_needed = false;
337 cmd_buffer->sample_positions_needed = false;
338
339 if (cmd_buffer->upload.upload_bo)
340 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
341 cmd_buffer->upload.upload_bo);
342 cmd_buffer->upload.offset = 0;
343
344 cmd_buffer->record_result = VK_SUCCESS;
345
346 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
347
348 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
349 cmd_buffer->descriptors[i].dirty = 0;
350 cmd_buffer->descriptors[i].valid = 0;
351 cmd_buffer->descriptors[i].push_dirty = false;
352 }
353
354 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
355 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
356 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
357 unsigned fence_offset, eop_bug_offset;
358 void *fence_ptr;
359
360 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
361 &fence_ptr);
362
363 cmd_buffer->gfx9_fence_va =
364 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
365 cmd_buffer->gfx9_fence_va += fence_offset;
366
367 /* Allocate a buffer for the EOP bug on GFX9. */
368 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
369 &eop_bug_offset, &fence_ptr);
370 cmd_buffer->gfx9_eop_bug_va =
371 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
372 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
373 }
374
375 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
376
377 return cmd_buffer->record_result;
378 }
379
380 static bool
381 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
382 uint64_t min_needed)
383 {
384 uint64_t new_size;
385 struct radeon_winsys_bo *bo;
386 struct radv_cmd_buffer_upload *upload;
387 struct radv_device *device = cmd_buffer->device;
388
389 new_size = MAX2(min_needed, 16 * 1024);
390 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
391
392 bo = device->ws->buffer_create(device->ws,
393 new_size, 4096,
394 RADEON_DOMAIN_GTT,
395 RADEON_FLAG_CPU_ACCESS|
396 RADEON_FLAG_NO_INTERPROCESS_SHARING |
397 RADEON_FLAG_32BIT,
398 RADV_BO_PRIORITY_UPLOAD_BUFFER);
399
400 if (!bo) {
401 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
402 return false;
403 }
404
405 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
406 if (cmd_buffer->upload.upload_bo) {
407 upload = malloc(sizeof(*upload));
408
409 if (!upload) {
410 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
411 device->ws->buffer_destroy(bo);
412 return false;
413 }
414
415 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
416 list_add(&upload->list, &cmd_buffer->upload.list);
417 }
418
419 cmd_buffer->upload.upload_bo = bo;
420 cmd_buffer->upload.size = new_size;
421 cmd_buffer->upload.offset = 0;
422 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
423
424 if (!cmd_buffer->upload.map) {
425 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
426 return false;
427 }
428
429 return true;
430 }
431
432 bool
433 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
434 unsigned size,
435 unsigned alignment,
436 unsigned *out_offset,
437 void **ptr)
438 {
439 assert(util_is_power_of_two_nonzero(alignment));
440
441 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
442 if (offset + size > cmd_buffer->upload.size) {
443 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
444 return false;
445 offset = 0;
446 }
447
448 *out_offset = offset;
449 *ptr = cmd_buffer->upload.map + offset;
450
451 cmd_buffer->upload.offset = offset + size;
452 return true;
453 }
454
455 bool
456 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
457 unsigned size, unsigned alignment,
458 const void *data, unsigned *out_offset)
459 {
460 uint8_t *ptr;
461
462 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
463 out_offset, (void **)&ptr))
464 return false;
465
466 if (ptr)
467 memcpy(ptr, data, size);
468
469 return true;
470 }
471
472 static void
473 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
474 unsigned count, const uint32_t *data)
475 {
476 struct radeon_cmdbuf *cs = cmd_buffer->cs;
477
478 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
479
480 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
481 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
482 S_370_WR_CONFIRM(1) |
483 S_370_ENGINE_SEL(V_370_ME));
484 radeon_emit(cs, va);
485 radeon_emit(cs, va >> 32);
486 radeon_emit_array(cs, data, count);
487 }
488
489 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
490 {
491 struct radv_device *device = cmd_buffer->device;
492 struct radeon_cmdbuf *cs = cmd_buffer->cs;
493 uint64_t va;
494
495 va = radv_buffer_get_va(device->trace_bo);
496 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
497 va += 4;
498
499 ++cmd_buffer->state.trace_id;
500 radv_emit_write_data_packet(cmd_buffer, va, 1,
501 &cmd_buffer->state.trace_id);
502
503 radeon_check_space(cmd_buffer->device->ws, cs, 2);
504
505 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
506 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
507 }
508
509 static void
510 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
511 enum radv_cmd_flush_bits flags)
512 {
513 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
514 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
515 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
516
517 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
518
519 /* Force wait for graphics or compute engines to be idle. */
520 si_cs_emit_cache_flush(cmd_buffer->cs,
521 cmd_buffer->device->physical_device->rad_info.chip_class,
522 &cmd_buffer->gfx9_fence_idx,
523 cmd_buffer->gfx9_fence_va,
524 radv_cmd_buffer_uses_mec(cmd_buffer),
525 flags, cmd_buffer->gfx9_eop_bug_va);
526 }
527
528 if (unlikely(cmd_buffer->device->trace_bo))
529 radv_cmd_buffer_trace_emit(cmd_buffer);
530 }
531
532 static void
533 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
534 struct radv_pipeline *pipeline, enum ring_type ring)
535 {
536 struct radv_device *device = cmd_buffer->device;
537 uint32_t data[2];
538 uint64_t va;
539
540 va = radv_buffer_get_va(device->trace_bo);
541
542 switch (ring) {
543 case RING_GFX:
544 va += 8;
545 break;
546 case RING_COMPUTE:
547 va += 16;
548 break;
549 default:
550 assert(!"invalid ring type");
551 }
552
553 data[0] = (uintptr_t)pipeline;
554 data[1] = (uintptr_t)pipeline >> 32;
555
556 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
557 }
558
559 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
560 VkPipelineBindPoint bind_point,
561 struct radv_descriptor_set *set,
562 unsigned idx)
563 {
564 struct radv_descriptor_state *descriptors_state =
565 radv_get_descriptors_state(cmd_buffer, bind_point);
566
567 descriptors_state->sets[idx] = set;
568
569 descriptors_state->valid |= (1u << idx); /* active descriptors */
570 descriptors_state->dirty |= (1u << idx);
571 }
572
573 static void
574 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
575 VkPipelineBindPoint bind_point)
576 {
577 struct radv_descriptor_state *descriptors_state =
578 radv_get_descriptors_state(cmd_buffer, bind_point);
579 struct radv_device *device = cmd_buffer->device;
580 uint32_t data[MAX_SETS * 2] = {};
581 uint64_t va;
582 unsigned i;
583 va = radv_buffer_get_va(device->trace_bo) + 24;
584
585 for_each_bit(i, descriptors_state->valid) {
586 struct radv_descriptor_set *set = descriptors_state->sets[i];
587 data[i * 2] = (uint64_t)(uintptr_t)set;
588 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
589 }
590
591 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
592 }
593
594 struct radv_userdata_info *
595 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
596 gl_shader_stage stage,
597 int idx)
598 {
599 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
600 return &shader->info.user_sgprs_locs.shader_data[idx];
601 }
602
603 static void
604 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
605 struct radv_pipeline *pipeline,
606 gl_shader_stage stage,
607 int idx, uint64_t va)
608 {
609 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
610 uint32_t base_reg = pipeline->user_data_0[stage];
611 if (loc->sgpr_idx == -1)
612 return;
613
614 assert(loc->num_sgprs == 1);
615
616 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
617 base_reg + loc->sgpr_idx * 4, va, false);
618 }
619
620 static void
621 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
622 struct radv_pipeline *pipeline,
623 struct radv_descriptor_state *descriptors_state,
624 gl_shader_stage stage)
625 {
626 struct radv_device *device = cmd_buffer->device;
627 struct radeon_cmdbuf *cs = cmd_buffer->cs;
628 uint32_t sh_base = pipeline->user_data_0[stage];
629 struct radv_userdata_locations *locs =
630 &pipeline->shaders[stage]->info.user_sgprs_locs;
631 unsigned mask = locs->descriptor_sets_enabled;
632
633 mask &= descriptors_state->dirty & descriptors_state->valid;
634
635 while (mask) {
636 int start, count;
637
638 u_bit_scan_consecutive_range(&mask, &start, &count);
639
640 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
641 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
642
643 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
644 for (int i = 0; i < count; i++) {
645 struct radv_descriptor_set *set =
646 descriptors_state->sets[start + i];
647
648 radv_emit_shader_pointer_body(device, cs, set->va, true);
649 }
650 }
651 }
652
653 /**
654 * Convert the user sample locations to hardware sample locations (the values
655 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
656 */
657 static void
658 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
659 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
660 {
661 uint32_t x_offset = x % state->grid_size.width;
662 uint32_t y_offset = y % state->grid_size.height;
663 uint32_t num_samples = (uint32_t)state->per_pixel;
664 VkSampleLocationEXT *user_locs;
665 uint32_t pixel_offset;
666
667 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
668
669 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
670 user_locs = &state->locations[pixel_offset];
671
672 for (uint32_t i = 0; i < num_samples; i++) {
673 float shifted_pos_x = user_locs[i].x - 0.5;
674 float shifted_pos_y = user_locs[i].y - 0.5;
675
676 int32_t scaled_pos_x = floor(shifted_pos_x * 16);
677 int32_t scaled_pos_y = floor(shifted_pos_y * 16);
678
679 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
680 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
681 }
682 }
683
684 /**
685 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
686 * locations.
687 */
688 static void
689 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
690 uint32_t *sample_locs_pixel)
691 {
692 for (uint32_t i = 0; i < num_samples; i++) {
693 uint32_t sample_reg_idx = i / 4;
694 uint32_t sample_loc_idx = i % 4;
695 int32_t pos_x = sample_locs[i].x;
696 int32_t pos_y = sample_locs[i].y;
697
698 uint32_t shift_x = 8 * sample_loc_idx;
699 uint32_t shift_y = shift_x + 4;
700
701 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
702 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
703 }
704 }
705
706 /**
707 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
708 * sample locations.
709 */
710 static uint64_t
711 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
712 VkOffset2D *sample_locs,
713 uint32_t num_samples)
714 {
715 uint32_t centroid_priorities[num_samples];
716 uint32_t sample_mask = num_samples - 1;
717 uint32_t distances[num_samples];
718 uint64_t centroid_priority = 0;
719
720 /* Compute the distances from center for each sample. */
721 for (int i = 0; i < num_samples; i++) {
722 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
723 (sample_locs[i].y * sample_locs[i].y);
724 }
725
726 /* Compute the centroid priorities by looking at the distances array. */
727 for (int i = 0; i < num_samples; i++) {
728 uint32_t min_idx = 0;
729
730 for (int j = 1; j < num_samples; j++) {
731 if (distances[j] < distances[min_idx])
732 min_idx = j;
733 }
734
735 centroid_priorities[i] = min_idx;
736 distances[min_idx] = 0xffffffff;
737 }
738
739 /* Compute the final centroid priority. */
740 for (int i = 0; i < 8; i++) {
741 centroid_priority |=
742 centroid_priorities[i & sample_mask] << (i * 4);
743 }
744
745 return centroid_priority << 32 | centroid_priority;
746 }
747
748 /**
749 * Emit the sample locations that are specified with VK_EXT_sample_locations.
750 */
751 static void
752 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
753 {
754 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
755 struct radv_multisample_state *ms = &pipeline->graphics.ms;
756 struct radv_sample_locations_state *sample_location =
757 &cmd_buffer->state.dynamic.sample_location;
758 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
759 struct radeon_cmdbuf *cs = cmd_buffer->cs;
760 uint32_t sample_locs_pixel[4][2] = {};
761 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
762 uint32_t max_sample_dist = 0;
763 uint64_t centroid_priority;
764
765 if (!cmd_buffer->state.dynamic.sample_location.count)
766 return;
767
768 /* Convert the user sample locations to hardware sample locations. */
769 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
770 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
771 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
772 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
773
774 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
775 for (uint32_t i = 0; i < 4; i++) {
776 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
777 sample_locs_pixel[i]);
778 }
779
780 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
781 centroid_priority =
782 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
783 num_samples);
784
785 /* Compute the maximum sample distance from the specified locations. */
786 for (uint32_t i = 0; i < num_samples; i++) {
787 VkOffset2D offset = sample_locs[0][i];
788 max_sample_dist = MAX2(max_sample_dist,
789 MAX2(abs(offset.x), abs(offset.y)));
790 }
791
792 /* Emit the specified user sample locations. */
793 switch (num_samples) {
794 case 2:
795 case 4:
796 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
797 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
798 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
799 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
800 break;
801 case 8:
802 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
803 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
804 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
805 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
806 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
807 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
808 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
809 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
810 break;
811 default:
812 unreachable("invalid number of samples");
813 }
814
815 /* Emit the maximum sample distance and the centroid priority. */
816 uint32_t pa_sc_aa_config = ms->pa_sc_aa_config;
817
818 pa_sc_aa_config &= C_028BE0_MAX_SAMPLE_DIST;
819 pa_sc_aa_config |= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist);
820
821 radeon_set_context_reg_seq(cs, R_028BE0_PA_SC_AA_CONFIG, 1);
822 radeon_emit(cs, pa_sc_aa_config);
823
824 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
825 radeon_emit(cs, centroid_priority);
826 radeon_emit(cs, centroid_priority >> 32);
827
828 /* GFX9: Flush DFSM when the AA mode changes. */
829 if (cmd_buffer->device->dfsm_allowed) {
830 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
831 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
832 }
833
834 cmd_buffer->state.context_roll_without_scissor_emitted = true;
835 }
836
837 static void
838 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
839 struct radv_pipeline *pipeline,
840 gl_shader_stage stage,
841 int idx, int count, uint32_t *values)
842 {
843 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
844 uint32_t base_reg = pipeline->user_data_0[stage];
845 if (loc->sgpr_idx == -1)
846 return;
847
848 assert(loc->num_sgprs == count);
849
850 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
851 radeon_emit_array(cmd_buffer->cs, values, count);
852 }
853
854 static void
855 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
856 struct radv_pipeline *pipeline)
857 {
858 int num_samples = pipeline->graphics.ms.num_samples;
859 struct radv_multisample_state *ms = &pipeline->graphics.ms;
860 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
861
862 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
863 cmd_buffer->sample_positions_needed = true;
864
865 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
866 return;
867
868 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
869 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
870 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
871
872 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
873
874 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
875
876 /* GFX9: Flush DFSM when the AA mode changes. */
877 if (cmd_buffer->device->dfsm_allowed) {
878 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
879 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
880 }
881
882 cmd_buffer->state.context_roll_without_scissor_emitted = true;
883 }
884
885 static void
886 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
887 struct radv_shader_variant *shader)
888 {
889 uint64_t va;
890
891 if (!shader)
892 return;
893
894 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
895
896 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
897 }
898
899 static void
900 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
901 struct radv_pipeline *pipeline,
902 bool vertex_stage_only)
903 {
904 struct radv_cmd_state *state = &cmd_buffer->state;
905 uint32_t mask = state->prefetch_L2_mask;
906
907 if (vertex_stage_only) {
908 /* Fast prefetch path for starting draws as soon as possible.
909 */
910 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
911 RADV_PREFETCH_VBO_DESCRIPTORS);
912 }
913
914 if (mask & RADV_PREFETCH_VS)
915 radv_emit_shader_prefetch(cmd_buffer,
916 pipeline->shaders[MESA_SHADER_VERTEX]);
917
918 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
919 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
920
921 if (mask & RADV_PREFETCH_TCS)
922 radv_emit_shader_prefetch(cmd_buffer,
923 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
924
925 if (mask & RADV_PREFETCH_TES)
926 radv_emit_shader_prefetch(cmd_buffer,
927 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
928
929 if (mask & RADV_PREFETCH_GS) {
930 radv_emit_shader_prefetch(cmd_buffer,
931 pipeline->shaders[MESA_SHADER_GEOMETRY]);
932 if (radv_pipeline_has_gs_copy_shader(pipeline))
933 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
934 }
935
936 if (mask & RADV_PREFETCH_PS)
937 radv_emit_shader_prefetch(cmd_buffer,
938 pipeline->shaders[MESA_SHADER_FRAGMENT]);
939
940 state->prefetch_L2_mask &= ~mask;
941 }
942
943 static void
944 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
945 {
946 if (!cmd_buffer->device->physical_device->rbplus_allowed)
947 return;
948
949 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
950 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
951 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
952
953 unsigned sx_ps_downconvert = 0;
954 unsigned sx_blend_opt_epsilon = 0;
955 unsigned sx_blend_opt_control = 0;
956
957 for (unsigned i = 0; i < subpass->color_count; ++i) {
958 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
959 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
960 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
961 continue;
962 }
963
964 int idx = subpass->color_attachments[i].attachment;
965 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
966
967 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
968 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
969 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
970 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
971
972 bool has_alpha, has_rgb;
973
974 /* Set if RGB and A are present. */
975 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
976
977 if (format == V_028C70_COLOR_8 ||
978 format == V_028C70_COLOR_16 ||
979 format == V_028C70_COLOR_32)
980 has_rgb = !has_alpha;
981 else
982 has_rgb = true;
983
984 /* Check the colormask and export format. */
985 if (!(colormask & 0x7))
986 has_rgb = false;
987 if (!(colormask & 0x8))
988 has_alpha = false;
989
990 if (spi_format == V_028714_SPI_SHADER_ZERO) {
991 has_rgb = false;
992 has_alpha = false;
993 }
994
995 /* Disable value checking for disabled channels. */
996 if (!has_rgb)
997 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
998 if (!has_alpha)
999 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1000
1001 /* Enable down-conversion for 32bpp and smaller formats. */
1002 switch (format) {
1003 case V_028C70_COLOR_8:
1004 case V_028C70_COLOR_8_8:
1005 case V_028C70_COLOR_8_8_8_8:
1006 /* For 1 and 2-channel formats, use the superset thereof. */
1007 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1008 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1009 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1010 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1011 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1012 }
1013 break;
1014
1015 case V_028C70_COLOR_5_6_5:
1016 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1017 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1018 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1019 }
1020 break;
1021
1022 case V_028C70_COLOR_1_5_5_5:
1023 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1024 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1025 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1026 }
1027 break;
1028
1029 case V_028C70_COLOR_4_4_4_4:
1030 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1031 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1032 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1033 }
1034 break;
1035
1036 case V_028C70_COLOR_32:
1037 if (swap == V_028C70_SWAP_STD &&
1038 spi_format == V_028714_SPI_SHADER_32_R)
1039 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1040 else if (swap == V_028C70_SWAP_ALT_REV &&
1041 spi_format == V_028714_SPI_SHADER_32_AR)
1042 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1043 break;
1044
1045 case V_028C70_COLOR_16:
1046 case V_028C70_COLOR_16_16:
1047 /* For 1-channel formats, use the superset thereof. */
1048 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1049 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1050 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1051 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1052 if (swap == V_028C70_SWAP_STD ||
1053 swap == V_028C70_SWAP_STD_REV)
1054 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1055 else
1056 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1057 }
1058 break;
1059
1060 case V_028C70_COLOR_10_11_11:
1061 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1062 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1063 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1064 }
1065 break;
1066
1067 case V_028C70_COLOR_2_10_10_10:
1068 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1069 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1070 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1071 }
1072 break;
1073 }
1074 }
1075
1076 for (unsigned i = subpass->color_count; i < 8; ++i) {
1077 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1078 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1079 }
1080 /* TODO: avoid redundantly setting context registers */
1081 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1082 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1083 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1084 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1085
1086 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1087 }
1088
1089 static void
1090 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1091 {
1092 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1093
1094 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1095 return;
1096
1097 radv_update_multisample_state(cmd_buffer, pipeline);
1098
1099 cmd_buffer->scratch_size_needed =
1100 MAX2(cmd_buffer->scratch_size_needed,
1101 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1102
1103 if (!cmd_buffer->state.emitted_pipeline ||
1104 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1105 pipeline->graphics.can_use_guardband)
1106 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1107
1108 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1109
1110 if (!cmd_buffer->state.emitted_pipeline ||
1111 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1112 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1113 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1114 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1115 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1116 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1117 }
1118
1119 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1120 if (!pipeline->shaders[i])
1121 continue;
1122
1123 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1124 pipeline->shaders[i]->bo);
1125 }
1126
1127 if (radv_pipeline_has_gs_copy_shader(pipeline))
1128 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1129 pipeline->gs_copy_shader->bo);
1130
1131 if (unlikely(cmd_buffer->device->trace_bo))
1132 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1133
1134 cmd_buffer->state.emitted_pipeline = pipeline;
1135
1136 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1137 }
1138
1139 static void
1140 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1141 {
1142 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1143 cmd_buffer->state.dynamic.viewport.viewports);
1144 }
1145
1146 static void
1147 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1148 {
1149 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1150
1151 si_write_scissors(cmd_buffer->cs, 0, count,
1152 cmd_buffer->state.dynamic.scissor.scissors,
1153 cmd_buffer->state.dynamic.viewport.viewports,
1154 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1155
1156 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1157 }
1158
1159 static void
1160 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1161 {
1162 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1163 return;
1164
1165 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1166 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1167 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1168 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1169 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1170 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1171 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1172 }
1173 }
1174
1175 static void
1176 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1177 {
1178 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1179
1180 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1181 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1182 }
1183
1184 static void
1185 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1186 {
1187 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1188
1189 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1190 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1191 }
1192
1193 static void
1194 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1195 {
1196 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1197
1198 radeon_set_context_reg_seq(cmd_buffer->cs,
1199 R_028430_DB_STENCILREFMASK, 2);
1200 radeon_emit(cmd_buffer->cs,
1201 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1202 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1203 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1204 S_028430_STENCILOPVAL(1));
1205 radeon_emit(cmd_buffer->cs,
1206 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1207 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1208 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1209 S_028434_STENCILOPVAL_BF(1));
1210 }
1211
1212 static void
1213 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1214 {
1215 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1216
1217 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1218 fui(d->depth_bounds.min));
1219 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1220 fui(d->depth_bounds.max));
1221 }
1222
1223 static void
1224 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1225 {
1226 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1227 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1228 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1229
1230
1231 radeon_set_context_reg_seq(cmd_buffer->cs,
1232 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1233 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1234 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1235 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1236 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1237 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1238 }
1239
1240 static void
1241 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1242 int index,
1243 struct radv_attachment_info *att,
1244 struct radv_image_view *iview,
1245 VkImageLayout layout)
1246 {
1247 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1248 struct radv_color_buffer_info *cb = &att->cb;
1249 uint32_t cb_color_info = cb->cb_color_info;
1250 struct radv_image *image = iview->image;
1251
1252 if (!radv_layout_dcc_compressed(image, layout,
1253 radv_image_queue_family_mask(image,
1254 cmd_buffer->queue_family_index,
1255 cmd_buffer->queue_family_index))) {
1256 cb_color_info &= C_028C70_DCC_ENABLE;
1257 }
1258
1259 if (radv_image_is_tc_compat_cmask(image) &&
1260 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1261 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1262 /* If this bit is set, the FMASK decompression operation
1263 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1264 */
1265 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1266 }
1267
1268 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1269 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1270 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1271 radeon_emit(cmd_buffer->cs, 0);
1272 radeon_emit(cmd_buffer->cs, 0);
1273 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1274 radeon_emit(cmd_buffer->cs, cb_color_info);
1275 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1276 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1277 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1278 radeon_emit(cmd_buffer->cs, 0);
1279 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1280 radeon_emit(cmd_buffer->cs, 0);
1281
1282 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1283 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1284
1285 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1286 cb->cb_color_base >> 32);
1287 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1288 cb->cb_color_cmask >> 32);
1289 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1290 cb->cb_color_fmask >> 32);
1291 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1292 cb->cb_dcc_base >> 32);
1293 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1294 cb->cb_color_attrib2);
1295 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1296 cb->cb_color_attrib3);
1297 } else if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1298 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1299 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1300 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1301 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1302 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1303 radeon_emit(cmd_buffer->cs, cb_color_info);
1304 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1305 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1306 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1307 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1308 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1309 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1310
1311 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1312 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1313 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1314
1315 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1316 cb->cb_mrt_epitch);
1317 } else {
1318 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1319 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1320 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1321 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1322 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1323 radeon_emit(cmd_buffer->cs, cb_color_info);
1324 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1325 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1326 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1327 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1328 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1329 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1330
1331 if (is_vi) { /* DCC BASE */
1332 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1333 }
1334 }
1335
1336 if (radv_dcc_enabled(image, iview->base_mip)) {
1337 /* Drawing with DCC enabled also compresses colorbuffers. */
1338 VkImageSubresourceRange range = {
1339 .aspectMask = iview->aspect_mask,
1340 .baseMipLevel = iview->base_mip,
1341 .levelCount = iview->level_count,
1342 .baseArrayLayer = iview->base_layer,
1343 .layerCount = iview->layer_count,
1344 };
1345
1346 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1347 }
1348 }
1349
1350 static void
1351 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1352 struct radv_ds_buffer_info *ds,
1353 struct radv_image *image, VkImageLayout layout,
1354 bool requires_cond_exec)
1355 {
1356 uint32_t db_z_info = ds->db_z_info;
1357 uint32_t db_z_info_reg;
1358
1359 if (!cmd_buffer->device->physical_device->has_tc_compat_zrange_bug ||
1360 !radv_image_is_tc_compat_htile(image))
1361 return;
1362
1363 if (!radv_layout_has_htile(image, layout,
1364 radv_image_queue_family_mask(image,
1365 cmd_buffer->queue_family_index,
1366 cmd_buffer->queue_family_index))) {
1367 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1368 }
1369
1370 db_z_info &= C_028040_ZRANGE_PRECISION;
1371
1372 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1373 db_z_info_reg = R_028038_DB_Z_INFO;
1374 } else {
1375 db_z_info_reg = R_028040_DB_Z_INFO;
1376 }
1377
1378 /* When we don't know the last fast clear value we need to emit a
1379 * conditional packet that will eventually skip the following
1380 * SET_CONTEXT_REG packet.
1381 */
1382 if (requires_cond_exec) {
1383 uint64_t va = radv_buffer_get_va(image->bo);
1384 va += image->offset + image->tc_compat_zrange_offset;
1385
1386 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1387 radeon_emit(cmd_buffer->cs, va);
1388 radeon_emit(cmd_buffer->cs, va >> 32);
1389 radeon_emit(cmd_buffer->cs, 0);
1390 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1391 }
1392
1393 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1394 }
1395
1396 static void
1397 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1398 struct radv_ds_buffer_info *ds,
1399 struct radv_image *image,
1400 VkImageLayout layout)
1401 {
1402 uint32_t db_z_info = ds->db_z_info;
1403 uint32_t db_stencil_info = ds->db_stencil_info;
1404
1405 if (!radv_layout_has_htile(image, layout,
1406 radv_image_queue_family_mask(image,
1407 cmd_buffer->queue_family_index,
1408 cmd_buffer->queue_family_index))) {
1409 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1410 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1411 }
1412
1413 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1414 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1415
1416 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1417 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1418 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1419
1420 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1421 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1422 radeon_emit(cmd_buffer->cs, db_z_info);
1423 radeon_emit(cmd_buffer->cs, db_stencil_info);
1424 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1425 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1426 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1427 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1428
1429 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 5);
1430 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1431 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1432 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1433 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1434 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1435 } else if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1436 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1437 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1438 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1439 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1440
1441 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1442 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1443 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1444 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1445 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1446 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1447 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1448 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1449 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1450 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1451 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1452
1453 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1454 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1455 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1456 } else {
1457 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1458
1459 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1460 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1461 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1462 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1463 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1464 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1465 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1466 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1467 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1468 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1469
1470 }
1471
1472 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1473 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1474
1475 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1476 ds->pa_su_poly_offset_db_fmt_cntl);
1477 }
1478
1479 /**
1480 * Update the fast clear depth/stencil values if the image is bound as a
1481 * depth/stencil buffer.
1482 */
1483 static void
1484 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1485 struct radv_image *image,
1486 VkClearDepthStencilValue ds_clear_value,
1487 VkImageAspectFlags aspects)
1488 {
1489 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1490 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1491 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1492 struct radv_attachment_info *att;
1493 uint32_t att_idx;
1494
1495 if (!framebuffer || !subpass)
1496 return;
1497
1498 if (!subpass->depth_stencil_attachment)
1499 return;
1500
1501 att_idx = subpass->depth_stencil_attachment->attachment;
1502 att = &framebuffer->attachments[att_idx];
1503 if (att->attachment->image != image)
1504 return;
1505
1506 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1507 radeon_emit(cs, ds_clear_value.stencil);
1508 radeon_emit(cs, fui(ds_clear_value.depth));
1509
1510 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1511 * only needed when clearing Z to 0.0.
1512 */
1513 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1514 ds_clear_value.depth == 0.0) {
1515 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1516
1517 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1518 layout, false);
1519 }
1520
1521 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1522 }
1523
1524 /**
1525 * Set the clear depth/stencil values to the image's metadata.
1526 */
1527 static void
1528 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1529 struct radv_image *image,
1530 VkClearDepthStencilValue ds_clear_value,
1531 VkImageAspectFlags aspects)
1532 {
1533 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1534 uint64_t va = radv_buffer_get_va(image->bo);
1535 unsigned reg_offset = 0, reg_count = 0;
1536
1537 va += image->offset + image->clear_value_offset;
1538
1539 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1540 ++reg_count;
1541 } else {
1542 ++reg_offset;
1543 va += 4;
1544 }
1545 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1546 ++reg_count;
1547
1548 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, cmd_buffer->state.predicating));
1549 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1550 S_370_WR_CONFIRM(1) |
1551 S_370_ENGINE_SEL(V_370_PFP));
1552 radeon_emit(cs, va);
1553 radeon_emit(cs, va >> 32);
1554 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1555 radeon_emit(cs, ds_clear_value.stencil);
1556 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1557 radeon_emit(cs, fui(ds_clear_value.depth));
1558 }
1559
1560 /**
1561 * Update the TC-compat metadata value for this image.
1562 */
1563 static void
1564 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1565 struct radv_image *image,
1566 uint32_t value)
1567 {
1568 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1569 uint64_t va = radv_buffer_get_va(image->bo);
1570
1571 if (!cmd_buffer->device->physical_device->has_tc_compat_zrange_bug)
1572 return;
1573
1574 va += image->offset + image->tc_compat_zrange_offset;
1575
1576 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1577 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1578 S_370_WR_CONFIRM(1) |
1579 S_370_ENGINE_SEL(V_370_PFP));
1580 radeon_emit(cs, va);
1581 radeon_emit(cs, va >> 32);
1582 radeon_emit(cs, value);
1583 }
1584
1585 static void
1586 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1587 struct radv_image *image,
1588 VkClearDepthStencilValue ds_clear_value)
1589 {
1590 uint32_t cond_val;
1591
1592 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1593 * depth clear value is 0.0f.
1594 */
1595 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1596
1597 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, cond_val);
1598 }
1599
1600 /**
1601 * Update the clear depth/stencil values for this image.
1602 */
1603 void
1604 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1605 struct radv_image *image,
1606 VkClearDepthStencilValue ds_clear_value,
1607 VkImageAspectFlags aspects)
1608 {
1609 assert(radv_image_has_htile(image));
1610
1611 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1612
1613 if (radv_image_is_tc_compat_htile(image) &&
1614 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1615 radv_update_tc_compat_zrange_metadata(cmd_buffer, image,
1616 ds_clear_value);
1617 }
1618
1619 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1620 aspects);
1621 }
1622
1623 /**
1624 * Load the clear depth/stencil values from the image's metadata.
1625 */
1626 static void
1627 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1628 struct radv_image *image)
1629 {
1630 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1631 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1632 uint64_t va = radv_buffer_get_va(image->bo);
1633 unsigned reg_offset = 0, reg_count = 0;
1634
1635 va += image->offset + image->clear_value_offset;
1636
1637 if (!radv_image_has_htile(image))
1638 return;
1639
1640 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1641 ++reg_count;
1642 } else {
1643 ++reg_offset;
1644 va += 4;
1645 }
1646 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1647 ++reg_count;
1648
1649 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1650
1651 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1652 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1653 radeon_emit(cs, va);
1654 radeon_emit(cs, va >> 32);
1655 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1656 radeon_emit(cs, reg_count);
1657 } else {
1658 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1659 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1660 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1661 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1662 radeon_emit(cs, va);
1663 radeon_emit(cs, va >> 32);
1664 radeon_emit(cs, reg >> 2);
1665 radeon_emit(cs, 0);
1666
1667 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1668 radeon_emit(cs, 0);
1669 }
1670 }
1671
1672 /*
1673 * With DCC some colors don't require CMASK elimination before being
1674 * used as a texture. This sets a predicate value to determine if the
1675 * cmask eliminate is required.
1676 */
1677 void
1678 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1679 struct radv_image *image,
1680 const VkImageSubresourceRange *range, bool value)
1681 {
1682 uint64_t pred_val = value;
1683 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
1684 uint32_t level_count = radv_get_levelCount(image, range);
1685 uint32_t count = 2 * level_count;
1686
1687 assert(radv_dcc_enabled(image, range->baseMipLevel));
1688
1689 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1690 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1691 S_370_WR_CONFIRM(1) |
1692 S_370_ENGINE_SEL(V_370_PFP));
1693 radeon_emit(cmd_buffer->cs, va);
1694 radeon_emit(cmd_buffer->cs, va >> 32);
1695
1696 for (uint32_t l = 0; l < level_count; l++) {
1697 radeon_emit(cmd_buffer->cs, pred_val);
1698 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1699 }
1700 }
1701
1702 /**
1703 * Update the DCC predicate to reflect the compression state.
1704 */
1705 void
1706 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1707 struct radv_image *image,
1708 const VkImageSubresourceRange *range, bool value)
1709 {
1710 uint64_t pred_val = value;
1711 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
1712 uint32_t level_count = radv_get_levelCount(image, range);
1713 uint32_t count = 2 * level_count;
1714
1715 assert(radv_dcc_enabled(image, range->baseMipLevel));
1716
1717 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1718 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1719 S_370_WR_CONFIRM(1) |
1720 S_370_ENGINE_SEL(V_370_PFP));
1721 radeon_emit(cmd_buffer->cs, va);
1722 radeon_emit(cmd_buffer->cs, va >> 32);
1723
1724 for (uint32_t l = 0; l < level_count; l++) {
1725 radeon_emit(cmd_buffer->cs, pred_val);
1726 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1727 }
1728 }
1729
1730 /**
1731 * Update the fast clear color values if the image is bound as a color buffer.
1732 */
1733 static void
1734 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1735 struct radv_image *image,
1736 int cb_idx,
1737 uint32_t color_values[2])
1738 {
1739 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1740 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1741 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1742 struct radv_attachment_info *att;
1743 uint32_t att_idx;
1744
1745 if (!framebuffer || !subpass)
1746 return;
1747
1748 att_idx = subpass->color_attachments[cb_idx].attachment;
1749 if (att_idx == VK_ATTACHMENT_UNUSED)
1750 return;
1751
1752 att = &framebuffer->attachments[att_idx];
1753 if (att->attachment->image != image)
1754 return;
1755
1756 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1757 radeon_emit(cs, color_values[0]);
1758 radeon_emit(cs, color_values[1]);
1759
1760 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1761 }
1762
1763 /**
1764 * Set the clear color values to the image's metadata.
1765 */
1766 static void
1767 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1768 struct radv_image *image,
1769 const VkImageSubresourceRange *range,
1770 uint32_t color_values[2])
1771 {
1772 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1773 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
1774 uint32_t level_count = radv_get_levelCount(image, range);
1775 uint32_t count = 2 * level_count;
1776
1777 assert(radv_image_has_cmask(image) ||
1778 radv_dcc_enabled(image, range->baseMipLevel));
1779
1780 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
1781 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1782 S_370_WR_CONFIRM(1) |
1783 S_370_ENGINE_SEL(V_370_PFP));
1784 radeon_emit(cs, va);
1785 radeon_emit(cs, va >> 32);
1786
1787 for (uint32_t l = 0; l < level_count; l++) {
1788 radeon_emit(cs, color_values[0]);
1789 radeon_emit(cs, color_values[1]);
1790 }
1791 }
1792
1793 /**
1794 * Update the clear color values for this image.
1795 */
1796 void
1797 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1798 const struct radv_image_view *iview,
1799 int cb_idx,
1800 uint32_t color_values[2])
1801 {
1802 struct radv_image *image = iview->image;
1803 VkImageSubresourceRange range = {
1804 .aspectMask = iview->aspect_mask,
1805 .baseMipLevel = iview->base_mip,
1806 .levelCount = iview->level_count,
1807 .baseArrayLayer = iview->base_layer,
1808 .layerCount = iview->layer_count,
1809 };
1810
1811 assert(radv_image_has_cmask(image) ||
1812 radv_dcc_enabled(image, iview->base_mip));
1813
1814 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
1815
1816 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1817 color_values);
1818 }
1819
1820 /**
1821 * Load the clear color values from the image's metadata.
1822 */
1823 static void
1824 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1825 struct radv_image_view *iview,
1826 int cb_idx)
1827 {
1828 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1829 struct radv_image *image = iview->image;
1830 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
1831
1832 if (!radv_image_has_cmask(image) &&
1833 !radv_dcc_enabled(image, iview->base_mip))
1834 return;
1835
1836 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1837
1838 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1839 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1840 radeon_emit(cs, va);
1841 radeon_emit(cs, va >> 32);
1842 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1843 radeon_emit(cs, 2);
1844 } else {
1845 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1846 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1847 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1848 COPY_DATA_COUNT_SEL);
1849 radeon_emit(cs, va);
1850 radeon_emit(cs, va >> 32);
1851 radeon_emit(cs, reg >> 2);
1852 radeon_emit(cs, 0);
1853
1854 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1855 radeon_emit(cs, 0);
1856 }
1857 }
1858
1859 static void
1860 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1861 {
1862 int i;
1863 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1864 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1865
1866 /* this may happen for inherited secondary recording */
1867 if (!framebuffer)
1868 return;
1869
1870 for (i = 0; i < 8; ++i) {
1871 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1872 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1873 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1874 continue;
1875 }
1876
1877 int idx = subpass->color_attachments[i].attachment;
1878 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1879 struct radv_image_view *iview = att->attachment;
1880 VkImageLayout layout = subpass->color_attachments[i].layout;
1881
1882 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1883
1884 assert(att->attachment->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
1885 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
1886 radv_emit_fb_color_state(cmd_buffer, i, att, iview, layout);
1887
1888 radv_load_color_clear_metadata(cmd_buffer, iview, i);
1889 }
1890
1891 if (subpass->depth_stencil_attachment) {
1892 int idx = subpass->depth_stencil_attachment->attachment;
1893 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1894 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1895 struct radv_image *image = att->attachment->image;
1896 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1897 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1898 cmd_buffer->queue_family_index,
1899 cmd_buffer->queue_family_index);
1900 /* We currently don't support writing decompressed HTILE */
1901 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1902 radv_layout_is_htile_compressed(image, layout, queue_mask));
1903
1904 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1905
1906 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1907 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1908 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1909 }
1910 radv_load_ds_clear_metadata(cmd_buffer, image);
1911 } else {
1912 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
1913 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1914 else
1915 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1916
1917 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1918 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1919 }
1920 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1921 S_028208_BR_X(framebuffer->width) |
1922 S_028208_BR_Y(framebuffer->height));
1923
1924 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
1925 bool disable_constant_encode =
1926 cmd_buffer->device->physical_device->has_dcc_constant_encode;
1927 enum chip_class chip_class =
1928 cmd_buffer->device->physical_device->rad_info.chip_class;
1929 uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
1930
1931 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
1932 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
1933 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
1934 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
1935 }
1936
1937 if (cmd_buffer->device->dfsm_allowed) {
1938 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1939 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1940 }
1941
1942 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1943 }
1944
1945 static void
1946 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1947 {
1948 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1949 struct radv_cmd_state *state = &cmd_buffer->state;
1950
1951 if (state->index_type != state->last_index_type) {
1952 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1953 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
1954 cs, R_03090C_VGT_INDEX_TYPE,
1955 2, state->index_type);
1956 } else {
1957 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1958 radeon_emit(cs, state->index_type);
1959 }
1960
1961 state->last_index_type = state->index_type;
1962 }
1963
1964 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1965 radeon_emit(cs, state->index_va);
1966 radeon_emit(cs, state->index_va >> 32);
1967
1968 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1969 radeon_emit(cs, state->max_index_count);
1970
1971 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1972 }
1973
1974 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1975 {
1976 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1977 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1978 uint32_t pa_sc_mode_cntl_1 =
1979 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1980 uint32_t db_count_control;
1981
1982 if(!cmd_buffer->state.active_occlusion_queries) {
1983 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1984 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1985 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1986 has_perfect_queries) {
1987 /* Re-enable out-of-order rasterization if the
1988 * bound pipeline supports it and if it's has
1989 * been disabled before starting any perfect
1990 * occlusion queries.
1991 */
1992 radeon_set_context_reg(cmd_buffer->cs,
1993 R_028A4C_PA_SC_MODE_CNTL_1,
1994 pa_sc_mode_cntl_1);
1995 }
1996 }
1997 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1998 } else {
1999 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2000 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
2001 bool gfx10_perfect = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries;
2002
2003 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2004 db_count_control =
2005 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
2006 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
2007 S_028004_SAMPLE_RATE(sample_rate) |
2008 S_028004_ZPASS_ENABLE(1) |
2009 S_028004_SLICE_EVEN_ENABLE(1) |
2010 S_028004_SLICE_ODD_ENABLE(1);
2011
2012 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2013 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2014 has_perfect_queries) {
2015 /* If the bound pipeline has enabled
2016 * out-of-order rasterization, we should
2017 * disable it before starting any perfect
2018 * occlusion queries.
2019 */
2020 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2021
2022 radeon_set_context_reg(cmd_buffer->cs,
2023 R_028A4C_PA_SC_MODE_CNTL_1,
2024 pa_sc_mode_cntl_1);
2025 }
2026 } else {
2027 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2028 S_028004_SAMPLE_RATE(sample_rate);
2029 }
2030 }
2031
2032 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2033
2034 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2035 }
2036
2037 static void
2038 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2039 {
2040 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2041
2042 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2043 radv_emit_viewport(cmd_buffer);
2044
2045 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2046 !cmd_buffer->device->physical_device->has_scissor_bug)
2047 radv_emit_scissor(cmd_buffer);
2048
2049 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2050 radv_emit_line_width(cmd_buffer);
2051
2052 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2053 radv_emit_blend_constants(cmd_buffer);
2054
2055 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2056 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2057 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2058 radv_emit_stencil(cmd_buffer);
2059
2060 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2061 radv_emit_depth_bounds(cmd_buffer);
2062
2063 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2064 radv_emit_depth_bias(cmd_buffer);
2065
2066 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2067 radv_emit_discard_rectangle(cmd_buffer);
2068
2069 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2070 radv_emit_sample_locations(cmd_buffer);
2071
2072 cmd_buffer->state.dirty &= ~states;
2073 }
2074
2075 static void
2076 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2077 VkPipelineBindPoint bind_point)
2078 {
2079 struct radv_descriptor_state *descriptors_state =
2080 radv_get_descriptors_state(cmd_buffer, bind_point);
2081 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2082 unsigned bo_offset;
2083
2084 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2085 set->mapped_ptr,
2086 &bo_offset))
2087 return;
2088
2089 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2090 set->va += bo_offset;
2091 }
2092
2093 static void
2094 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2095 VkPipelineBindPoint bind_point)
2096 {
2097 struct radv_descriptor_state *descriptors_state =
2098 radv_get_descriptors_state(cmd_buffer, bind_point);
2099 uint32_t size = MAX_SETS * 4;
2100 uint32_t offset;
2101 void *ptr;
2102
2103 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2104 256, &offset, &ptr))
2105 return;
2106
2107 for (unsigned i = 0; i < MAX_SETS; i++) {
2108 uint32_t *uptr = ((uint32_t *)ptr) + i;
2109 uint64_t set_va = 0;
2110 struct radv_descriptor_set *set = descriptors_state->sets[i];
2111 if (descriptors_state->valid & (1u << i))
2112 set_va = set->va;
2113 uptr[0] = set_va & 0xffffffff;
2114 }
2115
2116 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2117 va += offset;
2118
2119 if (cmd_buffer->state.pipeline) {
2120 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2121 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2122 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2123
2124 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2125 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2126 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2127
2128 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2129 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2130 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2131
2132 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2133 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2134 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2135
2136 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2137 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2138 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2139 }
2140
2141 if (cmd_buffer->state.compute_pipeline)
2142 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2143 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2144 }
2145
2146 static void
2147 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2148 VkShaderStageFlags stages)
2149 {
2150 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2151 VK_PIPELINE_BIND_POINT_COMPUTE :
2152 VK_PIPELINE_BIND_POINT_GRAPHICS;
2153 struct radv_descriptor_state *descriptors_state =
2154 radv_get_descriptors_state(cmd_buffer, bind_point);
2155 struct radv_cmd_state *state = &cmd_buffer->state;
2156 bool flush_indirect_descriptors;
2157
2158 if (!descriptors_state->dirty)
2159 return;
2160
2161 if (descriptors_state->push_dirty)
2162 radv_flush_push_descriptors(cmd_buffer, bind_point);
2163
2164 flush_indirect_descriptors =
2165 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2166 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2167 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2168 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2169
2170 if (flush_indirect_descriptors)
2171 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2172
2173 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2174 cmd_buffer->cs,
2175 MAX_SETS * MESA_SHADER_STAGES * 4);
2176
2177 if (cmd_buffer->state.pipeline) {
2178 radv_foreach_stage(stage, stages) {
2179 if (!cmd_buffer->state.pipeline->shaders[stage])
2180 continue;
2181
2182 radv_emit_descriptor_pointers(cmd_buffer,
2183 cmd_buffer->state.pipeline,
2184 descriptors_state, stage);
2185 }
2186 }
2187
2188 if (cmd_buffer->state.compute_pipeline &&
2189 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2190 radv_emit_descriptor_pointers(cmd_buffer,
2191 cmd_buffer->state.compute_pipeline,
2192 descriptors_state,
2193 MESA_SHADER_COMPUTE);
2194 }
2195
2196 descriptors_state->dirty = 0;
2197 descriptors_state->push_dirty = false;
2198
2199 assert(cmd_buffer->cs->cdw <= cdw_max);
2200
2201 if (unlikely(cmd_buffer->device->trace_bo))
2202 radv_save_descriptors(cmd_buffer, bind_point);
2203 }
2204
2205 static void
2206 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2207 VkShaderStageFlags stages)
2208 {
2209 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2210 ? cmd_buffer->state.compute_pipeline
2211 : cmd_buffer->state.pipeline;
2212 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2213 VK_PIPELINE_BIND_POINT_COMPUTE :
2214 VK_PIPELINE_BIND_POINT_GRAPHICS;
2215 struct radv_descriptor_state *descriptors_state =
2216 radv_get_descriptors_state(cmd_buffer, bind_point);
2217 struct radv_pipeline_layout *layout = pipeline->layout;
2218 struct radv_shader_variant *shader, *prev_shader;
2219 bool need_push_constants = false;
2220 unsigned offset;
2221 void *ptr;
2222 uint64_t va;
2223
2224 stages &= cmd_buffer->push_constant_stages;
2225 if (!stages ||
2226 (!layout->push_constant_size && !layout->dynamic_offset_count))
2227 return;
2228
2229 radv_foreach_stage(stage, stages) {
2230 if (!pipeline->shaders[stage])
2231 continue;
2232
2233 need_push_constants |= pipeline->shaders[stage]->info.info.loads_push_constants;
2234 need_push_constants |= pipeline->shaders[stage]->info.info.loads_dynamic_offsets;
2235
2236 uint8_t base = pipeline->shaders[stage]->info.info.base_inline_push_consts;
2237 uint8_t count = pipeline->shaders[stage]->info.info.num_inline_push_consts;
2238
2239 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2240 AC_UD_INLINE_PUSH_CONSTANTS,
2241 count,
2242 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2243 }
2244
2245 if (need_push_constants) {
2246 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2247 16 * layout->dynamic_offset_count,
2248 256, &offset, &ptr))
2249 return;
2250
2251 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2252 memcpy((char*)ptr + layout->push_constant_size,
2253 descriptors_state->dynamic_buffers,
2254 16 * layout->dynamic_offset_count);
2255
2256 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2257 va += offset;
2258
2259 MAYBE_UNUSED unsigned cdw_max =
2260 radeon_check_space(cmd_buffer->device->ws,
2261 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2262
2263 prev_shader = NULL;
2264 radv_foreach_stage(stage, stages) {
2265 shader = radv_get_shader(pipeline, stage);
2266
2267 /* Avoid redundantly emitting the address for merged stages. */
2268 if (shader && shader != prev_shader) {
2269 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2270 AC_UD_PUSH_CONSTANTS, va);
2271
2272 prev_shader = shader;
2273 }
2274 }
2275 assert(cmd_buffer->cs->cdw <= cdw_max);
2276 }
2277
2278 cmd_buffer->push_constant_stages &= ~stages;
2279 }
2280
2281 static void
2282 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2283 bool pipeline_is_dirty)
2284 {
2285 if ((pipeline_is_dirty ||
2286 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2287 cmd_buffer->state.pipeline->num_vertex_bindings &&
2288 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
2289 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
2290 unsigned vb_offset;
2291 void *vb_ptr;
2292 uint32_t i = 0;
2293 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2294 uint64_t va;
2295
2296 /* allocate some descriptor state for vertex buffers */
2297 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2298 &vb_offset, &vb_ptr))
2299 return;
2300
2301 for (i = 0; i < count; i++) {
2302 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2303 uint32_t offset;
2304 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2305 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2306
2307 if (!buffer)
2308 continue;
2309
2310 va = radv_buffer_get_va(buffer->bo);
2311
2312 offset = cmd_buffer->vertex_bindings[i].offset;
2313 va += offset + buffer->offset;
2314 desc[0] = va;
2315 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2316 if (cmd_buffer->device->physical_device->rad_info.chip_class <= GFX7 && stride)
2317 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
2318 else
2319 desc[2] = buffer->size - offset;
2320 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2321 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2322 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2323 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2324
2325 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2326 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
2327 S_008F0C_OOB_SELECT(1) |
2328 S_008F0C_RESOURCE_LEVEL(1);
2329 } else {
2330 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2331 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2332 }
2333 }
2334
2335 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2336 va += vb_offset;
2337
2338 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2339 AC_UD_VS_VERTEX_BUFFERS, va);
2340
2341 cmd_buffer->state.vb_va = va;
2342 cmd_buffer->state.vb_size = count * 16;
2343 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2344 }
2345 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2346 }
2347
2348 static void
2349 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2350 {
2351 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2352 struct radv_userdata_info *loc;
2353 uint32_t base_reg;
2354
2355 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2356 if (!radv_get_shader(pipeline, stage))
2357 continue;
2358
2359 loc = radv_lookup_user_sgpr(pipeline, stage,
2360 AC_UD_STREAMOUT_BUFFERS);
2361 if (loc->sgpr_idx == -1)
2362 continue;
2363
2364 base_reg = pipeline->user_data_0[stage];
2365
2366 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2367 base_reg + loc->sgpr_idx * 4, va, false);
2368 }
2369
2370 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
2371 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2372 if (loc->sgpr_idx != -1) {
2373 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2374
2375 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2376 base_reg + loc->sgpr_idx * 4, va, false);
2377 }
2378 }
2379 }
2380
2381 static void
2382 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2383 {
2384 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2385 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2386 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2387 unsigned so_offset;
2388 void *so_ptr;
2389 uint64_t va;
2390
2391 /* Allocate some descriptor state for streamout buffers. */
2392 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2393 MAX_SO_BUFFERS * 16, 256,
2394 &so_offset, &so_ptr))
2395 return;
2396
2397 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2398 struct radv_buffer *buffer = sb[i].buffer;
2399 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2400
2401 if (!(so->enabled_mask & (1 << i)))
2402 continue;
2403
2404 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2405
2406 va += sb[i].offset;
2407
2408 /* Set the descriptor.
2409 *
2410 * On GFX8, the format must be non-INVALID, otherwise
2411 * the buffer will be considered not bound and store
2412 * instructions will be no-ops.
2413 */
2414 desc[0] = va;
2415 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2416 desc[2] = 0xffffffff;
2417 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2418 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2419 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2420 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2421 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2422 }
2423
2424 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2425 va += so_offset;
2426
2427 radv_emit_streamout_buffers(cmd_buffer, va);
2428 }
2429
2430 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2431 }
2432
2433 static void
2434 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2435 {
2436 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2437 radv_flush_streamout_descriptors(cmd_buffer);
2438 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2439 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2440 }
2441
2442 struct radv_draw_info {
2443 /**
2444 * Number of vertices.
2445 */
2446 uint32_t count;
2447
2448 /**
2449 * Index of the first vertex.
2450 */
2451 int32_t vertex_offset;
2452
2453 /**
2454 * First instance id.
2455 */
2456 uint32_t first_instance;
2457
2458 /**
2459 * Number of instances.
2460 */
2461 uint32_t instance_count;
2462
2463 /**
2464 * First index (indexed draws only).
2465 */
2466 uint32_t first_index;
2467
2468 /**
2469 * Whether it's an indexed draw.
2470 */
2471 bool indexed;
2472
2473 /**
2474 * Indirect draw parameters resource.
2475 */
2476 struct radv_buffer *indirect;
2477 uint64_t indirect_offset;
2478 uint32_t stride;
2479
2480 /**
2481 * Draw count parameters resource.
2482 */
2483 struct radv_buffer *count_buffer;
2484 uint64_t count_buffer_offset;
2485
2486 /**
2487 * Stream output parameters resource.
2488 */
2489 struct radv_buffer *strmout_buffer;
2490 uint64_t strmout_buffer_offset;
2491 };
2492
2493 static void
2494 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
2495 bool instanced_draw, bool indirect_draw,
2496 bool count_from_stream_output,
2497 uint32_t draw_vertex_count)
2498 {
2499 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2500 struct radv_cmd_state *state = &cmd_buffer->state;
2501 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2502 unsigned ia_multi_vgt_param;
2503
2504 ia_multi_vgt_param =
2505 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2506 indirect_draw,
2507 count_from_stream_output,
2508 draw_vertex_count);
2509
2510 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2511 if (info->chip_class >= GFX9) {
2512 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2513 cs,
2514 R_030960_IA_MULTI_VGT_PARAM,
2515 4, ia_multi_vgt_param);
2516 } else if (info->chip_class >= GFX7) {
2517 radeon_set_context_reg_idx(cs,
2518 R_028AA8_IA_MULTI_VGT_PARAM,
2519 1, ia_multi_vgt_param);
2520 } else {
2521 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2522 ia_multi_vgt_param);
2523 }
2524 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2525 }
2526 }
2527
2528 static void
2529 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2530 const struct radv_draw_info *draw_info)
2531 {
2532 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2533 struct radv_cmd_state *state = &cmd_buffer->state;
2534 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2535 int32_t primitive_reset_en;
2536
2537 /* Draw state. */
2538 if (info->chip_class < GFX10) {
2539 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2540 draw_info->indirect,
2541 !!draw_info->strmout_buffer,
2542 draw_info->indirect ? 0 : draw_info->count);
2543 }
2544
2545 /* Primitive restart. */
2546 primitive_reset_en =
2547 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2548
2549 if (primitive_reset_en != state->last_primitive_reset_en) {
2550 state->last_primitive_reset_en = primitive_reset_en;
2551 if (info->chip_class >= GFX9) {
2552 radeon_set_uconfig_reg(cs,
2553 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2554 primitive_reset_en);
2555 } else {
2556 radeon_set_context_reg(cs,
2557 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2558 primitive_reset_en);
2559 }
2560 }
2561
2562 if (primitive_reset_en) {
2563 uint32_t primitive_reset_index =
2564 state->index_type ? 0xffffffffu : 0xffffu;
2565
2566 if (primitive_reset_index != state->last_primitive_reset_index) {
2567 radeon_set_context_reg(cs,
2568 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2569 primitive_reset_index);
2570 state->last_primitive_reset_index = primitive_reset_index;
2571 }
2572 }
2573
2574 if (draw_info->strmout_buffer) {
2575 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2576
2577 va += draw_info->strmout_buffer->offset +
2578 draw_info->strmout_buffer_offset;
2579
2580 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2581 draw_info->stride);
2582
2583 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2584 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2585 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2586 COPY_DATA_WR_CONFIRM);
2587 radeon_emit(cs, va);
2588 radeon_emit(cs, va >> 32);
2589 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2590 radeon_emit(cs, 0); /* unused */
2591
2592 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2593 }
2594 }
2595
2596 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2597 VkPipelineStageFlags src_stage_mask)
2598 {
2599 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2600 VK_PIPELINE_STAGE_TRANSFER_BIT |
2601 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2602 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2603 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2604 }
2605
2606 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2607 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2608 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2609 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2610 VK_PIPELINE_STAGE_TRANSFER_BIT |
2611 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2612 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2613 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2614 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2615 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2616 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2617 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2618 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2619 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2620 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2621 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2622 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2623 }
2624 }
2625
2626 static enum radv_cmd_flush_bits
2627 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2628 VkAccessFlags src_flags,
2629 struct radv_image *image)
2630 {
2631 bool flush_CB_meta = true, flush_DB_meta = true;
2632 enum radv_cmd_flush_bits flush_bits = 0;
2633 uint32_t b;
2634
2635 if (image) {
2636 if (!radv_image_has_CB_metadata(image))
2637 flush_CB_meta = false;
2638 if (!radv_image_has_htile(image))
2639 flush_DB_meta = false;
2640 }
2641
2642 for_each_bit(b, src_flags) {
2643 switch ((VkAccessFlagBits)(1 << b)) {
2644 case VK_ACCESS_SHADER_WRITE_BIT:
2645 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2646 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2647 flush_bits |= RADV_CMD_FLAG_WB_L2;
2648 break;
2649 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2650 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2651 if (flush_CB_meta)
2652 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2653 break;
2654 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2655 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2656 if (flush_DB_meta)
2657 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2658 break;
2659 case VK_ACCESS_TRANSFER_WRITE_BIT:
2660 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2661 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2662 RADV_CMD_FLAG_INV_L2;
2663
2664 if (flush_CB_meta)
2665 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2666 if (flush_DB_meta)
2667 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2668 break;
2669 default:
2670 break;
2671 }
2672 }
2673 return flush_bits;
2674 }
2675
2676 static enum radv_cmd_flush_bits
2677 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2678 VkAccessFlags dst_flags,
2679 struct radv_image *image)
2680 {
2681 bool flush_CB_meta = true, flush_DB_meta = true;
2682 enum radv_cmd_flush_bits flush_bits = 0;
2683 bool flush_CB = true, flush_DB = true;
2684 bool image_is_coherent = false;
2685 uint32_t b;
2686
2687 if (image) {
2688 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2689 flush_CB = false;
2690 flush_DB = false;
2691 }
2692
2693 if (!radv_image_has_CB_metadata(image))
2694 flush_CB_meta = false;
2695 if (!radv_image_has_htile(image))
2696 flush_DB_meta = false;
2697
2698 /* TODO: implement shader coherent for GFX10 */
2699
2700 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
2701 if (image->info.samples == 1 &&
2702 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2703 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2704 !vk_format_is_stencil(image->vk_format)) {
2705 /* Single-sample color and single-sample depth
2706 * (not stencil) are coherent with shaders on
2707 * GFX9.
2708 */
2709 image_is_coherent = true;
2710 }
2711 }
2712 }
2713
2714 for_each_bit(b, dst_flags) {
2715 switch ((VkAccessFlagBits)(1 << b)) {
2716 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2717 case VK_ACCESS_INDEX_READ_BIT:
2718 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2719 break;
2720 case VK_ACCESS_UNIFORM_READ_BIT:
2721 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
2722 break;
2723 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2724 case VK_ACCESS_TRANSFER_READ_BIT:
2725 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2726 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
2727 RADV_CMD_FLAG_INV_L2;
2728 break;
2729 case VK_ACCESS_SHADER_READ_BIT:
2730 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
2731
2732 if (!image_is_coherent)
2733 flush_bits |= RADV_CMD_FLAG_INV_L2;
2734 break;
2735 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2736 if (flush_CB)
2737 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2738 if (flush_CB_meta)
2739 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2740 break;
2741 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2742 if (flush_DB)
2743 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2744 if (flush_DB_meta)
2745 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2746 break;
2747 default:
2748 break;
2749 }
2750 }
2751 return flush_bits;
2752 }
2753
2754 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2755 const struct radv_subpass_barrier *barrier)
2756 {
2757 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2758 NULL);
2759 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2760 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2761 NULL);
2762 }
2763
2764 uint32_t
2765 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
2766 {
2767 struct radv_cmd_state *state = &cmd_buffer->state;
2768 uint32_t subpass_id = state->subpass - state->pass->subpasses;
2769
2770 /* The id of this subpass shouldn't exceed the number of subpasses in
2771 * this render pass minus 1.
2772 */
2773 assert(subpass_id < state->pass->subpass_count);
2774 return subpass_id;
2775 }
2776
2777 static struct radv_sample_locations_state *
2778 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2779 uint32_t att_idx,
2780 bool begin_subpass)
2781 {
2782 struct radv_cmd_state *state = &cmd_buffer->state;
2783 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
2784 struct radv_image_view *view = state->framebuffer->attachments[att_idx].attachment;
2785
2786 if (view->image->info.samples == 1)
2787 return NULL;
2788
2789 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
2790 /* Return the initial sample locations if this is the initial
2791 * layout transition of the given subpass attachemnt.
2792 */
2793 if (state->attachments[att_idx].sample_location.count > 0)
2794 return &state->attachments[att_idx].sample_location;
2795 } else {
2796 /* Otherwise return the subpass sample locations if defined. */
2797 if (state->subpass_sample_locs) {
2798 /* Because the driver sets the current subpass before
2799 * initial layout transitions, we should use the sample
2800 * locations from the previous subpass to avoid an
2801 * off-by-one problem. Otherwise, use the sample
2802 * locations for the current subpass for final layout
2803 * transitions.
2804 */
2805 if (begin_subpass)
2806 subpass_id--;
2807
2808 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
2809 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
2810 return &state->subpass_sample_locs[i].sample_location;
2811 }
2812 }
2813 }
2814
2815 return NULL;
2816 }
2817
2818 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2819 struct radv_subpass_attachment att,
2820 bool begin_subpass)
2821 {
2822 unsigned idx = att.attachment;
2823 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2824 struct radv_sample_locations_state *sample_locs;
2825 VkImageSubresourceRange range;
2826 range.aspectMask = 0;
2827 range.baseMipLevel = view->base_mip;
2828 range.levelCount = 1;
2829 range.baseArrayLayer = view->base_layer;
2830 range.layerCount = cmd_buffer->state.framebuffer->layers;
2831
2832 if (cmd_buffer->state.subpass->view_mask) {
2833 /* If the current subpass uses multiview, the driver might have
2834 * performed a fast color/depth clear to the whole image
2835 * (including all layers). To make sure the driver will
2836 * decompress the image correctly (if needed), we have to
2837 * account for the "real" number of layers. If the view mask is
2838 * sparse, this will decompress more layers than needed.
2839 */
2840 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
2841 }
2842
2843 /* Get the subpass sample locations for the given attachment, if NULL
2844 * is returned the driver will use the default HW locations.
2845 */
2846 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
2847 begin_subpass);
2848
2849 radv_handle_image_transition(cmd_buffer,
2850 view->image,
2851 cmd_buffer->state.attachments[idx].current_layout,
2852 att.layout, 0, 0, &range, sample_locs);
2853
2854 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2855
2856
2857 }
2858
2859 void
2860 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2861 const struct radv_subpass *subpass)
2862 {
2863 cmd_buffer->state.subpass = subpass;
2864
2865 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2866 }
2867
2868 static VkResult
2869 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2870 struct radv_render_pass *pass,
2871 const VkRenderPassBeginInfo *info)
2872 {
2873 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
2874 vk_find_struct_const(info->pNext,
2875 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
2876 struct radv_cmd_state *state = &cmd_buffer->state;
2877 struct radv_framebuffer *framebuffer = state->framebuffer;
2878
2879 if (!sample_locs) {
2880 state->subpass_sample_locs = NULL;
2881 return VK_SUCCESS;
2882 }
2883
2884 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
2885 const VkAttachmentSampleLocationsEXT *att_sample_locs =
2886 &sample_locs->pAttachmentInitialSampleLocations[i];
2887 uint32_t att_idx = att_sample_locs->attachmentIndex;
2888 struct radv_attachment_info *att = &framebuffer->attachments[att_idx];
2889 struct radv_image *image = att->attachment->image;
2890
2891 assert(vk_format_is_depth_or_stencil(image->vk_format));
2892
2893 /* From the Vulkan spec 1.1.108:
2894 *
2895 * "If the image referenced by the framebuffer attachment at
2896 * index attachmentIndex was not created with
2897 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
2898 * then the values specified in sampleLocationsInfo are
2899 * ignored."
2900 */
2901 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
2902 continue;
2903
2904 const VkSampleLocationsInfoEXT *sample_locs_info =
2905 &att_sample_locs->sampleLocationsInfo;
2906
2907 state->attachments[att_idx].sample_location.per_pixel =
2908 sample_locs_info->sampleLocationsPerPixel;
2909 state->attachments[att_idx].sample_location.grid_size =
2910 sample_locs_info->sampleLocationGridSize;
2911 state->attachments[att_idx].sample_location.count =
2912 sample_locs_info->sampleLocationsCount;
2913 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
2914 sample_locs_info->pSampleLocations,
2915 sample_locs_info->sampleLocationsCount);
2916 }
2917
2918 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
2919 sample_locs->postSubpassSampleLocationsCount *
2920 sizeof(state->subpass_sample_locs[0]),
2921 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2922 if (state->subpass_sample_locs == NULL) {
2923 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2924 return cmd_buffer->record_result;
2925 }
2926
2927 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
2928
2929 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
2930 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
2931 &sample_locs->pPostSubpassSampleLocations[i];
2932 const VkSampleLocationsInfoEXT *sample_locs_info =
2933 &subpass_sample_locs_info->sampleLocationsInfo;
2934
2935 state->subpass_sample_locs[i].subpass_idx =
2936 subpass_sample_locs_info->subpassIndex;
2937 state->subpass_sample_locs[i].sample_location.per_pixel =
2938 sample_locs_info->sampleLocationsPerPixel;
2939 state->subpass_sample_locs[i].sample_location.grid_size =
2940 sample_locs_info->sampleLocationGridSize;
2941 state->subpass_sample_locs[i].sample_location.count =
2942 sample_locs_info->sampleLocationsCount;
2943 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
2944 sample_locs_info->pSampleLocations,
2945 sample_locs_info->sampleLocationsCount);
2946 }
2947
2948 return VK_SUCCESS;
2949 }
2950
2951 static VkResult
2952 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2953 struct radv_render_pass *pass,
2954 const VkRenderPassBeginInfo *info)
2955 {
2956 struct radv_cmd_state *state = &cmd_buffer->state;
2957
2958 if (pass->attachment_count == 0) {
2959 state->attachments = NULL;
2960 return VK_SUCCESS;
2961 }
2962
2963 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2964 pass->attachment_count *
2965 sizeof(state->attachments[0]),
2966 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2967 if (state->attachments == NULL) {
2968 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2969 return cmd_buffer->record_result;
2970 }
2971
2972 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2973 struct radv_render_pass_attachment *att = &pass->attachments[i];
2974 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2975 VkImageAspectFlags clear_aspects = 0;
2976
2977 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2978 /* color attachment */
2979 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2980 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2981 }
2982 } else {
2983 /* depthstencil attachment */
2984 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2985 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2986 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2987 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2988 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2989 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2990 }
2991 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2992 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2993 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2994 }
2995 }
2996
2997 state->attachments[i].pending_clear_aspects = clear_aspects;
2998 state->attachments[i].cleared_views = 0;
2999 if (clear_aspects && info) {
3000 assert(info->clearValueCount > i);
3001 state->attachments[i].clear_value = info->pClearValues[i];
3002 }
3003
3004 state->attachments[i].current_layout = att->initial_layout;
3005 state->attachments[i].sample_location.count = 0;
3006 }
3007
3008 return VK_SUCCESS;
3009 }
3010
3011 VkResult radv_AllocateCommandBuffers(
3012 VkDevice _device,
3013 const VkCommandBufferAllocateInfo *pAllocateInfo,
3014 VkCommandBuffer *pCommandBuffers)
3015 {
3016 RADV_FROM_HANDLE(radv_device, device, _device);
3017 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
3018
3019 VkResult result = VK_SUCCESS;
3020 uint32_t i;
3021
3022 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
3023
3024 if (!list_empty(&pool->free_cmd_buffers)) {
3025 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
3026
3027 list_del(&cmd_buffer->pool_link);
3028 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
3029
3030 result = radv_reset_cmd_buffer(cmd_buffer);
3031 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
3032 cmd_buffer->level = pAllocateInfo->level;
3033
3034 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
3035 } else {
3036 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
3037 &pCommandBuffers[i]);
3038 }
3039 if (result != VK_SUCCESS)
3040 break;
3041 }
3042
3043 if (result != VK_SUCCESS) {
3044 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
3045 i, pCommandBuffers);
3046
3047 /* From the Vulkan 1.0.66 spec:
3048 *
3049 * "vkAllocateCommandBuffers can be used to create multiple
3050 * command buffers. If the creation of any of those command
3051 * buffers fails, the implementation must destroy all
3052 * successfully created command buffer objects from this
3053 * command, set all entries of the pCommandBuffers array to
3054 * NULL and return the error."
3055 */
3056 memset(pCommandBuffers, 0,
3057 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
3058 }
3059
3060 return result;
3061 }
3062
3063 void radv_FreeCommandBuffers(
3064 VkDevice device,
3065 VkCommandPool commandPool,
3066 uint32_t commandBufferCount,
3067 const VkCommandBuffer *pCommandBuffers)
3068 {
3069 for (uint32_t i = 0; i < commandBufferCount; i++) {
3070 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
3071
3072 if (cmd_buffer) {
3073 if (cmd_buffer->pool) {
3074 list_del(&cmd_buffer->pool_link);
3075 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3076 } else
3077 radv_cmd_buffer_destroy(cmd_buffer);
3078
3079 }
3080 }
3081 }
3082
3083 VkResult radv_ResetCommandBuffer(
3084 VkCommandBuffer commandBuffer,
3085 VkCommandBufferResetFlags flags)
3086 {
3087 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3088 return radv_reset_cmd_buffer(cmd_buffer);
3089 }
3090
3091 VkResult radv_BeginCommandBuffer(
3092 VkCommandBuffer commandBuffer,
3093 const VkCommandBufferBeginInfo *pBeginInfo)
3094 {
3095 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3096 VkResult result = VK_SUCCESS;
3097
3098 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3099 /* If the command buffer has already been resetted with
3100 * vkResetCommandBuffer, no need to do it again.
3101 */
3102 result = radv_reset_cmd_buffer(cmd_buffer);
3103 if (result != VK_SUCCESS)
3104 return result;
3105 }
3106
3107 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3108 cmd_buffer->state.last_primitive_reset_en = -1;
3109 cmd_buffer->state.last_index_type = -1;
3110 cmd_buffer->state.last_num_instances = -1;
3111 cmd_buffer->state.last_vertex_offset = -1;
3112 cmd_buffer->state.last_first_instance = -1;
3113 cmd_buffer->state.predication_type = -1;
3114 cmd_buffer->usage_flags = pBeginInfo->flags;
3115
3116 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3117 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3118 assert(pBeginInfo->pInheritanceInfo);
3119 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3120 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3121
3122 struct radv_subpass *subpass =
3123 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3124
3125 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3126 if (result != VK_SUCCESS)
3127 return result;
3128
3129 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3130 }
3131
3132 if (unlikely(cmd_buffer->device->trace_bo)) {
3133 struct radv_device *device = cmd_buffer->device;
3134
3135 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
3136 device->trace_bo);
3137
3138 radv_cmd_buffer_trace_emit(cmd_buffer);
3139 }
3140
3141 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3142
3143 return result;
3144 }
3145
3146 void radv_CmdBindVertexBuffers(
3147 VkCommandBuffer commandBuffer,
3148 uint32_t firstBinding,
3149 uint32_t bindingCount,
3150 const VkBuffer* pBuffers,
3151 const VkDeviceSize* pOffsets)
3152 {
3153 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3154 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3155 bool changed = false;
3156
3157 /* We have to defer setting up vertex buffer since we need the buffer
3158 * stride from the pipeline. */
3159
3160 assert(firstBinding + bindingCount <= MAX_VBS);
3161 for (uint32_t i = 0; i < bindingCount; i++) {
3162 uint32_t idx = firstBinding + i;
3163
3164 if (!changed &&
3165 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
3166 vb[idx].offset != pOffsets[i])) {
3167 changed = true;
3168 }
3169
3170 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
3171 vb[idx].offset = pOffsets[i];
3172
3173 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3174 vb[idx].buffer->bo);
3175 }
3176
3177 if (!changed) {
3178 /* No state changes. */
3179 return;
3180 }
3181
3182 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3183 }
3184
3185 void radv_CmdBindIndexBuffer(
3186 VkCommandBuffer commandBuffer,
3187 VkBuffer buffer,
3188 VkDeviceSize offset,
3189 VkIndexType indexType)
3190 {
3191 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3192 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3193
3194 if (cmd_buffer->state.index_buffer == index_buffer &&
3195 cmd_buffer->state.index_offset == offset &&
3196 cmd_buffer->state.index_type == indexType) {
3197 /* No state changes. */
3198 return;
3199 }
3200
3201 cmd_buffer->state.index_buffer = index_buffer;
3202 cmd_buffer->state.index_offset = offset;
3203 cmd_buffer->state.index_type = indexType; /* vk matches hw */
3204 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3205 cmd_buffer->state.index_va += index_buffer->offset + offset;
3206
3207 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
3208 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
3209 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3210 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3211 }
3212
3213
3214 static void
3215 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3216 VkPipelineBindPoint bind_point,
3217 struct radv_descriptor_set *set, unsigned idx)
3218 {
3219 struct radeon_winsys *ws = cmd_buffer->device->ws;
3220
3221 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3222
3223 assert(set);
3224 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3225
3226 if (!cmd_buffer->device->use_global_bo_list) {
3227 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3228 if (set->descriptors[j])
3229 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3230 }
3231
3232 if(set->bo)
3233 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3234 }
3235
3236 void radv_CmdBindDescriptorSets(
3237 VkCommandBuffer commandBuffer,
3238 VkPipelineBindPoint pipelineBindPoint,
3239 VkPipelineLayout _layout,
3240 uint32_t firstSet,
3241 uint32_t descriptorSetCount,
3242 const VkDescriptorSet* pDescriptorSets,
3243 uint32_t dynamicOffsetCount,
3244 const uint32_t* pDynamicOffsets)
3245 {
3246 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3247 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3248 unsigned dyn_idx = 0;
3249
3250 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3251 struct radv_descriptor_state *descriptors_state =
3252 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3253
3254 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3255 unsigned idx = i + firstSet;
3256 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3257 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3258
3259 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3260 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3261 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3262 assert(dyn_idx < dynamicOffsetCount);
3263
3264 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3265 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3266 dst[0] = va;
3267 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3268 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3269 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3270 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3271 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3272 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3273
3274 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
3275 dst[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3276 S_008F0C_OOB_SELECT(3) |
3277 S_008F0C_RESOURCE_LEVEL(1);
3278 } else {
3279 dst[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3280 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3281 }
3282
3283 cmd_buffer->push_constant_stages |=
3284 set->layout->dynamic_shader_stages;
3285 }
3286 }
3287 }
3288
3289 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3290 struct radv_descriptor_set *set,
3291 struct radv_descriptor_set_layout *layout,
3292 VkPipelineBindPoint bind_point)
3293 {
3294 struct radv_descriptor_state *descriptors_state =
3295 radv_get_descriptors_state(cmd_buffer, bind_point);
3296 set->size = layout->size;
3297 set->layout = layout;
3298
3299 if (descriptors_state->push_set.capacity < set->size) {
3300 size_t new_size = MAX2(set->size, 1024);
3301 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3302 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3303
3304 free(set->mapped_ptr);
3305 set->mapped_ptr = malloc(new_size);
3306
3307 if (!set->mapped_ptr) {
3308 descriptors_state->push_set.capacity = 0;
3309 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3310 return false;
3311 }
3312
3313 descriptors_state->push_set.capacity = new_size;
3314 }
3315
3316 return true;
3317 }
3318
3319 void radv_meta_push_descriptor_set(
3320 struct radv_cmd_buffer* cmd_buffer,
3321 VkPipelineBindPoint pipelineBindPoint,
3322 VkPipelineLayout _layout,
3323 uint32_t set,
3324 uint32_t descriptorWriteCount,
3325 const VkWriteDescriptorSet* pDescriptorWrites)
3326 {
3327 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3328 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3329 unsigned bo_offset;
3330
3331 assert(set == 0);
3332 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3333
3334 push_set->size = layout->set[set].layout->size;
3335 push_set->layout = layout->set[set].layout;
3336
3337 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3338 &bo_offset,
3339 (void**) &push_set->mapped_ptr))
3340 return;
3341
3342 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3343 push_set->va += bo_offset;
3344
3345 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3346 radv_descriptor_set_to_handle(push_set),
3347 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3348
3349 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3350 }
3351
3352 void radv_CmdPushDescriptorSetKHR(
3353 VkCommandBuffer commandBuffer,
3354 VkPipelineBindPoint pipelineBindPoint,
3355 VkPipelineLayout _layout,
3356 uint32_t set,
3357 uint32_t descriptorWriteCount,
3358 const VkWriteDescriptorSet* pDescriptorWrites)
3359 {
3360 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3361 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3362 struct radv_descriptor_state *descriptors_state =
3363 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3364 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3365
3366 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3367
3368 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3369 layout->set[set].layout,
3370 pipelineBindPoint))
3371 return;
3372
3373 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3374 * because it is invalid, according to Vulkan spec.
3375 */
3376 for (int i = 0; i < descriptorWriteCount; i++) {
3377 MAYBE_UNUSED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
3378 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
3379 }
3380
3381 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3382 radv_descriptor_set_to_handle(push_set),
3383 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3384
3385 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3386 descriptors_state->push_dirty = true;
3387 }
3388
3389 void radv_CmdPushDescriptorSetWithTemplateKHR(
3390 VkCommandBuffer commandBuffer,
3391 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
3392 VkPipelineLayout _layout,
3393 uint32_t set,
3394 const void* pData)
3395 {
3396 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3397 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3398 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
3399 struct radv_descriptor_state *descriptors_state =
3400 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
3401 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3402
3403 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3404
3405 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3406 layout->set[set].layout,
3407 templ->bind_point))
3408 return;
3409
3410 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
3411 descriptorUpdateTemplate, pData);
3412
3413 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
3414 descriptors_state->push_dirty = true;
3415 }
3416
3417 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
3418 VkPipelineLayout layout,
3419 VkShaderStageFlags stageFlags,
3420 uint32_t offset,
3421 uint32_t size,
3422 const void* pValues)
3423 {
3424 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3425 memcpy(cmd_buffer->push_constants + offset, pValues, size);
3426 cmd_buffer->push_constant_stages |= stageFlags;
3427 }
3428
3429 VkResult radv_EndCommandBuffer(
3430 VkCommandBuffer commandBuffer)
3431 {
3432 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3433
3434 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
3435 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
3436 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
3437
3438 /* Make sure to sync all pending active queries at the end of
3439 * command buffer.
3440 */
3441 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
3442
3443 si_emit_cache_flush(cmd_buffer);
3444 }
3445
3446 /* Make sure CP DMA is idle at the end of IBs because the kernel
3447 * doesn't wait for it.
3448 */
3449 si_cp_dma_wait_for_idle(cmd_buffer);
3450
3451 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3452 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
3453
3454 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
3455 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3456
3457 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
3458
3459 return cmd_buffer->record_result;
3460 }
3461
3462 static void
3463 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
3464 {
3465 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3466
3467 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
3468 return;
3469
3470 assert(!pipeline->ctx_cs.cdw);
3471
3472 cmd_buffer->state.emitted_compute_pipeline = pipeline;
3473
3474 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
3475 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
3476
3477 cmd_buffer->compute_scratch_size_needed =
3478 MAX2(cmd_buffer->compute_scratch_size_needed,
3479 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
3480
3481 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3482 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
3483
3484 if (unlikely(cmd_buffer->device->trace_bo))
3485 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
3486 }
3487
3488 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
3489 VkPipelineBindPoint bind_point)
3490 {
3491 struct radv_descriptor_state *descriptors_state =
3492 radv_get_descriptors_state(cmd_buffer, bind_point);
3493
3494 descriptors_state->dirty |= descriptors_state->valid;
3495 }
3496
3497 void radv_CmdBindPipeline(
3498 VkCommandBuffer commandBuffer,
3499 VkPipelineBindPoint pipelineBindPoint,
3500 VkPipeline _pipeline)
3501 {
3502 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3503 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3504
3505 switch (pipelineBindPoint) {
3506 case VK_PIPELINE_BIND_POINT_COMPUTE:
3507 if (cmd_buffer->state.compute_pipeline == pipeline)
3508 return;
3509 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3510
3511 cmd_buffer->state.compute_pipeline = pipeline;
3512 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3513 break;
3514 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3515 if (cmd_buffer->state.pipeline == pipeline)
3516 return;
3517 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3518
3519 cmd_buffer->state.pipeline = pipeline;
3520 if (!pipeline)
3521 break;
3522
3523 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3524 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3525
3526 /* the new vertex shader might not have the same user regs */
3527 cmd_buffer->state.last_first_instance = -1;
3528 cmd_buffer->state.last_vertex_offset = -1;
3529
3530 /* Prefetch all pipeline shaders at first draw time. */
3531 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3532
3533 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3534 radv_bind_streamout_state(cmd_buffer, pipeline);
3535
3536 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3537 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3538 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3539 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3540
3541 if (radv_pipeline_has_tess(pipeline))
3542 cmd_buffer->tess_rings_needed = true;
3543 break;
3544 default:
3545 assert(!"invalid bind point");
3546 break;
3547 }
3548 }
3549
3550 void radv_CmdSetViewport(
3551 VkCommandBuffer commandBuffer,
3552 uint32_t firstViewport,
3553 uint32_t viewportCount,
3554 const VkViewport* pViewports)
3555 {
3556 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3557 struct radv_cmd_state *state = &cmd_buffer->state;
3558 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
3559
3560 assert(firstViewport < MAX_VIEWPORTS);
3561 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3562
3563 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3564 pViewports, viewportCount * sizeof(*pViewports))) {
3565 return;
3566 }
3567
3568 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3569 viewportCount * sizeof(*pViewports));
3570
3571 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3572 }
3573
3574 void radv_CmdSetScissor(
3575 VkCommandBuffer commandBuffer,
3576 uint32_t firstScissor,
3577 uint32_t scissorCount,
3578 const VkRect2D* pScissors)
3579 {
3580 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3581 struct radv_cmd_state *state = &cmd_buffer->state;
3582 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
3583
3584 assert(firstScissor < MAX_SCISSORS);
3585 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3586
3587 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3588 scissorCount * sizeof(*pScissors))) {
3589 return;
3590 }
3591
3592 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3593 scissorCount * sizeof(*pScissors));
3594
3595 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3596 }
3597
3598 void radv_CmdSetLineWidth(
3599 VkCommandBuffer commandBuffer,
3600 float lineWidth)
3601 {
3602 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3603
3604 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3605 return;
3606
3607 cmd_buffer->state.dynamic.line_width = lineWidth;
3608 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3609 }
3610
3611 void radv_CmdSetDepthBias(
3612 VkCommandBuffer commandBuffer,
3613 float depthBiasConstantFactor,
3614 float depthBiasClamp,
3615 float depthBiasSlopeFactor)
3616 {
3617 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3618 struct radv_cmd_state *state = &cmd_buffer->state;
3619
3620 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3621 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3622 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3623 return;
3624 }
3625
3626 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3627 state->dynamic.depth_bias.clamp = depthBiasClamp;
3628 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3629
3630 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3631 }
3632
3633 void radv_CmdSetBlendConstants(
3634 VkCommandBuffer commandBuffer,
3635 const float blendConstants[4])
3636 {
3637 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3638 struct radv_cmd_state *state = &cmd_buffer->state;
3639
3640 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3641 return;
3642
3643 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
3644
3645 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3646 }
3647
3648 void radv_CmdSetDepthBounds(
3649 VkCommandBuffer commandBuffer,
3650 float minDepthBounds,
3651 float maxDepthBounds)
3652 {
3653 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3654 struct radv_cmd_state *state = &cmd_buffer->state;
3655
3656 if (state->dynamic.depth_bounds.min == minDepthBounds &&
3657 state->dynamic.depth_bounds.max == maxDepthBounds) {
3658 return;
3659 }
3660
3661 state->dynamic.depth_bounds.min = minDepthBounds;
3662 state->dynamic.depth_bounds.max = maxDepthBounds;
3663
3664 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
3665 }
3666
3667 void radv_CmdSetStencilCompareMask(
3668 VkCommandBuffer commandBuffer,
3669 VkStencilFaceFlags faceMask,
3670 uint32_t compareMask)
3671 {
3672 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3673 struct radv_cmd_state *state = &cmd_buffer->state;
3674 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
3675 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
3676
3677 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3678 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3679 return;
3680 }
3681
3682 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3683 state->dynamic.stencil_compare_mask.front = compareMask;
3684 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3685 state->dynamic.stencil_compare_mask.back = compareMask;
3686
3687 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
3688 }
3689
3690 void radv_CmdSetStencilWriteMask(
3691 VkCommandBuffer commandBuffer,
3692 VkStencilFaceFlags faceMask,
3693 uint32_t writeMask)
3694 {
3695 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3696 struct radv_cmd_state *state = &cmd_buffer->state;
3697 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
3698 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
3699
3700 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3701 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3702 return;
3703 }
3704
3705 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3706 state->dynamic.stencil_write_mask.front = writeMask;
3707 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3708 state->dynamic.stencil_write_mask.back = writeMask;
3709
3710 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
3711 }
3712
3713 void radv_CmdSetStencilReference(
3714 VkCommandBuffer commandBuffer,
3715 VkStencilFaceFlags faceMask,
3716 uint32_t reference)
3717 {
3718 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3719 struct radv_cmd_state *state = &cmd_buffer->state;
3720 bool front_same = state->dynamic.stencil_reference.front == reference;
3721 bool back_same = state->dynamic.stencil_reference.back == reference;
3722
3723 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3724 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3725 return;
3726 }
3727
3728 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3729 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3730 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3731 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3732
3733 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3734 }
3735
3736 void radv_CmdSetDiscardRectangleEXT(
3737 VkCommandBuffer commandBuffer,
3738 uint32_t firstDiscardRectangle,
3739 uint32_t discardRectangleCount,
3740 const VkRect2D* pDiscardRectangles)
3741 {
3742 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3743 struct radv_cmd_state *state = &cmd_buffer->state;
3744 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3745
3746 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3747 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3748
3749 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
3750 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
3751 return;
3752 }
3753
3754 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3755 pDiscardRectangles, discardRectangleCount);
3756
3757 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3758 }
3759
3760 void radv_CmdSetSampleLocationsEXT(
3761 VkCommandBuffer commandBuffer,
3762 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
3763 {
3764 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3765 struct radv_cmd_state *state = &cmd_buffer->state;
3766
3767 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
3768
3769 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
3770 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
3771 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
3772 typed_memcpy(&state->dynamic.sample_location.locations[0],
3773 pSampleLocationsInfo->pSampleLocations,
3774 pSampleLocationsInfo->sampleLocationsCount);
3775
3776 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
3777 }
3778
3779 void radv_CmdExecuteCommands(
3780 VkCommandBuffer commandBuffer,
3781 uint32_t commandBufferCount,
3782 const VkCommandBuffer* pCmdBuffers)
3783 {
3784 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3785
3786 assert(commandBufferCount > 0);
3787
3788 /* Emit pending flushes on primary prior to executing secondary */
3789 si_emit_cache_flush(primary);
3790
3791 for (uint32_t i = 0; i < commandBufferCount; i++) {
3792 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3793
3794 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3795 secondary->scratch_size_needed);
3796 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3797 secondary->compute_scratch_size_needed);
3798
3799 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
3800 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
3801 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
3802 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
3803 if (secondary->tess_rings_needed)
3804 primary->tess_rings_needed = true;
3805 if (secondary->sample_positions_needed)
3806 primary->sample_positions_needed = true;
3807
3808 if (!secondary->state.framebuffer &&
3809 (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
3810 /* Emit the framebuffer state from primary if secondary
3811 * has been recorded without a framebuffer, otherwise
3812 * fast color/depth clears can't work.
3813 */
3814 radv_emit_framebuffer_state(primary);
3815 }
3816
3817 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
3818
3819
3820 /* When the secondary command buffer is compute only we don't
3821 * need to re-emit the current graphics pipeline.
3822 */
3823 if (secondary->state.emitted_pipeline) {
3824 primary->state.emitted_pipeline =
3825 secondary->state.emitted_pipeline;
3826 }
3827
3828 /* When the secondary command buffer is graphics only we don't
3829 * need to re-emit the current compute pipeline.
3830 */
3831 if (secondary->state.emitted_compute_pipeline) {
3832 primary->state.emitted_compute_pipeline =
3833 secondary->state.emitted_compute_pipeline;
3834 }
3835
3836 /* Only re-emit the draw packets when needed. */
3837 if (secondary->state.last_primitive_reset_en != -1) {
3838 primary->state.last_primitive_reset_en =
3839 secondary->state.last_primitive_reset_en;
3840 }
3841
3842 if (secondary->state.last_primitive_reset_index) {
3843 primary->state.last_primitive_reset_index =
3844 secondary->state.last_primitive_reset_index;
3845 }
3846
3847 if (secondary->state.last_ia_multi_vgt_param) {
3848 primary->state.last_ia_multi_vgt_param =
3849 secondary->state.last_ia_multi_vgt_param;
3850 }
3851
3852 primary->state.last_first_instance = secondary->state.last_first_instance;
3853 primary->state.last_num_instances = secondary->state.last_num_instances;
3854 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
3855
3856 if (secondary->state.last_index_type != -1) {
3857 primary->state.last_index_type =
3858 secondary->state.last_index_type;
3859 }
3860 }
3861
3862 /* After executing commands from secondary buffers we have to dirty
3863 * some states.
3864 */
3865 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
3866 RADV_CMD_DIRTY_INDEX_BUFFER |
3867 RADV_CMD_DIRTY_DYNAMIC_ALL;
3868 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
3869 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
3870 }
3871
3872 VkResult radv_CreateCommandPool(
3873 VkDevice _device,
3874 const VkCommandPoolCreateInfo* pCreateInfo,
3875 const VkAllocationCallbacks* pAllocator,
3876 VkCommandPool* pCmdPool)
3877 {
3878 RADV_FROM_HANDLE(radv_device, device, _device);
3879 struct radv_cmd_pool *pool;
3880
3881 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3882 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3883 if (pool == NULL)
3884 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3885
3886 if (pAllocator)
3887 pool->alloc = *pAllocator;
3888 else
3889 pool->alloc = device->alloc;
3890
3891 list_inithead(&pool->cmd_buffers);
3892 list_inithead(&pool->free_cmd_buffers);
3893
3894 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3895
3896 *pCmdPool = radv_cmd_pool_to_handle(pool);
3897
3898 return VK_SUCCESS;
3899
3900 }
3901
3902 void radv_DestroyCommandPool(
3903 VkDevice _device,
3904 VkCommandPool commandPool,
3905 const VkAllocationCallbacks* pAllocator)
3906 {
3907 RADV_FROM_HANDLE(radv_device, device, _device);
3908 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3909
3910 if (!pool)
3911 return;
3912
3913 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3914 &pool->cmd_buffers, pool_link) {
3915 radv_cmd_buffer_destroy(cmd_buffer);
3916 }
3917
3918 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3919 &pool->free_cmd_buffers, pool_link) {
3920 radv_cmd_buffer_destroy(cmd_buffer);
3921 }
3922
3923 vk_free2(&device->alloc, pAllocator, pool);
3924 }
3925
3926 VkResult radv_ResetCommandPool(
3927 VkDevice device,
3928 VkCommandPool commandPool,
3929 VkCommandPoolResetFlags flags)
3930 {
3931 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3932 VkResult result;
3933
3934 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3935 &pool->cmd_buffers, pool_link) {
3936 result = radv_reset_cmd_buffer(cmd_buffer);
3937 if (result != VK_SUCCESS)
3938 return result;
3939 }
3940
3941 return VK_SUCCESS;
3942 }
3943
3944 void radv_TrimCommandPool(
3945 VkDevice device,
3946 VkCommandPool commandPool,
3947 VkCommandPoolTrimFlags flags)
3948 {
3949 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3950
3951 if (!pool)
3952 return;
3953
3954 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3955 &pool->free_cmd_buffers, pool_link) {
3956 radv_cmd_buffer_destroy(cmd_buffer);
3957 }
3958 }
3959
3960 static void
3961 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
3962 uint32_t subpass_id)
3963 {
3964 struct radv_cmd_state *state = &cmd_buffer->state;
3965 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
3966
3967 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3968 cmd_buffer->cs, 4096);
3969
3970 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
3971
3972 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3973
3974 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
3975 const uint32_t a = subpass->attachments[i].attachment;
3976 if (a == VK_ATTACHMENT_UNUSED)
3977 continue;
3978
3979 radv_handle_subpass_image_transition(cmd_buffer,
3980 subpass->attachments[i],
3981 true);
3982 }
3983
3984 radv_cmd_buffer_clear_subpass(cmd_buffer);
3985
3986 assert(cmd_buffer->cs->cdw <= cdw_max);
3987 }
3988
3989 static void
3990 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
3991 {
3992 struct radv_cmd_state *state = &cmd_buffer->state;
3993 const struct radv_subpass *subpass = state->subpass;
3994 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
3995
3996 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3997
3998 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
3999 const uint32_t a = subpass->attachments[i].attachment;
4000 if (a == VK_ATTACHMENT_UNUSED)
4001 continue;
4002
4003 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
4004 continue;
4005
4006 VkImageLayout layout = state->pass->attachments[a].final_layout;
4007 struct radv_subpass_attachment att = { a, layout };
4008 radv_handle_subpass_image_transition(cmd_buffer, att, false);
4009 }
4010 }
4011
4012 void radv_CmdBeginRenderPass(
4013 VkCommandBuffer commandBuffer,
4014 const VkRenderPassBeginInfo* pRenderPassBegin,
4015 VkSubpassContents contents)
4016 {
4017 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4018 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
4019 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
4020 VkResult result;
4021
4022 cmd_buffer->state.framebuffer = framebuffer;
4023 cmd_buffer->state.pass = pass;
4024 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
4025
4026 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
4027 if (result != VK_SUCCESS)
4028 return;
4029
4030 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
4031 if (result != VK_SUCCESS)
4032 return;
4033
4034 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
4035 }
4036
4037 void radv_CmdBeginRenderPass2KHR(
4038 VkCommandBuffer commandBuffer,
4039 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
4040 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
4041 {
4042 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
4043 pSubpassBeginInfo->contents);
4044 }
4045
4046 void radv_CmdNextSubpass(
4047 VkCommandBuffer commandBuffer,
4048 VkSubpassContents contents)
4049 {
4050 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4051
4052 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
4053 radv_cmd_buffer_end_subpass(cmd_buffer);
4054 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
4055 }
4056
4057 void radv_CmdNextSubpass2KHR(
4058 VkCommandBuffer commandBuffer,
4059 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
4060 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4061 {
4062 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
4063 }
4064
4065 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
4066 {
4067 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
4068 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
4069 if (!radv_get_shader(pipeline, stage))
4070 continue;
4071
4072 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
4073 if (loc->sgpr_idx == -1)
4074 continue;
4075 uint32_t base_reg = pipeline->user_data_0[stage];
4076 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4077
4078 }
4079 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
4080 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
4081 if (loc->sgpr_idx != -1) {
4082 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
4083 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4084 }
4085 }
4086 }
4087
4088 static void
4089 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4090 uint32_t vertex_count,
4091 bool use_opaque)
4092 {
4093 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
4094 radeon_emit(cmd_buffer->cs, vertex_count);
4095 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
4096 S_0287F0_USE_OPAQUE(use_opaque));
4097 }
4098
4099 static void
4100 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
4101 uint64_t index_va,
4102 uint32_t index_count)
4103 {
4104 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
4105 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
4106 radeon_emit(cmd_buffer->cs, index_va);
4107 radeon_emit(cmd_buffer->cs, index_va >> 32);
4108 radeon_emit(cmd_buffer->cs, index_count);
4109 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
4110 }
4111
4112 static void
4113 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4114 bool indexed,
4115 uint32_t draw_count,
4116 uint64_t count_va,
4117 uint32_t stride)
4118 {
4119 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4120 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
4121 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
4122 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
4123 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
4124 bool predicating = cmd_buffer->state.predicating;
4125 assert(base_reg);
4126
4127 /* just reset draw state for vertex data */
4128 cmd_buffer->state.last_first_instance = -1;
4129 cmd_buffer->state.last_num_instances = -1;
4130 cmd_buffer->state.last_vertex_offset = -1;
4131
4132 if (draw_count == 1 && !count_va && !draw_id_enable) {
4133 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
4134 PKT3_DRAW_INDIRECT, 3, predicating));
4135 radeon_emit(cs, 0);
4136 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4137 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4138 radeon_emit(cs, di_src_sel);
4139 } else {
4140 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
4141 PKT3_DRAW_INDIRECT_MULTI,
4142 8, predicating));
4143 radeon_emit(cs, 0);
4144 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4145 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4146 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
4147 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
4148 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
4149 radeon_emit(cs, draw_count); /* count */
4150 radeon_emit(cs, count_va); /* count_addr */
4151 radeon_emit(cs, count_va >> 32);
4152 radeon_emit(cs, stride); /* stride */
4153 radeon_emit(cs, di_src_sel);
4154 }
4155 }
4156
4157 static void
4158 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
4159 const struct radv_draw_info *info)
4160 {
4161 struct radv_cmd_state *state = &cmd_buffer->state;
4162 struct radeon_winsys *ws = cmd_buffer->device->ws;
4163 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4164
4165 if (info->indirect) {
4166 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4167 uint64_t count_va = 0;
4168
4169 va += info->indirect->offset + info->indirect_offset;
4170
4171 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4172
4173 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
4174 radeon_emit(cs, 1);
4175 radeon_emit(cs, va);
4176 radeon_emit(cs, va >> 32);
4177
4178 if (info->count_buffer) {
4179 count_va = radv_buffer_get_va(info->count_buffer->bo);
4180 count_va += info->count_buffer->offset +
4181 info->count_buffer_offset;
4182
4183 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
4184 }
4185
4186 if (!state->subpass->view_mask) {
4187 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4188 info->indexed,
4189 info->count,
4190 count_va,
4191 info->stride);
4192 } else {
4193 unsigned i;
4194 for_each_bit(i, state->subpass->view_mask) {
4195 radv_emit_view_index(cmd_buffer, i);
4196
4197 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4198 info->indexed,
4199 info->count,
4200 count_va,
4201 info->stride);
4202 }
4203 }
4204 } else {
4205 assert(state->pipeline->graphics.vtx_base_sgpr);
4206
4207 if (info->vertex_offset != state->last_vertex_offset ||
4208 info->first_instance != state->last_first_instance) {
4209 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
4210 state->pipeline->graphics.vtx_emit_num);
4211
4212 radeon_emit(cs, info->vertex_offset);
4213 radeon_emit(cs, info->first_instance);
4214 if (state->pipeline->graphics.vtx_emit_num == 3)
4215 radeon_emit(cs, 0);
4216 state->last_first_instance = info->first_instance;
4217 state->last_vertex_offset = info->vertex_offset;
4218 }
4219
4220 if (state->last_num_instances != info->instance_count) {
4221 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
4222 radeon_emit(cs, info->instance_count);
4223 state->last_num_instances = info->instance_count;
4224 }
4225
4226 if (info->indexed) {
4227 int index_size = state->index_type ? 4 : 2;
4228 uint64_t index_va;
4229
4230 index_va = state->index_va;
4231 index_va += info->first_index * index_size;
4232
4233 if (!state->subpass->view_mask) {
4234 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4235 index_va,
4236 info->count);
4237 } else {
4238 unsigned i;
4239 for_each_bit(i, state->subpass->view_mask) {
4240 radv_emit_view_index(cmd_buffer, i);
4241
4242 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4243 index_va,
4244 info->count);
4245 }
4246 }
4247 } else {
4248 if (!state->subpass->view_mask) {
4249 radv_cs_emit_draw_packet(cmd_buffer,
4250 info->count,
4251 !!info->strmout_buffer);
4252 } else {
4253 unsigned i;
4254 for_each_bit(i, state->subpass->view_mask) {
4255 radv_emit_view_index(cmd_buffer, i);
4256
4257 radv_cs_emit_draw_packet(cmd_buffer,
4258 info->count,
4259 !!info->strmout_buffer);
4260 }
4261 }
4262 }
4263 }
4264 }
4265
4266 /*
4267 * Vega and raven have a bug which triggers if there are multiple context
4268 * register contexts active at the same time with different scissor values.
4269 *
4270 * There are two possible workarounds:
4271 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4272 * there is only ever 1 active set of scissor values at the same time.
4273 *
4274 * 2) Whenever the hardware switches contexts we have to set the scissor
4275 * registers again even if it is a noop. That way the new context gets
4276 * the correct scissor values.
4277 *
4278 * This implements option 2. radv_need_late_scissor_emission needs to
4279 * return true on affected HW if radv_emit_all_graphics_states sets
4280 * any context registers.
4281 */
4282 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
4283 const struct radv_draw_info *info)
4284 {
4285 struct radv_cmd_state *state = &cmd_buffer->state;
4286
4287 if (!cmd_buffer->device->physical_device->has_scissor_bug)
4288 return false;
4289
4290 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
4291 return true;
4292
4293 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
4294
4295 /* Index, vertex and streamout buffers don't change context regs, and
4296 * pipeline is already handled.
4297 */
4298 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
4299 RADV_CMD_DIRTY_VERTEX_BUFFER |
4300 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
4301 RADV_CMD_DIRTY_PIPELINE);
4302
4303 if (cmd_buffer->state.dirty & used_states)
4304 return true;
4305
4306 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
4307 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
4308 return true;
4309
4310 return false;
4311 }
4312
4313 static void
4314 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
4315 const struct radv_draw_info *info)
4316 {
4317 bool late_scissor_emission;
4318
4319 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
4320 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
4321 radv_emit_rbplus_state(cmd_buffer);
4322
4323 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
4324 radv_emit_graphics_pipeline(cmd_buffer);
4325
4326 /* This should be before the cmd_buffer->state.dirty is cleared
4327 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4328 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4329 late_scissor_emission =
4330 radv_need_late_scissor_emission(cmd_buffer, info);
4331
4332 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
4333 radv_emit_framebuffer_state(cmd_buffer);
4334
4335 if (info->indexed) {
4336 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
4337 radv_emit_index_buffer(cmd_buffer);
4338 } else {
4339 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4340 * so the state must be re-emitted before the next indexed
4341 * draw.
4342 */
4343 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
4344 cmd_buffer->state.last_index_type = -1;
4345 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
4346 }
4347 }
4348
4349 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
4350
4351 radv_emit_draw_registers(cmd_buffer, info);
4352
4353 if (late_scissor_emission)
4354 radv_emit_scissor(cmd_buffer);
4355 }
4356
4357 static void
4358 radv_draw(struct radv_cmd_buffer *cmd_buffer,
4359 const struct radv_draw_info *info)
4360 {
4361 struct radeon_info *rad_info =
4362 &cmd_buffer->device->physical_device->rad_info;
4363 bool has_prefetch =
4364 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4365 bool pipeline_is_dirty =
4366 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
4367 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
4368
4369 MAYBE_UNUSED unsigned cdw_max =
4370 radeon_check_space(cmd_buffer->device->ws,
4371 cmd_buffer->cs, 4096);
4372
4373 if (likely(!info->indirect)) {
4374 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4375 * no workaround for indirect draws, but we can at least skip
4376 * direct draws.
4377 */
4378 if (unlikely(!info->instance_count))
4379 return;
4380
4381 /* Handle count == 0. */
4382 if (unlikely(!info->count && !info->strmout_buffer))
4383 return;
4384 }
4385
4386 /* Use optimal packet order based on whether we need to sync the
4387 * pipeline.
4388 */
4389 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4390 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4391 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4392 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4393 /* If we have to wait for idle, set all states first, so that
4394 * all SET packets are processed in parallel with previous draw
4395 * calls. Then upload descriptors, set shader pointers, and
4396 * draw, and prefetch at the end. This ensures that the time
4397 * the CUs are idle is very short. (there are only SET_SH
4398 * packets between the wait and the draw)
4399 */
4400 radv_emit_all_graphics_states(cmd_buffer, info);
4401 si_emit_cache_flush(cmd_buffer);
4402 /* <-- CUs are idle here --> */
4403
4404 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4405
4406 radv_emit_draw_packets(cmd_buffer, info);
4407 /* <-- CUs are busy here --> */
4408
4409 /* Start prefetches after the draw has been started. Both will
4410 * run in parallel, but starting the draw first is more
4411 * important.
4412 */
4413 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4414 radv_emit_prefetch_L2(cmd_buffer,
4415 cmd_buffer->state.pipeline, false);
4416 }
4417 } else {
4418 /* If we don't wait for idle, start prefetches first, then set
4419 * states, and draw at the end.
4420 */
4421 si_emit_cache_flush(cmd_buffer);
4422
4423 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4424 /* Only prefetch the vertex shader and VBO descriptors
4425 * in order to start the draw as soon as possible.
4426 */
4427 radv_emit_prefetch_L2(cmd_buffer,
4428 cmd_buffer->state.pipeline, true);
4429 }
4430
4431 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4432
4433 radv_emit_all_graphics_states(cmd_buffer, info);
4434 radv_emit_draw_packets(cmd_buffer, info);
4435
4436 /* Prefetch the remaining shaders after the draw has been
4437 * started.
4438 */
4439 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4440 radv_emit_prefetch_L2(cmd_buffer,
4441 cmd_buffer->state.pipeline, false);
4442 }
4443 }
4444
4445 /* Workaround for a VGT hang when streamout is enabled.
4446 * It must be done after drawing.
4447 */
4448 if (cmd_buffer->state.streamout.streamout_enabled &&
4449 (rad_info->family == CHIP_HAWAII ||
4450 rad_info->family == CHIP_TONGA ||
4451 rad_info->family == CHIP_FIJI)) {
4452 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
4453 }
4454
4455 assert(cmd_buffer->cs->cdw <= cdw_max);
4456 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
4457 }
4458
4459 void radv_CmdDraw(
4460 VkCommandBuffer commandBuffer,
4461 uint32_t vertexCount,
4462 uint32_t instanceCount,
4463 uint32_t firstVertex,
4464 uint32_t firstInstance)
4465 {
4466 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4467 struct radv_draw_info info = {};
4468
4469 info.count = vertexCount;
4470 info.instance_count = instanceCount;
4471 info.first_instance = firstInstance;
4472 info.vertex_offset = firstVertex;
4473
4474 radv_draw(cmd_buffer, &info);
4475 }
4476
4477 void radv_CmdDrawIndexed(
4478 VkCommandBuffer commandBuffer,
4479 uint32_t indexCount,
4480 uint32_t instanceCount,
4481 uint32_t firstIndex,
4482 int32_t vertexOffset,
4483 uint32_t firstInstance)
4484 {
4485 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4486 struct radv_draw_info info = {};
4487
4488 info.indexed = true;
4489 info.count = indexCount;
4490 info.instance_count = instanceCount;
4491 info.first_index = firstIndex;
4492 info.vertex_offset = vertexOffset;
4493 info.first_instance = firstInstance;
4494
4495 radv_draw(cmd_buffer, &info);
4496 }
4497
4498 void radv_CmdDrawIndirect(
4499 VkCommandBuffer commandBuffer,
4500 VkBuffer _buffer,
4501 VkDeviceSize offset,
4502 uint32_t drawCount,
4503 uint32_t stride)
4504 {
4505 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4506 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4507 struct radv_draw_info info = {};
4508
4509 info.count = drawCount;
4510 info.indirect = buffer;
4511 info.indirect_offset = offset;
4512 info.stride = stride;
4513
4514 radv_draw(cmd_buffer, &info);
4515 }
4516
4517 void radv_CmdDrawIndexedIndirect(
4518 VkCommandBuffer commandBuffer,
4519 VkBuffer _buffer,
4520 VkDeviceSize offset,
4521 uint32_t drawCount,
4522 uint32_t stride)
4523 {
4524 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4525 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4526 struct radv_draw_info info = {};
4527
4528 info.indexed = true;
4529 info.count = drawCount;
4530 info.indirect = buffer;
4531 info.indirect_offset = offset;
4532 info.stride = stride;
4533
4534 radv_draw(cmd_buffer, &info);
4535 }
4536
4537 void radv_CmdDrawIndirectCountKHR(
4538 VkCommandBuffer commandBuffer,
4539 VkBuffer _buffer,
4540 VkDeviceSize offset,
4541 VkBuffer _countBuffer,
4542 VkDeviceSize countBufferOffset,
4543 uint32_t maxDrawCount,
4544 uint32_t stride)
4545 {
4546 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4547 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4548 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4549 struct radv_draw_info info = {};
4550
4551 info.count = maxDrawCount;
4552 info.indirect = buffer;
4553 info.indirect_offset = offset;
4554 info.count_buffer = count_buffer;
4555 info.count_buffer_offset = countBufferOffset;
4556 info.stride = stride;
4557
4558 radv_draw(cmd_buffer, &info);
4559 }
4560
4561 void radv_CmdDrawIndexedIndirectCountKHR(
4562 VkCommandBuffer commandBuffer,
4563 VkBuffer _buffer,
4564 VkDeviceSize offset,
4565 VkBuffer _countBuffer,
4566 VkDeviceSize countBufferOffset,
4567 uint32_t maxDrawCount,
4568 uint32_t stride)
4569 {
4570 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4571 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4572 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4573 struct radv_draw_info info = {};
4574
4575 info.indexed = true;
4576 info.count = maxDrawCount;
4577 info.indirect = buffer;
4578 info.indirect_offset = offset;
4579 info.count_buffer = count_buffer;
4580 info.count_buffer_offset = countBufferOffset;
4581 info.stride = stride;
4582
4583 radv_draw(cmd_buffer, &info);
4584 }
4585
4586 struct radv_dispatch_info {
4587 /**
4588 * Determine the layout of the grid (in block units) to be used.
4589 */
4590 uint32_t blocks[3];
4591
4592 /**
4593 * A starting offset for the grid. If unaligned is set, the offset
4594 * must still be aligned.
4595 */
4596 uint32_t offsets[3];
4597 /**
4598 * Whether it's an unaligned compute dispatch.
4599 */
4600 bool unaligned;
4601
4602 /**
4603 * Indirect compute parameters resource.
4604 */
4605 struct radv_buffer *indirect;
4606 uint64_t indirect_offset;
4607 };
4608
4609 static void
4610 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
4611 const struct radv_dispatch_info *info)
4612 {
4613 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4614 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4615 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
4616 struct radeon_winsys *ws = cmd_buffer->device->ws;
4617 bool predicating = cmd_buffer->state.predicating;
4618 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4619 struct radv_userdata_info *loc;
4620
4621 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
4622 AC_UD_CS_GRID_SIZE);
4623
4624 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
4625
4626 if (info->indirect) {
4627 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4628
4629 va += info->indirect->offset + info->indirect_offset;
4630
4631 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4632
4633 if (loc->sgpr_idx != -1) {
4634 for (unsigned i = 0; i < 3; ++i) {
4635 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4636 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4637 COPY_DATA_DST_SEL(COPY_DATA_REG));
4638 radeon_emit(cs, (va + 4 * i));
4639 radeon_emit(cs, (va + 4 * i) >> 32);
4640 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
4641 + loc->sgpr_idx * 4) >> 2) + i);
4642 radeon_emit(cs, 0);
4643 }
4644 }
4645
4646 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
4647 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
4648 PKT3_SHADER_TYPE_S(1));
4649 radeon_emit(cs, va);
4650 radeon_emit(cs, va >> 32);
4651 radeon_emit(cs, dispatch_initiator);
4652 } else {
4653 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
4654 PKT3_SHADER_TYPE_S(1));
4655 radeon_emit(cs, 1);
4656 radeon_emit(cs, va);
4657 radeon_emit(cs, va >> 32);
4658
4659 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
4660 PKT3_SHADER_TYPE_S(1));
4661 radeon_emit(cs, 0);
4662 radeon_emit(cs, dispatch_initiator);
4663 }
4664 } else {
4665 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
4666 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
4667
4668 if (info->unaligned) {
4669 unsigned *cs_block_size = compute_shader->info.cs.block_size;
4670 unsigned remainder[3];
4671
4672 /* If aligned, these should be an entire block size,
4673 * not 0.
4674 */
4675 remainder[0] = blocks[0] + cs_block_size[0] -
4676 align_u32_npot(blocks[0], cs_block_size[0]);
4677 remainder[1] = blocks[1] + cs_block_size[1] -
4678 align_u32_npot(blocks[1], cs_block_size[1]);
4679 remainder[2] = blocks[2] + cs_block_size[2] -
4680 align_u32_npot(blocks[2], cs_block_size[2]);
4681
4682 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
4683 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
4684 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
4685
4686 for(unsigned i = 0; i < 3; ++i) {
4687 assert(offsets[i] % cs_block_size[i] == 0);
4688 offsets[i] /= cs_block_size[i];
4689 }
4690
4691 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4692 radeon_emit(cs,
4693 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
4694 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4695 radeon_emit(cs,
4696 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4697 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4698 radeon_emit(cs,
4699 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4700 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4701
4702 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4703 }
4704
4705 if (loc->sgpr_idx != -1) {
4706 assert(loc->num_sgprs == 3);
4707
4708 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4709 loc->sgpr_idx * 4, 3);
4710 radeon_emit(cs, blocks[0]);
4711 radeon_emit(cs, blocks[1]);
4712 radeon_emit(cs, blocks[2]);
4713 }
4714
4715 if (offsets[0] || offsets[1] || offsets[2]) {
4716 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4717 radeon_emit(cs, offsets[0]);
4718 radeon_emit(cs, offsets[1]);
4719 radeon_emit(cs, offsets[2]);
4720
4721 /* The blocks in the packet are not counts but end values. */
4722 for (unsigned i = 0; i < 3; ++i)
4723 blocks[i] += offsets[i];
4724 } else {
4725 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4726 }
4727
4728 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4729 PKT3_SHADER_TYPE_S(1));
4730 radeon_emit(cs, blocks[0]);
4731 radeon_emit(cs, blocks[1]);
4732 radeon_emit(cs, blocks[2]);
4733 radeon_emit(cs, dispatch_initiator);
4734 }
4735
4736 assert(cmd_buffer->cs->cdw <= cdw_max);
4737 }
4738
4739 static void
4740 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4741 {
4742 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4743 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4744 }
4745
4746 static void
4747 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4748 const struct radv_dispatch_info *info)
4749 {
4750 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4751 bool has_prefetch =
4752 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4753 bool pipeline_is_dirty = pipeline &&
4754 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4755
4756 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4757 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4758 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4759 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4760 /* If we have to wait for idle, set all states first, so that
4761 * all SET packets are processed in parallel with previous draw
4762 * calls. Then upload descriptors, set shader pointers, and
4763 * dispatch, and prefetch at the end. This ensures that the
4764 * time the CUs are idle is very short. (there are only SET_SH
4765 * packets between the wait and the draw)
4766 */
4767 radv_emit_compute_pipeline(cmd_buffer);
4768 si_emit_cache_flush(cmd_buffer);
4769 /* <-- CUs are idle here --> */
4770
4771 radv_upload_compute_shader_descriptors(cmd_buffer);
4772
4773 radv_emit_dispatch_packets(cmd_buffer, info);
4774 /* <-- CUs are busy here --> */
4775
4776 /* Start prefetches after the dispatch has been started. Both
4777 * will run in parallel, but starting the dispatch first is
4778 * more important.
4779 */
4780 if (has_prefetch && pipeline_is_dirty) {
4781 radv_emit_shader_prefetch(cmd_buffer,
4782 pipeline->shaders[MESA_SHADER_COMPUTE]);
4783 }
4784 } else {
4785 /* If we don't wait for idle, start prefetches first, then set
4786 * states, and dispatch at the end.
4787 */
4788 si_emit_cache_flush(cmd_buffer);
4789
4790 if (has_prefetch && pipeline_is_dirty) {
4791 radv_emit_shader_prefetch(cmd_buffer,
4792 pipeline->shaders[MESA_SHADER_COMPUTE]);
4793 }
4794
4795 radv_upload_compute_shader_descriptors(cmd_buffer);
4796
4797 radv_emit_compute_pipeline(cmd_buffer);
4798 radv_emit_dispatch_packets(cmd_buffer, info);
4799 }
4800
4801 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
4802 }
4803
4804 void radv_CmdDispatchBase(
4805 VkCommandBuffer commandBuffer,
4806 uint32_t base_x,
4807 uint32_t base_y,
4808 uint32_t base_z,
4809 uint32_t x,
4810 uint32_t y,
4811 uint32_t z)
4812 {
4813 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4814 struct radv_dispatch_info info = {};
4815
4816 info.blocks[0] = x;
4817 info.blocks[1] = y;
4818 info.blocks[2] = z;
4819
4820 info.offsets[0] = base_x;
4821 info.offsets[1] = base_y;
4822 info.offsets[2] = base_z;
4823 radv_dispatch(cmd_buffer, &info);
4824 }
4825
4826 void radv_CmdDispatch(
4827 VkCommandBuffer commandBuffer,
4828 uint32_t x,
4829 uint32_t y,
4830 uint32_t z)
4831 {
4832 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4833 }
4834
4835 void radv_CmdDispatchIndirect(
4836 VkCommandBuffer commandBuffer,
4837 VkBuffer _buffer,
4838 VkDeviceSize offset)
4839 {
4840 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4841 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4842 struct radv_dispatch_info info = {};
4843
4844 info.indirect = buffer;
4845 info.indirect_offset = offset;
4846
4847 radv_dispatch(cmd_buffer, &info);
4848 }
4849
4850 void radv_unaligned_dispatch(
4851 struct radv_cmd_buffer *cmd_buffer,
4852 uint32_t x,
4853 uint32_t y,
4854 uint32_t z)
4855 {
4856 struct radv_dispatch_info info = {};
4857
4858 info.blocks[0] = x;
4859 info.blocks[1] = y;
4860 info.blocks[2] = z;
4861 info.unaligned = 1;
4862
4863 radv_dispatch(cmd_buffer, &info);
4864 }
4865
4866 void radv_CmdEndRenderPass(
4867 VkCommandBuffer commandBuffer)
4868 {
4869 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4870
4871 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
4872
4873 radv_cmd_buffer_end_subpass(cmd_buffer);
4874
4875 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4876 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
4877
4878 cmd_buffer->state.pass = NULL;
4879 cmd_buffer->state.subpass = NULL;
4880 cmd_buffer->state.attachments = NULL;
4881 cmd_buffer->state.framebuffer = NULL;
4882 cmd_buffer->state.subpass_sample_locs = NULL;
4883 }
4884
4885 void radv_CmdEndRenderPass2KHR(
4886 VkCommandBuffer commandBuffer,
4887 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4888 {
4889 radv_CmdEndRenderPass(commandBuffer);
4890 }
4891
4892 /*
4893 * For HTILE we have the following interesting clear words:
4894 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4895 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4896 * 0xfffffff0: Clear depth to 1.0
4897 * 0x00000000: Clear depth to 0.0
4898 */
4899 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
4900 struct radv_image *image,
4901 const VkImageSubresourceRange *range,
4902 uint32_t clear_word)
4903 {
4904 assert(range->baseMipLevel == 0);
4905 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
4906 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
4907 struct radv_cmd_state *state = &cmd_buffer->state;
4908 VkClearDepthStencilValue value = {};
4909
4910 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4911 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4912
4913 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, clear_word);
4914
4915 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4916
4917 if (vk_format_is_stencil(image->vk_format))
4918 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4919
4920 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4921
4922 if (radv_image_is_tc_compat_htile(image)) {
4923 /* Initialize the TC-compat metada value to 0 because by
4924 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
4925 * need have to conditionally update its value when performing
4926 * a fast depth clear.
4927 */
4928 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, 0);
4929 }
4930 }
4931
4932 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4933 struct radv_image *image,
4934 VkImageLayout src_layout,
4935 VkImageLayout dst_layout,
4936 unsigned src_queue_mask,
4937 unsigned dst_queue_mask,
4938 const VkImageSubresourceRange *range,
4939 struct radv_sample_locations_state *sample_locs)
4940 {
4941 if (!radv_image_has_htile(image))
4942 return;
4943
4944 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4945 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4946
4947 if (radv_layout_is_htile_compressed(image, dst_layout,
4948 dst_queue_mask)) {
4949 clear_value = 0;
4950 }
4951
4952 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4953 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4954 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4955 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4956 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4957 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4958 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4959 VkImageSubresourceRange local_range = *range;
4960 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4961 local_range.baseMipLevel = 0;
4962 local_range.levelCount = 1;
4963
4964 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4965 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4966
4967 radv_decompress_depth_image_inplace(cmd_buffer, image,
4968 &local_range, sample_locs);
4969
4970 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4971 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4972 }
4973 }
4974
4975 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4976 struct radv_image *image,
4977 const VkImageSubresourceRange *range,
4978 uint32_t value)
4979 {
4980 struct radv_cmd_state *state = &cmd_buffer->state;
4981
4982 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4983 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4984
4985 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
4986
4987 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4988 }
4989
4990 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
4991 struct radv_image *image,
4992 const VkImageSubresourceRange *range)
4993 {
4994 struct radv_cmd_state *state = &cmd_buffer->state;
4995 static const uint32_t fmask_clear_values[4] = {
4996 0x00000000,
4997 0x02020202,
4998 0xE4E4E4E4,
4999 0x76543210
5000 };
5001 uint32_t log2_samples = util_logbase2(image->info.samples);
5002 uint32_t value = fmask_clear_values[log2_samples];
5003
5004 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5005 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5006
5007 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
5008
5009 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5010 }
5011
5012 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
5013 struct radv_image *image,
5014 const VkImageSubresourceRange *range, uint32_t value)
5015 {
5016 struct radv_cmd_state *state = &cmd_buffer->state;
5017 unsigned size = 0;
5018
5019 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5020 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5021
5022 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
5023
5024 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
5025 /* When DCC is enabled with mipmaps, some levels might not
5026 * support fast clears and we have to initialize them as "fully
5027 * expanded".
5028 */
5029 /* Compute the size of all fast clearable DCC levels. */
5030 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
5031 struct legacy_surf_level *surf_level =
5032 &image->planes[0].surface.u.legacy.level[i];
5033 unsigned dcc_fast_clear_size =
5034 surf_level->dcc_slice_fast_clear_size * image->info.array_size;
5035
5036 if (!dcc_fast_clear_size)
5037 break;
5038
5039 size = surf_level->dcc_offset + dcc_fast_clear_size;
5040 }
5041
5042 /* Initialize the mipmap levels without DCC. */
5043 if (size != image->planes[0].surface.dcc_size) {
5044 state->flush_bits |=
5045 radv_fill_buffer(cmd_buffer, image->bo,
5046 image->offset + image->dcc_offset + size,
5047 image->planes[0].surface.dcc_size - size,
5048 0xffffffff);
5049 }
5050 }
5051
5052 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5053 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5054 }
5055
5056 /**
5057 * Initialize DCC/FMASK/CMASK metadata for a color image.
5058 */
5059 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
5060 struct radv_image *image,
5061 VkImageLayout src_layout,
5062 VkImageLayout dst_layout,
5063 unsigned src_queue_mask,
5064 unsigned dst_queue_mask,
5065 const VkImageSubresourceRange *range)
5066 {
5067 if (radv_image_has_cmask(image)) {
5068 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5069
5070 /* TODO: clarify this. */
5071 if (radv_image_has_fmask(image)) {
5072 value = 0xccccccccu;
5073 }
5074
5075 radv_initialise_cmask(cmd_buffer, image, range, value);
5076 }
5077
5078 if (radv_image_has_fmask(image)) {
5079 radv_initialize_fmask(cmd_buffer, image, range);
5080 }
5081
5082 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5083 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5084 bool need_decompress_pass = false;
5085
5086 if (radv_layout_dcc_compressed(image, dst_layout,
5087 dst_queue_mask)) {
5088 value = 0x20202020u;
5089 need_decompress_pass = true;
5090 }
5091
5092 radv_initialize_dcc(cmd_buffer, image, range, value);
5093
5094 radv_update_fce_metadata(cmd_buffer, image, range,
5095 need_decompress_pass);
5096 }
5097
5098 if (radv_image_has_cmask(image) ||
5099 radv_dcc_enabled(image, range->baseMipLevel)) {
5100 uint32_t color_values[2] = {};
5101 radv_set_color_clear_metadata(cmd_buffer, image, range,
5102 color_values);
5103 }
5104 }
5105
5106 /**
5107 * Handle color image transitions for DCC/FMASK/CMASK.
5108 */
5109 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
5110 struct radv_image *image,
5111 VkImageLayout src_layout,
5112 VkImageLayout dst_layout,
5113 unsigned src_queue_mask,
5114 unsigned dst_queue_mask,
5115 const VkImageSubresourceRange *range)
5116 {
5117 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5118 radv_init_color_image_metadata(cmd_buffer, image,
5119 src_layout, dst_layout,
5120 src_queue_mask, dst_queue_mask,
5121 range);
5122 return;
5123 }
5124
5125 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5126 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
5127 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
5128 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
5129 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
5130 radv_decompress_dcc(cmd_buffer, image, range);
5131 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
5132 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
5133 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5134 }
5135 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
5136 bool fce_eliminate = false, fmask_expand = false;
5137
5138 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
5139 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
5140 fce_eliminate = true;
5141 }
5142
5143 if (radv_image_has_fmask(image)) {
5144 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
5145 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
5146 /* A FMASK decompress is required before doing
5147 * a MSAA decompress using FMASK.
5148 */
5149 fmask_expand = true;
5150 }
5151 }
5152
5153 if (fce_eliminate || fmask_expand)
5154 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5155
5156 if (fmask_expand)
5157 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
5158 }
5159 }
5160
5161 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
5162 struct radv_image *image,
5163 VkImageLayout src_layout,
5164 VkImageLayout dst_layout,
5165 uint32_t src_family,
5166 uint32_t dst_family,
5167 const VkImageSubresourceRange *range,
5168 struct radv_sample_locations_state *sample_locs)
5169 {
5170 if (image->exclusive && src_family != dst_family) {
5171 /* This is an acquire or a release operation and there will be
5172 * a corresponding release/acquire. Do the transition in the
5173 * most flexible queue. */
5174
5175 assert(src_family == cmd_buffer->queue_family_index ||
5176 dst_family == cmd_buffer->queue_family_index);
5177
5178 if (src_family == VK_QUEUE_FAMILY_EXTERNAL ||
5179 src_family == VK_QUEUE_FAMILY_FOREIGN_EXT)
5180 return;
5181
5182 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
5183 return;
5184
5185 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
5186 (src_family == RADV_QUEUE_GENERAL ||
5187 dst_family == RADV_QUEUE_GENERAL))
5188 return;
5189 }
5190
5191 if (src_layout == dst_layout)
5192 return;
5193
5194 unsigned src_queue_mask =
5195 radv_image_queue_family_mask(image, src_family,
5196 cmd_buffer->queue_family_index);
5197 unsigned dst_queue_mask =
5198 radv_image_queue_family_mask(image, dst_family,
5199 cmd_buffer->queue_family_index);
5200
5201 if (vk_format_is_depth(image->vk_format)) {
5202 radv_handle_depth_image_transition(cmd_buffer, image,
5203 src_layout, dst_layout,
5204 src_queue_mask, dst_queue_mask,
5205 range, sample_locs);
5206 } else {
5207 radv_handle_color_image_transition(cmd_buffer, image,
5208 src_layout, dst_layout,
5209 src_queue_mask, dst_queue_mask,
5210 range);
5211 }
5212 }
5213
5214 struct radv_barrier_info {
5215 uint32_t eventCount;
5216 const VkEvent *pEvents;
5217 VkPipelineStageFlags srcStageMask;
5218 VkPipelineStageFlags dstStageMask;
5219 };
5220
5221 static void
5222 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
5223 uint32_t memoryBarrierCount,
5224 const VkMemoryBarrier *pMemoryBarriers,
5225 uint32_t bufferMemoryBarrierCount,
5226 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
5227 uint32_t imageMemoryBarrierCount,
5228 const VkImageMemoryBarrier *pImageMemoryBarriers,
5229 const struct radv_barrier_info *info)
5230 {
5231 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5232 enum radv_cmd_flush_bits src_flush_bits = 0;
5233 enum radv_cmd_flush_bits dst_flush_bits = 0;
5234
5235 for (unsigned i = 0; i < info->eventCount; ++i) {
5236 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
5237 uint64_t va = radv_buffer_get_va(event->bo);
5238
5239 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5240
5241 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
5242
5243 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
5244 assert(cmd_buffer->cs->cdw <= cdw_max);
5245 }
5246
5247 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
5248 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
5249 NULL);
5250 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
5251 NULL);
5252 }
5253
5254 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
5255 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
5256 NULL);
5257 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
5258 NULL);
5259 }
5260
5261 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5262 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5263
5264 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
5265 image);
5266 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
5267 image);
5268 }
5269
5270 /* The Vulkan spec 1.1.98 says:
5271 *
5272 * "An execution dependency with only
5273 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5274 * will only prevent that stage from executing in subsequently
5275 * submitted commands. As this stage does not perform any actual
5276 * execution, this is not observable - in effect, it does not delay
5277 * processing of subsequent commands. Similarly an execution dependency
5278 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5279 * will effectively not wait for any prior commands to complete."
5280 */
5281 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
5282 radv_stage_flush(cmd_buffer, info->srcStageMask);
5283 cmd_buffer->state.flush_bits |= src_flush_bits;
5284
5285 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5286 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5287
5288 const struct VkSampleLocationsInfoEXT *sample_locs_info =
5289 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
5290 SAMPLE_LOCATIONS_INFO_EXT);
5291 struct radv_sample_locations_state sample_locations = {};
5292
5293 if (sample_locs_info) {
5294 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
5295 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
5296 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
5297 sample_locations.count = sample_locs_info->sampleLocationsCount;
5298 typed_memcpy(&sample_locations.locations[0],
5299 sample_locs_info->pSampleLocations,
5300 sample_locs_info->sampleLocationsCount);
5301 }
5302
5303 radv_handle_image_transition(cmd_buffer, image,
5304 pImageMemoryBarriers[i].oldLayout,
5305 pImageMemoryBarriers[i].newLayout,
5306 pImageMemoryBarriers[i].srcQueueFamilyIndex,
5307 pImageMemoryBarriers[i].dstQueueFamilyIndex,
5308 &pImageMemoryBarriers[i].subresourceRange,
5309 sample_locs_info ? &sample_locations : NULL);
5310 }
5311
5312 /* Make sure CP DMA is idle because the driver might have performed a
5313 * DMA operation for copying or filling buffers/images.
5314 */
5315 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5316 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5317 si_cp_dma_wait_for_idle(cmd_buffer);
5318
5319 cmd_buffer->state.flush_bits |= dst_flush_bits;
5320 }
5321
5322 void radv_CmdPipelineBarrier(
5323 VkCommandBuffer commandBuffer,
5324 VkPipelineStageFlags srcStageMask,
5325 VkPipelineStageFlags destStageMask,
5326 VkBool32 byRegion,
5327 uint32_t memoryBarrierCount,
5328 const VkMemoryBarrier* pMemoryBarriers,
5329 uint32_t bufferMemoryBarrierCount,
5330 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5331 uint32_t imageMemoryBarrierCount,
5332 const VkImageMemoryBarrier* pImageMemoryBarriers)
5333 {
5334 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5335 struct radv_barrier_info info;
5336
5337 info.eventCount = 0;
5338 info.pEvents = NULL;
5339 info.srcStageMask = srcStageMask;
5340 info.dstStageMask = destStageMask;
5341
5342 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5343 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5344 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5345 }
5346
5347
5348 static void write_event(struct radv_cmd_buffer *cmd_buffer,
5349 struct radv_event *event,
5350 VkPipelineStageFlags stageMask,
5351 unsigned value)
5352 {
5353 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5354 uint64_t va = radv_buffer_get_va(event->bo);
5355
5356 si_emit_cache_flush(cmd_buffer);
5357
5358 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5359
5360 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
5361
5362 /* Flags that only require a top-of-pipe event. */
5363 VkPipelineStageFlags top_of_pipe_flags =
5364 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
5365
5366 /* Flags that only require a post-index-fetch event. */
5367 VkPipelineStageFlags post_index_fetch_flags =
5368 top_of_pipe_flags |
5369 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
5370 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
5371
5372 /* Make sure CP DMA is idle because the driver might have performed a
5373 * DMA operation for copying or filling buffers/images.
5374 */
5375 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5376 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5377 si_cp_dma_wait_for_idle(cmd_buffer);
5378
5379 /* TODO: Emit EOS events for syncing PS/CS stages. */
5380
5381 if (!(stageMask & ~top_of_pipe_flags)) {
5382 /* Just need to sync the PFP engine. */
5383 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5384 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5385 S_370_WR_CONFIRM(1) |
5386 S_370_ENGINE_SEL(V_370_PFP));
5387 radeon_emit(cs, va);
5388 radeon_emit(cs, va >> 32);
5389 radeon_emit(cs, value);
5390 } else if (!(stageMask & ~post_index_fetch_flags)) {
5391 /* Sync ME because PFP reads index and indirect buffers. */
5392 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5393 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5394 S_370_WR_CONFIRM(1) |
5395 S_370_ENGINE_SEL(V_370_ME));
5396 radeon_emit(cs, va);
5397 radeon_emit(cs, va >> 32);
5398 radeon_emit(cs, value);
5399 } else {
5400 /* Otherwise, sync all prior GPU work using an EOP event. */
5401 si_cs_emit_write_event_eop(cs,
5402 cmd_buffer->device->physical_device->rad_info.chip_class,
5403 radv_cmd_buffer_uses_mec(cmd_buffer),
5404 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5405 EOP_DST_SEL_MEM,
5406 EOP_DATA_SEL_VALUE_32BIT, va, value,
5407 cmd_buffer->gfx9_eop_bug_va);
5408 }
5409
5410 assert(cmd_buffer->cs->cdw <= cdw_max);
5411 }
5412
5413 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
5414 VkEvent _event,
5415 VkPipelineStageFlags stageMask)
5416 {
5417 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5418 RADV_FROM_HANDLE(radv_event, event, _event);
5419
5420 write_event(cmd_buffer, event, stageMask, 1);
5421 }
5422
5423 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
5424 VkEvent _event,
5425 VkPipelineStageFlags stageMask)
5426 {
5427 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5428 RADV_FROM_HANDLE(radv_event, event, _event);
5429
5430 write_event(cmd_buffer, event, stageMask, 0);
5431 }
5432
5433 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
5434 uint32_t eventCount,
5435 const VkEvent* pEvents,
5436 VkPipelineStageFlags srcStageMask,
5437 VkPipelineStageFlags dstStageMask,
5438 uint32_t memoryBarrierCount,
5439 const VkMemoryBarrier* pMemoryBarriers,
5440 uint32_t bufferMemoryBarrierCount,
5441 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5442 uint32_t imageMemoryBarrierCount,
5443 const VkImageMemoryBarrier* pImageMemoryBarriers)
5444 {
5445 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5446 struct radv_barrier_info info;
5447
5448 info.eventCount = eventCount;
5449 info.pEvents = pEvents;
5450 info.srcStageMask = 0;
5451
5452 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5453 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5454 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5455 }
5456
5457
5458 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
5459 uint32_t deviceMask)
5460 {
5461 /* No-op */
5462 }
5463
5464 /* VK_EXT_conditional_rendering */
5465 void radv_CmdBeginConditionalRenderingEXT(
5466 VkCommandBuffer commandBuffer,
5467 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
5468 {
5469 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5470 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
5471 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5472 bool draw_visible = true;
5473 uint64_t pred_value = 0;
5474 uint64_t va, new_va;
5475 unsigned pred_offset;
5476
5477 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
5478
5479 /* By default, if the 32-bit value at offset in buffer memory is zero,
5480 * then the rendering commands are discarded, otherwise they are
5481 * executed as normal. If the inverted flag is set, all commands are
5482 * discarded if the value is non zero.
5483 */
5484 if (pConditionalRenderingBegin->flags &
5485 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
5486 draw_visible = false;
5487 }
5488
5489 si_emit_cache_flush(cmd_buffer);
5490
5491 /* From the Vulkan spec 1.1.107:
5492 *
5493 * "If the 32-bit value at offset in buffer memory is zero, then the
5494 * rendering commands are discarded, otherwise they are executed as
5495 * normal. If the value of the predicate in buffer memory changes while
5496 * conditional rendering is active, the rendering commands may be
5497 * discarded in an implementation-dependent way. Some implementations
5498 * may latch the value of the predicate upon beginning conditional
5499 * rendering while others may read it before every rendering command."
5500 *
5501 * But, the AMD hardware treats the predicate as a 64-bit value which
5502 * means we need a workaround in the driver. Luckily, it's not required
5503 * to support if the value changes when predication is active.
5504 *
5505 * The workaround is as follows:
5506 * 1) allocate a 64-value in the upload BO and initialize it to 0
5507 * 2) copy the 32-bit predicate value to the upload BO
5508 * 3) use the new allocated VA address for predication
5509 *
5510 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5511 * in ME (+ sync PFP) instead of PFP.
5512 */
5513 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
5514
5515 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
5516
5517 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5518 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5519 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5520 COPY_DATA_WR_CONFIRM);
5521 radeon_emit(cs, va);
5522 radeon_emit(cs, va >> 32);
5523 radeon_emit(cs, new_va);
5524 radeon_emit(cs, new_va >> 32);
5525
5526 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
5527 radeon_emit(cs, 0);
5528
5529 /* Enable predication for this command buffer. */
5530 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
5531 cmd_buffer->state.predicating = true;
5532
5533 /* Store conditional rendering user info. */
5534 cmd_buffer->state.predication_type = draw_visible;
5535 cmd_buffer->state.predication_va = new_va;
5536 }
5537
5538 void radv_CmdEndConditionalRenderingEXT(
5539 VkCommandBuffer commandBuffer)
5540 {
5541 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5542
5543 /* Disable predication for this command buffer. */
5544 si_emit_set_predication_state(cmd_buffer, false, 0);
5545 cmd_buffer->state.predicating = false;
5546
5547 /* Reset conditional rendering user info. */
5548 cmd_buffer->state.predication_type = -1;
5549 cmd_buffer->state.predication_va = 0;
5550 }
5551
5552 /* VK_EXT_transform_feedback */
5553 void radv_CmdBindTransformFeedbackBuffersEXT(
5554 VkCommandBuffer commandBuffer,
5555 uint32_t firstBinding,
5556 uint32_t bindingCount,
5557 const VkBuffer* pBuffers,
5558 const VkDeviceSize* pOffsets,
5559 const VkDeviceSize* pSizes)
5560 {
5561 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5562 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5563 uint8_t enabled_mask = 0;
5564
5565 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
5566 for (uint32_t i = 0; i < bindingCount; i++) {
5567 uint32_t idx = firstBinding + i;
5568
5569 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
5570 sb[idx].offset = pOffsets[i];
5571 sb[idx].size = pSizes[i];
5572
5573 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
5574 sb[idx].buffer->bo);
5575
5576 enabled_mask |= 1 << idx;
5577 }
5578
5579 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
5580
5581 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
5582 }
5583
5584 static void
5585 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
5586 {
5587 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5588 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5589
5590 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
5591 radeon_emit(cs,
5592 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
5593 S_028B94_RAST_STREAM(0) |
5594 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
5595 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
5596 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
5597 radeon_emit(cs, so->hw_enabled_mask &
5598 so->enabled_stream_buffers_mask);
5599
5600 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5601 }
5602
5603 static void
5604 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
5605 {
5606 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5607 bool old_streamout_enabled = so->streamout_enabled;
5608 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
5609
5610 so->streamout_enabled = enable;
5611
5612 so->hw_enabled_mask = so->enabled_mask |
5613 (so->enabled_mask << 4) |
5614 (so->enabled_mask << 8) |
5615 (so->enabled_mask << 12);
5616
5617 if ((old_streamout_enabled != so->streamout_enabled) ||
5618 (old_hw_enabled_mask != so->hw_enabled_mask))
5619 radv_emit_streamout_enable(cmd_buffer);
5620 }
5621
5622 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
5623 {
5624 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5625 unsigned reg_strmout_cntl;
5626
5627 /* The register is at different places on different ASICs. */
5628 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
5629 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
5630 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
5631 } else {
5632 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
5633 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
5634 }
5635
5636 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
5637 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
5638
5639 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
5640 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
5641 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
5642 radeon_emit(cs, 0);
5643 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5644 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5645 radeon_emit(cs, 4); /* poll interval */
5646 }
5647
5648 static void
5649 radv_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
5650 uint32_t firstCounterBuffer,
5651 uint32_t counterBufferCount,
5652 const VkBuffer *pCounterBuffers,
5653 const VkDeviceSize *pCounterBufferOffsets)
5654
5655 {
5656 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5657 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5658 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5659 uint32_t i;
5660
5661 radv_flush_vgt_streamout(cmd_buffer);
5662
5663 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5664 for_each_bit(i, so->enabled_mask) {
5665 int32_t counter_buffer_idx = i - firstCounterBuffer;
5666 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5667 counter_buffer_idx = -1;
5668
5669 /* AMD GCN binds streamout buffers as shader resources.
5670 * VGT only counts primitives and tells the shader through
5671 * SGPRs what to do.
5672 */
5673 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
5674 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
5675 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
5676
5677 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5678
5679 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5680 /* The array of counter buffers is optional. */
5681 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5682 uint64_t va = radv_buffer_get_va(buffer->bo);
5683
5684 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5685
5686 /* Append */
5687 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5688 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5689 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5690 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
5691 radeon_emit(cs, 0); /* unused */
5692 radeon_emit(cs, 0); /* unused */
5693 radeon_emit(cs, va); /* src address lo */
5694 radeon_emit(cs, va >> 32); /* src address hi */
5695
5696 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5697 } else {
5698 /* Start from the beginning. */
5699 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5700 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5701 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5702 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
5703 radeon_emit(cs, 0); /* unused */
5704 radeon_emit(cs, 0); /* unused */
5705 radeon_emit(cs, 0); /* unused */
5706 radeon_emit(cs, 0); /* unused */
5707 }
5708 }
5709
5710 radv_set_streamout_enable(cmd_buffer, true);
5711 }
5712
5713 void radv_CmdBeginTransformFeedbackEXT(
5714 VkCommandBuffer commandBuffer,
5715 uint32_t firstCounterBuffer,
5716 uint32_t counterBufferCount,
5717 const VkBuffer* pCounterBuffers,
5718 const VkDeviceSize* pCounterBufferOffsets)
5719 {
5720 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5721
5722 radv_emit_streamout_begin(cmd_buffer,
5723 firstCounterBuffer, counterBufferCount,
5724 pCounterBuffers, pCounterBufferOffsets);
5725 }
5726
5727 static void
5728 radv_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
5729 uint32_t firstCounterBuffer,
5730 uint32_t counterBufferCount,
5731 const VkBuffer *pCounterBuffers,
5732 const VkDeviceSize *pCounterBufferOffsets)
5733 {
5734 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5735 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5736 uint32_t i;
5737
5738 radv_flush_vgt_streamout(cmd_buffer);
5739
5740 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5741 for_each_bit(i, so->enabled_mask) {
5742 int32_t counter_buffer_idx = i - firstCounterBuffer;
5743 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5744 counter_buffer_idx = -1;
5745
5746 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5747 /* The array of counters buffer is optional. */
5748 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5749 uint64_t va = radv_buffer_get_va(buffer->bo);
5750
5751 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5752
5753 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5754 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5755 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5756 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
5757 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
5758 radeon_emit(cs, va); /* dst address lo */
5759 radeon_emit(cs, va >> 32); /* dst address hi */
5760 radeon_emit(cs, 0); /* unused */
5761 radeon_emit(cs, 0); /* unused */
5762
5763 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5764 }
5765
5766 /* Deactivate transform feedback by zeroing the buffer size.
5767 * The counters (primitives generated, primitives emitted) may
5768 * be enabled even if there is not buffer bound. This ensures
5769 * that the primitives-emitted query won't increment.
5770 */
5771 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
5772
5773 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5774 }
5775
5776 radv_set_streamout_enable(cmd_buffer, false);
5777 }
5778
5779 void radv_CmdEndTransformFeedbackEXT(
5780 VkCommandBuffer commandBuffer,
5781 uint32_t firstCounterBuffer,
5782 uint32_t counterBufferCount,
5783 const VkBuffer* pCounterBuffers,
5784 const VkDeviceSize* pCounterBufferOffsets)
5785 {
5786 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5787
5788 radv_emit_streamout_end(cmd_buffer,
5789 firstCounterBuffer, counterBufferCount,
5790 pCounterBuffers, pCounterBufferOffsets);
5791 }
5792
5793 void radv_CmdDrawIndirectByteCountEXT(
5794 VkCommandBuffer commandBuffer,
5795 uint32_t instanceCount,
5796 uint32_t firstInstance,
5797 VkBuffer _counterBuffer,
5798 VkDeviceSize counterBufferOffset,
5799 uint32_t counterOffset,
5800 uint32_t vertexStride)
5801 {
5802 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5803 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
5804 struct radv_draw_info info = {};
5805
5806 info.instance_count = instanceCount;
5807 info.first_instance = firstInstance;
5808 info.strmout_buffer = counterBuffer;
5809 info.strmout_buffer_offset = counterBufferOffset;
5810 info.stride = vertexStride;
5811
5812 radv_draw(cmd_buffer, &info);
5813 }
5814
5815 /* VK_AMD_buffer_marker */
5816 void radv_CmdWriteBufferMarkerAMD(
5817 VkCommandBuffer commandBuffer,
5818 VkPipelineStageFlagBits pipelineStage,
5819 VkBuffer dstBuffer,
5820 VkDeviceSize dstOffset,
5821 uint32_t marker)
5822 {
5823 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5824 RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
5825 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5826 uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
5827
5828 si_emit_cache_flush(cmd_buffer);
5829
5830 if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
5831 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5832 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
5833 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5834 COPY_DATA_WR_CONFIRM);
5835 radeon_emit(cs, marker);
5836 radeon_emit(cs, 0);
5837 radeon_emit(cs, va);
5838 radeon_emit(cs, va >> 32);
5839 } else {
5840 si_cs_emit_write_event_eop(cs,
5841 cmd_buffer->device->physical_device->rad_info.chip_class,
5842 radv_cmd_buffer_uses_mec(cmd_buffer),
5843 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5844 EOP_DST_SEL_MEM,
5845 EOP_DATA_SEL_VALUE_32BIT,
5846 va, marker,
5847 cmd_buffer->gfx9_eop_bug_va);
5848 }
5849 }