projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: remove predication on cache flushes
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
41 struct radv_image *image,
42 VkImageLayout src_layout,
43 VkImageLayout dst_layout,
44 uint32_t src_family,
45 uint32_t dst_family,
46 const VkImageSubresourceRange *range,
47 VkImageAspectFlags pending_clears);
48
49 const struct radv_dynamic_state default_dynamic_state = {
50 .viewport = {
51 .count = 0,
52 },
53 .scissor = {
54 .count = 0,
55 },
56 .line_width = 1.0f,
57 .depth_bias = {
58 .bias = 0.0f,
59 .clamp = 0.0f,
60 .slope = 0.0f,
61 },
62 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
63 .depth_bounds = {
64 .min = 0.0f,
65 .max = 1.0f,
66 },
67 .stencil_compare_mask = {
68 .front = ~0u,
69 .back = ~0u,
70 },
71 .stencil_write_mask = {
72 .front = ~0u,
73 .back = ~0u,
74 },
75 .stencil_reference = {
76 .front = 0u,
77 .back = 0u,
78 },
79 };
80
81 static void
82 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
83 const struct radv_dynamic_state *src)
84 {
85 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
86 uint32_t copy_mask = src->mask;
87 uint32_t dest_mask = 0;
88
89 /* Make sure to copy the number of viewports/scissors because they can
90 * only be specified at pipeline creation time.
91 */
92 dest->viewport.count = src->viewport.count;
93 dest->scissor.count = src->scissor.count;
94 dest->discard_rectangle.count = src->discard_rectangle.count;
95
96 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
97 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
98 src->viewport.count * sizeof(VkViewport))) {
99 typed_memcpy(dest->viewport.viewports,
100 src->viewport.viewports,
101 src->viewport.count);
102 dest_mask |= RADV_DYNAMIC_VIEWPORT;
103 }
104 }
105
106 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
107 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
108 src->scissor.count * sizeof(VkRect2D))) {
109 typed_memcpy(dest->scissor.scissors,
110 src->scissor.scissors, src->scissor.count);
111 dest_mask |= RADV_DYNAMIC_SCISSOR;
112 }
113 }
114
115 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
116 if (dest->line_width != src->line_width) {
117 dest->line_width = src->line_width;
118 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
119 }
120 }
121
122 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
123 if (memcmp(&dest->depth_bias, &src->depth_bias,
124 sizeof(src->depth_bias))) {
125 dest->depth_bias = src->depth_bias;
126 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
127 }
128 }
129
130 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
131 if (memcmp(&dest->blend_constants, &src->blend_constants,
132 sizeof(src->blend_constants))) {
133 typed_memcpy(dest->blend_constants,
134 src->blend_constants, 4);
135 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
136 }
137 }
138
139 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
140 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
141 sizeof(src->depth_bounds))) {
142 dest->depth_bounds = src->depth_bounds;
143 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
144 }
145 }
146
147 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
148 if (memcmp(&dest->stencil_compare_mask,
149 &src->stencil_compare_mask,
150 sizeof(src->stencil_compare_mask))) {
151 dest->stencil_compare_mask = src->stencil_compare_mask;
152 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
153 }
154 }
155
156 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
157 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
158 sizeof(src->stencil_write_mask))) {
159 dest->stencil_write_mask = src->stencil_write_mask;
160 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
161 }
162 }
163
164 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
165 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
166 sizeof(src->stencil_reference))) {
167 dest->stencil_reference = src->stencil_reference;
168 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
169 }
170 }
171
172 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
173 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
174 src->discard_rectangle.count * sizeof(VkRect2D))) {
175 typed_memcpy(dest->discard_rectangle.rectangles,
176 src->discard_rectangle.rectangles,
177 src->discard_rectangle.count);
178 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
179 }
180 }
181
182 cmd_buffer->state.dirty |= dest_mask;
183 }
184
185 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
186 {
187 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
188 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
189 }
190
191 enum ring_type radv_queue_family_to_ring(int f) {
192 switch (f) {
193 case RADV_QUEUE_GENERAL:
194 return RING_GFX;
195 case RADV_QUEUE_COMPUTE:
196 return RING_COMPUTE;
197 case RADV_QUEUE_TRANSFER:
198 return RING_DMA;
199 default:
200 unreachable("Unknown queue family");
201 }
202 }
203
204 static VkResult radv_create_cmd_buffer(
205 struct radv_device * device,
206 struct radv_cmd_pool * pool,
207 VkCommandBufferLevel level,
208 VkCommandBuffer* pCommandBuffer)
209 {
210 struct radv_cmd_buffer *cmd_buffer;
211 unsigned ring;
212 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
213 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
214 if (cmd_buffer == NULL)
215 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
216
217 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
218 cmd_buffer->device = device;
219 cmd_buffer->pool = pool;
220 cmd_buffer->level = level;
221
222 if (pool) {
223 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
224 cmd_buffer->queue_family_index = pool->queue_family_index;
225
226 } else {
227 /* Init the pool_link so we can safefly call list_del when we destroy
228 * the command buffer
229 */
230 list_inithead(&cmd_buffer->pool_link);
231 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
232 }
233
234 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
235
236 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
237 if (!cmd_buffer->cs) {
238 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
239 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
240 }
241
242 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
243
244 list_inithead(&cmd_buffer->upload.list);
245
246 return VK_SUCCESS;
247 }
248
249 static void
250 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
251 {
252 list_del(&cmd_buffer->pool_link);
253
254 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
255 &cmd_buffer->upload.list, list) {
256 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
257 list_del(&up->list);
258 free(up);
259 }
260
261 if (cmd_buffer->upload.upload_bo)
262 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
263 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
264 free(cmd_buffer->push_descriptors.set.mapped_ptr);
265 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
266 }
267
268 static VkResult
269 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
270 {
271
272 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
273
274 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
275 &cmd_buffer->upload.list, list) {
276 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
277 list_del(&up->list);
278 free(up);
279 }
280
281 cmd_buffer->push_constant_stages = 0;
282 cmd_buffer->scratch_size_needed = 0;
283 cmd_buffer->compute_scratch_size_needed = 0;
284 cmd_buffer->esgs_ring_size_needed = 0;
285 cmd_buffer->gsvs_ring_size_needed = 0;
286 cmd_buffer->tess_rings_needed = false;
287 cmd_buffer->sample_positions_needed = false;
288
289 if (cmd_buffer->upload.upload_bo)
290 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
291 cmd_buffer->upload.upload_bo, 8);
292 cmd_buffer->upload.offset = 0;
293
294 cmd_buffer->record_result = VK_SUCCESS;
295
296 cmd_buffer->ring_offsets_idx = -1;
297
298 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
299 void *fence_ptr;
300 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
301 &cmd_buffer->gfx9_fence_offset,
302 &fence_ptr);
303 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
304 }
305
306 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
307
308 return cmd_buffer->record_result;
309 }
310
311 static bool
312 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
313 uint64_t min_needed)
314 {
315 uint64_t new_size;
316 struct radeon_winsys_bo *bo;
317 struct radv_cmd_buffer_upload *upload;
318 struct radv_device *device = cmd_buffer->device;
319
320 new_size = MAX2(min_needed, 16 * 1024);
321 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
322
323 bo = device->ws->buffer_create(device->ws,
324 new_size, 4096,
325 RADEON_DOMAIN_GTT,
326 RADEON_FLAG_CPU_ACCESS|
327 RADEON_FLAG_NO_INTERPROCESS_SHARING);
328
329 if (!bo) {
330 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
331 return false;
332 }
333
334 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
335 if (cmd_buffer->upload.upload_bo) {
336 upload = malloc(sizeof(*upload));
337
338 if (!upload) {
339 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
340 device->ws->buffer_destroy(bo);
341 return false;
342 }
343
344 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
345 list_add(&upload->list, &cmd_buffer->upload.list);
346 }
347
348 cmd_buffer->upload.upload_bo = bo;
349 cmd_buffer->upload.size = new_size;
350 cmd_buffer->upload.offset = 0;
351 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
352
353 if (!cmd_buffer->upload.map) {
354 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
355 return false;
356 }
357
358 return true;
359 }
360
361 bool
362 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
363 unsigned size,
364 unsigned alignment,
365 unsigned *out_offset,
366 void **ptr)
367 {
368 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
369 if (offset + size > cmd_buffer->upload.size) {
370 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
371 return false;
372 offset = 0;
373 }
374
375 *out_offset = offset;
376 *ptr = cmd_buffer->upload.map + offset;
377
378 cmd_buffer->upload.offset = offset + size;
379 return true;
380 }
381
382 bool
383 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
384 unsigned size, unsigned alignment,
385 const void *data, unsigned *out_offset)
386 {
387 uint8_t *ptr;
388
389 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
390 out_offset, (void **)&ptr))
391 return false;
392
393 if (ptr)
394 memcpy(ptr, data, size);
395
396 return true;
397 }
398
399 static void
400 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
401 unsigned count, const uint32_t *data)
402 {
403 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
404 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
405 S_370_WR_CONFIRM(1) |
406 S_370_ENGINE_SEL(V_370_ME));
407 radeon_emit(cs, va);
408 radeon_emit(cs, va >> 32);
409 radeon_emit_array(cs, data, count);
410 }
411
412 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
413 {
414 struct radv_device *device = cmd_buffer->device;
415 struct radeon_winsys_cs *cs = cmd_buffer->cs;
416 uint64_t va;
417
418 va = radv_buffer_get_va(device->trace_bo);
419 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
420 va += 4;
421
422 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
423
424 ++cmd_buffer->state.trace_id;
425 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
426 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
427 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
428 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
429 }
430
431 static void
432 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
433 enum radv_cmd_flush_bits flags)
434 {
435 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
436 uint32_t *ptr = NULL;
437 uint64_t va = 0;
438
439 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
440 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
441
442 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
443 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
444 cmd_buffer->gfx9_fence_offset;
445 ptr = &cmd_buffer->gfx9_fence_idx;
446 }
447
448 /* Force wait for graphics or compute engines to be idle. */
449 si_cs_emit_cache_flush(cmd_buffer->cs,
450 cmd_buffer->device->physical_device->rad_info.chip_class,
451 ptr, va,
452 radv_cmd_buffer_uses_mec(cmd_buffer),
453 flags);
454 }
455
456 if (unlikely(cmd_buffer->device->trace_bo))
457 radv_cmd_buffer_trace_emit(cmd_buffer);
458 }
459
460 static void
461 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
462 struct radv_pipeline *pipeline, enum ring_type ring)
463 {
464 struct radv_device *device = cmd_buffer->device;
465 struct radeon_winsys_cs *cs = cmd_buffer->cs;
466 uint32_t data[2];
467 uint64_t va;
468
469 va = radv_buffer_get_va(device->trace_bo);
470
471 switch (ring) {
472 case RING_GFX:
473 va += 8;
474 break;
475 case RING_COMPUTE:
476 va += 16;
477 break;
478 default:
479 assert(!"invalid ring type");
480 }
481
482 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
483 cmd_buffer->cs, 6);
484
485 data[0] = (uintptr_t)pipeline;
486 data[1] = (uintptr_t)pipeline >> 32;
487
488 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
489 radv_emit_write_data_packet(cs, va, 2, data);
490 }
491
492 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
493 struct radv_descriptor_set *set,
494 unsigned idx)
495 {
496 cmd_buffer->descriptors[idx] = set;
497 if (set)
498 cmd_buffer->state.valid_descriptors |= (1u << idx);
499 else
500 cmd_buffer->state.valid_descriptors &= ~(1u << idx);
501 cmd_buffer->state.descriptors_dirty |= (1u << idx);
502
503 }
504
505 static void
506 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer)
507 {
508 struct radv_device *device = cmd_buffer->device;
509 struct radeon_winsys_cs *cs = cmd_buffer->cs;
510 uint32_t data[MAX_SETS * 2] = {};
511 uint64_t va;
512 unsigned i;
513 va = radv_buffer_get_va(device->trace_bo) + 24;
514
515 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
516 cmd_buffer->cs, 4 + MAX_SETS * 2);
517
518 for_each_bit(i, cmd_buffer->state.valid_descriptors) {
519 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
520 data[i * 2] = (uintptr_t)set;
521 data[i * 2 + 1] = (uintptr_t)set >> 32;
522 }
523
524 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
525 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
526 }
527
528 struct ac_userdata_info *
529 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
530 gl_shader_stage stage,
531 int idx)
532 {
533 if (stage == MESA_SHADER_VERTEX) {
534 if (pipeline->shaders[MESA_SHADER_VERTEX])
535 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.user_sgprs_locs.shader_data[idx];
536 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
537 return &pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx];
538 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
539 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
540 } else if (stage == MESA_SHADER_TESS_EVAL) {
541 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
542 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.user_sgprs_locs.shader_data[idx];
543 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
544 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
545 }
546 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
547 }
548
549 static void
550 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
551 struct radv_pipeline *pipeline,
552 gl_shader_stage stage,
553 int idx, uint64_t va)
554 {
555 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
556 uint32_t base_reg = pipeline->user_data_0[stage];
557 if (loc->sgpr_idx == -1)
558 return;
559 assert(loc->num_sgprs == 2);
560 assert(!loc->indirect);
561 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
562 radeon_emit(cmd_buffer->cs, va);
563 radeon_emit(cmd_buffer->cs, va >> 32);
564 }
565
566 static void
567 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
568 struct radv_pipeline *pipeline)
569 {
570 int num_samples = pipeline->graphics.ms.num_samples;
571 struct radv_multisample_state *ms = &pipeline->graphics.ms;
572 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
573
574 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
575 cmd_buffer->sample_positions_needed = true;
576
577 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
578 return;
579
580 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
581 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
582 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
583
584 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
585
586 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
587
588 /* GFX9: Flush DFSM when the AA mode changes. */
589 if (cmd_buffer->device->dfsm_allowed) {
590 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
591 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
592 }
593 }
594
595
596
597 static inline void
598 radv_emit_prefetch_TC_L2_async(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
599 unsigned size)
600 {
601 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
602 si_cp_dma_prefetch(cmd_buffer, va, size);
603 }
604
605 static void
606 radv_emit_VBO_descriptors_prefetch(struct radv_cmd_buffer *cmd_buffer)
607 {
608 if (cmd_buffer->state.vb_prefetch_dirty) {
609 radv_emit_prefetch_TC_L2_async(cmd_buffer,
610 cmd_buffer->state.vb_va,
611 cmd_buffer->state.vb_size);
612 cmd_buffer->state.vb_prefetch_dirty = false;
613 }
614 }
615
616 static void
617 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
618 struct radv_shader_variant *shader)
619 {
620 struct radeon_winsys *ws = cmd_buffer->device->ws;
621 struct radeon_winsys_cs *cs = cmd_buffer->cs;
622 uint64_t va;
623
624 if (!shader)
625 return;
626
627 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
628
629 radv_cs_add_buffer(ws, cs, shader->bo, 8);
630 radv_emit_prefetch_TC_L2_async(cmd_buffer, va, shader->code_size);
631 }
632
633 static void
634 radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer,
635 struct radv_pipeline *pipeline)
636 {
637 radv_emit_shader_prefetch(cmd_buffer,
638 pipeline->shaders[MESA_SHADER_VERTEX]);
639 radv_emit_VBO_descriptors_prefetch(cmd_buffer);
640 radv_emit_shader_prefetch(cmd_buffer,
641 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
642 radv_emit_shader_prefetch(cmd_buffer,
643 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
644 radv_emit_shader_prefetch(cmd_buffer,
645 pipeline->shaders[MESA_SHADER_GEOMETRY]);
646 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
647 radv_emit_shader_prefetch(cmd_buffer,
648 pipeline->shaders[MESA_SHADER_FRAGMENT]);
649 }
650
651 static void
652 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
653 {
654 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
655
656 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
657 return;
658
659 radv_update_multisample_state(cmd_buffer, pipeline);
660
661 cmd_buffer->scratch_size_needed =
662 MAX2(cmd_buffer->scratch_size_needed,
663 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
664
665 if (!cmd_buffer->state.emitted_pipeline ||
666 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
667 pipeline->graphics.can_use_guardband)
668 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
669
670 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
671
672 if (unlikely(cmd_buffer->device->trace_bo))
673 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
674
675 cmd_buffer->state.emitted_pipeline = pipeline;
676
677 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
678 }
679
680 static void
681 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
682 {
683 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
684 cmd_buffer->state.dynamic.viewport.viewports);
685 }
686
687 static void
688 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
689 {
690 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
691
692 /* Vega10/Raven scissor bug workaround. This must be done before VPORT
693 * scissor registers are changed. There is also a more efficient but
694 * more involved alternative workaround.
695 */
696 if (cmd_buffer->device->physical_device->has_scissor_bug) {
697 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
698 si_emit_cache_flush(cmd_buffer);
699 }
700 si_write_scissors(cmd_buffer->cs, 0, count,
701 cmd_buffer->state.dynamic.scissor.scissors,
702 cmd_buffer->state.dynamic.viewport.viewports,
703 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
704 }
705
706 static void
707 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
708 {
709 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
710 return;
711
712 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
713 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
714 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
715 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
716 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
717 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
718 S_028214_BR_Y(rect.offset.y + rect.extent.height));
719 }
720 }
721
722 static void
723 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
724 {
725 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
726
727 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
728 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
729 }
730
731 static void
732 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
733 {
734 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
735
736 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
737 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
738 }
739
740 static void
741 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
742 {
743 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
744
745 radeon_set_context_reg_seq(cmd_buffer->cs,
746 R_028430_DB_STENCILREFMASK, 2);
747 radeon_emit(cmd_buffer->cs,
748 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
749 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
750 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
751 S_028430_STENCILOPVAL(1));
752 radeon_emit(cmd_buffer->cs,
753 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
754 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
755 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
756 S_028434_STENCILOPVAL_BF(1));
757 }
758
759 static void
760 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
761 {
762 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
763
764 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
765 fui(d->depth_bounds.min));
766 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
767 fui(d->depth_bounds.max));
768 }
769
770 static void
771 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
772 {
773 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
774 unsigned slope = fui(d->depth_bias.slope * 16.0f);
775 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
776
777
778 radeon_set_context_reg_seq(cmd_buffer->cs,
779 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
780 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
781 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
782 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
783 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
784 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
785 }
786
787 static void
788 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
789 int index,
790 struct radv_attachment_info *att,
791 struct radv_image *image,
792 VkImageLayout layout)
793 {
794 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
795 struct radv_color_buffer_info *cb = &att->cb;
796 uint32_t cb_color_info = cb->cb_color_info;
797
798 if (!radv_layout_dcc_compressed(image, layout,
799 radv_image_queue_family_mask(image,
800 cmd_buffer->queue_family_index,
801 cmd_buffer->queue_family_index))) {
802 cb_color_info &= C_028C70_DCC_ENABLE;
803 }
804
805 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
806 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
807 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
808 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
809 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
810 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
811 radeon_emit(cmd_buffer->cs, cb_color_info);
812 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
813 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
814 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
815 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
816 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
817 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
818
819 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
820 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
821 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
822
823 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
824 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
825 } else {
826 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
827 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
828 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
829 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
830 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
831 radeon_emit(cmd_buffer->cs, cb_color_info);
832 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
833 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
834 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
835 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
836 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
837 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
838
839 if (is_vi) { /* DCC BASE */
840 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
841 }
842 }
843 }
844
845 static void
846 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
847 struct radv_ds_buffer_info *ds,
848 struct radv_image *image,
849 VkImageLayout layout)
850 {
851 uint32_t db_z_info = ds->db_z_info;
852 uint32_t db_stencil_info = ds->db_stencil_info;
853
854 if (!radv_layout_has_htile(image, layout,
855 radv_image_queue_family_mask(image,
856 cmd_buffer->queue_family_index,
857 cmd_buffer->queue_family_index))) {
858 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
859 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
860 }
861
862 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
863 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
864
865
866 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
867 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
868 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
869 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
870 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
871
872 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
873 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
874 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
875 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
876 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); /* DB_Z_READ_BASE_HI */
877 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
878 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
879 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
880 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
881 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
882 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
883
884 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
885 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
886 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
887 } else {
888 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
889
890 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
891 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
892 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
893 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
894 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
895 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
896 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
897 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
898 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
899 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
900
901 }
902
903 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
904 ds->pa_su_poly_offset_db_fmt_cntl);
905 }
906
907 void
908 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
909 struct radv_image *image,
910 VkClearDepthStencilValue ds_clear_value,
911 VkImageAspectFlags aspects)
912 {
913 uint64_t va = radv_buffer_get_va(image->bo);
914 va += image->offset + image->clear_value_offset;
915 unsigned reg_offset = 0, reg_count = 0;
916
917 assert(image->surface.htile_size);
918
919 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
920 ++reg_count;
921 } else {
922 ++reg_offset;
923 va += 4;
924 }
925 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
926 ++reg_count;
927
928 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
929 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
930 S_370_WR_CONFIRM(1) |
931 S_370_ENGINE_SEL(V_370_PFP));
932 radeon_emit(cmd_buffer->cs, va);
933 radeon_emit(cmd_buffer->cs, va >> 32);
934 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
935 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
936 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
937 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
938
939 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
940 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
941 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
942 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
943 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
944 }
945
946 static void
947 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
948 struct radv_image *image)
949 {
950 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
951 uint64_t va = radv_buffer_get_va(image->bo);
952 va += image->offset + image->clear_value_offset;
953 unsigned reg_offset = 0, reg_count = 0;
954
955 if (!image->surface.htile_size)
956 return;
957
958 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
959 ++reg_count;
960 } else {
961 ++reg_offset;
962 va += 4;
963 }
964 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
965 ++reg_count;
966
967 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
968 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
969 COPY_DATA_DST_SEL(COPY_DATA_REG) |
970 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
971 radeon_emit(cmd_buffer->cs, va);
972 radeon_emit(cmd_buffer->cs, va >> 32);
973 radeon_emit(cmd_buffer->cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
974 radeon_emit(cmd_buffer->cs, 0);
975
976 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
977 radeon_emit(cmd_buffer->cs, 0);
978 }
979
980 /*
981 *with DCC some colors don't require CMASK elimiation before being
982 * used as a texture. This sets a predicate value to determine if the
983 * cmask eliminate is required.
984 */
985 void
986 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
987 struct radv_image *image,
988 bool value)
989 {
990 uint64_t pred_val = value;
991 uint64_t va = radv_buffer_get_va(image->bo);
992 va += image->offset + image->dcc_pred_offset;
993
994 assert(image->surface.dcc_size);
995
996 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
997 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
998 S_370_WR_CONFIRM(1) |
999 S_370_ENGINE_SEL(V_370_PFP));
1000 radeon_emit(cmd_buffer->cs, va);
1001 radeon_emit(cmd_buffer->cs, va >> 32);
1002 radeon_emit(cmd_buffer->cs, pred_val);
1003 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1004 }
1005
1006 void
1007 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1008 struct radv_image *image,
1009 int idx,
1010 uint32_t color_values[2])
1011 {
1012 uint64_t va = radv_buffer_get_va(image->bo);
1013 va += image->offset + image->clear_value_offset;
1014
1015 assert(image->cmask.size || image->surface.dcc_size);
1016
1017 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1018 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1019 S_370_WR_CONFIRM(1) |
1020 S_370_ENGINE_SEL(V_370_PFP));
1021 radeon_emit(cmd_buffer->cs, va);
1022 radeon_emit(cmd_buffer->cs, va >> 32);
1023 radeon_emit(cmd_buffer->cs, color_values[0]);
1024 radeon_emit(cmd_buffer->cs, color_values[1]);
1025
1026 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1027 radeon_emit(cmd_buffer->cs, color_values[0]);
1028 radeon_emit(cmd_buffer->cs, color_values[1]);
1029 }
1030
1031 static void
1032 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1033 struct radv_image *image,
1034 int idx)
1035 {
1036 uint64_t va = radv_buffer_get_va(image->bo);
1037 va += image->offset + image->clear_value_offset;
1038
1039 if (!image->cmask.size && !image->surface.dcc_size)
1040 return;
1041
1042 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1043
1044 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1045 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1046 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1047 COPY_DATA_COUNT_SEL);
1048 radeon_emit(cmd_buffer->cs, va);
1049 radeon_emit(cmd_buffer->cs, va >> 32);
1050 radeon_emit(cmd_buffer->cs, reg >> 2);
1051 radeon_emit(cmd_buffer->cs, 0);
1052
1053 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1054 radeon_emit(cmd_buffer->cs, 0);
1055 }
1056
1057 static void
1058 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1059 {
1060 int i;
1061 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1062 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1063
1064 /* this may happen for inherited secondary recording */
1065 if (!framebuffer)
1066 return;
1067
1068 for (i = 0; i < 8; ++i) {
1069 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1070 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1071 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1072 continue;
1073 }
1074
1075 int idx = subpass->color_attachments[i].attachment;
1076 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1077 struct radv_image *image = att->attachment->image;
1078 VkImageLayout layout = subpass->color_attachments[i].layout;
1079
1080 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1081
1082 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1083 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1084
1085 radv_load_color_clear_regs(cmd_buffer, image, i);
1086 }
1087
1088 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1089 int idx = subpass->depth_stencil_attachment.attachment;
1090 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1091 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1092 struct radv_image *image = att->attachment->image;
1093 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1094 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1095 cmd_buffer->queue_family_index,
1096 cmd_buffer->queue_family_index);
1097 /* We currently don't support writing decompressed HTILE */
1098 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1099 radv_layout_is_htile_compressed(image, layout, queue_mask));
1100
1101 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1102
1103 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1104 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1105 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1106 }
1107 radv_load_depth_clear_regs(cmd_buffer, image);
1108 } else {
1109 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1110 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1111 else
1112 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1113
1114 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1115 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1116 }
1117 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1118 S_028208_BR_X(framebuffer->width) |
1119 S_028208_BR_Y(framebuffer->height));
1120
1121 if (cmd_buffer->device->dfsm_allowed) {
1122 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1123 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1124 }
1125
1126 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1127 }
1128
1129 static void
1130 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1131 {
1132 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1133 struct radv_cmd_state *state = &cmd_buffer->state;
1134
1135 if (state->index_type != state->last_index_type) {
1136 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1137 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1138 2, state->index_type);
1139 } else {
1140 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1141 radeon_emit(cs, state->index_type);
1142 }
1143
1144 state->last_index_type = state->index_type;
1145 }
1146
1147 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1148 radeon_emit(cs, state->index_va);
1149 radeon_emit(cs, state->index_va >> 32);
1150
1151 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1152 radeon_emit(cs, state->max_index_count);
1153
1154 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1155 }
1156
1157 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1158 {
1159 uint32_t db_count_control;
1160
1161 if(!cmd_buffer->state.active_occlusion_queries) {
1162 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1163 db_count_control = 0;
1164 } else {
1165 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1166 }
1167 } else {
1168 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1169 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1170 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1171 S_028004_ZPASS_ENABLE(1) |
1172 S_028004_SLICE_EVEN_ENABLE(1) |
1173 S_028004_SLICE_ODD_ENABLE(1);
1174 } else {
1175 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1176 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1177 }
1178 }
1179
1180 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1181 }
1182
1183 static void
1184 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1185 {
1186 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1187
1188 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1189 radv_emit_viewport(cmd_buffer);
1190
1191 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1192 radv_emit_scissor(cmd_buffer);
1193
1194 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1195 radv_emit_line_width(cmd_buffer);
1196
1197 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1198 radv_emit_blend_constants(cmd_buffer);
1199
1200 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1201 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1202 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1203 radv_emit_stencil(cmd_buffer);
1204
1205 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1206 radv_emit_depth_bounds(cmd_buffer);
1207
1208 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1209 radv_emit_depth_bias(cmd_buffer);
1210
1211 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1212 radv_emit_discard_rectangle(cmd_buffer);
1213
1214 cmd_buffer->state.dirty &= ~states;
1215 }
1216
1217 static void
1218 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1219 struct radv_pipeline *pipeline,
1220 int idx,
1221 uint64_t va,
1222 gl_shader_stage stage)
1223 {
1224 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1225 uint32_t base_reg = pipeline->user_data_0[stage];
1226
1227 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1228 return;
1229
1230 assert(!desc_set_loc->indirect);
1231 assert(desc_set_loc->num_sgprs == 2);
1232 radeon_set_sh_reg_seq(cmd_buffer->cs,
1233 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1234 radeon_emit(cmd_buffer->cs, va);
1235 radeon_emit(cmd_buffer->cs, va >> 32);
1236 }
1237
1238 static void
1239 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1240 VkShaderStageFlags stages,
1241 struct radv_descriptor_set *set,
1242 unsigned idx)
1243 {
1244 if (cmd_buffer->state.pipeline) {
1245 radv_foreach_stage(stage, stages) {
1246 if (cmd_buffer->state.pipeline->shaders[stage])
1247 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1248 idx, set->va,
1249 stage);
1250 }
1251 }
1252
1253 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1254 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1255 idx, set->va,
1256 MESA_SHADER_COMPUTE);
1257 }
1258
1259 static void
1260 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1261 {
1262 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1263 unsigned bo_offset;
1264
1265 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1266 set->mapped_ptr,
1267 &bo_offset))
1268 return;
1269
1270 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1271 set->va += bo_offset;
1272 }
1273
1274 static void
1275 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1276 {
1277 uint32_t size = MAX_SETS * 2 * 4;
1278 uint32_t offset;
1279 void *ptr;
1280
1281 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1282 256, &offset, &ptr))
1283 return;
1284
1285 for (unsigned i = 0; i < MAX_SETS; i++) {
1286 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1287 uint64_t set_va = 0;
1288 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
1289 if (cmd_buffer->state.valid_descriptors & (1u << i))
1290 set_va = set->va;
1291 uptr[0] = set_va & 0xffffffff;
1292 uptr[1] = set_va >> 32;
1293 }
1294
1295 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1296 va += offset;
1297
1298 if (cmd_buffer->state.pipeline) {
1299 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1300 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1301 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1302
1303 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1304 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1305 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1306
1307 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1308 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1309 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1310
1311 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1312 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1313 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1314
1315 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1316 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1317 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1318 }
1319
1320 if (cmd_buffer->state.compute_pipeline)
1321 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1322 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1323 }
1324
1325 static void
1326 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1327 VkShaderStageFlags stages)
1328 {
1329 unsigned i;
1330
1331 if (!cmd_buffer->state.descriptors_dirty)
1332 return;
1333
1334 if (cmd_buffer->state.push_descriptors_dirty)
1335 radv_flush_push_descriptors(cmd_buffer);
1336
1337 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1338 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1339 radv_flush_indirect_descriptor_sets(cmd_buffer);
1340 }
1341
1342 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1343 cmd_buffer->cs,
1344 MAX_SETS * MESA_SHADER_STAGES * 4);
1345
1346 for_each_bit(i, cmd_buffer->state.descriptors_dirty) {
1347 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
1348 if (!(cmd_buffer->state.valid_descriptors & (1u << i)))
1349 continue;
1350
1351 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1352 }
1353 cmd_buffer->state.descriptors_dirty = 0;
1354 cmd_buffer->state.push_descriptors_dirty = false;
1355
1356 if (unlikely(cmd_buffer->device->trace_bo))
1357 radv_save_descriptors(cmd_buffer);
1358
1359 assert(cmd_buffer->cs->cdw <= cdw_max);
1360 }
1361
1362 static void
1363 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1364 struct radv_pipeline *pipeline,
1365 VkShaderStageFlags stages)
1366 {
1367 struct radv_pipeline_layout *layout = pipeline->layout;
1368 unsigned offset;
1369 void *ptr;
1370 uint64_t va;
1371
1372 stages &= cmd_buffer->push_constant_stages;
1373 if (!stages ||
1374 (!layout->push_constant_size && !layout->dynamic_offset_count))
1375 return;
1376
1377 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1378 16 * layout->dynamic_offset_count,
1379 256, &offset, &ptr))
1380 return;
1381
1382 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1383 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1384 16 * layout->dynamic_offset_count);
1385
1386 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1387 va += offset;
1388
1389 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1390 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1391
1392 radv_foreach_stage(stage, stages) {
1393 if (pipeline->shaders[stage]) {
1394 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1395 AC_UD_PUSH_CONSTANTS, va);
1396 }
1397 }
1398
1399 cmd_buffer->push_constant_stages &= ~stages;
1400 assert(cmd_buffer->cs->cdw <= cdw_max);
1401 }
1402
1403 static bool
1404 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1405 {
1406 if ((pipeline_is_dirty ||
1407 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1408 cmd_buffer->state.pipeline->vertex_elements.count &&
1409 radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers) {
1410 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1411 unsigned vb_offset;
1412 void *vb_ptr;
1413 uint32_t i = 0;
1414 uint32_t count = velems->count;
1415 uint64_t va;
1416
1417 /* allocate some descriptor state for vertex buffers */
1418 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1419 &vb_offset, &vb_ptr))
1420 return false;
1421
1422 for (i = 0; i < count; i++) {
1423 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1424 uint32_t offset;
1425 int vb = velems->binding[i];
1426 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1427 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1428
1429 va = radv_buffer_get_va(buffer->bo);
1430
1431 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1432 va += offset + buffer->offset;
1433 desc[0] = va;
1434 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1435 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1436 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1437 else
1438 desc[2] = buffer->size - offset;
1439 desc[3] = velems->rsrc_word3[i];
1440 }
1441
1442 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1443 va += vb_offset;
1444
1445 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1446 AC_UD_VS_VERTEX_BUFFERS, va);
1447
1448 cmd_buffer->state.vb_va = va;
1449 cmd_buffer->state.vb_size = count * 16;
1450 cmd_buffer->state.vb_prefetch_dirty = true;
1451 }
1452 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1453
1454 return true;
1455 }
1456
1457 static bool
1458 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1459 {
1460 if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer, pipeline_is_dirty))
1461 return false;
1462
1463 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1464 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1465 VK_SHADER_STAGE_ALL_GRAPHICS);
1466
1467 return true;
1468 }
1469
1470 static void
1471 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1472 bool instanced_draw, bool indirect_draw,
1473 uint32_t draw_vertex_count)
1474 {
1475 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1476 struct radv_cmd_state *state = &cmd_buffer->state;
1477 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1478 uint32_t ia_multi_vgt_param;
1479 int32_t primitive_reset_en;
1480
1481 /* Draw state. */
1482 ia_multi_vgt_param =
1483 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1484 indirect_draw, draw_vertex_count);
1485
1486 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1487 if (info->chip_class >= GFX9) {
1488 radeon_set_uconfig_reg_idx(cs,
1489 R_030960_IA_MULTI_VGT_PARAM,
1490 4, ia_multi_vgt_param);
1491 } else if (info->chip_class >= CIK) {
1492 radeon_set_context_reg_idx(cs,
1493 R_028AA8_IA_MULTI_VGT_PARAM,
1494 1, ia_multi_vgt_param);
1495 } else {
1496 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1497 ia_multi_vgt_param);
1498 }
1499 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1500 }
1501
1502 /* Primitive restart. */
1503 primitive_reset_en =
1504 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1505
1506 if (primitive_reset_en != state->last_primitive_reset_en) {
1507 state->last_primitive_reset_en = primitive_reset_en;
1508 if (info->chip_class >= GFX9) {
1509 radeon_set_uconfig_reg(cs,
1510 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1511 primitive_reset_en);
1512 } else {
1513 radeon_set_context_reg(cs,
1514 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1515 primitive_reset_en);
1516 }
1517 }
1518
1519 if (primitive_reset_en) {
1520 uint32_t primitive_reset_index =
1521 state->index_type ? 0xffffffffu : 0xffffu;
1522
1523 if (primitive_reset_index != state->last_primitive_reset_index) {
1524 radeon_set_context_reg(cs,
1525 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1526 primitive_reset_index);
1527 state->last_primitive_reset_index = primitive_reset_index;
1528 }
1529 }
1530 }
1531
1532 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1533 VkPipelineStageFlags src_stage_mask)
1534 {
1535 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1536 VK_PIPELINE_STAGE_TRANSFER_BIT |
1537 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1538 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1539 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1540 }
1541
1542 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1543 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1544 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1545 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1546 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1547 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1548 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1549 VK_PIPELINE_STAGE_TRANSFER_BIT |
1550 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1551 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1552 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1553 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1554 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1555 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1556 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1557 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1558 }
1559 }
1560
1561 static enum radv_cmd_flush_bits
1562 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1563 VkAccessFlags src_flags)
1564 {
1565 enum radv_cmd_flush_bits flush_bits = 0;
1566 uint32_t b;
1567 for_each_bit(b, src_flags) {
1568 switch ((VkAccessFlagBits)(1 << b)) {
1569 case VK_ACCESS_SHADER_WRITE_BIT:
1570 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1571 break;
1572 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1573 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1574 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1575 break;
1576 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1577 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1578 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1579 break;
1580 case VK_ACCESS_TRANSFER_WRITE_BIT:
1581 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1582 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1583 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1584 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1585 RADV_CMD_FLAG_INV_GLOBAL_L2;
1586 break;
1587 default:
1588 break;
1589 }
1590 }
1591 return flush_bits;
1592 }
1593
1594 static enum radv_cmd_flush_bits
1595 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1596 VkAccessFlags dst_flags,
1597 struct radv_image *image)
1598 {
1599 enum radv_cmd_flush_bits flush_bits = 0;
1600 uint32_t b;
1601 for_each_bit(b, dst_flags) {
1602 switch ((VkAccessFlagBits)(1 << b)) {
1603 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1604 case VK_ACCESS_INDEX_READ_BIT:
1605 break;
1606 case VK_ACCESS_UNIFORM_READ_BIT:
1607 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1608 break;
1609 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1610 case VK_ACCESS_SHADER_READ_BIT:
1611 case VK_ACCESS_TRANSFER_READ_BIT:
1612 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1613 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1614 RADV_CMD_FLAG_INV_GLOBAL_L2;
1615 break;
1616 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1617 /* TODO: change to image && when the image gets passed
1618 * through from the subpass. */
1619 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1620 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1621 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1622 break;
1623 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1624 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1625 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1626 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1627 break;
1628 default:
1629 break;
1630 }
1631 }
1632 return flush_bits;
1633 }
1634
1635 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1636 {
1637 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1638 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1639 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1640 NULL);
1641 }
1642
1643 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1644 VkAttachmentReference att)
1645 {
1646 unsigned idx = att.attachment;
1647 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1648 VkImageSubresourceRange range;
1649 range.aspectMask = 0;
1650 range.baseMipLevel = view->base_mip;
1651 range.levelCount = 1;
1652 range.baseArrayLayer = view->base_layer;
1653 range.layerCount = cmd_buffer->state.framebuffer->layers;
1654
1655 radv_handle_image_transition(cmd_buffer,
1656 view->image,
1657 cmd_buffer->state.attachments[idx].current_layout,
1658 att.layout, 0, 0, &range,
1659 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1660
1661 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1662
1663
1664 }
1665
1666 void
1667 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1668 const struct radv_subpass *subpass, bool transitions)
1669 {
1670 if (transitions) {
1671 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1672
1673 for (unsigned i = 0; i < subpass->color_count; ++i) {
1674 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
1675 radv_handle_subpass_image_transition(cmd_buffer,
1676 subpass->color_attachments[i]);
1677 }
1678
1679 for (unsigned i = 0; i < subpass->input_count; ++i) {
1680 radv_handle_subpass_image_transition(cmd_buffer,
1681 subpass->input_attachments[i]);
1682 }
1683
1684 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1685 radv_handle_subpass_image_transition(cmd_buffer,
1686 subpass->depth_stencil_attachment);
1687 }
1688 }
1689
1690 cmd_buffer->state.subpass = subpass;
1691
1692 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
1693 }
1694
1695 static VkResult
1696 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1697 struct radv_render_pass *pass,
1698 const VkRenderPassBeginInfo *info)
1699 {
1700 struct radv_cmd_state *state = &cmd_buffer->state;
1701
1702 if (pass->attachment_count == 0) {
1703 state->attachments = NULL;
1704 return VK_SUCCESS;
1705 }
1706
1707 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1708 pass->attachment_count *
1709 sizeof(state->attachments[0]),
1710 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1711 if (state->attachments == NULL) {
1712 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
1713 return cmd_buffer->record_result;
1714 }
1715
1716 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1717 struct radv_render_pass_attachment *att = &pass->attachments[i];
1718 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1719 VkImageAspectFlags clear_aspects = 0;
1720
1721 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1722 /* color attachment */
1723 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1724 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1725 }
1726 } else {
1727 /* depthstencil attachment */
1728 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1729 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1730 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1731 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1732 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
1733 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1734 }
1735 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1736 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1737 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1738 }
1739 }
1740
1741 state->attachments[i].pending_clear_aspects = clear_aspects;
1742 state->attachments[i].cleared_views = 0;
1743 if (clear_aspects && info) {
1744 assert(info->clearValueCount > i);
1745 state->attachments[i].clear_value = info->pClearValues[i];
1746 }
1747
1748 state->attachments[i].current_layout = att->initial_layout;
1749 }
1750
1751 return VK_SUCCESS;
1752 }
1753
1754 VkResult radv_AllocateCommandBuffers(
1755 VkDevice _device,
1756 const VkCommandBufferAllocateInfo *pAllocateInfo,
1757 VkCommandBuffer *pCommandBuffers)
1758 {
1759 RADV_FROM_HANDLE(radv_device, device, _device);
1760 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1761
1762 VkResult result = VK_SUCCESS;
1763 uint32_t i;
1764
1765 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1766
1767 if (!list_empty(&pool->free_cmd_buffers)) {
1768 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1769
1770 list_del(&cmd_buffer->pool_link);
1771 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1772
1773 result = radv_reset_cmd_buffer(cmd_buffer);
1774 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1775 cmd_buffer->level = pAllocateInfo->level;
1776
1777 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
1778 } else {
1779 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1780 &pCommandBuffers[i]);
1781 }
1782 if (result != VK_SUCCESS)
1783 break;
1784 }
1785
1786 if (result != VK_SUCCESS) {
1787 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1788 i, pCommandBuffers);
1789
1790 /* From the Vulkan 1.0.66 spec:
1791 *
1792 * "vkAllocateCommandBuffers can be used to create multiple
1793 * command buffers. If the creation of any of those command
1794 * buffers fails, the implementation must destroy all
1795 * successfully created command buffer objects from this
1796 * command, set all entries of the pCommandBuffers array to
1797 * NULL and return the error."
1798 */
1799 memset(pCommandBuffers, 0,
1800 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
1801 }
1802
1803 return result;
1804 }
1805
1806 void radv_FreeCommandBuffers(
1807 VkDevice device,
1808 VkCommandPool commandPool,
1809 uint32_t commandBufferCount,
1810 const VkCommandBuffer *pCommandBuffers)
1811 {
1812 for (uint32_t i = 0; i < commandBufferCount; i++) {
1813 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1814
1815 if (cmd_buffer) {
1816 if (cmd_buffer->pool) {
1817 list_del(&cmd_buffer->pool_link);
1818 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
1819 } else
1820 radv_cmd_buffer_destroy(cmd_buffer);
1821
1822 }
1823 }
1824 }
1825
1826 VkResult radv_ResetCommandBuffer(
1827 VkCommandBuffer commandBuffer,
1828 VkCommandBufferResetFlags flags)
1829 {
1830 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1831 return radv_reset_cmd_buffer(cmd_buffer);
1832 }
1833
1834 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
1835 {
1836 struct radv_device *device = cmd_buffer->device;
1837 if (device->gfx_init) {
1838 uint64_t va = radv_buffer_get_va(device->gfx_init);
1839 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8);
1840 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
1841 radeon_emit(cmd_buffer->cs, va);
1842 radeon_emit(cmd_buffer->cs, va >> 32);
1843 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
1844 } else
1845 si_init_config(cmd_buffer);
1846 }
1847
1848 VkResult radv_BeginCommandBuffer(
1849 VkCommandBuffer commandBuffer,
1850 const VkCommandBufferBeginInfo *pBeginInfo)
1851 {
1852 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1853 VkResult result = VK_SUCCESS;
1854
1855 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
1856 /* If the command buffer has already been resetted with
1857 * vkResetCommandBuffer, no need to do it again.
1858 */
1859 result = radv_reset_cmd_buffer(cmd_buffer);
1860 if (result != VK_SUCCESS)
1861 return result;
1862 }
1863
1864 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1865 cmd_buffer->state.last_primitive_reset_en = -1;
1866 cmd_buffer->state.last_index_type = -1;
1867 cmd_buffer->state.last_num_instances = -1;
1868 cmd_buffer->state.last_vertex_offset = -1;
1869 cmd_buffer->state.last_first_instance = -1;
1870 cmd_buffer->usage_flags = pBeginInfo->flags;
1871
1872 /* setup initial configuration into command buffer */
1873 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1874 switch (cmd_buffer->queue_family_index) {
1875 case RADV_QUEUE_GENERAL:
1876 emit_gfx_buffer_state(cmd_buffer);
1877 break;
1878 case RADV_QUEUE_COMPUTE:
1879 si_init_compute(cmd_buffer);
1880 break;
1881 case RADV_QUEUE_TRANSFER:
1882 default:
1883 break;
1884 }
1885 }
1886
1887 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1888 assert(pBeginInfo->pInheritanceInfo);
1889 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1890 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1891
1892 struct radv_subpass *subpass =
1893 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1894
1895 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1896 if (result != VK_SUCCESS)
1897 return result;
1898
1899 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
1900 }
1901
1902 if (unlikely(cmd_buffer->device->trace_bo))
1903 radv_cmd_buffer_trace_emit(cmd_buffer);
1904
1905 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
1906
1907 return result;
1908 }
1909
1910 void radv_CmdBindVertexBuffers(
1911 VkCommandBuffer commandBuffer,
1912 uint32_t firstBinding,
1913 uint32_t bindingCount,
1914 const VkBuffer* pBuffers,
1915 const VkDeviceSize* pOffsets)
1916 {
1917 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1918 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
1919 bool changed = false;
1920
1921 /* We have to defer setting up vertex buffer since we need the buffer
1922 * stride from the pipeline. */
1923
1924 assert(firstBinding + bindingCount <= MAX_VBS);
1925 for (uint32_t i = 0; i < bindingCount; i++) {
1926 uint32_t idx = firstBinding + i;
1927
1928 if (!changed &&
1929 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
1930 vb[idx].offset != pOffsets[i])) {
1931 changed = true;
1932 }
1933
1934 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
1935 vb[idx].offset = pOffsets[i];
1936
1937 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1938 vb[idx].buffer->bo, 8);
1939 }
1940
1941 if (!changed) {
1942 /* No state changes. */
1943 return;
1944 }
1945
1946 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
1947 }
1948
1949 void radv_CmdBindIndexBuffer(
1950 VkCommandBuffer commandBuffer,
1951 VkBuffer buffer,
1952 VkDeviceSize offset,
1953 VkIndexType indexType)
1954 {
1955 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1956 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
1957
1958 if (cmd_buffer->state.index_buffer == index_buffer &&
1959 cmd_buffer->state.index_offset == offset &&
1960 cmd_buffer->state.index_type == indexType) {
1961 /* No state changes. */
1962 return;
1963 }
1964
1965 cmd_buffer->state.index_buffer = index_buffer;
1966 cmd_buffer->state.index_offset = offset;
1967 cmd_buffer->state.index_type = indexType; /* vk matches hw */
1968 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
1969 cmd_buffer->state.index_va += index_buffer->offset + offset;
1970
1971 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
1972 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
1973 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
1974 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8);
1975 }
1976
1977
1978 static void
1979 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1980 struct radv_descriptor_set *set, unsigned idx)
1981 {
1982 struct radeon_winsys *ws = cmd_buffer->device->ws;
1983
1984 radv_set_descriptor_set(cmd_buffer, set, idx);
1985 if (!set)
1986 return;
1987
1988 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
1989
1990 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
1991 if (set->descriptors[j])
1992 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7);
1993
1994 if(set->bo)
1995 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
1996 }
1997
1998 void radv_CmdBindDescriptorSets(
1999 VkCommandBuffer commandBuffer,
2000 VkPipelineBindPoint pipelineBindPoint,
2001 VkPipelineLayout _layout,
2002 uint32_t firstSet,
2003 uint32_t descriptorSetCount,
2004 const VkDescriptorSet* pDescriptorSets,
2005 uint32_t dynamicOffsetCount,
2006 const uint32_t* pDynamicOffsets)
2007 {
2008 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2009 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2010 unsigned dyn_idx = 0;
2011
2012 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2013 unsigned idx = i + firstSet;
2014 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2015 radv_bind_descriptor_set(cmd_buffer, set, idx);
2016
2017 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2018 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2019 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2020 assert(dyn_idx < dynamicOffsetCount);
2021
2022 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2023 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2024 dst[0] = va;
2025 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2026 dst[2] = range->size;
2027 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2028 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2029 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2030 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2031 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2032 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2033 cmd_buffer->push_constant_stages |=
2034 set->layout->dynamic_shader_stages;
2035 }
2036 }
2037 }
2038
2039 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2040 struct radv_descriptor_set *set,
2041 struct radv_descriptor_set_layout *layout)
2042 {
2043 set->size = layout->size;
2044 set->layout = layout;
2045
2046 if (cmd_buffer->push_descriptors.capacity < set->size) {
2047 size_t new_size = MAX2(set->size, 1024);
2048 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2049 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2050
2051 free(set->mapped_ptr);
2052 set->mapped_ptr = malloc(new_size);
2053
2054 if (!set->mapped_ptr) {
2055 cmd_buffer->push_descriptors.capacity = 0;
2056 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2057 return false;
2058 }
2059
2060 cmd_buffer->push_descriptors.capacity = new_size;
2061 }
2062
2063 return true;
2064 }
2065
2066 void radv_meta_push_descriptor_set(
2067 struct radv_cmd_buffer* cmd_buffer,
2068 VkPipelineBindPoint pipelineBindPoint,
2069 VkPipelineLayout _layout,
2070 uint32_t set,
2071 uint32_t descriptorWriteCount,
2072 const VkWriteDescriptorSet* pDescriptorWrites)
2073 {
2074 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2075 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2076 unsigned bo_offset;
2077
2078 assert(set == 0);
2079 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2080
2081 push_set->size = layout->set[set].layout->size;
2082 push_set->layout = layout->set[set].layout;
2083
2084 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2085 &bo_offset,
2086 (void**) &push_set->mapped_ptr))
2087 return;
2088
2089 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2090 push_set->va += bo_offset;
2091
2092 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2093 radv_descriptor_set_to_handle(push_set),
2094 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2095
2096 radv_set_descriptor_set(cmd_buffer, push_set, set);
2097 }
2098
2099 void radv_CmdPushDescriptorSetKHR(
2100 VkCommandBuffer commandBuffer,
2101 VkPipelineBindPoint pipelineBindPoint,
2102 VkPipelineLayout _layout,
2103 uint32_t set,
2104 uint32_t descriptorWriteCount,
2105 const VkWriteDescriptorSet* pDescriptorWrites)
2106 {
2107 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2108 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2109 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2110
2111 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2112
2113 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2114 return;
2115
2116 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2117 radv_descriptor_set_to_handle(push_set),
2118 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2119
2120 radv_set_descriptor_set(cmd_buffer, push_set, set);
2121 cmd_buffer->state.push_descriptors_dirty = true;
2122 }
2123
2124 void radv_CmdPushDescriptorSetWithTemplateKHR(
2125 VkCommandBuffer commandBuffer,
2126 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2127 VkPipelineLayout _layout,
2128 uint32_t set,
2129 const void* pData)
2130 {
2131 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2132 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2133 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2134
2135 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2136
2137 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2138 return;
2139
2140 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2141 descriptorUpdateTemplate, pData);
2142
2143 radv_set_descriptor_set(cmd_buffer, push_set, set);
2144 cmd_buffer->state.push_descriptors_dirty = true;
2145 }
2146
2147 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2148 VkPipelineLayout layout,
2149 VkShaderStageFlags stageFlags,
2150 uint32_t offset,
2151 uint32_t size,
2152 const void* pValues)
2153 {
2154 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2155 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2156 cmd_buffer->push_constant_stages |= stageFlags;
2157 }
2158
2159 VkResult radv_EndCommandBuffer(
2160 VkCommandBuffer commandBuffer)
2161 {
2162 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2163
2164 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2165 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2166 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2167 si_emit_cache_flush(cmd_buffer);
2168 }
2169
2170 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2171
2172 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2173 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2174
2175 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2176
2177 return cmd_buffer->record_result;
2178 }
2179
2180 static void
2181 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2182 {
2183 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2184
2185 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2186 return;
2187
2188 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2189
2190 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2191 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2192
2193 cmd_buffer->compute_scratch_size_needed =
2194 MAX2(cmd_buffer->compute_scratch_size_needed,
2195 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2196
2197 if (unlikely(cmd_buffer->device->trace_bo))
2198 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2199 }
2200
2201 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2202 {
2203 cmd_buffer->state.descriptors_dirty |= cmd_buffer->state.valid_descriptors;
2204 }
2205
2206 void radv_CmdBindPipeline(
2207 VkCommandBuffer commandBuffer,
2208 VkPipelineBindPoint pipelineBindPoint,
2209 VkPipeline _pipeline)
2210 {
2211 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2212 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2213
2214 switch (pipelineBindPoint) {
2215 case VK_PIPELINE_BIND_POINT_COMPUTE:
2216 if (cmd_buffer->state.compute_pipeline == pipeline)
2217 return;
2218 radv_mark_descriptor_sets_dirty(cmd_buffer);
2219
2220 cmd_buffer->state.compute_pipeline = pipeline;
2221 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2222 break;
2223 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2224 if (cmd_buffer->state.pipeline == pipeline)
2225 return;
2226 radv_mark_descriptor_sets_dirty(cmd_buffer);
2227
2228 cmd_buffer->state.pipeline = pipeline;
2229 if (!pipeline)
2230 break;
2231
2232 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2233 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2234
2235 /* the new vertex shader might not have the same user regs */
2236 cmd_buffer->state.last_first_instance = -1;
2237 cmd_buffer->state.last_vertex_offset = -1;
2238
2239 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2240
2241 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2242 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2243 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2244 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2245
2246 if (radv_pipeline_has_tess(pipeline))
2247 cmd_buffer->tess_rings_needed = true;
2248
2249 if (radv_pipeline_has_gs(pipeline)) {
2250 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2251 AC_UD_SCRATCH_RING_OFFSETS);
2252 if (cmd_buffer->ring_offsets_idx == -1)
2253 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2254 else if (loc->sgpr_idx != -1)
2255 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2256 }
2257 break;
2258 default:
2259 assert(!"invalid bind point");
2260 break;
2261 }
2262 }
2263
2264 void radv_CmdSetViewport(
2265 VkCommandBuffer commandBuffer,
2266 uint32_t firstViewport,
2267 uint32_t viewportCount,
2268 const VkViewport* pViewports)
2269 {
2270 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2271 struct radv_cmd_state *state = &cmd_buffer->state;
2272 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2273
2274 assert(firstViewport < MAX_VIEWPORTS);
2275 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2276
2277 if (cmd_buffer->device->physical_device->has_scissor_bug) {
2278 /* Try to skip unnecessary PS partial flushes when the viewports
2279 * don't change.
2280 */
2281 if (!(state->dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT |
2282 RADV_CMD_DIRTY_DYNAMIC_SCISSOR)) &&
2283 !memcmp(state->dynamic.viewport.viewports + firstViewport,
2284 pViewports, viewportCount * sizeof(*pViewports))) {
2285 return;
2286 }
2287 }
2288
2289 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2290 viewportCount * sizeof(*pViewports));
2291
2292 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2293 }
2294
2295 void radv_CmdSetScissor(
2296 VkCommandBuffer commandBuffer,
2297 uint32_t firstScissor,
2298 uint32_t scissorCount,
2299 const VkRect2D* pScissors)
2300 {
2301 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2302 struct radv_cmd_state *state = &cmd_buffer->state;
2303 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2304
2305 assert(firstScissor < MAX_SCISSORS);
2306 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2307
2308 if (cmd_buffer->device->physical_device->has_scissor_bug) {
2309 /* Try to skip unnecessary PS partial flushes when the scissors
2310 * don't change.
2311 */
2312 if (!(state->dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT |
2313 RADV_CMD_DIRTY_DYNAMIC_SCISSOR)) &&
2314 !memcmp(state->dynamic.scissor.scissors + firstScissor,
2315 pScissors, scissorCount * sizeof(*pScissors))) {
2316 return;
2317 }
2318 }
2319
2320 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2321 scissorCount * sizeof(*pScissors));
2322
2323 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2324 }
2325
2326 void radv_CmdSetLineWidth(
2327 VkCommandBuffer commandBuffer,
2328 float lineWidth)
2329 {
2330 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2331 cmd_buffer->state.dynamic.line_width = lineWidth;
2332 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2333 }
2334
2335 void radv_CmdSetDepthBias(
2336 VkCommandBuffer commandBuffer,
2337 float depthBiasConstantFactor,
2338 float depthBiasClamp,
2339 float depthBiasSlopeFactor)
2340 {
2341 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2342
2343 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2344 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2345 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2346
2347 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2348 }
2349
2350 void radv_CmdSetBlendConstants(
2351 VkCommandBuffer commandBuffer,
2352 const float blendConstants[4])
2353 {
2354 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2355
2356 memcpy(cmd_buffer->state.dynamic.blend_constants,
2357 blendConstants, sizeof(float) * 4);
2358
2359 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2360 }
2361
2362 void radv_CmdSetDepthBounds(
2363 VkCommandBuffer commandBuffer,
2364 float minDepthBounds,
2365 float maxDepthBounds)
2366 {
2367 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2368
2369 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2370 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2371
2372 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2373 }
2374
2375 void radv_CmdSetStencilCompareMask(
2376 VkCommandBuffer commandBuffer,
2377 VkStencilFaceFlags faceMask,
2378 uint32_t compareMask)
2379 {
2380 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2381
2382 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2383 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2384 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2385 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2386
2387 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2388 }
2389
2390 void radv_CmdSetStencilWriteMask(
2391 VkCommandBuffer commandBuffer,
2392 VkStencilFaceFlags faceMask,
2393 uint32_t writeMask)
2394 {
2395 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2396
2397 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2398 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2399 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2400 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2401
2402 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2403 }
2404
2405 void radv_CmdSetStencilReference(
2406 VkCommandBuffer commandBuffer,
2407 VkStencilFaceFlags faceMask,
2408 uint32_t reference)
2409 {
2410 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2411
2412 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2413 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2414 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2415 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2416
2417 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2418 }
2419
2420 void radv_CmdSetDiscardRectangleEXT(
2421 VkCommandBuffer commandBuffer,
2422 uint32_t firstDiscardRectangle,
2423 uint32_t discardRectangleCount,
2424 const VkRect2D* pDiscardRectangles)
2425 {
2426 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2427 struct radv_cmd_state *state = &cmd_buffer->state;
2428 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
2429
2430 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
2431 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
2432
2433 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
2434 pDiscardRectangles, discardRectangleCount);
2435
2436 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
2437 }
2438
2439 void radv_CmdExecuteCommands(
2440 VkCommandBuffer commandBuffer,
2441 uint32_t commandBufferCount,
2442 const VkCommandBuffer* pCmdBuffers)
2443 {
2444 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2445
2446 assert(commandBufferCount > 0);
2447
2448 /* Emit pending flushes on primary prior to executing secondary */
2449 si_emit_cache_flush(primary);
2450
2451 for (uint32_t i = 0; i < commandBufferCount; i++) {
2452 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2453
2454 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2455 secondary->scratch_size_needed);
2456 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2457 secondary->compute_scratch_size_needed);
2458
2459 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2460 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2461 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2462 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2463 if (secondary->tess_rings_needed)
2464 primary->tess_rings_needed = true;
2465 if (secondary->sample_positions_needed)
2466 primary->sample_positions_needed = true;
2467
2468 if (secondary->ring_offsets_idx != -1) {
2469 if (primary->ring_offsets_idx == -1)
2470 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2471 else
2472 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2473 }
2474 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2475
2476
2477 /* When the secondary command buffer is compute only we don't
2478 * need to re-emit the current graphics pipeline.
2479 */
2480 if (secondary->state.emitted_pipeline) {
2481 primary->state.emitted_pipeline =
2482 secondary->state.emitted_pipeline;
2483 }
2484
2485 /* When the secondary command buffer is graphics only we don't
2486 * need to re-emit the current compute pipeline.
2487 */
2488 if (secondary->state.emitted_compute_pipeline) {
2489 primary->state.emitted_compute_pipeline =
2490 secondary->state.emitted_compute_pipeline;
2491 }
2492
2493 /* Only re-emit the draw packets when needed. */
2494 if (secondary->state.last_primitive_reset_en != -1) {
2495 primary->state.last_primitive_reset_en =
2496 secondary->state.last_primitive_reset_en;
2497 }
2498
2499 if (secondary->state.last_primitive_reset_index) {
2500 primary->state.last_primitive_reset_index =
2501 secondary->state.last_primitive_reset_index;
2502 }
2503
2504 if (secondary->state.last_ia_multi_vgt_param) {
2505 primary->state.last_ia_multi_vgt_param =
2506 secondary->state.last_ia_multi_vgt_param;
2507 }
2508
2509 if (secondary->state.last_first_instance != -1) {
2510 primary->state.last_first_instance =
2511 secondary->state.last_first_instance;
2512 }
2513
2514 if (secondary->state.last_num_instances != -1) {
2515 primary->state.last_num_instances =
2516 secondary->state.last_num_instances;
2517 }
2518
2519 if (secondary->state.last_vertex_offset != -1) {
2520 primary->state.last_vertex_offset =
2521 secondary->state.last_vertex_offset;
2522 }
2523
2524 if (secondary->state.last_index_type != -1) {
2525 primary->state.last_index_type =
2526 secondary->state.last_index_type;
2527 }
2528 }
2529
2530 /* After executing commands from secondary buffers we have to dirty
2531 * some states.
2532 */
2533 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2534 RADV_CMD_DIRTY_INDEX_BUFFER |
2535 RADV_CMD_DIRTY_DYNAMIC_ALL;
2536 radv_mark_descriptor_sets_dirty(primary);
2537 }
2538
2539 VkResult radv_CreateCommandPool(
2540 VkDevice _device,
2541 const VkCommandPoolCreateInfo* pCreateInfo,
2542 const VkAllocationCallbacks* pAllocator,
2543 VkCommandPool* pCmdPool)
2544 {
2545 RADV_FROM_HANDLE(radv_device, device, _device);
2546 struct radv_cmd_pool *pool;
2547
2548 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2549 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2550 if (pool == NULL)
2551 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2552
2553 if (pAllocator)
2554 pool->alloc = *pAllocator;
2555 else
2556 pool->alloc = device->alloc;
2557
2558 list_inithead(&pool->cmd_buffers);
2559 list_inithead(&pool->free_cmd_buffers);
2560
2561 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2562
2563 *pCmdPool = radv_cmd_pool_to_handle(pool);
2564
2565 return VK_SUCCESS;
2566
2567 }
2568
2569 void radv_DestroyCommandPool(
2570 VkDevice _device,
2571 VkCommandPool commandPool,
2572 const VkAllocationCallbacks* pAllocator)
2573 {
2574 RADV_FROM_HANDLE(radv_device, device, _device);
2575 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2576
2577 if (!pool)
2578 return;
2579
2580 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2581 &pool->cmd_buffers, pool_link) {
2582 radv_cmd_buffer_destroy(cmd_buffer);
2583 }
2584
2585 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2586 &pool->free_cmd_buffers, pool_link) {
2587 radv_cmd_buffer_destroy(cmd_buffer);
2588 }
2589
2590 vk_free2(&device->alloc, pAllocator, pool);
2591 }
2592
2593 VkResult radv_ResetCommandPool(
2594 VkDevice device,
2595 VkCommandPool commandPool,
2596 VkCommandPoolResetFlags flags)
2597 {
2598 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2599 VkResult result;
2600
2601 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2602 &pool->cmd_buffers, pool_link) {
2603 result = radv_reset_cmd_buffer(cmd_buffer);
2604 if (result != VK_SUCCESS)
2605 return result;
2606 }
2607
2608 return VK_SUCCESS;
2609 }
2610
2611 void radv_TrimCommandPoolKHR(
2612 VkDevice device,
2613 VkCommandPool commandPool,
2614 VkCommandPoolTrimFlagsKHR flags)
2615 {
2616 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2617
2618 if (!pool)
2619 return;
2620
2621 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2622 &pool->free_cmd_buffers, pool_link) {
2623 radv_cmd_buffer_destroy(cmd_buffer);
2624 }
2625 }
2626
2627 void radv_CmdBeginRenderPass(
2628 VkCommandBuffer commandBuffer,
2629 const VkRenderPassBeginInfo* pRenderPassBegin,
2630 VkSubpassContents contents)
2631 {
2632 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2633 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2634 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2635
2636 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2637 cmd_buffer->cs, 2048);
2638 MAYBE_UNUSED VkResult result;
2639
2640 cmd_buffer->state.framebuffer = framebuffer;
2641 cmd_buffer->state.pass = pass;
2642 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2643
2644 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2645 if (result != VK_SUCCESS)
2646 return;
2647
2648 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2649 assert(cmd_buffer->cs->cdw <= cdw_max);
2650
2651 radv_cmd_buffer_clear_subpass(cmd_buffer);
2652 }
2653
2654 void radv_CmdNextSubpass(
2655 VkCommandBuffer commandBuffer,
2656 VkSubpassContents contents)
2657 {
2658 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2659
2660 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2661
2662 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2663 2048);
2664
2665 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2666 radv_cmd_buffer_clear_subpass(cmd_buffer);
2667 }
2668
2669 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
2670 {
2671 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2672 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2673 if (!pipeline->shaders[stage])
2674 continue;
2675 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
2676 if (loc->sgpr_idx == -1)
2677 continue;
2678 uint32_t base_reg = pipeline->user_data_0[stage];
2679 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2680
2681 }
2682 if (pipeline->gs_copy_shader) {
2683 struct ac_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
2684 if (loc->sgpr_idx != -1) {
2685 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2686 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2687 }
2688 }
2689 }
2690
2691 static void
2692 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2693 uint32_t vertex_count)
2694 {
2695 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
2696 radeon_emit(cmd_buffer->cs, vertex_count);
2697 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2698 S_0287F0_USE_OPAQUE(0));
2699 }
2700
2701 static void
2702 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
2703 uint64_t index_va,
2704 uint32_t index_count)
2705 {
2706 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2707 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2708 radeon_emit(cmd_buffer->cs, index_va);
2709 radeon_emit(cmd_buffer->cs, index_va >> 32);
2710 radeon_emit(cmd_buffer->cs, index_count);
2711 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2712 }
2713
2714 static void
2715 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2716 bool indexed,
2717 uint32_t draw_count,
2718 uint64_t count_va,
2719 uint32_t stride)
2720 {
2721 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2722 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2723 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2724 bool draw_id_enable = radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.needs_draw_id;
2725 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
2726 assert(base_reg);
2727
2728 /* just reset draw state for vertex data */
2729 cmd_buffer->state.last_first_instance = -1;
2730 cmd_buffer->state.last_num_instances = -1;
2731 cmd_buffer->state.last_vertex_offset = -1;
2732
2733 if (draw_count == 1 && !count_va && !draw_id_enable) {
2734 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
2735 PKT3_DRAW_INDIRECT, 3, false));
2736 radeon_emit(cs, 0);
2737 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2738 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2739 radeon_emit(cs, di_src_sel);
2740 } else {
2741 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2742 PKT3_DRAW_INDIRECT_MULTI,
2743 8, false));
2744 radeon_emit(cs, 0);
2745 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2746 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2747 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
2748 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
2749 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2750 radeon_emit(cs, draw_count); /* count */
2751 radeon_emit(cs, count_va); /* count_addr */
2752 radeon_emit(cs, count_va >> 32);
2753 radeon_emit(cs, stride); /* stride */
2754 radeon_emit(cs, di_src_sel);
2755 }
2756 }
2757
2758 struct radv_draw_info {
2759 /**
2760 * Number of vertices.
2761 */
2762 uint32_t count;
2763
2764 /**
2765 * Index of the first vertex.
2766 */
2767 int32_t vertex_offset;
2768
2769 /**
2770 * First instance id.
2771 */
2772 uint32_t first_instance;
2773
2774 /**
2775 * Number of instances.
2776 */
2777 uint32_t instance_count;
2778
2779 /**
2780 * First index (indexed draws only).
2781 */
2782 uint32_t first_index;
2783
2784 /**
2785 * Whether it's an indexed draw.
2786 */
2787 bool indexed;
2788
2789 /**
2790 * Indirect draw parameters resource.
2791 */
2792 struct radv_buffer *indirect;
2793 uint64_t indirect_offset;
2794 uint32_t stride;
2795
2796 /**
2797 * Draw count parameters resource.
2798 */
2799 struct radv_buffer *count_buffer;
2800 uint64_t count_buffer_offset;
2801 };
2802
2803 static void
2804 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
2805 const struct radv_draw_info *info)
2806 {
2807 struct radv_cmd_state *state = &cmd_buffer->state;
2808 struct radeon_winsys *ws = cmd_buffer->device->ws;
2809 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2810
2811 if (info->indirect) {
2812 uint64_t va = radv_buffer_get_va(info->indirect->bo);
2813 uint64_t count_va = 0;
2814
2815 va += info->indirect->offset + info->indirect_offset;
2816
2817 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
2818
2819 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2820 radeon_emit(cs, 1);
2821 radeon_emit(cs, va);
2822 radeon_emit(cs, va >> 32);
2823
2824 if (info->count_buffer) {
2825 count_va = radv_buffer_get_va(info->count_buffer->bo);
2826 count_va += info->count_buffer->offset +
2827 info->count_buffer_offset;
2828
2829 radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
2830 }
2831
2832 if (!state->subpass->view_mask) {
2833 radv_cs_emit_indirect_draw_packet(cmd_buffer,
2834 info->indexed,
2835 info->count,
2836 count_va,
2837 info->stride);
2838 } else {
2839 unsigned i;
2840 for_each_bit(i, state->subpass->view_mask) {
2841 radv_emit_view_index(cmd_buffer, i);
2842
2843 radv_cs_emit_indirect_draw_packet(cmd_buffer,
2844 info->indexed,
2845 info->count,
2846 count_va,
2847 info->stride);
2848 }
2849 }
2850 } else {
2851 assert(state->pipeline->graphics.vtx_base_sgpr);
2852
2853 if (info->vertex_offset != state->last_vertex_offset ||
2854 info->first_instance != state->last_first_instance) {
2855 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
2856 state->pipeline->graphics.vtx_emit_num);
2857
2858 radeon_emit(cs, info->vertex_offset);
2859 radeon_emit(cs, info->first_instance);
2860 if (state->pipeline->graphics.vtx_emit_num == 3)
2861 radeon_emit(cs, 0);
2862 state->last_first_instance = info->first_instance;
2863 state->last_vertex_offset = info->vertex_offset;
2864 }
2865
2866 if (state->last_num_instances != info->instance_count) {
2867 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, state->predicating));
2868 radeon_emit(cs, info->instance_count);
2869 state->last_num_instances = info->instance_count;
2870 }
2871
2872 if (info->indexed) {
2873 int index_size = state->index_type ? 4 : 2;
2874 uint64_t index_va;
2875
2876 index_va = state->index_va;
2877 index_va += info->first_index * index_size;
2878
2879 if (!state->subpass->view_mask) {
2880 radv_cs_emit_draw_indexed_packet(cmd_buffer,
2881 index_va,
2882 info->count);
2883 } else {
2884 unsigned i;
2885 for_each_bit(i, state->subpass->view_mask) {
2886 radv_emit_view_index(cmd_buffer, i);
2887
2888 radv_cs_emit_draw_indexed_packet(cmd_buffer,
2889 index_va,
2890 info->count);
2891 }
2892 }
2893 } else {
2894 if (!state->subpass->view_mask) {
2895 radv_cs_emit_draw_packet(cmd_buffer, info->count);
2896 } else {
2897 unsigned i;
2898 for_each_bit(i, state->subpass->view_mask) {
2899 radv_emit_view_index(cmd_buffer, i);
2900
2901 radv_cs_emit_draw_packet(cmd_buffer,
2902 info->count);
2903 }
2904 }
2905 }
2906 }
2907 }
2908
2909 static void
2910 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
2911 const struct radv_draw_info *info)
2912 {
2913 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
2914 radv_emit_graphics_pipeline(cmd_buffer);
2915
2916 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
2917 radv_emit_framebuffer_state(cmd_buffer);
2918
2919 if (info->indexed) {
2920 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
2921 radv_emit_index_buffer(cmd_buffer);
2922 } else {
2923 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
2924 * so the state must be re-emitted before the next indexed
2925 * draw.
2926 */
2927 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
2928 cmd_buffer->state.last_index_type = -1;
2929 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2930 }
2931 }
2932
2933 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
2934
2935 radv_emit_draw_registers(cmd_buffer, info->indexed,
2936 info->instance_count > 1, info->indirect,
2937 info->indirect ? 0 : info->count);
2938 }
2939
2940 static void
2941 radv_draw(struct radv_cmd_buffer *cmd_buffer,
2942 const struct radv_draw_info *info)
2943 {
2944 bool pipeline_is_dirty =
2945 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
2946 cmd_buffer->state.pipeline &&
2947 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
2948
2949 MAYBE_UNUSED unsigned cdw_max =
2950 radeon_check_space(cmd_buffer->device->ws,
2951 cmd_buffer->cs, 4096);
2952
2953 /* Use optimal packet order based on whether we need to sync the
2954 * pipeline.
2955 */
2956 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2957 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2958 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
2959 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
2960 /* If we have to wait for idle, set all states first, so that
2961 * all SET packets are processed in parallel with previous draw
2962 * calls. Then upload descriptors, set shader pointers, and
2963 * draw, and prefetch at the end. This ensures that the time
2964 * the CUs are idle is very short. (there are only SET_SH
2965 * packets between the wait and the draw)
2966 */
2967 radv_emit_all_graphics_states(cmd_buffer, info);
2968 si_emit_cache_flush(cmd_buffer);
2969 /* <-- CUs are idle here --> */
2970
2971 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
2972 return;
2973
2974 radv_emit_draw_packets(cmd_buffer, info);
2975 /* <-- CUs are busy here --> */
2976
2977 /* Start prefetches after the draw has been started. Both will
2978 * run in parallel, but starting the draw first is more
2979 * important.
2980 */
2981 if (pipeline_is_dirty) {
2982 radv_emit_prefetch(cmd_buffer,
2983 cmd_buffer->state.pipeline);
2984 }
2985 } else {
2986 /* If we don't wait for idle, start prefetches first, then set
2987 * states, and draw at the end.
2988 */
2989 si_emit_cache_flush(cmd_buffer);
2990
2991 if (pipeline_is_dirty) {
2992 radv_emit_prefetch(cmd_buffer,
2993 cmd_buffer->state.pipeline);
2994 }
2995
2996 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
2997 return;
2998
2999 radv_emit_all_graphics_states(cmd_buffer, info);
3000 radv_emit_draw_packets(cmd_buffer, info);
3001 }
3002
3003 assert(cmd_buffer->cs->cdw <= cdw_max);
3004 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3005 }
3006
3007 void radv_CmdDraw(
3008 VkCommandBuffer commandBuffer,
3009 uint32_t vertexCount,
3010 uint32_t instanceCount,
3011 uint32_t firstVertex,
3012 uint32_t firstInstance)
3013 {
3014 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3015 struct radv_draw_info info = {};
3016
3017 info.count = vertexCount;
3018 info.instance_count = instanceCount;
3019 info.first_instance = firstInstance;
3020 info.vertex_offset = firstVertex;
3021
3022 radv_draw(cmd_buffer, &info);
3023 }
3024
3025 void radv_CmdDrawIndexed(
3026 VkCommandBuffer commandBuffer,
3027 uint32_t indexCount,
3028 uint32_t instanceCount,
3029 uint32_t firstIndex,
3030 int32_t vertexOffset,
3031 uint32_t firstInstance)
3032 {
3033 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3034 struct radv_draw_info info = {};
3035
3036 info.indexed = true;
3037 info.count = indexCount;
3038 info.instance_count = instanceCount;
3039 info.first_index = firstIndex;
3040 info.vertex_offset = vertexOffset;
3041 info.first_instance = firstInstance;
3042
3043 radv_draw(cmd_buffer, &info);
3044 }
3045
3046 void radv_CmdDrawIndirect(
3047 VkCommandBuffer commandBuffer,
3048 VkBuffer _buffer,
3049 VkDeviceSize offset,
3050 uint32_t drawCount,
3051 uint32_t stride)
3052 {
3053 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3054 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3055 struct radv_draw_info info = {};
3056
3057 info.count = drawCount;
3058 info.indirect = buffer;
3059 info.indirect_offset = offset;
3060 info.stride = stride;
3061
3062 radv_draw(cmd_buffer, &info);
3063 }
3064
3065 void radv_CmdDrawIndexedIndirect(
3066 VkCommandBuffer commandBuffer,
3067 VkBuffer _buffer,
3068 VkDeviceSize offset,
3069 uint32_t drawCount,
3070 uint32_t stride)
3071 {
3072 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3073 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3074 struct radv_draw_info info = {};
3075
3076 info.indexed = true;
3077 info.count = drawCount;
3078 info.indirect = buffer;
3079 info.indirect_offset = offset;
3080 info.stride = stride;
3081
3082 radv_draw(cmd_buffer, &info);
3083 }
3084
3085 void radv_CmdDrawIndirectCountAMD(
3086 VkCommandBuffer commandBuffer,
3087 VkBuffer _buffer,
3088 VkDeviceSize offset,
3089 VkBuffer _countBuffer,
3090 VkDeviceSize countBufferOffset,
3091 uint32_t maxDrawCount,
3092 uint32_t stride)
3093 {
3094 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3095 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3096 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3097 struct radv_draw_info info = {};
3098
3099 info.count = maxDrawCount;
3100 info.indirect = buffer;
3101 info.indirect_offset = offset;
3102 info.count_buffer = count_buffer;
3103 info.count_buffer_offset = countBufferOffset;
3104 info.stride = stride;
3105
3106 radv_draw(cmd_buffer, &info);
3107 }
3108
3109 void radv_CmdDrawIndexedIndirectCountAMD(
3110 VkCommandBuffer commandBuffer,
3111 VkBuffer _buffer,
3112 VkDeviceSize offset,
3113 VkBuffer _countBuffer,
3114 VkDeviceSize countBufferOffset,
3115 uint32_t maxDrawCount,
3116 uint32_t stride)
3117 {
3118 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3119 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3120 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3121 struct radv_draw_info info = {};
3122
3123 info.indexed = true;
3124 info.count = maxDrawCount;
3125 info.indirect = buffer;
3126 info.indirect_offset = offset;
3127 info.count_buffer = count_buffer;
3128 info.count_buffer_offset = countBufferOffset;
3129 info.stride = stride;
3130
3131 radv_draw(cmd_buffer, &info);
3132 }
3133
3134 struct radv_dispatch_info {
3135 /**
3136 * Determine the layout of the grid (in block units) to be used.
3137 */
3138 uint32_t blocks[3];
3139
3140 /**
3141 * Whether it's an unaligned compute dispatch.
3142 */
3143 bool unaligned;
3144
3145 /**
3146 * Indirect compute parameters resource.
3147 */
3148 struct radv_buffer *indirect;
3149 uint64_t indirect_offset;
3150 };
3151
3152 static void
3153 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3154 const struct radv_dispatch_info *info)
3155 {
3156 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3157 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3158 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3159 struct radeon_winsys *ws = cmd_buffer->device->ws;
3160 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3161 struct ac_userdata_info *loc;
3162
3163 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3164 AC_UD_CS_GRID_SIZE);
3165
3166 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3167
3168 if (info->indirect) {
3169 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3170
3171 va += info->indirect->offset + info->indirect_offset;
3172
3173 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3174
3175 if (loc->sgpr_idx != -1) {
3176 for (unsigned i = 0; i < 3; ++i) {
3177 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3178 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3179 COPY_DATA_DST_SEL(COPY_DATA_REG));
3180 radeon_emit(cs, (va + 4 * i));
3181 radeon_emit(cs, (va + 4 * i) >> 32);
3182 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3183 + loc->sgpr_idx * 4) >> 2) + i);
3184 radeon_emit(cs, 0);
3185 }
3186 }
3187
3188 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3189 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3190 PKT3_SHADER_TYPE_S(1));
3191 radeon_emit(cs, va);
3192 radeon_emit(cs, va >> 32);
3193 radeon_emit(cs, dispatch_initiator);
3194 } else {
3195 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3196 PKT3_SHADER_TYPE_S(1));
3197 radeon_emit(cs, 1);
3198 radeon_emit(cs, va);
3199 radeon_emit(cs, va >> 32);
3200
3201 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3202 PKT3_SHADER_TYPE_S(1));
3203 radeon_emit(cs, 0);
3204 radeon_emit(cs, dispatch_initiator);
3205 }
3206 } else {
3207 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3208
3209 if (info->unaligned) {
3210 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3211 unsigned remainder[3];
3212
3213 /* If aligned, these should be an entire block size,
3214 * not 0.
3215 */
3216 remainder[0] = blocks[0] + cs_block_size[0] -
3217 align_u32_npot(blocks[0], cs_block_size[0]);
3218 remainder[1] = blocks[1] + cs_block_size[1] -
3219 align_u32_npot(blocks[1], cs_block_size[1]);
3220 remainder[2] = blocks[2] + cs_block_size[2] -
3221 align_u32_npot(blocks[2], cs_block_size[2]);
3222
3223 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3224 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3225 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3226
3227 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3228 radeon_emit(cs,
3229 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3230 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3231 radeon_emit(cs,
3232 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3233 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3234 radeon_emit(cs,
3235 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3236 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3237
3238 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3239 }
3240
3241 if (loc->sgpr_idx != -1) {
3242 assert(!loc->indirect);
3243 assert(loc->num_sgprs == 3);
3244
3245 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3246 loc->sgpr_idx * 4, 3);
3247 radeon_emit(cs, blocks[0]);
3248 radeon_emit(cs, blocks[1]);
3249 radeon_emit(cs, blocks[2]);
3250 }
3251
3252 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3253 PKT3_SHADER_TYPE_S(1));
3254 radeon_emit(cs, blocks[0]);
3255 radeon_emit(cs, blocks[1]);
3256 radeon_emit(cs, blocks[2]);
3257 radeon_emit(cs, dispatch_initiator);
3258 }
3259
3260 assert(cmd_buffer->cs->cdw <= cdw_max);
3261 }
3262
3263 static void
3264 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3265 {
3266 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3267 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
3268 VK_SHADER_STAGE_COMPUTE_BIT);
3269 }
3270
3271 static void
3272 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3273 const struct radv_dispatch_info *info)
3274 {
3275 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3276 bool pipeline_is_dirty = pipeline &&
3277 pipeline != cmd_buffer->state.emitted_compute_pipeline;
3278
3279 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3280 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3281 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3282 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3283 /* If we have to wait for idle, set all states first, so that
3284 * all SET packets are processed in parallel with previous draw
3285 * calls. Then upload descriptors, set shader pointers, and
3286 * dispatch, and prefetch at the end. This ensures that the
3287 * time the CUs are idle is very short. (there are only SET_SH
3288 * packets between the wait and the draw)
3289 */
3290 radv_emit_compute_pipeline(cmd_buffer);
3291 si_emit_cache_flush(cmd_buffer);
3292 /* <-- CUs are idle here --> */
3293
3294 radv_upload_compute_shader_descriptors(cmd_buffer);
3295
3296 radv_emit_dispatch_packets(cmd_buffer, info);
3297 /* <-- CUs are busy here --> */
3298
3299 /* Start prefetches after the dispatch has been started. Both
3300 * will run in parallel, but starting the dispatch first is
3301 * more important.
3302 */
3303 if (pipeline_is_dirty) {
3304 radv_emit_shader_prefetch(cmd_buffer,
3305 pipeline->shaders[MESA_SHADER_COMPUTE]);
3306 }
3307 } else {
3308 /* If we don't wait for idle, start prefetches first, then set
3309 * states, and dispatch at the end.
3310 */
3311 si_emit_cache_flush(cmd_buffer);
3312
3313 if (pipeline_is_dirty) {
3314 radv_emit_shader_prefetch(cmd_buffer,
3315 pipeline->shaders[MESA_SHADER_COMPUTE]);
3316 }
3317
3318 radv_upload_compute_shader_descriptors(cmd_buffer);
3319
3320 radv_emit_compute_pipeline(cmd_buffer);
3321 radv_emit_dispatch_packets(cmd_buffer, info);
3322 }
3323
3324 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
3325 }
3326
3327 void radv_CmdDispatch(
3328 VkCommandBuffer commandBuffer,
3329 uint32_t x,
3330 uint32_t y,
3331 uint32_t z)
3332 {
3333 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3334 struct radv_dispatch_info info = {};
3335
3336 info.blocks[0] = x;
3337 info.blocks[1] = y;
3338 info.blocks[2] = z;
3339
3340 radv_dispatch(cmd_buffer, &info);
3341 }
3342
3343 void radv_CmdDispatchIndirect(
3344 VkCommandBuffer commandBuffer,
3345 VkBuffer _buffer,
3346 VkDeviceSize offset)
3347 {
3348 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3349 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3350 struct radv_dispatch_info info = {};
3351
3352 info.indirect = buffer;
3353 info.indirect_offset = offset;
3354
3355 radv_dispatch(cmd_buffer, &info);
3356 }
3357
3358 void radv_unaligned_dispatch(
3359 struct radv_cmd_buffer *cmd_buffer,
3360 uint32_t x,
3361 uint32_t y,
3362 uint32_t z)
3363 {
3364 struct radv_dispatch_info info = {};
3365
3366 info.blocks[0] = x;
3367 info.blocks[1] = y;
3368 info.blocks[2] = z;
3369 info.unaligned = 1;
3370
3371 radv_dispatch(cmd_buffer, &info);
3372 }
3373
3374 void radv_CmdEndRenderPass(
3375 VkCommandBuffer commandBuffer)
3376 {
3377 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3378
3379 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3380
3381 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3382
3383 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3384 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3385 radv_handle_subpass_image_transition(cmd_buffer,
3386 (VkAttachmentReference){i, layout});
3387 }
3388
3389 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3390
3391 cmd_buffer->state.pass = NULL;
3392 cmd_buffer->state.subpass = NULL;
3393 cmd_buffer->state.attachments = NULL;
3394 cmd_buffer->state.framebuffer = NULL;
3395 }
3396
3397 /*
3398 * For HTILE we have the following interesting clear words:
3399 * 0x0000030f: Uncompressed for depth+stencil HTILE.
3400 * 0x0000000f: Uncompressed for depth only HTILE.
3401 * 0xfffffff0: Clear depth to 1.0
3402 * 0x00000000: Clear depth to 0.0
3403 */
3404 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3405 struct radv_image *image,
3406 const VkImageSubresourceRange *range,
3407 uint32_t clear_word)
3408 {
3409 assert(range->baseMipLevel == 0);
3410 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3411 unsigned layer_count = radv_get_layerCount(image, range);
3412 uint64_t size = image->surface.htile_slice_size * layer_count;
3413 uint64_t offset = image->offset + image->htile_offset +
3414 image->surface.htile_slice_size * range->baseArrayLayer;
3415 struct radv_cmd_state *state = &cmd_buffer->state;
3416
3417 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3418 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3419
3420 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3421 size, clear_word);
3422
3423 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3424 }
3425
3426 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3427 struct radv_image *image,
3428 VkImageLayout src_layout,
3429 VkImageLayout dst_layout,
3430 unsigned src_queue_mask,
3431 unsigned dst_queue_mask,
3432 const VkImageSubresourceRange *range,
3433 VkImageAspectFlags pending_clears)
3434 {
3435 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3436 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3437 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3438 cmd_buffer->state.render_area.extent.width == image->info.width &&
3439 cmd_buffer->state.render_area.extent.height == image->info.height) {
3440 /* The clear will initialize htile. */
3441 return;
3442 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3443 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3444 /* TODO: merge with the clear if applicable */
3445 radv_initialize_htile(cmd_buffer, image, range, 0);
3446 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3447 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3448 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0x30f : 0xf;
3449 radv_initialize_htile(cmd_buffer, image, range, clear_value);
3450 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3451 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3452 VkImageSubresourceRange local_range = *range;
3453 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3454 local_range.baseMipLevel = 0;
3455 local_range.levelCount = 1;
3456
3457 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3458 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3459
3460 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3461
3462 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3463 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3464 }
3465 }
3466
3467 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3468 struct radv_image *image, uint32_t value)
3469 {
3470 struct radv_cmd_state *state = &cmd_buffer->state;
3471
3472 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3473 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3474
3475 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3476 image->offset + image->cmask.offset,
3477 image->cmask.size, value);
3478
3479 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3480 }
3481
3482 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3483 struct radv_image *image,
3484 VkImageLayout src_layout,
3485 VkImageLayout dst_layout,
3486 unsigned src_queue_mask,
3487 unsigned dst_queue_mask,
3488 const VkImageSubresourceRange *range)
3489 {
3490 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3491 if (image->fmask.size)
3492 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3493 else
3494 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3495 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3496 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3497 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3498 }
3499 }
3500
3501 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3502 struct radv_image *image, uint32_t value)
3503 {
3504 struct radv_cmd_state *state = &cmd_buffer->state;
3505
3506 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3507 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3508
3509 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3510 image->offset + image->dcc_offset,
3511 image->surface.dcc_size, value);
3512
3513 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3514 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3515 }
3516
3517 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3518 struct radv_image *image,
3519 VkImageLayout src_layout,
3520 VkImageLayout dst_layout,
3521 unsigned src_queue_mask,
3522 unsigned dst_queue_mask,
3523 const VkImageSubresourceRange *range)
3524 {
3525 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
3526 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
3527 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3528 radv_initialize_dcc(cmd_buffer, image,
3529 radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask) ?
3530 0x20202020u : 0xffffffffu);
3531 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
3532 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
3533 radv_decompress_dcc(cmd_buffer, image, range);
3534 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3535 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3536 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3537 }
3538 }
3539
3540 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3541 struct radv_image *image,
3542 VkImageLayout src_layout,
3543 VkImageLayout dst_layout,
3544 uint32_t src_family,
3545 uint32_t dst_family,
3546 const VkImageSubresourceRange *range,
3547 VkImageAspectFlags pending_clears)
3548 {
3549 if (image->exclusive && src_family != dst_family) {
3550 /* This is an acquire or a release operation and there will be
3551 * a corresponding release/acquire. Do the transition in the
3552 * most flexible queue. */
3553
3554 assert(src_family == cmd_buffer->queue_family_index ||
3555 dst_family == cmd_buffer->queue_family_index);
3556
3557 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3558 return;
3559
3560 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3561 (src_family == RADV_QUEUE_GENERAL ||
3562 dst_family == RADV_QUEUE_GENERAL))
3563 return;
3564 }
3565
3566 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3567 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3568
3569 if (image->surface.htile_size)
3570 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3571 dst_layout, src_queue_mask,
3572 dst_queue_mask, range,
3573 pending_clears);
3574
3575 if (image->cmask.size || image->fmask.size)
3576 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3577 dst_layout, src_queue_mask,
3578 dst_queue_mask, range);
3579
3580 if (image->surface.dcc_size)
3581 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3582 dst_layout, src_queue_mask,
3583 dst_queue_mask, range);
3584 }
3585
3586 void radv_CmdPipelineBarrier(
3587 VkCommandBuffer commandBuffer,
3588 VkPipelineStageFlags srcStageMask,
3589 VkPipelineStageFlags destStageMask,
3590 VkBool32 byRegion,
3591 uint32_t memoryBarrierCount,
3592 const VkMemoryBarrier* pMemoryBarriers,
3593 uint32_t bufferMemoryBarrierCount,
3594 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3595 uint32_t imageMemoryBarrierCount,
3596 const VkImageMemoryBarrier* pImageMemoryBarriers)
3597 {
3598 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3599 enum radv_cmd_flush_bits src_flush_bits = 0;
3600 enum radv_cmd_flush_bits dst_flush_bits = 0;
3601
3602 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3603 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3604 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3605 NULL);
3606 }
3607
3608 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3609 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3610 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3611 NULL);
3612 }
3613
3614 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3615 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3616 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3617 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3618 image);
3619 }
3620
3621 radv_stage_flush(cmd_buffer, srcStageMask);
3622 cmd_buffer->state.flush_bits |= src_flush_bits;
3623
3624 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3625 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3626 radv_handle_image_transition(cmd_buffer, image,
3627 pImageMemoryBarriers[i].oldLayout,
3628 pImageMemoryBarriers[i].newLayout,
3629 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3630 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3631 &pImageMemoryBarriers[i].subresourceRange,
3632 0);
3633 }
3634
3635 cmd_buffer->state.flush_bits |= dst_flush_bits;
3636 }
3637
3638
3639 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3640 struct radv_event *event,
3641 VkPipelineStageFlags stageMask,
3642 unsigned value)
3643 {
3644 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3645 uint64_t va = radv_buffer_get_va(event->bo);
3646
3647 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
3648
3649 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3650
3651 /* TODO: this is overkill. Probably should figure something out from
3652 * the stage mask. */
3653
3654 si_cs_emit_write_event_eop(cs,
3655 cmd_buffer->state.predicating,
3656 cmd_buffer->device->physical_device->rad_info.chip_class,
3657 radv_cmd_buffer_uses_mec(cmd_buffer),
3658 V_028A90_BOTTOM_OF_PIPE_TS, 0,
3659 1, va, 2, value);
3660
3661 assert(cmd_buffer->cs->cdw <= cdw_max);
3662 }
3663
3664 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3665 VkEvent _event,
3666 VkPipelineStageFlags stageMask)
3667 {
3668 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3669 RADV_FROM_HANDLE(radv_event, event, _event);
3670
3671 write_event(cmd_buffer, event, stageMask, 1);
3672 }
3673
3674 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3675 VkEvent _event,
3676 VkPipelineStageFlags stageMask)
3677 {
3678 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3679 RADV_FROM_HANDLE(radv_event, event, _event);
3680
3681 write_event(cmd_buffer, event, stageMask, 0);
3682 }
3683
3684 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3685 uint32_t eventCount,
3686 const VkEvent* pEvents,
3687 VkPipelineStageFlags srcStageMask,
3688 VkPipelineStageFlags dstStageMask,
3689 uint32_t memoryBarrierCount,
3690 const VkMemoryBarrier* pMemoryBarriers,
3691 uint32_t bufferMemoryBarrierCount,
3692 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3693 uint32_t imageMemoryBarrierCount,
3694 const VkImageMemoryBarrier* pImageMemoryBarriers)
3695 {
3696 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3697 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3698
3699 for (unsigned i = 0; i < eventCount; ++i) {
3700 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3701 uint64_t va = radv_buffer_get_va(event->bo);
3702
3703 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
3704
3705 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3706
3707 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
3708 assert(cmd_buffer->cs->cdw <= cdw_max);
3709 }
3710
3711
3712 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3713 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3714
3715 radv_handle_image_transition(cmd_buffer, image,
3716 pImageMemoryBarriers[i].oldLayout,
3717 pImageMemoryBarriers[i].newLayout,
3718 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3719 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3720 &pImageMemoryBarriers[i].subresourceRange,
3721 0);
3722 }
3723
3724 /* TODO: figure out how to do memory barriers without waiting */
3725 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3726 RADV_CMD_FLAG_INV_GLOBAL_L2 |
3727 RADV_CMD_FLAG_INV_VMEM_L1 |
3728 RADV_CMD_FLAG_INV_SMEM_L1;
3729 }