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radv: use LOAD_CONTEXT_REG when loading fast clear values
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 #include "addrlib/gfx9/chip/gfx9_enum.h"
41
42 enum {
43 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
44 RADV_PREFETCH_VS = (1 << 1),
45 RADV_PREFETCH_TCS = (1 << 2),
46 RADV_PREFETCH_TES = (1 << 3),
47 RADV_PREFETCH_GS = (1 << 4),
48 RADV_PREFETCH_PS = (1 << 5),
49 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
50 RADV_PREFETCH_TCS |
51 RADV_PREFETCH_TES |
52 RADV_PREFETCH_GS |
53 RADV_PREFETCH_PS)
54 };
55
56 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
57 struct radv_image *image,
58 VkImageLayout src_layout,
59 VkImageLayout dst_layout,
60 uint32_t src_family,
61 uint32_t dst_family,
62 const VkImageSubresourceRange *range,
63 VkImageAspectFlags pending_clears);
64
65 const struct radv_dynamic_state default_dynamic_state = {
66 .viewport = {
67 .count = 0,
68 },
69 .scissor = {
70 .count = 0,
71 },
72 .line_width = 1.0f,
73 .depth_bias = {
74 .bias = 0.0f,
75 .clamp = 0.0f,
76 .slope = 0.0f,
77 },
78 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
79 .depth_bounds = {
80 .min = 0.0f,
81 .max = 1.0f,
82 },
83 .stencil_compare_mask = {
84 .front = ~0u,
85 .back = ~0u,
86 },
87 .stencil_write_mask = {
88 .front = ~0u,
89 .back = ~0u,
90 },
91 .stencil_reference = {
92 .front = 0u,
93 .back = 0u,
94 },
95 };
96
97 static void
98 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
99 const struct radv_dynamic_state *src)
100 {
101 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
102 uint32_t copy_mask = src->mask;
103 uint32_t dest_mask = 0;
104
105 /* Make sure to copy the number of viewports/scissors because they can
106 * only be specified at pipeline creation time.
107 */
108 dest->viewport.count = src->viewport.count;
109 dest->scissor.count = src->scissor.count;
110 dest->discard_rectangle.count = src->discard_rectangle.count;
111
112 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
113 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
114 src->viewport.count * sizeof(VkViewport))) {
115 typed_memcpy(dest->viewport.viewports,
116 src->viewport.viewports,
117 src->viewport.count);
118 dest_mask |= RADV_DYNAMIC_VIEWPORT;
119 }
120 }
121
122 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
123 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
124 src->scissor.count * sizeof(VkRect2D))) {
125 typed_memcpy(dest->scissor.scissors,
126 src->scissor.scissors, src->scissor.count);
127 dest_mask |= RADV_DYNAMIC_SCISSOR;
128 }
129 }
130
131 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
132 if (dest->line_width != src->line_width) {
133 dest->line_width = src->line_width;
134 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
135 }
136 }
137
138 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
139 if (memcmp(&dest->depth_bias, &src->depth_bias,
140 sizeof(src->depth_bias))) {
141 dest->depth_bias = src->depth_bias;
142 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
143 }
144 }
145
146 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
147 if (memcmp(&dest->blend_constants, &src->blend_constants,
148 sizeof(src->blend_constants))) {
149 typed_memcpy(dest->blend_constants,
150 src->blend_constants, 4);
151 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
152 }
153 }
154
155 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
156 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
157 sizeof(src->depth_bounds))) {
158 dest->depth_bounds = src->depth_bounds;
159 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
160 }
161 }
162
163 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
164 if (memcmp(&dest->stencil_compare_mask,
165 &src->stencil_compare_mask,
166 sizeof(src->stencil_compare_mask))) {
167 dest->stencil_compare_mask = src->stencil_compare_mask;
168 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
169 }
170 }
171
172 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
173 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
174 sizeof(src->stencil_write_mask))) {
175 dest->stencil_write_mask = src->stencil_write_mask;
176 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
177 }
178 }
179
180 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
181 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
182 sizeof(src->stencil_reference))) {
183 dest->stencil_reference = src->stencil_reference;
184 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
185 }
186 }
187
188 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
189 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
190 src->discard_rectangle.count * sizeof(VkRect2D))) {
191 typed_memcpy(dest->discard_rectangle.rectangles,
192 src->discard_rectangle.rectangles,
193 src->discard_rectangle.count);
194 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
195 }
196 }
197
198 cmd_buffer->state.dirty |= dest_mask;
199 }
200
201 static void
202 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
203 struct radv_pipeline *pipeline)
204 {
205 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
206 struct radv_shader_info *info;
207
208 if (!pipeline->streamout_shader)
209 return;
210
211 info = &pipeline->streamout_shader->info.info;
212 for (int i = 0; i < MAX_SO_BUFFERS; i++)
213 so->stride_in_dw[i] = info->so.strides[i];
214
215 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
216 }
217
218 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
219 {
220 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
221 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
222 }
223
224 enum ring_type radv_queue_family_to_ring(int f) {
225 switch (f) {
226 case RADV_QUEUE_GENERAL:
227 return RING_GFX;
228 case RADV_QUEUE_COMPUTE:
229 return RING_COMPUTE;
230 case RADV_QUEUE_TRANSFER:
231 return RING_DMA;
232 default:
233 unreachable("Unknown queue family");
234 }
235 }
236
237 static VkResult radv_create_cmd_buffer(
238 struct radv_device * device,
239 struct radv_cmd_pool * pool,
240 VkCommandBufferLevel level,
241 VkCommandBuffer* pCommandBuffer)
242 {
243 struct radv_cmd_buffer *cmd_buffer;
244 unsigned ring;
245 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
246 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
247 if (cmd_buffer == NULL)
248 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
249
250 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
251 cmd_buffer->device = device;
252 cmd_buffer->pool = pool;
253 cmd_buffer->level = level;
254
255 if (pool) {
256 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
257 cmd_buffer->queue_family_index = pool->queue_family_index;
258
259 } else {
260 /* Init the pool_link so we can safely call list_del when we destroy
261 * the command buffer
262 */
263 list_inithead(&cmd_buffer->pool_link);
264 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
265 }
266
267 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
268
269 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
270 if (!cmd_buffer->cs) {
271 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
272 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
273 }
274
275 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
276
277 list_inithead(&cmd_buffer->upload.list);
278
279 return VK_SUCCESS;
280 }
281
282 static void
283 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
284 {
285 list_del(&cmd_buffer->pool_link);
286
287 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
288 &cmd_buffer->upload.list, list) {
289 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
290 list_del(&up->list);
291 free(up);
292 }
293
294 if (cmd_buffer->upload.upload_bo)
295 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
296 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
297
298 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
299 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
300
301 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
302 }
303
304 static VkResult
305 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
306 {
307
308 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
309
310 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
311 &cmd_buffer->upload.list, list) {
312 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
313 list_del(&up->list);
314 free(up);
315 }
316
317 cmd_buffer->push_constant_stages = 0;
318 cmd_buffer->scratch_size_needed = 0;
319 cmd_buffer->compute_scratch_size_needed = 0;
320 cmd_buffer->esgs_ring_size_needed = 0;
321 cmd_buffer->gsvs_ring_size_needed = 0;
322 cmd_buffer->tess_rings_needed = false;
323 cmd_buffer->sample_positions_needed = false;
324
325 if (cmd_buffer->upload.upload_bo)
326 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
327 cmd_buffer->upload.upload_bo);
328 cmd_buffer->upload.offset = 0;
329
330 cmd_buffer->record_result = VK_SUCCESS;
331
332 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
333 cmd_buffer->descriptors[i].dirty = 0;
334 cmd_buffer->descriptors[i].valid = 0;
335 cmd_buffer->descriptors[i].push_dirty = false;
336 }
337
338 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
339 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
340 unsigned eop_bug_offset;
341 void *fence_ptr;
342
343 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
344 &cmd_buffer->gfx9_fence_offset,
345 &fence_ptr);
346 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
347
348 /* Allocate a buffer for the EOP bug on GFX9. */
349 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 0,
350 &eop_bug_offset, &fence_ptr);
351 cmd_buffer->gfx9_eop_bug_va =
352 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
353 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
354 }
355
356 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
357
358 return cmd_buffer->record_result;
359 }
360
361 static bool
362 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
363 uint64_t min_needed)
364 {
365 uint64_t new_size;
366 struct radeon_winsys_bo *bo;
367 struct radv_cmd_buffer_upload *upload;
368 struct radv_device *device = cmd_buffer->device;
369
370 new_size = MAX2(min_needed, 16 * 1024);
371 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
372
373 bo = device->ws->buffer_create(device->ws,
374 new_size, 4096,
375 RADEON_DOMAIN_GTT,
376 RADEON_FLAG_CPU_ACCESS|
377 RADEON_FLAG_NO_INTERPROCESS_SHARING |
378 RADEON_FLAG_32BIT);
379
380 if (!bo) {
381 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
382 return false;
383 }
384
385 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
386 if (cmd_buffer->upload.upload_bo) {
387 upload = malloc(sizeof(*upload));
388
389 if (!upload) {
390 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
391 device->ws->buffer_destroy(bo);
392 return false;
393 }
394
395 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
396 list_add(&upload->list, &cmd_buffer->upload.list);
397 }
398
399 cmd_buffer->upload.upload_bo = bo;
400 cmd_buffer->upload.size = new_size;
401 cmd_buffer->upload.offset = 0;
402 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
403
404 if (!cmd_buffer->upload.map) {
405 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
406 return false;
407 }
408
409 return true;
410 }
411
412 bool
413 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
414 unsigned size,
415 unsigned alignment,
416 unsigned *out_offset,
417 void **ptr)
418 {
419 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
420 if (offset + size > cmd_buffer->upload.size) {
421 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
422 return false;
423 offset = 0;
424 }
425
426 *out_offset = offset;
427 *ptr = cmd_buffer->upload.map + offset;
428
429 cmd_buffer->upload.offset = offset + size;
430 return true;
431 }
432
433 bool
434 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
435 unsigned size, unsigned alignment,
436 const void *data, unsigned *out_offset)
437 {
438 uint8_t *ptr;
439
440 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
441 out_offset, (void **)&ptr))
442 return false;
443
444 if (ptr)
445 memcpy(ptr, data, size);
446
447 return true;
448 }
449
450 static void
451 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
452 unsigned count, const uint32_t *data)
453 {
454 struct radeon_cmdbuf *cs = cmd_buffer->cs;
455
456 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
457
458 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
459 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
460 S_370_WR_CONFIRM(1) |
461 S_370_ENGINE_SEL(V_370_ME));
462 radeon_emit(cs, va);
463 radeon_emit(cs, va >> 32);
464 radeon_emit_array(cs, data, count);
465 }
466
467 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
468 {
469 struct radv_device *device = cmd_buffer->device;
470 struct radeon_cmdbuf *cs = cmd_buffer->cs;
471 uint64_t va;
472
473 va = radv_buffer_get_va(device->trace_bo);
474 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
475 va += 4;
476
477 ++cmd_buffer->state.trace_id;
478 radv_emit_write_data_packet(cmd_buffer, va, 1,
479 &cmd_buffer->state.trace_id);
480
481 radeon_check_space(cmd_buffer->device->ws, cs, 2);
482
483 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
484 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
485 }
486
487 static void
488 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
489 enum radv_cmd_flush_bits flags)
490 {
491 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
492 uint32_t *ptr = NULL;
493 uint64_t va = 0;
494
495 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
496 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
497
498 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
499 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
500 cmd_buffer->gfx9_fence_offset;
501 ptr = &cmd_buffer->gfx9_fence_idx;
502 }
503
504 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
505
506 /* Force wait for graphics or compute engines to be idle. */
507 si_cs_emit_cache_flush(cmd_buffer->cs,
508 cmd_buffer->device->physical_device->rad_info.chip_class,
509 ptr, va,
510 radv_cmd_buffer_uses_mec(cmd_buffer),
511 flags, cmd_buffer->gfx9_eop_bug_va);
512 }
513
514 if (unlikely(cmd_buffer->device->trace_bo))
515 radv_cmd_buffer_trace_emit(cmd_buffer);
516 }
517
518 static void
519 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
520 struct radv_pipeline *pipeline, enum ring_type ring)
521 {
522 struct radv_device *device = cmd_buffer->device;
523 uint32_t data[2];
524 uint64_t va;
525
526 va = radv_buffer_get_va(device->trace_bo);
527
528 switch (ring) {
529 case RING_GFX:
530 va += 8;
531 break;
532 case RING_COMPUTE:
533 va += 16;
534 break;
535 default:
536 assert(!"invalid ring type");
537 }
538
539 data[0] = (uintptr_t)pipeline;
540 data[1] = (uintptr_t)pipeline >> 32;
541
542 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
543 }
544
545 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
546 VkPipelineBindPoint bind_point,
547 struct radv_descriptor_set *set,
548 unsigned idx)
549 {
550 struct radv_descriptor_state *descriptors_state =
551 radv_get_descriptors_state(cmd_buffer, bind_point);
552
553 descriptors_state->sets[idx] = set;
554
555 descriptors_state->valid |= (1u << idx); /* active descriptors */
556 descriptors_state->dirty |= (1u << idx);
557 }
558
559 static void
560 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
561 VkPipelineBindPoint bind_point)
562 {
563 struct radv_descriptor_state *descriptors_state =
564 radv_get_descriptors_state(cmd_buffer, bind_point);
565 struct radv_device *device = cmd_buffer->device;
566 uint32_t data[MAX_SETS * 2] = {};
567 uint64_t va;
568 unsigned i;
569 va = radv_buffer_get_va(device->trace_bo) + 24;
570
571 for_each_bit(i, descriptors_state->valid) {
572 struct radv_descriptor_set *set = descriptors_state->sets[i];
573 data[i * 2] = (uintptr_t)set;
574 data[i * 2 + 1] = (uintptr_t)set >> 32;
575 }
576
577 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
578 }
579
580 struct radv_userdata_info *
581 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
582 gl_shader_stage stage,
583 int idx)
584 {
585 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
586 return &shader->info.user_sgprs_locs.shader_data[idx];
587 }
588
589 static void
590 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
591 struct radv_pipeline *pipeline,
592 gl_shader_stage stage,
593 int idx, uint64_t va)
594 {
595 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
596 uint32_t base_reg = pipeline->user_data_0[stage];
597 if (loc->sgpr_idx == -1)
598 return;
599
600 assert(loc->num_sgprs == (HAVE_32BIT_POINTERS ? 1 : 2));
601 assert(!loc->indirect);
602
603 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
604 base_reg + loc->sgpr_idx * 4, va, false);
605 }
606
607 static void
608 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
609 struct radv_pipeline *pipeline,
610 struct radv_descriptor_state *descriptors_state,
611 gl_shader_stage stage)
612 {
613 struct radv_device *device = cmd_buffer->device;
614 struct radeon_cmdbuf *cs = cmd_buffer->cs;
615 uint32_t sh_base = pipeline->user_data_0[stage];
616 struct radv_userdata_locations *locs =
617 &pipeline->shaders[stage]->info.user_sgprs_locs;
618 unsigned mask = locs->descriptor_sets_enabled;
619
620 mask &= descriptors_state->dirty & descriptors_state->valid;
621
622 while (mask) {
623 int start, count;
624
625 u_bit_scan_consecutive_range(&mask, &start, &count);
626
627 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
628 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
629
630 radv_emit_shader_pointer_head(cs, sh_offset, count,
631 HAVE_32BIT_POINTERS);
632 for (int i = 0; i < count; i++) {
633 struct radv_descriptor_set *set =
634 descriptors_state->sets[start + i];
635
636 radv_emit_shader_pointer_body(device, cs, set->va,
637 HAVE_32BIT_POINTERS);
638 }
639 }
640 }
641
642 static void
643 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
644 struct radv_pipeline *pipeline)
645 {
646 int num_samples = pipeline->graphics.ms.num_samples;
647 struct radv_multisample_state *ms = &pipeline->graphics.ms;
648 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
649
650 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
651 cmd_buffer->sample_positions_needed = true;
652
653 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
654 return;
655
656 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
657 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
658 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
659
660 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
661
662 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
663
664 /* GFX9: Flush DFSM when the AA mode changes. */
665 if (cmd_buffer->device->dfsm_allowed) {
666 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
667 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
668 }
669 }
670
671 static void
672 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
673 struct radv_shader_variant *shader)
674 {
675 uint64_t va;
676
677 if (!shader)
678 return;
679
680 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
681
682 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
683 }
684
685 static void
686 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
687 struct radv_pipeline *pipeline,
688 bool vertex_stage_only)
689 {
690 struct radv_cmd_state *state = &cmd_buffer->state;
691 uint32_t mask = state->prefetch_L2_mask;
692
693 if (vertex_stage_only) {
694 /* Fast prefetch path for starting draws as soon as possible.
695 */
696 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
697 RADV_PREFETCH_VBO_DESCRIPTORS);
698 }
699
700 if (mask & RADV_PREFETCH_VS)
701 radv_emit_shader_prefetch(cmd_buffer,
702 pipeline->shaders[MESA_SHADER_VERTEX]);
703
704 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
705 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
706
707 if (mask & RADV_PREFETCH_TCS)
708 radv_emit_shader_prefetch(cmd_buffer,
709 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
710
711 if (mask & RADV_PREFETCH_TES)
712 radv_emit_shader_prefetch(cmd_buffer,
713 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
714
715 if (mask & RADV_PREFETCH_GS) {
716 radv_emit_shader_prefetch(cmd_buffer,
717 pipeline->shaders[MESA_SHADER_GEOMETRY]);
718 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
719 }
720
721 if (mask & RADV_PREFETCH_PS)
722 radv_emit_shader_prefetch(cmd_buffer,
723 pipeline->shaders[MESA_SHADER_FRAGMENT]);
724
725 state->prefetch_L2_mask &= ~mask;
726 }
727
728 static void
729 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
730 {
731 if (!cmd_buffer->device->physical_device->rbplus_allowed)
732 return;
733
734 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
735 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
736 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
737
738 unsigned sx_ps_downconvert = 0;
739 unsigned sx_blend_opt_epsilon = 0;
740 unsigned sx_blend_opt_control = 0;
741
742 for (unsigned i = 0; i < subpass->color_count; ++i) {
743 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
744 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
745 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
746 continue;
747 }
748
749 int idx = subpass->color_attachments[i].attachment;
750 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
751
752 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
753 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
754 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
755 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
756
757 bool has_alpha, has_rgb;
758
759 /* Set if RGB and A are present. */
760 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
761
762 if (format == V_028C70_COLOR_8 ||
763 format == V_028C70_COLOR_16 ||
764 format == V_028C70_COLOR_32)
765 has_rgb = !has_alpha;
766 else
767 has_rgb = true;
768
769 /* Check the colormask and export format. */
770 if (!(colormask & 0x7))
771 has_rgb = false;
772 if (!(colormask & 0x8))
773 has_alpha = false;
774
775 if (spi_format == V_028714_SPI_SHADER_ZERO) {
776 has_rgb = false;
777 has_alpha = false;
778 }
779
780 /* Disable value checking for disabled channels. */
781 if (!has_rgb)
782 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
783 if (!has_alpha)
784 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
785
786 /* Enable down-conversion for 32bpp and smaller formats. */
787 switch (format) {
788 case V_028C70_COLOR_8:
789 case V_028C70_COLOR_8_8:
790 case V_028C70_COLOR_8_8_8_8:
791 /* For 1 and 2-channel formats, use the superset thereof. */
792 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
793 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
794 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
795 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
796 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
797 }
798 break;
799
800 case V_028C70_COLOR_5_6_5:
801 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
802 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
803 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
804 }
805 break;
806
807 case V_028C70_COLOR_1_5_5_5:
808 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
809 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
810 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
811 }
812 break;
813
814 case V_028C70_COLOR_4_4_4_4:
815 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
816 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
817 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
818 }
819 break;
820
821 case V_028C70_COLOR_32:
822 if (swap == V_028C70_SWAP_STD &&
823 spi_format == V_028714_SPI_SHADER_32_R)
824 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
825 else if (swap == V_028C70_SWAP_ALT_REV &&
826 spi_format == V_028714_SPI_SHADER_32_AR)
827 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
828 break;
829
830 case V_028C70_COLOR_16:
831 case V_028C70_COLOR_16_16:
832 /* For 1-channel formats, use the superset thereof. */
833 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
834 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
835 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
836 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
837 if (swap == V_028C70_SWAP_STD ||
838 swap == V_028C70_SWAP_STD_REV)
839 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
840 else
841 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
842 }
843 break;
844
845 case V_028C70_COLOR_10_11_11:
846 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
847 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
848 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
849 }
850 break;
851
852 case V_028C70_COLOR_2_10_10_10:
853 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
854 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
855 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
856 }
857 break;
858 }
859 }
860
861 for (unsigned i = subpass->color_count; i < 8; ++i) {
862 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
863 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
864 }
865 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
866 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
867 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
868 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
869 }
870
871 static void
872 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
873 {
874 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
875
876 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
877 return;
878
879 radv_update_multisample_state(cmd_buffer, pipeline);
880
881 cmd_buffer->scratch_size_needed =
882 MAX2(cmd_buffer->scratch_size_needed,
883 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
884
885 if (!cmd_buffer->state.emitted_pipeline ||
886 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
887 pipeline->graphics.can_use_guardband)
888 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
889
890 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
891
892 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
893 if (!pipeline->shaders[i])
894 continue;
895
896 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
897 pipeline->shaders[i]->bo);
898 }
899
900 if (radv_pipeline_has_gs(pipeline))
901 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
902 pipeline->gs_copy_shader->bo);
903
904 if (unlikely(cmd_buffer->device->trace_bo))
905 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
906
907 cmd_buffer->state.emitted_pipeline = pipeline;
908
909 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
910 }
911
912 static void
913 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
914 {
915 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
916 cmd_buffer->state.dynamic.viewport.viewports);
917 }
918
919 static void
920 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
921 {
922 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
923
924 si_write_scissors(cmd_buffer->cs, 0, count,
925 cmd_buffer->state.dynamic.scissor.scissors,
926 cmd_buffer->state.dynamic.viewport.viewports,
927 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
928 }
929
930 static void
931 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
932 {
933 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
934 return;
935
936 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
937 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
938 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
939 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
940 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
941 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
942 S_028214_BR_Y(rect.offset.y + rect.extent.height));
943 }
944 }
945
946 static void
947 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
948 {
949 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
950
951 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
952 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
953 }
954
955 static void
956 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
957 {
958 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
959
960 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
961 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
962 }
963
964 static void
965 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
966 {
967 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
968
969 radeon_set_context_reg_seq(cmd_buffer->cs,
970 R_028430_DB_STENCILREFMASK, 2);
971 radeon_emit(cmd_buffer->cs,
972 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
973 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
974 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
975 S_028430_STENCILOPVAL(1));
976 radeon_emit(cmd_buffer->cs,
977 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
978 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
979 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
980 S_028434_STENCILOPVAL_BF(1));
981 }
982
983 static void
984 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
985 {
986 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
987
988 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
989 fui(d->depth_bounds.min));
990 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
991 fui(d->depth_bounds.max));
992 }
993
994 static void
995 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
996 {
997 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
998 unsigned slope = fui(d->depth_bias.slope * 16.0f);
999 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1000
1001
1002 radeon_set_context_reg_seq(cmd_buffer->cs,
1003 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1004 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1005 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1006 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1007 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1008 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1009 }
1010
1011 static void
1012 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1013 int index,
1014 struct radv_attachment_info *att,
1015 struct radv_image *image,
1016 VkImageLayout layout)
1017 {
1018 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1019 struct radv_color_buffer_info *cb = &att->cb;
1020 uint32_t cb_color_info = cb->cb_color_info;
1021
1022 if (!radv_layout_dcc_compressed(image, layout,
1023 radv_image_queue_family_mask(image,
1024 cmd_buffer->queue_family_index,
1025 cmd_buffer->queue_family_index))) {
1026 cb_color_info &= C_028C70_DCC_ENABLE;
1027 }
1028
1029 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1030 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1031 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1032 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1033 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1034 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1035 radeon_emit(cmd_buffer->cs, cb_color_info);
1036 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1037 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1038 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1039 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1040 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1041 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1042
1043 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1044 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1045 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1046
1047 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1048 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1049 } else {
1050 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1051 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1052 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1053 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1054 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1055 radeon_emit(cmd_buffer->cs, cb_color_info);
1056 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1057 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1058 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1059 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1060 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1061 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1062
1063 if (is_vi) { /* DCC BASE */
1064 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1065 }
1066 }
1067 }
1068
1069 static void
1070 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1071 struct radv_ds_buffer_info *ds,
1072 struct radv_image *image, VkImageLayout layout,
1073 bool requires_cond_write)
1074 {
1075 uint32_t db_z_info = ds->db_z_info;
1076 uint32_t db_z_info_reg;
1077
1078 if (!radv_image_is_tc_compat_htile(image))
1079 return;
1080
1081 if (!radv_layout_has_htile(image, layout,
1082 radv_image_queue_family_mask(image,
1083 cmd_buffer->queue_family_index,
1084 cmd_buffer->queue_family_index))) {
1085 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1086 }
1087
1088 db_z_info &= C_028040_ZRANGE_PRECISION;
1089
1090 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1091 db_z_info_reg = R_028038_DB_Z_INFO;
1092 } else {
1093 db_z_info_reg = R_028040_DB_Z_INFO;
1094 }
1095
1096 /* When we don't know the last fast clear value we need to emit a
1097 * conditional packet, otherwise we can update DB_Z_INFO directly.
1098 */
1099 if (requires_cond_write) {
1100 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_WRITE, 7, 0));
1101
1102 const uint32_t write_space = 0 << 8; /* register */
1103 const uint32_t poll_space = 1 << 4; /* memory */
1104 const uint32_t function = 3 << 0; /* equal to the reference */
1105 const uint32_t options = write_space | poll_space | function;
1106 radeon_emit(cmd_buffer->cs, options);
1107
1108 /* poll address - location of the depth clear value */
1109 uint64_t va = radv_buffer_get_va(image->bo);
1110 va += image->offset + image->clear_value_offset;
1111
1112 /* In presence of stencil format, we have to adjust the base
1113 * address because the first value is the stencil clear value.
1114 */
1115 if (vk_format_is_stencil(image->vk_format))
1116 va += 4;
1117
1118 radeon_emit(cmd_buffer->cs, va);
1119 radeon_emit(cmd_buffer->cs, va >> 32);
1120
1121 radeon_emit(cmd_buffer->cs, fui(0.0f)); /* reference value */
1122 radeon_emit(cmd_buffer->cs, (uint32_t)-1); /* comparison mask */
1123 radeon_emit(cmd_buffer->cs, db_z_info_reg >> 2); /* write address low */
1124 radeon_emit(cmd_buffer->cs, 0u); /* write address high */
1125 radeon_emit(cmd_buffer->cs, db_z_info);
1126 } else {
1127 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1128 }
1129 }
1130
1131 static void
1132 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1133 struct radv_ds_buffer_info *ds,
1134 struct radv_image *image,
1135 VkImageLayout layout)
1136 {
1137 uint32_t db_z_info = ds->db_z_info;
1138 uint32_t db_stencil_info = ds->db_stencil_info;
1139
1140 if (!radv_layout_has_htile(image, layout,
1141 radv_image_queue_family_mask(image,
1142 cmd_buffer->queue_family_index,
1143 cmd_buffer->queue_family_index))) {
1144 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1145 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1146 }
1147
1148 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1149 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1150
1151
1152 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1153 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1154 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1155 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1156 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1157
1158 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1159 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1160 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1161 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1162 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1163 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1164 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1165 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1166 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1167 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1168 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1169
1170 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1171 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1172 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1173 } else {
1174 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1175
1176 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1177 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1178 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1179 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1180 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1181 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1182 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1183 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1184 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1185 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1186
1187 }
1188
1189 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1190 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1191
1192 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1193 ds->pa_su_poly_offset_db_fmt_cntl);
1194 }
1195
1196 /**
1197 * Update the fast clear depth/stencil values if the image is bound as a
1198 * depth/stencil buffer.
1199 */
1200 static void
1201 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1202 struct radv_image *image,
1203 VkClearDepthStencilValue ds_clear_value,
1204 VkImageAspectFlags aspects)
1205 {
1206 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1207 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1208 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1209 struct radv_attachment_info *att;
1210 uint32_t att_idx;
1211
1212 if (!framebuffer || !subpass)
1213 return;
1214
1215 att_idx = subpass->depth_stencil_attachment.attachment;
1216 if (att_idx == VK_ATTACHMENT_UNUSED)
1217 return;
1218
1219 att = &framebuffer->attachments[att_idx];
1220 if (att->attachment->image != image)
1221 return;
1222
1223 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1224 radeon_emit(cs, ds_clear_value.stencil);
1225 radeon_emit(cs, fui(ds_clear_value.depth));
1226
1227 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1228 * only needed when clearing Z to 0.0.
1229 */
1230 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1231 ds_clear_value.depth == 0.0) {
1232 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1233
1234 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1235 layout, false);
1236 }
1237 }
1238
1239 /**
1240 * Set the clear depth/stencil values to the image's metadata.
1241 */
1242 static void
1243 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1244 struct radv_image *image,
1245 VkClearDepthStencilValue ds_clear_value,
1246 VkImageAspectFlags aspects)
1247 {
1248 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1249 uint64_t va = radv_buffer_get_va(image->bo);
1250 unsigned reg_offset = 0, reg_count = 0;
1251
1252 va += image->offset + image->clear_value_offset;
1253
1254 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1255 ++reg_count;
1256 } else {
1257 ++reg_offset;
1258 va += 4;
1259 }
1260 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1261 ++reg_count;
1262
1263 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1264 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1265 S_370_WR_CONFIRM(1) |
1266 S_370_ENGINE_SEL(V_370_PFP));
1267 radeon_emit(cs, va);
1268 radeon_emit(cs, va >> 32);
1269 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1270 radeon_emit(cs, ds_clear_value.stencil);
1271 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1272 radeon_emit(cs, fui(ds_clear_value.depth));
1273 }
1274
1275 /**
1276 * Update the clear depth/stencil values for this image.
1277 */
1278 void
1279 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1280 struct radv_image *image,
1281 VkClearDepthStencilValue ds_clear_value,
1282 VkImageAspectFlags aspects)
1283 {
1284 assert(radv_image_has_htile(image));
1285
1286 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1287
1288 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1289 aspects);
1290 }
1291
1292 /**
1293 * Load the clear depth/stencil values from the image's metadata.
1294 */
1295 static void
1296 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1297 struct radv_image *image)
1298 {
1299 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1300 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1301 uint64_t va = radv_buffer_get_va(image->bo);
1302 unsigned reg_offset = 0, reg_count = 0;
1303
1304 va += image->offset + image->clear_value_offset;
1305
1306 if (!radv_image_has_htile(image))
1307 return;
1308
1309 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1310 ++reg_count;
1311 } else {
1312 ++reg_offset;
1313 va += 4;
1314 }
1315 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1316 ++reg_count;
1317
1318 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1319
1320 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1321 radeon_emit(cs, va);
1322 radeon_emit(cs, va >> 32);
1323 radeon_emit(cs, (reg >> 2) - CONTEXT_SPACE_START);
1324 radeon_emit(cs, reg_count);
1325 }
1326
1327 /*
1328 * With DCC some colors don't require CMASK elimination before being
1329 * used as a texture. This sets a predicate value to determine if the
1330 * cmask eliminate is required.
1331 */
1332 void
1333 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1334 struct radv_image *image,
1335 bool value)
1336 {
1337 uint64_t pred_val = value;
1338 uint64_t va = radv_buffer_get_va(image->bo);
1339 va += image->offset + image->dcc_pred_offset;
1340
1341 assert(radv_image_has_dcc(image));
1342
1343 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1344 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1345 S_370_WR_CONFIRM(1) |
1346 S_370_ENGINE_SEL(V_370_PFP));
1347 radeon_emit(cmd_buffer->cs, va);
1348 radeon_emit(cmd_buffer->cs, va >> 32);
1349 radeon_emit(cmd_buffer->cs, pred_val);
1350 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1351 }
1352
1353 /**
1354 * Update the fast clear color values if the image is bound as a color buffer.
1355 */
1356 static void
1357 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1358 struct radv_image *image,
1359 int cb_idx,
1360 uint32_t color_values[2])
1361 {
1362 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1363 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1364 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1365 struct radv_attachment_info *att;
1366 uint32_t att_idx;
1367
1368 if (!framebuffer || !subpass)
1369 return;
1370
1371 att_idx = subpass->color_attachments[cb_idx].attachment;
1372 if (att_idx == VK_ATTACHMENT_UNUSED)
1373 return;
1374
1375 att = &framebuffer->attachments[att_idx];
1376 if (att->attachment->image != image)
1377 return;
1378
1379 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1380 radeon_emit(cs, color_values[0]);
1381 radeon_emit(cs, color_values[1]);
1382 }
1383
1384 /**
1385 * Set the clear color values to the image's metadata.
1386 */
1387 static void
1388 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1389 struct radv_image *image,
1390 uint32_t color_values[2])
1391 {
1392 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1393 uint64_t va = radv_buffer_get_va(image->bo);
1394
1395 va += image->offset + image->clear_value_offset;
1396
1397 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1398
1399 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1400 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1401 S_370_WR_CONFIRM(1) |
1402 S_370_ENGINE_SEL(V_370_PFP));
1403 radeon_emit(cs, va);
1404 radeon_emit(cs, va >> 32);
1405 radeon_emit(cs, color_values[0]);
1406 radeon_emit(cs, color_values[1]);
1407 }
1408
1409 /**
1410 * Update the clear color values for this image.
1411 */
1412 void
1413 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1414 struct radv_image *image,
1415 int cb_idx,
1416 uint32_t color_values[2])
1417 {
1418 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1419
1420 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
1421
1422 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1423 color_values);
1424 }
1425
1426 /**
1427 * Load the clear color values from the image's metadata.
1428 */
1429 static void
1430 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1431 struct radv_image *image,
1432 int cb_idx)
1433 {
1434 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1435 uint64_t va = radv_buffer_get_va(image->bo);
1436
1437 va += image->offset + image->clear_value_offset;
1438
1439 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1440 return;
1441
1442 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1443
1444 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1445 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1446 radeon_emit(cs, va);
1447 radeon_emit(cs, va >> 32);
1448 radeon_emit(cs, (reg >> 2) - CONTEXT_SPACE_START);
1449 radeon_emit(cs, 2);
1450 } else {
1451 /* TODO: Figure out how to use LOAD_CONTEXT_REG on SI/CIK. */
1452 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1453 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1454 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1455 COPY_DATA_COUNT_SEL);
1456 radeon_emit(cs, va);
1457 radeon_emit(cs, va >> 32);
1458 radeon_emit(cs, reg >> 2);
1459 radeon_emit(cs, 0);
1460
1461 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1462 radeon_emit(cs, 0);
1463 }
1464 }
1465
1466 static void
1467 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1468 {
1469 int i;
1470 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1471 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1472
1473 /* this may happen for inherited secondary recording */
1474 if (!framebuffer)
1475 return;
1476
1477 for (i = 0; i < 8; ++i) {
1478 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1479 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1480 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1481 continue;
1482 }
1483
1484 int idx = subpass->color_attachments[i].attachment;
1485 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1486 struct radv_image *image = att->attachment->image;
1487 VkImageLayout layout = subpass->color_attachments[i].layout;
1488
1489 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1490
1491 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1492 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1493
1494 radv_load_color_clear_metadata(cmd_buffer, image, i);
1495 }
1496
1497 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1498 int idx = subpass->depth_stencil_attachment.attachment;
1499 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1500 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1501 struct radv_image *image = att->attachment->image;
1502 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1503 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1504 cmd_buffer->queue_family_index,
1505 cmd_buffer->queue_family_index);
1506 /* We currently don't support writing decompressed HTILE */
1507 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1508 radv_layout_is_htile_compressed(image, layout, queue_mask));
1509
1510 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1511
1512 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1513 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1514 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1515 }
1516 radv_load_ds_clear_metadata(cmd_buffer, image);
1517 } else {
1518 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1519 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1520 else
1521 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1522
1523 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1524 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1525 }
1526 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1527 S_028208_BR_X(framebuffer->width) |
1528 S_028208_BR_Y(framebuffer->height));
1529
1530 if (cmd_buffer->device->dfsm_allowed) {
1531 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1532 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1533 }
1534
1535 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1536 }
1537
1538 static void
1539 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1540 {
1541 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1542 struct radv_cmd_state *state = &cmd_buffer->state;
1543
1544 if (state->index_type != state->last_index_type) {
1545 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1546 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1547 2, state->index_type);
1548 } else {
1549 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1550 radeon_emit(cs, state->index_type);
1551 }
1552
1553 state->last_index_type = state->index_type;
1554 }
1555
1556 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1557 radeon_emit(cs, state->index_va);
1558 radeon_emit(cs, state->index_va >> 32);
1559
1560 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1561 radeon_emit(cs, state->max_index_count);
1562
1563 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1564 }
1565
1566 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1567 {
1568 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1569 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1570 uint32_t pa_sc_mode_cntl_1 =
1571 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1572 uint32_t db_count_control;
1573
1574 if(!cmd_buffer->state.active_occlusion_queries) {
1575 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1576 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1577 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1578 has_perfect_queries) {
1579 /* Re-enable out-of-order rasterization if the
1580 * bound pipeline supports it and if it's has
1581 * been disabled before starting any perfect
1582 * occlusion queries.
1583 */
1584 radeon_set_context_reg(cmd_buffer->cs,
1585 R_028A4C_PA_SC_MODE_CNTL_1,
1586 pa_sc_mode_cntl_1);
1587 }
1588 }
1589 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1590 } else {
1591 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1592 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1593
1594 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1595 db_count_control =
1596 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1597 S_028004_SAMPLE_RATE(sample_rate) |
1598 S_028004_ZPASS_ENABLE(1) |
1599 S_028004_SLICE_EVEN_ENABLE(1) |
1600 S_028004_SLICE_ODD_ENABLE(1);
1601
1602 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1603 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1604 has_perfect_queries) {
1605 /* If the bound pipeline has enabled
1606 * out-of-order rasterization, we should
1607 * disable it before starting any perfect
1608 * occlusion queries.
1609 */
1610 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1611
1612 radeon_set_context_reg(cmd_buffer->cs,
1613 R_028A4C_PA_SC_MODE_CNTL_1,
1614 pa_sc_mode_cntl_1);
1615 }
1616 } else {
1617 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1618 S_028004_SAMPLE_RATE(sample_rate);
1619 }
1620 }
1621
1622 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1623 }
1624
1625 static void
1626 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1627 {
1628 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1629
1630 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1631 radv_emit_viewport(cmd_buffer);
1632
1633 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1634 !cmd_buffer->device->physical_device->has_scissor_bug)
1635 radv_emit_scissor(cmd_buffer);
1636
1637 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1638 radv_emit_line_width(cmd_buffer);
1639
1640 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1641 radv_emit_blend_constants(cmd_buffer);
1642
1643 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1644 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1645 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1646 radv_emit_stencil(cmd_buffer);
1647
1648 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1649 radv_emit_depth_bounds(cmd_buffer);
1650
1651 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1652 radv_emit_depth_bias(cmd_buffer);
1653
1654 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1655 radv_emit_discard_rectangle(cmd_buffer);
1656
1657 cmd_buffer->state.dirty &= ~states;
1658 }
1659
1660 static void
1661 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1662 VkPipelineBindPoint bind_point)
1663 {
1664 struct radv_descriptor_state *descriptors_state =
1665 radv_get_descriptors_state(cmd_buffer, bind_point);
1666 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1667 unsigned bo_offset;
1668
1669 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1670 set->mapped_ptr,
1671 &bo_offset))
1672 return;
1673
1674 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1675 set->va += bo_offset;
1676 }
1677
1678 static void
1679 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1680 VkPipelineBindPoint bind_point)
1681 {
1682 struct radv_descriptor_state *descriptors_state =
1683 radv_get_descriptors_state(cmd_buffer, bind_point);
1684 uint8_t ptr_size = HAVE_32BIT_POINTERS ? 1 : 2;
1685 uint32_t size = MAX_SETS * 4 * ptr_size;
1686 uint32_t offset;
1687 void *ptr;
1688
1689 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1690 256, &offset, &ptr))
1691 return;
1692
1693 for (unsigned i = 0; i < MAX_SETS; i++) {
1694 uint32_t *uptr = ((uint32_t *)ptr) + i * ptr_size;
1695 uint64_t set_va = 0;
1696 struct radv_descriptor_set *set = descriptors_state->sets[i];
1697 if (descriptors_state->valid & (1u << i))
1698 set_va = set->va;
1699 uptr[0] = set_va & 0xffffffff;
1700 if (ptr_size == 2)
1701 uptr[1] = set_va >> 32;
1702 }
1703
1704 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1705 va += offset;
1706
1707 if (cmd_buffer->state.pipeline) {
1708 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1709 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1710 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1711
1712 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1713 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1714 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1715
1716 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1717 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1718 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1719
1720 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1721 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1722 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1723
1724 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1725 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1726 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1727 }
1728
1729 if (cmd_buffer->state.compute_pipeline)
1730 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1731 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1732 }
1733
1734 static void
1735 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1736 VkShaderStageFlags stages)
1737 {
1738 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1739 VK_PIPELINE_BIND_POINT_COMPUTE :
1740 VK_PIPELINE_BIND_POINT_GRAPHICS;
1741 struct radv_descriptor_state *descriptors_state =
1742 radv_get_descriptors_state(cmd_buffer, bind_point);
1743 struct radv_cmd_state *state = &cmd_buffer->state;
1744 bool flush_indirect_descriptors;
1745
1746 if (!descriptors_state->dirty)
1747 return;
1748
1749 if (descriptors_state->push_dirty)
1750 radv_flush_push_descriptors(cmd_buffer, bind_point);
1751
1752 flush_indirect_descriptors =
1753 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
1754 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
1755 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
1756 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
1757
1758 if (flush_indirect_descriptors)
1759 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1760
1761 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1762 cmd_buffer->cs,
1763 MAX_SETS * MESA_SHADER_STAGES * 4);
1764
1765 if (cmd_buffer->state.pipeline) {
1766 radv_foreach_stage(stage, stages) {
1767 if (!cmd_buffer->state.pipeline->shaders[stage])
1768 continue;
1769
1770 radv_emit_descriptor_pointers(cmd_buffer,
1771 cmd_buffer->state.pipeline,
1772 descriptors_state, stage);
1773 }
1774 }
1775
1776 if (cmd_buffer->state.compute_pipeline &&
1777 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
1778 radv_emit_descriptor_pointers(cmd_buffer,
1779 cmd_buffer->state.compute_pipeline,
1780 descriptors_state,
1781 MESA_SHADER_COMPUTE);
1782 }
1783
1784 descriptors_state->dirty = 0;
1785 descriptors_state->push_dirty = false;
1786
1787 assert(cmd_buffer->cs->cdw <= cdw_max);
1788
1789 if (unlikely(cmd_buffer->device->trace_bo))
1790 radv_save_descriptors(cmd_buffer, bind_point);
1791 }
1792
1793 static void
1794 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1795 VkShaderStageFlags stages)
1796 {
1797 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1798 ? cmd_buffer->state.compute_pipeline
1799 : cmd_buffer->state.pipeline;
1800 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1801 VK_PIPELINE_BIND_POINT_COMPUTE :
1802 VK_PIPELINE_BIND_POINT_GRAPHICS;
1803 struct radv_descriptor_state *descriptors_state =
1804 radv_get_descriptors_state(cmd_buffer, bind_point);
1805 struct radv_pipeline_layout *layout = pipeline->layout;
1806 struct radv_shader_variant *shader, *prev_shader;
1807 unsigned offset;
1808 void *ptr;
1809 uint64_t va;
1810
1811 stages &= cmd_buffer->push_constant_stages;
1812 if (!stages ||
1813 (!layout->push_constant_size && !layout->dynamic_offset_count))
1814 return;
1815
1816 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1817 16 * layout->dynamic_offset_count,
1818 256, &offset, &ptr))
1819 return;
1820
1821 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1822 memcpy((char*)ptr + layout->push_constant_size,
1823 descriptors_state->dynamic_buffers,
1824 16 * layout->dynamic_offset_count);
1825
1826 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1827 va += offset;
1828
1829 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1830 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1831
1832 prev_shader = NULL;
1833 radv_foreach_stage(stage, stages) {
1834 shader = radv_get_shader(pipeline, stage);
1835
1836 /* Avoid redundantly emitting the address for merged stages. */
1837 if (shader && shader != prev_shader) {
1838 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1839 AC_UD_PUSH_CONSTANTS, va);
1840
1841 prev_shader = shader;
1842 }
1843 }
1844
1845 cmd_buffer->push_constant_stages &= ~stages;
1846 assert(cmd_buffer->cs->cdw <= cdw_max);
1847 }
1848
1849 static void
1850 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1851 bool pipeline_is_dirty)
1852 {
1853 if ((pipeline_is_dirty ||
1854 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1855 cmd_buffer->state.pipeline->vertex_elements.count &&
1856 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
1857 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1858 unsigned vb_offset;
1859 void *vb_ptr;
1860 uint32_t i = 0;
1861 uint32_t count = velems->count;
1862 uint64_t va;
1863
1864 /* allocate some descriptor state for vertex buffers */
1865 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1866 &vb_offset, &vb_ptr))
1867 return;
1868
1869 for (i = 0; i < count; i++) {
1870 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1871 uint32_t offset;
1872 int vb = velems->binding[i];
1873 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1874 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1875
1876 va = radv_buffer_get_va(buffer->bo);
1877
1878 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1879 va += offset + buffer->offset;
1880 desc[0] = va;
1881 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1882 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1883 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1884 else
1885 desc[2] = buffer->size - offset;
1886 desc[3] = velems->rsrc_word3[i];
1887 }
1888
1889 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1890 va += vb_offset;
1891
1892 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1893 AC_UD_VS_VERTEX_BUFFERS, va);
1894
1895 cmd_buffer->state.vb_va = va;
1896 cmd_buffer->state.vb_size = count * 16;
1897 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
1898 }
1899 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1900 }
1901
1902 static void
1903 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
1904 {
1905 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1906 struct radv_userdata_info *loc;
1907 uint32_t base_reg;
1908
1909 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
1910 if (!radv_get_shader(pipeline, stage))
1911 continue;
1912
1913 loc = radv_lookup_user_sgpr(pipeline, stage,
1914 AC_UD_STREAMOUT_BUFFERS);
1915 if (loc->sgpr_idx == -1)
1916 continue;
1917
1918 base_reg = pipeline->user_data_0[stage];
1919
1920 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
1921 base_reg + loc->sgpr_idx * 4, va, false);
1922 }
1923
1924 if (pipeline->gs_copy_shader) {
1925 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
1926 if (loc->sgpr_idx != -1) {
1927 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
1928
1929 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
1930 base_reg + loc->sgpr_idx * 4, va, false);
1931 }
1932 }
1933 }
1934
1935 static void
1936 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
1937 {
1938 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
1939 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
1940 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
1941 unsigned so_offset;
1942 void *so_ptr;
1943 uint64_t va;
1944
1945 /* Allocate some descriptor state for streamout buffers. */
1946 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
1947 MAX_SO_BUFFERS * 16, 256,
1948 &so_offset, &so_ptr))
1949 return;
1950
1951 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
1952 struct radv_buffer *buffer = sb[i].buffer;
1953 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
1954
1955 if (!(so->enabled_mask & (1 << i)))
1956 continue;
1957
1958 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
1959
1960 va += sb[i].offset;
1961
1962 /* Set the descriptor.
1963 *
1964 * On VI, the format must be non-INVALID, otherwise
1965 * the buffer will be considered not bound and store
1966 * instructions will be no-ops.
1967 */
1968 desc[0] = va;
1969 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
1970 desc[2] = 0xffffffff;
1971 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1972 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1973 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1974 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1975 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1976 }
1977
1978 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1979 va += so_offset;
1980
1981 radv_emit_streamout_buffers(cmd_buffer, va);
1982 }
1983
1984 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
1985 }
1986
1987 static void
1988 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1989 {
1990 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
1991 radv_flush_streamout_descriptors(cmd_buffer);
1992 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1993 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1994 }
1995
1996 static void
1997 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1998 bool instanced_draw, bool indirect_draw,
1999 uint32_t draw_vertex_count)
2000 {
2001 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2002 struct radv_cmd_state *state = &cmd_buffer->state;
2003 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2004 uint32_t ia_multi_vgt_param;
2005 int32_t primitive_reset_en;
2006
2007 /* Draw state. */
2008 ia_multi_vgt_param =
2009 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2010 indirect_draw, draw_vertex_count);
2011
2012 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2013 if (info->chip_class >= GFX9) {
2014 radeon_set_uconfig_reg_idx(cs,
2015 R_030960_IA_MULTI_VGT_PARAM,
2016 4, ia_multi_vgt_param);
2017 } else if (info->chip_class >= CIK) {
2018 radeon_set_context_reg_idx(cs,
2019 R_028AA8_IA_MULTI_VGT_PARAM,
2020 1, ia_multi_vgt_param);
2021 } else {
2022 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2023 ia_multi_vgt_param);
2024 }
2025 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2026 }
2027
2028 /* Primitive restart. */
2029 primitive_reset_en =
2030 indexed_draw && state->pipeline->graphics.prim_restart_enable;
2031
2032 if (primitive_reset_en != state->last_primitive_reset_en) {
2033 state->last_primitive_reset_en = primitive_reset_en;
2034 if (info->chip_class >= GFX9) {
2035 radeon_set_uconfig_reg(cs,
2036 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2037 primitive_reset_en);
2038 } else {
2039 radeon_set_context_reg(cs,
2040 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2041 primitive_reset_en);
2042 }
2043 }
2044
2045 if (primitive_reset_en) {
2046 uint32_t primitive_reset_index =
2047 state->index_type ? 0xffffffffu : 0xffffu;
2048
2049 if (primitive_reset_index != state->last_primitive_reset_index) {
2050 radeon_set_context_reg(cs,
2051 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2052 primitive_reset_index);
2053 state->last_primitive_reset_index = primitive_reset_index;
2054 }
2055 }
2056 }
2057
2058 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2059 VkPipelineStageFlags src_stage_mask)
2060 {
2061 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2062 VK_PIPELINE_STAGE_TRANSFER_BIT |
2063 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2064 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2065 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2066 }
2067
2068 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2069 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2070 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2071 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2072 VK_PIPELINE_STAGE_TRANSFER_BIT |
2073 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2074 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2075 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2076 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2077 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2078 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2079 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2080 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2081 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2082 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2083 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2084 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2085 }
2086 }
2087
2088 static enum radv_cmd_flush_bits
2089 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2090 VkAccessFlags src_flags,
2091 struct radv_image *image)
2092 {
2093 bool flush_CB_meta = true, flush_DB_meta = true;
2094 enum radv_cmd_flush_bits flush_bits = 0;
2095 uint32_t b;
2096
2097 if (image) {
2098 if (!radv_image_has_CB_metadata(image))
2099 flush_CB_meta = false;
2100 if (!radv_image_has_htile(image))
2101 flush_DB_meta = false;
2102 }
2103
2104 for_each_bit(b, src_flags) {
2105 switch ((VkAccessFlagBits)(1 << b)) {
2106 case VK_ACCESS_SHADER_WRITE_BIT:
2107 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2108 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2109 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2110 break;
2111 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2112 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2113 if (flush_CB_meta)
2114 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2115 break;
2116 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2117 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2118 if (flush_DB_meta)
2119 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2120 break;
2121 case VK_ACCESS_TRANSFER_WRITE_BIT:
2122 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2123 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2124 RADV_CMD_FLAG_INV_GLOBAL_L2;
2125
2126 if (flush_CB_meta)
2127 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2128 if (flush_DB_meta)
2129 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2130 break;
2131 default:
2132 break;
2133 }
2134 }
2135 return flush_bits;
2136 }
2137
2138 static enum radv_cmd_flush_bits
2139 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2140 VkAccessFlags dst_flags,
2141 struct radv_image *image)
2142 {
2143 bool flush_CB_meta = true, flush_DB_meta = true;
2144 enum radv_cmd_flush_bits flush_bits = 0;
2145 bool flush_CB = true, flush_DB = true;
2146 bool image_is_coherent = false;
2147 uint32_t b;
2148
2149 if (image) {
2150 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2151 flush_CB = false;
2152 flush_DB = false;
2153 }
2154
2155 if (!radv_image_has_CB_metadata(image))
2156 flush_CB_meta = false;
2157 if (!radv_image_has_htile(image))
2158 flush_DB_meta = false;
2159
2160 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2161 if (image->info.samples == 1 &&
2162 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2163 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2164 !vk_format_is_stencil(image->vk_format)) {
2165 /* Single-sample color and single-sample depth
2166 * (not stencil) are coherent with shaders on
2167 * GFX9.
2168 */
2169 image_is_coherent = true;
2170 }
2171 }
2172 }
2173
2174 for_each_bit(b, dst_flags) {
2175 switch ((VkAccessFlagBits)(1 << b)) {
2176 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2177 case VK_ACCESS_INDEX_READ_BIT:
2178 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2179 break;
2180 case VK_ACCESS_UNIFORM_READ_BIT:
2181 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2182 break;
2183 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2184 case VK_ACCESS_TRANSFER_READ_BIT:
2185 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2186 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2187 RADV_CMD_FLAG_INV_GLOBAL_L2;
2188 break;
2189 case VK_ACCESS_SHADER_READ_BIT:
2190 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2191
2192 if (!image_is_coherent)
2193 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2194 break;
2195 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2196 if (flush_CB)
2197 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2198 if (flush_CB_meta)
2199 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2200 break;
2201 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2202 if (flush_DB)
2203 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2204 if (flush_DB_meta)
2205 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2206 break;
2207 default:
2208 break;
2209 }
2210 }
2211 return flush_bits;
2212 }
2213
2214 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2215 const struct radv_subpass_barrier *barrier)
2216 {
2217 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2218 NULL);
2219 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2220 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2221 NULL);
2222 }
2223
2224 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2225 struct radv_subpass_attachment att)
2226 {
2227 unsigned idx = att.attachment;
2228 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2229 VkImageSubresourceRange range;
2230 range.aspectMask = 0;
2231 range.baseMipLevel = view->base_mip;
2232 range.levelCount = 1;
2233 range.baseArrayLayer = view->base_layer;
2234 range.layerCount = cmd_buffer->state.framebuffer->layers;
2235
2236 radv_handle_image_transition(cmd_buffer,
2237 view->image,
2238 cmd_buffer->state.attachments[idx].current_layout,
2239 att.layout, 0, 0, &range,
2240 cmd_buffer->state.attachments[idx].pending_clear_aspects);
2241
2242 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2243
2244
2245 }
2246
2247 void
2248 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2249 const struct radv_subpass *subpass, bool transitions)
2250 {
2251 if (transitions) {
2252 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2253
2254 for (unsigned i = 0; i < subpass->color_count; ++i) {
2255 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2256 radv_handle_subpass_image_transition(cmd_buffer,
2257 subpass->color_attachments[i]);
2258 }
2259
2260 for (unsigned i = 0; i < subpass->input_count; ++i) {
2261 radv_handle_subpass_image_transition(cmd_buffer,
2262 subpass->input_attachments[i]);
2263 }
2264
2265 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2266 radv_handle_subpass_image_transition(cmd_buffer,
2267 subpass->depth_stencil_attachment);
2268 }
2269 }
2270
2271 cmd_buffer->state.subpass = subpass;
2272
2273 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2274 }
2275
2276 static VkResult
2277 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2278 struct radv_render_pass *pass,
2279 const VkRenderPassBeginInfo *info)
2280 {
2281 struct radv_cmd_state *state = &cmd_buffer->state;
2282
2283 if (pass->attachment_count == 0) {
2284 state->attachments = NULL;
2285 return VK_SUCCESS;
2286 }
2287
2288 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2289 pass->attachment_count *
2290 sizeof(state->attachments[0]),
2291 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2292 if (state->attachments == NULL) {
2293 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2294 return cmd_buffer->record_result;
2295 }
2296
2297 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2298 struct radv_render_pass_attachment *att = &pass->attachments[i];
2299 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2300 VkImageAspectFlags clear_aspects = 0;
2301
2302 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2303 /* color attachment */
2304 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2305 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2306 }
2307 } else {
2308 /* depthstencil attachment */
2309 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2310 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2311 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2312 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2313 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2314 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2315 }
2316 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2317 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2318 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2319 }
2320 }
2321
2322 state->attachments[i].pending_clear_aspects = clear_aspects;
2323 state->attachments[i].cleared_views = 0;
2324 if (clear_aspects && info) {
2325 assert(info->clearValueCount > i);
2326 state->attachments[i].clear_value = info->pClearValues[i];
2327 }
2328
2329 state->attachments[i].current_layout = att->initial_layout;
2330 }
2331
2332 return VK_SUCCESS;
2333 }
2334
2335 VkResult radv_AllocateCommandBuffers(
2336 VkDevice _device,
2337 const VkCommandBufferAllocateInfo *pAllocateInfo,
2338 VkCommandBuffer *pCommandBuffers)
2339 {
2340 RADV_FROM_HANDLE(radv_device, device, _device);
2341 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2342
2343 VkResult result = VK_SUCCESS;
2344 uint32_t i;
2345
2346 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2347
2348 if (!list_empty(&pool->free_cmd_buffers)) {
2349 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2350
2351 list_del(&cmd_buffer->pool_link);
2352 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2353
2354 result = radv_reset_cmd_buffer(cmd_buffer);
2355 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2356 cmd_buffer->level = pAllocateInfo->level;
2357
2358 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2359 } else {
2360 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2361 &pCommandBuffers[i]);
2362 }
2363 if (result != VK_SUCCESS)
2364 break;
2365 }
2366
2367 if (result != VK_SUCCESS) {
2368 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2369 i, pCommandBuffers);
2370
2371 /* From the Vulkan 1.0.66 spec:
2372 *
2373 * "vkAllocateCommandBuffers can be used to create multiple
2374 * command buffers. If the creation of any of those command
2375 * buffers fails, the implementation must destroy all
2376 * successfully created command buffer objects from this
2377 * command, set all entries of the pCommandBuffers array to
2378 * NULL and return the error."
2379 */
2380 memset(pCommandBuffers, 0,
2381 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2382 }
2383
2384 return result;
2385 }
2386
2387 void radv_FreeCommandBuffers(
2388 VkDevice device,
2389 VkCommandPool commandPool,
2390 uint32_t commandBufferCount,
2391 const VkCommandBuffer *pCommandBuffers)
2392 {
2393 for (uint32_t i = 0; i < commandBufferCount; i++) {
2394 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2395
2396 if (cmd_buffer) {
2397 if (cmd_buffer->pool) {
2398 list_del(&cmd_buffer->pool_link);
2399 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2400 } else
2401 radv_cmd_buffer_destroy(cmd_buffer);
2402
2403 }
2404 }
2405 }
2406
2407 VkResult radv_ResetCommandBuffer(
2408 VkCommandBuffer commandBuffer,
2409 VkCommandBufferResetFlags flags)
2410 {
2411 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2412 return radv_reset_cmd_buffer(cmd_buffer);
2413 }
2414
2415 VkResult radv_BeginCommandBuffer(
2416 VkCommandBuffer commandBuffer,
2417 const VkCommandBufferBeginInfo *pBeginInfo)
2418 {
2419 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2420 VkResult result = VK_SUCCESS;
2421
2422 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2423 /* If the command buffer has already been resetted with
2424 * vkResetCommandBuffer, no need to do it again.
2425 */
2426 result = radv_reset_cmd_buffer(cmd_buffer);
2427 if (result != VK_SUCCESS)
2428 return result;
2429 }
2430
2431 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2432 cmd_buffer->state.last_primitive_reset_en = -1;
2433 cmd_buffer->state.last_index_type = -1;
2434 cmd_buffer->state.last_num_instances = -1;
2435 cmd_buffer->state.last_vertex_offset = -1;
2436 cmd_buffer->state.last_first_instance = -1;
2437 cmd_buffer->state.predication_type = -1;
2438 cmd_buffer->usage_flags = pBeginInfo->flags;
2439
2440 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
2441 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
2442 assert(pBeginInfo->pInheritanceInfo);
2443 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2444 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2445
2446 struct radv_subpass *subpass =
2447 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2448
2449 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2450 if (result != VK_SUCCESS)
2451 return result;
2452
2453 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2454 }
2455
2456 if (unlikely(cmd_buffer->device->trace_bo)) {
2457 struct radv_device *device = cmd_buffer->device;
2458
2459 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
2460 device->trace_bo);
2461
2462 radv_cmd_buffer_trace_emit(cmd_buffer);
2463 }
2464
2465 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2466
2467 return result;
2468 }
2469
2470 void radv_CmdBindVertexBuffers(
2471 VkCommandBuffer commandBuffer,
2472 uint32_t firstBinding,
2473 uint32_t bindingCount,
2474 const VkBuffer* pBuffers,
2475 const VkDeviceSize* pOffsets)
2476 {
2477 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2478 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2479 bool changed = false;
2480
2481 /* We have to defer setting up vertex buffer since we need the buffer
2482 * stride from the pipeline. */
2483
2484 assert(firstBinding + bindingCount <= MAX_VBS);
2485 for (uint32_t i = 0; i < bindingCount; i++) {
2486 uint32_t idx = firstBinding + i;
2487
2488 if (!changed &&
2489 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2490 vb[idx].offset != pOffsets[i])) {
2491 changed = true;
2492 }
2493
2494 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2495 vb[idx].offset = pOffsets[i];
2496
2497 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2498 vb[idx].buffer->bo);
2499 }
2500
2501 if (!changed) {
2502 /* No state changes. */
2503 return;
2504 }
2505
2506 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2507 }
2508
2509 void radv_CmdBindIndexBuffer(
2510 VkCommandBuffer commandBuffer,
2511 VkBuffer buffer,
2512 VkDeviceSize offset,
2513 VkIndexType indexType)
2514 {
2515 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2516 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2517
2518 if (cmd_buffer->state.index_buffer == index_buffer &&
2519 cmd_buffer->state.index_offset == offset &&
2520 cmd_buffer->state.index_type == indexType) {
2521 /* No state changes. */
2522 return;
2523 }
2524
2525 cmd_buffer->state.index_buffer = index_buffer;
2526 cmd_buffer->state.index_offset = offset;
2527 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2528 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2529 cmd_buffer->state.index_va += index_buffer->offset + offset;
2530
2531 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2532 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2533 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2534 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
2535 }
2536
2537
2538 static void
2539 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2540 VkPipelineBindPoint bind_point,
2541 struct radv_descriptor_set *set, unsigned idx)
2542 {
2543 struct radeon_winsys *ws = cmd_buffer->device->ws;
2544
2545 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2546
2547 assert(set);
2548 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2549
2550 if (!cmd_buffer->device->use_global_bo_list) {
2551 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2552 if (set->descriptors[j])
2553 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
2554 }
2555
2556 if(set->bo)
2557 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
2558 }
2559
2560 void radv_CmdBindDescriptorSets(
2561 VkCommandBuffer commandBuffer,
2562 VkPipelineBindPoint pipelineBindPoint,
2563 VkPipelineLayout _layout,
2564 uint32_t firstSet,
2565 uint32_t descriptorSetCount,
2566 const VkDescriptorSet* pDescriptorSets,
2567 uint32_t dynamicOffsetCount,
2568 const uint32_t* pDynamicOffsets)
2569 {
2570 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2571 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2572 unsigned dyn_idx = 0;
2573
2574 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2575 struct radv_descriptor_state *descriptors_state =
2576 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2577
2578 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2579 unsigned idx = i + firstSet;
2580 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2581 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2582
2583 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2584 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2585 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
2586 assert(dyn_idx < dynamicOffsetCount);
2587
2588 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2589 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2590 dst[0] = va;
2591 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2592 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2593 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2594 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2595 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2596 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2597 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2598 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2599 cmd_buffer->push_constant_stages |=
2600 set->layout->dynamic_shader_stages;
2601 }
2602 }
2603 }
2604
2605 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2606 struct radv_descriptor_set *set,
2607 struct radv_descriptor_set_layout *layout,
2608 VkPipelineBindPoint bind_point)
2609 {
2610 struct radv_descriptor_state *descriptors_state =
2611 radv_get_descriptors_state(cmd_buffer, bind_point);
2612 set->size = layout->size;
2613 set->layout = layout;
2614
2615 if (descriptors_state->push_set.capacity < set->size) {
2616 size_t new_size = MAX2(set->size, 1024);
2617 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2618 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2619
2620 free(set->mapped_ptr);
2621 set->mapped_ptr = malloc(new_size);
2622
2623 if (!set->mapped_ptr) {
2624 descriptors_state->push_set.capacity = 0;
2625 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2626 return false;
2627 }
2628
2629 descriptors_state->push_set.capacity = new_size;
2630 }
2631
2632 return true;
2633 }
2634
2635 void radv_meta_push_descriptor_set(
2636 struct radv_cmd_buffer* cmd_buffer,
2637 VkPipelineBindPoint pipelineBindPoint,
2638 VkPipelineLayout _layout,
2639 uint32_t set,
2640 uint32_t descriptorWriteCount,
2641 const VkWriteDescriptorSet* pDescriptorWrites)
2642 {
2643 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2644 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2645 unsigned bo_offset;
2646
2647 assert(set == 0);
2648 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2649
2650 push_set->size = layout->set[set].layout->size;
2651 push_set->layout = layout->set[set].layout;
2652
2653 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2654 &bo_offset,
2655 (void**) &push_set->mapped_ptr))
2656 return;
2657
2658 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2659 push_set->va += bo_offset;
2660
2661 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2662 radv_descriptor_set_to_handle(push_set),
2663 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2664
2665 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2666 }
2667
2668 void radv_CmdPushDescriptorSetKHR(
2669 VkCommandBuffer commandBuffer,
2670 VkPipelineBindPoint pipelineBindPoint,
2671 VkPipelineLayout _layout,
2672 uint32_t set,
2673 uint32_t descriptorWriteCount,
2674 const VkWriteDescriptorSet* pDescriptorWrites)
2675 {
2676 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2677 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2678 struct radv_descriptor_state *descriptors_state =
2679 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2680 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2681
2682 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2683
2684 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2685 layout->set[set].layout,
2686 pipelineBindPoint))
2687 return;
2688
2689 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2690 radv_descriptor_set_to_handle(push_set),
2691 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2692
2693 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2694 descriptors_state->push_dirty = true;
2695 }
2696
2697 void radv_CmdPushDescriptorSetWithTemplateKHR(
2698 VkCommandBuffer commandBuffer,
2699 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2700 VkPipelineLayout _layout,
2701 uint32_t set,
2702 const void* pData)
2703 {
2704 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2705 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2706 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2707 struct radv_descriptor_state *descriptors_state =
2708 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2709 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2710
2711 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2712
2713 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2714 layout->set[set].layout,
2715 templ->bind_point))
2716 return;
2717
2718 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2719 descriptorUpdateTemplate, pData);
2720
2721 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2722 descriptors_state->push_dirty = true;
2723 }
2724
2725 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2726 VkPipelineLayout layout,
2727 VkShaderStageFlags stageFlags,
2728 uint32_t offset,
2729 uint32_t size,
2730 const void* pValues)
2731 {
2732 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2733 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2734 cmd_buffer->push_constant_stages |= stageFlags;
2735 }
2736
2737 VkResult radv_EndCommandBuffer(
2738 VkCommandBuffer commandBuffer)
2739 {
2740 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2741
2742 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2743 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2744 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2745 si_emit_cache_flush(cmd_buffer);
2746 }
2747
2748 /* Make sure CP DMA is idle at the end of IBs because the kernel
2749 * doesn't wait for it.
2750 */
2751 si_cp_dma_wait_for_idle(cmd_buffer);
2752
2753 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2754
2755 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2756 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2757
2758 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2759
2760 return cmd_buffer->record_result;
2761 }
2762
2763 static void
2764 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2765 {
2766 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2767
2768 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2769 return;
2770
2771 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2772
2773 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2774 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2775
2776 cmd_buffer->compute_scratch_size_needed =
2777 MAX2(cmd_buffer->compute_scratch_size_needed,
2778 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2779
2780 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2781 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
2782
2783 if (unlikely(cmd_buffer->device->trace_bo))
2784 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2785 }
2786
2787 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2788 VkPipelineBindPoint bind_point)
2789 {
2790 struct radv_descriptor_state *descriptors_state =
2791 radv_get_descriptors_state(cmd_buffer, bind_point);
2792
2793 descriptors_state->dirty |= descriptors_state->valid;
2794 }
2795
2796 void radv_CmdBindPipeline(
2797 VkCommandBuffer commandBuffer,
2798 VkPipelineBindPoint pipelineBindPoint,
2799 VkPipeline _pipeline)
2800 {
2801 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2802 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2803
2804 switch (pipelineBindPoint) {
2805 case VK_PIPELINE_BIND_POINT_COMPUTE:
2806 if (cmd_buffer->state.compute_pipeline == pipeline)
2807 return;
2808 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2809
2810 cmd_buffer->state.compute_pipeline = pipeline;
2811 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2812 break;
2813 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2814 if (cmd_buffer->state.pipeline == pipeline)
2815 return;
2816 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2817
2818 cmd_buffer->state.pipeline = pipeline;
2819 if (!pipeline)
2820 break;
2821
2822 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2823 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2824
2825 /* the new vertex shader might not have the same user regs */
2826 cmd_buffer->state.last_first_instance = -1;
2827 cmd_buffer->state.last_vertex_offset = -1;
2828
2829 /* Prefetch all pipeline shaders at first draw time. */
2830 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
2831
2832 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2833 radv_bind_streamout_state(cmd_buffer, pipeline);
2834
2835 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2836 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2837 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2838 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2839
2840 if (radv_pipeline_has_tess(pipeline))
2841 cmd_buffer->tess_rings_needed = true;
2842 break;
2843 default:
2844 assert(!"invalid bind point");
2845 break;
2846 }
2847 }
2848
2849 void radv_CmdSetViewport(
2850 VkCommandBuffer commandBuffer,
2851 uint32_t firstViewport,
2852 uint32_t viewportCount,
2853 const VkViewport* pViewports)
2854 {
2855 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2856 struct radv_cmd_state *state = &cmd_buffer->state;
2857 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2858
2859 assert(firstViewport < MAX_VIEWPORTS);
2860 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2861
2862 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2863 viewportCount * sizeof(*pViewports));
2864
2865 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2866 }
2867
2868 void radv_CmdSetScissor(
2869 VkCommandBuffer commandBuffer,
2870 uint32_t firstScissor,
2871 uint32_t scissorCount,
2872 const VkRect2D* pScissors)
2873 {
2874 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2875 struct radv_cmd_state *state = &cmd_buffer->state;
2876 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2877
2878 assert(firstScissor < MAX_SCISSORS);
2879 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2880
2881 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2882 scissorCount * sizeof(*pScissors));
2883
2884 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2885 }
2886
2887 void radv_CmdSetLineWidth(
2888 VkCommandBuffer commandBuffer,
2889 float lineWidth)
2890 {
2891 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2892 cmd_buffer->state.dynamic.line_width = lineWidth;
2893 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2894 }
2895
2896 void radv_CmdSetDepthBias(
2897 VkCommandBuffer commandBuffer,
2898 float depthBiasConstantFactor,
2899 float depthBiasClamp,
2900 float depthBiasSlopeFactor)
2901 {
2902 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2903
2904 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2905 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2906 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2907
2908 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2909 }
2910
2911 void radv_CmdSetBlendConstants(
2912 VkCommandBuffer commandBuffer,
2913 const float blendConstants[4])
2914 {
2915 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2916
2917 memcpy(cmd_buffer->state.dynamic.blend_constants,
2918 blendConstants, sizeof(float) * 4);
2919
2920 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2921 }
2922
2923 void radv_CmdSetDepthBounds(
2924 VkCommandBuffer commandBuffer,
2925 float minDepthBounds,
2926 float maxDepthBounds)
2927 {
2928 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2929
2930 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2931 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2932
2933 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2934 }
2935
2936 void radv_CmdSetStencilCompareMask(
2937 VkCommandBuffer commandBuffer,
2938 VkStencilFaceFlags faceMask,
2939 uint32_t compareMask)
2940 {
2941 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2942
2943 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2944 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2945 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2946 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2947
2948 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2949 }
2950
2951 void radv_CmdSetStencilWriteMask(
2952 VkCommandBuffer commandBuffer,
2953 VkStencilFaceFlags faceMask,
2954 uint32_t writeMask)
2955 {
2956 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2957
2958 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2959 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2960 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2961 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2962
2963 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2964 }
2965
2966 void radv_CmdSetStencilReference(
2967 VkCommandBuffer commandBuffer,
2968 VkStencilFaceFlags faceMask,
2969 uint32_t reference)
2970 {
2971 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2972
2973 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2974 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2975 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2976 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2977
2978 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2979 }
2980
2981 void radv_CmdSetDiscardRectangleEXT(
2982 VkCommandBuffer commandBuffer,
2983 uint32_t firstDiscardRectangle,
2984 uint32_t discardRectangleCount,
2985 const VkRect2D* pDiscardRectangles)
2986 {
2987 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2988 struct radv_cmd_state *state = &cmd_buffer->state;
2989 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
2990
2991 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
2992 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
2993
2994 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
2995 pDiscardRectangles, discardRectangleCount);
2996
2997 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
2998 }
2999
3000 void radv_CmdExecuteCommands(
3001 VkCommandBuffer commandBuffer,
3002 uint32_t commandBufferCount,
3003 const VkCommandBuffer* pCmdBuffers)
3004 {
3005 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3006
3007 assert(commandBufferCount > 0);
3008
3009 /* Emit pending flushes on primary prior to executing secondary */
3010 si_emit_cache_flush(primary);
3011
3012 for (uint32_t i = 0; i < commandBufferCount; i++) {
3013 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3014
3015 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3016 secondary->scratch_size_needed);
3017 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3018 secondary->compute_scratch_size_needed);
3019
3020 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
3021 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
3022 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
3023 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
3024 if (secondary->tess_rings_needed)
3025 primary->tess_rings_needed = true;
3026 if (secondary->sample_positions_needed)
3027 primary->sample_positions_needed = true;
3028
3029 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
3030
3031
3032 /* When the secondary command buffer is compute only we don't
3033 * need to re-emit the current graphics pipeline.
3034 */
3035 if (secondary->state.emitted_pipeline) {
3036 primary->state.emitted_pipeline =
3037 secondary->state.emitted_pipeline;
3038 }
3039
3040 /* When the secondary command buffer is graphics only we don't
3041 * need to re-emit the current compute pipeline.
3042 */
3043 if (secondary->state.emitted_compute_pipeline) {
3044 primary->state.emitted_compute_pipeline =
3045 secondary->state.emitted_compute_pipeline;
3046 }
3047
3048 /* Only re-emit the draw packets when needed. */
3049 if (secondary->state.last_primitive_reset_en != -1) {
3050 primary->state.last_primitive_reset_en =
3051 secondary->state.last_primitive_reset_en;
3052 }
3053
3054 if (secondary->state.last_primitive_reset_index) {
3055 primary->state.last_primitive_reset_index =
3056 secondary->state.last_primitive_reset_index;
3057 }
3058
3059 if (secondary->state.last_ia_multi_vgt_param) {
3060 primary->state.last_ia_multi_vgt_param =
3061 secondary->state.last_ia_multi_vgt_param;
3062 }
3063
3064 primary->state.last_first_instance = secondary->state.last_first_instance;
3065 primary->state.last_num_instances = secondary->state.last_num_instances;
3066 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
3067
3068 if (secondary->state.last_index_type != -1) {
3069 primary->state.last_index_type =
3070 secondary->state.last_index_type;
3071 }
3072 }
3073
3074 /* After executing commands from secondary buffers we have to dirty
3075 * some states.
3076 */
3077 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
3078 RADV_CMD_DIRTY_INDEX_BUFFER |
3079 RADV_CMD_DIRTY_DYNAMIC_ALL;
3080 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
3081 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
3082 }
3083
3084 VkResult radv_CreateCommandPool(
3085 VkDevice _device,
3086 const VkCommandPoolCreateInfo* pCreateInfo,
3087 const VkAllocationCallbacks* pAllocator,
3088 VkCommandPool* pCmdPool)
3089 {
3090 RADV_FROM_HANDLE(radv_device, device, _device);
3091 struct radv_cmd_pool *pool;
3092
3093 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3094 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3095 if (pool == NULL)
3096 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3097
3098 if (pAllocator)
3099 pool->alloc = *pAllocator;
3100 else
3101 pool->alloc = device->alloc;
3102
3103 list_inithead(&pool->cmd_buffers);
3104 list_inithead(&pool->free_cmd_buffers);
3105
3106 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3107
3108 *pCmdPool = radv_cmd_pool_to_handle(pool);
3109
3110 return VK_SUCCESS;
3111
3112 }
3113
3114 void radv_DestroyCommandPool(
3115 VkDevice _device,
3116 VkCommandPool commandPool,
3117 const VkAllocationCallbacks* pAllocator)
3118 {
3119 RADV_FROM_HANDLE(radv_device, device, _device);
3120 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3121
3122 if (!pool)
3123 return;
3124
3125 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3126 &pool->cmd_buffers, pool_link) {
3127 radv_cmd_buffer_destroy(cmd_buffer);
3128 }
3129
3130 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3131 &pool->free_cmd_buffers, pool_link) {
3132 radv_cmd_buffer_destroy(cmd_buffer);
3133 }
3134
3135 vk_free2(&device->alloc, pAllocator, pool);
3136 }
3137
3138 VkResult radv_ResetCommandPool(
3139 VkDevice device,
3140 VkCommandPool commandPool,
3141 VkCommandPoolResetFlags flags)
3142 {
3143 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3144 VkResult result;
3145
3146 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3147 &pool->cmd_buffers, pool_link) {
3148 result = radv_reset_cmd_buffer(cmd_buffer);
3149 if (result != VK_SUCCESS)
3150 return result;
3151 }
3152
3153 return VK_SUCCESS;
3154 }
3155
3156 void radv_TrimCommandPool(
3157 VkDevice device,
3158 VkCommandPool commandPool,
3159 VkCommandPoolTrimFlagsKHR flags)
3160 {
3161 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3162
3163 if (!pool)
3164 return;
3165
3166 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3167 &pool->free_cmd_buffers, pool_link) {
3168 radv_cmd_buffer_destroy(cmd_buffer);
3169 }
3170 }
3171
3172 void radv_CmdBeginRenderPass(
3173 VkCommandBuffer commandBuffer,
3174 const VkRenderPassBeginInfo* pRenderPassBegin,
3175 VkSubpassContents contents)
3176 {
3177 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3178 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3179 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3180
3181 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3182 cmd_buffer->cs, 2048);
3183 MAYBE_UNUSED VkResult result;
3184
3185 cmd_buffer->state.framebuffer = framebuffer;
3186 cmd_buffer->state.pass = pass;
3187 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3188
3189 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3190 if (result != VK_SUCCESS)
3191 return;
3192
3193 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
3194 assert(cmd_buffer->cs->cdw <= cdw_max);
3195
3196 radv_cmd_buffer_clear_subpass(cmd_buffer);
3197 }
3198
3199 void radv_CmdBeginRenderPass2KHR(
3200 VkCommandBuffer commandBuffer,
3201 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
3202 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
3203 {
3204 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
3205 pSubpassBeginInfo->contents);
3206 }
3207
3208 void radv_CmdNextSubpass(
3209 VkCommandBuffer commandBuffer,
3210 VkSubpassContents contents)
3211 {
3212 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3213
3214 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3215
3216 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
3217 2048);
3218
3219 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
3220 radv_cmd_buffer_clear_subpass(cmd_buffer);
3221 }
3222
3223 void radv_CmdNextSubpass2KHR(
3224 VkCommandBuffer commandBuffer,
3225 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
3226 const VkSubpassEndInfoKHR* pSubpassEndInfo)
3227 {
3228 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
3229 }
3230
3231 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3232 {
3233 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3234 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3235 if (!radv_get_shader(pipeline, stage))
3236 continue;
3237
3238 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3239 if (loc->sgpr_idx == -1)
3240 continue;
3241 uint32_t base_reg = pipeline->user_data_0[stage];
3242 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3243
3244 }
3245 if (pipeline->gs_copy_shader) {
3246 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3247 if (loc->sgpr_idx != -1) {
3248 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3249 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3250 }
3251 }
3252 }
3253
3254 static void
3255 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3256 uint32_t vertex_count,
3257 bool use_opaque)
3258 {
3259 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3260 radeon_emit(cmd_buffer->cs, vertex_count);
3261 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3262 S_0287F0_USE_OPAQUE(use_opaque));
3263 }
3264
3265 static void
3266 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3267 uint64_t index_va,
3268 uint32_t index_count)
3269 {
3270 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
3271 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3272 radeon_emit(cmd_buffer->cs, index_va);
3273 radeon_emit(cmd_buffer->cs, index_va >> 32);
3274 radeon_emit(cmd_buffer->cs, index_count);
3275 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3276 }
3277
3278 static void
3279 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3280 bool indexed,
3281 uint32_t draw_count,
3282 uint64_t count_va,
3283 uint32_t stride)
3284 {
3285 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3286 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3287 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3288 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
3289 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3290 bool predicating = cmd_buffer->state.predicating;
3291 assert(base_reg);
3292
3293 /* just reset draw state for vertex data */
3294 cmd_buffer->state.last_first_instance = -1;
3295 cmd_buffer->state.last_num_instances = -1;
3296 cmd_buffer->state.last_vertex_offset = -1;
3297
3298 if (draw_count == 1 && !count_va && !draw_id_enable) {
3299 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3300 PKT3_DRAW_INDIRECT, 3, predicating));
3301 radeon_emit(cs, 0);
3302 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3303 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3304 radeon_emit(cs, di_src_sel);
3305 } else {
3306 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3307 PKT3_DRAW_INDIRECT_MULTI,
3308 8, predicating));
3309 radeon_emit(cs, 0);
3310 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3311 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3312 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3313 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3314 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3315 radeon_emit(cs, draw_count); /* count */
3316 radeon_emit(cs, count_va); /* count_addr */
3317 radeon_emit(cs, count_va >> 32);
3318 radeon_emit(cs, stride); /* stride */
3319 radeon_emit(cs, di_src_sel);
3320 }
3321 }
3322
3323 struct radv_draw_info {
3324 /**
3325 * Number of vertices.
3326 */
3327 uint32_t count;
3328
3329 /**
3330 * Index of the first vertex.
3331 */
3332 int32_t vertex_offset;
3333
3334 /**
3335 * First instance id.
3336 */
3337 uint32_t first_instance;
3338
3339 /**
3340 * Number of instances.
3341 */
3342 uint32_t instance_count;
3343
3344 /**
3345 * First index (indexed draws only).
3346 */
3347 uint32_t first_index;
3348
3349 /**
3350 * Whether it's an indexed draw.
3351 */
3352 bool indexed;
3353
3354 /**
3355 * Indirect draw parameters resource.
3356 */
3357 struct radv_buffer *indirect;
3358 uint64_t indirect_offset;
3359 uint32_t stride;
3360
3361 /**
3362 * Draw count parameters resource.
3363 */
3364 struct radv_buffer *count_buffer;
3365 uint64_t count_buffer_offset;
3366
3367 /**
3368 * Stream output parameters resource.
3369 */
3370 struct radv_buffer *strmout_buffer;
3371 uint64_t strmout_buffer_offset;
3372 };
3373
3374 static void
3375 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3376 const struct radv_draw_info *info)
3377 {
3378 struct radv_cmd_state *state = &cmd_buffer->state;
3379 struct radeon_winsys *ws = cmd_buffer->device->ws;
3380 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3381
3382 if (info->strmout_buffer) {
3383 uint64_t va = radv_buffer_get_va(info->strmout_buffer->bo);
3384
3385 va += info->strmout_buffer->offset +
3386 info->strmout_buffer_offset;
3387
3388 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
3389 info->stride);
3390
3391 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3392 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
3393 COPY_DATA_DST_SEL(COPY_DATA_REG) |
3394 COPY_DATA_WR_CONFIRM);
3395 radeon_emit(cs, va);
3396 radeon_emit(cs, va >> 32);
3397 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
3398 radeon_emit(cs, 0); /* unused */
3399
3400 radv_cs_add_buffer(ws, cs, info->strmout_buffer->bo);
3401 }
3402
3403 if (info->indirect) {
3404 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3405 uint64_t count_va = 0;
3406
3407 va += info->indirect->offset + info->indirect_offset;
3408
3409 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3410
3411 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3412 radeon_emit(cs, 1);
3413 radeon_emit(cs, va);
3414 radeon_emit(cs, va >> 32);
3415
3416 if (info->count_buffer) {
3417 count_va = radv_buffer_get_va(info->count_buffer->bo);
3418 count_va += info->count_buffer->offset +
3419 info->count_buffer_offset;
3420
3421 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
3422 }
3423
3424 if (!state->subpass->view_mask) {
3425 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3426 info->indexed,
3427 info->count,
3428 count_va,
3429 info->stride);
3430 } else {
3431 unsigned i;
3432 for_each_bit(i, state->subpass->view_mask) {
3433 radv_emit_view_index(cmd_buffer, i);
3434
3435 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3436 info->indexed,
3437 info->count,
3438 count_va,
3439 info->stride);
3440 }
3441 }
3442 } else {
3443 assert(state->pipeline->graphics.vtx_base_sgpr);
3444
3445 if (info->vertex_offset != state->last_vertex_offset ||
3446 info->first_instance != state->last_first_instance) {
3447 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3448 state->pipeline->graphics.vtx_emit_num);
3449
3450 radeon_emit(cs, info->vertex_offset);
3451 radeon_emit(cs, info->first_instance);
3452 if (state->pipeline->graphics.vtx_emit_num == 3)
3453 radeon_emit(cs, 0);
3454 state->last_first_instance = info->first_instance;
3455 state->last_vertex_offset = info->vertex_offset;
3456 }
3457
3458 if (state->last_num_instances != info->instance_count) {
3459 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3460 radeon_emit(cs, info->instance_count);
3461 state->last_num_instances = info->instance_count;
3462 }
3463
3464 if (info->indexed) {
3465 int index_size = state->index_type ? 4 : 2;
3466 uint64_t index_va;
3467
3468 index_va = state->index_va;
3469 index_va += info->first_index * index_size;
3470
3471 if (!state->subpass->view_mask) {
3472 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3473 index_va,
3474 info->count);
3475 } else {
3476 unsigned i;
3477 for_each_bit(i, state->subpass->view_mask) {
3478 radv_emit_view_index(cmd_buffer, i);
3479
3480 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3481 index_va,
3482 info->count);
3483 }
3484 }
3485 } else {
3486 if (!state->subpass->view_mask) {
3487 radv_cs_emit_draw_packet(cmd_buffer,
3488 info->count,
3489 !!info->strmout_buffer);
3490 } else {
3491 unsigned i;
3492 for_each_bit(i, state->subpass->view_mask) {
3493 radv_emit_view_index(cmd_buffer, i);
3494
3495 radv_cs_emit_draw_packet(cmd_buffer,
3496 info->count,
3497 !!info->strmout_buffer);
3498 }
3499 }
3500 }
3501 }
3502 }
3503
3504 /*
3505 * Vega and raven have a bug which triggers if there are multiple context
3506 * register contexts active at the same time with different scissor values.
3507 *
3508 * There are two possible workarounds:
3509 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3510 * there is only ever 1 active set of scissor values at the same time.
3511 *
3512 * 2) Whenever the hardware switches contexts we have to set the scissor
3513 * registers again even if it is a noop. That way the new context gets
3514 * the correct scissor values.
3515 *
3516 * This implements option 2. radv_need_late_scissor_emission needs to
3517 * return true on affected HW if radv_emit_all_graphics_states sets
3518 * any context registers.
3519 */
3520 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
3521 bool indexed_draw)
3522 {
3523 struct radv_cmd_state *state = &cmd_buffer->state;
3524
3525 if (!cmd_buffer->device->physical_device->has_scissor_bug)
3526 return false;
3527
3528 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
3529
3530 /* Index & Vertex buffer don't change context regs, and pipeline is handled later. */
3531 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER | RADV_CMD_DIRTY_VERTEX_BUFFER | RADV_CMD_DIRTY_PIPELINE);
3532
3533 /* Assume all state changes except these two can imply context rolls. */
3534 if (cmd_buffer->state.dirty & used_states)
3535 return true;
3536
3537 if (cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3538 return true;
3539
3540 if (indexed_draw && state->pipeline->graphics.prim_restart_enable &&
3541 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
3542 return true;
3543
3544 return false;
3545 }
3546
3547 static void
3548 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3549 const struct radv_draw_info *info)
3550 {
3551 bool late_scissor_emission = radv_need_late_scissor_emission(cmd_buffer, info->indexed);
3552
3553 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3554 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3555 radv_emit_rbplus_state(cmd_buffer);
3556
3557 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3558 radv_emit_graphics_pipeline(cmd_buffer);
3559
3560 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3561 radv_emit_framebuffer_state(cmd_buffer);
3562
3563 if (info->indexed) {
3564 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3565 radv_emit_index_buffer(cmd_buffer);
3566 } else {
3567 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3568 * so the state must be re-emitted before the next indexed
3569 * draw.
3570 */
3571 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3572 cmd_buffer->state.last_index_type = -1;
3573 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3574 }
3575 }
3576
3577 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3578
3579 radv_emit_draw_registers(cmd_buffer, info->indexed,
3580 info->instance_count > 1, info->indirect,
3581 info->indirect ? 0 : info->count);
3582
3583 if (late_scissor_emission)
3584 radv_emit_scissor(cmd_buffer);
3585 }
3586
3587 static void
3588 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3589 const struct radv_draw_info *info)
3590 {
3591 struct radeon_info *rad_info =
3592 &cmd_buffer->device->physical_device->rad_info;
3593 bool has_prefetch =
3594 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3595 bool pipeline_is_dirty =
3596 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3597 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3598
3599 MAYBE_UNUSED unsigned cdw_max =
3600 radeon_check_space(cmd_buffer->device->ws,
3601 cmd_buffer->cs, 4096);
3602
3603 /* Use optimal packet order based on whether we need to sync the
3604 * pipeline.
3605 */
3606 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3607 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3608 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3609 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3610 /* If we have to wait for idle, set all states first, so that
3611 * all SET packets are processed in parallel with previous draw
3612 * calls. Then upload descriptors, set shader pointers, and
3613 * draw, and prefetch at the end. This ensures that the time
3614 * the CUs are idle is very short. (there are only SET_SH
3615 * packets between the wait and the draw)
3616 */
3617 radv_emit_all_graphics_states(cmd_buffer, info);
3618 si_emit_cache_flush(cmd_buffer);
3619 /* <-- CUs are idle here --> */
3620
3621 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3622
3623 radv_emit_draw_packets(cmd_buffer, info);
3624 /* <-- CUs are busy here --> */
3625
3626 /* Start prefetches after the draw has been started. Both will
3627 * run in parallel, but starting the draw first is more
3628 * important.
3629 */
3630 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3631 radv_emit_prefetch_L2(cmd_buffer,
3632 cmd_buffer->state.pipeline, false);
3633 }
3634 } else {
3635 /* If we don't wait for idle, start prefetches first, then set
3636 * states, and draw at the end.
3637 */
3638 si_emit_cache_flush(cmd_buffer);
3639
3640 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3641 /* Only prefetch the vertex shader and VBO descriptors
3642 * in order to start the draw as soon as possible.
3643 */
3644 radv_emit_prefetch_L2(cmd_buffer,
3645 cmd_buffer->state.pipeline, true);
3646 }
3647
3648 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3649
3650 radv_emit_all_graphics_states(cmd_buffer, info);
3651 radv_emit_draw_packets(cmd_buffer, info);
3652
3653 /* Prefetch the remaining shaders after the draw has been
3654 * started.
3655 */
3656 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3657 radv_emit_prefetch_L2(cmd_buffer,
3658 cmd_buffer->state.pipeline, false);
3659 }
3660 }
3661
3662 /* Workaround for a VGT hang when streamout is enabled.
3663 * It must be done after drawing.
3664 */
3665 if (cmd_buffer->state.streamout.streamout_enabled &&
3666 (rad_info->family == CHIP_HAWAII ||
3667 rad_info->family == CHIP_TONGA ||
3668 rad_info->family == CHIP_FIJI)) {
3669 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
3670 }
3671
3672 assert(cmd_buffer->cs->cdw <= cdw_max);
3673 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3674 }
3675
3676 void radv_CmdDraw(
3677 VkCommandBuffer commandBuffer,
3678 uint32_t vertexCount,
3679 uint32_t instanceCount,
3680 uint32_t firstVertex,
3681 uint32_t firstInstance)
3682 {
3683 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3684 struct radv_draw_info info = {};
3685
3686 info.count = vertexCount;
3687 info.instance_count = instanceCount;
3688 info.first_instance = firstInstance;
3689 info.vertex_offset = firstVertex;
3690
3691 radv_draw(cmd_buffer, &info);
3692 }
3693
3694 void radv_CmdDrawIndexed(
3695 VkCommandBuffer commandBuffer,
3696 uint32_t indexCount,
3697 uint32_t instanceCount,
3698 uint32_t firstIndex,
3699 int32_t vertexOffset,
3700 uint32_t firstInstance)
3701 {
3702 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3703 struct radv_draw_info info = {};
3704
3705 info.indexed = true;
3706 info.count = indexCount;
3707 info.instance_count = instanceCount;
3708 info.first_index = firstIndex;
3709 info.vertex_offset = vertexOffset;
3710 info.first_instance = firstInstance;
3711
3712 radv_draw(cmd_buffer, &info);
3713 }
3714
3715 void radv_CmdDrawIndirect(
3716 VkCommandBuffer commandBuffer,
3717 VkBuffer _buffer,
3718 VkDeviceSize offset,
3719 uint32_t drawCount,
3720 uint32_t stride)
3721 {
3722 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3723 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3724 struct radv_draw_info info = {};
3725
3726 info.count = drawCount;
3727 info.indirect = buffer;
3728 info.indirect_offset = offset;
3729 info.stride = stride;
3730
3731 radv_draw(cmd_buffer, &info);
3732 }
3733
3734 void radv_CmdDrawIndexedIndirect(
3735 VkCommandBuffer commandBuffer,
3736 VkBuffer _buffer,
3737 VkDeviceSize offset,
3738 uint32_t drawCount,
3739 uint32_t stride)
3740 {
3741 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3742 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3743 struct radv_draw_info info = {};
3744
3745 info.indexed = true;
3746 info.count = drawCount;
3747 info.indirect = buffer;
3748 info.indirect_offset = offset;
3749 info.stride = stride;
3750
3751 radv_draw(cmd_buffer, &info);
3752 }
3753
3754 void radv_CmdDrawIndirectCountAMD(
3755 VkCommandBuffer commandBuffer,
3756 VkBuffer _buffer,
3757 VkDeviceSize offset,
3758 VkBuffer _countBuffer,
3759 VkDeviceSize countBufferOffset,
3760 uint32_t maxDrawCount,
3761 uint32_t stride)
3762 {
3763 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3764 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3765 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3766 struct radv_draw_info info = {};
3767
3768 info.count = maxDrawCount;
3769 info.indirect = buffer;
3770 info.indirect_offset = offset;
3771 info.count_buffer = count_buffer;
3772 info.count_buffer_offset = countBufferOffset;
3773 info.stride = stride;
3774
3775 radv_draw(cmd_buffer, &info);
3776 }
3777
3778 void radv_CmdDrawIndexedIndirectCountAMD(
3779 VkCommandBuffer commandBuffer,
3780 VkBuffer _buffer,
3781 VkDeviceSize offset,
3782 VkBuffer _countBuffer,
3783 VkDeviceSize countBufferOffset,
3784 uint32_t maxDrawCount,
3785 uint32_t stride)
3786 {
3787 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3788 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3789 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3790 struct radv_draw_info info = {};
3791
3792 info.indexed = true;
3793 info.count = maxDrawCount;
3794 info.indirect = buffer;
3795 info.indirect_offset = offset;
3796 info.count_buffer = count_buffer;
3797 info.count_buffer_offset = countBufferOffset;
3798 info.stride = stride;
3799
3800 radv_draw(cmd_buffer, &info);
3801 }
3802
3803 void radv_CmdDrawIndirectCountKHR(
3804 VkCommandBuffer commandBuffer,
3805 VkBuffer _buffer,
3806 VkDeviceSize offset,
3807 VkBuffer _countBuffer,
3808 VkDeviceSize countBufferOffset,
3809 uint32_t maxDrawCount,
3810 uint32_t stride)
3811 {
3812 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3813 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3814 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3815 struct radv_draw_info info = {};
3816
3817 info.count = maxDrawCount;
3818 info.indirect = buffer;
3819 info.indirect_offset = offset;
3820 info.count_buffer = count_buffer;
3821 info.count_buffer_offset = countBufferOffset;
3822 info.stride = stride;
3823
3824 radv_draw(cmd_buffer, &info);
3825 }
3826
3827 void radv_CmdDrawIndexedIndirectCountKHR(
3828 VkCommandBuffer commandBuffer,
3829 VkBuffer _buffer,
3830 VkDeviceSize offset,
3831 VkBuffer _countBuffer,
3832 VkDeviceSize countBufferOffset,
3833 uint32_t maxDrawCount,
3834 uint32_t stride)
3835 {
3836 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3837 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3838 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3839 struct radv_draw_info info = {};
3840
3841 info.indexed = true;
3842 info.count = maxDrawCount;
3843 info.indirect = buffer;
3844 info.indirect_offset = offset;
3845 info.count_buffer = count_buffer;
3846 info.count_buffer_offset = countBufferOffset;
3847 info.stride = stride;
3848
3849 radv_draw(cmd_buffer, &info);
3850 }
3851
3852 struct radv_dispatch_info {
3853 /**
3854 * Determine the layout of the grid (in block units) to be used.
3855 */
3856 uint32_t blocks[3];
3857
3858 /**
3859 * A starting offset for the grid. If unaligned is set, the offset
3860 * must still be aligned.
3861 */
3862 uint32_t offsets[3];
3863 /**
3864 * Whether it's an unaligned compute dispatch.
3865 */
3866 bool unaligned;
3867
3868 /**
3869 * Indirect compute parameters resource.
3870 */
3871 struct radv_buffer *indirect;
3872 uint64_t indirect_offset;
3873 };
3874
3875 static void
3876 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3877 const struct radv_dispatch_info *info)
3878 {
3879 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3880 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3881 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3882 struct radeon_winsys *ws = cmd_buffer->device->ws;
3883 bool predicating = cmd_buffer->state.predicating;
3884 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3885 struct radv_userdata_info *loc;
3886
3887 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3888 AC_UD_CS_GRID_SIZE);
3889
3890 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3891
3892 if (info->indirect) {
3893 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3894
3895 va += info->indirect->offset + info->indirect_offset;
3896
3897 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3898
3899 if (loc->sgpr_idx != -1) {
3900 for (unsigned i = 0; i < 3; ++i) {
3901 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3902 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
3903 COPY_DATA_DST_SEL(COPY_DATA_REG));
3904 radeon_emit(cs, (va + 4 * i));
3905 radeon_emit(cs, (va + 4 * i) >> 32);
3906 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3907 + loc->sgpr_idx * 4) >> 2) + i);
3908 radeon_emit(cs, 0);
3909 }
3910 }
3911
3912 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3913 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
3914 PKT3_SHADER_TYPE_S(1));
3915 radeon_emit(cs, va);
3916 radeon_emit(cs, va >> 32);
3917 radeon_emit(cs, dispatch_initiator);
3918 } else {
3919 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3920 PKT3_SHADER_TYPE_S(1));
3921 radeon_emit(cs, 1);
3922 radeon_emit(cs, va);
3923 radeon_emit(cs, va >> 32);
3924
3925 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
3926 PKT3_SHADER_TYPE_S(1));
3927 radeon_emit(cs, 0);
3928 radeon_emit(cs, dispatch_initiator);
3929 }
3930 } else {
3931 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3932 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
3933
3934 if (info->unaligned) {
3935 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3936 unsigned remainder[3];
3937
3938 /* If aligned, these should be an entire block size,
3939 * not 0.
3940 */
3941 remainder[0] = blocks[0] + cs_block_size[0] -
3942 align_u32_npot(blocks[0], cs_block_size[0]);
3943 remainder[1] = blocks[1] + cs_block_size[1] -
3944 align_u32_npot(blocks[1], cs_block_size[1]);
3945 remainder[2] = blocks[2] + cs_block_size[2] -
3946 align_u32_npot(blocks[2], cs_block_size[2]);
3947
3948 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3949 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3950 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3951
3952 for(unsigned i = 0; i < 3; ++i) {
3953 assert(offsets[i] % cs_block_size[i] == 0);
3954 offsets[i] /= cs_block_size[i];
3955 }
3956
3957 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3958 radeon_emit(cs,
3959 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3960 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3961 radeon_emit(cs,
3962 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3963 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3964 radeon_emit(cs,
3965 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3966 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3967
3968 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3969 }
3970
3971 if (loc->sgpr_idx != -1) {
3972 assert(!loc->indirect);
3973 assert(loc->num_sgprs == 3);
3974
3975 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3976 loc->sgpr_idx * 4, 3);
3977 radeon_emit(cs, blocks[0]);
3978 radeon_emit(cs, blocks[1]);
3979 radeon_emit(cs, blocks[2]);
3980 }
3981
3982 if (offsets[0] || offsets[1] || offsets[2]) {
3983 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
3984 radeon_emit(cs, offsets[0]);
3985 radeon_emit(cs, offsets[1]);
3986 radeon_emit(cs, offsets[2]);
3987
3988 /* The blocks in the packet are not counts but end values. */
3989 for (unsigned i = 0; i < 3; ++i)
3990 blocks[i] += offsets[i];
3991 } else {
3992 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
3993 }
3994
3995 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
3996 PKT3_SHADER_TYPE_S(1));
3997 radeon_emit(cs, blocks[0]);
3998 radeon_emit(cs, blocks[1]);
3999 radeon_emit(cs, blocks[2]);
4000 radeon_emit(cs, dispatch_initiator);
4001 }
4002
4003 assert(cmd_buffer->cs->cdw <= cdw_max);
4004 }
4005
4006 static void
4007 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4008 {
4009 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4010 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4011 }
4012
4013 static void
4014 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4015 const struct radv_dispatch_info *info)
4016 {
4017 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4018 bool has_prefetch =
4019 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
4020 bool pipeline_is_dirty = pipeline &&
4021 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4022
4023 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4024 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4025 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4026 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4027 /* If we have to wait for idle, set all states first, so that
4028 * all SET packets are processed in parallel with previous draw
4029 * calls. Then upload descriptors, set shader pointers, and
4030 * dispatch, and prefetch at the end. This ensures that the
4031 * time the CUs are idle is very short. (there are only SET_SH
4032 * packets between the wait and the draw)
4033 */
4034 radv_emit_compute_pipeline(cmd_buffer);
4035 si_emit_cache_flush(cmd_buffer);
4036 /* <-- CUs are idle here --> */
4037
4038 radv_upload_compute_shader_descriptors(cmd_buffer);
4039
4040 radv_emit_dispatch_packets(cmd_buffer, info);
4041 /* <-- CUs are busy here --> */
4042
4043 /* Start prefetches after the dispatch has been started. Both
4044 * will run in parallel, but starting the dispatch first is
4045 * more important.
4046 */
4047 if (has_prefetch && pipeline_is_dirty) {
4048 radv_emit_shader_prefetch(cmd_buffer,
4049 pipeline->shaders[MESA_SHADER_COMPUTE]);
4050 }
4051 } else {
4052 /* If we don't wait for idle, start prefetches first, then set
4053 * states, and dispatch at the end.
4054 */
4055 si_emit_cache_flush(cmd_buffer);
4056
4057 if (has_prefetch && pipeline_is_dirty) {
4058 radv_emit_shader_prefetch(cmd_buffer,
4059 pipeline->shaders[MESA_SHADER_COMPUTE]);
4060 }
4061
4062 radv_upload_compute_shader_descriptors(cmd_buffer);
4063
4064 radv_emit_compute_pipeline(cmd_buffer);
4065 radv_emit_dispatch_packets(cmd_buffer, info);
4066 }
4067
4068 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
4069 }
4070
4071 void radv_CmdDispatchBase(
4072 VkCommandBuffer commandBuffer,
4073 uint32_t base_x,
4074 uint32_t base_y,
4075 uint32_t base_z,
4076 uint32_t x,
4077 uint32_t y,
4078 uint32_t z)
4079 {
4080 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4081 struct radv_dispatch_info info = {};
4082
4083 info.blocks[0] = x;
4084 info.blocks[1] = y;
4085 info.blocks[2] = z;
4086
4087 info.offsets[0] = base_x;
4088 info.offsets[1] = base_y;
4089 info.offsets[2] = base_z;
4090 radv_dispatch(cmd_buffer, &info);
4091 }
4092
4093 void radv_CmdDispatch(
4094 VkCommandBuffer commandBuffer,
4095 uint32_t x,
4096 uint32_t y,
4097 uint32_t z)
4098 {
4099 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4100 }
4101
4102 void radv_CmdDispatchIndirect(
4103 VkCommandBuffer commandBuffer,
4104 VkBuffer _buffer,
4105 VkDeviceSize offset)
4106 {
4107 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4108 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4109 struct radv_dispatch_info info = {};
4110
4111 info.indirect = buffer;
4112 info.indirect_offset = offset;
4113
4114 radv_dispatch(cmd_buffer, &info);
4115 }
4116
4117 void radv_unaligned_dispatch(
4118 struct radv_cmd_buffer *cmd_buffer,
4119 uint32_t x,
4120 uint32_t y,
4121 uint32_t z)
4122 {
4123 struct radv_dispatch_info info = {};
4124
4125 info.blocks[0] = x;
4126 info.blocks[1] = y;
4127 info.blocks[2] = z;
4128 info.unaligned = 1;
4129
4130 radv_dispatch(cmd_buffer, &info);
4131 }
4132
4133 void radv_CmdEndRenderPass(
4134 VkCommandBuffer commandBuffer)
4135 {
4136 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4137
4138 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
4139
4140 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4141
4142 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
4143 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
4144 radv_handle_subpass_image_transition(cmd_buffer,
4145 (struct radv_subpass_attachment){i, layout});
4146 }
4147
4148 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4149
4150 cmd_buffer->state.pass = NULL;
4151 cmd_buffer->state.subpass = NULL;
4152 cmd_buffer->state.attachments = NULL;
4153 cmd_buffer->state.framebuffer = NULL;
4154 }
4155
4156 void radv_CmdEndRenderPass2KHR(
4157 VkCommandBuffer commandBuffer,
4158 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4159 {
4160 radv_CmdEndRenderPass(commandBuffer);
4161 }
4162
4163 /*
4164 * For HTILE we have the following interesting clear words:
4165 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4166 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4167 * 0xfffffff0: Clear depth to 1.0
4168 * 0x00000000: Clear depth to 0.0
4169 */
4170 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
4171 struct radv_image *image,
4172 const VkImageSubresourceRange *range,
4173 uint32_t clear_word)
4174 {
4175 assert(range->baseMipLevel == 0);
4176 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
4177 unsigned layer_count = radv_get_layerCount(image, range);
4178 uint64_t size = image->surface.htile_slice_size * layer_count;
4179 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
4180 uint64_t offset = image->offset + image->htile_offset +
4181 image->surface.htile_slice_size * range->baseArrayLayer;
4182 struct radv_cmd_state *state = &cmd_buffer->state;
4183 VkClearDepthStencilValue value = {};
4184
4185 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4186 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4187
4188 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
4189 size, clear_word);
4190
4191 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4192
4193 if (vk_format_is_stencil(image->vk_format))
4194 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4195
4196 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4197 }
4198
4199 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4200 struct radv_image *image,
4201 VkImageLayout src_layout,
4202 VkImageLayout dst_layout,
4203 unsigned src_queue_mask,
4204 unsigned dst_queue_mask,
4205 const VkImageSubresourceRange *range,
4206 VkImageAspectFlags pending_clears)
4207 {
4208 if (!radv_image_has_htile(image))
4209 return;
4210
4211 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
4212 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
4213 /* TODO: merge with the clear if applicable */
4214 radv_initialize_htile(cmd_buffer, image, range, 0);
4215 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4216 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4217 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4218 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4219 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4220 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4221 VkImageSubresourceRange local_range = *range;
4222 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4223 local_range.baseMipLevel = 0;
4224 local_range.levelCount = 1;
4225
4226 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4227 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4228
4229 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
4230
4231 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4232 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4233 }
4234 }
4235
4236 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4237 struct radv_image *image, uint32_t value)
4238 {
4239 struct radv_cmd_state *state = &cmd_buffer->state;
4240
4241 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4242 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4243
4244 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
4245
4246 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4247 }
4248
4249 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4250 struct radv_image *image, uint32_t value)
4251 {
4252 struct radv_cmd_state *state = &cmd_buffer->state;
4253
4254 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4255 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4256
4257 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
4258
4259 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4260 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4261 }
4262
4263 /**
4264 * Initialize DCC/FMASK/CMASK metadata for a color image.
4265 */
4266 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4267 struct radv_image *image,
4268 VkImageLayout src_layout,
4269 VkImageLayout dst_layout,
4270 unsigned src_queue_mask,
4271 unsigned dst_queue_mask)
4272 {
4273 if (radv_image_has_cmask(image)) {
4274 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4275
4276 /* TODO: clarify this. */
4277 if (radv_image_has_fmask(image)) {
4278 value = 0xccccccccu;
4279 }
4280
4281 radv_initialise_cmask(cmd_buffer, image, value);
4282 }
4283
4284 if (radv_image_has_dcc(image)) {
4285 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4286 bool need_decompress_pass = false;
4287
4288 if (radv_layout_dcc_compressed(image, dst_layout,
4289 dst_queue_mask)) {
4290 value = 0x20202020u;
4291 need_decompress_pass = true;
4292 }
4293
4294 radv_initialize_dcc(cmd_buffer, image, value);
4295
4296 radv_set_dcc_need_cmask_elim_pred(cmd_buffer, image,
4297 need_decompress_pass);
4298 }
4299
4300 if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
4301 uint32_t color_values[2] = {};
4302 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
4303 }
4304 }
4305
4306 /**
4307 * Handle color image transitions for DCC/FMASK/CMASK.
4308 */
4309 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4310 struct radv_image *image,
4311 VkImageLayout src_layout,
4312 VkImageLayout dst_layout,
4313 unsigned src_queue_mask,
4314 unsigned dst_queue_mask,
4315 const VkImageSubresourceRange *range)
4316 {
4317 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4318 radv_init_color_image_metadata(cmd_buffer, image,
4319 src_layout, dst_layout,
4320 src_queue_mask, dst_queue_mask);
4321 return;
4322 }
4323
4324 if (radv_image_has_dcc(image)) {
4325 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4326 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4327 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4328 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4329 radv_decompress_dcc(cmd_buffer, image, range);
4330 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4331 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4332 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4333 }
4334 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
4335 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4336 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4337 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4338 }
4339 }
4340 }
4341
4342 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4343 struct radv_image *image,
4344 VkImageLayout src_layout,
4345 VkImageLayout dst_layout,
4346 uint32_t src_family,
4347 uint32_t dst_family,
4348 const VkImageSubresourceRange *range,
4349 VkImageAspectFlags pending_clears)
4350 {
4351 if (image->exclusive && src_family != dst_family) {
4352 /* This is an acquire or a release operation and there will be
4353 * a corresponding release/acquire. Do the transition in the
4354 * most flexible queue. */
4355
4356 assert(src_family == cmd_buffer->queue_family_index ||
4357 dst_family == cmd_buffer->queue_family_index);
4358
4359 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4360 return;
4361
4362 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4363 (src_family == RADV_QUEUE_GENERAL ||
4364 dst_family == RADV_QUEUE_GENERAL))
4365 return;
4366 }
4367
4368 unsigned src_queue_mask =
4369 radv_image_queue_family_mask(image, src_family,
4370 cmd_buffer->queue_family_index);
4371 unsigned dst_queue_mask =
4372 radv_image_queue_family_mask(image, dst_family,
4373 cmd_buffer->queue_family_index);
4374
4375 if (vk_format_is_depth(image->vk_format)) {
4376 radv_handle_depth_image_transition(cmd_buffer, image,
4377 src_layout, dst_layout,
4378 src_queue_mask, dst_queue_mask,
4379 range, pending_clears);
4380 } else {
4381 radv_handle_color_image_transition(cmd_buffer, image,
4382 src_layout, dst_layout,
4383 src_queue_mask, dst_queue_mask,
4384 range);
4385 }
4386 }
4387
4388 struct radv_barrier_info {
4389 uint32_t eventCount;
4390 const VkEvent *pEvents;
4391 VkPipelineStageFlags srcStageMask;
4392 };
4393
4394 static void
4395 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
4396 uint32_t memoryBarrierCount,
4397 const VkMemoryBarrier *pMemoryBarriers,
4398 uint32_t bufferMemoryBarrierCount,
4399 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4400 uint32_t imageMemoryBarrierCount,
4401 const VkImageMemoryBarrier *pImageMemoryBarriers,
4402 const struct radv_barrier_info *info)
4403 {
4404 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4405 enum radv_cmd_flush_bits src_flush_bits = 0;
4406 enum radv_cmd_flush_bits dst_flush_bits = 0;
4407
4408 for (unsigned i = 0; i < info->eventCount; ++i) {
4409 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
4410 uint64_t va = radv_buffer_get_va(event->bo);
4411
4412 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4413
4414 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4415
4416 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
4417 assert(cmd_buffer->cs->cdw <= cdw_max);
4418 }
4419
4420 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4421 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
4422 NULL);
4423 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4424 NULL);
4425 }
4426
4427 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4428 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
4429 NULL);
4430 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4431 NULL);
4432 }
4433
4434 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4435 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4436
4437 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
4438 image);
4439 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4440 image);
4441 }
4442
4443 radv_stage_flush(cmd_buffer, info->srcStageMask);
4444 cmd_buffer->state.flush_bits |= src_flush_bits;
4445
4446 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4447 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4448 radv_handle_image_transition(cmd_buffer, image,
4449 pImageMemoryBarriers[i].oldLayout,
4450 pImageMemoryBarriers[i].newLayout,
4451 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4452 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4453 &pImageMemoryBarriers[i].subresourceRange,
4454 0);
4455 }
4456
4457 /* Make sure CP DMA is idle because the driver might have performed a
4458 * DMA operation for copying or filling buffers/images.
4459 */
4460 si_cp_dma_wait_for_idle(cmd_buffer);
4461
4462 cmd_buffer->state.flush_bits |= dst_flush_bits;
4463 }
4464
4465 void radv_CmdPipelineBarrier(
4466 VkCommandBuffer commandBuffer,
4467 VkPipelineStageFlags srcStageMask,
4468 VkPipelineStageFlags destStageMask,
4469 VkBool32 byRegion,
4470 uint32_t memoryBarrierCount,
4471 const VkMemoryBarrier* pMemoryBarriers,
4472 uint32_t bufferMemoryBarrierCount,
4473 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4474 uint32_t imageMemoryBarrierCount,
4475 const VkImageMemoryBarrier* pImageMemoryBarriers)
4476 {
4477 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4478 struct radv_barrier_info info;
4479
4480 info.eventCount = 0;
4481 info.pEvents = NULL;
4482 info.srcStageMask = srcStageMask;
4483
4484 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4485 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4486 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4487 }
4488
4489
4490 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4491 struct radv_event *event,
4492 VkPipelineStageFlags stageMask,
4493 unsigned value)
4494 {
4495 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4496 uint64_t va = radv_buffer_get_va(event->bo);
4497
4498 si_emit_cache_flush(cmd_buffer);
4499
4500 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4501
4502 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4503
4504 /* Flags that only require a top-of-pipe event. */
4505 VkPipelineStageFlags top_of_pipe_flags =
4506 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
4507
4508 /* Flags that only require a post-index-fetch event. */
4509 VkPipelineStageFlags post_index_fetch_flags =
4510 top_of_pipe_flags |
4511 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
4512 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
4513
4514 /* Make sure CP DMA is idle because the driver might have performed a
4515 * DMA operation for copying or filling buffers/images.
4516 */
4517 si_cp_dma_wait_for_idle(cmd_buffer);
4518
4519 /* TODO: Emit EOS events for syncing PS/CS stages. */
4520
4521 if (!(stageMask & ~top_of_pipe_flags)) {
4522 /* Just need to sync the PFP engine. */
4523 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4524 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
4525 S_370_WR_CONFIRM(1) |
4526 S_370_ENGINE_SEL(V_370_PFP));
4527 radeon_emit(cs, va);
4528 radeon_emit(cs, va >> 32);
4529 radeon_emit(cs, value);
4530 } else if (!(stageMask & ~post_index_fetch_flags)) {
4531 /* Sync ME because PFP reads index and indirect buffers. */
4532 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4533 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
4534 S_370_WR_CONFIRM(1) |
4535 S_370_ENGINE_SEL(V_370_ME));
4536 radeon_emit(cs, va);
4537 radeon_emit(cs, va >> 32);
4538 radeon_emit(cs, value);
4539 } else {
4540 /* Otherwise, sync all prior GPU work using an EOP event. */
4541 si_cs_emit_write_event_eop(cs,
4542 cmd_buffer->device->physical_device->rad_info.chip_class,
4543 radv_cmd_buffer_uses_mec(cmd_buffer),
4544 V_028A90_BOTTOM_OF_PIPE_TS, 0,
4545 EOP_DATA_SEL_VALUE_32BIT, va, 2, value,
4546 cmd_buffer->gfx9_eop_bug_va);
4547 }
4548
4549 assert(cmd_buffer->cs->cdw <= cdw_max);
4550 }
4551
4552 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4553 VkEvent _event,
4554 VkPipelineStageFlags stageMask)
4555 {
4556 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4557 RADV_FROM_HANDLE(radv_event, event, _event);
4558
4559 write_event(cmd_buffer, event, stageMask, 1);
4560 }
4561
4562 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4563 VkEvent _event,
4564 VkPipelineStageFlags stageMask)
4565 {
4566 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4567 RADV_FROM_HANDLE(radv_event, event, _event);
4568
4569 write_event(cmd_buffer, event, stageMask, 0);
4570 }
4571
4572 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4573 uint32_t eventCount,
4574 const VkEvent* pEvents,
4575 VkPipelineStageFlags srcStageMask,
4576 VkPipelineStageFlags dstStageMask,
4577 uint32_t memoryBarrierCount,
4578 const VkMemoryBarrier* pMemoryBarriers,
4579 uint32_t bufferMemoryBarrierCount,
4580 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4581 uint32_t imageMemoryBarrierCount,
4582 const VkImageMemoryBarrier* pImageMemoryBarriers)
4583 {
4584 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4585 struct radv_barrier_info info;
4586
4587 info.eventCount = eventCount;
4588 info.pEvents = pEvents;
4589 info.srcStageMask = 0;
4590
4591 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4592 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4593 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4594 }
4595
4596
4597 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4598 uint32_t deviceMask)
4599 {
4600 /* No-op */
4601 }
4602
4603 /* VK_EXT_conditional_rendering */
4604 void radv_CmdBeginConditionalRenderingEXT(
4605 VkCommandBuffer commandBuffer,
4606 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
4607 {
4608 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4609 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
4610 bool draw_visible = true;
4611 uint64_t va;
4612
4613 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
4614
4615 /* By default, if the 32-bit value at offset in buffer memory is zero,
4616 * then the rendering commands are discarded, otherwise they are
4617 * executed as normal. If the inverted flag is set, all commands are
4618 * discarded if the value is non zero.
4619 */
4620 if (pConditionalRenderingBegin->flags &
4621 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
4622 draw_visible = false;
4623 }
4624
4625 /* Enable predication for this command buffer. */
4626 si_emit_set_predication_state(cmd_buffer, draw_visible, va);
4627 cmd_buffer->state.predicating = true;
4628
4629 /* Store conditional rendering user info. */
4630 cmd_buffer->state.predication_type = draw_visible;
4631 cmd_buffer->state.predication_va = va;
4632 }
4633
4634 void radv_CmdEndConditionalRenderingEXT(
4635 VkCommandBuffer commandBuffer)
4636 {
4637 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4638
4639 /* Disable predication for this command buffer. */
4640 si_emit_set_predication_state(cmd_buffer, false, 0);
4641 cmd_buffer->state.predicating = false;
4642
4643 /* Reset conditional rendering user info. */
4644 cmd_buffer->state.predication_type = -1;
4645 cmd_buffer->state.predication_va = 0;
4646 }
4647
4648 /* VK_EXT_transform_feedback */
4649 void radv_CmdBindTransformFeedbackBuffersEXT(
4650 VkCommandBuffer commandBuffer,
4651 uint32_t firstBinding,
4652 uint32_t bindingCount,
4653 const VkBuffer* pBuffers,
4654 const VkDeviceSize* pOffsets,
4655 const VkDeviceSize* pSizes)
4656 {
4657 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4658 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
4659 uint8_t enabled_mask = 0;
4660
4661 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
4662 for (uint32_t i = 0; i < bindingCount; i++) {
4663 uint32_t idx = firstBinding + i;
4664
4665 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
4666 sb[idx].offset = pOffsets[i];
4667 sb[idx].size = pSizes[i];
4668
4669 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
4670 sb[idx].buffer->bo);
4671
4672 enabled_mask |= 1 << idx;
4673 }
4674
4675 cmd_buffer->state.streamout.enabled_mask = enabled_mask;
4676
4677 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
4678 }
4679
4680 static void
4681 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
4682 {
4683 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4684 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4685
4686 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
4687 radeon_emit(cs,
4688 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
4689 S_028B94_RAST_STREAM(0) |
4690 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
4691 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
4692 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
4693 radeon_emit(cs, so->hw_enabled_mask &
4694 so->enabled_stream_buffers_mask);
4695 }
4696
4697 static void
4698 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
4699 {
4700 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4701 bool old_streamout_enabled = so->streamout_enabled;
4702 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
4703
4704 so->streamout_enabled = enable;
4705
4706 so->hw_enabled_mask = so->enabled_mask |
4707 (so->enabled_mask << 4) |
4708 (so->enabled_mask << 8) |
4709 (so->enabled_mask << 12);
4710
4711 if ((old_streamout_enabled != so->streamout_enabled) ||
4712 (old_hw_enabled_mask != so->hw_enabled_mask))
4713 radv_emit_streamout_enable(cmd_buffer);
4714 }
4715
4716 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
4717 {
4718 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4719 unsigned reg_strmout_cntl;
4720
4721 /* The register is at different places on different ASICs. */
4722 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
4723 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
4724 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
4725 } else {
4726 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
4727 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
4728 }
4729
4730 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4731 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
4732
4733 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
4734 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
4735 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
4736 radeon_emit(cs, 0);
4737 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
4738 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
4739 radeon_emit(cs, 4); /* poll interval */
4740 }
4741
4742 void radv_CmdBeginTransformFeedbackEXT(
4743 VkCommandBuffer commandBuffer,
4744 uint32_t firstCounterBuffer,
4745 uint32_t counterBufferCount,
4746 const VkBuffer* pCounterBuffers,
4747 const VkDeviceSize* pCounterBufferOffsets)
4748 {
4749 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4750 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
4751 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4752 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4753 uint32_t i;
4754
4755 radv_flush_vgt_streamout(cmd_buffer);
4756
4757 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
4758 for_each_bit(i, so->enabled_mask) {
4759 int32_t counter_buffer_idx = i - firstCounterBuffer;
4760 if (counter_buffer_idx >= 0 && counter_buffer_idx > counterBufferCount)
4761 counter_buffer_idx = -1;
4762
4763 /* SI binds streamout buffers as shader resources.
4764 * VGT only counts primitives and tells the shader through
4765 * SGPRs what to do.
4766 */
4767 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
4768 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
4769 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
4770
4771 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
4772 /* The array of counter buffers is optional. */
4773 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
4774 uint64_t va = radv_buffer_get_va(buffer->bo);
4775
4776 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
4777
4778 /* Append */
4779 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
4780 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
4781 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4782 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
4783 radeon_emit(cs, 0); /* unused */
4784 radeon_emit(cs, 0); /* unused */
4785 radeon_emit(cs, va); /* src address lo */
4786 radeon_emit(cs, va >> 32); /* src address hi */
4787
4788 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
4789 } else {
4790 /* Start from the beginning. */
4791 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
4792 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
4793 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4794 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
4795 radeon_emit(cs, 0); /* unused */
4796 radeon_emit(cs, 0); /* unused */
4797 radeon_emit(cs, 0); /* unused */
4798 radeon_emit(cs, 0); /* unused */
4799 }
4800 }
4801
4802 radv_set_streamout_enable(cmd_buffer, true);
4803 }
4804
4805 void radv_CmdEndTransformFeedbackEXT(
4806 VkCommandBuffer commandBuffer,
4807 uint32_t firstCounterBuffer,
4808 uint32_t counterBufferCount,
4809 const VkBuffer* pCounterBuffers,
4810 const VkDeviceSize* pCounterBufferOffsets)
4811 {
4812 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4813 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4814 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4815 uint32_t i;
4816
4817 radv_flush_vgt_streamout(cmd_buffer);
4818
4819 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
4820 for_each_bit(i, so->enabled_mask) {
4821 int32_t counter_buffer_idx = i - firstCounterBuffer;
4822 if (counter_buffer_idx >= 0 && counter_buffer_idx > counterBufferCount)
4823 counter_buffer_idx = -1;
4824
4825 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
4826 /* The array of counters buffer is optional. */
4827 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
4828 uint64_t va = radv_buffer_get_va(buffer->bo);
4829
4830 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
4831
4832 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
4833 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
4834 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4835 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
4836 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
4837 radeon_emit(cs, va); /* dst address lo */
4838 radeon_emit(cs, va >> 32); /* dst address hi */
4839 radeon_emit(cs, 0); /* unused */
4840 radeon_emit(cs, 0); /* unused */
4841
4842 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
4843 }
4844
4845 /* Deactivate transform feedback by zeroing the buffer size.
4846 * The counters (primitives generated, primitives emitted) may
4847 * be enabled even if there is not buffer bound. This ensures
4848 * that the primitives-emitted query won't increment.
4849 */
4850 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
4851 }
4852
4853 radv_set_streamout_enable(cmd_buffer, false);
4854 }
4855
4856 void radv_CmdDrawIndirectByteCountEXT(
4857 VkCommandBuffer commandBuffer,
4858 uint32_t instanceCount,
4859 uint32_t firstInstance,
4860 VkBuffer _counterBuffer,
4861 VkDeviceSize counterBufferOffset,
4862 uint32_t counterOffset,
4863 uint32_t vertexStride)
4864 {
4865 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4866 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
4867 struct radv_draw_info info = {};
4868
4869 info.instance_count = instanceCount;
4870 info.first_instance = firstInstance;
4871 info.strmout_buffer = counterBuffer;
4872 info.strmout_buffer_offset = counterBufferOffset;
4873 info.stride = vertexStride;
4874
4875 radv_draw(cmd_buffer, &info);
4876 }