2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
32 #include "vk_format.h"
33 #include "radv_meta.h"
35 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
36 struct radv_image
*image
,
37 VkImageLayout src_layout
,
38 VkImageLayout dst_layout
,
39 VkImageSubresourceRange range
,
40 VkImageAspectFlags pending_clears
);
42 const struct radv_dynamic_state default_dynamic_state
= {
55 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
60 .stencil_compare_mask
= {
64 .stencil_write_mask
= {
68 .stencil_reference
= {
75 radv_dynamic_state_copy(struct radv_dynamic_state
*dest
,
76 const struct radv_dynamic_state
*src
,
79 if (copy_mask
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
80 dest
->viewport
.count
= src
->viewport
.count
;
81 typed_memcpy(dest
->viewport
.viewports
, src
->viewport
.viewports
,
85 if (copy_mask
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
86 dest
->scissor
.count
= src
->scissor
.count
;
87 typed_memcpy(dest
->scissor
.scissors
, src
->scissor
.scissors
,
91 if (copy_mask
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
))
92 dest
->line_width
= src
->line_width
;
94 if (copy_mask
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
))
95 dest
->depth_bias
= src
->depth_bias
;
97 if (copy_mask
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
))
98 typed_memcpy(dest
->blend_constants
, src
->blend_constants
, 4);
100 if (copy_mask
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
))
101 dest
->depth_bounds
= src
->depth_bounds
;
103 if (copy_mask
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
))
104 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
106 if (copy_mask
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
))
107 dest
->stencil_write_mask
= src
->stencil_write_mask
;
109 if (copy_mask
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
))
110 dest
->stencil_reference
= src
->stencil_reference
;
113 static VkResult
radv_create_cmd_buffer(
114 struct radv_device
* device
,
115 struct radv_cmd_pool
* pool
,
116 VkCommandBufferLevel level
,
117 VkCommandBuffer
* pCommandBuffer
)
119 struct radv_cmd_buffer
*cmd_buffer
;
122 cmd_buffer
= radv_alloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
123 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
124 if (cmd_buffer
== NULL
)
125 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
127 memset(cmd_buffer
, 0, sizeof(*cmd_buffer
));
128 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
129 cmd_buffer
->device
= device
;
130 cmd_buffer
->pool
= pool
;
131 cmd_buffer
->level
= level
;
134 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
136 /* Init the pool_link so we can safefly call list_del when we destroy
139 list_inithead(&cmd_buffer
->pool_link
);
142 cmd_buffer
->cs
= device
->ws
->cs_create(device
->ws
, RING_GFX
);
143 if (!cmd_buffer
->cs
) {
144 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
148 *pCommandBuffer
= radv_cmd_buffer_to_handle(cmd_buffer
);
150 cmd_buffer
->upload
.offset
= 0;
151 cmd_buffer
->upload
.size
= 0;
152 list_inithead(&cmd_buffer
->upload
.list
);
157 radv_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
163 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer
*cmd_buffer
,
167 struct radeon_winsys_bo
*bo
;
168 struct radv_cmd_buffer_upload
*upload
;
169 struct radv_device
*device
= cmd_buffer
->device
;
171 new_size
= MAX2(min_needed
, 16 * 1024);
172 new_size
= MAX2(new_size
, 2 * cmd_buffer
->upload
.size
);
174 bo
= device
->ws
->buffer_create(device
->ws
,
177 RADEON_FLAG_CPU_ACCESS
);
180 cmd_buffer
->record_fail
= true;
184 device
->ws
->cs_add_buffer(cmd_buffer
->cs
, bo
, 8);
185 if (cmd_buffer
->upload
.upload_bo
) {
186 upload
= malloc(sizeof(*upload
));
189 cmd_buffer
->record_fail
= true;
190 device
->ws
->buffer_destroy(bo
);
194 memcpy(upload
, &cmd_buffer
->upload
, sizeof(*upload
));
195 list_add(&upload
->list
, &cmd_buffer
->upload
.list
);
198 cmd_buffer
->upload
.upload_bo
= bo
;
199 cmd_buffer
->upload
.size
= new_size
;
200 cmd_buffer
->upload
.offset
= 0;
201 cmd_buffer
->upload
.map
= device
->ws
->buffer_map(cmd_buffer
->upload
.upload_bo
);
203 if (!cmd_buffer
->upload
.map
) {
204 cmd_buffer
->record_fail
= true;
212 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
215 unsigned *out_offset
,
218 uint64_t offset
= align(cmd_buffer
->upload
.offset
, alignment
);
219 if (offset
+ size
> cmd_buffer
->upload
.size
) {
220 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer
, size
))
225 *out_offset
= offset
;
226 *ptr
= cmd_buffer
->upload
.map
+ offset
;
228 cmd_buffer
->upload
.offset
= offset
+ size
;
233 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
234 unsigned size
, unsigned alignment
,
235 const void *data
, unsigned *out_offset
)
239 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
, alignment
,
240 out_offset
, (void **)&ptr
))
244 memcpy(ptr
, data
, size
);
250 radv_emit_graphics_blend_state(struct radv_cmd_buffer
*cmd_buffer
,
251 struct radv_pipeline
*pipeline
)
253 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028780_CB_BLEND0_CONTROL
, 8);
254 radeon_emit_array(cmd_buffer
->cs
, pipeline
->graphics
.blend
.cb_blend_control
,
256 radeon_set_context_reg(cmd_buffer
->cs
, R_028808_CB_COLOR_CONTROL
, pipeline
->graphics
.blend
.cb_color_control
);
257 radeon_set_context_reg(cmd_buffer
->cs
, R_028B70_DB_ALPHA_TO_MASK
, pipeline
->graphics
.blend
.db_alpha_to_mask
);
261 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer
*cmd_buffer
,
262 struct radv_pipeline
*pipeline
)
264 struct radv_depth_stencil_state
*ds
= &pipeline
->graphics
.ds
;
265 radeon_set_context_reg(cmd_buffer
->cs
, R_028800_DB_DEPTH_CONTROL
, ds
->db_depth_control
);
266 radeon_set_context_reg(cmd_buffer
->cs
, R_02842C_DB_STENCIL_CONTROL
, ds
->db_stencil_control
);
268 radeon_set_context_reg(cmd_buffer
->cs
, R_028000_DB_RENDER_CONTROL
, ds
->db_render_control
);
269 radeon_set_context_reg(cmd_buffer
->cs
, R_028010_DB_RENDER_OVERRIDE2
, ds
->db_render_override2
);
272 /* 12.4 fixed-point */
273 static unsigned radv_pack_float_12p4(float x
)
276 x
>= 4096 ? 0xffff : x
* 16;
280 radv_update_multisample_state(struct radv_cmd_buffer
*cmd_buffer
,
281 struct radv_pipeline
*pipeline
)
283 int num_samples
= pipeline
->graphics
.ms
.num_samples
;
284 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
285 struct radv_pipeline
*old_pipeline
= cmd_buffer
->state
.emitted_pipeline
;
287 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
288 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_mask
[0]);
289 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_mask
[1]);
291 if (old_pipeline
&& num_samples
== old_pipeline
->graphics
.ms
.num_samples
)
294 radeon_set_context_reg_seq(cmd_buffer
->cs
, CM_R_028BDC_PA_SC_LINE_CNTL
, 2);
295 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_line_cntl
);
296 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_config
);
298 radeon_set_context_reg(cmd_buffer
->cs
, CM_R_028804_DB_EQAA
, ms
->db_eqaa
);
299 radeon_set_context_reg(cmd_buffer
->cs
, EG_R_028A4C_PA_SC_MODE_CNTL_1
, ms
->pa_sc_mode_cntl_1
);
301 radv_cayman_emit_msaa_sample_locs(cmd_buffer
->cs
, num_samples
);
303 uint32_t samples_offset
;
306 radv_cmd_buffer_upload_alloc(cmd_buffer
, num_samples
* 4 * 2, 256, &samples_offset
,
308 switch (num_samples
) {
310 src
= cmd_buffer
->device
->sample_locations_1x
;
313 src
= cmd_buffer
->device
->sample_locations_2x
;
316 src
= cmd_buffer
->device
->sample_locations_4x
;
319 src
= cmd_buffer
->device
->sample_locations_8x
;
322 src
= cmd_buffer
->device
->sample_locations_16x
;
325 memcpy(samples_ptr
, src
, num_samples
* 4 * 2);
327 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(cmd_buffer
->upload
.upload_bo
);
328 va
+= samples_offset
;
330 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B030_SPI_SHADER_USER_DATA_PS_0
+ 10 * 4, 2);
331 radeon_emit(cmd_buffer
->cs
, va
);
332 radeon_emit(cmd_buffer
->cs
, va
>> 32);
336 radv_emit_graphics_raster_state(struct radv_cmd_buffer
*cmd_buffer
,
337 struct radv_pipeline
*pipeline
)
339 struct radv_raster_state
*raster
= &pipeline
->graphics
.raster
;
341 radeon_set_context_reg(cmd_buffer
->cs
, R_028810_PA_CL_CLIP_CNTL
,
342 raster
->pa_cl_clip_cntl
);
344 radeon_set_context_reg(cmd_buffer
->cs
, R_0286D4_SPI_INTERP_CONTROL_0
,
345 raster
->spi_interp_control
);
347 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028A00_PA_SU_POINT_SIZE
, 2);
348 radeon_emit(cmd_buffer
->cs
, 0);
349 radeon_emit(cmd_buffer
->cs
, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
350 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
352 radeon_set_context_reg(cmd_buffer
->cs
, R_028BE4_PA_SU_VTX_CNTL
,
353 raster
->pa_su_vtx_cntl
);
355 radeon_set_context_reg(cmd_buffer
->cs
, R_028814_PA_SU_SC_MODE_CNTL
,
356 raster
->pa_su_sc_mode_cntl
);
360 radv_emit_vertex_shader(struct radv_cmd_buffer
*cmd_buffer
,
361 struct radv_pipeline
*pipeline
)
363 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
364 struct radv_shader_variant
*vs
;
366 unsigned export_count
;
367 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
369 assert (pipeline
->shaders
[MESA_SHADER_VERTEX
]);
371 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
372 va
= ws
->buffer_get_va(vs
->bo
);
373 ws
->cs_add_buffer(cmd_buffer
->cs
, vs
->bo
, 8);
375 clip_dist_mask
= vs
->info
.vs
.clip_dist_mask
;
376 cull_dist_mask
= vs
->info
.vs
.cull_dist_mask
;
377 total_mask
= clip_dist_mask
| cull_dist_mask
;
378 radeon_set_context_reg(cmd_buffer
->cs
, R_028A40_VGT_GS_MODE
, 0);
379 radeon_set_context_reg(cmd_buffer
->cs
, R_028A84_VGT_PRIMITIVEID_EN
, 0);
381 export_count
= MAX2(1, vs
->info
.vs
.param_exports
);
382 radeon_set_context_reg(cmd_buffer
->cs
, R_0286C4_SPI_VS_OUT_CONFIG
,
383 S_0286C4_VS_EXPORT_COUNT(export_count
- 1));
384 radeon_set_context_reg(cmd_buffer
->cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
385 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
386 S_02870C_POS1_EXPORT_FORMAT(vs
->info
.vs
.pos_exports
> 1 ?
387 V_02870C_SPI_SHADER_4COMP
:
388 V_02870C_SPI_SHADER_NONE
) |
389 S_02870C_POS2_EXPORT_FORMAT(vs
->info
.vs
.pos_exports
> 2 ?
390 V_02870C_SPI_SHADER_4COMP
:
391 V_02870C_SPI_SHADER_NONE
) |
392 S_02870C_POS3_EXPORT_FORMAT(vs
->info
.vs
.pos_exports
> 3 ?
393 V_02870C_SPI_SHADER_4COMP
:
394 V_02870C_SPI_SHADER_NONE
));
396 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B120_SPI_SHADER_PGM_LO_VS
, 4);
397 radeon_emit(cmd_buffer
->cs
, va
>> 8);
398 radeon_emit(cmd_buffer
->cs
, va
>> 40);
399 radeon_emit(cmd_buffer
->cs
, vs
->rsrc1
);
400 radeon_emit(cmd_buffer
->cs
, vs
->rsrc2
);
402 radeon_set_context_reg(cmd_buffer
->cs
, R_028818_PA_CL_VTE_CNTL
,
403 S_028818_VTX_W0_FMT(1) |
404 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
405 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
406 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
408 radeon_set_context_reg(cmd_buffer
->cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
409 S_02881C_USE_VTX_POINT_SIZE(vs
->info
.vs
.writes_pointsize
) |
410 S_02881C_VS_OUT_MISC_VEC_ENA(vs
->info
.vs
.writes_pointsize
) |
411 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
412 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
413 pipeline
->graphics
.raster
.pa_cl_vs_out_cntl
|
414 cull_dist_mask
<< 8 |
422 radv_emit_fragment_shader(struct radv_cmd_buffer
*cmd_buffer
,
423 struct radv_pipeline
*pipeline
)
425 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
426 struct radv_shader_variant
*ps
, *vs
;
428 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
429 struct radv_blend_state
*blend
= &pipeline
->graphics
.blend
;
430 unsigned ps_offset
= 0;
432 assert (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
434 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
435 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
436 va
= ws
->buffer_get_va(ps
->bo
);
437 ws
->cs_add_buffer(cmd_buffer
->cs
, ps
->bo
, 8);
439 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B020_SPI_SHADER_PGM_LO_PS
, 4);
440 radeon_emit(cmd_buffer
->cs
, va
>> 8);
441 radeon_emit(cmd_buffer
->cs
, va
>> 40);
442 radeon_emit(cmd_buffer
->cs
, ps
->rsrc1
);
443 radeon_emit(cmd_buffer
->cs
, ps
->rsrc2
);
445 if (ps
->info
.fs
.early_fragment_test
|| !ps
->info
.fs
.writes_memory
)
446 z_order
= V_02880C_EARLY_Z_THEN_LATE_Z
;
448 z_order
= V_02880C_LATE_Z
;
451 radeon_set_context_reg(cmd_buffer
->cs
, R_02880C_DB_SHADER_CONTROL
,
452 S_02880C_Z_EXPORT_ENABLE(ps
->info
.fs
.writes_z
) |
453 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps
->info
.fs
.writes_stencil
) |
454 S_02880C_KILL_ENABLE(!!ps
->info
.fs
.can_discard
) |
455 S_02880C_Z_ORDER(z_order
) |
456 S_02880C_DEPTH_BEFORE_SHADER(ps
->info
.fs
.early_fragment_test
) |
457 S_02880C_EXEC_ON_HIER_FAIL(ps
->info
.fs
.writes_memory
) |
458 S_02880C_EXEC_ON_NOOP(ps
->info
.fs
.writes_memory
));
460 radeon_set_context_reg(cmd_buffer
->cs
, R_0286CC_SPI_PS_INPUT_ENA
,
461 ps
->config
.spi_ps_input_ena
);
463 radeon_set_context_reg(cmd_buffer
->cs
, R_0286D0_SPI_PS_INPUT_ADDR
,
464 ps
->config
.spi_ps_input_addr
);
466 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
467 radeon_set_context_reg(cmd_buffer
->cs
, R_0286D8_SPI_PS_IN_CONTROL
,
468 S_0286D8_NUM_INTERP(ps
->info
.fs
.num_interp
));
470 radeon_set_context_reg(cmd_buffer
->cs
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
472 radeon_set_context_reg(cmd_buffer
->cs
, R_028710_SPI_SHADER_Z_FORMAT
,
473 ps
->info
.fs
.writes_stencil
? V_028710_SPI_SHADER_32_GR
:
474 ps
->info
.fs
.writes_z
? V_028710_SPI_SHADER_32_R
:
475 V_028710_SPI_SHADER_ZERO
);
477 radeon_set_context_reg(cmd_buffer
->cs
, R_028714_SPI_SHADER_COL_FORMAT
, blend
->spi_shader_col_format
);
479 radeon_set_context_reg(cmd_buffer
->cs
, R_028238_CB_TARGET_MASK
, blend
->cb_target_mask
);
480 radeon_set_context_reg(cmd_buffer
->cs
, R_02823C_CB_SHADER_MASK
, blend
->cb_shader_mask
);
482 if (ps
->info
.fs
.has_pcoord
) {
484 val
= S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
485 radeon_set_context_reg(cmd_buffer
->cs
, R_028644_SPI_PS_INPUT_CNTL_0
+ 4 * ps_offset
, val
);
489 for (unsigned i
= 0; i
< 32 && (1u << i
) <= ps
->info
.fs
.input_mask
; ++i
) {
490 unsigned vs_offset
, flat_shade
;
493 if (!(ps
->info
.fs
.input_mask
& (1u << i
)))
497 if (!(vs
->info
.vs
.export_mask
& (1u << i
))) {
498 radeon_set_context_reg(cmd_buffer
->cs
, R_028644_SPI_PS_INPUT_CNTL_0
+ 4 * ps_offset
,
499 S_028644_OFFSET(0x20));
504 vs_offset
= util_bitcount(vs
->info
.vs
.export_mask
& ((1u << i
) - 1));
505 flat_shade
= !!(ps
->info
.fs
.flat_shaded_mask
& (1u << ps_offset
));
507 val
= S_028644_OFFSET(vs_offset
) | S_028644_FLAT_SHADE(flat_shade
);
508 radeon_set_context_reg(cmd_buffer
->cs
, R_028644_SPI_PS_INPUT_CNTL_0
+ 4 * ps_offset
, val
);
514 radv_emit_graphics_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
515 struct radv_pipeline
*pipeline
)
517 if (!pipeline
|| cmd_buffer
->state
.emitted_pipeline
== pipeline
)
520 radv_emit_graphics_depth_stencil_state(cmd_buffer
, pipeline
);
521 radv_emit_graphics_blend_state(cmd_buffer
, pipeline
);
522 radv_emit_graphics_raster_state(cmd_buffer
, pipeline
);
523 radv_update_multisample_state(cmd_buffer
, pipeline
);
524 radv_emit_vertex_shader(cmd_buffer
, pipeline
);
525 radv_emit_fragment_shader(cmd_buffer
, pipeline
);
527 radeon_set_context_reg(cmd_buffer
->cs
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
,
528 pipeline
->graphics
.prim_restart_enable
);
530 cmd_buffer
->state
.emitted_pipeline
= pipeline
;
534 radv_emit_viewport(struct radv_cmd_buffer
*cmd_buffer
)
536 si_write_viewport(cmd_buffer
->cs
, 0, cmd_buffer
->state
.dynamic
.viewport
.count
,
537 cmd_buffer
->state
.dynamic
.viewport
.viewports
);
541 radv_emit_scissor(struct radv_cmd_buffer
*cmd_buffer
)
543 uint32_t count
= cmd_buffer
->state
.dynamic
.scissor
.count
;
544 si_write_scissors(cmd_buffer
->cs
, 0, count
,
545 cmd_buffer
->state
.dynamic
.scissor
.scissors
);
546 radeon_set_context_reg(cmd_buffer
->cs
, R_028A48_PA_SC_MODE_CNTL_0
,
547 cmd_buffer
->state
.pipeline
->graphics
.ms
.pa_sc_mode_cntl_0
| S_028A48_VPORT_SCISSOR_ENABLE(count
? 1 : 0));
551 radv_emit_fb_color_state(struct radv_cmd_buffer
*cmd_buffer
,
553 struct radv_color_buffer_info
*cb
)
555 bool is_vi
= cmd_buffer
->device
->instance
->physicalDevice
.rad_info
.chip_class
>= VI
;
556 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
557 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
558 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_pitch
);
559 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_slice
);
560 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
561 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_info
);
562 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
563 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
564 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
565 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask_slice
);
566 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
567 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask_slice
);
569 if (is_vi
) { /* DCC BASE */
570 radeon_set_context_reg(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, cb
->cb_dcc_base
);
575 radv_emit_fb_ds_state(struct radv_cmd_buffer
*cmd_buffer
,
576 struct radv_ds_buffer_info
*ds
,
577 struct radv_image
*image
,
578 VkImageLayout layout
)
580 uint32_t db_z_info
= ds
->db_z_info
;
582 if (!radv_layout_has_htile(image
, layout
))
583 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
585 if (!radv_layout_can_expclear(image
, layout
))
586 db_z_info
&= C_028040_ALLOW_EXPCLEAR
& C_028044_ALLOW_EXPCLEAR
;
588 radeon_set_context_reg(cmd_buffer
->cs
, R_028008_DB_DEPTH_VIEW
, ds
->db_depth_view
);
589 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
591 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 9);
592 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_info
); /* R_02803C_DB_DEPTH_INFO */
593 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* R_028040_DB_Z_INFO */
594 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
595 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* R_028048_DB_Z_READ_BASE */
596 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* R_02804C_DB_STENCIL_READ_BASE */
597 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* R_028050_DB_Z_WRITE_BASE */
598 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
599 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
600 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
602 radeon_set_context_reg(cmd_buffer
->cs
, R_028ABC_DB_HTILE_SURFACE
, ds
->db_htile_surface
);
603 radeon_set_context_reg(cmd_buffer
->cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
604 ds
->pa_su_poly_offset_db_fmt_cntl
);
608 * To hw resolve multisample images both src and dst need to have the same
609 * micro tiling mode. However we don't always know in advance when creating
610 * the images. This function gets called if we have a resolve attachment,
611 * and tests if the attachment image has the same tiling mode, then it
612 * checks if the generated framebuffer data has the same tiling mode, and
615 static void radv_set_optimal_micro_tile_mode(struct radv_device
*device
,
616 struct radv_attachment_info
*att
,
617 uint32_t micro_tile_mode
)
619 struct radv_image
*image
= att
->attachment
->image
;
620 uint32_t tile_mode_index
;
621 if (image
->surface
.nsamples
<= 1)
624 if (image
->surface
.micro_tile_mode
!= micro_tile_mode
) {
625 radv_image_set_optimal_micro_tile_mode(device
, image
, micro_tile_mode
);
628 if (att
->cb
.micro_tile_mode
!= micro_tile_mode
) {
629 tile_mode_index
= image
->surface
.tiling_index
[0];
631 att
->cb
.cb_color_attrib
&= C_028C74_TILE_MODE_INDEX
;
632 att
->cb
.cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
633 att
->cb
.micro_tile_mode
= micro_tile_mode
;
638 radv_set_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
639 struct radv_image
*image
,
640 VkClearDepthStencilValue ds_clear_value
,
641 VkImageAspectFlags aspects
)
643 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(image
->bo
);
644 va
+= image
->offset
+ image
->clear_value_offset
;
645 unsigned reg_offset
= 0, reg_count
= 0;
647 if (!image
->htile
.size
|| !aspects
)
650 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
656 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
659 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
661 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 2 + reg_count
, 0));
662 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
663 S_370_WR_CONFIRM(1) |
664 S_370_ENGINE_SEL(V_370_PFP
));
665 radeon_emit(cmd_buffer
->cs
, va
);
666 radeon_emit(cmd_buffer
->cs
, va
>> 32);
667 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)
668 radeon_emit(cmd_buffer
->cs
, ds_clear_value
.stencil
);
669 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
670 radeon_emit(cmd_buffer
->cs
, fui(ds_clear_value
.depth
));
672 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028028_DB_STENCIL_CLEAR
+ 4 * reg_offset
, reg_count
);
673 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)
674 radeon_emit(cmd_buffer
->cs
, ds_clear_value
.stencil
); /* R_028028_DB_STENCIL_CLEAR */
675 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
676 radeon_emit(cmd_buffer
->cs
, fui(ds_clear_value
.depth
)); /* R_02802C_DB_DEPTH_CLEAR */
680 radv_load_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
681 struct radv_image
*image
)
683 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(image
->bo
);
684 va
+= image
->offset
+ image
->clear_value_offset
;
686 if (!image
->htile
.size
)
689 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
691 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
692 radeon_emit(cmd_buffer
->cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
693 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
694 COPY_DATA_COUNT_SEL
);
695 radeon_emit(cmd_buffer
->cs
, va
);
696 radeon_emit(cmd_buffer
->cs
, va
>> 32);
697 radeon_emit(cmd_buffer
->cs
, R_028028_DB_STENCIL_CLEAR
>> 2);
698 radeon_emit(cmd_buffer
->cs
, 0);
700 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
701 radeon_emit(cmd_buffer
->cs
, 0);
705 radv_set_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
706 struct radv_image
*image
,
708 uint32_t color_values
[2])
710 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(image
->bo
);
711 va
+= image
->offset
+ image
->clear_value_offset
;
713 if (!image
->cmask
.size
&& !image
->surface
.dcc_size
)
716 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
718 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
719 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
720 S_370_WR_CONFIRM(1) |
721 S_370_ENGINE_SEL(V_370_PFP
));
722 radeon_emit(cmd_buffer
->cs
, va
);
723 radeon_emit(cmd_buffer
->cs
, va
>> 32);
724 radeon_emit(cmd_buffer
->cs
, color_values
[0]);
725 radeon_emit(cmd_buffer
->cs
, color_values
[1]);
727 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C8C_CB_COLOR0_CLEAR_WORD0
+ idx
* 0x3c, 2);
728 radeon_emit(cmd_buffer
->cs
, color_values
[0]);
729 radeon_emit(cmd_buffer
->cs
, color_values
[1]);
733 radv_load_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
734 struct radv_image
*image
,
737 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(image
->bo
);
738 va
+= image
->offset
+ image
->clear_value_offset
;
740 if (!image
->cmask
.size
&& !image
->surface
.dcc_size
)
743 uint32_t reg
= R_028C8C_CB_COLOR0_CLEAR_WORD0
+ idx
* 0x3c;
744 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
746 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
747 radeon_emit(cmd_buffer
->cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
748 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
749 COPY_DATA_COUNT_SEL
);
750 radeon_emit(cmd_buffer
->cs
, va
);
751 radeon_emit(cmd_buffer
->cs
, va
>> 32);
752 radeon_emit(cmd_buffer
->cs
, reg
>> 2);
753 radeon_emit(cmd_buffer
->cs
, 0);
755 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
756 radeon_emit(cmd_buffer
->cs
, 0);
760 radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer
)
763 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
764 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
765 int dst_resolve_micro_tile_mode
= -1;
767 if (subpass
->has_resolve
) {
768 uint32_t a
= subpass
->resolve_attachments
[0].attachment
;
769 const struct radv_image
*image
= framebuffer
->attachments
[a
].attachment
->image
;
770 dst_resolve_micro_tile_mode
= image
->surface
.micro_tile_mode
;
772 for (i
= 0; i
< subpass
->color_count
; ++i
) {
773 int idx
= subpass
->color_attachments
[i
].attachment
;
774 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
776 if (dst_resolve_micro_tile_mode
!= -1) {
777 radv_set_optimal_micro_tile_mode(cmd_buffer
->device
,
778 att
, dst_resolve_micro_tile_mode
);
780 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, att
->attachment
->bo
, 8);
782 assert(att
->attachment
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
);
783 radv_emit_fb_color_state(cmd_buffer
, i
, &att
->cb
);
785 radv_load_color_clear_regs(cmd_buffer
, att
->attachment
->image
, i
);
788 for (i
= subpass
->color_count
; i
< 8; i
++)
789 radeon_set_context_reg(cmd_buffer
->cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
790 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
792 if(subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
793 int idx
= subpass
->depth_stencil_attachment
.attachment
;
794 VkImageLayout layout
= subpass
->depth_stencil_attachment
.layout
;
795 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
796 struct radv_image
*image
= att
->attachment
->image
;
797 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, att
->attachment
->bo
, 8);
799 radv_emit_fb_ds_state(cmd_buffer
, &att
->ds
, image
, layout
);
801 if (att
->ds
.offset_scale
!= cmd_buffer
->state
.offset_scale
) {
802 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
803 cmd_buffer
->state
.offset_scale
= att
->ds
.offset_scale
;
805 radv_load_depth_clear_regs(cmd_buffer
, image
);
807 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028040_DB_Z_INFO
, 2);
808 radeon_emit(cmd_buffer
->cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* R_028040_DB_Z_INFO */
809 radeon_emit(cmd_buffer
->cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* R_028044_DB_STENCIL_INFO */
811 radeon_set_context_reg(cmd_buffer
->cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
812 S_028208_BR_X(framebuffer
->width
) |
813 S_028208_BR_Y(framebuffer
->height
));
816 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
)
818 uint32_t db_count_control
;
820 if(!cmd_buffer
->state
.active_occlusion_queries
) {
821 if (cmd_buffer
->device
->instance
->physicalDevice
.rad_info
.chip_class
>= CIK
) {
822 db_count_control
= 0;
824 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
827 if (cmd_buffer
->device
->instance
->physicalDevice
.rad_info
.chip_class
>= CIK
) {
828 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
829 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
830 S_028004_ZPASS_ENABLE(1) |
831 S_028004_SLICE_EVEN_ENABLE(1) |
832 S_028004_SLICE_ODD_ENABLE(1);
834 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
835 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
839 radeon_set_context_reg(cmd_buffer
->cs
, R_028004_DB_COUNT_CONTROL
, db_count_control
);
843 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
)
845 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
847 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
) {
848 unsigned width
= cmd_buffer
->state
.dynamic
.line_width
* 8;
849 radeon_set_context_reg(cmd_buffer
->cs
, R_028A08_PA_SU_LINE_CNTL
,
850 S_028A08_WIDTH(CLAMP(width
, 0, 0xFFF)));
853 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
) {
854 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028414_CB_BLEND_RED
, 4);
855 radeon_emit_array(cmd_buffer
->cs
, (uint32_t*)d
->blend_constants
, 4);
858 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
|
859 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
|
860 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
)) {
861 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028430_DB_STENCILREFMASK
, 2);
862 radeon_emit(cmd_buffer
->cs
, S_028430_STENCILTESTVAL(d
->stencil_reference
.front
) |
863 S_028430_STENCILMASK(d
->stencil_compare_mask
.front
) |
864 S_028430_STENCILWRITEMASK(d
->stencil_write_mask
.front
) |
865 S_028430_STENCILOPVAL(1));
866 radeon_emit(cmd_buffer
->cs
, S_028434_STENCILTESTVAL_BF(d
->stencil_reference
.back
) |
867 S_028434_STENCILMASK_BF(d
->stencil_compare_mask
.back
) |
868 S_028434_STENCILWRITEMASK_BF(d
->stencil_write_mask
.back
) |
869 S_028434_STENCILOPVAL_BF(1));
872 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_PIPELINE
|
873 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
)) {
874 radeon_set_context_reg(cmd_buffer
->cs
, R_028020_DB_DEPTH_BOUNDS_MIN
, fui(d
->depth_bounds
.min
));
875 radeon_set_context_reg(cmd_buffer
->cs
, R_028024_DB_DEPTH_BOUNDS_MAX
, fui(d
->depth_bounds
.max
));
878 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_PIPELINE
|
879 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
)) {
880 struct radv_raster_state
*raster
= &cmd_buffer
->state
.pipeline
->graphics
.raster
;
881 unsigned slope
= fui(d
->depth_bias
.slope
* 16.0f
);
882 unsigned bias
= fui(d
->depth_bias
.bias
* cmd_buffer
->state
.offset_scale
);
884 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster
->pa_su_sc_mode_cntl
)) {
885 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, 5);
886 radeon_emit(cmd_buffer
->cs
, fui(d
->depth_bias
.clamp
)); /* CLAMP */
887 radeon_emit(cmd_buffer
->cs
, slope
); /* FRONT SCALE */
888 radeon_emit(cmd_buffer
->cs
, bias
); /* FRONT OFFSET */
889 radeon_emit(cmd_buffer
->cs
, slope
); /* BACK SCALE */
890 radeon_emit(cmd_buffer
->cs
, bias
); /* BACK OFFSET */
894 cmd_buffer
->state
.dirty
= 0;
898 radv_flush_constants(struct radv_cmd_buffer
*cmd_buffer
,
899 struct radv_pipeline_layout
*layout
,
900 VkShaderStageFlags stages
) {
905 stages
&= cmd_buffer
->push_constant_stages
;
906 if (!stages
|| !layout
|| (!layout
->push_constant_size
&& !layout
->dynamic_offset_count
))
909 radv_cmd_buffer_upload_alloc(cmd_buffer
, layout
->push_constant_size
+
910 16 * layout
->dynamic_offset_count
,
913 memcpy(ptr
, cmd_buffer
->push_constants
, layout
->push_constant_size
);
914 memcpy((char*)ptr
+ layout
->push_constant_size
, cmd_buffer
->dynamic_buffers
,
915 16 * layout
->dynamic_offset_count
);
917 va
= cmd_buffer
->device
->ws
->buffer_get_va(cmd_buffer
->upload
.upload_bo
);
920 if (stages
& VK_SHADER_STAGE_VERTEX_BIT
) {
921 radeon_set_sh_reg_seq(cmd_buffer
->cs
,
922 R_00B130_SPI_SHADER_USER_DATA_VS_0
+ 8 * 4, 2);
923 radeon_emit(cmd_buffer
->cs
, va
);
924 radeon_emit(cmd_buffer
->cs
, va
>> 32);
927 if (stages
& VK_SHADER_STAGE_FRAGMENT_BIT
) {
928 radeon_set_sh_reg_seq(cmd_buffer
->cs
,
929 R_00B030_SPI_SHADER_USER_DATA_PS_0
+ 8 * 4, 2);
930 radeon_emit(cmd_buffer
->cs
, va
);
931 radeon_emit(cmd_buffer
->cs
, va
>> 32);
934 if (stages
& VK_SHADER_STAGE_COMPUTE_BIT
) {
935 radeon_set_sh_reg_seq(cmd_buffer
->cs
,
936 R_00B900_COMPUTE_USER_DATA_0
+ 8 * 4, 2);
937 radeon_emit(cmd_buffer
->cs
, va
);
938 radeon_emit(cmd_buffer
->cs
, va
>> 32);
941 cmd_buffer
->push_constant_stages
&= ~stages
;
945 radv_cmd_buffer_flush_state(struct radv_cmd_buffer
*cmd_buffer
)
947 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
948 struct radv_device
*device
= cmd_buffer
->device
;
949 uint32_t ia_multi_vgt_param
;
950 uint32_t ls_hs_config
= 0;
952 unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
955 if ((cmd_buffer
->state
.vertex_descriptors_dirty
|| cmd_buffer
->state
.vb_dirty
) &&
956 cmd_buffer
->state
.pipeline
->num_vertex_attribs
) {
960 uint32_t num_attribs
= cmd_buffer
->state
.pipeline
->num_vertex_attribs
;
963 /* allocate some descriptor state for vertex buffers */
964 radv_cmd_buffer_upload_alloc(cmd_buffer
, num_attribs
* 16, 256,
965 &vb_offset
, &vb_ptr
);
967 for (i
= 0; i
< num_attribs
; i
++) {
968 uint32_t *desc
= &((uint32_t *)vb_ptr
)[i
* 4];
970 int vb
= cmd_buffer
->state
.pipeline
->va_binding
[i
];
971 struct radv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
972 uint32_t stride
= cmd_buffer
->state
.pipeline
->binding_stride
[vb
];
974 device
->ws
->cs_add_buffer(cmd_buffer
->cs
, buffer
->bo
, 8);
975 va
= device
->ws
->buffer_get_va(buffer
->bo
);
977 offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
+ cmd_buffer
->state
.pipeline
->va_offset
[i
];
978 va
+= offset
+ buffer
->offset
;
980 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(stride
);
981 if (cmd_buffer
->device
->instance
->physicalDevice
.rad_info
.chip_class
<= CIK
&& stride
)
982 desc
[2] = (buffer
->size
- offset
- cmd_buffer
->state
.pipeline
->va_format_size
[i
]) / stride
+ 1;
984 desc
[2] = buffer
->size
- offset
;
985 desc
[3] = cmd_buffer
->state
.pipeline
->va_rsrc_word3
[i
];
988 va
= device
->ws
->buffer_get_va(cmd_buffer
->upload
.upload_bo
);
990 radeon_set_sh_reg_seq(cmd_buffer
->cs
,
991 R_00B130_SPI_SHADER_USER_DATA_VS_0
+ 10 * 4, 2);
992 radeon_emit(cmd_buffer
->cs
, va
);
993 radeon_emit(cmd_buffer
->cs
, va
>> 32);
997 cmd_buffer
->state
.vertex_descriptors_dirty
= false;
998 cmd_buffer
->state
.vb_dirty
= 0;
999 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
)
1000 radv_emit_graphics_pipeline(cmd_buffer
, pipeline
);
1002 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_RENDER_TARGETS
)
1003 radv_emit_framebuffer_state(cmd_buffer
);
1005 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
1006 radv_emit_viewport(cmd_buffer
);
1008 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_DYNAMIC_SCISSOR
))
1009 radv_emit_scissor(cmd_buffer
);
1011 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
) {
1012 radeon_set_context_reg(cmd_buffer
->cs
, R_028B54_VGT_SHADER_STAGES_EN
, 0);
1013 ia_multi_vgt_param
= si_get_ia_multi_vgt_param(cmd_buffer
);
1015 if (cmd_buffer
->device
->instance
->physicalDevice
.rad_info
.chip_class
>= CIK
) {
1016 radeon_set_context_reg_idx(cmd_buffer
->cs
, R_028AA8_IA_MULTI_VGT_PARAM
, 1, ia_multi_vgt_param
);
1017 radeon_set_context_reg_idx(cmd_buffer
->cs
, R_028B58_VGT_LS_HS_CONFIG
, 2, ls_hs_config
);
1018 radeon_set_uconfig_reg_idx(cmd_buffer
->cs
, R_030908_VGT_PRIMITIVE_TYPE
, 1, cmd_buffer
->state
.pipeline
->graphics
.prim
);
1020 radeon_set_config_reg(cmd_buffer
->cs
, R_008958_VGT_PRIMITIVE_TYPE
, cmd_buffer
->state
.pipeline
->graphics
.prim
);
1021 radeon_set_context_reg(cmd_buffer
->cs
, R_028AA8_IA_MULTI_VGT_PARAM
, ia_multi_vgt_param
);
1022 radeon_set_context_reg(cmd_buffer
->cs
, R_028B58_VGT_LS_HS_CONFIG
, ls_hs_config
);
1024 radeon_set_context_reg(cmd_buffer
->cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, cmd_buffer
->state
.pipeline
->graphics
.gs_out
);
1027 radv_cmd_buffer_flush_dynamic_state(cmd_buffer
);
1029 radv_flush_constants(cmd_buffer
, cmd_buffer
->state
.pipeline
->layout
,
1030 VK_SHADER_STAGE_ALL_GRAPHICS
);
1032 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1034 si_emit_cache_flush(cmd_buffer
);
1037 static void radv_stage_flush(struct radv_cmd_buffer
*cmd_buffer
,
1038 VkPipelineStageFlags src_stage_mask
)
1040 if (src_stage_mask
& (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT
|
1041 VK_PIPELINE_STAGE_TRANSFER_BIT
|
1042 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
1043 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
1044 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
;
1047 if (src_stage_mask
& (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT
|
1048 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT
|
1049 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT
|
1050 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT
|
1051 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT
|
1052 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT
|
1053 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
|
1054 VK_PIPELINE_STAGE_TRANSFER_BIT
|
1055 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
1056 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT
|
1057 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
1058 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
1059 } else if (src_stage_mask
& (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
|
1060 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
1061 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
|
1062 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT
)) {
1063 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VS_PARTIAL_FLUSH
;
1067 static void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
, const struct radv_subpass_barrier
*barrier
)
1069 radv_stage_flush(cmd_buffer
, barrier
->src_stage_mask
);
1071 /* TODO: actual cache flushes */
1074 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
1075 VkAttachmentReference att
)
1077 unsigned idx
= att
.attachment
;
1078 struct radv_image_view
*view
= cmd_buffer
->state
.framebuffer
->attachments
[idx
].attachment
;
1079 VkImageSubresourceRange range
;
1080 range
.aspectMask
= 0;
1081 range
.baseMipLevel
= view
->base_mip
;
1082 range
.levelCount
= 1;
1083 range
.baseArrayLayer
= view
->base_layer
;
1084 range
.layerCount
= cmd_buffer
->state
.framebuffer
->layers
;
1086 radv_handle_image_transition(cmd_buffer
,
1088 cmd_buffer
->state
.attachments
[idx
].current_layout
,
1090 cmd_buffer
->state
.attachments
[idx
].pending_clear_aspects
);
1092 cmd_buffer
->state
.attachments
[idx
].current_layout
= att
.layout
;
1098 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
1099 const struct radv_subpass
*subpass
, bool transitions
)
1102 radv_subpass_barrier(cmd_buffer
, &subpass
->start_barrier
);
1104 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1105 radv_handle_subpass_image_transition(cmd_buffer
,
1106 subpass
->color_attachments
[i
]);
1109 for (unsigned i
= 0; i
< subpass
->input_count
; ++i
) {
1110 radv_handle_subpass_image_transition(cmd_buffer
,
1111 subpass
->input_attachments
[i
]);
1114 if (subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1115 radv_handle_subpass_image_transition(cmd_buffer
,
1116 subpass
->depth_stencil_attachment
);
1120 cmd_buffer
->state
.subpass
= subpass
;
1122 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_RENDER_TARGETS
;
1126 radv_cmd_state_setup_attachments(struct radv_cmd_buffer
*cmd_buffer
,
1127 struct radv_render_pass
*pass
,
1128 const VkRenderPassBeginInfo
*info
)
1130 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
1132 if (pass
->attachment_count
== 0) {
1133 state
->attachments
= NULL
;
1137 state
->attachments
= radv_alloc(&cmd_buffer
->pool
->alloc
,
1138 pass
->attachment_count
*
1139 sizeof(state
->attachments
[0]),
1140 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1141 if (state
->attachments
== NULL
) {
1142 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1146 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1147 struct radv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1148 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1149 VkImageAspectFlags clear_aspects
= 0;
1151 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
1152 /* color attachment */
1153 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1154 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1157 /* depthstencil attachment */
1158 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
1159 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1160 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1162 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
1163 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1164 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1168 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1169 if (clear_aspects
&& info
) {
1170 assert(info
->clearValueCount
> i
);
1171 state
->attachments
[i
].clear_value
= info
->pClearValues
[i
];
1174 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1178 VkResult
radv_AllocateCommandBuffers(
1180 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
1181 VkCommandBuffer
*pCommandBuffers
)
1183 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1184 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
1186 VkResult result
= VK_SUCCESS
;
1189 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
1190 result
= radv_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
1191 &pCommandBuffers
[i
]);
1192 if (result
!= VK_SUCCESS
)
1196 if (result
!= VK_SUCCESS
)
1197 radv_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
,
1198 i
, pCommandBuffers
);
1204 radv_cmd_buffer_destroy(struct radv_cmd_buffer
*cmd_buffer
)
1206 list_del(&cmd_buffer
->pool_link
);
1208 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
1209 &cmd_buffer
->upload
.list
, list
) {
1210 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
1211 list_del(&up
->list
);
1215 if (cmd_buffer
->upload
.upload_bo
)
1216 cmd_buffer
->device
->ws
->buffer_destroy(cmd_buffer
->upload
.upload_bo
);
1217 cmd_buffer
->device
->ws
->cs_destroy(cmd_buffer
->cs
);
1218 radv_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
1221 void radv_FreeCommandBuffers(
1223 VkCommandPool commandPool
,
1224 uint32_t commandBufferCount
,
1225 const VkCommandBuffer
*pCommandBuffers
)
1227 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1228 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
1231 radv_cmd_buffer_destroy(cmd_buffer
);
1235 static void radv_reset_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
)
1238 cmd_buffer
->device
->ws
->cs_reset(cmd_buffer
->cs
);
1240 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
1241 &cmd_buffer
->upload
.list
, list
) {
1242 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
1243 list_del(&up
->list
);
1247 if (cmd_buffer
->upload
.upload_bo
)
1248 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
,
1249 cmd_buffer
->upload
.upload_bo
, 8);
1250 cmd_buffer
->upload
.offset
= 0;
1252 cmd_buffer
->record_fail
= false;
1255 VkResult
radv_ResetCommandBuffer(
1256 VkCommandBuffer commandBuffer
,
1257 VkCommandBufferResetFlags flags
)
1259 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1260 radv_reset_cmd_buffer(cmd_buffer
);
1264 VkResult
radv_BeginCommandBuffer(
1265 VkCommandBuffer commandBuffer
,
1266 const VkCommandBufferBeginInfo
*pBeginInfo
)
1268 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1269 radv_reset_cmd_buffer(cmd_buffer
);
1271 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
1273 /* setup initial configuration into command buffer */
1274 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
) {
1275 /* Flush read caches at the beginning of CS not flushed by the kernel. */
1276 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_INV_ICACHE
|
1277 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
1278 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
1279 RADV_CMD_FLAG_INV_VMEM_L1
|
1280 RADV_CMD_FLAG_INV_SMEM_L1
|
1281 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
|
1282 RADV_CMD_FLAG_INV_GLOBAL_L2
;
1283 si_init_config(&cmd_buffer
->device
->instance
->physicalDevice
, cmd_buffer
);
1284 radv_set_db_count_control(cmd_buffer
);
1285 si_emit_cache_flush(cmd_buffer
);
1288 if (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1289 cmd_buffer
->state
.framebuffer
= radv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
1290 cmd_buffer
->state
.pass
= radv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1292 struct radv_subpass
*subpass
=
1293 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1295 radv_cmd_state_setup_attachments(cmd_buffer
, cmd_buffer
->state
.pass
, NULL
);
1296 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
, false);
1302 void radv_CmdBindVertexBuffers(
1303 VkCommandBuffer commandBuffer
,
1304 uint32_t firstBinding
,
1305 uint32_t bindingCount
,
1306 const VkBuffer
* pBuffers
,
1307 const VkDeviceSize
* pOffsets
)
1309 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1310 struct radv_vertex_binding
*vb
= cmd_buffer
->state
.vertex_bindings
;
1312 /* We have to defer setting up vertex buffer since we need the buffer
1313 * stride from the pipeline. */
1315 assert(firstBinding
+ bindingCount
< MAX_VBS
);
1316 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
1317 vb
[firstBinding
+ i
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
1318 vb
[firstBinding
+ i
].offset
= pOffsets
[i
];
1319 cmd_buffer
->state
.vb_dirty
|= 1 << (firstBinding
+ i
);
1323 void radv_CmdBindIndexBuffer(
1324 VkCommandBuffer commandBuffer
,
1326 VkDeviceSize offset
,
1327 VkIndexType indexType
)
1329 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1331 cmd_buffer
->state
.index_buffer
= radv_buffer_from_handle(buffer
);
1332 cmd_buffer
->state
.index_offset
= offset
;
1333 cmd_buffer
->state
.index_type
= indexType
; /* vk matches hw */
1334 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
1335 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, cmd_buffer
->state
.index_buffer
->bo
, 8);
1339 void radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
1340 struct radv_descriptor_set
*set
,
1343 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
1345 cmd_buffer
->state
.descriptors
[idx
] = set
;
1350 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
)
1351 if (set
->descriptors
[j
])
1352 ws
->cs_add_buffer(cmd_buffer
->cs
, set
->descriptors
[j
], 7);
1354 radeon_set_sh_reg_seq(cmd_buffer
->cs
,
1355 R_00B030_SPI_SHADER_USER_DATA_PS_0
+ 8 * idx
, 2);
1356 radeon_emit(cmd_buffer
->cs
, set
->va
);
1357 radeon_emit(cmd_buffer
->cs
, set
->va
>> 32);
1359 radeon_set_sh_reg_seq(cmd_buffer
->cs
,
1360 R_00B130_SPI_SHADER_USER_DATA_VS_0
+ 8 * idx
, 2);
1361 radeon_emit(cmd_buffer
->cs
, set
->va
);
1362 radeon_emit(cmd_buffer
->cs
, set
->va
>> 32);
1364 radeon_set_sh_reg_seq(cmd_buffer
->cs
,
1365 R_00B900_COMPUTE_USER_DATA_0
+ 8 * idx
, 2);
1366 radeon_emit(cmd_buffer
->cs
, set
->va
);
1367 radeon_emit(cmd_buffer
->cs
, set
->va
>> 32);
1370 ws
->cs_add_buffer(cmd_buffer
->cs
, set
->bo
, 8);
1373 void radv_CmdBindDescriptorSets(
1374 VkCommandBuffer commandBuffer
,
1375 VkPipelineBindPoint pipelineBindPoint
,
1376 VkPipelineLayout _layout
,
1378 uint32_t descriptorSetCount
,
1379 const VkDescriptorSet
* pDescriptorSets
,
1380 uint32_t dynamicOffsetCount
,
1381 const uint32_t* pDynamicOffsets
)
1383 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1384 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
1385 unsigned dyn_idx
= 0;
1387 unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
1390 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
1391 unsigned idx
= i
+ firstSet
;
1392 RADV_FROM_HANDLE(radv_descriptor_set
, set
, pDescriptorSets
[i
]);
1393 radv_bind_descriptor_set(cmd_buffer
, set
, idx
);
1395 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
1396 unsigned idx
= j
+ layout
->set
[i
].dynamic_offset_start
;
1397 uint32_t *dst
= cmd_buffer
->dynamic_buffers
+ idx
* 4;
1398 assert(dyn_idx
< dynamicOffsetCount
);
1400 struct radv_descriptor_range
*range
= set
->dynamic_descriptors
+ j
;
1401 uint64_t va
= range
->va
+ pDynamicOffsets
[dyn_idx
];
1403 dst
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
1404 dst
[2] = range
->size
;
1405 dst
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1406 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1407 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1408 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1409 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1410 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1411 cmd_buffer
->push_constant_stages
|=
1412 set
->layout
->dynamic_shader_stages
;
1416 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1419 void radv_CmdPushConstants(VkCommandBuffer commandBuffer
,
1420 VkPipelineLayout layout
,
1421 VkShaderStageFlags stageFlags
,
1424 const void* pValues
)
1426 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1427 memcpy(cmd_buffer
->push_constants
+ offset
, pValues
, size
);
1428 cmd_buffer
->push_constant_stages
|= stageFlags
;
1431 VkResult
radv_EndCommandBuffer(
1432 VkCommandBuffer commandBuffer
)
1434 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1436 si_emit_cache_flush(cmd_buffer
);
1437 if (!cmd_buffer
->device
->ws
->cs_finalize(cmd_buffer
->cs
) ||
1438 cmd_buffer
->record_fail
)
1439 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1444 radv_emit_compute_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
1446 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
1447 struct radv_shader_variant
*compute_shader
;
1448 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1451 if (!pipeline
|| pipeline
== cmd_buffer
->state
.emitted_compute_pipeline
)
1454 cmd_buffer
->state
.emitted_compute_pipeline
= pipeline
;
1456 compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
1457 va
= ws
->buffer_get_va(compute_shader
->bo
);
1459 ws
->cs_add_buffer(cmd_buffer
->cs
, compute_shader
->bo
, 8);
1461 unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 16);
1463 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B830_COMPUTE_PGM_LO
, 2);
1464 radeon_emit(cmd_buffer
->cs
, va
>> 8);
1465 radeon_emit(cmd_buffer
->cs
, va
>> 40);
1467 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
1468 radeon_emit(cmd_buffer
->cs
, compute_shader
->rsrc1
);
1469 radeon_emit(cmd_buffer
->cs
, compute_shader
->rsrc2
);
1471 /* change these once we have scratch support */
1472 radeon_set_sh_reg(cmd_buffer
->cs
, R_00B860_COMPUTE_TMPRING_SIZE
,
1473 S_00B860_WAVES(32) | S_00B860_WAVESIZE(0));
1475 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
1476 radeon_emit(cmd_buffer
->cs
,
1477 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[0]));
1478 radeon_emit(cmd_buffer
->cs
,
1479 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[1]));
1480 radeon_emit(cmd_buffer
->cs
,
1481 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[2]));
1483 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1487 void radv_CmdBindPipeline(
1488 VkCommandBuffer commandBuffer
,
1489 VkPipelineBindPoint pipelineBindPoint
,
1490 VkPipeline _pipeline
)
1492 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1493 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
1495 switch (pipelineBindPoint
) {
1496 case VK_PIPELINE_BIND_POINT_COMPUTE
:
1497 cmd_buffer
->state
.compute_pipeline
= pipeline
;
1498 cmd_buffer
->push_constant_stages
|= VK_SHADER_STAGE_COMPUTE_BIT
;
1500 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
1501 cmd_buffer
->state
.pipeline
= pipeline
;
1502 cmd_buffer
->state
.vertex_descriptors_dirty
= true;
1503 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
;
1504 cmd_buffer
->push_constant_stages
|= pipeline
->active_stages
;
1506 /* Apply the dynamic state from the pipeline */
1507 cmd_buffer
->state
.dirty
|= pipeline
->dynamic_state_mask
;
1508 radv_dynamic_state_copy(&cmd_buffer
->state
.dynamic
,
1509 &pipeline
->dynamic_state
,
1510 pipeline
->dynamic_state_mask
);
1513 assert(!"invalid bind point");
1518 void radv_CmdSetViewport(
1519 VkCommandBuffer commandBuffer
,
1520 uint32_t firstViewport
,
1521 uint32_t viewportCount
,
1522 const VkViewport
* pViewports
)
1524 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1526 const uint32_t total_count
= firstViewport
+ viewportCount
;
1527 if (cmd_buffer
->state
.dynamic
.viewport
.count
< total_count
)
1528 cmd_buffer
->state
.dynamic
.viewport
.count
= total_count
;
1530 memcpy(cmd_buffer
->state
.dynamic
.viewport
.viewports
+ firstViewport
,
1531 pViewports
, viewportCount
* sizeof(*pViewports
));
1533 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
1536 void radv_CmdSetScissor(
1537 VkCommandBuffer commandBuffer
,
1538 uint32_t firstScissor
,
1539 uint32_t scissorCount
,
1540 const VkRect2D
* pScissors
)
1542 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1544 const uint32_t total_count
= firstScissor
+ scissorCount
;
1545 if (cmd_buffer
->state
.dynamic
.scissor
.count
< total_count
)
1546 cmd_buffer
->state
.dynamic
.scissor
.count
= total_count
;
1548 memcpy(cmd_buffer
->state
.dynamic
.scissor
.scissors
+ firstScissor
,
1549 pScissors
, scissorCount
* sizeof(*pScissors
));
1550 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
1553 void radv_CmdSetLineWidth(
1554 VkCommandBuffer commandBuffer
,
1557 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1558 cmd_buffer
->state
.dynamic
.line_width
= lineWidth
;
1559 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
1562 void radv_CmdSetDepthBias(
1563 VkCommandBuffer commandBuffer
,
1564 float depthBiasConstantFactor
,
1565 float depthBiasClamp
,
1566 float depthBiasSlopeFactor
)
1568 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1570 cmd_buffer
->state
.dynamic
.depth_bias
.bias
= depthBiasConstantFactor
;
1571 cmd_buffer
->state
.dynamic
.depth_bias
.clamp
= depthBiasClamp
;
1572 cmd_buffer
->state
.dynamic
.depth_bias
.slope
= depthBiasSlopeFactor
;
1574 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
1577 void radv_CmdSetBlendConstants(
1578 VkCommandBuffer commandBuffer
,
1579 const float blendConstants
[4])
1581 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1583 memcpy(cmd_buffer
->state
.dynamic
.blend_constants
,
1584 blendConstants
, sizeof(float) * 4);
1586 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
1589 void radv_CmdSetDepthBounds(
1590 VkCommandBuffer commandBuffer
,
1591 float minDepthBounds
,
1592 float maxDepthBounds
)
1594 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1596 cmd_buffer
->state
.dynamic
.depth_bounds
.min
= minDepthBounds
;
1597 cmd_buffer
->state
.dynamic
.depth_bounds
.max
= maxDepthBounds
;
1599 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
1602 void radv_CmdSetStencilCompareMask(
1603 VkCommandBuffer commandBuffer
,
1604 VkStencilFaceFlags faceMask
,
1605 uint32_t compareMask
)
1607 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1609 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
1610 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.front
= compareMask
;
1611 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
1612 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.back
= compareMask
;
1614 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
1617 void radv_CmdSetStencilWriteMask(
1618 VkCommandBuffer commandBuffer
,
1619 VkStencilFaceFlags faceMask
,
1622 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1624 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
1625 cmd_buffer
->state
.dynamic
.stencil_write_mask
.front
= writeMask
;
1626 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
1627 cmd_buffer
->state
.dynamic
.stencil_write_mask
.back
= writeMask
;
1629 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
1632 void radv_CmdSetStencilReference(
1633 VkCommandBuffer commandBuffer
,
1634 VkStencilFaceFlags faceMask
,
1637 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1639 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
1640 cmd_buffer
->state
.dynamic
.stencil_reference
.front
= reference
;
1641 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
1642 cmd_buffer
->state
.dynamic
.stencil_reference
.back
= reference
;
1644 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
1648 void radv_CmdExecuteCommands(
1649 VkCommandBuffer commandBuffer
,
1650 uint32_t commandBufferCount
,
1651 const VkCommandBuffer
* pCmdBuffers
)
1653 RADV_FROM_HANDLE(radv_cmd_buffer
, primary
, commandBuffer
);
1655 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1656 RADV_FROM_HANDLE(radv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1658 primary
->device
->ws
->cs_execute_secondary(primary
->cs
, secondary
->cs
);
1661 /* if we execute secondary we need to re-emit out pipelines */
1662 if (commandBufferCount
) {
1663 primary
->state
.emitted_pipeline
= NULL
;
1664 primary
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
;
1665 primary
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_ALL
;
1669 VkResult
radv_CreateCommandPool(
1671 const VkCommandPoolCreateInfo
* pCreateInfo
,
1672 const VkAllocationCallbacks
* pAllocator
,
1673 VkCommandPool
* pCmdPool
)
1675 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1676 struct radv_cmd_pool
*pool
;
1678 pool
= radv_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
1679 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1681 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1684 pool
->alloc
= *pAllocator
;
1686 pool
->alloc
= device
->alloc
;
1688 list_inithead(&pool
->cmd_buffers
);
1690 *pCmdPool
= radv_cmd_pool_to_handle(pool
);
1696 void radv_DestroyCommandPool(
1698 VkCommandPool commandPool
,
1699 const VkAllocationCallbacks
* pAllocator
)
1701 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1702 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
1707 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
1708 &pool
->cmd_buffers
, pool_link
) {
1709 radv_cmd_buffer_destroy(cmd_buffer
);
1712 radv_free2(&device
->alloc
, pAllocator
, pool
);
1715 VkResult
radv_ResetCommandPool(
1717 VkCommandPool commandPool
,
1718 VkCommandPoolResetFlags flags
)
1720 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
1722 list_for_each_entry(struct radv_cmd_buffer
, cmd_buffer
,
1723 &pool
->cmd_buffers
, pool_link
) {
1724 radv_reset_cmd_buffer(cmd_buffer
);
1730 void radv_CmdBeginRenderPass(
1731 VkCommandBuffer commandBuffer
,
1732 const VkRenderPassBeginInfo
* pRenderPassBegin
,
1733 VkSubpassContents contents
)
1735 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1736 RADV_FROM_HANDLE(radv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
1737 RADV_FROM_HANDLE(radv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
1739 unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
1742 cmd_buffer
->state
.framebuffer
= framebuffer
;
1743 cmd_buffer
->state
.pass
= pass
;
1744 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
1745 radv_cmd_state_setup_attachments(cmd_buffer
, pass
, pRenderPassBegin
);
1747 si_emit_cache_flush(cmd_buffer
);
1749 radv_cmd_buffer_set_subpass(cmd_buffer
, pass
->subpasses
, true);
1750 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1752 radv_cmd_buffer_clear_subpass(cmd_buffer
);
1755 void radv_CmdNextSubpass(
1756 VkCommandBuffer commandBuffer
,
1757 VkSubpassContents contents
)
1759 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1761 si_emit_cache_flush(cmd_buffer
);
1762 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
1764 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
1767 radv_cmd_buffer_set_subpass(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1, true);
1768 radv_cmd_buffer_clear_subpass(cmd_buffer
);
1772 VkCommandBuffer commandBuffer
,
1773 uint32_t vertexCount
,
1774 uint32_t instanceCount
,
1775 uint32_t firstVertex
,
1776 uint32_t firstInstance
)
1778 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1779 radv_cmd_buffer_flush_state(cmd_buffer
);
1781 unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 9);
1783 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B130_SPI_SHADER_USER_DATA_VS_0
+ 12 * 4, 2);
1784 radeon_emit(cmd_buffer
->cs
, firstVertex
);
1785 radeon_emit(cmd_buffer
->cs
, firstInstance
);
1786 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_NUM_INSTANCES
, 0, 0));
1787 radeon_emit(cmd_buffer
->cs
, instanceCount
);
1789 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, 0));
1790 radeon_emit(cmd_buffer
->cs
, vertexCount
);
1791 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
1792 S_0287F0_USE_OPAQUE(0));
1794 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1797 static void radv_emit_primitive_reset_index(struct radv_cmd_buffer
*cmd_buffer
)
1799 uint32_t primitive_reset_index
= cmd_buffer
->state
.last_primitive_reset_index
? 0xffffffffu
: 0xffffu
;
1801 if (cmd_buffer
->state
.pipeline
->graphics
.prim_restart_enable
&&
1802 primitive_reset_index
!= cmd_buffer
->state
.last_primitive_reset_index
) {
1803 cmd_buffer
->state
.last_primitive_reset_index
= primitive_reset_index
;
1804 radeon_set_context_reg(cmd_buffer
->cs
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
1805 primitive_reset_index
);
1809 void radv_CmdDrawIndexed(
1810 VkCommandBuffer commandBuffer
,
1811 uint32_t indexCount
,
1812 uint32_t instanceCount
,
1813 uint32_t firstIndex
,
1814 int32_t vertexOffset
,
1815 uint32_t firstInstance
)
1817 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1818 int index_size
= cmd_buffer
->state
.index_type
? 4 : 2;
1819 uint32_t index_max_size
= (cmd_buffer
->state
.index_buffer
->size
- cmd_buffer
->state
.index_offset
) / index_size
;
1822 radv_cmd_buffer_flush_state(cmd_buffer
);
1823 radv_emit_primitive_reset_index(cmd_buffer
);
1825 unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 14);
1827 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
1828 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.index_type
);
1830 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B130_SPI_SHADER_USER_DATA_VS_0
+ 12 * 4, 2);
1831 radeon_emit(cmd_buffer
->cs
, vertexOffset
);
1832 radeon_emit(cmd_buffer
->cs
, firstInstance
);
1833 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_NUM_INSTANCES
, 0, 0));
1834 radeon_emit(cmd_buffer
->cs
, instanceCount
);
1836 index_va
= cmd_buffer
->device
->ws
->buffer_get_va(cmd_buffer
->state
.index_buffer
->bo
);
1837 index_va
+= firstIndex
* index_size
+ cmd_buffer
->state
.index_buffer
->offset
+ cmd_buffer
->state
.index_offset
;
1838 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, false));
1839 radeon_emit(cmd_buffer
->cs
, index_max_size
);
1840 radeon_emit(cmd_buffer
->cs
, index_va
);
1841 radeon_emit(cmd_buffer
->cs
, (index_va
>> 32UL) & 0xFF);
1842 radeon_emit(cmd_buffer
->cs
, indexCount
);
1843 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_DMA
);
1845 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1849 radv_emit_indirect_draw(struct radv_cmd_buffer
*cmd_buffer
,
1851 VkDeviceSize offset
,
1852 uint32_t draw_count
,
1856 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
1857 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
1858 unsigned di_src_sel
= indexed
? V_0287F0_DI_SRC_SEL_DMA
1859 : V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
1860 uint64_t indirect_va
= cmd_buffer
->device
->ws
->buffer_get_va(buffer
->bo
);
1861 indirect_va
+= offset
+ buffer
->offset
;
1866 cmd_buffer
->device
->ws
->cs_add_buffer(cs
, buffer
->bo
, 8);
1868 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
1870 radeon_emit(cs
, indirect_va
);
1871 radeon_emit(cs
, indirect_va
>> 32);
1873 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT_MULTI
:
1874 PKT3_DRAW_INDIRECT_MULTI
,
1877 radeon_emit(cs
, (R_00B160_SPI_SHADER_USER_DATA_VS_12
- SI_SH_REG_OFFSET
) >> 2);
1878 radeon_emit(cs
, (R_00B164_SPI_SHADER_USER_DATA_VS_13
- SI_SH_REG_OFFSET
) >> 2);
1879 radeon_emit(cs
, 0); /* draw_index */
1880 radeon_emit(cs
, draw_count
); /* count */
1881 radeon_emit(cs
, 0); /* count_addr -- disabled */
1883 radeon_emit(cs
, stride
); /* stride */
1884 radeon_emit(cs
, di_src_sel
);
1887 void radv_CmdDrawIndirect(
1888 VkCommandBuffer commandBuffer
,
1890 VkDeviceSize offset
,
1894 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1895 radv_cmd_buffer_flush_state(cmd_buffer
);
1897 unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 14);
1899 radv_emit_indirect_draw(cmd_buffer
, _buffer
, offset
, drawCount
, stride
, false);
1901 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1904 void radv_CmdDrawIndexedIndirect(
1905 VkCommandBuffer commandBuffer
,
1907 VkDeviceSize offset
,
1911 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1912 int index_size
= cmd_buffer
->state
.index_type
? 4 : 2;
1913 uint32_t index_max_size
= (cmd_buffer
->state
.index_buffer
->size
- cmd_buffer
->state
.index_offset
) / index_size
;
1915 radv_cmd_buffer_flush_state(cmd_buffer
);
1916 radv_emit_primitive_reset_index(cmd_buffer
);
1918 index_va
= cmd_buffer
->device
->ws
->buffer_get_va(cmd_buffer
->state
.index_buffer
->bo
);
1919 index_va
+= cmd_buffer
->state
.index_buffer
->offset
+ cmd_buffer
->state
.index_offset
;
1921 unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 21);
1923 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
1924 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.index_type
);
1926 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
1927 radeon_emit(cmd_buffer
->cs
, index_va
);
1928 radeon_emit(cmd_buffer
->cs
, index_va
>> 32);
1930 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
1931 radeon_emit(cmd_buffer
->cs
, index_max_size
);
1933 radv_emit_indirect_draw(cmd_buffer
, _buffer
, offset
, drawCount
, stride
, true);
1935 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1938 void radv_CmdDispatch(
1939 VkCommandBuffer commandBuffer
,
1944 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1946 radv_emit_compute_pipeline(cmd_buffer
);
1947 radv_flush_constants(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
->layout
,
1948 VK_SHADER_STAGE_COMPUTE_BIT
);
1949 si_emit_cache_flush(cmd_buffer
);
1950 unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 10);
1952 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B900_COMPUTE_USER_DATA_0
+ 10 * 4, 3);
1953 radeon_emit(cmd_buffer
->cs
, x
);
1954 radeon_emit(cmd_buffer
->cs
, y
);
1955 radeon_emit(cmd_buffer
->cs
, z
);
1957 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, 0) |
1958 PKT3_SHADER_TYPE_S(1));
1959 radeon_emit(cmd_buffer
->cs
, x
);
1960 radeon_emit(cmd_buffer
->cs
, y
);
1961 radeon_emit(cmd_buffer
->cs
, z
);
1962 radeon_emit(cmd_buffer
->cs
, 1);
1964 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1967 void radv_CmdDispatchIndirect(
1968 VkCommandBuffer commandBuffer
,
1970 VkDeviceSize offset
)
1972 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1973 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
1974 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(buffer
->bo
);
1975 va
+= buffer
->offset
+ offset
;
1977 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, buffer
->bo
, 8);
1979 radv_emit_compute_pipeline(cmd_buffer
);
1980 radv_flush_constants(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
->layout
,
1981 VK_SHADER_STAGE_COMPUTE_BIT
);
1982 si_emit_cache_flush(cmd_buffer
);
1984 unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 25);
1986 for (unsigned i
= 0; i
< 3; ++i
) {
1987 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
1988 radeon_emit(cmd_buffer
->cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
1989 COPY_DATA_DST_SEL(COPY_DATA_REG
));
1990 radeon_emit(cmd_buffer
->cs
, (va
+ 4 * i
));
1991 radeon_emit(cmd_buffer
->cs
, (va
+ 4 * i
) >> 32);
1992 radeon_emit(cmd_buffer
->cs
, (R_00B928_COMPUTE_USER_DATA_10
>> 2) + i
);
1993 radeon_emit(cmd_buffer
->cs
, 0);
1996 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_SET_BASE
, 2, 0) |
1997 PKT3_SHADER_TYPE_S(1));
1998 radeon_emit(cmd_buffer
->cs
, 1);
1999 radeon_emit(cmd_buffer
->cs
, va
);
2000 radeon_emit(cmd_buffer
->cs
, va
>> 32);
2002 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 1, 0) |
2003 PKT3_SHADER_TYPE_S(1));
2004 radeon_emit(cmd_buffer
->cs
, 0);
2005 radeon_emit(cmd_buffer
->cs
, 1);
2007 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2010 void radv_unaligned_dispatch(
2011 struct radv_cmd_buffer
*cmd_buffer
,
2016 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
2017 struct radv_shader_variant
*compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
2018 uint32_t blocks
[3], remainder
[3];
2020 blocks
[0] = round_up_u32(x
, compute_shader
->info
.cs
.block_size
[0]);
2021 blocks
[1] = round_up_u32(y
, compute_shader
->info
.cs
.block_size
[1]);
2022 blocks
[2] = round_up_u32(z
, compute_shader
->info
.cs
.block_size
[2]);
2024 /* If aligned, these should be an entire block size, not 0 */
2025 remainder
[0] = x
+ compute_shader
->info
.cs
.block_size
[0] - align_u32_npot(x
, compute_shader
->info
.cs
.block_size
[0]);
2026 remainder
[1] = y
+ compute_shader
->info
.cs
.block_size
[1] - align_u32_npot(y
, compute_shader
->info
.cs
.block_size
[1]);
2027 remainder
[2] = z
+ compute_shader
->info
.cs
.block_size
[2] - align_u32_npot(z
, compute_shader
->info
.cs
.block_size
[2]);
2029 radv_emit_compute_pipeline(cmd_buffer
);
2030 radv_flush_constants(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
->layout
,
2031 VK_SHADER_STAGE_COMPUTE_BIT
);
2032 si_emit_cache_flush(cmd_buffer
);
2033 unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 15);
2035 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
2036 radeon_emit(cmd_buffer
->cs
,
2037 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[0]) |
2038 S_00B81C_NUM_THREAD_PARTIAL(remainder
[0]));
2039 radeon_emit(cmd_buffer
->cs
,
2040 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[1]) |
2041 S_00B81C_NUM_THREAD_PARTIAL(remainder
[1]));
2042 radeon_emit(cmd_buffer
->cs
,
2043 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[2]) |
2044 S_00B81C_NUM_THREAD_PARTIAL(remainder
[2]));
2046 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B900_COMPUTE_USER_DATA_0
+ 10 * 4, 3);
2047 radeon_emit(cmd_buffer
->cs
, blocks
[0]);
2048 radeon_emit(cmd_buffer
->cs
, blocks
[1]);
2049 radeon_emit(cmd_buffer
->cs
, blocks
[2]);
2051 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, 0) |
2052 PKT3_SHADER_TYPE_S(1));
2053 radeon_emit(cmd_buffer
->cs
, blocks
[0]);
2054 radeon_emit(cmd_buffer
->cs
, blocks
[1]);
2055 radeon_emit(cmd_buffer
->cs
, blocks
[2]);
2056 radeon_emit(cmd_buffer
->cs
, S_00B800_COMPUTE_SHADER_EN(1) |
2057 S_00B800_PARTIAL_TG_EN(1));
2059 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2062 void radv_CmdEndRenderPass(
2063 VkCommandBuffer commandBuffer
)
2065 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2067 radv_subpass_barrier(cmd_buffer
, &cmd_buffer
->state
.pass
->end_barrier
);
2069 si_emit_cache_flush(cmd_buffer
);
2070 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
2072 for (unsigned i
= 0; i
< cmd_buffer
->state
.framebuffer
->attachment_count
; ++i
) {
2073 VkImageLayout layout
= cmd_buffer
->state
.pass
->attachments
[i
].final_layout
;
2074 radv_handle_subpass_image_transition(cmd_buffer
,
2075 (VkAttachmentReference
){i
, layout
});
2078 radv_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
2080 cmd_buffer
->state
.pass
= NULL
;
2081 cmd_buffer
->state
.subpass
= NULL
;
2082 cmd_buffer
->state
.attachments
= NULL
;
2083 cmd_buffer
->state
.framebuffer
= NULL
;
2087 static void radv_initialize_htile(struct radv_cmd_buffer
*cmd_buffer
,
2088 struct radv_image
*image
)
2091 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
2092 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2094 radv_fill_buffer(cmd_buffer
, image
->bo
, image
->offset
+ image
->htile
.offset
,
2095 image
->htile
.size
, 0xffffffff);
2097 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
|
2098 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
2099 RADV_CMD_FLAG_INV_VMEM_L1
|
2100 RADV_CMD_FLAG_INV_GLOBAL_L2
;
2103 static void radv_handle_depth_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
2104 struct radv_image
*image
,
2105 VkImageLayout src_layout
,
2106 VkImageLayout dst_layout
,
2107 VkImageSubresourceRange range
,
2108 VkImageAspectFlags pending_clears
)
2110 if (dst_layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
&&
2111 (pending_clears
& vk_format_aspects(image
->vk_format
)) == vk_format_aspects(image
->vk_format
) &&
2112 cmd_buffer
->state
.render_area
.offset
.x
== 0 && cmd_buffer
->state
.render_area
.offset
.y
== 0 &&
2113 cmd_buffer
->state
.render_area
.extent
.width
== image
->extent
.width
&&
2114 cmd_buffer
->state
.render_area
.extent
.height
== image
->extent
.height
) {
2115 /* The clear will initialize htile. */
2117 } else if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
&&
2118 radv_layout_has_htile(image
, dst_layout
)) {
2119 /* TODO: merge with the clear if applicable */
2120 radv_initialize_htile(cmd_buffer
, image
);
2121 } else if (!radv_layout_has_htile(image
, src_layout
) &&
2122 radv_layout_has_htile(image
, dst_layout
)) {
2123 radv_initialize_htile(cmd_buffer
, image
);
2124 } else if ((radv_layout_has_htile(image
, src_layout
) &&
2125 !radv_layout_has_htile(image
, dst_layout
)) ||
2126 (radv_layout_is_htile_compressed(image
, src_layout
) &&
2127 !radv_layout_is_htile_compressed(image
, dst_layout
))) {
2129 range
.aspectMask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
2130 range
.baseMipLevel
= 0;
2131 range
.levelCount
= 1;
2133 radv_decompress_depth_image_inplace(cmd_buffer
, image
, &range
);
2137 void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
2138 struct radv_image
*image
, uint32_t value
)
2140 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
2141 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2143 radv_fill_buffer(cmd_buffer
, image
->bo
, image
->offset
+ image
->cmask
.offset
,
2144 image
->cmask
.size
, value
);
2146 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
2147 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
2148 RADV_CMD_FLAG_INV_VMEM_L1
|
2149 RADV_CMD_FLAG_INV_GLOBAL_L2
;
2152 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
2153 struct radv_image
*image
,
2154 VkImageLayout src_layout
,
2155 VkImageLayout dst_layout
,
2156 VkImageSubresourceRange range
,
2157 VkImageAspectFlags pending_clears
)
2159 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
2160 if (image
->fmask
.size
)
2161 radv_initialise_cmask(cmd_buffer
, image
, 0xccccccccu
);
2163 radv_initialise_cmask(cmd_buffer
, image
, 0xffffffffu
);
2164 } else if (radv_layout_has_cmask(image
, src_layout
) &&
2165 !radv_layout_has_cmask(image
, dst_layout
)) {
2166 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
);
2170 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
2171 struct radv_image
*image
, uint32_t value
)
2174 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
2175 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2177 radv_fill_buffer(cmd_buffer
, image
->bo
, image
->offset
+ image
->dcc_offset
,
2178 image
->surface
.dcc_size
, value
);
2180 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
2181 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
2182 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
2183 RADV_CMD_FLAG_INV_VMEM_L1
|
2184 RADV_CMD_FLAG_INV_GLOBAL_L2
;
2187 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
2188 struct radv_image
*image
,
2189 VkImageLayout src_layout
,
2190 VkImageLayout dst_layout
,
2191 VkImageSubresourceRange range
,
2192 VkImageAspectFlags pending_clears
)
2194 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
2195 radv_initialize_dcc(cmd_buffer
, image
, 0x20202020u
);
2196 } else if(src_layout
== VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
&&
2197 dst_layout
!= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
2198 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
);
2202 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
2203 struct radv_image
*image
,
2204 VkImageLayout src_layout
,
2205 VkImageLayout dst_layout
,
2206 VkImageSubresourceRange range
,
2207 VkImageAspectFlags pending_clears
)
2209 if (image
->htile
.size
)
2210 radv_handle_depth_image_transition(cmd_buffer
, image
, src_layout
,
2211 dst_layout
, range
, pending_clears
);
2213 if (image
->cmask
.size
)
2214 radv_handle_cmask_image_transition(cmd_buffer
, image
, src_layout
,
2215 dst_layout
, range
, pending_clears
);
2217 if (image
->surface
.dcc_size
)
2218 radv_handle_dcc_image_transition(cmd_buffer
, image
, src_layout
,
2219 dst_layout
, range
, pending_clears
);
2222 void radv_CmdPipelineBarrier(
2223 VkCommandBuffer commandBuffer
,
2224 VkPipelineStageFlags srcStageMask
,
2225 VkPipelineStageFlags destStageMask
,
2227 uint32_t memoryBarrierCount
,
2228 const VkMemoryBarrier
* pMemoryBarriers
,
2229 uint32_t bufferMemoryBarrierCount
,
2230 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
2231 uint32_t imageMemoryBarrierCount
,
2232 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
2234 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2235 VkAccessFlags src_flags
= 0;
2236 VkAccessFlags dst_flags
= 0;
2238 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
2239 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
2240 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
2243 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
2244 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
2245 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
2248 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
2249 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
2250 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
2251 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
2253 radv_handle_image_transition(cmd_buffer
, image
,
2254 pImageMemoryBarriers
[i
].oldLayout
,
2255 pImageMemoryBarriers
[i
].newLayout
,
2256 pImageMemoryBarriers
[i
].subresourceRange
,
2260 enum radv_cmd_flush_bits flush_bits
= 0;
2262 for_each_bit(b
, src_flags
) {
2263 switch ((VkAccessFlagBits
)(1 << b
)) {
2264 case VK_ACCESS_SHADER_WRITE_BIT
:
2265 flush_bits
|= RADV_CMD_FLAG_INV_GLOBAL_L2
;
2267 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2268 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
2270 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2271 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
2273 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2274 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
2281 for_each_bit(b
, dst_flags
) {
2282 switch ((VkAccessFlagBits
)(1 << b
)) {
2283 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2284 case VK_ACCESS_INDEX_READ_BIT
:
2285 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2286 case VK_ACCESS_UNIFORM_READ_BIT
:
2287 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
;
2289 case VK_ACCESS_SHADER_READ_BIT
:
2290 flush_bits
|= RADV_CMD_FLAG_INV_GLOBAL_L2
;
2292 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
:
2293 case VK_ACCESS_TRANSFER_READ_BIT
:
2294 flush_bits
|= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
| RADV_CMD_FLAG_INV_GLOBAL_L2
;
2300 flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
2301 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
2303 cmd_buffer
->state
.flush_bits
|= flush_bits
;
2307 static void write_event(struct radv_cmd_buffer
*cmd_buffer
,
2308 struct radv_event
*event
,
2309 VkPipelineStageFlags stageMask
,
2312 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
2313 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(event
->bo
);
2315 cmd_buffer
->device
->ws
->cs_add_buffer(cs
, event
->bo
, 8);
2317 unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 12);
2319 /* TODO: this is overkill. Probably should figure something out from
2320 * the stage mask. */
2322 if (cmd_buffer
->device
->instance
->physicalDevice
.rad_info
.chip_class
== CIK
) {
2323 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE_EOP
, 4, 0));
2324 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS
) |
2326 radeon_emit(cs
, va
);
2327 radeon_emit(cs
, (va
>> 32) | EOP_DATA_SEL(1));
2332 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE_EOP
, 4, 0));
2333 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS
) |
2335 radeon_emit(cs
, va
);
2336 radeon_emit(cs
, (va
>> 32) | EOP_DATA_SEL(1));
2337 radeon_emit(cs
, value
);
2340 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2343 void radv_CmdSetEvent(VkCommandBuffer commandBuffer
,
2345 VkPipelineStageFlags stageMask
)
2347 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2348 RADV_FROM_HANDLE(radv_event
, event
, _event
);
2350 write_event(cmd_buffer
, event
, stageMask
, 1);
2353 void radv_CmdResetEvent(VkCommandBuffer commandBuffer
,
2355 VkPipelineStageFlags stageMask
)
2357 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2358 RADV_FROM_HANDLE(radv_event
, event
, _event
);
2360 write_event(cmd_buffer
, event
, stageMask
, 0);
2363 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer
,
2364 uint32_t eventCount
,
2365 const VkEvent
* pEvents
,
2366 VkPipelineStageFlags srcStageMask
,
2367 VkPipelineStageFlags dstStageMask
,
2368 uint32_t memoryBarrierCount
,
2369 const VkMemoryBarrier
* pMemoryBarriers
,
2370 uint32_t bufferMemoryBarrierCount
,
2371 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
2372 uint32_t imageMemoryBarrierCount
,
2373 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
2375 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2376 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
2378 for (unsigned i
= 0; i
< eventCount
; ++i
) {
2379 RADV_FROM_HANDLE(radv_event
, event
, pEvents
[i
]);
2380 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(event
->bo
);
2382 cmd_buffer
->device
->ws
->cs_add_buffer(cs
, event
->bo
, 8);
2384 unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 7);
2386 radeon_emit(cs
, PKT3(PKT3_WAIT_REG_MEM
, 5, 0));
2387 radeon_emit(cs
, WAIT_REG_MEM_EQUAL
| WAIT_REG_MEM_MEM_SPACE(1));
2388 radeon_emit(cs
, va
);
2389 radeon_emit(cs
, va
>> 32);
2390 radeon_emit(cs
, 1); /* reference value */
2391 radeon_emit(cs
, 0xffffffff); /* mask */
2392 radeon_emit(cs
, 4); /* poll interval */
2394 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2398 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
2399 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
2401 radv_handle_image_transition(cmd_buffer
, image
,
2402 pImageMemoryBarriers
[i
].oldLayout
,
2403 pImageMemoryBarriers
[i
].newLayout
,
2404 pImageMemoryBarriers
[i
].subresourceRange
,
2408 /* TODO: figure out how to do memory barriers without waiting */
2409 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
|
2410 RADV_CMD_FLAG_INV_GLOBAL_L2
|
2411 RADV_CMD_FLAG_INV_VMEM_L1
|
2412 RADV_CMD_FLAG_INV_SMEM_L1
;