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radv: Don't invalidate CB/DB for images that aren't modified outside CB/DB.
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_cs.h"
31 #include "sid.h"
32 #include "vk_format.h"
33 #include "radv_meta.h"
34
35 #include "ac_debug.h"
36
37 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
38 struct radv_image *image,
39 VkImageLayout src_layout,
40 VkImageLayout dst_layout,
41 uint32_t src_family,
42 uint32_t dst_family,
43 const VkImageSubresourceRange *range,
44 VkImageAspectFlags pending_clears);
45
46 const struct radv_dynamic_state default_dynamic_state = {
47 .viewport = {
48 .count = 0,
49 },
50 .scissor = {
51 .count = 0,
52 },
53 .line_width = 1.0f,
54 .depth_bias = {
55 .bias = 0.0f,
56 .clamp = 0.0f,
57 .slope = 0.0f,
58 },
59 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
60 .depth_bounds = {
61 .min = 0.0f,
62 .max = 1.0f,
63 },
64 .stencil_compare_mask = {
65 .front = ~0u,
66 .back = ~0u,
67 },
68 .stencil_write_mask = {
69 .front = ~0u,
70 .back = ~0u,
71 },
72 .stencil_reference = {
73 .front = 0u,
74 .back = 0u,
75 },
76 };
77
78 void
79 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
80 const struct radv_dynamic_state *src,
81 uint32_t copy_mask)
82 {
83 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
84 dest->viewport.count = src->viewport.count;
85 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
86 src->viewport.count);
87 }
88
89 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
90 dest->scissor.count = src->scissor.count;
91 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
92 src->scissor.count);
93 }
94
95 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
96 dest->line_width = src->line_width;
97
98 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
99 dest->depth_bias = src->depth_bias;
100
101 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
102 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
103
104 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
105 dest->depth_bounds = src->depth_bounds;
106
107 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
108 dest->stencil_compare_mask = src->stencil_compare_mask;
109
110 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
111 dest->stencil_write_mask = src->stencil_write_mask;
112
113 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
114 dest->stencil_reference = src->stencil_reference;
115 }
116
117 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
118 {
119 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
120 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
121 }
122
123 enum ring_type radv_queue_family_to_ring(int f) {
124 switch (f) {
125 case RADV_QUEUE_GENERAL:
126 return RING_GFX;
127 case RADV_QUEUE_COMPUTE:
128 return RING_COMPUTE;
129 case RADV_QUEUE_TRANSFER:
130 return RING_DMA;
131 default:
132 unreachable("Unknown queue family");
133 }
134 }
135
136 static VkResult radv_create_cmd_buffer(
137 struct radv_device * device,
138 struct radv_cmd_pool * pool,
139 VkCommandBufferLevel level,
140 VkCommandBuffer* pCommandBuffer)
141 {
142 struct radv_cmd_buffer *cmd_buffer;
143 VkResult result;
144 unsigned ring;
145 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
146 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
147 if (cmd_buffer == NULL)
148 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
149
150 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
151 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
152 cmd_buffer->device = device;
153 cmd_buffer->pool = pool;
154 cmd_buffer->level = level;
155
156 if (pool) {
157 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
158 cmd_buffer->queue_family_index = pool->queue_family_index;
159
160 } else {
161 /* Init the pool_link so we can safefly call list_del when we destroy
162 * the command buffer
163 */
164 list_inithead(&cmd_buffer->pool_link);
165 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
166 }
167
168 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
169
170 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
171 if (!cmd_buffer->cs) {
172 result = VK_ERROR_OUT_OF_HOST_MEMORY;
173 goto fail;
174 }
175
176 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
177
178 cmd_buffer->upload.offset = 0;
179 cmd_buffer->upload.size = 0;
180 list_inithead(&cmd_buffer->upload.list);
181
182 return VK_SUCCESS;
183
184 fail:
185 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
186
187 return result;
188 }
189
190 static void
191 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
192 {
193 list_del(&cmd_buffer->pool_link);
194
195 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
196 &cmd_buffer->upload.list, list) {
197 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
198 list_del(&up->list);
199 free(up);
200 }
201
202 if (cmd_buffer->upload.upload_bo)
203 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
204 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
205 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
206 }
207
208 static void radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
209 {
210
211 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
212
213 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
214 &cmd_buffer->upload.list, list) {
215 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
216 list_del(&up->list);
217 free(up);
218 }
219
220 cmd_buffer->scratch_size_needed = 0;
221 cmd_buffer->compute_scratch_size_needed = 0;
222 cmd_buffer->esgs_ring_size_needed = 0;
223 cmd_buffer->gsvs_ring_size_needed = 0;
224
225 if (cmd_buffer->upload.upload_bo)
226 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
227 cmd_buffer->upload.upload_bo, 8);
228 cmd_buffer->upload.offset = 0;
229
230 cmd_buffer->record_fail = false;
231
232 cmd_buffer->ring_offsets_idx = -1;
233 }
234
235 static bool
236 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
237 uint64_t min_needed)
238 {
239 uint64_t new_size;
240 struct radeon_winsys_bo *bo;
241 struct radv_cmd_buffer_upload *upload;
242 struct radv_device *device = cmd_buffer->device;
243
244 new_size = MAX2(min_needed, 16 * 1024);
245 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
246
247 bo = device->ws->buffer_create(device->ws,
248 new_size, 4096,
249 RADEON_DOMAIN_GTT,
250 RADEON_FLAG_CPU_ACCESS);
251
252 if (!bo) {
253 cmd_buffer->record_fail = true;
254 return false;
255 }
256
257 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
258 if (cmd_buffer->upload.upload_bo) {
259 upload = malloc(sizeof(*upload));
260
261 if (!upload) {
262 cmd_buffer->record_fail = true;
263 device->ws->buffer_destroy(bo);
264 return false;
265 }
266
267 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
268 list_add(&upload->list, &cmd_buffer->upload.list);
269 }
270
271 cmd_buffer->upload.upload_bo = bo;
272 cmd_buffer->upload.size = new_size;
273 cmd_buffer->upload.offset = 0;
274 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
275
276 if (!cmd_buffer->upload.map) {
277 cmd_buffer->record_fail = true;
278 return false;
279 }
280
281 return true;
282 }
283
284 bool
285 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
286 unsigned size,
287 unsigned alignment,
288 unsigned *out_offset,
289 void **ptr)
290 {
291 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
292 if (offset + size > cmd_buffer->upload.size) {
293 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
294 return false;
295 offset = 0;
296 }
297
298 *out_offset = offset;
299 *ptr = cmd_buffer->upload.map + offset;
300
301 cmd_buffer->upload.offset = offset + size;
302 return true;
303 }
304
305 bool
306 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
307 unsigned size, unsigned alignment,
308 const void *data, unsigned *out_offset)
309 {
310 uint8_t *ptr;
311
312 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
313 out_offset, (void **)&ptr))
314 return false;
315
316 if (ptr)
317 memcpy(ptr, data, size);
318
319 return true;
320 }
321
322 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
323 {
324 struct radv_device *device = cmd_buffer->device;
325 struct radeon_winsys_cs *cs = cmd_buffer->cs;
326 uint64_t va;
327
328 if (!device->trace_bo)
329 return;
330
331 va = device->ws->buffer_get_va(device->trace_bo);
332
333 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
334
335 ++cmd_buffer->state.trace_id;
336 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
337 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
338 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
339 S_370_WR_CONFIRM(1) |
340 S_370_ENGINE_SEL(V_370_ME));
341 radeon_emit(cs, va);
342 radeon_emit(cs, va >> 32);
343 radeon_emit(cs, cmd_buffer->state.trace_id);
344 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
345 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
346 }
347
348 static void
349 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
350 struct radv_pipeline *pipeline)
351 {
352 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
353 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
354 8);
355 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
356 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
357 }
358
359 static void
360 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
361 struct radv_pipeline *pipeline)
362 {
363 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
364 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
365 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
366
367 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
368 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
369 }
370
371 /* 12.4 fixed-point */
372 static unsigned radv_pack_float_12p4(float x)
373 {
374 return x <= 0 ? 0 :
375 x >= 4096 ? 0xffff : x * 16;
376 }
377
378 static uint32_t
379 shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs)
380 {
381 switch (stage) {
382 case MESA_SHADER_FRAGMENT:
383 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
384 case MESA_SHADER_VERTEX:
385 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
386 case MESA_SHADER_GEOMETRY:
387 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
388 case MESA_SHADER_COMPUTE:
389 return R_00B900_COMPUTE_USER_DATA_0;
390 default:
391 unreachable("unknown shader");
392 }
393 }
394
395 static struct ac_userdata_info *
396 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
397 gl_shader_stage stage,
398 int idx)
399 {
400 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
401 }
402
403 static void
404 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
405 struct radv_pipeline *pipeline,
406 gl_shader_stage stage,
407 int idx, uint64_t va)
408 {
409 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
410 uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline));
411 if (loc->sgpr_idx == -1)
412 return;
413 assert(loc->num_sgprs == 2);
414 assert(!loc->indirect);
415 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
416 radeon_emit(cmd_buffer->cs, va);
417 radeon_emit(cmd_buffer->cs, va >> 32);
418 }
419
420 static void
421 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
422 struct radv_pipeline *pipeline)
423 {
424 int num_samples = pipeline->graphics.ms.num_samples;
425 struct radv_multisample_state *ms = &pipeline->graphics.ms;
426 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
427
428 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
429 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
430 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
431
432 radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa);
433 radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
434
435 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
436 return;
437
438 radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
439 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
440 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
441
442 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
443
444 uint32_t samples_offset;
445 void *samples_ptr;
446 void *src;
447 radv_cmd_buffer_upload_alloc(cmd_buffer, num_samples * 4 * 2, 256, &samples_offset,
448 &samples_ptr);
449 switch (num_samples) {
450 case 1:
451 src = cmd_buffer->device->sample_locations_1x;
452 break;
453 case 2:
454 src = cmd_buffer->device->sample_locations_2x;
455 break;
456 case 4:
457 src = cmd_buffer->device->sample_locations_4x;
458 break;
459 case 8:
460 src = cmd_buffer->device->sample_locations_8x;
461 break;
462 case 16:
463 src = cmd_buffer->device->sample_locations_16x;
464 break;
465 default:
466 unreachable("unknown number of samples");
467 }
468 memcpy(samples_ptr, src, num_samples * 4 * 2);
469
470 uint64_t va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
471 va += samples_offset;
472
473 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
474 AC_UD_PS_SAMPLE_POS, va);
475 }
476
477 static void
478 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
479 struct radv_pipeline *pipeline)
480 {
481 struct radv_raster_state *raster = &pipeline->graphics.raster;
482
483 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
484 raster->pa_cl_clip_cntl);
485
486 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
487 raster->spi_interp_control);
488
489 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A00_PA_SU_POINT_SIZE, 2);
490 unsigned tmp = (unsigned)(1.0 * 8.0);
491 radeon_emit(cmd_buffer->cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
492 radeon_emit(cmd_buffer->cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
493 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
494
495 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
496 raster->pa_su_vtx_cntl);
497
498 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
499 raster->pa_su_sc_mode_cntl);
500 }
501
502 static void
503 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
504 struct radv_pipeline *pipeline,
505 struct radv_shader_variant *shader)
506 {
507 struct radeon_winsys *ws = cmd_buffer->device->ws;
508 uint64_t va = ws->buffer_get_va(shader->bo);
509 unsigned export_count;
510
511 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
512
513 export_count = MAX2(1, shader->info.vs.param_exports);
514 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
515 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
516
517 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
518 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
519 S_02870C_POS1_EXPORT_FORMAT(shader->info.vs.pos_exports > 1 ?
520 V_02870C_SPI_SHADER_4COMP :
521 V_02870C_SPI_SHADER_NONE) |
522 S_02870C_POS2_EXPORT_FORMAT(shader->info.vs.pos_exports > 2 ?
523 V_02870C_SPI_SHADER_4COMP :
524 V_02870C_SPI_SHADER_NONE) |
525 S_02870C_POS3_EXPORT_FORMAT(shader->info.vs.pos_exports > 3 ?
526 V_02870C_SPI_SHADER_4COMP :
527 V_02870C_SPI_SHADER_NONE));
528
529
530 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
531 radeon_emit(cmd_buffer->cs, va >> 8);
532 radeon_emit(cmd_buffer->cs, va >> 40);
533 radeon_emit(cmd_buffer->cs, shader->rsrc1);
534 radeon_emit(cmd_buffer->cs, shader->rsrc2);
535
536 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
537 S_028818_VTX_W0_FMT(1) |
538 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
539 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
540 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
541
542 unsigned clip_dist_mask, cull_dist_mask, total_mask;
543 clip_dist_mask = shader->info.vs.clip_dist_mask;
544 cull_dist_mask = shader->info.vs.cull_dist_mask;
545 total_mask = clip_dist_mask | cull_dist_mask;
546
547 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
548 S_02881C_USE_VTX_POINT_SIZE(shader->info.vs.writes_pointsize) |
549 S_02881C_USE_VTX_RENDER_TARGET_INDX(shader->info.vs.writes_layer) |
550 S_02881C_USE_VTX_VIEWPORT_INDX(shader->info.vs.writes_viewport_index) |
551 S_02881C_VS_OUT_MISC_VEC_ENA(shader->info.vs.writes_pointsize ||
552 shader->info.vs.writes_layer ||
553 shader->info.vs.writes_viewport_index) |
554 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
555 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
556 pipeline->graphics.raster.pa_cl_vs_out_cntl |
557 cull_dist_mask << 8 |
558 clip_dist_mask);
559
560 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
561 S_028AB4_REUSE_OFF(shader->info.vs.writes_viewport_index));
562 }
563
564 static void
565 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
566 struct radv_shader_variant *shader)
567 {
568 struct radeon_winsys *ws = cmd_buffer->device->ws;
569 uint64_t va = ws->buffer_get_va(shader->bo);
570
571 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
572
573 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
574 shader->info.vs.esgs_itemsize / 4);
575 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
576 radeon_emit(cmd_buffer->cs, va >> 8);
577 radeon_emit(cmd_buffer->cs, va >> 40);
578 radeon_emit(cmd_buffer->cs, shader->rsrc1);
579 radeon_emit(cmd_buffer->cs, shader->rsrc2);
580 }
581
582 static void
583 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
584 struct radv_pipeline *pipeline)
585 {
586 struct radv_shader_variant *vs;
587
588 assert (pipeline->shaders[MESA_SHADER_VERTEX]);
589
590 vs = pipeline->shaders[MESA_SHADER_VERTEX];
591
592 if (vs->info.vs.as_es)
593 radv_emit_hw_es(cmd_buffer, vs);
594 else
595 radv_emit_hw_vs(cmd_buffer, pipeline, vs);
596
597 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, 0);
598 }
599
600 static uint32_t si_vgt_gs_mode(struct radv_shader_variant *gs)
601 {
602 unsigned gs_max_vert_out = gs->info.gs.vertices_out;
603 unsigned cut_mode;
604
605 if (gs_max_vert_out <= 128) {
606 cut_mode = V_028A40_GS_CUT_128;
607 } else if (gs_max_vert_out <= 256) {
608 cut_mode = V_028A40_GS_CUT_256;
609 } else if (gs_max_vert_out <= 512) {
610 cut_mode = V_028A40_GS_CUT_512;
611 } else {
612 assert(gs_max_vert_out <= 1024);
613 cut_mode = V_028A40_GS_CUT_1024;
614 }
615
616 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
617 S_028A40_CUT_MODE(cut_mode)|
618 S_028A40_ES_WRITE_OPTIMIZE(1) |
619 S_028A40_GS_WRITE_OPTIMIZE(1);
620 }
621
622 static void
623 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
624 struct radv_pipeline *pipeline)
625 {
626 struct radeon_winsys *ws = cmd_buffer->device->ws;
627 struct radv_shader_variant *gs;
628 uint64_t va;
629
630 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
631 if (!gs) {
632 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, 0);
633 return;
634 }
635
636 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(gs));
637
638 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
639
640 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
641 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
642 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
643 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
644
645 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
646
647 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
648
649 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
650 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
651 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
652 radeon_emit(cmd_buffer->cs, 0);
653 radeon_emit(cmd_buffer->cs, 0);
654 radeon_emit(cmd_buffer->cs, 0);
655
656 uint32_t gs_num_invocations = gs->info.gs.invocations;
657 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
658 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
659 S_028B90_ENABLE(gs_num_invocations > 0));
660
661 va = ws->buffer_get_va(gs->bo);
662 ws->cs_add_buffer(cmd_buffer->cs, gs->bo, 8);
663 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
664 radeon_emit(cmd_buffer->cs, va >> 8);
665 radeon_emit(cmd_buffer->cs, va >> 40);
666 radeon_emit(cmd_buffer->cs, gs->rsrc1);
667 radeon_emit(cmd_buffer->cs, gs->rsrc2);
668
669 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader);
670
671 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
672 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
673 if (loc->sgpr_idx != -1) {
674 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
675 uint32_t num_entries = 64;
676 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
677
678 if (is_vi)
679 num_entries *= stride;
680
681 stride = S_008F04_STRIDE(stride);
682 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
683 radeon_emit(cmd_buffer->cs, stride);
684 radeon_emit(cmd_buffer->cs, num_entries);
685 }
686 }
687
688 static void
689 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
690 struct radv_pipeline *pipeline)
691 {
692 struct radeon_winsys *ws = cmd_buffer->device->ws;
693 struct radv_shader_variant *ps, *vs;
694 uint64_t va;
695 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
696 struct radv_blend_state *blend = &pipeline->graphics.blend;
697 unsigned ps_offset = 0;
698 unsigned z_order;
699 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
700
701 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
702 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : pipeline->shaders[MESA_SHADER_VERTEX];
703 va = ws->buffer_get_va(ps->bo);
704 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
705
706 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
707 radeon_emit(cmd_buffer->cs, va >> 8);
708 radeon_emit(cmd_buffer->cs, va >> 40);
709 radeon_emit(cmd_buffer->cs, ps->rsrc1);
710 radeon_emit(cmd_buffer->cs, ps->rsrc2);
711
712 if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
713 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
714 else
715 z_order = V_02880C_LATE_Z;
716
717
718 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
719 S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
720 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
721 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
722 S_02880C_MASK_EXPORT_ENABLE(ps->info.fs.writes_sample_mask) |
723 S_02880C_Z_ORDER(z_order) |
724 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
725 S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
726 S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory));
727
728 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
729 ps->config.spi_ps_input_ena);
730
731 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
732 ps->config.spi_ps_input_addr);
733
734 if (ps->info.fs.force_persample)
735 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
736
737 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
738 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
739
740 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
741
742 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
743 ps->info.fs.writes_sample_mask ? V_028710_SPI_SHADER_32_ABGR :
744 ps->info.fs.writes_stencil ? V_028710_SPI_SHADER_32_GR :
745 ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R :
746 V_028710_SPI_SHADER_ZERO);
747
748 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
749
750 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
751 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
752
753 if (ps->info.fs.has_pcoord) {
754 unsigned val;
755 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
756 radeon_set_context_reg(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset, val);
757 ps_offset++;
758 }
759
760 if (ps->info.fs.prim_id_input && (vs->info.vs.prim_id_output != 0xffffffff)) {
761 unsigned vs_offset, flat_shade;
762 unsigned val;
763 vs_offset = vs->info.vs.prim_id_output;
764 flat_shade = true;
765 val = S_028644_OFFSET(vs_offset) | S_028644_FLAT_SHADE(flat_shade);
766 radeon_set_context_reg(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset, val);
767 ++ps_offset;
768 }
769
770 if (ps->info.fs.layer_input && (vs->info.vs.layer_output != 0xffffffff)) {
771 unsigned vs_offset, flat_shade;
772 unsigned val;
773 vs_offset = vs->info.vs.layer_output;
774 flat_shade = true;
775 val = S_028644_OFFSET(vs_offset) | S_028644_FLAT_SHADE(flat_shade);
776 radeon_set_context_reg(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset, val);
777 ++ps_offset;
778 }
779
780 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
781 unsigned vs_offset, flat_shade;
782 unsigned val;
783
784 if (!(ps->info.fs.input_mask & (1u << i)))
785 continue;
786
787
788 if (!(vs->info.vs.export_mask & (1u << i))) {
789 radeon_set_context_reg(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset,
790 S_028644_OFFSET(0x20));
791 ++ps_offset;
792 continue;
793 }
794
795 vs_offset = util_bitcount(vs->info.vs.export_mask & ((1u << i) - 1));
796 if (vs->info.vs.prim_id_output != 0xffffffff) {
797 if (vs_offset >= vs->info.vs.prim_id_output)
798 vs_offset++;
799 }
800 if (vs->info.vs.layer_output != 0xffffffff) {
801 if (vs_offset >= vs->info.vs.layer_output)
802 vs_offset++;
803 }
804 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
805
806 val = S_028644_OFFSET(vs_offset) | S_028644_FLAT_SHADE(flat_shade);
807 radeon_set_context_reg(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset, val);
808 ++ps_offset;
809 }
810 }
811
812 static void
813 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer,
814 struct radv_pipeline *pipeline)
815 {
816 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
817 return;
818
819 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
820 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
821 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
822 radv_update_multisample_state(cmd_buffer, pipeline);
823 radv_emit_vertex_shader(cmd_buffer, pipeline);
824 radv_emit_geometry_shader(cmd_buffer, pipeline);
825 radv_emit_fragment_shader(cmd_buffer, pipeline);
826
827 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
828 pipeline->graphics.prim_restart_enable);
829
830 cmd_buffer->scratch_size_needed =
831 MAX2(cmd_buffer->scratch_size_needed,
832 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
833
834 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
835 S_0286E8_WAVES(pipeline->max_waves) |
836 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
837 cmd_buffer->state.emitted_pipeline = pipeline;
838 }
839
840 static void
841 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
842 {
843 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
844 cmd_buffer->state.dynamic.viewport.viewports);
845 }
846
847 static void
848 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
849 {
850 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
851 si_write_scissors(cmd_buffer->cs, 0, count,
852 cmd_buffer->state.dynamic.scissor.scissors);
853 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
854 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
855 }
856
857 static void
858 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
859 int index,
860 struct radv_color_buffer_info *cb)
861 {
862 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
863 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
864 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
865 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
866 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
867 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
868 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
869 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
870 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
871 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
872 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
873 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
874 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
875
876 if (is_vi) { /* DCC BASE */
877 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
878 }
879 }
880
881 static void
882 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
883 struct radv_ds_buffer_info *ds,
884 struct radv_image *image,
885 VkImageLayout layout)
886 {
887 uint32_t db_z_info = ds->db_z_info;
888
889 if (!radv_layout_has_htile(image, layout))
890 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
891
892 if (!radv_layout_can_expclear(image, layout))
893 db_z_info &= C_028040_ALLOW_EXPCLEAR & C_028044_ALLOW_EXPCLEAR;
894
895 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
896 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
897
898 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
899 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
900 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
901 radeon_emit(cmd_buffer->cs, ds->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
902 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
903 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
904 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
905 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
906 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
907 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
908
909 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
910 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
911 ds->pa_su_poly_offset_db_fmt_cntl);
912 }
913
914 /*
915 * To hw resolve multisample images both src and dst need to have the same
916 * micro tiling mode. However we don't always know in advance when creating
917 * the images. This function gets called if we have a resolve attachment,
918 * and tests if the attachment image has the same tiling mode, then it
919 * checks if the generated framebuffer data has the same tiling mode, and
920 * updates it if not.
921 */
922 static void radv_set_optimal_micro_tile_mode(struct radv_device *device,
923 struct radv_attachment_info *att,
924 uint32_t micro_tile_mode)
925 {
926 struct radv_image *image = att->attachment->image;
927 uint32_t tile_mode_index;
928 if (image->surface.nsamples <= 1)
929 return;
930
931 if (image->surface.micro_tile_mode != micro_tile_mode) {
932 radv_image_set_optimal_micro_tile_mode(device, image, micro_tile_mode);
933 }
934
935 if (att->cb.micro_tile_mode != micro_tile_mode) {
936 tile_mode_index = image->surface.tiling_index[0];
937
938 att->cb.cb_color_attrib &= C_028C74_TILE_MODE_INDEX;
939 att->cb.cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
940 att->cb.micro_tile_mode = micro_tile_mode;
941 }
942 }
943
944 void
945 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
946 struct radv_image *image,
947 VkClearDepthStencilValue ds_clear_value,
948 VkImageAspectFlags aspects)
949 {
950 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
951 va += image->offset + image->clear_value_offset;
952 unsigned reg_offset = 0, reg_count = 0;
953
954 if (!image->surface.htile_size || !aspects)
955 return;
956
957 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
958 ++reg_count;
959 } else {
960 ++reg_offset;
961 va += 4;
962 }
963 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
964 ++reg_count;
965
966 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
967
968 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
969 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
970 S_370_WR_CONFIRM(1) |
971 S_370_ENGINE_SEL(V_370_PFP));
972 radeon_emit(cmd_buffer->cs, va);
973 radeon_emit(cmd_buffer->cs, va >> 32);
974 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
975 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
976 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
977 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
978
979 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
980 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
981 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
982 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
983 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
984 }
985
986 static void
987 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
988 struct radv_image *image)
989 {
990 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
991 va += image->offset + image->clear_value_offset;
992
993 if (!image->surface.htile_size)
994 return;
995
996 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
997
998 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
999 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1000 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1001 COPY_DATA_COUNT_SEL);
1002 radeon_emit(cmd_buffer->cs, va);
1003 radeon_emit(cmd_buffer->cs, va >> 32);
1004 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
1005 radeon_emit(cmd_buffer->cs, 0);
1006
1007 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1008 radeon_emit(cmd_buffer->cs, 0);
1009 }
1010
1011 void
1012 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1013 struct radv_image *image,
1014 int idx,
1015 uint32_t color_values[2])
1016 {
1017 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1018 va += image->offset + image->clear_value_offset;
1019
1020 if (!image->cmask.size && !image->surface.dcc_size)
1021 return;
1022
1023 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1024
1025 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1026 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1027 S_370_WR_CONFIRM(1) |
1028 S_370_ENGINE_SEL(V_370_PFP));
1029 radeon_emit(cmd_buffer->cs, va);
1030 radeon_emit(cmd_buffer->cs, va >> 32);
1031 radeon_emit(cmd_buffer->cs, color_values[0]);
1032 radeon_emit(cmd_buffer->cs, color_values[1]);
1033
1034 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1035 radeon_emit(cmd_buffer->cs, color_values[0]);
1036 radeon_emit(cmd_buffer->cs, color_values[1]);
1037 }
1038
1039 static void
1040 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1041 struct radv_image *image,
1042 int idx)
1043 {
1044 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1045 va += image->offset + image->clear_value_offset;
1046
1047 if (!image->cmask.size && !image->surface.dcc_size)
1048 return;
1049
1050 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1051 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1052
1053 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1054 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1055 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1056 COPY_DATA_COUNT_SEL);
1057 radeon_emit(cmd_buffer->cs, va);
1058 radeon_emit(cmd_buffer->cs, va >> 32);
1059 radeon_emit(cmd_buffer->cs, reg >> 2);
1060 radeon_emit(cmd_buffer->cs, 0);
1061
1062 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1063 radeon_emit(cmd_buffer->cs, 0);
1064 }
1065
1066 void
1067 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1068 {
1069 int i;
1070 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1071 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1072 int dst_resolve_micro_tile_mode = -1;
1073
1074 if (subpass->has_resolve) {
1075 uint32_t a = subpass->resolve_attachments[0].attachment;
1076 const struct radv_image *image = framebuffer->attachments[a].attachment->image;
1077 dst_resolve_micro_tile_mode = image->surface.micro_tile_mode;
1078 }
1079 for (i = 0; i < subpass->color_count; ++i) {
1080 int idx = subpass->color_attachments[i].attachment;
1081 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1082
1083 if (dst_resolve_micro_tile_mode != -1) {
1084 radv_set_optimal_micro_tile_mode(cmd_buffer->device,
1085 att, dst_resolve_micro_tile_mode);
1086 }
1087 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1088
1089 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1090 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1091
1092 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1093 }
1094
1095 for (i = subpass->color_count; i < 8; i++)
1096 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1097 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1098
1099 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1100 int idx = subpass->depth_stencil_attachment.attachment;
1101 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1102 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1103 struct radv_image *image = att->attachment->image;
1104 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1105
1106 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1107
1108 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1109 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1110 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1111 }
1112 radv_load_depth_clear_regs(cmd_buffer, image);
1113 } else {
1114 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1115 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1116 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1117 }
1118 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1119 S_028208_BR_X(framebuffer->width) |
1120 S_028208_BR_Y(framebuffer->height));
1121 }
1122
1123 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1124 {
1125 uint32_t db_count_control;
1126
1127 if(!cmd_buffer->state.active_occlusion_queries) {
1128 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1129 db_count_control = 0;
1130 } else {
1131 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1132 }
1133 } else {
1134 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1135 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1136 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1137 S_028004_ZPASS_ENABLE(1) |
1138 S_028004_SLICE_EVEN_ENABLE(1) |
1139 S_028004_SLICE_ODD_ENABLE(1);
1140 } else {
1141 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1142 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1143 }
1144 }
1145
1146 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1147 }
1148
1149 static void
1150 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1151 {
1152 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1153
1154 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH) {
1155 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1156 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1157 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1158 }
1159
1160 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
1161 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1162 radeon_emit_array(cmd_buffer->cs, (uint32_t*)d->blend_constants, 4);
1163 }
1164
1165 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1166 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1167 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK)) {
1168 radeon_set_context_reg_seq(cmd_buffer->cs, R_028430_DB_STENCILREFMASK, 2);
1169 radeon_emit(cmd_buffer->cs, S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1170 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1171 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1172 S_028430_STENCILOPVAL(1));
1173 radeon_emit(cmd_buffer->cs, S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1174 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1175 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1176 S_028434_STENCILOPVAL_BF(1));
1177 }
1178
1179 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1180 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) {
1181 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, fui(d->depth_bounds.min));
1182 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX, fui(d->depth_bounds.max));
1183 }
1184
1185 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1186 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
1187 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1188 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1189 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1190
1191 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1192 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1193 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1194 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1195 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1196 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1197 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1198 }
1199 }
1200
1201 cmd_buffer->state.dirty = 0;
1202 }
1203
1204 static void
1205 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1206 struct radv_pipeline *pipeline,
1207 int idx,
1208 uint64_t va,
1209 gl_shader_stage stage)
1210 {
1211 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1212 uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline));
1213
1214 if (desc_set_loc->sgpr_idx == -1)
1215 return;
1216
1217 assert(!desc_set_loc->indirect);
1218 assert(desc_set_loc->num_sgprs == 2);
1219 radeon_set_sh_reg_seq(cmd_buffer->cs,
1220 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1221 radeon_emit(cmd_buffer->cs, va);
1222 radeon_emit(cmd_buffer->cs, va >> 32);
1223 }
1224
1225 static void
1226 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1227 struct radv_pipeline *pipeline,
1228 VkShaderStageFlags stages,
1229 struct radv_descriptor_set *set,
1230 unsigned idx)
1231 {
1232 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1233 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1234 idx, set->va,
1235 MESA_SHADER_FRAGMENT);
1236
1237 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1238 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1239 idx, set->va,
1240 MESA_SHADER_VERTEX);
1241
1242 if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(pipeline))
1243 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1244 idx, set->va,
1245 MESA_SHADER_GEOMETRY);
1246
1247 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1248 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1249 idx, set->va,
1250 MESA_SHADER_COMPUTE);
1251 }
1252
1253 static void
1254 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1255 struct radv_pipeline *pipeline,
1256 VkShaderStageFlags stages)
1257 {
1258 unsigned i;
1259 if (!cmd_buffer->state.descriptors_dirty)
1260 return;
1261
1262 for (i = 0; i < MAX_SETS; i++) {
1263 if (!(cmd_buffer->state.descriptors_dirty & (1 << i)))
1264 continue;
1265 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1266 if (!set)
1267 continue;
1268
1269 radv_emit_descriptor_set_userdata(cmd_buffer, pipeline, stages, set, i);
1270 }
1271 cmd_buffer->state.descriptors_dirty = 0;
1272 }
1273
1274 static void
1275 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1276 struct radv_pipeline *pipeline,
1277 VkShaderStageFlags stages)
1278 {
1279 struct radv_pipeline_layout *layout = pipeline->layout;
1280 unsigned offset;
1281 void *ptr;
1282 uint64_t va;
1283
1284 stages &= cmd_buffer->push_constant_stages;
1285 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1286 return;
1287
1288 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1289 16 * layout->dynamic_offset_count,
1290 256, &offset, &ptr))
1291 return;
1292
1293 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1294 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1295 16 * layout->dynamic_offset_count);
1296
1297 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1298 va += offset;
1299
1300 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1301 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1302 AC_UD_PUSH_CONSTANTS, va);
1303
1304 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1305 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
1306 AC_UD_PUSH_CONSTANTS, va);
1307
1308 if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(pipeline))
1309 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_GEOMETRY,
1310 AC_UD_PUSH_CONSTANTS, va);
1311
1312 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1313 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_COMPUTE,
1314 AC_UD_PUSH_CONSTANTS, va);
1315
1316 cmd_buffer->push_constant_stages &= ~stages;
1317 }
1318
1319 static void
1320 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer, bool instanced_or_indirect_draw,
1321 uint32_t draw_vertex_count)
1322 {
1323 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1324 struct radv_device *device = cmd_buffer->device;
1325 uint32_t ia_multi_vgt_param;
1326 uint32_t ls_hs_config = 0;
1327
1328 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1329 cmd_buffer->cs, 4096);
1330
1331 if ((cmd_buffer->state.vertex_descriptors_dirty || cmd_buffer->state.vb_dirty) &&
1332 cmd_buffer->state.pipeline->num_vertex_attribs) {
1333 unsigned vb_offset;
1334 void *vb_ptr;
1335 uint32_t i = 0;
1336 uint32_t num_attribs = cmd_buffer->state.pipeline->num_vertex_attribs;
1337 uint64_t va;
1338
1339 /* allocate some descriptor state for vertex buffers */
1340 radv_cmd_buffer_upload_alloc(cmd_buffer, num_attribs * 16, 256,
1341 &vb_offset, &vb_ptr);
1342
1343 for (i = 0; i < num_attribs; i++) {
1344 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1345 uint32_t offset;
1346 int vb = cmd_buffer->state.pipeline->va_binding[i];
1347 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1348 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1349
1350 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1351 va = device->ws->buffer_get_va(buffer->bo);
1352
1353 offset = cmd_buffer->state.vertex_bindings[vb].offset + cmd_buffer->state.pipeline->va_offset[i];
1354 va += offset + buffer->offset;
1355 desc[0] = va;
1356 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1357 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1358 desc[2] = (buffer->size - offset - cmd_buffer->state.pipeline->va_format_size[i]) / stride + 1;
1359 else
1360 desc[2] = buffer->size - offset;
1361 desc[3] = cmd_buffer->state.pipeline->va_rsrc_word3[i];
1362 }
1363
1364 va = device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1365 va += vb_offset;
1366
1367 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1368 AC_UD_VS_VERTEX_BUFFERS, va);
1369 }
1370
1371 cmd_buffer->state.vertex_descriptors_dirty = false;
1372 cmd_buffer->state.vb_dirty = 0;
1373 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1374 radv_emit_graphics_pipeline(cmd_buffer, pipeline);
1375
1376 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1377 radv_emit_framebuffer_state(cmd_buffer);
1378
1379 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1380 radv_emit_viewport(cmd_buffer);
1381
1382 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR))
1383 radv_emit_scissor(cmd_buffer);
1384
1385 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_or_indirect_draw, draw_vertex_count);
1386 if (cmd_buffer->state.last_ia_multi_vgt_param != ia_multi_vgt_param) {
1387 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
1388 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1389 else
1390 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1391 cmd_buffer->state.last_ia_multi_vgt_param = ia_multi_vgt_param;
1392 }
1393
1394 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) {
1395 uint32_t stages = 0;
1396
1397 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1398 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
1399 S_028B54_GS_EN(1) |
1400 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1401
1402 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, stages);
1403
1404 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1405 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2, ls_hs_config);
1406 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, cmd_buffer->state.pipeline->graphics.prim);
1407 } else {
1408 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, cmd_buffer->state.pipeline->graphics.prim);
1409 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
1410 }
1411 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, cmd_buffer->state.pipeline->graphics.gs_out);
1412 }
1413
1414 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1415
1416 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.pipeline,
1417 VK_SHADER_STAGE_ALL_GRAPHICS);
1418 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1419 VK_SHADER_STAGE_ALL_GRAPHICS);
1420
1421 assert(cmd_buffer->cs->cdw <= cdw_max);
1422
1423 si_emit_cache_flush(cmd_buffer);
1424 }
1425
1426 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1427 VkPipelineStageFlags src_stage_mask)
1428 {
1429 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1430 VK_PIPELINE_STAGE_TRANSFER_BIT |
1431 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1432 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1433 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1434 }
1435
1436 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1437 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1438 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1439 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1440 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1441 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1442 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1443 VK_PIPELINE_STAGE_TRANSFER_BIT |
1444 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1445 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1446 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1447 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1448 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1449 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1450 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1451 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1452 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1453 }
1454 }
1455
1456 static enum radv_cmd_flush_bits
1457 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1458 VkAccessFlags src_flags)
1459 {
1460 enum radv_cmd_flush_bits flush_bits = 0;
1461 uint32_t b;
1462 for_each_bit(b, src_flags) {
1463 switch ((VkAccessFlagBits)(1 << b)) {
1464 case VK_ACCESS_SHADER_WRITE_BIT:
1465 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1466 break;
1467 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1468 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1469 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1470 break;
1471 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1472 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1473 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1474 break;
1475 case VK_ACCESS_TRANSFER_WRITE_BIT:
1476 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1477 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1478 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1479 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1480 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1481 break;
1482 default:
1483 break;
1484 }
1485 }
1486 return flush_bits;
1487 }
1488
1489 static enum radv_cmd_flush_bits
1490 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1491 VkAccessFlags dst_flags,
1492 struct radv_image *image)
1493 {
1494 enum radv_cmd_flush_bits flush_bits = 0;
1495 uint32_t b;
1496 for_each_bit(b, dst_flags) {
1497 switch ((VkAccessFlagBits)(1 << b)) {
1498 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1499 case VK_ACCESS_INDEX_READ_BIT:
1500 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1501 break;
1502 case VK_ACCESS_UNIFORM_READ_BIT:
1503 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1504 break;
1505 case VK_ACCESS_SHADER_READ_BIT:
1506 case VK_ACCESS_TRANSFER_READ_BIT:
1507 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1508 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1509 RADV_CMD_FLAG_INV_GLOBAL_L2;
1510 break;
1511 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1512 /* TODO: change to image && when the image gets passed
1513 * through from the subpass. */
1514 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1515 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1516 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1517 break;
1518 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1519 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1520 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1521 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1522 break;
1523 default:
1524 break;
1525 }
1526 }
1527 return flush_bits;
1528 }
1529
1530 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1531 {
1532 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1533 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1534 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1535 NULL);
1536 }
1537
1538 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1539 VkAttachmentReference att)
1540 {
1541 unsigned idx = att.attachment;
1542 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1543 VkImageSubresourceRange range;
1544 range.aspectMask = 0;
1545 range.baseMipLevel = view->base_mip;
1546 range.levelCount = 1;
1547 range.baseArrayLayer = view->base_layer;
1548 range.layerCount = cmd_buffer->state.framebuffer->layers;
1549
1550 radv_handle_image_transition(cmd_buffer,
1551 view->image,
1552 cmd_buffer->state.attachments[idx].current_layout,
1553 att.layout, 0, 0, &range,
1554 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1555
1556 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1557
1558
1559 }
1560
1561 void
1562 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1563 const struct radv_subpass *subpass, bool transitions)
1564 {
1565 if (transitions) {
1566 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1567
1568 for (unsigned i = 0; i < subpass->color_count; ++i) {
1569 radv_handle_subpass_image_transition(cmd_buffer,
1570 subpass->color_attachments[i]);
1571 }
1572
1573 for (unsigned i = 0; i < subpass->input_count; ++i) {
1574 radv_handle_subpass_image_transition(cmd_buffer,
1575 subpass->input_attachments[i]);
1576 }
1577
1578 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1579 radv_handle_subpass_image_transition(cmd_buffer,
1580 subpass->depth_stencil_attachment);
1581 }
1582 }
1583
1584 cmd_buffer->state.subpass = subpass;
1585
1586 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1587 }
1588
1589 static void
1590 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1591 struct radv_render_pass *pass,
1592 const VkRenderPassBeginInfo *info)
1593 {
1594 struct radv_cmd_state *state = &cmd_buffer->state;
1595
1596 if (pass->attachment_count == 0) {
1597 state->attachments = NULL;
1598 return;
1599 }
1600
1601 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1602 pass->attachment_count *
1603 sizeof(state->attachments[0]),
1604 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1605 if (state->attachments == NULL) {
1606 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1607 abort();
1608 }
1609
1610 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1611 struct radv_render_pass_attachment *att = &pass->attachments[i];
1612 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1613 VkImageAspectFlags clear_aspects = 0;
1614
1615 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1616 /* color attachment */
1617 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1618 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1619 }
1620 } else {
1621 /* depthstencil attachment */
1622 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1623 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1624 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1625 }
1626 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1627 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1628 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1629 }
1630 }
1631
1632 state->attachments[i].pending_clear_aspects = clear_aspects;
1633 if (clear_aspects && info) {
1634 assert(info->clearValueCount > i);
1635 state->attachments[i].clear_value = info->pClearValues[i];
1636 }
1637
1638 state->attachments[i].current_layout = att->initial_layout;
1639 }
1640 }
1641
1642 VkResult radv_AllocateCommandBuffers(
1643 VkDevice _device,
1644 const VkCommandBufferAllocateInfo *pAllocateInfo,
1645 VkCommandBuffer *pCommandBuffers)
1646 {
1647 RADV_FROM_HANDLE(radv_device, device, _device);
1648 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1649
1650 VkResult result = VK_SUCCESS;
1651 uint32_t i;
1652
1653 memset(pCommandBuffers, 0,
1654 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
1655
1656 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1657
1658 if (!list_empty(&pool->free_cmd_buffers)) {
1659 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1660
1661 list_del(&cmd_buffer->pool_link);
1662 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1663
1664 radv_reset_cmd_buffer(cmd_buffer);
1665 cmd_buffer->level = pAllocateInfo->level;
1666
1667 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
1668 result = VK_SUCCESS;
1669 } else {
1670 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1671 &pCommandBuffers[i]);
1672 }
1673 if (result != VK_SUCCESS)
1674 break;
1675 }
1676
1677 if (result != VK_SUCCESS)
1678 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1679 i, pCommandBuffers);
1680
1681 return result;
1682 }
1683
1684 void radv_FreeCommandBuffers(
1685 VkDevice device,
1686 VkCommandPool commandPool,
1687 uint32_t commandBufferCount,
1688 const VkCommandBuffer *pCommandBuffers)
1689 {
1690 for (uint32_t i = 0; i < commandBufferCount; i++) {
1691 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1692
1693 if (cmd_buffer) {
1694 if (cmd_buffer->pool) {
1695 list_del(&cmd_buffer->pool_link);
1696 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
1697 } else
1698 radv_cmd_buffer_destroy(cmd_buffer);
1699
1700 }
1701 }
1702 }
1703
1704 VkResult radv_ResetCommandBuffer(
1705 VkCommandBuffer commandBuffer,
1706 VkCommandBufferResetFlags flags)
1707 {
1708 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1709 radv_reset_cmd_buffer(cmd_buffer);
1710 return VK_SUCCESS;
1711 }
1712
1713 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
1714 {
1715 struct radv_device *device = cmd_buffer->device;
1716 if (device->gfx_init) {
1717 uint64_t va = device->ws->buffer_get_va(device->gfx_init);
1718 device->ws->cs_add_buffer(cmd_buffer->cs, device->gfx_init, 8);
1719 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
1720 radeon_emit(cmd_buffer->cs, va);
1721 radeon_emit(cmd_buffer->cs, (va >> 32) & 0xffff);
1722 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
1723 } else
1724 si_init_config(cmd_buffer);
1725 }
1726
1727 VkResult radv_BeginCommandBuffer(
1728 VkCommandBuffer commandBuffer,
1729 const VkCommandBufferBeginInfo *pBeginInfo)
1730 {
1731 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1732 radv_reset_cmd_buffer(cmd_buffer);
1733
1734 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1735
1736 /* setup initial configuration into command buffer */
1737 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1738 switch (cmd_buffer->queue_family_index) {
1739 case RADV_QUEUE_GENERAL:
1740 emit_gfx_buffer_state(cmd_buffer);
1741 radv_set_db_count_control(cmd_buffer);
1742 break;
1743 case RADV_QUEUE_COMPUTE:
1744 si_init_compute(cmd_buffer);
1745 break;
1746 case RADV_QUEUE_TRANSFER:
1747 default:
1748 break;
1749 }
1750 }
1751
1752 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1753 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1754 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1755
1756 struct radv_subpass *subpass =
1757 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1758
1759 radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1760 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
1761 }
1762
1763 return VK_SUCCESS;
1764 }
1765
1766 void radv_CmdBindVertexBuffers(
1767 VkCommandBuffer commandBuffer,
1768 uint32_t firstBinding,
1769 uint32_t bindingCount,
1770 const VkBuffer* pBuffers,
1771 const VkDeviceSize* pOffsets)
1772 {
1773 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1774 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
1775
1776 /* We have to defer setting up vertex buffer since we need the buffer
1777 * stride from the pipeline. */
1778
1779 assert(firstBinding + bindingCount < MAX_VBS);
1780 for (uint32_t i = 0; i < bindingCount; i++) {
1781 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
1782 vb[firstBinding + i].offset = pOffsets[i];
1783 cmd_buffer->state.vb_dirty |= 1 << (firstBinding + i);
1784 }
1785 }
1786
1787 void radv_CmdBindIndexBuffer(
1788 VkCommandBuffer commandBuffer,
1789 VkBuffer buffer,
1790 VkDeviceSize offset,
1791 VkIndexType indexType)
1792 {
1793 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1794
1795 cmd_buffer->state.index_buffer = radv_buffer_from_handle(buffer);
1796 cmd_buffer->state.index_offset = offset;
1797 cmd_buffer->state.index_type = indexType; /* vk matches hw */
1798 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
1799 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, cmd_buffer->state.index_buffer->bo, 8);
1800 }
1801
1802
1803 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1804 struct radv_descriptor_set *set,
1805 unsigned idx)
1806 {
1807 struct radeon_winsys *ws = cmd_buffer->device->ws;
1808
1809 cmd_buffer->state.descriptors[idx] = set;
1810 cmd_buffer->state.descriptors_dirty |= (1 << idx);
1811 if (!set)
1812 return;
1813
1814 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
1815 if (set->descriptors[j])
1816 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
1817
1818 if(set->bo)
1819 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
1820 }
1821
1822 void radv_CmdBindDescriptorSets(
1823 VkCommandBuffer commandBuffer,
1824 VkPipelineBindPoint pipelineBindPoint,
1825 VkPipelineLayout _layout,
1826 uint32_t firstSet,
1827 uint32_t descriptorSetCount,
1828 const VkDescriptorSet* pDescriptorSets,
1829 uint32_t dynamicOffsetCount,
1830 const uint32_t* pDynamicOffsets)
1831 {
1832 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1833 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
1834 unsigned dyn_idx = 0;
1835
1836 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1837 cmd_buffer->cs, MAX_SETS * 4 * 6);
1838
1839 for (unsigned i = 0; i < descriptorSetCount; ++i) {
1840 unsigned idx = i + firstSet;
1841 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
1842 radv_bind_descriptor_set(cmd_buffer, set, idx);
1843
1844 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1845 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
1846 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
1847 assert(dyn_idx < dynamicOffsetCount);
1848
1849 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
1850 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
1851 dst[0] = va;
1852 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
1853 dst[2] = range->size;
1854 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1855 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1856 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1857 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1858 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1859 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1860 cmd_buffer->push_constant_stages |=
1861 set->layout->dynamic_shader_stages;
1862 }
1863 }
1864
1865 assert(cmd_buffer->cs->cdw <= cdw_max);
1866 }
1867
1868 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
1869 VkPipelineLayout layout,
1870 VkShaderStageFlags stageFlags,
1871 uint32_t offset,
1872 uint32_t size,
1873 const void* pValues)
1874 {
1875 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1876 memcpy(cmd_buffer->push_constants + offset, pValues, size);
1877 cmd_buffer->push_constant_stages |= stageFlags;
1878 }
1879
1880 VkResult radv_EndCommandBuffer(
1881 VkCommandBuffer commandBuffer)
1882 {
1883 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1884
1885 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER)
1886 si_emit_cache_flush(cmd_buffer);
1887
1888 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs) ||
1889 cmd_buffer->record_fail)
1890 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1891 return VK_SUCCESS;
1892 }
1893
1894 static void
1895 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
1896 {
1897 struct radeon_winsys *ws = cmd_buffer->device->ws;
1898 struct radv_shader_variant *compute_shader;
1899 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
1900 uint64_t va;
1901
1902 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
1903 return;
1904
1905 cmd_buffer->state.emitted_compute_pipeline = pipeline;
1906
1907 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
1908 va = ws->buffer_get_va(compute_shader->bo);
1909
1910 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
1911
1912 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1913 cmd_buffer->cs, 16);
1914
1915 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
1916 radeon_emit(cmd_buffer->cs, va >> 8);
1917 radeon_emit(cmd_buffer->cs, va >> 40);
1918
1919 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
1920 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
1921 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
1922
1923
1924 cmd_buffer->compute_scratch_size_needed =
1925 MAX2(cmd_buffer->compute_scratch_size_needed,
1926 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1927
1928 /* change these once we have scratch support */
1929 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
1930 S_00B860_WAVES(pipeline->max_waves) |
1931 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
1932
1933 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
1934 radeon_emit(cmd_buffer->cs,
1935 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
1936 radeon_emit(cmd_buffer->cs,
1937 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
1938 radeon_emit(cmd_buffer->cs,
1939 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
1940
1941 assert(cmd_buffer->cs->cdw <= cdw_max);
1942 }
1943
1944
1945 void radv_CmdBindPipeline(
1946 VkCommandBuffer commandBuffer,
1947 VkPipelineBindPoint pipelineBindPoint,
1948 VkPipeline _pipeline)
1949 {
1950 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1951 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1952
1953 for (unsigned i = 0; i < MAX_SETS; i++) {
1954 if (cmd_buffer->state.descriptors[i])
1955 cmd_buffer->state.descriptors_dirty |= (1 << i);
1956 }
1957
1958 switch (pipelineBindPoint) {
1959 case VK_PIPELINE_BIND_POINT_COMPUTE:
1960 cmd_buffer->state.compute_pipeline = pipeline;
1961 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
1962 break;
1963 case VK_PIPELINE_BIND_POINT_GRAPHICS:
1964 cmd_buffer->state.pipeline = pipeline;
1965 cmd_buffer->state.vertex_descriptors_dirty = true;
1966 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
1967 cmd_buffer->push_constant_stages |= pipeline->active_stages;
1968
1969 /* Apply the dynamic state from the pipeline */
1970 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
1971 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
1972 &pipeline->dynamic_state,
1973 pipeline->dynamic_state_mask);
1974
1975 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
1976 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
1977 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
1978 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
1979
1980 if (radv_pipeline_has_gs(pipeline)) {
1981 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1982 AC_UD_SCRATCH_RING_OFFSETS);
1983 if (cmd_buffer->ring_offsets_idx == -1)
1984 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
1985 else if (loc->sgpr_idx != -1)
1986 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
1987 }
1988 break;
1989 default:
1990 assert(!"invalid bind point");
1991 break;
1992 }
1993 }
1994
1995 void radv_CmdSetViewport(
1996 VkCommandBuffer commandBuffer,
1997 uint32_t firstViewport,
1998 uint32_t viewportCount,
1999 const VkViewport* pViewports)
2000 {
2001 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2002
2003 const uint32_t total_count = firstViewport + viewportCount;
2004 if (cmd_buffer->state.dynamic.viewport.count < total_count)
2005 cmd_buffer->state.dynamic.viewport.count = total_count;
2006
2007 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2008 pViewports, viewportCount * sizeof(*pViewports));
2009
2010 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2011 }
2012
2013 void radv_CmdSetScissor(
2014 VkCommandBuffer commandBuffer,
2015 uint32_t firstScissor,
2016 uint32_t scissorCount,
2017 const VkRect2D* pScissors)
2018 {
2019 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2020
2021 const uint32_t total_count = firstScissor + scissorCount;
2022 if (cmd_buffer->state.dynamic.scissor.count < total_count)
2023 cmd_buffer->state.dynamic.scissor.count = total_count;
2024
2025 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2026 pScissors, scissorCount * sizeof(*pScissors));
2027 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2028 }
2029
2030 void radv_CmdSetLineWidth(
2031 VkCommandBuffer commandBuffer,
2032 float lineWidth)
2033 {
2034 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2035 cmd_buffer->state.dynamic.line_width = lineWidth;
2036 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2037 }
2038
2039 void radv_CmdSetDepthBias(
2040 VkCommandBuffer commandBuffer,
2041 float depthBiasConstantFactor,
2042 float depthBiasClamp,
2043 float depthBiasSlopeFactor)
2044 {
2045 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2046
2047 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2048 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2049 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2050
2051 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2052 }
2053
2054 void radv_CmdSetBlendConstants(
2055 VkCommandBuffer commandBuffer,
2056 const float blendConstants[4])
2057 {
2058 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2059
2060 memcpy(cmd_buffer->state.dynamic.blend_constants,
2061 blendConstants, sizeof(float) * 4);
2062
2063 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2064 }
2065
2066 void radv_CmdSetDepthBounds(
2067 VkCommandBuffer commandBuffer,
2068 float minDepthBounds,
2069 float maxDepthBounds)
2070 {
2071 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2072
2073 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2074 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2075
2076 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2077 }
2078
2079 void radv_CmdSetStencilCompareMask(
2080 VkCommandBuffer commandBuffer,
2081 VkStencilFaceFlags faceMask,
2082 uint32_t compareMask)
2083 {
2084 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2085
2086 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2087 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2088 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2089 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2090
2091 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2092 }
2093
2094 void radv_CmdSetStencilWriteMask(
2095 VkCommandBuffer commandBuffer,
2096 VkStencilFaceFlags faceMask,
2097 uint32_t writeMask)
2098 {
2099 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2100
2101 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2102 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2103 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2104 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2105
2106 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2107 }
2108
2109 void radv_CmdSetStencilReference(
2110 VkCommandBuffer commandBuffer,
2111 VkStencilFaceFlags faceMask,
2112 uint32_t reference)
2113 {
2114 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2115
2116 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2117 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2118 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2119 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2120
2121 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2122 }
2123
2124
2125 void radv_CmdExecuteCommands(
2126 VkCommandBuffer commandBuffer,
2127 uint32_t commandBufferCount,
2128 const VkCommandBuffer* pCmdBuffers)
2129 {
2130 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2131
2132 /* Emit pending flushes on primary prior to executing secondary */
2133 si_emit_cache_flush(primary);
2134
2135 for (uint32_t i = 0; i < commandBufferCount; i++) {
2136 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2137
2138 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2139 secondary->scratch_size_needed);
2140 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2141 secondary->compute_scratch_size_needed);
2142
2143 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2144 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2145 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2146 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2147
2148 if (secondary->ring_offsets_idx != -1) {
2149 if (primary->ring_offsets_idx == -1)
2150 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2151 else
2152 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2153 }
2154 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2155 }
2156
2157 /* if we execute secondary we need to re-emit out pipelines */
2158 if (commandBufferCount) {
2159 primary->state.emitted_pipeline = NULL;
2160 primary->state.emitted_compute_pipeline = NULL;
2161 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2162 primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
2163 }
2164 }
2165
2166 VkResult radv_CreateCommandPool(
2167 VkDevice _device,
2168 const VkCommandPoolCreateInfo* pCreateInfo,
2169 const VkAllocationCallbacks* pAllocator,
2170 VkCommandPool* pCmdPool)
2171 {
2172 RADV_FROM_HANDLE(radv_device, device, _device);
2173 struct radv_cmd_pool *pool;
2174
2175 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2176 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2177 if (pool == NULL)
2178 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2179
2180 if (pAllocator)
2181 pool->alloc = *pAllocator;
2182 else
2183 pool->alloc = device->alloc;
2184
2185 list_inithead(&pool->cmd_buffers);
2186 list_inithead(&pool->free_cmd_buffers);
2187
2188 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2189
2190 *pCmdPool = radv_cmd_pool_to_handle(pool);
2191
2192 return VK_SUCCESS;
2193
2194 }
2195
2196 void radv_DestroyCommandPool(
2197 VkDevice _device,
2198 VkCommandPool commandPool,
2199 const VkAllocationCallbacks* pAllocator)
2200 {
2201 RADV_FROM_HANDLE(radv_device, device, _device);
2202 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2203
2204 if (!pool)
2205 return;
2206
2207 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2208 &pool->cmd_buffers, pool_link) {
2209 radv_cmd_buffer_destroy(cmd_buffer);
2210 }
2211
2212 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2213 &pool->free_cmd_buffers, pool_link) {
2214 radv_cmd_buffer_destroy(cmd_buffer);
2215 }
2216
2217 vk_free2(&device->alloc, pAllocator, pool);
2218 }
2219
2220 VkResult radv_ResetCommandPool(
2221 VkDevice device,
2222 VkCommandPool commandPool,
2223 VkCommandPoolResetFlags flags)
2224 {
2225 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2226
2227 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2228 &pool->cmd_buffers, pool_link) {
2229 radv_reset_cmd_buffer(cmd_buffer);
2230 }
2231
2232 return VK_SUCCESS;
2233 }
2234
2235 void radv_TrimCommandPoolKHR(
2236 VkDevice device,
2237 VkCommandPool commandPool,
2238 VkCommandPoolTrimFlagsKHR flags)
2239 {
2240 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2241
2242 if (!pool)
2243 return;
2244
2245 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2246 &pool->free_cmd_buffers, pool_link) {
2247 radv_cmd_buffer_destroy(cmd_buffer);
2248 }
2249 }
2250
2251 void radv_CmdBeginRenderPass(
2252 VkCommandBuffer commandBuffer,
2253 const VkRenderPassBeginInfo* pRenderPassBegin,
2254 VkSubpassContents contents)
2255 {
2256 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2257 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2258 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2259
2260 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2261 cmd_buffer->cs, 2048);
2262
2263 cmd_buffer->state.framebuffer = framebuffer;
2264 cmd_buffer->state.pass = pass;
2265 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2266 radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2267
2268 si_emit_cache_flush(cmd_buffer);
2269
2270 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2271 assert(cmd_buffer->cs->cdw <= cdw_max);
2272
2273 radv_cmd_buffer_clear_subpass(cmd_buffer);
2274 }
2275
2276 void radv_CmdNextSubpass(
2277 VkCommandBuffer commandBuffer,
2278 VkSubpassContents contents)
2279 {
2280 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2281
2282 si_emit_cache_flush(cmd_buffer);
2283 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2284
2285 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2286 2048);
2287
2288 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2289 radv_cmd_buffer_clear_subpass(cmd_buffer);
2290 }
2291
2292 void radv_CmdDraw(
2293 VkCommandBuffer commandBuffer,
2294 uint32_t vertexCount,
2295 uint32_t instanceCount,
2296 uint32_t firstVertex,
2297 uint32_t firstInstance)
2298 {
2299 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2300
2301 radv_cmd_buffer_flush_state(cmd_buffer, (instanceCount > 1), vertexCount);
2302
2303 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2304
2305 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2306 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2307 if (loc->sgpr_idx != -1) {
2308 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline));
2309 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 3);
2310 radeon_emit(cmd_buffer->cs, firstVertex);
2311 radeon_emit(cmd_buffer->cs, firstInstance);
2312 radeon_emit(cmd_buffer->cs, 0);
2313 }
2314 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2315 radeon_emit(cmd_buffer->cs, instanceCount);
2316
2317 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, 0));
2318 radeon_emit(cmd_buffer->cs, vertexCount);
2319 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2320 S_0287F0_USE_OPAQUE(0));
2321
2322 assert(cmd_buffer->cs->cdw <= cdw_max);
2323
2324 radv_cmd_buffer_trace_emit(cmd_buffer);
2325 }
2326
2327 static void radv_emit_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2328 {
2329 uint32_t primitive_reset_index = cmd_buffer->state.last_primitive_reset_index ? 0xffffffffu : 0xffffu;
2330
2331 if (cmd_buffer->state.pipeline->graphics.prim_restart_enable &&
2332 primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
2333 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
2334 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2335 primitive_reset_index);
2336 }
2337 }
2338
2339 void radv_CmdDrawIndexed(
2340 VkCommandBuffer commandBuffer,
2341 uint32_t indexCount,
2342 uint32_t instanceCount,
2343 uint32_t firstIndex,
2344 int32_t vertexOffset,
2345 uint32_t firstInstance)
2346 {
2347 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2348 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2349 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2350 uint64_t index_va;
2351
2352 radv_cmd_buffer_flush_state(cmd_buffer, (instanceCount > 1), indexCount);
2353 radv_emit_primitive_reset_index(cmd_buffer);
2354
2355 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2356
2357 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2358 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2359
2360 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2361 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2362 if (loc->sgpr_idx != -1) {
2363 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline));
2364 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 3);
2365 radeon_emit(cmd_buffer->cs, vertexOffset);
2366 radeon_emit(cmd_buffer->cs, firstInstance);
2367 radeon_emit(cmd_buffer->cs, 0);
2368 }
2369 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2370 radeon_emit(cmd_buffer->cs, instanceCount);
2371
2372 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2373 index_va += firstIndex * index_size + cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2374 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2375 radeon_emit(cmd_buffer->cs, index_max_size);
2376 radeon_emit(cmd_buffer->cs, index_va);
2377 radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
2378 radeon_emit(cmd_buffer->cs, indexCount);
2379 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2380
2381 assert(cmd_buffer->cs->cdw <= cdw_max);
2382 radv_cmd_buffer_trace_emit(cmd_buffer);
2383 }
2384
2385 static void
2386 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
2387 VkBuffer _buffer,
2388 VkDeviceSize offset,
2389 VkBuffer _count_buffer,
2390 VkDeviceSize count_offset,
2391 uint32_t draw_count,
2392 uint32_t stride,
2393 bool indexed)
2394 {
2395 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2396 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
2397 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2398 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2399 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2400 uint64_t indirect_va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2401 indirect_va += offset + buffer->offset;
2402 uint64_t count_va = 0;
2403
2404 if (count_buffer) {
2405 count_va = cmd_buffer->device->ws->buffer_get_va(count_buffer->bo);
2406 count_va += count_offset + count_buffer->offset;
2407 }
2408
2409 if (!draw_count)
2410 return;
2411
2412 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
2413
2414 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2415 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2416 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline));
2417 assert(loc->sgpr_idx != -1);
2418 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2419 radeon_emit(cs, 1);
2420 radeon_emit(cs, indirect_va);
2421 radeon_emit(cs, indirect_va >> 32);
2422
2423 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2424 PKT3_DRAW_INDIRECT_MULTI,
2425 8, false));
2426 radeon_emit(cs, 0);
2427 radeon_emit(cs, ((base_reg + loc->sgpr_idx * 4) - SI_SH_REG_OFFSET) >> 2);
2428 radeon_emit(cs, ((base_reg + (loc->sgpr_idx + 1) * 4) - SI_SH_REG_OFFSET) >> 2);
2429 radeon_emit(cs, (((base_reg + (loc->sgpr_idx + 2) * 4) - SI_SH_REG_OFFSET) >> 2) |
2430 S_2C3_DRAW_INDEX_ENABLE(1) |
2431 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2432 radeon_emit(cs, draw_count); /* count */
2433 radeon_emit(cs, count_va); /* count_addr */
2434 radeon_emit(cs, count_va >> 32);
2435 radeon_emit(cs, stride); /* stride */
2436 radeon_emit(cs, di_src_sel);
2437 radv_cmd_buffer_trace_emit(cmd_buffer);
2438 }
2439
2440 static void
2441 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
2442 VkBuffer buffer,
2443 VkDeviceSize offset,
2444 VkBuffer countBuffer,
2445 VkDeviceSize countBufferOffset,
2446 uint32_t maxDrawCount,
2447 uint32_t stride)
2448 {
2449 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2450 radv_cmd_buffer_flush_state(cmd_buffer, true, 0);
2451
2452 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2453 cmd_buffer->cs, 14);
2454
2455 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2456 countBuffer, countBufferOffset, maxDrawCount, stride, false);
2457
2458 assert(cmd_buffer->cs->cdw <= cdw_max);
2459 }
2460
2461 static void
2462 radv_cmd_draw_indexed_indirect_count(
2463 VkCommandBuffer commandBuffer,
2464 VkBuffer buffer,
2465 VkDeviceSize offset,
2466 VkBuffer countBuffer,
2467 VkDeviceSize countBufferOffset,
2468 uint32_t maxDrawCount,
2469 uint32_t stride)
2470 {
2471 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2472 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2473 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2474 uint64_t index_va;
2475 radv_cmd_buffer_flush_state(cmd_buffer, true, 0);
2476 radv_emit_primitive_reset_index(cmd_buffer);
2477
2478 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2479 index_va += cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2480
2481 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 21);
2482
2483 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2484 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2485
2486 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2487 radeon_emit(cmd_buffer->cs, index_va);
2488 radeon_emit(cmd_buffer->cs, index_va >> 32);
2489
2490 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2491 radeon_emit(cmd_buffer->cs, index_max_size);
2492
2493 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2494 countBuffer, countBufferOffset, maxDrawCount, stride, true);
2495
2496 assert(cmd_buffer->cs->cdw <= cdw_max);
2497 }
2498
2499 void radv_CmdDrawIndirect(
2500 VkCommandBuffer commandBuffer,
2501 VkBuffer buffer,
2502 VkDeviceSize offset,
2503 uint32_t drawCount,
2504 uint32_t stride)
2505 {
2506 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2507 VK_NULL_HANDLE, 0, drawCount, stride);
2508 }
2509
2510 void radv_CmdDrawIndexedIndirect(
2511 VkCommandBuffer commandBuffer,
2512 VkBuffer buffer,
2513 VkDeviceSize offset,
2514 uint32_t drawCount,
2515 uint32_t stride)
2516 {
2517 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2518 VK_NULL_HANDLE, 0, drawCount, stride);
2519 }
2520
2521 void radv_CmdDrawIndirectCountAMD(
2522 VkCommandBuffer commandBuffer,
2523 VkBuffer buffer,
2524 VkDeviceSize offset,
2525 VkBuffer countBuffer,
2526 VkDeviceSize countBufferOffset,
2527 uint32_t maxDrawCount,
2528 uint32_t stride)
2529 {
2530 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2531 countBuffer, countBufferOffset,
2532 maxDrawCount, stride);
2533 }
2534
2535 void radv_CmdDrawIndexedIndirectCountAMD(
2536 VkCommandBuffer commandBuffer,
2537 VkBuffer buffer,
2538 VkDeviceSize offset,
2539 VkBuffer countBuffer,
2540 VkDeviceSize countBufferOffset,
2541 uint32_t maxDrawCount,
2542 uint32_t stride)
2543 {
2544 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2545 countBuffer, countBufferOffset,
2546 maxDrawCount, stride);
2547 }
2548
2549 static void
2550 radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
2551 {
2552 radv_emit_compute_pipeline(cmd_buffer);
2553 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.compute_pipeline,
2554 VK_SHADER_STAGE_COMPUTE_BIT);
2555 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
2556 VK_SHADER_STAGE_COMPUTE_BIT);
2557 si_emit_cache_flush(cmd_buffer);
2558 }
2559
2560 void radv_CmdDispatch(
2561 VkCommandBuffer commandBuffer,
2562 uint32_t x,
2563 uint32_t y,
2564 uint32_t z)
2565 {
2566 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2567
2568 radv_flush_compute_state(cmd_buffer);
2569
2570 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2571
2572 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2573 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2574 if (loc->sgpr_idx != -1) {
2575 assert(!loc->indirect);
2576 assert(loc->num_sgprs == 3);
2577 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3);
2578 radeon_emit(cmd_buffer->cs, x);
2579 radeon_emit(cmd_buffer->cs, y);
2580 radeon_emit(cmd_buffer->cs, z);
2581 }
2582
2583 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2584 PKT3_SHADER_TYPE_S(1));
2585 radeon_emit(cmd_buffer->cs, x);
2586 radeon_emit(cmd_buffer->cs, y);
2587 radeon_emit(cmd_buffer->cs, z);
2588 radeon_emit(cmd_buffer->cs, 1);
2589
2590 assert(cmd_buffer->cs->cdw <= cdw_max);
2591 radv_cmd_buffer_trace_emit(cmd_buffer);
2592 }
2593
2594 void radv_CmdDispatchIndirect(
2595 VkCommandBuffer commandBuffer,
2596 VkBuffer _buffer,
2597 VkDeviceSize offset)
2598 {
2599 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2600 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2601 uint64_t va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2602 va += buffer->offset + offset;
2603
2604 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
2605
2606 radv_flush_compute_state(cmd_buffer);
2607
2608 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 25);
2609 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2610 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2611 if (loc->sgpr_idx != -1) {
2612 for (unsigned i = 0; i < 3; ++i) {
2613 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
2614 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
2615 COPY_DATA_DST_SEL(COPY_DATA_REG));
2616 radeon_emit(cmd_buffer->cs, (va + 4 * i));
2617 radeon_emit(cmd_buffer->cs, (va + 4 * i) >> 32);
2618 radeon_emit(cmd_buffer->cs, ((R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4) >> 2) + i);
2619 radeon_emit(cmd_buffer->cs, 0);
2620 }
2621 }
2622
2623 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
2624 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
2625 PKT3_SHADER_TYPE_S(1));
2626 radeon_emit(cmd_buffer->cs, va);
2627 radeon_emit(cmd_buffer->cs, va >> 32);
2628 radeon_emit(cmd_buffer->cs, 1);
2629 } else {
2630 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_BASE, 2, 0) |
2631 PKT3_SHADER_TYPE_S(1));
2632 radeon_emit(cmd_buffer->cs, 1);
2633 radeon_emit(cmd_buffer->cs, va);
2634 radeon_emit(cmd_buffer->cs, va >> 32);
2635
2636 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
2637 PKT3_SHADER_TYPE_S(1));
2638 radeon_emit(cmd_buffer->cs, 0);
2639 radeon_emit(cmd_buffer->cs, 1);
2640 }
2641
2642 assert(cmd_buffer->cs->cdw <= cdw_max);
2643 radv_cmd_buffer_trace_emit(cmd_buffer);
2644 }
2645
2646 void radv_unaligned_dispatch(
2647 struct radv_cmd_buffer *cmd_buffer,
2648 uint32_t x,
2649 uint32_t y,
2650 uint32_t z)
2651 {
2652 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2653 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2654 uint32_t blocks[3], remainder[3];
2655
2656 blocks[0] = round_up_u32(x, compute_shader->info.cs.block_size[0]);
2657 blocks[1] = round_up_u32(y, compute_shader->info.cs.block_size[1]);
2658 blocks[2] = round_up_u32(z, compute_shader->info.cs.block_size[2]);
2659
2660 /* If aligned, these should be an entire block size, not 0 */
2661 remainder[0] = x + compute_shader->info.cs.block_size[0] - align_u32_npot(x, compute_shader->info.cs.block_size[0]);
2662 remainder[1] = y + compute_shader->info.cs.block_size[1] - align_u32_npot(y, compute_shader->info.cs.block_size[1]);
2663 remainder[2] = z + compute_shader->info.cs.block_size[2] - align_u32_npot(z, compute_shader->info.cs.block_size[2]);
2664
2665 radv_flush_compute_state(cmd_buffer);
2666
2667 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2668
2669 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2670 radeon_emit(cmd_buffer->cs,
2671 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]) |
2672 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
2673 radeon_emit(cmd_buffer->cs,
2674 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]) |
2675 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
2676 radeon_emit(cmd_buffer->cs,
2677 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]) |
2678 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
2679
2680 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2681 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2682 if (loc->sgpr_idx != -1) {
2683 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3);
2684 radeon_emit(cmd_buffer->cs, blocks[0]);
2685 radeon_emit(cmd_buffer->cs, blocks[1]);
2686 radeon_emit(cmd_buffer->cs, blocks[2]);
2687 }
2688 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2689 PKT3_SHADER_TYPE_S(1));
2690 radeon_emit(cmd_buffer->cs, blocks[0]);
2691 radeon_emit(cmd_buffer->cs, blocks[1]);
2692 radeon_emit(cmd_buffer->cs, blocks[2]);
2693 radeon_emit(cmd_buffer->cs, S_00B800_COMPUTE_SHADER_EN(1) |
2694 S_00B800_PARTIAL_TG_EN(1));
2695
2696 assert(cmd_buffer->cs->cdw <= cdw_max);
2697 radv_cmd_buffer_trace_emit(cmd_buffer);
2698 }
2699
2700 void radv_CmdEndRenderPass(
2701 VkCommandBuffer commandBuffer)
2702 {
2703 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2704
2705 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
2706
2707 si_emit_cache_flush(cmd_buffer);
2708 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2709
2710 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
2711 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
2712 radv_handle_subpass_image_transition(cmd_buffer,
2713 (VkAttachmentReference){i, layout});
2714 }
2715
2716 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2717
2718 cmd_buffer->state.pass = NULL;
2719 cmd_buffer->state.subpass = NULL;
2720 cmd_buffer->state.attachments = NULL;
2721 cmd_buffer->state.framebuffer = NULL;
2722 }
2723
2724
2725 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
2726 struct radv_image *image,
2727 const VkImageSubresourceRange *range)
2728 {
2729 assert(range->baseMipLevel == 0);
2730 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
2731 unsigned layer_count = radv_get_layerCount(image, range);
2732 uint64_t size = image->surface.htile_slice_size * layer_count;
2733 uint64_t offset = image->offset + image->htile_offset +
2734 image->surface.htile_slice_size * range->baseArrayLayer;
2735
2736 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2737 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2738
2739 radv_fill_buffer(cmd_buffer, image->bo, offset, size, 0xffffffff);
2740
2741 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
2742 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2743 RADV_CMD_FLAG_INV_VMEM_L1 |
2744 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2745 }
2746
2747 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
2748 struct radv_image *image,
2749 VkImageLayout src_layout,
2750 VkImageLayout dst_layout,
2751 const VkImageSubresourceRange *range,
2752 VkImageAspectFlags pending_clears)
2753 {
2754 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
2755 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
2756 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
2757 cmd_buffer->state.render_area.extent.width == image->extent.width &&
2758 cmd_buffer->state.render_area.extent.height == image->extent.height) {
2759 /* The clear will initialize htile. */
2760 return;
2761 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
2762 radv_layout_has_htile(image, dst_layout)) {
2763 /* TODO: merge with the clear if applicable */
2764 radv_initialize_htile(cmd_buffer, image, range);
2765 } else if (!radv_layout_has_htile(image, src_layout) &&
2766 radv_layout_has_htile(image, dst_layout)) {
2767 radv_initialize_htile(cmd_buffer, image, range);
2768 } else if ((radv_layout_has_htile(image, src_layout) &&
2769 !radv_layout_has_htile(image, dst_layout)) ||
2770 (radv_layout_is_htile_compressed(image, src_layout) &&
2771 !radv_layout_is_htile_compressed(image, dst_layout))) {
2772 VkImageSubresourceRange local_range = *range;
2773 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
2774 local_range.baseMipLevel = 0;
2775 local_range.levelCount = 1;
2776
2777 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
2778 }
2779 }
2780
2781 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
2782 struct radv_image *image, uint32_t value)
2783 {
2784 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2785 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2786
2787 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
2788 image->cmask.size, value);
2789
2790 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2791 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2792 RADV_CMD_FLAG_INV_VMEM_L1 |
2793 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2794 }
2795
2796 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
2797 struct radv_image *image,
2798 VkImageLayout src_layout,
2799 VkImageLayout dst_layout,
2800 unsigned src_queue_mask,
2801 unsigned dst_queue_mask,
2802 const VkImageSubresourceRange *range,
2803 VkImageAspectFlags pending_clears)
2804 {
2805 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
2806 if (image->fmask.size)
2807 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
2808 else
2809 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
2810 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
2811 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
2812 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
2813 }
2814 }
2815
2816 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
2817 struct radv_image *image, uint32_t value)
2818 {
2819
2820 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2821 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2822
2823 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
2824 image->surface.dcc_size, value);
2825
2826 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2827 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2828 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2829 RADV_CMD_FLAG_INV_VMEM_L1 |
2830 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2831 }
2832
2833 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
2834 struct radv_image *image,
2835 VkImageLayout src_layout,
2836 VkImageLayout dst_layout,
2837 unsigned src_queue_mask,
2838 unsigned dst_queue_mask,
2839 const VkImageSubresourceRange *range,
2840 VkImageAspectFlags pending_clears)
2841 {
2842 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
2843 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
2844 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
2845 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
2846 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
2847 }
2848 }
2849
2850 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
2851 struct radv_image *image,
2852 VkImageLayout src_layout,
2853 VkImageLayout dst_layout,
2854 uint32_t src_family,
2855 uint32_t dst_family,
2856 const VkImageSubresourceRange *range,
2857 VkImageAspectFlags pending_clears)
2858 {
2859 if (image->exclusive && src_family != dst_family) {
2860 /* This is an acquire or a release operation and there will be
2861 * a corresponding release/acquire. Do the transition in the
2862 * most flexible queue. */
2863
2864 assert(src_family == cmd_buffer->queue_family_index ||
2865 dst_family == cmd_buffer->queue_family_index);
2866
2867 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
2868 return;
2869
2870 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
2871 (src_family == RADV_QUEUE_GENERAL ||
2872 dst_family == RADV_QUEUE_GENERAL))
2873 return;
2874 }
2875
2876 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
2877 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
2878
2879 if (image->surface.htile_size)
2880 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
2881 dst_layout, range, pending_clears);
2882
2883 if (image->cmask.size)
2884 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
2885 dst_layout, src_queue_mask,
2886 dst_queue_mask, range,
2887 pending_clears);
2888
2889 if (image->surface.dcc_size)
2890 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
2891 dst_layout, src_queue_mask,
2892 dst_queue_mask, range,
2893 pending_clears);
2894 }
2895
2896 void radv_CmdPipelineBarrier(
2897 VkCommandBuffer commandBuffer,
2898 VkPipelineStageFlags srcStageMask,
2899 VkPipelineStageFlags destStageMask,
2900 VkBool32 byRegion,
2901 uint32_t memoryBarrierCount,
2902 const VkMemoryBarrier* pMemoryBarriers,
2903 uint32_t bufferMemoryBarrierCount,
2904 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
2905 uint32_t imageMemoryBarrierCount,
2906 const VkImageMemoryBarrier* pImageMemoryBarriers)
2907 {
2908 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2909 enum radv_cmd_flush_bits src_flush_bits = 0;
2910 enum radv_cmd_flush_bits dst_flush_bits = 0;
2911
2912 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
2913 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
2914 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
2915 NULL);
2916 }
2917
2918 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
2919 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
2920 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
2921 NULL);
2922 }
2923
2924 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2925 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
2926 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
2927 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
2928 image);
2929 }
2930
2931 cmd_buffer->state.flush_bits |= src_flush_bits;
2932
2933 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2934 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
2935 radv_handle_image_transition(cmd_buffer, image,
2936 pImageMemoryBarriers[i].oldLayout,
2937 pImageMemoryBarriers[i].newLayout,
2938 pImageMemoryBarriers[i].srcQueueFamilyIndex,
2939 pImageMemoryBarriers[i].dstQueueFamilyIndex,
2940 &pImageMemoryBarriers[i].subresourceRange,
2941 0);
2942 }
2943
2944 cmd_buffer->state.flush_bits |= dst_flush_bits;
2945
2946 /* TODO reduce this */
2947 enum radv_cmd_flush_bits flush_bits = RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2948 RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2949
2950 cmd_buffer->state.flush_bits |= flush_bits;
2951 }
2952
2953
2954 static void write_event(struct radv_cmd_buffer *cmd_buffer,
2955 struct radv_event *event,
2956 VkPipelineStageFlags stageMask,
2957 unsigned value)
2958 {
2959 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2960 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
2961
2962 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
2963
2964 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 12);
2965
2966 /* TODO: this is overkill. Probably should figure something out from
2967 * the stage mask. */
2968
2969 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK) {
2970 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
2971 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
2972 EVENT_INDEX(5));
2973 radeon_emit(cs, va);
2974 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
2975 radeon_emit(cs, 2);
2976 radeon_emit(cs, 0);
2977 }
2978
2979 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
2980 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
2981 EVENT_INDEX(5));
2982 radeon_emit(cs, va);
2983 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
2984 radeon_emit(cs, value);
2985 radeon_emit(cs, 0);
2986
2987 assert(cmd_buffer->cs->cdw <= cdw_max);
2988 }
2989
2990 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
2991 VkEvent _event,
2992 VkPipelineStageFlags stageMask)
2993 {
2994 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2995 RADV_FROM_HANDLE(radv_event, event, _event);
2996
2997 write_event(cmd_buffer, event, stageMask, 1);
2998 }
2999
3000 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3001 VkEvent _event,
3002 VkPipelineStageFlags stageMask)
3003 {
3004 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3005 RADV_FROM_HANDLE(radv_event, event, _event);
3006
3007 write_event(cmd_buffer, event, stageMask, 0);
3008 }
3009
3010 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3011 uint32_t eventCount,
3012 const VkEvent* pEvents,
3013 VkPipelineStageFlags srcStageMask,
3014 VkPipelineStageFlags dstStageMask,
3015 uint32_t memoryBarrierCount,
3016 const VkMemoryBarrier* pMemoryBarriers,
3017 uint32_t bufferMemoryBarrierCount,
3018 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3019 uint32_t imageMemoryBarrierCount,
3020 const VkImageMemoryBarrier* pImageMemoryBarriers)
3021 {
3022 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3023 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3024
3025 for (unsigned i = 0; i < eventCount; ++i) {
3026 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3027 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3028
3029 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3030
3031 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3032
3033 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
3034 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
3035 radeon_emit(cs, va);
3036 radeon_emit(cs, va >> 32);
3037 radeon_emit(cs, 1); /* reference value */
3038 radeon_emit(cs, 0xffffffff); /* mask */
3039 radeon_emit(cs, 4); /* poll interval */
3040
3041 assert(cmd_buffer->cs->cdw <= cdw_max);
3042 }
3043
3044
3045 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3046 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3047
3048 radv_handle_image_transition(cmd_buffer, image,
3049 pImageMemoryBarriers[i].oldLayout,
3050 pImageMemoryBarriers[i].newLayout,
3051 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3052 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3053 &pImageMemoryBarriers[i].subresourceRange,
3054 0);
3055 }
3056
3057 /* TODO: figure out how to do memory barriers without waiting */
3058 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3059 RADV_CMD_FLAG_INV_GLOBAL_L2 |
3060 RADV_CMD_FLAG_INV_VMEM_L1 |
3061 RADV_CMD_FLAG_INV_SMEM_L1;
3062 }