2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
33 #include "vk_format.h"
34 #include "radv_meta.h"
38 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
39 struct radv_image
*image
,
40 VkImageLayout src_layout
,
41 VkImageLayout dst_layout
,
44 const VkImageSubresourceRange
*range
,
45 VkImageAspectFlags pending_clears
);
47 const struct radv_dynamic_state default_dynamic_state
= {
60 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
65 .stencil_compare_mask
= {
69 .stencil_write_mask
= {
73 .stencil_reference
= {
80 radv_dynamic_state_copy(struct radv_dynamic_state
*dest
,
81 const struct radv_dynamic_state
*src
,
84 if (copy_mask
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
85 dest
->viewport
.count
= src
->viewport
.count
;
86 typed_memcpy(dest
->viewport
.viewports
, src
->viewport
.viewports
,
90 if (copy_mask
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
91 dest
->scissor
.count
= src
->scissor
.count
;
92 typed_memcpy(dest
->scissor
.scissors
, src
->scissor
.scissors
,
96 if (copy_mask
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
))
97 dest
->line_width
= src
->line_width
;
99 if (copy_mask
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
))
100 dest
->depth_bias
= src
->depth_bias
;
102 if (copy_mask
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
))
103 typed_memcpy(dest
->blend_constants
, src
->blend_constants
, 4);
105 if (copy_mask
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
))
106 dest
->depth_bounds
= src
->depth_bounds
;
108 if (copy_mask
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
))
109 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
111 if (copy_mask
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
))
112 dest
->stencil_write_mask
= src
->stencil_write_mask
;
114 if (copy_mask
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
))
115 dest
->stencil_reference
= src
->stencil_reference
;
118 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
)
120 return cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
121 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
;
124 enum ring_type
radv_queue_family_to_ring(int f
) {
126 case RADV_QUEUE_GENERAL
:
128 case RADV_QUEUE_COMPUTE
:
130 case RADV_QUEUE_TRANSFER
:
133 unreachable("Unknown queue family");
137 static VkResult
radv_create_cmd_buffer(
138 struct radv_device
* device
,
139 struct radv_cmd_pool
* pool
,
140 VkCommandBufferLevel level
,
141 VkCommandBuffer
* pCommandBuffer
)
143 struct radv_cmd_buffer
*cmd_buffer
;
146 cmd_buffer
= vk_alloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
147 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
148 if (cmd_buffer
== NULL
)
149 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
151 memset(cmd_buffer
, 0, sizeof(*cmd_buffer
));
152 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
153 cmd_buffer
->device
= device
;
154 cmd_buffer
->pool
= pool
;
155 cmd_buffer
->level
= level
;
158 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
159 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
162 /* Init the pool_link so we can safefly call list_del when we destroy
165 list_inithead(&cmd_buffer
->pool_link
);
166 cmd_buffer
->queue_family_index
= RADV_QUEUE_GENERAL
;
169 ring
= radv_queue_family_to_ring(cmd_buffer
->queue_family_index
);
171 cmd_buffer
->cs
= device
->ws
->cs_create(device
->ws
, ring
);
172 if (!cmd_buffer
->cs
) {
173 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
177 *pCommandBuffer
= radv_cmd_buffer_to_handle(cmd_buffer
);
179 cmd_buffer
->upload
.offset
= 0;
180 cmd_buffer
->upload
.size
= 0;
181 list_inithead(&cmd_buffer
->upload
.list
);
186 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
192 radv_cmd_buffer_destroy(struct radv_cmd_buffer
*cmd_buffer
)
194 list_del(&cmd_buffer
->pool_link
);
196 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
197 &cmd_buffer
->upload
.list
, list
) {
198 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
203 if (cmd_buffer
->upload
.upload_bo
)
204 cmd_buffer
->device
->ws
->buffer_destroy(cmd_buffer
->upload
.upload_bo
);
205 cmd_buffer
->device
->ws
->cs_destroy(cmd_buffer
->cs
);
206 free(cmd_buffer
->push_descriptors
.set
.mapped_ptr
);
207 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
210 static void radv_reset_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
)
213 cmd_buffer
->device
->ws
->cs_reset(cmd_buffer
->cs
);
215 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
216 &cmd_buffer
->upload
.list
, list
) {
217 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
222 cmd_buffer
->scratch_size_needed
= 0;
223 cmd_buffer
->compute_scratch_size_needed
= 0;
224 cmd_buffer
->esgs_ring_size_needed
= 0;
225 cmd_buffer
->gsvs_ring_size_needed
= 0;
226 cmd_buffer
->tess_rings_needed
= false;
227 cmd_buffer
->sample_positions_needed
= false;
229 if (cmd_buffer
->upload
.upload_bo
)
230 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
,
231 cmd_buffer
->upload
.upload_bo
, 8);
232 cmd_buffer
->upload
.offset
= 0;
234 cmd_buffer
->record_fail
= false;
236 cmd_buffer
->ring_offsets_idx
= -1;
238 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
240 radv_cmd_buffer_upload_alloc(cmd_buffer
, 8, 0,
241 &cmd_buffer
->gfx9_fence_offset
,
243 cmd_buffer
->gfx9_fence_bo
= cmd_buffer
->upload
.upload_bo
;
248 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer
*cmd_buffer
,
252 struct radeon_winsys_bo
*bo
;
253 struct radv_cmd_buffer_upload
*upload
;
254 struct radv_device
*device
= cmd_buffer
->device
;
256 new_size
= MAX2(min_needed
, 16 * 1024);
257 new_size
= MAX2(new_size
, 2 * cmd_buffer
->upload
.size
);
259 bo
= device
->ws
->buffer_create(device
->ws
,
262 RADEON_FLAG_CPU_ACCESS
);
265 cmd_buffer
->record_fail
= true;
269 device
->ws
->cs_add_buffer(cmd_buffer
->cs
, bo
, 8);
270 if (cmd_buffer
->upload
.upload_bo
) {
271 upload
= malloc(sizeof(*upload
));
274 cmd_buffer
->record_fail
= true;
275 device
->ws
->buffer_destroy(bo
);
279 memcpy(upload
, &cmd_buffer
->upload
, sizeof(*upload
));
280 list_add(&upload
->list
, &cmd_buffer
->upload
.list
);
283 cmd_buffer
->upload
.upload_bo
= bo
;
284 cmd_buffer
->upload
.size
= new_size
;
285 cmd_buffer
->upload
.offset
= 0;
286 cmd_buffer
->upload
.map
= device
->ws
->buffer_map(cmd_buffer
->upload
.upload_bo
);
288 if (!cmd_buffer
->upload
.map
) {
289 cmd_buffer
->record_fail
= true;
297 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
300 unsigned *out_offset
,
303 uint64_t offset
= align(cmd_buffer
->upload
.offset
, alignment
);
304 if (offset
+ size
> cmd_buffer
->upload
.size
) {
305 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer
, size
))
310 *out_offset
= offset
;
311 *ptr
= cmd_buffer
->upload
.map
+ offset
;
313 cmd_buffer
->upload
.offset
= offset
+ size
;
318 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
319 unsigned size
, unsigned alignment
,
320 const void *data
, unsigned *out_offset
)
324 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
, alignment
,
325 out_offset
, (void **)&ptr
))
329 memcpy(ptr
, data
, size
);
334 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
)
336 struct radv_device
*device
= cmd_buffer
->device
;
337 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
340 if (!device
->trace_bo
)
343 va
= device
->ws
->buffer_get_va(device
->trace_bo
);
345 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 7);
347 ++cmd_buffer
->state
.trace_id
;
348 device
->ws
->cs_add_buffer(cs
, device
->trace_bo
, 8);
349 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
350 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
351 S_370_WR_CONFIRM(1) |
352 S_370_ENGINE_SEL(V_370_ME
));
354 radeon_emit(cs
, va
>> 32);
355 radeon_emit(cs
, cmd_buffer
->state
.trace_id
);
356 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
357 radeon_emit(cs
, AC_ENCODE_TRACE_POINT(cmd_buffer
->state
.trace_id
));
361 radv_emit_graphics_blend_state(struct radv_cmd_buffer
*cmd_buffer
,
362 struct radv_pipeline
*pipeline
)
364 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028780_CB_BLEND0_CONTROL
, 8);
365 radeon_emit_array(cmd_buffer
->cs
, pipeline
->graphics
.blend
.cb_blend_control
,
367 radeon_set_context_reg(cmd_buffer
->cs
, R_028808_CB_COLOR_CONTROL
, pipeline
->graphics
.blend
.cb_color_control
);
368 radeon_set_context_reg(cmd_buffer
->cs
, R_028B70_DB_ALPHA_TO_MASK
, pipeline
->graphics
.blend
.db_alpha_to_mask
);
370 if (cmd_buffer
->device
->physical_device
->has_rbplus
) {
371 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
372 radeon_emit(cmd_buffer
->cs
, 0); /* R_028754_SX_PS_DOWNCONVERT */
373 radeon_emit(cmd_buffer
->cs
, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
374 radeon_emit(cmd_buffer
->cs
, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
379 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer
*cmd_buffer
,
380 struct radv_pipeline
*pipeline
)
382 struct radv_depth_stencil_state
*ds
= &pipeline
->graphics
.ds
;
383 radeon_set_context_reg(cmd_buffer
->cs
, R_028800_DB_DEPTH_CONTROL
, ds
->db_depth_control
);
384 radeon_set_context_reg(cmd_buffer
->cs
, R_02842C_DB_STENCIL_CONTROL
, ds
->db_stencil_control
);
386 radeon_set_context_reg(cmd_buffer
->cs
, R_028000_DB_RENDER_CONTROL
, ds
->db_render_control
);
387 radeon_set_context_reg(cmd_buffer
->cs
, R_028010_DB_RENDER_OVERRIDE2
, ds
->db_render_override2
);
390 /* 12.4 fixed-point */
391 static unsigned radv_pack_float_12p4(float x
)
394 x
>= 4096 ? 0xffff : x
* 16;
398 shader_stage_to_user_data_0(gl_shader_stage stage
, bool has_gs
, bool has_tess
)
401 case MESA_SHADER_FRAGMENT
:
402 return R_00B030_SPI_SHADER_USER_DATA_PS_0
;
403 case MESA_SHADER_VERTEX
:
405 return R_00B530_SPI_SHADER_USER_DATA_LS_0
;
407 return has_gs
? R_00B330_SPI_SHADER_USER_DATA_ES_0
: R_00B130_SPI_SHADER_USER_DATA_VS_0
;
408 case MESA_SHADER_GEOMETRY
:
409 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
410 case MESA_SHADER_COMPUTE
:
411 return R_00B900_COMPUTE_USER_DATA_0
;
412 case MESA_SHADER_TESS_CTRL
:
413 return R_00B430_SPI_SHADER_USER_DATA_HS_0
;
414 case MESA_SHADER_TESS_EVAL
:
416 return R_00B330_SPI_SHADER_USER_DATA_ES_0
;
418 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
420 unreachable("unknown shader");
424 static struct ac_userdata_info
*
425 radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
426 gl_shader_stage stage
,
429 return &pipeline
->shaders
[stage
]->info
.user_sgprs_locs
.shader_data
[idx
];
433 radv_emit_userdata_address(struct radv_cmd_buffer
*cmd_buffer
,
434 struct radv_pipeline
*pipeline
,
435 gl_shader_stage stage
,
436 int idx
, uint64_t va
)
438 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
439 uint32_t base_reg
= shader_stage_to_user_data_0(stage
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
440 if (loc
->sgpr_idx
== -1)
442 assert(loc
->num_sgprs
== 2);
443 assert(!loc
->indirect
);
444 radeon_set_sh_reg_seq(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, 2);
445 radeon_emit(cmd_buffer
->cs
, va
);
446 radeon_emit(cmd_buffer
->cs
, va
>> 32);
450 radv_update_multisample_state(struct radv_cmd_buffer
*cmd_buffer
,
451 struct radv_pipeline
*pipeline
)
453 int num_samples
= pipeline
->graphics
.ms
.num_samples
;
454 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
455 struct radv_pipeline
*old_pipeline
= cmd_buffer
->state
.emitted_pipeline
;
457 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
458 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_mask
[0]);
459 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_mask
[1]);
461 radeon_set_context_reg(cmd_buffer
->cs
, CM_R_028804_DB_EQAA
, ms
->db_eqaa
);
462 radeon_set_context_reg(cmd_buffer
->cs
, EG_R_028A4C_PA_SC_MODE_CNTL_1
, ms
->pa_sc_mode_cntl_1
);
464 if (old_pipeline
&& num_samples
== old_pipeline
->graphics
.ms
.num_samples
)
467 radeon_set_context_reg_seq(cmd_buffer
->cs
, CM_R_028BDC_PA_SC_LINE_CNTL
, 2);
468 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_line_cntl
);
469 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_config
);
471 radv_cayman_emit_msaa_sample_locs(cmd_buffer
->cs
, num_samples
);
473 /* GFX9: Flush DFSM when the AA mode changes. */
474 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
475 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
476 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
478 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.needs_sample_positions
) {
480 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_FRAGMENT
, AC_UD_PS_SAMPLE_POS_OFFSET
);
481 uint32_t base_reg
= shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
482 if (loc
->sgpr_idx
== -1)
484 assert(loc
->num_sgprs
== 1);
485 assert(!loc
->indirect
);
486 switch (num_samples
) {
504 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, offset
);
505 cmd_buffer
->sample_positions_needed
= true;
510 radv_emit_graphics_raster_state(struct radv_cmd_buffer
*cmd_buffer
,
511 struct radv_pipeline
*pipeline
)
513 struct radv_raster_state
*raster
= &pipeline
->graphics
.raster
;
515 radeon_set_context_reg(cmd_buffer
->cs
, R_028810_PA_CL_CLIP_CNTL
,
516 raster
->pa_cl_clip_cntl
);
518 radeon_set_context_reg(cmd_buffer
->cs
, R_0286D4_SPI_INTERP_CONTROL_0
,
519 raster
->spi_interp_control
);
521 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028A00_PA_SU_POINT_SIZE
, 2);
522 unsigned tmp
= (unsigned)(1.0 * 8.0);
523 radeon_emit(cmd_buffer
->cs
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
524 radeon_emit(cmd_buffer
->cs
, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
525 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
527 radeon_set_context_reg(cmd_buffer
->cs
, R_028BE4_PA_SU_VTX_CNTL
,
528 raster
->pa_su_vtx_cntl
);
530 radeon_set_context_reg(cmd_buffer
->cs
, R_028814_PA_SU_SC_MODE_CNTL
,
531 raster
->pa_su_sc_mode_cntl
);
535 radv_emit_hw_vs(struct radv_cmd_buffer
*cmd_buffer
,
536 struct radv_pipeline
*pipeline
,
537 struct radv_shader_variant
*shader
,
538 struct ac_vs_output_info
*outinfo
)
540 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
541 uint64_t va
= ws
->buffer_get_va(shader
->bo
);
542 unsigned export_count
;
544 ws
->cs_add_buffer(cmd_buffer
->cs
, shader
->bo
, 8);
545 si_cp_dma_prefetch(cmd_buffer
, va
, shader
->code_size
);
547 export_count
= MAX2(1, outinfo
->param_exports
);
548 radeon_set_context_reg(cmd_buffer
->cs
, R_0286C4_SPI_VS_OUT_CONFIG
,
549 S_0286C4_VS_EXPORT_COUNT(export_count
- 1));
551 radeon_set_context_reg(cmd_buffer
->cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
552 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
553 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
554 V_02870C_SPI_SHADER_4COMP
:
555 V_02870C_SPI_SHADER_NONE
) |
556 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
557 V_02870C_SPI_SHADER_4COMP
:
558 V_02870C_SPI_SHADER_NONE
) |
559 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
560 V_02870C_SPI_SHADER_4COMP
:
561 V_02870C_SPI_SHADER_NONE
));
564 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B120_SPI_SHADER_PGM_LO_VS
, 4);
565 radeon_emit(cmd_buffer
->cs
, va
>> 8);
566 radeon_emit(cmd_buffer
->cs
, va
>> 40);
567 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
568 radeon_emit(cmd_buffer
->cs
, shader
->rsrc2
);
570 radeon_set_context_reg(cmd_buffer
->cs
, R_028818_PA_CL_VTE_CNTL
,
571 S_028818_VTX_W0_FMT(1) |
572 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
573 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
574 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
577 radeon_set_context_reg(cmd_buffer
->cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
578 pipeline
->graphics
.pa_cl_vs_out_cntl
);
580 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
<= VI
)
581 radeon_set_context_reg(cmd_buffer
->cs
, R_028AB4_VGT_REUSE_OFF
,
582 S_028AB4_REUSE_OFF(outinfo
->writes_viewport_index
));
586 radv_emit_hw_es(struct radv_cmd_buffer
*cmd_buffer
,
587 struct radv_shader_variant
*shader
,
588 struct ac_es_output_info
*outinfo
)
590 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
591 uint64_t va
= ws
->buffer_get_va(shader
->bo
);
593 ws
->cs_add_buffer(cmd_buffer
->cs
, shader
->bo
, 8);
594 si_cp_dma_prefetch(cmd_buffer
, va
, shader
->code_size
);
596 radeon_set_context_reg(cmd_buffer
->cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
597 outinfo
->esgs_itemsize
/ 4);
598 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 4);
599 radeon_emit(cmd_buffer
->cs
, va
>> 8);
600 radeon_emit(cmd_buffer
->cs
, va
>> 40);
601 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
602 radeon_emit(cmd_buffer
->cs
, shader
->rsrc2
);
606 radv_emit_hw_ls(struct radv_cmd_buffer
*cmd_buffer
,
607 struct radv_shader_variant
*shader
)
609 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
610 uint64_t va
= ws
->buffer_get_va(shader
->bo
);
611 uint32_t rsrc2
= shader
->rsrc2
;
613 ws
->cs_add_buffer(cmd_buffer
->cs
, shader
->bo
, 8);
614 si_cp_dma_prefetch(cmd_buffer
, va
, shader
->code_size
);
616 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
617 radeon_emit(cmd_buffer
->cs
, va
>> 8);
618 radeon_emit(cmd_buffer
->cs
, va
>> 40);
620 rsrc2
|= S_00B52C_LDS_SIZE(cmd_buffer
->state
.pipeline
->graphics
.tess
.lds_size
);
621 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== CIK
&&
622 cmd_buffer
->device
->physical_device
->rad_info
.family
!= CHIP_HAWAII
)
623 radeon_set_sh_reg(cmd_buffer
->cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, rsrc2
);
625 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
626 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
627 radeon_emit(cmd_buffer
->cs
, rsrc2
);
631 radv_emit_hw_hs(struct radv_cmd_buffer
*cmd_buffer
,
632 struct radv_shader_variant
*shader
)
634 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
635 uint64_t va
= ws
->buffer_get_va(shader
->bo
);
637 ws
->cs_add_buffer(cmd_buffer
->cs
, shader
->bo
, 8);
638 si_cp_dma_prefetch(cmd_buffer
, va
, shader
->code_size
);
640 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B420_SPI_SHADER_PGM_LO_HS
, 4);
641 radeon_emit(cmd_buffer
->cs
, va
>> 8);
642 radeon_emit(cmd_buffer
->cs
, va
>> 40);
643 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
644 radeon_emit(cmd_buffer
->cs
, shader
->rsrc2
);
648 radv_emit_vertex_shader(struct radv_cmd_buffer
*cmd_buffer
,
649 struct radv_pipeline
*pipeline
)
651 struct radv_shader_variant
*vs
;
653 assert (pipeline
->shaders
[MESA_SHADER_VERTEX
]);
655 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
657 if (vs
->info
.vs
.as_ls
)
658 radv_emit_hw_ls(cmd_buffer
, vs
);
659 else if (vs
->info
.vs
.as_es
)
660 radv_emit_hw_es(cmd_buffer
, vs
, &vs
->info
.vs
.es_info
);
662 radv_emit_hw_vs(cmd_buffer
, pipeline
, vs
, &vs
->info
.vs
.outinfo
);
664 radeon_set_context_reg(cmd_buffer
->cs
, R_028A84_VGT_PRIMITIVEID_EN
, 0);
669 radv_emit_tess_shaders(struct radv_cmd_buffer
*cmd_buffer
,
670 struct radv_pipeline
*pipeline
)
672 if (!radv_pipeline_has_tess(pipeline
))
675 struct radv_shader_variant
*tes
, *tcs
;
677 tcs
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
678 tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
680 if (tes
->info
.tes
.as_es
)
681 radv_emit_hw_es(cmd_buffer
, tes
, &tes
->info
.tes
.es_info
);
683 radv_emit_hw_vs(cmd_buffer
, pipeline
, tes
, &tes
->info
.tes
.outinfo
);
685 radv_emit_hw_hs(cmd_buffer
, tcs
);
687 radeon_set_context_reg(cmd_buffer
->cs
, R_028B6C_VGT_TF_PARAM
,
688 pipeline
->graphics
.tess
.tf_param
);
690 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
)
691 radeon_set_context_reg_idx(cmd_buffer
->cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
692 pipeline
->graphics
.tess
.ls_hs_config
);
694 radeon_set_context_reg(cmd_buffer
->cs
, R_028B58_VGT_LS_HS_CONFIG
,
695 pipeline
->graphics
.tess
.ls_hs_config
);
697 struct ac_userdata_info
*loc
;
699 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_TESS_CTRL
, AC_UD_TCS_OFFCHIP_LAYOUT
);
700 if (loc
->sgpr_idx
!= -1) {
701 uint32_t base_reg
= shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
702 assert(loc
->num_sgprs
== 4);
703 assert(!loc
->indirect
);
704 radeon_set_sh_reg_seq(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, 4);
705 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.offchip_layout
);
706 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.tcs_out_offsets
);
707 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.tcs_out_layout
|
708 pipeline
->graphics
.tess
.num_tcs_input_cp
<< 26);
709 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.tcs_in_layout
);
712 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_TESS_EVAL
, AC_UD_TES_OFFCHIP_LAYOUT
);
713 if (loc
->sgpr_idx
!= -1) {
714 uint32_t base_reg
= shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
715 assert(loc
->num_sgprs
== 1);
716 assert(!loc
->indirect
);
718 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4,
719 pipeline
->graphics
.tess
.offchip_layout
);
722 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
, AC_UD_VS_LS_TCS_IN_LAYOUT
);
723 if (loc
->sgpr_idx
!= -1) {
724 uint32_t base_reg
= shader_stage_to_user_data_0(MESA_SHADER_VERTEX
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
725 assert(loc
->num_sgprs
== 1);
726 assert(!loc
->indirect
);
728 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4,
729 pipeline
->graphics
.tess
.tcs_in_layout
);
734 radv_emit_geometry_shader(struct radv_cmd_buffer
*cmd_buffer
,
735 struct radv_pipeline
*pipeline
)
737 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
738 struct radv_shader_variant
*gs
;
741 radeon_set_context_reg(cmd_buffer
->cs
, R_028A40_VGT_GS_MODE
, pipeline
->graphics
.vgt_gs_mode
);
743 gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
747 uint32_t gsvs_itemsize
= gs
->info
.gs
.max_gsvs_emit_size
>> 2;
749 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028A60_VGT_GSVS_RING_OFFSET_1
, 3);
750 radeon_emit(cmd_buffer
->cs
, gsvs_itemsize
);
751 radeon_emit(cmd_buffer
->cs
, gsvs_itemsize
);
752 radeon_emit(cmd_buffer
->cs
, gsvs_itemsize
);
754 radeon_set_context_reg(cmd_buffer
->cs
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, gsvs_itemsize
);
756 radeon_set_context_reg(cmd_buffer
->cs
, R_028B38_VGT_GS_MAX_VERT_OUT
, gs
->info
.gs
.vertices_out
);
758 uint32_t gs_vert_itemsize
= gs
->info
.gs
.gsvs_vertex_size
;
759 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, 4);
760 radeon_emit(cmd_buffer
->cs
, gs_vert_itemsize
>> 2);
761 radeon_emit(cmd_buffer
->cs
, 0);
762 radeon_emit(cmd_buffer
->cs
, 0);
763 radeon_emit(cmd_buffer
->cs
, 0);
765 uint32_t gs_num_invocations
= gs
->info
.gs
.invocations
;
766 radeon_set_context_reg(cmd_buffer
->cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
767 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
768 S_028B90_ENABLE(gs_num_invocations
> 0));
770 va
= ws
->buffer_get_va(gs
->bo
);
771 ws
->cs_add_buffer(cmd_buffer
->cs
, gs
->bo
, 8);
772 si_cp_dma_prefetch(cmd_buffer
, va
, gs
->code_size
);
773 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B220_SPI_SHADER_PGM_LO_GS
, 4);
774 radeon_emit(cmd_buffer
->cs
, va
>> 8);
775 radeon_emit(cmd_buffer
->cs
, va
>> 40);
776 radeon_emit(cmd_buffer
->cs
, gs
->rsrc1
);
777 radeon_emit(cmd_buffer
->cs
, gs
->rsrc2
);
779 radv_emit_hw_vs(cmd_buffer
, pipeline
, pipeline
->gs_copy_shader
, &pipeline
->gs_copy_shader
->info
.vs
.outinfo
);
781 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
782 AC_UD_GS_VS_RING_STRIDE_ENTRIES
);
783 if (loc
->sgpr_idx
!= -1) {
784 uint32_t stride
= gs
->info
.gs
.max_gsvs_emit_size
;
785 uint32_t num_entries
= 64;
786 bool is_vi
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= VI
;
789 num_entries
*= stride
;
791 stride
= S_008F04_STRIDE(stride
);
792 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B230_SPI_SHADER_USER_DATA_GS_0
+ loc
->sgpr_idx
* 4, 2);
793 radeon_emit(cmd_buffer
->cs
, stride
);
794 radeon_emit(cmd_buffer
->cs
, num_entries
);
799 radv_emit_fragment_shader(struct radv_cmd_buffer
*cmd_buffer
,
800 struct radv_pipeline
*pipeline
)
802 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
803 struct radv_shader_variant
*ps
;
805 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
806 struct radv_blend_state
*blend
= &pipeline
->graphics
.blend
;
807 assert (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
809 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
811 va
= ws
->buffer_get_va(ps
->bo
);
812 ws
->cs_add_buffer(cmd_buffer
->cs
, ps
->bo
, 8);
813 si_cp_dma_prefetch(cmd_buffer
, va
, ps
->code_size
);
815 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B020_SPI_SHADER_PGM_LO_PS
, 4);
816 radeon_emit(cmd_buffer
->cs
, va
>> 8);
817 radeon_emit(cmd_buffer
->cs
, va
>> 40);
818 radeon_emit(cmd_buffer
->cs
, ps
->rsrc1
);
819 radeon_emit(cmd_buffer
->cs
, ps
->rsrc2
);
821 radeon_set_context_reg(cmd_buffer
->cs
, R_02880C_DB_SHADER_CONTROL
,
822 pipeline
->graphics
.db_shader_control
);
824 radeon_set_context_reg(cmd_buffer
->cs
, R_0286CC_SPI_PS_INPUT_ENA
,
825 ps
->config
.spi_ps_input_ena
);
827 radeon_set_context_reg(cmd_buffer
->cs
, R_0286D0_SPI_PS_INPUT_ADDR
,
828 ps
->config
.spi_ps_input_addr
);
830 if (ps
->info
.fs
.force_persample
)
831 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
833 radeon_set_context_reg(cmd_buffer
->cs
, R_0286D8_SPI_PS_IN_CONTROL
,
834 S_0286D8_NUM_INTERP(ps
->info
.fs
.num_interp
));
836 radeon_set_context_reg(cmd_buffer
->cs
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
838 radeon_set_context_reg(cmd_buffer
->cs
, R_028710_SPI_SHADER_Z_FORMAT
,
839 pipeline
->graphics
.shader_z_format
);
841 radeon_set_context_reg(cmd_buffer
->cs
, R_028714_SPI_SHADER_COL_FORMAT
, blend
->spi_shader_col_format
);
843 radeon_set_context_reg(cmd_buffer
->cs
, R_028238_CB_TARGET_MASK
, blend
->cb_target_mask
);
844 radeon_set_context_reg(cmd_buffer
->cs
, R_02823C_CB_SHADER_MASK
, blend
->cb_shader_mask
);
846 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
848 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
849 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
852 if (pipeline
->graphics
.ps_input_cntl_num
) {
853 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028644_SPI_PS_INPUT_CNTL_0
, pipeline
->graphics
.ps_input_cntl_num
);
854 for (unsigned i
= 0; i
< pipeline
->graphics
.ps_input_cntl_num
; i
++) {
855 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.ps_input_cntl
[i
]);
860 static void polaris_set_vgt_vertex_reuse(struct radv_cmd_buffer
*cmd_buffer
,
861 struct radv_pipeline
*pipeline
)
863 uint32_t vtx_reuse_depth
= 30;
864 if (cmd_buffer
->device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
)
867 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]) {
868 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.spacing
== TESS_SPACING_FRACTIONAL_ODD
)
869 vtx_reuse_depth
= 14;
871 radeon_set_context_reg(cmd_buffer
->cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
876 radv_emit_graphics_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
877 struct radv_pipeline
*pipeline
)
879 if (!pipeline
|| cmd_buffer
->state
.emitted_pipeline
== pipeline
)
882 radv_emit_graphics_depth_stencil_state(cmd_buffer
, pipeline
);
883 radv_emit_graphics_blend_state(cmd_buffer
, pipeline
);
884 radv_emit_graphics_raster_state(cmd_buffer
, pipeline
);
885 radv_update_multisample_state(cmd_buffer
, pipeline
);
886 radv_emit_vertex_shader(cmd_buffer
, pipeline
);
887 radv_emit_tess_shaders(cmd_buffer
, pipeline
);
888 radv_emit_geometry_shader(cmd_buffer
, pipeline
);
889 radv_emit_fragment_shader(cmd_buffer
, pipeline
);
890 polaris_set_vgt_vertex_reuse(cmd_buffer
, pipeline
);
892 cmd_buffer
->scratch_size_needed
=
893 MAX2(cmd_buffer
->scratch_size_needed
,
894 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
896 radeon_set_context_reg(cmd_buffer
->cs
, R_0286E8_SPI_TMPRING_SIZE
,
897 S_0286E8_WAVES(pipeline
->max_waves
) |
898 S_0286E8_WAVESIZE(pipeline
->scratch_bytes_per_wave
>> 10));
900 if (!cmd_buffer
->state
.emitted_pipeline
||
901 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
!=
902 pipeline
->graphics
.can_use_guardband
)
903 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
904 cmd_buffer
->state
.emitted_pipeline
= pipeline
;
908 radv_emit_viewport(struct radv_cmd_buffer
*cmd_buffer
)
910 si_write_viewport(cmd_buffer
->cs
, 0, cmd_buffer
->state
.dynamic
.viewport
.count
,
911 cmd_buffer
->state
.dynamic
.viewport
.viewports
);
915 radv_emit_scissor(struct radv_cmd_buffer
*cmd_buffer
)
917 uint32_t count
= cmd_buffer
->state
.dynamic
.scissor
.count
;
918 si_write_scissors(cmd_buffer
->cs
, 0, count
,
919 cmd_buffer
->state
.dynamic
.scissor
.scissors
,
920 cmd_buffer
->state
.dynamic
.viewport
.viewports
,
921 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
);
922 radeon_set_context_reg(cmd_buffer
->cs
, R_028A48_PA_SC_MODE_CNTL_0
,
923 cmd_buffer
->state
.pipeline
->graphics
.ms
.pa_sc_mode_cntl_0
| S_028A48_VPORT_SCISSOR_ENABLE(count
? 1 : 0));
927 radv_emit_fb_color_state(struct radv_cmd_buffer
*cmd_buffer
,
929 struct radv_color_buffer_info
*cb
)
931 bool is_vi
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= VI
;
933 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
934 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
935 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
936 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
>> 32);
937 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib2
);
938 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
939 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_info
);
940 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
941 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
942 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
943 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
>> 32);
944 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
945 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
>> 32);
947 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, 2);
948 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
);
949 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
>> 32);
951 radeon_set_context_reg(cmd_buffer
->cs
, R_0287A0_CB_MRT0_EPITCH
+ index
* 4,
954 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
955 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
956 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_pitch
);
957 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_slice
);
958 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
959 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_info
);
960 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
961 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
962 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
963 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask_slice
);
964 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
965 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask_slice
);
967 if (is_vi
) { /* DCC BASE */
968 radeon_set_context_reg(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, cb
->cb_dcc_base
);
974 radv_emit_fb_ds_state(struct radv_cmd_buffer
*cmd_buffer
,
975 struct radv_ds_buffer_info
*ds
,
976 struct radv_image
*image
,
977 VkImageLayout layout
)
979 uint32_t db_z_info
= ds
->db_z_info
;
980 uint32_t db_stencil_info
= ds
->db_stencil_info
;
982 if (!radv_layout_has_htile(image
, layout
,
983 radv_image_queue_family_mask(image
,
984 cmd_buffer
->queue_family_index
,
985 cmd_buffer
->queue_family_index
))) {
986 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
987 db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
990 radeon_set_context_reg(cmd_buffer
->cs
, R_028008_DB_DEPTH_VIEW
, ds
->db_depth_view
);
992 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
993 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
994 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
);
995 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
>> 32);
996 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
);
998 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 10);
999 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* DB_Z_INFO */
1000 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* DB_STENCIL_INFO */
1001 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* DB_Z_READ_BASE */
1002 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
>> 32); /* DB_Z_READ_BASE_HI */
1003 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* DB_STENCIL_READ_BASE */
1004 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
>> 32); /* DB_STENCIL_READ_BASE_HI */
1005 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* DB_Z_WRITE_BASE */
1006 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
>> 32); /* DB_Z_WRITE_BASE_HI */
1007 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* DB_STENCIL_WRITE_BASE */
1008 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
>> 32); /* DB_STENCIL_WRITE_BASE_HI */
1010 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028068_DB_Z_INFO2
, 2);
1011 radeon_emit(cmd_buffer
->cs
, ds
->db_z_info2
);
1012 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_info2
);
1014 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
1016 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 9);
1017 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_info
); /* R_02803C_DB_DEPTH_INFO */
1018 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* R_028040_DB_Z_INFO */
1019 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
1020 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* R_028048_DB_Z_READ_BASE */
1021 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* R_02804C_DB_STENCIL_READ_BASE */
1022 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* R_028050_DB_Z_WRITE_BASE */
1023 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
1024 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
1025 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
1027 radeon_set_context_reg(cmd_buffer
->cs
, R_028ABC_DB_HTILE_SURFACE
, ds
->db_htile_surface
);
1030 radeon_set_context_reg(cmd_buffer
->cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1031 ds
->pa_su_poly_offset_db_fmt_cntl
);
1035 radv_set_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1036 struct radv_image
*image
,
1037 VkClearDepthStencilValue ds_clear_value
,
1038 VkImageAspectFlags aspects
)
1040 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(image
->bo
);
1041 va
+= image
->offset
+ image
->clear_value_offset
;
1042 unsigned reg_offset
= 0, reg_count
= 0;
1044 if (!image
->surface
.htile_size
|| !aspects
)
1047 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1053 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1056 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
1058 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 2 + reg_count
, 0));
1059 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1060 S_370_WR_CONFIRM(1) |
1061 S_370_ENGINE_SEL(V_370_PFP
));
1062 radeon_emit(cmd_buffer
->cs
, va
);
1063 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1064 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)
1065 radeon_emit(cmd_buffer
->cs
, ds_clear_value
.stencil
);
1066 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1067 radeon_emit(cmd_buffer
->cs
, fui(ds_clear_value
.depth
));
1069 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028028_DB_STENCIL_CLEAR
+ 4 * reg_offset
, reg_count
);
1070 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)
1071 radeon_emit(cmd_buffer
->cs
, ds_clear_value
.stencil
); /* R_028028_DB_STENCIL_CLEAR */
1072 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1073 radeon_emit(cmd_buffer
->cs
, fui(ds_clear_value
.depth
)); /* R_02802C_DB_DEPTH_CLEAR */
1077 radv_load_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1078 struct radv_image
*image
)
1080 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(image
->bo
);
1081 va
+= image
->offset
+ image
->clear_value_offset
;
1083 if (!image
->surface
.htile_size
)
1086 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
1088 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
1089 radeon_emit(cmd_buffer
->cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
1090 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1091 COPY_DATA_COUNT_SEL
);
1092 radeon_emit(cmd_buffer
->cs
, va
);
1093 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1094 radeon_emit(cmd_buffer
->cs
, R_028028_DB_STENCIL_CLEAR
>> 2);
1095 radeon_emit(cmd_buffer
->cs
, 0);
1097 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1098 radeon_emit(cmd_buffer
->cs
, 0);
1102 radv_set_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1103 struct radv_image
*image
,
1105 uint32_t color_values
[2])
1107 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(image
->bo
);
1108 va
+= image
->offset
+ image
->clear_value_offset
;
1110 if (!image
->cmask
.size
&& !image
->surface
.dcc_size
)
1113 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
1115 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1116 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1117 S_370_WR_CONFIRM(1) |
1118 S_370_ENGINE_SEL(V_370_PFP
));
1119 radeon_emit(cmd_buffer
->cs
, va
);
1120 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1121 radeon_emit(cmd_buffer
->cs
, color_values
[0]);
1122 radeon_emit(cmd_buffer
->cs
, color_values
[1]);
1124 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C8C_CB_COLOR0_CLEAR_WORD0
+ idx
* 0x3c, 2);
1125 radeon_emit(cmd_buffer
->cs
, color_values
[0]);
1126 radeon_emit(cmd_buffer
->cs
, color_values
[1]);
1130 radv_load_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1131 struct radv_image
*image
,
1134 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(image
->bo
);
1135 va
+= image
->offset
+ image
->clear_value_offset
;
1137 if (!image
->cmask
.size
&& !image
->surface
.dcc_size
)
1140 uint32_t reg
= R_028C8C_CB_COLOR0_CLEAR_WORD0
+ idx
* 0x3c;
1141 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
1143 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
1144 radeon_emit(cmd_buffer
->cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
1145 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1146 COPY_DATA_COUNT_SEL
);
1147 radeon_emit(cmd_buffer
->cs
, va
);
1148 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1149 radeon_emit(cmd_buffer
->cs
, reg
>> 2);
1150 radeon_emit(cmd_buffer
->cs
, 0);
1152 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1153 radeon_emit(cmd_buffer
->cs
, 0);
1157 radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer
)
1160 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1161 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1163 for (i
= 0; i
< subpass
->color_count
; ++i
) {
1164 int idx
= subpass
->color_attachments
[i
].attachment
;
1165 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1167 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, att
->attachment
->bo
, 8);
1169 assert(att
->attachment
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
);
1170 radv_emit_fb_color_state(cmd_buffer
, i
, &att
->cb
);
1172 radv_load_color_clear_regs(cmd_buffer
, att
->attachment
->image
, i
);
1175 for (i
= subpass
->color_count
; i
< 8; i
++)
1176 radeon_set_context_reg(cmd_buffer
->cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
1177 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
1179 if(subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1180 int idx
= subpass
->depth_stencil_attachment
.attachment
;
1181 VkImageLayout layout
= subpass
->depth_stencil_attachment
.layout
;
1182 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1183 struct radv_image
*image
= att
->attachment
->image
;
1184 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, att
->attachment
->bo
, 8);
1185 uint32_t queue_mask
= radv_image_queue_family_mask(image
,
1186 cmd_buffer
->queue_family_index
,
1187 cmd_buffer
->queue_family_index
);
1188 /* We currently don't support writing decompressed HTILE */
1189 assert(radv_layout_has_htile(image
, layout
, queue_mask
) ==
1190 radv_layout_is_htile_compressed(image
, layout
, queue_mask
));
1192 radv_emit_fb_ds_state(cmd_buffer
, &att
->ds
, image
, layout
);
1194 if (att
->ds
.offset_scale
!= cmd_buffer
->state
.offset_scale
) {
1195 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
1196 cmd_buffer
->state
.offset_scale
= att
->ds
.offset_scale
;
1198 radv_load_depth_clear_regs(cmd_buffer
, image
);
1200 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028040_DB_Z_INFO
, 2);
1201 radeon_emit(cmd_buffer
->cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* R_028040_DB_Z_INFO */
1202 radeon_emit(cmd_buffer
->cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* R_028044_DB_STENCIL_INFO */
1204 radeon_set_context_reg(cmd_buffer
->cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
1205 S_028208_BR_X(framebuffer
->width
) |
1206 S_028208_BR_Y(framebuffer
->height
));
1208 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1209 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1210 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
1214 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
)
1216 uint32_t db_count_control
;
1218 if(!cmd_buffer
->state
.active_occlusion_queries
) {
1219 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1220 db_count_control
= 0;
1222 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
1225 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1226 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
1227 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1228 S_028004_ZPASS_ENABLE(1) |
1229 S_028004_SLICE_EVEN_ENABLE(1) |
1230 S_028004_SLICE_ODD_ENABLE(1);
1232 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
1233 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1237 radeon_set_context_reg(cmd_buffer
->cs
, R_028004_DB_COUNT_CONTROL
, db_count_control
);
1241 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
)
1243 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1245 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer
->state
.pipeline
->graphics
.raster
.pa_cl_clip_cntl
))
1248 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
1249 radv_emit_viewport(cmd_buffer
);
1251 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_DYNAMIC_SCISSOR
| RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
1252 radv_emit_scissor(cmd_buffer
);
1254 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
) {
1255 unsigned width
= cmd_buffer
->state
.dynamic
.line_width
* 8;
1256 radeon_set_context_reg(cmd_buffer
->cs
, R_028A08_PA_SU_LINE_CNTL
,
1257 S_028A08_WIDTH(CLAMP(width
, 0, 0xFFF)));
1260 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
) {
1261 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028414_CB_BLEND_RED
, 4);
1262 radeon_emit_array(cmd_buffer
->cs
, (uint32_t*)d
->blend_constants
, 4);
1265 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
|
1266 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
|
1267 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
)) {
1268 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028430_DB_STENCILREFMASK
, 2);
1269 radeon_emit(cmd_buffer
->cs
, S_028430_STENCILTESTVAL(d
->stencil_reference
.front
) |
1270 S_028430_STENCILMASK(d
->stencil_compare_mask
.front
) |
1271 S_028430_STENCILWRITEMASK(d
->stencil_write_mask
.front
) |
1272 S_028430_STENCILOPVAL(1));
1273 radeon_emit(cmd_buffer
->cs
, S_028434_STENCILTESTVAL_BF(d
->stencil_reference
.back
) |
1274 S_028434_STENCILMASK_BF(d
->stencil_compare_mask
.back
) |
1275 S_028434_STENCILWRITEMASK_BF(d
->stencil_write_mask
.back
) |
1276 S_028434_STENCILOPVAL_BF(1));
1279 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_PIPELINE
|
1280 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
)) {
1281 radeon_set_context_reg(cmd_buffer
->cs
, R_028020_DB_DEPTH_BOUNDS_MIN
, fui(d
->depth_bounds
.min
));
1282 radeon_set_context_reg(cmd_buffer
->cs
, R_028024_DB_DEPTH_BOUNDS_MAX
, fui(d
->depth_bounds
.max
));
1285 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_PIPELINE
|
1286 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
)) {
1287 struct radv_raster_state
*raster
= &cmd_buffer
->state
.pipeline
->graphics
.raster
;
1288 unsigned slope
= fui(d
->depth_bias
.slope
* 16.0f
);
1289 unsigned bias
= fui(d
->depth_bias
.bias
* cmd_buffer
->state
.offset_scale
);
1291 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster
->pa_su_sc_mode_cntl
)) {
1292 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, 5);
1293 radeon_emit(cmd_buffer
->cs
, fui(d
->depth_bias
.clamp
)); /* CLAMP */
1294 radeon_emit(cmd_buffer
->cs
, slope
); /* FRONT SCALE */
1295 radeon_emit(cmd_buffer
->cs
, bias
); /* FRONT OFFSET */
1296 radeon_emit(cmd_buffer
->cs
, slope
); /* BACK SCALE */
1297 radeon_emit(cmd_buffer
->cs
, bias
); /* BACK OFFSET */
1301 cmd_buffer
->state
.dirty
= 0;
1305 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer
*cmd_buffer
,
1306 struct radv_pipeline
*pipeline
,
1309 gl_shader_stage stage
)
1311 struct ac_userdata_info
*desc_set_loc
= &pipeline
->shaders
[stage
]->info
.user_sgprs_locs
.descriptor_sets
[idx
];
1312 uint32_t base_reg
= shader_stage_to_user_data_0(stage
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
1314 if (desc_set_loc
->sgpr_idx
== -1 || desc_set_loc
->indirect
)
1317 assert(!desc_set_loc
->indirect
);
1318 assert(desc_set_loc
->num_sgprs
== 2);
1319 radeon_set_sh_reg_seq(cmd_buffer
->cs
,
1320 base_reg
+ desc_set_loc
->sgpr_idx
* 4, 2);
1321 radeon_emit(cmd_buffer
->cs
, va
);
1322 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1326 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer
*cmd_buffer
,
1327 VkShaderStageFlags stages
,
1328 struct radv_descriptor_set
*set
,
1331 if (cmd_buffer
->state
.pipeline
) {
1332 radv_foreach_stage(stage
, stages
) {
1333 if (cmd_buffer
->state
.pipeline
->shaders
[stage
])
1334 emit_stage_descriptor_set_userdata(cmd_buffer
, cmd_buffer
->state
.pipeline
,
1340 if (cmd_buffer
->state
.compute_pipeline
&& (stages
& VK_SHADER_STAGE_COMPUTE_BIT
))
1341 emit_stage_descriptor_set_userdata(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
,
1343 MESA_SHADER_COMPUTE
);
1347 radv_flush_push_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
1349 struct radv_descriptor_set
*set
= &cmd_buffer
->push_descriptors
.set
;
1350 uint32_t *ptr
= NULL
;
1353 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, set
->size
, 32,
1358 set
->va
= cmd_buffer
->device
->ws
->buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1359 set
->va
+= bo_offset
;
1361 memcpy(ptr
, set
->mapped_ptr
, set
->size
);
1365 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer
*cmd_buffer
)
1367 uint32_t size
= MAX_SETS
* 2 * 4;
1371 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
,
1372 256, &offset
, &ptr
))
1375 for (unsigned i
= 0; i
< MAX_SETS
; i
++) {
1376 uint32_t *uptr
= ((uint32_t *)ptr
) + i
* 2;
1377 uint64_t set_va
= 0;
1378 struct radv_descriptor_set
*set
= cmd_buffer
->state
.descriptors
[i
];
1381 uptr
[0] = set_va
& 0xffffffff;
1382 uptr
[1] = set_va
>> 32;
1385 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1388 if (cmd_buffer
->state
.pipeline
) {
1389 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
])
1390 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
1391 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1393 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_FRAGMENT
])
1394 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_FRAGMENT
,
1395 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1397 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
))
1398 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
1399 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1401 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
1402 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_CTRL
,
1403 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1405 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
1406 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_EVAL
,
1407 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1410 if (cmd_buffer
->state
.compute_pipeline
)
1411 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
, MESA_SHADER_COMPUTE
,
1412 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1416 radv_flush_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
1417 VkShaderStageFlags stages
)
1421 if (!cmd_buffer
->state
.descriptors_dirty
)
1424 if (cmd_buffer
->state
.push_descriptors_dirty
)
1425 radv_flush_push_descriptors(cmd_buffer
);
1427 if ((cmd_buffer
->state
.pipeline
&& cmd_buffer
->state
.pipeline
->need_indirect_descriptor_sets
) ||
1428 (cmd_buffer
->state
.compute_pipeline
&& cmd_buffer
->state
.compute_pipeline
->need_indirect_descriptor_sets
)) {
1429 radv_flush_indirect_descriptor_sets(cmd_buffer
);
1432 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
1434 MAX_SETS
* MESA_SHADER_STAGES
* 4);
1436 for (i
= 0; i
< MAX_SETS
; i
++) {
1437 if (!(cmd_buffer
->state
.descriptors_dirty
& (1u << i
)))
1439 struct radv_descriptor_set
*set
= cmd_buffer
->state
.descriptors
[i
];
1443 radv_emit_descriptor_set_userdata(cmd_buffer
, stages
, set
, i
);
1445 cmd_buffer
->state
.descriptors_dirty
= 0;
1446 cmd_buffer
->state
.push_descriptors_dirty
= false;
1447 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1451 radv_flush_constants(struct radv_cmd_buffer
*cmd_buffer
,
1452 struct radv_pipeline
*pipeline
,
1453 VkShaderStageFlags stages
)
1455 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
1460 stages
&= cmd_buffer
->push_constant_stages
;
1461 if (!stages
|| !layout
|| (!layout
->push_constant_size
&& !layout
->dynamic_offset_count
))
1464 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, layout
->push_constant_size
+
1465 16 * layout
->dynamic_offset_count
,
1466 256, &offset
, &ptr
))
1469 memcpy(ptr
, cmd_buffer
->push_constants
, layout
->push_constant_size
);
1470 memcpy((char*)ptr
+ layout
->push_constant_size
, cmd_buffer
->dynamic_buffers
,
1471 16 * layout
->dynamic_offset_count
);
1473 va
= cmd_buffer
->device
->ws
->buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1476 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
1477 cmd_buffer
->cs
, MESA_SHADER_STAGES
* 4);
1479 radv_foreach_stage(stage
, stages
) {
1480 if (pipeline
->shaders
[stage
]) {
1481 radv_emit_userdata_address(cmd_buffer
, pipeline
, stage
,
1482 AC_UD_PUSH_CONSTANTS
, va
);
1486 cmd_buffer
->push_constant_stages
&= ~stages
;
1487 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1490 static void radv_emit_primitive_reset_state(struct radv_cmd_buffer
*cmd_buffer
,
1493 int32_t primitive_reset_en
= indexed_draw
&& cmd_buffer
->state
.pipeline
->graphics
.prim_restart_enable
;
1495 if (primitive_reset_en
!= cmd_buffer
->state
.last_primitive_reset_en
) {
1496 cmd_buffer
->state
.last_primitive_reset_en
= primitive_reset_en
;
1497 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1498 radeon_set_uconfig_reg(cmd_buffer
->cs
, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN
,
1499 primitive_reset_en
);
1501 radeon_set_context_reg(cmd_buffer
->cs
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
,
1502 primitive_reset_en
);
1506 if (primitive_reset_en
) {
1507 uint32_t primitive_reset_index
= cmd_buffer
->state
.index_type
? 0xffffffffu
: 0xffffu
;
1509 if (primitive_reset_index
!= cmd_buffer
->state
.last_primitive_reset_index
) {
1510 cmd_buffer
->state
.last_primitive_reset_index
= primitive_reset_index
;
1511 radeon_set_context_reg(cmd_buffer
->cs
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
1512 primitive_reset_index
);
1518 radv_cmd_buffer_flush_state(struct radv_cmd_buffer
*cmd_buffer
,
1519 bool indexed_draw
, bool instanced_draw
,
1521 uint32_t draw_vertex_count
)
1523 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1524 struct radv_device
*device
= cmd_buffer
->device
;
1525 uint32_t ia_multi_vgt_param
;
1527 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
1528 cmd_buffer
->cs
, 4096);
1530 if ((cmd_buffer
->state
.vertex_descriptors_dirty
|| cmd_buffer
->state
.vb_dirty
) &&
1531 cmd_buffer
->state
.pipeline
->num_vertex_attribs
&&
1532 cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.info
.vs
.has_vertex_buffers
) {
1536 uint32_t num_attribs
= cmd_buffer
->state
.pipeline
->num_vertex_attribs
;
1539 /* allocate some descriptor state for vertex buffers */
1540 radv_cmd_buffer_upload_alloc(cmd_buffer
, num_attribs
* 16, 256,
1541 &vb_offset
, &vb_ptr
);
1543 for (i
= 0; i
< num_attribs
; i
++) {
1544 uint32_t *desc
= &((uint32_t *)vb_ptr
)[i
* 4];
1546 int vb
= cmd_buffer
->state
.pipeline
->va_binding
[i
];
1547 struct radv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
1548 uint32_t stride
= cmd_buffer
->state
.pipeline
->binding_stride
[vb
];
1550 device
->ws
->cs_add_buffer(cmd_buffer
->cs
, buffer
->bo
, 8);
1551 va
= device
->ws
->buffer_get_va(buffer
->bo
);
1553 offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
+ cmd_buffer
->state
.pipeline
->va_offset
[i
];
1554 va
+= offset
+ buffer
->offset
;
1556 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(stride
);
1557 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
<= CIK
&& stride
)
1558 desc
[2] = (buffer
->size
- offset
- cmd_buffer
->state
.pipeline
->va_format_size
[i
]) / stride
+ 1;
1560 desc
[2] = buffer
->size
- offset
;
1561 desc
[3] = cmd_buffer
->state
.pipeline
->va_rsrc_word3
[i
];
1564 va
= device
->ws
->buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1567 radv_emit_userdata_address(cmd_buffer
, pipeline
, MESA_SHADER_VERTEX
,
1568 AC_UD_VS_VERTEX_BUFFERS
, va
);
1571 cmd_buffer
->state
.vertex_descriptors_dirty
= false;
1572 cmd_buffer
->state
.vb_dirty
= 0;
1573 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
)
1574 radv_emit_graphics_pipeline(cmd_buffer
, pipeline
);
1576 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_RENDER_TARGETS
)
1577 radv_emit_framebuffer_state(cmd_buffer
);
1579 ia_multi_vgt_param
= si_get_ia_multi_vgt_param(cmd_buffer
, instanced_draw
, indirect_draw
, draw_vertex_count
);
1580 if (cmd_buffer
->state
.last_ia_multi_vgt_param
!= ia_multi_vgt_param
) {
1581 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1582 radeon_set_uconfig_reg_idx(cmd_buffer
->cs
, R_030960_IA_MULTI_VGT_PARAM
, 4, ia_multi_vgt_param
);
1583 else if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
)
1584 radeon_set_context_reg_idx(cmd_buffer
->cs
, R_028AA8_IA_MULTI_VGT_PARAM
, 1, ia_multi_vgt_param
);
1586 radeon_set_context_reg(cmd_buffer
->cs
, R_028AA8_IA_MULTI_VGT_PARAM
, ia_multi_vgt_param
);
1587 cmd_buffer
->state
.last_ia_multi_vgt_param
= ia_multi_vgt_param
;
1590 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
) {
1591 radeon_set_context_reg(cmd_buffer
->cs
, R_028B54_VGT_SHADER_STAGES_EN
, pipeline
->graphics
.vgt_shader_stages_en
);
1593 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1594 radeon_set_uconfig_reg_idx(cmd_buffer
->cs
, R_030908_VGT_PRIMITIVE_TYPE
, 1, cmd_buffer
->state
.pipeline
->graphics
.prim
);
1596 radeon_set_config_reg(cmd_buffer
->cs
, R_008958_VGT_PRIMITIVE_TYPE
, cmd_buffer
->state
.pipeline
->graphics
.prim
);
1598 radeon_set_context_reg(cmd_buffer
->cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, cmd_buffer
->state
.pipeline
->graphics
.gs_out
);
1601 radv_cmd_buffer_flush_dynamic_state(cmd_buffer
);
1603 radv_emit_primitive_reset_state(cmd_buffer
, indexed_draw
);
1605 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
1606 radv_flush_constants(cmd_buffer
, cmd_buffer
->state
.pipeline
,
1607 VK_SHADER_STAGE_ALL_GRAPHICS
);
1609 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1611 si_emit_cache_flush(cmd_buffer
);
1614 static void radv_stage_flush(struct radv_cmd_buffer
*cmd_buffer
,
1615 VkPipelineStageFlags src_stage_mask
)
1617 if (src_stage_mask
& (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT
|
1618 VK_PIPELINE_STAGE_TRANSFER_BIT
|
1619 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
1620 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
1621 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
;
1624 if (src_stage_mask
& (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT
|
1625 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT
|
1626 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT
|
1627 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT
|
1628 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT
|
1629 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT
|
1630 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
|
1631 VK_PIPELINE_STAGE_TRANSFER_BIT
|
1632 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
1633 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT
|
1634 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
1635 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
1636 } else if (src_stage_mask
& (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
|
1637 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
1638 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
|
1639 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT
)) {
1640 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VS_PARTIAL_FLUSH
;
1644 static enum radv_cmd_flush_bits
1645 radv_src_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
1646 VkAccessFlags src_flags
)
1648 enum radv_cmd_flush_bits flush_bits
= 0;
1650 for_each_bit(b
, src_flags
) {
1651 switch ((VkAccessFlagBits
)(1 << b
)) {
1652 case VK_ACCESS_SHADER_WRITE_BIT
:
1653 flush_bits
|= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
1655 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
1656 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1657 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
1659 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
1660 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1661 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
1663 case VK_ACCESS_TRANSFER_WRITE_BIT
:
1664 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1665 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
1666 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1667 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
|
1668 RADV_CMD_FLAG_INV_GLOBAL_L2
;
1677 static enum radv_cmd_flush_bits
1678 radv_dst_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
1679 VkAccessFlags dst_flags
,
1680 struct radv_image
*image
)
1682 enum radv_cmd_flush_bits flush_bits
= 0;
1684 for_each_bit(b
, dst_flags
) {
1685 switch ((VkAccessFlagBits
)(1 << b
)) {
1686 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
1687 case VK_ACCESS_INDEX_READ_BIT
:
1688 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
1690 case VK_ACCESS_UNIFORM_READ_BIT
:
1691 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
| RADV_CMD_FLAG_INV_SMEM_L1
;
1693 case VK_ACCESS_SHADER_READ_BIT
:
1694 case VK_ACCESS_TRANSFER_READ_BIT
:
1695 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
1696 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
|
1697 RADV_CMD_FLAG_INV_GLOBAL_L2
;
1699 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
:
1700 /* TODO: change to image && when the image gets passed
1701 * through from the subpass. */
1702 if (!image
|| (image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
))
1703 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1704 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
1706 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
:
1707 if (!image
|| (image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
))
1708 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1709 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
1718 static void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
, const struct radv_subpass_barrier
*barrier
)
1720 cmd_buffer
->state
.flush_bits
|= radv_src_access_flush(cmd_buffer
, barrier
->src_access_mask
);
1721 radv_stage_flush(cmd_buffer
, barrier
->src_stage_mask
);
1722 cmd_buffer
->state
.flush_bits
|= radv_dst_access_flush(cmd_buffer
, barrier
->dst_access_mask
,
1726 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
1727 VkAttachmentReference att
)
1729 unsigned idx
= att
.attachment
;
1730 struct radv_image_view
*view
= cmd_buffer
->state
.framebuffer
->attachments
[idx
].attachment
;
1731 VkImageSubresourceRange range
;
1732 range
.aspectMask
= 0;
1733 range
.baseMipLevel
= view
->base_mip
;
1734 range
.levelCount
= 1;
1735 range
.baseArrayLayer
= view
->base_layer
;
1736 range
.layerCount
= cmd_buffer
->state
.framebuffer
->layers
;
1738 radv_handle_image_transition(cmd_buffer
,
1740 cmd_buffer
->state
.attachments
[idx
].current_layout
,
1741 att
.layout
, 0, 0, &range
,
1742 cmd_buffer
->state
.attachments
[idx
].pending_clear_aspects
);
1744 cmd_buffer
->state
.attachments
[idx
].current_layout
= att
.layout
;
1750 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
1751 const struct radv_subpass
*subpass
, bool transitions
)
1754 radv_subpass_barrier(cmd_buffer
, &subpass
->start_barrier
);
1756 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1757 radv_handle_subpass_image_transition(cmd_buffer
,
1758 subpass
->color_attachments
[i
]);
1761 for (unsigned i
= 0; i
< subpass
->input_count
; ++i
) {
1762 radv_handle_subpass_image_transition(cmd_buffer
,
1763 subpass
->input_attachments
[i
]);
1766 if (subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1767 radv_handle_subpass_image_transition(cmd_buffer
,
1768 subpass
->depth_stencil_attachment
);
1772 cmd_buffer
->state
.subpass
= subpass
;
1774 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_RENDER_TARGETS
;
1778 radv_cmd_state_setup_attachments(struct radv_cmd_buffer
*cmd_buffer
,
1779 struct radv_render_pass
*pass
,
1780 const VkRenderPassBeginInfo
*info
)
1782 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
1784 if (pass
->attachment_count
== 0) {
1785 state
->attachments
= NULL
;
1789 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
1790 pass
->attachment_count
*
1791 sizeof(state
->attachments
[0]),
1792 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1793 if (state
->attachments
== NULL
) {
1794 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1798 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1799 struct radv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1800 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1801 VkImageAspectFlags clear_aspects
= 0;
1803 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
1804 /* color attachment */
1805 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1806 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1809 /* depthstencil attachment */
1810 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
1811 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1812 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1814 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
1815 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1816 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1820 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1821 if (clear_aspects
&& info
) {
1822 assert(info
->clearValueCount
> i
);
1823 state
->attachments
[i
].clear_value
= info
->pClearValues
[i
];
1826 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1830 VkResult
radv_AllocateCommandBuffers(
1832 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
1833 VkCommandBuffer
*pCommandBuffers
)
1835 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1836 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
1838 VkResult result
= VK_SUCCESS
;
1841 memset(pCommandBuffers
, 0,
1842 sizeof(*pCommandBuffers
)*pAllocateInfo
->commandBufferCount
);
1844 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
1846 if (!list_empty(&pool
->free_cmd_buffers
)) {
1847 struct radv_cmd_buffer
*cmd_buffer
= list_first_entry(&pool
->free_cmd_buffers
, struct radv_cmd_buffer
, pool_link
);
1849 list_del(&cmd_buffer
->pool_link
);
1850 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
1852 radv_reset_cmd_buffer(cmd_buffer
);
1853 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1854 cmd_buffer
->level
= pAllocateInfo
->level
;
1856 pCommandBuffers
[i
] = radv_cmd_buffer_to_handle(cmd_buffer
);
1857 result
= VK_SUCCESS
;
1859 result
= radv_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
1860 &pCommandBuffers
[i
]);
1862 if (result
!= VK_SUCCESS
)
1866 if (result
!= VK_SUCCESS
)
1867 radv_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
,
1868 i
, pCommandBuffers
);
1873 void radv_FreeCommandBuffers(
1875 VkCommandPool commandPool
,
1876 uint32_t commandBufferCount
,
1877 const VkCommandBuffer
*pCommandBuffers
)
1879 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1880 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
1883 if (cmd_buffer
->pool
) {
1884 list_del(&cmd_buffer
->pool_link
);
1885 list_addtail(&cmd_buffer
->pool_link
, &cmd_buffer
->pool
->free_cmd_buffers
);
1887 radv_cmd_buffer_destroy(cmd_buffer
);
1893 VkResult
radv_ResetCommandBuffer(
1894 VkCommandBuffer commandBuffer
,
1895 VkCommandBufferResetFlags flags
)
1897 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1898 radv_reset_cmd_buffer(cmd_buffer
);
1902 static void emit_gfx_buffer_state(struct radv_cmd_buffer
*cmd_buffer
)
1904 struct radv_device
*device
= cmd_buffer
->device
;
1905 if (device
->gfx_init
) {
1906 uint64_t va
= device
->ws
->buffer_get_va(device
->gfx_init
);
1907 device
->ws
->cs_add_buffer(cmd_buffer
->cs
, device
->gfx_init
, 8);
1908 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
1909 radeon_emit(cmd_buffer
->cs
, va
);
1910 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1911 radeon_emit(cmd_buffer
->cs
, device
->gfx_init_size_dw
& 0xffff);
1913 si_init_config(cmd_buffer
);
1916 VkResult
radv_BeginCommandBuffer(
1917 VkCommandBuffer commandBuffer
,
1918 const VkCommandBufferBeginInfo
*pBeginInfo
)
1920 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1921 radv_reset_cmd_buffer(cmd_buffer
);
1923 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
1924 cmd_buffer
->state
.last_primitive_reset_en
= -1;
1926 /* setup initial configuration into command buffer */
1927 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
) {
1928 switch (cmd_buffer
->queue_family_index
) {
1929 case RADV_QUEUE_GENERAL
:
1930 emit_gfx_buffer_state(cmd_buffer
);
1931 radv_set_db_count_control(cmd_buffer
);
1933 case RADV_QUEUE_COMPUTE
:
1934 si_init_compute(cmd_buffer
);
1936 case RADV_QUEUE_TRANSFER
:
1942 if (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1943 cmd_buffer
->state
.framebuffer
= radv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
1944 cmd_buffer
->state
.pass
= radv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1946 struct radv_subpass
*subpass
=
1947 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1949 radv_cmd_state_setup_attachments(cmd_buffer
, cmd_buffer
->state
.pass
, NULL
);
1950 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
, false);
1953 radv_cmd_buffer_trace_emit(cmd_buffer
);
1957 void radv_CmdBindVertexBuffers(
1958 VkCommandBuffer commandBuffer
,
1959 uint32_t firstBinding
,
1960 uint32_t bindingCount
,
1961 const VkBuffer
* pBuffers
,
1962 const VkDeviceSize
* pOffsets
)
1964 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1965 struct radv_vertex_binding
*vb
= cmd_buffer
->state
.vertex_bindings
;
1967 /* We have to defer setting up vertex buffer since we need the buffer
1968 * stride from the pipeline. */
1970 assert(firstBinding
+ bindingCount
< MAX_VBS
);
1971 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
1972 vb
[firstBinding
+ i
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
1973 vb
[firstBinding
+ i
].offset
= pOffsets
[i
];
1974 cmd_buffer
->state
.vb_dirty
|= 1 << (firstBinding
+ i
);
1978 void radv_CmdBindIndexBuffer(
1979 VkCommandBuffer commandBuffer
,
1981 VkDeviceSize offset
,
1982 VkIndexType indexType
)
1984 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1986 cmd_buffer
->state
.index_buffer
= radv_buffer_from_handle(buffer
);
1987 cmd_buffer
->state
.index_offset
= offset
;
1988 cmd_buffer
->state
.index_type
= indexType
; /* vk matches hw */
1989 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
1990 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, cmd_buffer
->state
.index_buffer
->bo
, 8);
1994 void radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
1995 struct radv_descriptor_set
*set
,
1998 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
2000 assert(!(set
->layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
));
2002 cmd_buffer
->state
.descriptors
[idx
] = set
;
2003 cmd_buffer
->state
.descriptors_dirty
|= (1u << idx
);
2007 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
)
2008 if (set
->descriptors
[j
])
2009 ws
->cs_add_buffer(cmd_buffer
->cs
, set
->descriptors
[j
], 7);
2012 ws
->cs_add_buffer(cmd_buffer
->cs
, set
->bo
, 8);
2015 void radv_CmdBindDescriptorSets(
2016 VkCommandBuffer commandBuffer
,
2017 VkPipelineBindPoint pipelineBindPoint
,
2018 VkPipelineLayout _layout
,
2020 uint32_t descriptorSetCount
,
2021 const VkDescriptorSet
* pDescriptorSets
,
2022 uint32_t dynamicOffsetCount
,
2023 const uint32_t* pDynamicOffsets
)
2025 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2026 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2027 unsigned dyn_idx
= 0;
2029 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
2030 unsigned idx
= i
+ firstSet
;
2031 RADV_FROM_HANDLE(radv_descriptor_set
, set
, pDescriptorSets
[i
]);
2032 radv_bind_descriptor_set(cmd_buffer
, set
, idx
);
2034 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
2035 unsigned idx
= j
+ layout
->set
[i
+ firstSet
].dynamic_offset_start
;
2036 uint32_t *dst
= cmd_buffer
->dynamic_buffers
+ idx
* 4;
2037 assert(dyn_idx
< dynamicOffsetCount
);
2039 struct radv_descriptor_range
*range
= set
->dynamic_descriptors
+ j
;
2040 uint64_t va
= range
->va
+ pDynamicOffsets
[dyn_idx
];
2042 dst
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
2043 dst
[2] = range
->size
;
2044 dst
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2045 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2046 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2047 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2048 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2049 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2050 cmd_buffer
->push_constant_stages
|=
2051 set
->layout
->dynamic_shader_stages
;
2056 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2057 struct radv_descriptor_set
*set
,
2058 struct radv_descriptor_set_layout
*layout
)
2060 set
->size
= layout
->size
;
2061 set
->layout
= layout
;
2063 if (cmd_buffer
->push_descriptors
.capacity
< set
->size
) {
2064 size_t new_size
= MAX2(set
->size
, 1024);
2065 new_size
= MAX2(new_size
, 2 * cmd_buffer
->push_descriptors
.capacity
);
2066 new_size
= MIN2(new_size
, 96 * MAX_PUSH_DESCRIPTORS
);
2068 free(set
->mapped_ptr
);
2069 set
->mapped_ptr
= malloc(new_size
);
2071 if (!set
->mapped_ptr
) {
2072 cmd_buffer
->push_descriptors
.capacity
= 0;
2073 cmd_buffer
->record_fail
= true;
2077 cmd_buffer
->push_descriptors
.capacity
= new_size
;
2083 void radv_meta_push_descriptor_set(
2084 struct radv_cmd_buffer
* cmd_buffer
,
2085 VkPipelineBindPoint pipelineBindPoint
,
2086 VkPipelineLayout _layout
,
2088 uint32_t descriptorWriteCount
,
2089 const VkWriteDescriptorSet
* pDescriptorWrites
)
2091 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2092 struct radv_descriptor_set
*push_set
= &cmd_buffer
->meta_push_descriptors
;
2095 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2097 push_set
->size
= layout
->set
[set
].layout
->size
;
2098 push_set
->layout
= layout
->set
[set
].layout
;
2100 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, push_set
->size
, 32,
2102 (void**) &push_set
->mapped_ptr
))
2105 push_set
->va
= cmd_buffer
->device
->ws
->buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2106 push_set
->va
+= bo_offset
;
2108 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
2109 radv_descriptor_set_to_handle(push_set
),
2110 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
2112 cmd_buffer
->state
.descriptors
[set
] = push_set
;
2113 cmd_buffer
->state
.descriptors_dirty
|= (1u << set
);
2116 void radv_CmdPushDescriptorSetKHR(
2117 VkCommandBuffer commandBuffer
,
2118 VkPipelineBindPoint pipelineBindPoint
,
2119 VkPipelineLayout _layout
,
2121 uint32_t descriptorWriteCount
,
2122 const VkWriteDescriptorSet
* pDescriptorWrites
)
2124 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2125 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2126 struct radv_descriptor_set
*push_set
= &cmd_buffer
->push_descriptors
.set
;
2128 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2130 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
, layout
->set
[set
].layout
))
2133 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
2134 radv_descriptor_set_to_handle(push_set
),
2135 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
2137 cmd_buffer
->state
.descriptors
[set
] = push_set
;
2138 cmd_buffer
->state
.descriptors_dirty
|= (1u << set
);
2139 cmd_buffer
->state
.push_descriptors_dirty
= true;
2142 void radv_CmdPushDescriptorSetWithTemplateKHR(
2143 VkCommandBuffer commandBuffer
,
2144 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate
,
2145 VkPipelineLayout _layout
,
2149 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2150 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2151 struct radv_descriptor_set
*push_set
= &cmd_buffer
->push_descriptors
.set
;
2153 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2155 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
, layout
->set
[set
].layout
))
2158 radv_update_descriptor_set_with_template(cmd_buffer
->device
, cmd_buffer
, push_set
,
2159 descriptorUpdateTemplate
, pData
);
2161 cmd_buffer
->state
.descriptors
[set
] = push_set
;
2162 cmd_buffer
->state
.descriptors_dirty
|= (1u << set
);
2163 cmd_buffer
->state
.push_descriptors_dirty
= true;
2166 void radv_CmdPushConstants(VkCommandBuffer commandBuffer
,
2167 VkPipelineLayout layout
,
2168 VkShaderStageFlags stageFlags
,
2171 const void* pValues
)
2173 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2174 memcpy(cmd_buffer
->push_constants
+ offset
, pValues
, size
);
2175 cmd_buffer
->push_constant_stages
|= stageFlags
;
2178 VkResult
radv_EndCommandBuffer(
2179 VkCommandBuffer commandBuffer
)
2181 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2183 if (cmd_buffer
->queue_family_index
!= RADV_QUEUE_TRANSFER
)
2184 si_emit_cache_flush(cmd_buffer
);
2186 if (!cmd_buffer
->device
->ws
->cs_finalize(cmd_buffer
->cs
) ||
2187 cmd_buffer
->record_fail
)
2188 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2193 radv_emit_compute_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
2195 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
2196 struct radv_shader_variant
*compute_shader
;
2197 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
2200 if (!pipeline
|| pipeline
== cmd_buffer
->state
.emitted_compute_pipeline
)
2203 cmd_buffer
->state
.emitted_compute_pipeline
= pipeline
;
2205 compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
2206 va
= ws
->buffer_get_va(compute_shader
->bo
);
2208 ws
->cs_add_buffer(cmd_buffer
->cs
, compute_shader
->bo
, 8);
2209 si_cp_dma_prefetch(cmd_buffer
, va
, compute_shader
->code_size
);
2211 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
2212 cmd_buffer
->cs
, 16);
2214 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B830_COMPUTE_PGM_LO
, 2);
2215 radeon_emit(cmd_buffer
->cs
, va
>> 8);
2216 radeon_emit(cmd_buffer
->cs
, va
>> 40);
2218 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
2219 radeon_emit(cmd_buffer
->cs
, compute_shader
->rsrc1
);
2220 radeon_emit(cmd_buffer
->cs
, compute_shader
->rsrc2
);
2223 cmd_buffer
->compute_scratch_size_needed
=
2224 MAX2(cmd_buffer
->compute_scratch_size_needed
,
2225 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
2227 /* change these once we have scratch support */
2228 radeon_set_sh_reg(cmd_buffer
->cs
, R_00B860_COMPUTE_TMPRING_SIZE
,
2229 S_00B860_WAVES(pipeline
->max_waves
) |
2230 S_00B860_WAVESIZE(pipeline
->scratch_bytes_per_wave
>> 10));
2232 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
2233 radeon_emit(cmd_buffer
->cs
,
2234 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[0]));
2235 radeon_emit(cmd_buffer
->cs
,
2236 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[1]));
2237 radeon_emit(cmd_buffer
->cs
,
2238 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[2]));
2240 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2243 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer
*cmd_buffer
)
2245 for (unsigned i
= 0; i
< MAX_SETS
; i
++) {
2246 if (cmd_buffer
->state
.descriptors
[i
])
2247 cmd_buffer
->state
.descriptors_dirty
|= (1u << i
);
2251 void radv_CmdBindPipeline(
2252 VkCommandBuffer commandBuffer
,
2253 VkPipelineBindPoint pipelineBindPoint
,
2254 VkPipeline _pipeline
)
2256 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2257 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
2259 radv_mark_descriptor_sets_dirty(cmd_buffer
);
2261 switch (pipelineBindPoint
) {
2262 case VK_PIPELINE_BIND_POINT_COMPUTE
:
2263 cmd_buffer
->state
.compute_pipeline
= pipeline
;
2264 cmd_buffer
->push_constant_stages
|= VK_SHADER_STAGE_COMPUTE_BIT
;
2266 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
2267 cmd_buffer
->state
.pipeline
= pipeline
;
2271 cmd_buffer
->state
.vertex_descriptors_dirty
= true;
2272 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
;
2273 cmd_buffer
->push_constant_stages
|= pipeline
->active_stages
;
2275 /* Apply the dynamic state from the pipeline */
2276 cmd_buffer
->state
.dirty
|= pipeline
->dynamic_state_mask
;
2277 radv_dynamic_state_copy(&cmd_buffer
->state
.dynamic
,
2278 &pipeline
->dynamic_state
,
2279 pipeline
->dynamic_state_mask
);
2281 if (pipeline
->graphics
.esgs_ring_size
> cmd_buffer
->esgs_ring_size_needed
)
2282 cmd_buffer
->esgs_ring_size_needed
= pipeline
->graphics
.esgs_ring_size
;
2283 if (pipeline
->graphics
.gsvs_ring_size
> cmd_buffer
->gsvs_ring_size_needed
)
2284 cmd_buffer
->gsvs_ring_size_needed
= pipeline
->graphics
.gsvs_ring_size
;
2286 if (radv_pipeline_has_tess(pipeline
))
2287 cmd_buffer
->tess_rings_needed
= true;
2289 if (radv_pipeline_has_gs(pipeline
)) {
2290 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
2291 AC_UD_SCRATCH_RING_OFFSETS
);
2292 if (cmd_buffer
->ring_offsets_idx
== -1)
2293 cmd_buffer
->ring_offsets_idx
= loc
->sgpr_idx
;
2294 else if (loc
->sgpr_idx
!= -1)
2295 assert(loc
->sgpr_idx
== cmd_buffer
->ring_offsets_idx
);
2299 assert(!"invalid bind point");
2304 void radv_CmdSetViewport(
2305 VkCommandBuffer commandBuffer
,
2306 uint32_t firstViewport
,
2307 uint32_t viewportCount
,
2308 const VkViewport
* pViewports
)
2310 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2312 const uint32_t total_count
= firstViewport
+ viewportCount
;
2313 if (cmd_buffer
->state
.dynamic
.viewport
.count
< total_count
)
2314 cmd_buffer
->state
.dynamic
.viewport
.count
= total_count
;
2316 memcpy(cmd_buffer
->state
.dynamic
.viewport
.viewports
+ firstViewport
,
2317 pViewports
, viewportCount
* sizeof(*pViewports
));
2319 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2322 void radv_CmdSetScissor(
2323 VkCommandBuffer commandBuffer
,
2324 uint32_t firstScissor
,
2325 uint32_t scissorCount
,
2326 const VkRect2D
* pScissors
)
2328 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2330 const uint32_t total_count
= firstScissor
+ scissorCount
;
2331 if (cmd_buffer
->state
.dynamic
.scissor
.count
< total_count
)
2332 cmd_buffer
->state
.dynamic
.scissor
.count
= total_count
;
2334 memcpy(cmd_buffer
->state
.dynamic
.scissor
.scissors
+ firstScissor
,
2335 pScissors
, scissorCount
* sizeof(*pScissors
));
2336 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
2339 void radv_CmdSetLineWidth(
2340 VkCommandBuffer commandBuffer
,
2343 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2344 cmd_buffer
->state
.dynamic
.line_width
= lineWidth
;
2345 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2348 void radv_CmdSetDepthBias(
2349 VkCommandBuffer commandBuffer
,
2350 float depthBiasConstantFactor
,
2351 float depthBiasClamp
,
2352 float depthBiasSlopeFactor
)
2354 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2356 cmd_buffer
->state
.dynamic
.depth_bias
.bias
= depthBiasConstantFactor
;
2357 cmd_buffer
->state
.dynamic
.depth_bias
.clamp
= depthBiasClamp
;
2358 cmd_buffer
->state
.dynamic
.depth_bias
.slope
= depthBiasSlopeFactor
;
2360 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2363 void radv_CmdSetBlendConstants(
2364 VkCommandBuffer commandBuffer
,
2365 const float blendConstants
[4])
2367 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2369 memcpy(cmd_buffer
->state
.dynamic
.blend_constants
,
2370 blendConstants
, sizeof(float) * 4);
2372 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
2375 void radv_CmdSetDepthBounds(
2376 VkCommandBuffer commandBuffer
,
2377 float minDepthBounds
,
2378 float maxDepthBounds
)
2380 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2382 cmd_buffer
->state
.dynamic
.depth_bounds
.min
= minDepthBounds
;
2383 cmd_buffer
->state
.dynamic
.depth_bounds
.max
= maxDepthBounds
;
2385 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
2388 void radv_CmdSetStencilCompareMask(
2389 VkCommandBuffer commandBuffer
,
2390 VkStencilFaceFlags faceMask
,
2391 uint32_t compareMask
)
2393 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2395 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2396 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.front
= compareMask
;
2397 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2398 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.back
= compareMask
;
2400 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2403 void radv_CmdSetStencilWriteMask(
2404 VkCommandBuffer commandBuffer
,
2405 VkStencilFaceFlags faceMask
,
2408 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2410 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2411 cmd_buffer
->state
.dynamic
.stencil_write_mask
.front
= writeMask
;
2412 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2413 cmd_buffer
->state
.dynamic
.stencil_write_mask
.back
= writeMask
;
2415 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2418 void radv_CmdSetStencilReference(
2419 VkCommandBuffer commandBuffer
,
2420 VkStencilFaceFlags faceMask
,
2423 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2425 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2426 cmd_buffer
->state
.dynamic
.stencil_reference
.front
= reference
;
2427 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2428 cmd_buffer
->state
.dynamic
.stencil_reference
.back
= reference
;
2430 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2433 void radv_CmdExecuteCommands(
2434 VkCommandBuffer commandBuffer
,
2435 uint32_t commandBufferCount
,
2436 const VkCommandBuffer
* pCmdBuffers
)
2438 RADV_FROM_HANDLE(radv_cmd_buffer
, primary
, commandBuffer
);
2440 /* Emit pending flushes on primary prior to executing secondary */
2441 si_emit_cache_flush(primary
);
2443 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2444 RADV_FROM_HANDLE(radv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
2446 primary
->scratch_size_needed
= MAX2(primary
->scratch_size_needed
,
2447 secondary
->scratch_size_needed
);
2448 primary
->compute_scratch_size_needed
= MAX2(primary
->compute_scratch_size_needed
,
2449 secondary
->compute_scratch_size_needed
);
2451 if (secondary
->esgs_ring_size_needed
> primary
->esgs_ring_size_needed
)
2452 primary
->esgs_ring_size_needed
= secondary
->esgs_ring_size_needed
;
2453 if (secondary
->gsvs_ring_size_needed
> primary
->gsvs_ring_size_needed
)
2454 primary
->gsvs_ring_size_needed
= secondary
->gsvs_ring_size_needed
;
2455 if (secondary
->tess_rings_needed
)
2456 primary
->tess_rings_needed
= true;
2457 if (secondary
->sample_positions_needed
)
2458 primary
->sample_positions_needed
= true;
2460 if (secondary
->ring_offsets_idx
!= -1) {
2461 if (primary
->ring_offsets_idx
== -1)
2462 primary
->ring_offsets_idx
= secondary
->ring_offsets_idx
;
2464 assert(secondary
->ring_offsets_idx
== primary
->ring_offsets_idx
);
2466 primary
->device
->ws
->cs_execute_secondary(primary
->cs
, secondary
->cs
);
2469 /* if we execute secondary we need to re-emit out pipelines */
2470 if (commandBufferCount
) {
2471 primary
->state
.emitted_pipeline
= NULL
;
2472 primary
->state
.emitted_compute_pipeline
= NULL
;
2473 primary
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
;
2474 primary
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_ALL
;
2475 primary
->state
.last_primitive_reset_en
= -1;
2476 primary
->state
.last_primitive_reset_index
= 0;
2477 radv_mark_descriptor_sets_dirty(primary
);
2481 VkResult
radv_CreateCommandPool(
2483 const VkCommandPoolCreateInfo
* pCreateInfo
,
2484 const VkAllocationCallbacks
* pAllocator
,
2485 VkCommandPool
* pCmdPool
)
2487 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2488 struct radv_cmd_pool
*pool
;
2490 pool
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
2491 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2493 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2496 pool
->alloc
= *pAllocator
;
2498 pool
->alloc
= device
->alloc
;
2500 list_inithead(&pool
->cmd_buffers
);
2501 list_inithead(&pool
->free_cmd_buffers
);
2503 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
2505 *pCmdPool
= radv_cmd_pool_to_handle(pool
);
2511 void radv_DestroyCommandPool(
2513 VkCommandPool commandPool
,
2514 const VkAllocationCallbacks
* pAllocator
)
2516 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2517 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
2522 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
2523 &pool
->cmd_buffers
, pool_link
) {
2524 radv_cmd_buffer_destroy(cmd_buffer
);
2527 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
2528 &pool
->free_cmd_buffers
, pool_link
) {
2529 radv_cmd_buffer_destroy(cmd_buffer
);
2532 vk_free2(&device
->alloc
, pAllocator
, pool
);
2535 VkResult
radv_ResetCommandPool(
2537 VkCommandPool commandPool
,
2538 VkCommandPoolResetFlags flags
)
2540 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
2542 list_for_each_entry(struct radv_cmd_buffer
, cmd_buffer
,
2543 &pool
->cmd_buffers
, pool_link
) {
2544 radv_reset_cmd_buffer(cmd_buffer
);
2550 void radv_TrimCommandPoolKHR(
2552 VkCommandPool commandPool
,
2553 VkCommandPoolTrimFlagsKHR flags
)
2555 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
2560 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
2561 &pool
->free_cmd_buffers
, pool_link
) {
2562 radv_cmd_buffer_destroy(cmd_buffer
);
2566 void radv_CmdBeginRenderPass(
2567 VkCommandBuffer commandBuffer
,
2568 const VkRenderPassBeginInfo
* pRenderPassBegin
,
2569 VkSubpassContents contents
)
2571 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2572 RADV_FROM_HANDLE(radv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
2573 RADV_FROM_HANDLE(radv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
2575 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
2576 cmd_buffer
->cs
, 2048);
2578 cmd_buffer
->state
.framebuffer
= framebuffer
;
2579 cmd_buffer
->state
.pass
= pass
;
2580 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
2581 radv_cmd_state_setup_attachments(cmd_buffer
, pass
, pRenderPassBegin
);
2583 radv_cmd_buffer_set_subpass(cmd_buffer
, pass
->subpasses
, true);
2584 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2586 radv_cmd_buffer_clear_subpass(cmd_buffer
);
2589 void radv_CmdNextSubpass(
2590 VkCommandBuffer commandBuffer
,
2591 VkSubpassContents contents
)
2593 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2595 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
2597 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
2600 radv_cmd_buffer_set_subpass(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1, true);
2601 radv_cmd_buffer_clear_subpass(cmd_buffer
);
2605 VkCommandBuffer commandBuffer
,
2606 uint32_t vertexCount
,
2607 uint32_t instanceCount
,
2608 uint32_t firstVertex
,
2609 uint32_t firstInstance
)
2611 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2613 radv_cmd_buffer_flush_state(cmd_buffer
, false, (instanceCount
> 1), false, vertexCount
);
2615 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 10);
2617 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
2618 AC_UD_VS_BASE_VERTEX_START_INSTANCE
);
2619 if (loc
->sgpr_idx
!= -1) {
2620 uint32_t base_reg
= shader_stage_to_user_data_0(MESA_SHADER_VERTEX
, radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
),
2621 radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
));
2623 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.info
.vs
.needs_draw_id
)
2626 assert (loc
->num_sgprs
== vs_num
);
2627 radeon_set_sh_reg_seq(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, vs_num
);
2628 radeon_emit(cmd_buffer
->cs
, firstVertex
);
2629 radeon_emit(cmd_buffer
->cs
, firstInstance
);
2630 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.info
.vs
.needs_draw_id
)
2631 radeon_emit(cmd_buffer
->cs
, 0);
2633 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_NUM_INSTANCES
, 0, 0));
2634 radeon_emit(cmd_buffer
->cs
, instanceCount
);
2636 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, 0));
2637 radeon_emit(cmd_buffer
->cs
, vertexCount
);
2638 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
2639 S_0287F0_USE_OPAQUE(0));
2641 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2643 radv_cmd_buffer_trace_emit(cmd_buffer
);
2647 uint32_t radv_get_max_index_count(struct radv_cmd_buffer
*cmd_buffer
) {
2648 int index_size_shift
= cmd_buffer
->state
.index_type
? 2 : 1;
2649 return (cmd_buffer
->state
.index_buffer
->size
- cmd_buffer
->state
.index_offset
) >> index_size_shift
;
2652 void radv_CmdDrawIndexed(
2653 VkCommandBuffer commandBuffer
,
2654 uint32_t indexCount
,
2655 uint32_t instanceCount
,
2656 uint32_t firstIndex
,
2657 int32_t vertexOffset
,
2658 uint32_t firstInstance
)
2660 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2661 int index_size
= cmd_buffer
->state
.index_type
? 4 : 2;
2662 uint32_t index_max_size
= radv_get_max_index_count(cmd_buffer
);
2665 radv_cmd_buffer_flush_state(cmd_buffer
, true, (instanceCount
> 1), false, indexCount
);
2667 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 15);
2669 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2670 radeon_set_uconfig_reg_idx(cmd_buffer
->cs
, R_03090C_VGT_INDEX_TYPE
,
2671 2, cmd_buffer
->state
.index_type
);
2673 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
2674 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.index_type
);
2677 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
2678 AC_UD_VS_BASE_VERTEX_START_INSTANCE
);
2679 if (loc
->sgpr_idx
!= -1) {
2680 uint32_t base_reg
= shader_stage_to_user_data_0(MESA_SHADER_VERTEX
, radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
),
2681 radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
));
2683 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.info
.vs
.needs_draw_id
)
2686 assert (loc
->num_sgprs
== vs_num
);
2687 radeon_set_sh_reg_seq(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, vs_num
);
2688 radeon_emit(cmd_buffer
->cs
, vertexOffset
);
2689 radeon_emit(cmd_buffer
->cs
, firstInstance
);
2690 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.info
.vs
.needs_draw_id
)
2691 radeon_emit(cmd_buffer
->cs
, 0);
2693 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_NUM_INSTANCES
, 0, 0));
2694 radeon_emit(cmd_buffer
->cs
, instanceCount
);
2696 index_va
= cmd_buffer
->device
->ws
->buffer_get_va(cmd_buffer
->state
.index_buffer
->bo
);
2697 index_va
+= firstIndex
* index_size
+ cmd_buffer
->state
.index_buffer
->offset
+ cmd_buffer
->state
.index_offset
;
2698 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, false));
2699 radeon_emit(cmd_buffer
->cs
, index_max_size
);
2700 radeon_emit(cmd_buffer
->cs
, index_va
);
2701 radeon_emit(cmd_buffer
->cs
, (index_va
>> 32UL) & 0xFF);
2702 radeon_emit(cmd_buffer
->cs
, indexCount
);
2703 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_DMA
);
2705 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2706 radv_cmd_buffer_trace_emit(cmd_buffer
);
2710 radv_emit_indirect_draw(struct radv_cmd_buffer
*cmd_buffer
,
2712 VkDeviceSize offset
,
2713 VkBuffer _count_buffer
,
2714 VkDeviceSize count_offset
,
2715 uint32_t draw_count
,
2719 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
2720 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _count_buffer
);
2721 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
2722 unsigned di_src_sel
= indexed
? V_0287F0_DI_SRC_SEL_DMA
2723 : V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
2724 uint64_t indirect_va
= cmd_buffer
->device
->ws
->buffer_get_va(buffer
->bo
);
2725 indirect_va
+= offset
+ buffer
->offset
;
2726 uint64_t count_va
= 0;
2729 count_va
= cmd_buffer
->device
->ws
->buffer_get_va(count_buffer
->bo
);
2730 count_va
+= count_offset
+ count_buffer
->offset
;
2736 cmd_buffer
->device
->ws
->cs_add_buffer(cs
, buffer
->bo
, 8);
2738 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
2739 AC_UD_VS_BASE_VERTEX_START_INSTANCE
);
2740 uint32_t base_reg
= shader_stage_to_user_data_0(MESA_SHADER_VERTEX
, radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
),
2741 radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
));
2742 bool draw_id_enable
= cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.info
.vs
.needs_draw_id
;
2743 assert(loc
->sgpr_idx
!= -1);
2744 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
2746 radeon_emit(cs
, indirect_va
);
2747 radeon_emit(cs
, indirect_va
>> 32);
2749 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT_MULTI
:
2750 PKT3_DRAW_INDIRECT_MULTI
,
2753 radeon_emit(cs
, ((base_reg
+ loc
->sgpr_idx
* 4) - SI_SH_REG_OFFSET
) >> 2);
2754 radeon_emit(cs
, ((base_reg
+ (loc
->sgpr_idx
+ 1) * 4) - SI_SH_REG_OFFSET
) >> 2);
2755 radeon_emit(cs
, (((base_reg
+ (loc
->sgpr_idx
+ 2) * 4) - SI_SH_REG_OFFSET
) >> 2) |
2756 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable
) |
2757 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va
));
2758 radeon_emit(cs
, draw_count
); /* count */
2759 radeon_emit(cs
, count_va
); /* count_addr */
2760 radeon_emit(cs
, count_va
>> 32);
2761 radeon_emit(cs
, stride
); /* stride */
2762 radeon_emit(cs
, di_src_sel
);
2763 radv_cmd_buffer_trace_emit(cmd_buffer
);
2767 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer
,
2769 VkDeviceSize offset
,
2770 VkBuffer countBuffer
,
2771 VkDeviceSize countBufferOffset
,
2772 uint32_t maxDrawCount
,
2775 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2776 radv_cmd_buffer_flush_state(cmd_buffer
, false, false, true, 0);
2778 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
2779 cmd_buffer
->cs
, 14);
2781 radv_emit_indirect_draw(cmd_buffer
, buffer
, offset
,
2782 countBuffer
, countBufferOffset
, maxDrawCount
, stride
, false);
2784 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2788 radv_cmd_draw_indexed_indirect_count(
2789 VkCommandBuffer commandBuffer
,
2791 VkDeviceSize offset
,
2792 VkBuffer countBuffer
,
2793 VkDeviceSize countBufferOffset
,
2794 uint32_t maxDrawCount
,
2797 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2798 uint32_t index_max_size
= radv_get_max_index_count(cmd_buffer
);
2800 radv_cmd_buffer_flush_state(cmd_buffer
, true, false, true, 0);
2802 index_va
= cmd_buffer
->device
->ws
->buffer_get_va(cmd_buffer
->state
.index_buffer
->bo
);
2803 index_va
+= cmd_buffer
->state
.index_buffer
->offset
+ cmd_buffer
->state
.index_offset
;
2805 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 21);
2807 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
2808 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.index_type
);
2810 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
2811 radeon_emit(cmd_buffer
->cs
, index_va
);
2812 radeon_emit(cmd_buffer
->cs
, index_va
>> 32);
2814 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
2815 radeon_emit(cmd_buffer
->cs
, index_max_size
);
2817 radv_emit_indirect_draw(cmd_buffer
, buffer
, offset
,
2818 countBuffer
, countBufferOffset
, maxDrawCount
, stride
, true);
2820 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2823 void radv_CmdDrawIndirect(
2824 VkCommandBuffer commandBuffer
,
2826 VkDeviceSize offset
,
2830 radv_cmd_draw_indirect_count(commandBuffer
, buffer
, offset
,
2831 VK_NULL_HANDLE
, 0, drawCount
, stride
);
2834 void radv_CmdDrawIndexedIndirect(
2835 VkCommandBuffer commandBuffer
,
2837 VkDeviceSize offset
,
2841 radv_cmd_draw_indexed_indirect_count(commandBuffer
, buffer
, offset
,
2842 VK_NULL_HANDLE
, 0, drawCount
, stride
);
2845 void radv_CmdDrawIndirectCountAMD(
2846 VkCommandBuffer commandBuffer
,
2848 VkDeviceSize offset
,
2849 VkBuffer countBuffer
,
2850 VkDeviceSize countBufferOffset
,
2851 uint32_t maxDrawCount
,
2854 radv_cmd_draw_indirect_count(commandBuffer
, buffer
, offset
,
2855 countBuffer
, countBufferOffset
,
2856 maxDrawCount
, stride
);
2859 void radv_CmdDrawIndexedIndirectCountAMD(
2860 VkCommandBuffer commandBuffer
,
2862 VkDeviceSize offset
,
2863 VkBuffer countBuffer
,
2864 VkDeviceSize countBufferOffset
,
2865 uint32_t maxDrawCount
,
2868 radv_cmd_draw_indexed_indirect_count(commandBuffer
, buffer
, offset
,
2869 countBuffer
, countBufferOffset
,
2870 maxDrawCount
, stride
);
2874 radv_flush_compute_state(struct radv_cmd_buffer
*cmd_buffer
)
2876 radv_emit_compute_pipeline(cmd_buffer
);
2877 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
2878 radv_flush_constants(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
,
2879 VK_SHADER_STAGE_COMPUTE_BIT
);
2880 si_emit_cache_flush(cmd_buffer
);
2883 void radv_CmdDispatch(
2884 VkCommandBuffer commandBuffer
,
2889 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2891 radv_flush_compute_state(cmd_buffer
);
2893 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 10);
2895 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(cmd_buffer
->state
.compute_pipeline
,
2896 MESA_SHADER_COMPUTE
, AC_UD_CS_GRID_SIZE
);
2897 if (loc
->sgpr_idx
!= -1) {
2898 assert(!loc
->indirect
);
2899 uint8_t grid_used
= cmd_buffer
->state
.compute_pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.info
.cs
.grid_components_used
;
2900 assert(loc
->num_sgprs
== grid_used
);
2901 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B900_COMPUTE_USER_DATA_0
+ loc
->sgpr_idx
* 4, grid_used
);
2902 radeon_emit(cmd_buffer
->cs
, x
);
2904 radeon_emit(cmd_buffer
->cs
, y
);
2906 radeon_emit(cmd_buffer
->cs
, z
);
2909 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, 0) |
2910 PKT3_SHADER_TYPE_S(1));
2911 radeon_emit(cmd_buffer
->cs
, x
);
2912 radeon_emit(cmd_buffer
->cs
, y
);
2913 radeon_emit(cmd_buffer
->cs
, z
);
2914 radeon_emit(cmd_buffer
->cs
, 1);
2916 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2917 radv_cmd_buffer_trace_emit(cmd_buffer
);
2920 void radv_CmdDispatchIndirect(
2921 VkCommandBuffer commandBuffer
,
2923 VkDeviceSize offset
)
2925 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2926 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
2927 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(buffer
->bo
);
2928 va
+= buffer
->offset
+ offset
;
2930 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, buffer
->bo
, 8);
2932 radv_flush_compute_state(cmd_buffer
);
2934 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 25);
2935 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(cmd_buffer
->state
.compute_pipeline
,
2936 MESA_SHADER_COMPUTE
, AC_UD_CS_GRID_SIZE
);
2937 if (loc
->sgpr_idx
!= -1) {
2938 uint8_t grid_used
= cmd_buffer
->state
.compute_pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.info
.cs
.grid_components_used
;
2939 for (unsigned i
= 0; i
< grid_used
; ++i
) {
2940 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
2941 radeon_emit(cmd_buffer
->cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
2942 COPY_DATA_DST_SEL(COPY_DATA_REG
));
2943 radeon_emit(cmd_buffer
->cs
, (va
+ 4 * i
));
2944 radeon_emit(cmd_buffer
->cs
, (va
+ 4 * i
) >> 32);
2945 radeon_emit(cmd_buffer
->cs
, ((R_00B900_COMPUTE_USER_DATA_0
+ loc
->sgpr_idx
* 4) >> 2) + i
);
2946 radeon_emit(cmd_buffer
->cs
, 0);
2950 if (radv_cmd_buffer_uses_mec(cmd_buffer
)) {
2951 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 2, 0) |
2952 PKT3_SHADER_TYPE_S(1));
2953 radeon_emit(cmd_buffer
->cs
, va
);
2954 radeon_emit(cmd_buffer
->cs
, va
>> 32);
2955 radeon_emit(cmd_buffer
->cs
, 1);
2957 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_SET_BASE
, 2, 0) |
2958 PKT3_SHADER_TYPE_S(1));
2959 radeon_emit(cmd_buffer
->cs
, 1);
2960 radeon_emit(cmd_buffer
->cs
, va
);
2961 radeon_emit(cmd_buffer
->cs
, va
>> 32);
2963 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 1, 0) |
2964 PKT3_SHADER_TYPE_S(1));
2965 radeon_emit(cmd_buffer
->cs
, 0);
2966 radeon_emit(cmd_buffer
->cs
, 1);
2969 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2970 radv_cmd_buffer_trace_emit(cmd_buffer
);
2973 void radv_unaligned_dispatch(
2974 struct radv_cmd_buffer
*cmd_buffer
,
2979 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
2980 struct radv_shader_variant
*compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
2981 uint32_t blocks
[3], remainder
[3];
2983 blocks
[0] = round_up_u32(x
, compute_shader
->info
.cs
.block_size
[0]);
2984 blocks
[1] = round_up_u32(y
, compute_shader
->info
.cs
.block_size
[1]);
2985 blocks
[2] = round_up_u32(z
, compute_shader
->info
.cs
.block_size
[2]);
2987 /* If aligned, these should be an entire block size, not 0 */
2988 remainder
[0] = x
+ compute_shader
->info
.cs
.block_size
[0] - align_u32_npot(x
, compute_shader
->info
.cs
.block_size
[0]);
2989 remainder
[1] = y
+ compute_shader
->info
.cs
.block_size
[1] - align_u32_npot(y
, compute_shader
->info
.cs
.block_size
[1]);
2990 remainder
[2] = z
+ compute_shader
->info
.cs
.block_size
[2] - align_u32_npot(z
, compute_shader
->info
.cs
.block_size
[2]);
2992 radv_flush_compute_state(cmd_buffer
);
2994 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 15);
2996 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
2997 radeon_emit(cmd_buffer
->cs
,
2998 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[0]) |
2999 S_00B81C_NUM_THREAD_PARTIAL(remainder
[0]));
3000 radeon_emit(cmd_buffer
->cs
,
3001 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[1]) |
3002 S_00B81C_NUM_THREAD_PARTIAL(remainder
[1]));
3003 radeon_emit(cmd_buffer
->cs
,
3004 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[2]) |
3005 S_00B81C_NUM_THREAD_PARTIAL(remainder
[2]));
3007 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(cmd_buffer
->state
.compute_pipeline
,
3008 MESA_SHADER_COMPUTE
, AC_UD_CS_GRID_SIZE
);
3009 if (loc
->sgpr_idx
!= -1) {
3010 uint8_t grid_used
= cmd_buffer
->state
.compute_pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.info
.cs
.grid_components_used
;
3011 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B900_COMPUTE_USER_DATA_0
+ loc
->sgpr_idx
* 4, grid_used
);
3012 radeon_emit(cmd_buffer
->cs
, blocks
[0]);
3014 radeon_emit(cmd_buffer
->cs
, blocks
[1]);
3016 radeon_emit(cmd_buffer
->cs
, blocks
[2]);
3018 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, 0) |
3019 PKT3_SHADER_TYPE_S(1));
3020 radeon_emit(cmd_buffer
->cs
, blocks
[0]);
3021 radeon_emit(cmd_buffer
->cs
, blocks
[1]);
3022 radeon_emit(cmd_buffer
->cs
, blocks
[2]);
3023 radeon_emit(cmd_buffer
->cs
, S_00B800_COMPUTE_SHADER_EN(1) |
3024 S_00B800_PARTIAL_TG_EN(1));
3026 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3027 radv_cmd_buffer_trace_emit(cmd_buffer
);
3030 void radv_CmdEndRenderPass(
3031 VkCommandBuffer commandBuffer
)
3033 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3035 radv_subpass_barrier(cmd_buffer
, &cmd_buffer
->state
.pass
->end_barrier
);
3037 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
3039 for (unsigned i
= 0; i
< cmd_buffer
->state
.framebuffer
->attachment_count
; ++i
) {
3040 VkImageLayout layout
= cmd_buffer
->state
.pass
->attachments
[i
].final_layout
;
3041 radv_handle_subpass_image_transition(cmd_buffer
,
3042 (VkAttachmentReference
){i
, layout
});
3045 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
3047 cmd_buffer
->state
.pass
= NULL
;
3048 cmd_buffer
->state
.subpass
= NULL
;
3049 cmd_buffer
->state
.attachments
= NULL
;
3050 cmd_buffer
->state
.framebuffer
= NULL
;
3054 * For HTILE we have the following interesting clear words:
3055 * 0x0000030f: Uncompressed.
3056 * 0xfffffff0: Clear depth to 1.0
3057 * 0x00000000: Clear depth to 0.0
3059 static void radv_initialize_htile(struct radv_cmd_buffer
*cmd_buffer
,
3060 struct radv_image
*image
,
3061 const VkImageSubresourceRange
*range
,
3062 uint32_t clear_word
)
3064 assert(range
->baseMipLevel
== 0);
3065 assert(range
->levelCount
== 1 || range
->levelCount
== VK_REMAINING_ARRAY_LAYERS
);
3066 unsigned layer_count
= radv_get_layerCount(image
, range
);
3067 uint64_t size
= image
->surface
.htile_slice_size
* layer_count
;
3068 uint64_t offset
= image
->offset
+ image
->htile_offset
+
3069 image
->surface
.htile_slice_size
* range
->baseArrayLayer
;
3071 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3072 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
3074 radv_fill_buffer(cmd_buffer
, image
->bo
, offset
, size
, clear_word
);
3076 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
|
3077 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
3078 RADV_CMD_FLAG_INV_VMEM_L1
|
3079 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
3082 static void radv_handle_depth_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3083 struct radv_image
*image
,
3084 VkImageLayout src_layout
,
3085 VkImageLayout dst_layout
,
3086 unsigned src_queue_mask
,
3087 unsigned dst_queue_mask
,
3088 const VkImageSubresourceRange
*range
,
3089 VkImageAspectFlags pending_clears
)
3091 if (dst_layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
&&
3092 (pending_clears
& vk_format_aspects(image
->vk_format
)) == vk_format_aspects(image
->vk_format
) &&
3093 cmd_buffer
->state
.render_area
.offset
.x
== 0 && cmd_buffer
->state
.render_area
.offset
.y
== 0 &&
3094 cmd_buffer
->state
.render_area
.extent
.width
== image
->info
.width
&&
3095 cmd_buffer
->state
.render_area
.extent
.height
== image
->info
.height
) {
3096 /* The clear will initialize htile. */
3098 } else if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
&&
3099 radv_layout_has_htile(image
, dst_layout
, dst_queue_mask
)) {
3100 /* TODO: merge with the clear if applicable */
3101 radv_initialize_htile(cmd_buffer
, image
, range
, 0);
3102 } else if (!radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
3103 radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
3104 radv_initialize_htile(cmd_buffer
, image
, range
, 0xffffffff);
3105 } else if (radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
3106 !radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
3107 VkImageSubresourceRange local_range
= *range
;
3108 local_range
.aspectMask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
3109 local_range
.baseMipLevel
= 0;
3110 local_range
.levelCount
= 1;
3112 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3113 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
3115 radv_decompress_depth_image_inplace(cmd_buffer
, image
, &local_range
);
3117 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3118 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
3122 void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
3123 struct radv_image
*image
, uint32_t value
)
3125 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3126 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
3128 radv_fill_buffer(cmd_buffer
, image
->bo
, image
->offset
+ image
->cmask
.offset
,
3129 image
->cmask
.size
, value
);
3131 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
3132 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
3133 RADV_CMD_FLAG_INV_VMEM_L1
|
3134 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
3137 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3138 struct radv_image
*image
,
3139 VkImageLayout src_layout
,
3140 VkImageLayout dst_layout
,
3141 unsigned src_queue_mask
,
3142 unsigned dst_queue_mask
,
3143 const VkImageSubresourceRange
*range
,
3144 VkImageAspectFlags pending_clears
)
3146 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
3147 if (image
->fmask
.size
)
3148 radv_initialise_cmask(cmd_buffer
, image
, 0xccccccccu
);
3150 radv_initialise_cmask(cmd_buffer
, image
, 0xffffffffu
);
3151 } else if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
3152 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
3153 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
3157 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
3158 struct radv_image
*image
, uint32_t value
)
3161 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3162 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
3164 radv_fill_buffer(cmd_buffer
, image
->bo
, image
->offset
+ image
->dcc_offset
,
3165 image
->surface
.dcc_size
, value
);
3167 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3168 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
3169 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
3170 RADV_CMD_FLAG_INV_VMEM_L1
|
3171 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
3174 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3175 struct radv_image
*image
,
3176 VkImageLayout src_layout
,
3177 VkImageLayout dst_layout
,
3178 unsigned src_queue_mask
,
3179 unsigned dst_queue_mask
,
3180 const VkImageSubresourceRange
*range
,
3181 VkImageAspectFlags pending_clears
)
3183 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
3184 radv_initialize_dcc(cmd_buffer
, image
, 0x20202020u
);
3185 } else if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
3186 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
3187 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
3191 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3192 struct radv_image
*image
,
3193 VkImageLayout src_layout
,
3194 VkImageLayout dst_layout
,
3195 uint32_t src_family
,
3196 uint32_t dst_family
,
3197 const VkImageSubresourceRange
*range
,
3198 VkImageAspectFlags pending_clears
)
3200 if (image
->exclusive
&& src_family
!= dst_family
) {
3201 /* This is an acquire or a release operation and there will be
3202 * a corresponding release/acquire. Do the transition in the
3203 * most flexible queue. */
3205 assert(src_family
== cmd_buffer
->queue_family_index
||
3206 dst_family
== cmd_buffer
->queue_family_index
);
3208 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_TRANSFER
)
3211 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
3212 (src_family
== RADV_QUEUE_GENERAL
||
3213 dst_family
== RADV_QUEUE_GENERAL
))
3217 unsigned src_queue_mask
= radv_image_queue_family_mask(image
, src_family
, cmd_buffer
->queue_family_index
);
3218 unsigned dst_queue_mask
= radv_image_queue_family_mask(image
, dst_family
, cmd_buffer
->queue_family_index
);
3220 if (image
->surface
.htile_size
)
3221 radv_handle_depth_image_transition(cmd_buffer
, image
, src_layout
,
3222 dst_layout
, src_queue_mask
,
3223 dst_queue_mask
, range
,
3226 if (image
->cmask
.size
)
3227 radv_handle_cmask_image_transition(cmd_buffer
, image
, src_layout
,
3228 dst_layout
, src_queue_mask
,
3229 dst_queue_mask
, range
,
3232 if (image
->surface
.dcc_size
)
3233 radv_handle_dcc_image_transition(cmd_buffer
, image
, src_layout
,
3234 dst_layout
, src_queue_mask
,
3235 dst_queue_mask
, range
,
3239 void radv_CmdPipelineBarrier(
3240 VkCommandBuffer commandBuffer
,
3241 VkPipelineStageFlags srcStageMask
,
3242 VkPipelineStageFlags destStageMask
,
3244 uint32_t memoryBarrierCount
,
3245 const VkMemoryBarrier
* pMemoryBarriers
,
3246 uint32_t bufferMemoryBarrierCount
,
3247 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
3248 uint32_t imageMemoryBarrierCount
,
3249 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
3251 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3252 enum radv_cmd_flush_bits src_flush_bits
= 0;
3253 enum radv_cmd_flush_bits dst_flush_bits
= 0;
3255 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
3256 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pMemoryBarriers
[i
].srcAccessMask
);
3257 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pMemoryBarriers
[i
].dstAccessMask
,
3261 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
3262 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].srcAccessMask
);
3263 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].dstAccessMask
,
3267 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
3268 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
3269 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].srcAccessMask
);
3270 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].dstAccessMask
,
3274 radv_stage_flush(cmd_buffer
, srcStageMask
);
3275 cmd_buffer
->state
.flush_bits
|= src_flush_bits
;
3277 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
3278 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
3279 radv_handle_image_transition(cmd_buffer
, image
,
3280 pImageMemoryBarriers
[i
].oldLayout
,
3281 pImageMemoryBarriers
[i
].newLayout
,
3282 pImageMemoryBarriers
[i
].srcQueueFamilyIndex
,
3283 pImageMemoryBarriers
[i
].dstQueueFamilyIndex
,
3284 &pImageMemoryBarriers
[i
].subresourceRange
,
3288 cmd_buffer
->state
.flush_bits
|= dst_flush_bits
;
3292 static void write_event(struct radv_cmd_buffer
*cmd_buffer
,
3293 struct radv_event
*event
,
3294 VkPipelineStageFlags stageMask
,
3297 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
3298 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(event
->bo
);
3300 cmd_buffer
->device
->ws
->cs_add_buffer(cs
, event
->bo
, 8);
3302 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 18);
3304 /* TODO: this is overkill. Probably should figure something out from
3305 * the stage mask. */
3307 si_cs_emit_write_event_eop(cs
,
3308 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
3310 EVENT_TYPE_BOTTOM_OF_PIPE_TS
, 0,
3313 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3316 void radv_CmdSetEvent(VkCommandBuffer commandBuffer
,
3318 VkPipelineStageFlags stageMask
)
3320 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3321 RADV_FROM_HANDLE(radv_event
, event
, _event
);
3323 write_event(cmd_buffer
, event
, stageMask
, 1);
3326 void radv_CmdResetEvent(VkCommandBuffer commandBuffer
,
3328 VkPipelineStageFlags stageMask
)
3330 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3331 RADV_FROM_HANDLE(radv_event
, event
, _event
);
3333 write_event(cmd_buffer
, event
, stageMask
, 0);
3336 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer
,
3337 uint32_t eventCount
,
3338 const VkEvent
* pEvents
,
3339 VkPipelineStageFlags srcStageMask
,
3340 VkPipelineStageFlags dstStageMask
,
3341 uint32_t memoryBarrierCount
,
3342 const VkMemoryBarrier
* pMemoryBarriers
,
3343 uint32_t bufferMemoryBarrierCount
,
3344 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
3345 uint32_t imageMemoryBarrierCount
,
3346 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
3348 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3349 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
3351 for (unsigned i
= 0; i
< eventCount
; ++i
) {
3352 RADV_FROM_HANDLE(radv_event
, event
, pEvents
[i
]);
3353 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(event
->bo
);
3355 cmd_buffer
->device
->ws
->cs_add_buffer(cs
, event
->bo
, 8);
3357 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 7);
3359 si_emit_wait_fence(cs
, va
, 1, 0xffffffff);
3360 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3364 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
3365 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
3367 radv_handle_image_transition(cmd_buffer
, image
,
3368 pImageMemoryBarriers
[i
].oldLayout
,
3369 pImageMemoryBarriers
[i
].newLayout
,
3370 pImageMemoryBarriers
[i
].srcQueueFamilyIndex
,
3371 pImageMemoryBarriers
[i
].dstQueueFamilyIndex
,
3372 &pImageMemoryBarriers
[i
].subresourceRange
,
3376 /* TODO: figure out how to do memory barriers without waiting */
3377 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
|
3378 RADV_CMD_FLAG_INV_GLOBAL_L2
|
3379 RADV_CMD_FLAG_INV_VMEM_L1
|
3380 RADV_CMD_FLAG_INV_SMEM_L1
;