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radv/gfx10: update OVERWRITE_COMBINER_{MRT_SHARING,WATERMARK}
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range,
61 struct radv_sample_locations_state *sample_locs);
62
63 const struct radv_dynamic_state default_dynamic_state = {
64 .viewport = {
65 .count = 0,
66 },
67 .scissor = {
68 .count = 0,
69 },
70 .line_width = 1.0f,
71 .depth_bias = {
72 .bias = 0.0f,
73 .clamp = 0.0f,
74 .slope = 0.0f,
75 },
76 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
77 .depth_bounds = {
78 .min = 0.0f,
79 .max = 1.0f,
80 },
81 .stencil_compare_mask = {
82 .front = ~0u,
83 .back = ~0u,
84 },
85 .stencil_write_mask = {
86 .front = ~0u,
87 .back = ~0u,
88 },
89 .stencil_reference = {
90 .front = 0u,
91 .back = 0u,
92 },
93 };
94
95 static void
96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
97 const struct radv_dynamic_state *src)
98 {
99 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
100 uint32_t copy_mask = src->mask;
101 uint32_t dest_mask = 0;
102
103 /* Make sure to copy the number of viewports/scissors because they can
104 * only be specified at pipeline creation time.
105 */
106 dest->viewport.count = src->viewport.count;
107 dest->scissor.count = src->scissor.count;
108 dest->discard_rectangle.count = src->discard_rectangle.count;
109 dest->sample_location.count = src->sample_location.count;
110
111 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
112 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
113 src->viewport.count * sizeof(VkViewport))) {
114 typed_memcpy(dest->viewport.viewports,
115 src->viewport.viewports,
116 src->viewport.count);
117 dest_mask |= RADV_DYNAMIC_VIEWPORT;
118 }
119 }
120
121 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
122 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
123 src->scissor.count * sizeof(VkRect2D))) {
124 typed_memcpy(dest->scissor.scissors,
125 src->scissor.scissors, src->scissor.count);
126 dest_mask |= RADV_DYNAMIC_SCISSOR;
127 }
128 }
129
130 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
131 if (dest->line_width != src->line_width) {
132 dest->line_width = src->line_width;
133 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
134 }
135 }
136
137 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
138 if (memcmp(&dest->depth_bias, &src->depth_bias,
139 sizeof(src->depth_bias))) {
140 dest->depth_bias = src->depth_bias;
141 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
142 }
143 }
144
145 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
146 if (memcmp(&dest->blend_constants, &src->blend_constants,
147 sizeof(src->blend_constants))) {
148 typed_memcpy(dest->blend_constants,
149 src->blend_constants, 4);
150 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
151 }
152 }
153
154 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
155 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
156 sizeof(src->depth_bounds))) {
157 dest->depth_bounds = src->depth_bounds;
158 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
159 }
160 }
161
162 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
163 if (memcmp(&dest->stencil_compare_mask,
164 &src->stencil_compare_mask,
165 sizeof(src->stencil_compare_mask))) {
166 dest->stencil_compare_mask = src->stencil_compare_mask;
167 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
168 }
169 }
170
171 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
172 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
173 sizeof(src->stencil_write_mask))) {
174 dest->stencil_write_mask = src->stencil_write_mask;
175 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
176 }
177 }
178
179 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
180 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
181 sizeof(src->stencil_reference))) {
182 dest->stencil_reference = src->stencil_reference;
183 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
184 }
185 }
186
187 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
188 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
189 src->discard_rectangle.count * sizeof(VkRect2D))) {
190 typed_memcpy(dest->discard_rectangle.rectangles,
191 src->discard_rectangle.rectangles,
192 src->discard_rectangle.count);
193 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
194 }
195 }
196
197 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
198 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
199 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
200 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
201 memcmp(&dest->sample_location.locations,
202 &src->sample_location.locations,
203 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
204 dest->sample_location.per_pixel = src->sample_location.per_pixel;
205 dest->sample_location.grid_size = src->sample_location.grid_size;
206 typed_memcpy(dest->sample_location.locations,
207 src->sample_location.locations,
208 src->sample_location.count);
209 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
210 }
211 }
212
213 cmd_buffer->state.dirty |= dest_mask;
214 }
215
216 static void
217 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
218 struct radv_pipeline *pipeline)
219 {
220 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
221 struct radv_shader_info *info;
222
223 if (!pipeline->streamout_shader)
224 return;
225
226 info = &pipeline->streamout_shader->info.info;
227 for (int i = 0; i < MAX_SO_BUFFERS; i++)
228 so->stride_in_dw[i] = info->so.strides[i];
229
230 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
231 }
232
233 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
234 {
235 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
236 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
237 }
238
239 enum ring_type radv_queue_family_to_ring(int f) {
240 switch (f) {
241 case RADV_QUEUE_GENERAL:
242 return RING_GFX;
243 case RADV_QUEUE_COMPUTE:
244 return RING_COMPUTE;
245 case RADV_QUEUE_TRANSFER:
246 return RING_DMA;
247 default:
248 unreachable("Unknown queue family");
249 }
250 }
251
252 static VkResult radv_create_cmd_buffer(
253 struct radv_device * device,
254 struct radv_cmd_pool * pool,
255 VkCommandBufferLevel level,
256 VkCommandBuffer* pCommandBuffer)
257 {
258 struct radv_cmd_buffer *cmd_buffer;
259 unsigned ring;
260 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
261 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
262 if (cmd_buffer == NULL)
263 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
264
265 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
266 cmd_buffer->device = device;
267 cmd_buffer->pool = pool;
268 cmd_buffer->level = level;
269
270 if (pool) {
271 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
272 cmd_buffer->queue_family_index = pool->queue_family_index;
273
274 } else {
275 /* Init the pool_link so we can safely call list_del when we destroy
276 * the command buffer
277 */
278 list_inithead(&cmd_buffer->pool_link);
279 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
280 }
281
282 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
283
284 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
285 if (!cmd_buffer->cs) {
286 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
287 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
288 }
289
290 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
291
292 list_inithead(&cmd_buffer->upload.list);
293
294 return VK_SUCCESS;
295 }
296
297 static void
298 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
299 {
300 list_del(&cmd_buffer->pool_link);
301
302 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
303 &cmd_buffer->upload.list, list) {
304 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
305 list_del(&up->list);
306 free(up);
307 }
308
309 if (cmd_buffer->upload.upload_bo)
310 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
311 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
312
313 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
314 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
315
316 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
317 }
318
319 static VkResult
320 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
321 {
322 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
323
324 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
325 &cmd_buffer->upload.list, list) {
326 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
327 list_del(&up->list);
328 free(up);
329 }
330
331 cmd_buffer->push_constant_stages = 0;
332 cmd_buffer->scratch_size_needed = 0;
333 cmd_buffer->compute_scratch_size_needed = 0;
334 cmd_buffer->esgs_ring_size_needed = 0;
335 cmd_buffer->gsvs_ring_size_needed = 0;
336 cmd_buffer->tess_rings_needed = false;
337 cmd_buffer->sample_positions_needed = false;
338
339 if (cmd_buffer->upload.upload_bo)
340 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
341 cmd_buffer->upload.upload_bo);
342 cmd_buffer->upload.offset = 0;
343
344 cmd_buffer->record_result = VK_SUCCESS;
345
346 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
347
348 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
349 cmd_buffer->descriptors[i].dirty = 0;
350 cmd_buffer->descriptors[i].valid = 0;
351 cmd_buffer->descriptors[i].push_dirty = false;
352 }
353
354 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
355 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
356 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
357 unsigned fence_offset, eop_bug_offset;
358 void *fence_ptr;
359
360 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
361 &fence_ptr);
362
363 cmd_buffer->gfx9_fence_va =
364 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
365 cmd_buffer->gfx9_fence_va += fence_offset;
366
367 /* Allocate a buffer for the EOP bug on GFX9. */
368 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
369 &eop_bug_offset, &fence_ptr);
370 cmd_buffer->gfx9_eop_bug_va =
371 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
372 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
373 }
374
375 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
376
377 return cmd_buffer->record_result;
378 }
379
380 static bool
381 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
382 uint64_t min_needed)
383 {
384 uint64_t new_size;
385 struct radeon_winsys_bo *bo;
386 struct radv_cmd_buffer_upload *upload;
387 struct radv_device *device = cmd_buffer->device;
388
389 new_size = MAX2(min_needed, 16 * 1024);
390 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
391
392 bo = device->ws->buffer_create(device->ws,
393 new_size, 4096,
394 RADEON_DOMAIN_GTT,
395 RADEON_FLAG_CPU_ACCESS|
396 RADEON_FLAG_NO_INTERPROCESS_SHARING |
397 RADEON_FLAG_32BIT,
398 RADV_BO_PRIORITY_UPLOAD_BUFFER);
399
400 if (!bo) {
401 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
402 return false;
403 }
404
405 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
406 if (cmd_buffer->upload.upload_bo) {
407 upload = malloc(sizeof(*upload));
408
409 if (!upload) {
410 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
411 device->ws->buffer_destroy(bo);
412 return false;
413 }
414
415 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
416 list_add(&upload->list, &cmd_buffer->upload.list);
417 }
418
419 cmd_buffer->upload.upload_bo = bo;
420 cmd_buffer->upload.size = new_size;
421 cmd_buffer->upload.offset = 0;
422 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
423
424 if (!cmd_buffer->upload.map) {
425 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
426 return false;
427 }
428
429 return true;
430 }
431
432 bool
433 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
434 unsigned size,
435 unsigned alignment,
436 unsigned *out_offset,
437 void **ptr)
438 {
439 assert(util_is_power_of_two_nonzero(alignment));
440
441 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
442 if (offset + size > cmd_buffer->upload.size) {
443 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
444 return false;
445 offset = 0;
446 }
447
448 *out_offset = offset;
449 *ptr = cmd_buffer->upload.map + offset;
450
451 cmd_buffer->upload.offset = offset + size;
452 return true;
453 }
454
455 bool
456 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
457 unsigned size, unsigned alignment,
458 const void *data, unsigned *out_offset)
459 {
460 uint8_t *ptr;
461
462 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
463 out_offset, (void **)&ptr))
464 return false;
465
466 if (ptr)
467 memcpy(ptr, data, size);
468
469 return true;
470 }
471
472 static void
473 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
474 unsigned count, const uint32_t *data)
475 {
476 struct radeon_cmdbuf *cs = cmd_buffer->cs;
477
478 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
479
480 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
481 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
482 S_370_WR_CONFIRM(1) |
483 S_370_ENGINE_SEL(V_370_ME));
484 radeon_emit(cs, va);
485 radeon_emit(cs, va >> 32);
486 radeon_emit_array(cs, data, count);
487 }
488
489 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
490 {
491 struct radv_device *device = cmd_buffer->device;
492 struct radeon_cmdbuf *cs = cmd_buffer->cs;
493 uint64_t va;
494
495 va = radv_buffer_get_va(device->trace_bo);
496 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
497 va += 4;
498
499 ++cmd_buffer->state.trace_id;
500 radv_emit_write_data_packet(cmd_buffer, va, 1,
501 &cmd_buffer->state.trace_id);
502
503 radeon_check_space(cmd_buffer->device->ws, cs, 2);
504
505 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
506 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
507 }
508
509 static void
510 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
511 enum radv_cmd_flush_bits flags)
512 {
513 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
514 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
515 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
516
517 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
518
519 /* Force wait for graphics or compute engines to be idle. */
520 si_cs_emit_cache_flush(cmd_buffer->cs,
521 cmd_buffer->device->physical_device->rad_info.chip_class,
522 &cmd_buffer->gfx9_fence_idx,
523 cmd_buffer->gfx9_fence_va,
524 radv_cmd_buffer_uses_mec(cmd_buffer),
525 flags, cmd_buffer->gfx9_eop_bug_va);
526 }
527
528 if (unlikely(cmd_buffer->device->trace_bo))
529 radv_cmd_buffer_trace_emit(cmd_buffer);
530 }
531
532 static void
533 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
534 struct radv_pipeline *pipeline, enum ring_type ring)
535 {
536 struct radv_device *device = cmd_buffer->device;
537 uint32_t data[2];
538 uint64_t va;
539
540 va = radv_buffer_get_va(device->trace_bo);
541
542 switch (ring) {
543 case RING_GFX:
544 va += 8;
545 break;
546 case RING_COMPUTE:
547 va += 16;
548 break;
549 default:
550 assert(!"invalid ring type");
551 }
552
553 data[0] = (uintptr_t)pipeline;
554 data[1] = (uintptr_t)pipeline >> 32;
555
556 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
557 }
558
559 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
560 VkPipelineBindPoint bind_point,
561 struct radv_descriptor_set *set,
562 unsigned idx)
563 {
564 struct radv_descriptor_state *descriptors_state =
565 radv_get_descriptors_state(cmd_buffer, bind_point);
566
567 descriptors_state->sets[idx] = set;
568
569 descriptors_state->valid |= (1u << idx); /* active descriptors */
570 descriptors_state->dirty |= (1u << idx);
571 }
572
573 static void
574 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
575 VkPipelineBindPoint bind_point)
576 {
577 struct radv_descriptor_state *descriptors_state =
578 radv_get_descriptors_state(cmd_buffer, bind_point);
579 struct radv_device *device = cmd_buffer->device;
580 uint32_t data[MAX_SETS * 2] = {};
581 uint64_t va;
582 unsigned i;
583 va = radv_buffer_get_va(device->trace_bo) + 24;
584
585 for_each_bit(i, descriptors_state->valid) {
586 struct radv_descriptor_set *set = descriptors_state->sets[i];
587 data[i * 2] = (uint64_t)(uintptr_t)set;
588 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
589 }
590
591 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
592 }
593
594 struct radv_userdata_info *
595 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
596 gl_shader_stage stage,
597 int idx)
598 {
599 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
600 return &shader->info.user_sgprs_locs.shader_data[idx];
601 }
602
603 static void
604 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
605 struct radv_pipeline *pipeline,
606 gl_shader_stage stage,
607 int idx, uint64_t va)
608 {
609 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
610 uint32_t base_reg = pipeline->user_data_0[stage];
611 if (loc->sgpr_idx == -1)
612 return;
613
614 assert(loc->num_sgprs == 1);
615
616 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
617 base_reg + loc->sgpr_idx * 4, va, false);
618 }
619
620 static void
621 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
622 struct radv_pipeline *pipeline,
623 struct radv_descriptor_state *descriptors_state,
624 gl_shader_stage stage)
625 {
626 struct radv_device *device = cmd_buffer->device;
627 struct radeon_cmdbuf *cs = cmd_buffer->cs;
628 uint32_t sh_base = pipeline->user_data_0[stage];
629 struct radv_userdata_locations *locs =
630 &pipeline->shaders[stage]->info.user_sgprs_locs;
631 unsigned mask = locs->descriptor_sets_enabled;
632
633 mask &= descriptors_state->dirty & descriptors_state->valid;
634
635 while (mask) {
636 int start, count;
637
638 u_bit_scan_consecutive_range(&mask, &start, &count);
639
640 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
641 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
642
643 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
644 for (int i = 0; i < count; i++) {
645 struct radv_descriptor_set *set =
646 descriptors_state->sets[start + i];
647
648 radv_emit_shader_pointer_body(device, cs, set->va, true);
649 }
650 }
651 }
652
653 /**
654 * Convert the user sample locations to hardware sample locations (the values
655 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
656 */
657 static void
658 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
659 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
660 {
661 uint32_t x_offset = x % state->grid_size.width;
662 uint32_t y_offset = y % state->grid_size.height;
663 uint32_t num_samples = (uint32_t)state->per_pixel;
664 VkSampleLocationEXT *user_locs;
665 uint32_t pixel_offset;
666
667 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
668
669 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
670 user_locs = &state->locations[pixel_offset];
671
672 for (uint32_t i = 0; i < num_samples; i++) {
673 float shifted_pos_x = user_locs[i].x - 0.5;
674 float shifted_pos_y = user_locs[i].y - 0.5;
675
676 int32_t scaled_pos_x = floor(shifted_pos_x * 16);
677 int32_t scaled_pos_y = floor(shifted_pos_y * 16);
678
679 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
680 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
681 }
682 }
683
684 /**
685 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
686 * locations.
687 */
688 static void
689 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
690 uint32_t *sample_locs_pixel)
691 {
692 for (uint32_t i = 0; i < num_samples; i++) {
693 uint32_t sample_reg_idx = i / 4;
694 uint32_t sample_loc_idx = i % 4;
695 int32_t pos_x = sample_locs[i].x;
696 int32_t pos_y = sample_locs[i].y;
697
698 uint32_t shift_x = 8 * sample_loc_idx;
699 uint32_t shift_y = shift_x + 4;
700
701 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
702 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
703 }
704 }
705
706 /**
707 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
708 * sample locations.
709 */
710 static uint64_t
711 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
712 VkOffset2D *sample_locs,
713 uint32_t num_samples)
714 {
715 uint32_t centroid_priorities[num_samples];
716 uint32_t sample_mask = num_samples - 1;
717 uint32_t distances[num_samples];
718 uint64_t centroid_priority = 0;
719
720 /* Compute the distances from center for each sample. */
721 for (int i = 0; i < num_samples; i++) {
722 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
723 (sample_locs[i].y * sample_locs[i].y);
724 }
725
726 /* Compute the centroid priorities by looking at the distances array. */
727 for (int i = 0; i < num_samples; i++) {
728 uint32_t min_idx = 0;
729
730 for (int j = 1; j < num_samples; j++) {
731 if (distances[j] < distances[min_idx])
732 min_idx = j;
733 }
734
735 centroid_priorities[i] = min_idx;
736 distances[min_idx] = 0xffffffff;
737 }
738
739 /* Compute the final centroid priority. */
740 for (int i = 0; i < 8; i++) {
741 centroid_priority |=
742 centroid_priorities[i & sample_mask] << (i * 4);
743 }
744
745 return centroid_priority << 32 | centroid_priority;
746 }
747
748 /**
749 * Emit the sample locations that are specified with VK_EXT_sample_locations.
750 */
751 static void
752 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
753 {
754 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
755 struct radv_multisample_state *ms = &pipeline->graphics.ms;
756 struct radv_sample_locations_state *sample_location =
757 &cmd_buffer->state.dynamic.sample_location;
758 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
759 struct radeon_cmdbuf *cs = cmd_buffer->cs;
760 uint32_t sample_locs_pixel[4][2] = {};
761 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
762 uint32_t max_sample_dist = 0;
763 uint64_t centroid_priority;
764
765 if (!cmd_buffer->state.dynamic.sample_location.count)
766 return;
767
768 /* Convert the user sample locations to hardware sample locations. */
769 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
770 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
771 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
772 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
773
774 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
775 for (uint32_t i = 0; i < 4; i++) {
776 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
777 sample_locs_pixel[i]);
778 }
779
780 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
781 centroid_priority =
782 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
783 num_samples);
784
785 /* Compute the maximum sample distance from the specified locations. */
786 for (uint32_t i = 0; i < num_samples; i++) {
787 VkOffset2D offset = sample_locs[0][i];
788 max_sample_dist = MAX2(max_sample_dist,
789 MAX2(abs(offset.x), abs(offset.y)));
790 }
791
792 /* Emit the specified user sample locations. */
793 switch (num_samples) {
794 case 2:
795 case 4:
796 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
797 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
798 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
799 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
800 break;
801 case 8:
802 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
803 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
804 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
805 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
806 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
807 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
808 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
809 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
810 break;
811 default:
812 unreachable("invalid number of samples");
813 }
814
815 /* Emit the maximum sample distance and the centroid priority. */
816 uint32_t pa_sc_aa_config = ms->pa_sc_aa_config;
817
818 pa_sc_aa_config &= C_028BE0_MAX_SAMPLE_DIST;
819 pa_sc_aa_config |= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist);
820
821 radeon_set_context_reg_seq(cs, R_028BE0_PA_SC_AA_CONFIG, 1);
822 radeon_emit(cs, pa_sc_aa_config);
823
824 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
825 radeon_emit(cs, centroid_priority);
826 radeon_emit(cs, centroid_priority >> 32);
827
828 /* GFX9: Flush DFSM when the AA mode changes. */
829 if (cmd_buffer->device->dfsm_allowed) {
830 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
831 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
832 }
833
834 cmd_buffer->state.context_roll_without_scissor_emitted = true;
835 }
836
837 static void
838 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
839 struct radv_pipeline *pipeline,
840 gl_shader_stage stage,
841 int idx, int count, uint32_t *values)
842 {
843 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
844 uint32_t base_reg = pipeline->user_data_0[stage];
845 if (loc->sgpr_idx == -1)
846 return;
847
848 assert(loc->num_sgprs == count);
849
850 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
851 radeon_emit_array(cmd_buffer->cs, values, count);
852 }
853
854 static void
855 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
856 struct radv_pipeline *pipeline)
857 {
858 int num_samples = pipeline->graphics.ms.num_samples;
859 struct radv_multisample_state *ms = &pipeline->graphics.ms;
860 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
861
862 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
863 cmd_buffer->sample_positions_needed = true;
864
865 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
866 return;
867
868 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
869 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
870 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
871
872 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
873
874 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
875
876 /* GFX9: Flush DFSM when the AA mode changes. */
877 if (cmd_buffer->device->dfsm_allowed) {
878 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
879 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
880 }
881
882 cmd_buffer->state.context_roll_without_scissor_emitted = true;
883 }
884
885 static void
886 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
887 struct radv_shader_variant *shader)
888 {
889 uint64_t va;
890
891 if (!shader)
892 return;
893
894 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
895
896 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
897 }
898
899 static void
900 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
901 struct radv_pipeline *pipeline,
902 bool vertex_stage_only)
903 {
904 struct radv_cmd_state *state = &cmd_buffer->state;
905 uint32_t mask = state->prefetch_L2_mask;
906
907 if (vertex_stage_only) {
908 /* Fast prefetch path for starting draws as soon as possible.
909 */
910 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
911 RADV_PREFETCH_VBO_DESCRIPTORS);
912 }
913
914 if (mask & RADV_PREFETCH_VS)
915 radv_emit_shader_prefetch(cmd_buffer,
916 pipeline->shaders[MESA_SHADER_VERTEX]);
917
918 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
919 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
920
921 if (mask & RADV_PREFETCH_TCS)
922 radv_emit_shader_prefetch(cmd_buffer,
923 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
924
925 if (mask & RADV_PREFETCH_TES)
926 radv_emit_shader_prefetch(cmd_buffer,
927 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
928
929 if (mask & RADV_PREFETCH_GS) {
930 radv_emit_shader_prefetch(cmd_buffer,
931 pipeline->shaders[MESA_SHADER_GEOMETRY]);
932 if (pipeline->gs_copy_shader)
933 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
934 }
935
936 if (mask & RADV_PREFETCH_PS)
937 radv_emit_shader_prefetch(cmd_buffer,
938 pipeline->shaders[MESA_SHADER_FRAGMENT]);
939
940 state->prefetch_L2_mask &= ~mask;
941 }
942
943 static void
944 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
945 {
946 if (!cmd_buffer->device->physical_device->rbplus_allowed)
947 return;
948
949 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
950 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
951 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
952
953 unsigned sx_ps_downconvert = 0;
954 unsigned sx_blend_opt_epsilon = 0;
955 unsigned sx_blend_opt_control = 0;
956
957 for (unsigned i = 0; i < subpass->color_count; ++i) {
958 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
959 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
960 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
961 continue;
962 }
963
964 int idx = subpass->color_attachments[i].attachment;
965 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
966
967 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
968 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
969 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
970 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
971
972 bool has_alpha, has_rgb;
973
974 /* Set if RGB and A are present. */
975 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
976
977 if (format == V_028C70_COLOR_8 ||
978 format == V_028C70_COLOR_16 ||
979 format == V_028C70_COLOR_32)
980 has_rgb = !has_alpha;
981 else
982 has_rgb = true;
983
984 /* Check the colormask and export format. */
985 if (!(colormask & 0x7))
986 has_rgb = false;
987 if (!(colormask & 0x8))
988 has_alpha = false;
989
990 if (spi_format == V_028714_SPI_SHADER_ZERO) {
991 has_rgb = false;
992 has_alpha = false;
993 }
994
995 /* Disable value checking for disabled channels. */
996 if (!has_rgb)
997 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
998 if (!has_alpha)
999 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1000
1001 /* Enable down-conversion for 32bpp and smaller formats. */
1002 switch (format) {
1003 case V_028C70_COLOR_8:
1004 case V_028C70_COLOR_8_8:
1005 case V_028C70_COLOR_8_8_8_8:
1006 /* For 1 and 2-channel formats, use the superset thereof. */
1007 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1008 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1009 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1010 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1011 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1012 }
1013 break;
1014
1015 case V_028C70_COLOR_5_6_5:
1016 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1017 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1018 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1019 }
1020 break;
1021
1022 case V_028C70_COLOR_1_5_5_5:
1023 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1024 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1025 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1026 }
1027 break;
1028
1029 case V_028C70_COLOR_4_4_4_4:
1030 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1031 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1032 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1033 }
1034 break;
1035
1036 case V_028C70_COLOR_32:
1037 if (swap == V_028C70_SWAP_STD &&
1038 spi_format == V_028714_SPI_SHADER_32_R)
1039 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1040 else if (swap == V_028C70_SWAP_ALT_REV &&
1041 spi_format == V_028714_SPI_SHADER_32_AR)
1042 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1043 break;
1044
1045 case V_028C70_COLOR_16:
1046 case V_028C70_COLOR_16_16:
1047 /* For 1-channel formats, use the superset thereof. */
1048 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1049 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1050 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1051 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1052 if (swap == V_028C70_SWAP_STD ||
1053 swap == V_028C70_SWAP_STD_REV)
1054 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1055 else
1056 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1057 }
1058 break;
1059
1060 case V_028C70_COLOR_10_11_11:
1061 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1062 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1063 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1064 }
1065 break;
1066
1067 case V_028C70_COLOR_2_10_10_10:
1068 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1069 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1070 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1071 }
1072 break;
1073 }
1074 }
1075
1076 for (unsigned i = subpass->color_count; i < 8; ++i) {
1077 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1078 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1079 }
1080 /* TODO: avoid redundantly setting context registers */
1081 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1082 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1083 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1084 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1085
1086 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1087 }
1088
1089 static void
1090 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1091 {
1092 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1093
1094 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1095 return;
1096
1097 radv_update_multisample_state(cmd_buffer, pipeline);
1098
1099 cmd_buffer->scratch_size_needed =
1100 MAX2(cmd_buffer->scratch_size_needed,
1101 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1102
1103 if (!cmd_buffer->state.emitted_pipeline ||
1104 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1105 pipeline->graphics.can_use_guardband)
1106 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1107
1108 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1109
1110 if (!cmd_buffer->state.emitted_pipeline ||
1111 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1112 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1113 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1114 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1115 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1116 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1117 }
1118
1119 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1120 if (!pipeline->shaders[i])
1121 continue;
1122
1123 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1124 pipeline->shaders[i]->bo);
1125 }
1126
1127 if (radv_pipeline_has_gs(pipeline) && pipeline->gs_copy_shader)
1128 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1129 pipeline->gs_copy_shader->bo);
1130
1131 if (unlikely(cmd_buffer->device->trace_bo))
1132 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1133
1134 cmd_buffer->state.emitted_pipeline = pipeline;
1135
1136 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1137 }
1138
1139 static void
1140 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1141 {
1142 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1143 cmd_buffer->state.dynamic.viewport.viewports);
1144 }
1145
1146 static void
1147 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1148 {
1149 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1150
1151 si_write_scissors(cmd_buffer->cs, 0, count,
1152 cmd_buffer->state.dynamic.scissor.scissors,
1153 cmd_buffer->state.dynamic.viewport.viewports,
1154 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1155
1156 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1157 }
1158
1159 static void
1160 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1161 {
1162 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1163 return;
1164
1165 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1166 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1167 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1168 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1169 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1170 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1171 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1172 }
1173 }
1174
1175 static void
1176 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1177 {
1178 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1179
1180 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1181 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1182 }
1183
1184 static void
1185 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1186 {
1187 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1188
1189 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1190 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1191 }
1192
1193 static void
1194 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1195 {
1196 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1197
1198 radeon_set_context_reg_seq(cmd_buffer->cs,
1199 R_028430_DB_STENCILREFMASK, 2);
1200 radeon_emit(cmd_buffer->cs,
1201 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1202 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1203 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1204 S_028430_STENCILOPVAL(1));
1205 radeon_emit(cmd_buffer->cs,
1206 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1207 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1208 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1209 S_028434_STENCILOPVAL_BF(1));
1210 }
1211
1212 static void
1213 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1214 {
1215 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1216
1217 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1218 fui(d->depth_bounds.min));
1219 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1220 fui(d->depth_bounds.max));
1221 }
1222
1223 static void
1224 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1225 {
1226 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1227 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1228 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1229
1230
1231 radeon_set_context_reg_seq(cmd_buffer->cs,
1232 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1233 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1234 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1235 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1236 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1237 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1238 }
1239
1240 static void
1241 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1242 int index,
1243 struct radv_attachment_info *att,
1244 struct radv_image_view *iview,
1245 VkImageLayout layout)
1246 {
1247 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1248 struct radv_color_buffer_info *cb = &att->cb;
1249 uint32_t cb_color_info = cb->cb_color_info;
1250 struct radv_image *image = iview->image;
1251
1252 if (!radv_layout_dcc_compressed(image, layout,
1253 radv_image_queue_family_mask(image,
1254 cmd_buffer->queue_family_index,
1255 cmd_buffer->queue_family_index))) {
1256 cb_color_info &= C_028C70_DCC_ENABLE;
1257 }
1258
1259 if (radv_image_is_tc_compat_cmask(image) &&
1260 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1261 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1262 /* If this bit is set, the FMASK decompression operation
1263 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1264 */
1265 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1266 }
1267
1268 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1269 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1270 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1271 radeon_emit(cmd_buffer->cs, 0);
1272 radeon_emit(cmd_buffer->cs, 0);
1273 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1274 radeon_emit(cmd_buffer->cs, cb_color_info);
1275 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1276 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1277 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1278 radeon_emit(cmd_buffer->cs, 0);
1279 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1280 radeon_emit(cmd_buffer->cs, 0);
1281
1282 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1283 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1284
1285 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1286 cb->cb_color_base >> 32);
1287 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1288 cb->cb_color_cmask >> 32);
1289 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1290 cb->cb_color_fmask >> 32);
1291 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1292 cb->cb_dcc_base >> 32);
1293 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1294 cb->cb_color_attrib2);
1295 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1296 cb->cb_color_attrib3);
1297 } else if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1298 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1299 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1300 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1301 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1302 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1303 radeon_emit(cmd_buffer->cs, cb_color_info);
1304 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1305 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1306 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1307 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1308 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1309 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1310
1311 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1312 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1313 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1314
1315 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1316 cb->cb_mrt_epitch);
1317 } else {
1318 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1319 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1320 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1321 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1322 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1323 radeon_emit(cmd_buffer->cs, cb_color_info);
1324 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1325 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1326 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1327 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1328 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1329 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1330
1331 if (is_vi) { /* DCC BASE */
1332 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1333 }
1334 }
1335
1336 if (radv_dcc_enabled(image, iview->base_mip)) {
1337 /* Drawing with DCC enabled also compresses colorbuffers. */
1338 VkImageSubresourceRange range = {
1339 .aspectMask = iview->aspect_mask,
1340 .baseMipLevel = iview->base_mip,
1341 .levelCount = iview->level_count,
1342 .baseArrayLayer = iview->base_layer,
1343 .layerCount = iview->layer_count,
1344 };
1345
1346 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1347 }
1348 }
1349
1350 static void
1351 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1352 struct radv_ds_buffer_info *ds,
1353 struct radv_image *image, VkImageLayout layout,
1354 bool requires_cond_exec)
1355 {
1356 uint32_t db_z_info = ds->db_z_info;
1357 uint32_t db_z_info_reg;
1358
1359 if (!radv_image_is_tc_compat_htile(image))
1360 return;
1361
1362 if (!radv_layout_has_htile(image, layout,
1363 radv_image_queue_family_mask(image,
1364 cmd_buffer->queue_family_index,
1365 cmd_buffer->queue_family_index))) {
1366 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1367 }
1368
1369 db_z_info &= C_028040_ZRANGE_PRECISION;
1370
1371 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1372 db_z_info_reg = R_028038_DB_Z_INFO;
1373 } else {
1374 db_z_info_reg = R_028040_DB_Z_INFO;
1375 }
1376
1377 /* When we don't know the last fast clear value we need to emit a
1378 * conditional packet that will eventually skip the following
1379 * SET_CONTEXT_REG packet.
1380 */
1381 if (requires_cond_exec) {
1382 uint64_t va = radv_buffer_get_va(image->bo);
1383 va += image->offset + image->tc_compat_zrange_offset;
1384
1385 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1386 radeon_emit(cmd_buffer->cs, va);
1387 radeon_emit(cmd_buffer->cs, va >> 32);
1388 radeon_emit(cmd_buffer->cs, 0);
1389 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1390 }
1391
1392 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1393 }
1394
1395 static void
1396 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1397 struct radv_ds_buffer_info *ds,
1398 struct radv_image *image,
1399 VkImageLayout layout)
1400 {
1401 uint32_t db_z_info = ds->db_z_info;
1402 uint32_t db_stencil_info = ds->db_stencil_info;
1403
1404 if (!radv_layout_has_htile(image, layout,
1405 radv_image_queue_family_mask(image,
1406 cmd_buffer->queue_family_index,
1407 cmd_buffer->queue_family_index))) {
1408 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1409 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1410 }
1411
1412 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1413 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1414
1415 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1416 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1417 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1418
1419 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1420 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1421 radeon_emit(cmd_buffer->cs, db_z_info);
1422 radeon_emit(cmd_buffer->cs, db_stencil_info);
1423 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1424 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1425 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1426 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1427
1428 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 5);
1429 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1430 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1431 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1432 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1433 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1434 } else if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1435 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1436 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1437 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1438 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1439
1440 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1441 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1442 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1443 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1444 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1445 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1446 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1447 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1448 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1449 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1450 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1451
1452 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1453 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1454 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1455 } else {
1456 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1457
1458 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1459 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1460 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1461 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1462 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1463 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1464 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1465 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1466 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1467 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1468
1469 }
1470
1471 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1472 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1473
1474 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1475 ds->pa_su_poly_offset_db_fmt_cntl);
1476 }
1477
1478 /**
1479 * Update the fast clear depth/stencil values if the image is bound as a
1480 * depth/stencil buffer.
1481 */
1482 static void
1483 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1484 struct radv_image *image,
1485 VkClearDepthStencilValue ds_clear_value,
1486 VkImageAspectFlags aspects)
1487 {
1488 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1489 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1490 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1491 struct radv_attachment_info *att;
1492 uint32_t att_idx;
1493
1494 if (!framebuffer || !subpass)
1495 return;
1496
1497 if (!subpass->depth_stencil_attachment)
1498 return;
1499
1500 att_idx = subpass->depth_stencil_attachment->attachment;
1501 att = &framebuffer->attachments[att_idx];
1502 if (att->attachment->image != image)
1503 return;
1504
1505 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1506 radeon_emit(cs, ds_clear_value.stencil);
1507 radeon_emit(cs, fui(ds_clear_value.depth));
1508
1509 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1510 * only needed when clearing Z to 0.0.
1511 */
1512 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1513 ds_clear_value.depth == 0.0) {
1514 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1515
1516 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1517 layout, false);
1518 }
1519
1520 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1521 }
1522
1523 /**
1524 * Set the clear depth/stencil values to the image's metadata.
1525 */
1526 static void
1527 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1528 struct radv_image *image,
1529 VkClearDepthStencilValue ds_clear_value,
1530 VkImageAspectFlags aspects)
1531 {
1532 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1533 uint64_t va = radv_buffer_get_va(image->bo);
1534 unsigned reg_offset = 0, reg_count = 0;
1535
1536 va += image->offset + image->clear_value_offset;
1537
1538 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1539 ++reg_count;
1540 } else {
1541 ++reg_offset;
1542 va += 4;
1543 }
1544 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1545 ++reg_count;
1546
1547 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, cmd_buffer->state.predicating));
1548 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1549 S_370_WR_CONFIRM(1) |
1550 S_370_ENGINE_SEL(V_370_PFP));
1551 radeon_emit(cs, va);
1552 radeon_emit(cs, va >> 32);
1553 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1554 radeon_emit(cs, ds_clear_value.stencil);
1555 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1556 radeon_emit(cs, fui(ds_clear_value.depth));
1557 }
1558
1559 /**
1560 * Update the TC-compat metadata value for this image.
1561 */
1562 static void
1563 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1564 struct radv_image *image,
1565 uint32_t value)
1566 {
1567 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1568 uint64_t va = radv_buffer_get_va(image->bo);
1569 va += image->offset + image->tc_compat_zrange_offset;
1570
1571 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1572 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1573 S_370_WR_CONFIRM(1) |
1574 S_370_ENGINE_SEL(V_370_PFP));
1575 radeon_emit(cs, va);
1576 radeon_emit(cs, va >> 32);
1577 radeon_emit(cs, value);
1578 }
1579
1580 static void
1581 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1582 struct radv_image *image,
1583 VkClearDepthStencilValue ds_clear_value)
1584 {
1585 uint32_t cond_val;
1586
1587 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1588 * depth clear value is 0.0f.
1589 */
1590 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1591
1592 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, cond_val);
1593 }
1594
1595 /**
1596 * Update the clear depth/stencil values for this image.
1597 */
1598 void
1599 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1600 struct radv_image *image,
1601 VkClearDepthStencilValue ds_clear_value,
1602 VkImageAspectFlags aspects)
1603 {
1604 assert(radv_image_has_htile(image));
1605
1606 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1607
1608 if (radv_image_is_tc_compat_htile(image) &&
1609 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1610 radv_update_tc_compat_zrange_metadata(cmd_buffer, image,
1611 ds_clear_value);
1612 }
1613
1614 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1615 aspects);
1616 }
1617
1618 /**
1619 * Load the clear depth/stencil values from the image's metadata.
1620 */
1621 static void
1622 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1623 struct radv_image *image)
1624 {
1625 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1626 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1627 uint64_t va = radv_buffer_get_va(image->bo);
1628 unsigned reg_offset = 0, reg_count = 0;
1629
1630 va += image->offset + image->clear_value_offset;
1631
1632 if (!radv_image_has_htile(image))
1633 return;
1634
1635 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1636 ++reg_count;
1637 } else {
1638 ++reg_offset;
1639 va += 4;
1640 }
1641 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1642 ++reg_count;
1643
1644 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1645
1646 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1647 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1648 radeon_emit(cs, va);
1649 radeon_emit(cs, va >> 32);
1650 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1651 radeon_emit(cs, reg_count);
1652 } else {
1653 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1654 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1655 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1656 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1657 radeon_emit(cs, va);
1658 radeon_emit(cs, va >> 32);
1659 radeon_emit(cs, reg >> 2);
1660 radeon_emit(cs, 0);
1661
1662 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1663 radeon_emit(cs, 0);
1664 }
1665 }
1666
1667 /*
1668 * With DCC some colors don't require CMASK elimination before being
1669 * used as a texture. This sets a predicate value to determine if the
1670 * cmask eliminate is required.
1671 */
1672 void
1673 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1674 struct radv_image *image,
1675 const VkImageSubresourceRange *range, bool value)
1676 {
1677 uint64_t pred_val = value;
1678 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
1679 uint32_t level_count = radv_get_levelCount(image, range);
1680 uint32_t count = 2 * level_count;
1681
1682 assert(radv_dcc_enabled(image, range->baseMipLevel));
1683
1684 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1685 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1686 S_370_WR_CONFIRM(1) |
1687 S_370_ENGINE_SEL(V_370_PFP));
1688 radeon_emit(cmd_buffer->cs, va);
1689 radeon_emit(cmd_buffer->cs, va >> 32);
1690
1691 for (uint32_t l = 0; l < level_count; l++) {
1692 radeon_emit(cmd_buffer->cs, pred_val);
1693 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1694 }
1695 }
1696
1697 /**
1698 * Update the DCC predicate to reflect the compression state.
1699 */
1700 void
1701 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1702 struct radv_image *image,
1703 const VkImageSubresourceRange *range, bool value)
1704 {
1705 uint64_t pred_val = value;
1706 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
1707 uint32_t level_count = radv_get_levelCount(image, range);
1708 uint32_t count = 2 * level_count;
1709
1710 assert(radv_dcc_enabled(image, range->baseMipLevel));
1711
1712 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1713 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1714 S_370_WR_CONFIRM(1) |
1715 S_370_ENGINE_SEL(V_370_PFP));
1716 radeon_emit(cmd_buffer->cs, va);
1717 radeon_emit(cmd_buffer->cs, va >> 32);
1718
1719 for (uint32_t l = 0; l < level_count; l++) {
1720 radeon_emit(cmd_buffer->cs, pred_val);
1721 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1722 }
1723 }
1724
1725 /**
1726 * Update the fast clear color values if the image is bound as a color buffer.
1727 */
1728 static void
1729 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1730 struct radv_image *image,
1731 int cb_idx,
1732 uint32_t color_values[2])
1733 {
1734 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1735 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1736 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1737 struct radv_attachment_info *att;
1738 uint32_t att_idx;
1739
1740 if (!framebuffer || !subpass)
1741 return;
1742
1743 att_idx = subpass->color_attachments[cb_idx].attachment;
1744 if (att_idx == VK_ATTACHMENT_UNUSED)
1745 return;
1746
1747 att = &framebuffer->attachments[att_idx];
1748 if (att->attachment->image != image)
1749 return;
1750
1751 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1752 radeon_emit(cs, color_values[0]);
1753 radeon_emit(cs, color_values[1]);
1754
1755 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1756 }
1757
1758 /**
1759 * Set the clear color values to the image's metadata.
1760 */
1761 static void
1762 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1763 struct radv_image *image,
1764 const VkImageSubresourceRange *range,
1765 uint32_t color_values[2])
1766 {
1767 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1768 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
1769 uint32_t level_count = radv_get_levelCount(image, range);
1770 uint32_t count = 2 * level_count;
1771
1772 assert(radv_image_has_cmask(image) ||
1773 radv_dcc_enabled(image, range->baseMipLevel));
1774
1775 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
1776 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1777 S_370_WR_CONFIRM(1) |
1778 S_370_ENGINE_SEL(V_370_PFP));
1779 radeon_emit(cs, va);
1780 radeon_emit(cs, va >> 32);
1781
1782 for (uint32_t l = 0; l < level_count; l++) {
1783 radeon_emit(cs, color_values[0]);
1784 radeon_emit(cs, color_values[1]);
1785 }
1786 }
1787
1788 /**
1789 * Update the clear color values for this image.
1790 */
1791 void
1792 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1793 const struct radv_image_view *iview,
1794 int cb_idx,
1795 uint32_t color_values[2])
1796 {
1797 struct radv_image *image = iview->image;
1798 VkImageSubresourceRange range = {
1799 .aspectMask = iview->aspect_mask,
1800 .baseMipLevel = iview->base_mip,
1801 .levelCount = iview->level_count,
1802 .baseArrayLayer = iview->base_layer,
1803 .layerCount = iview->layer_count,
1804 };
1805
1806 assert(radv_image_has_cmask(image) ||
1807 radv_dcc_enabled(image, iview->base_mip));
1808
1809 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
1810
1811 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1812 color_values);
1813 }
1814
1815 /**
1816 * Load the clear color values from the image's metadata.
1817 */
1818 static void
1819 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1820 struct radv_image_view *iview,
1821 int cb_idx)
1822 {
1823 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1824 struct radv_image *image = iview->image;
1825 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
1826
1827 if (!radv_image_has_cmask(image) &&
1828 !radv_dcc_enabled(image, iview->base_mip))
1829 return;
1830
1831 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1832
1833 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1834 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1835 radeon_emit(cs, va);
1836 radeon_emit(cs, va >> 32);
1837 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1838 radeon_emit(cs, 2);
1839 } else {
1840 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1841 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1842 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1843 COPY_DATA_COUNT_SEL);
1844 radeon_emit(cs, va);
1845 radeon_emit(cs, va >> 32);
1846 radeon_emit(cs, reg >> 2);
1847 radeon_emit(cs, 0);
1848
1849 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1850 radeon_emit(cs, 0);
1851 }
1852 }
1853
1854 static void
1855 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1856 {
1857 int i;
1858 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1859 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1860
1861 /* this may happen for inherited secondary recording */
1862 if (!framebuffer)
1863 return;
1864
1865 for (i = 0; i < 8; ++i) {
1866 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1867 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1868 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1869 continue;
1870 }
1871
1872 int idx = subpass->color_attachments[i].attachment;
1873 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1874 struct radv_image_view *iview = att->attachment;
1875 VkImageLayout layout = subpass->color_attachments[i].layout;
1876
1877 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1878
1879 assert(att->attachment->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
1880 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
1881 radv_emit_fb_color_state(cmd_buffer, i, att, iview, layout);
1882
1883 radv_load_color_clear_metadata(cmd_buffer, iview, i);
1884 }
1885
1886 if (subpass->depth_stencil_attachment) {
1887 int idx = subpass->depth_stencil_attachment->attachment;
1888 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1889 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1890 struct radv_image *image = att->attachment->image;
1891 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1892 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1893 cmd_buffer->queue_family_index,
1894 cmd_buffer->queue_family_index);
1895 /* We currently don't support writing decompressed HTILE */
1896 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1897 radv_layout_is_htile_compressed(image, layout, queue_mask));
1898
1899 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1900
1901 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1902 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1903 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1904 }
1905 radv_load_ds_clear_metadata(cmd_buffer, image);
1906 } else {
1907 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
1908 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1909 else
1910 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1911
1912 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1913 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1914 }
1915 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1916 S_028208_BR_X(framebuffer->width) |
1917 S_028208_BR_Y(framebuffer->height));
1918
1919 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
1920 bool disable_constant_encode =
1921 cmd_buffer->device->physical_device->has_dcc_constant_encode;
1922 enum chip_class chip_class =
1923 cmd_buffer->device->physical_device->rad_info.chip_class;
1924 uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
1925
1926 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
1927 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
1928 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
1929 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
1930 }
1931
1932 if (cmd_buffer->device->dfsm_allowed) {
1933 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1934 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1935 }
1936
1937 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1938 }
1939
1940 static void
1941 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1942 {
1943 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1944 struct radv_cmd_state *state = &cmd_buffer->state;
1945
1946 if (state->index_type != state->last_index_type) {
1947 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1948 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
1949 cs, R_03090C_VGT_INDEX_TYPE,
1950 2, state->index_type);
1951 } else {
1952 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1953 radeon_emit(cs, state->index_type);
1954 }
1955
1956 state->last_index_type = state->index_type;
1957 }
1958
1959 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1960 radeon_emit(cs, state->index_va);
1961 radeon_emit(cs, state->index_va >> 32);
1962
1963 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1964 radeon_emit(cs, state->max_index_count);
1965
1966 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1967 }
1968
1969 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1970 {
1971 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1972 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1973 uint32_t pa_sc_mode_cntl_1 =
1974 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1975 uint32_t db_count_control;
1976
1977 if(!cmd_buffer->state.active_occlusion_queries) {
1978 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1979 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1980 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1981 has_perfect_queries) {
1982 /* Re-enable out-of-order rasterization if the
1983 * bound pipeline supports it and if it's has
1984 * been disabled before starting any perfect
1985 * occlusion queries.
1986 */
1987 radeon_set_context_reg(cmd_buffer->cs,
1988 R_028A4C_PA_SC_MODE_CNTL_1,
1989 pa_sc_mode_cntl_1);
1990 }
1991 }
1992 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1993 } else {
1994 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1995 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1996
1997 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1998 db_count_control =
1999 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
2000 S_028004_SAMPLE_RATE(sample_rate) |
2001 S_028004_ZPASS_ENABLE(1) |
2002 S_028004_SLICE_EVEN_ENABLE(1) |
2003 S_028004_SLICE_ODD_ENABLE(1);
2004
2005 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2006 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2007 has_perfect_queries) {
2008 /* If the bound pipeline has enabled
2009 * out-of-order rasterization, we should
2010 * disable it before starting any perfect
2011 * occlusion queries.
2012 */
2013 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2014
2015 radeon_set_context_reg(cmd_buffer->cs,
2016 R_028A4C_PA_SC_MODE_CNTL_1,
2017 pa_sc_mode_cntl_1);
2018 }
2019 } else {
2020 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2021 S_028004_SAMPLE_RATE(sample_rate);
2022 }
2023 }
2024
2025 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2026
2027 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2028 }
2029
2030 static void
2031 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2032 {
2033 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2034
2035 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2036 radv_emit_viewport(cmd_buffer);
2037
2038 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2039 !cmd_buffer->device->physical_device->has_scissor_bug)
2040 radv_emit_scissor(cmd_buffer);
2041
2042 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2043 radv_emit_line_width(cmd_buffer);
2044
2045 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2046 radv_emit_blend_constants(cmd_buffer);
2047
2048 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2049 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2050 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2051 radv_emit_stencil(cmd_buffer);
2052
2053 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2054 radv_emit_depth_bounds(cmd_buffer);
2055
2056 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2057 radv_emit_depth_bias(cmd_buffer);
2058
2059 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2060 radv_emit_discard_rectangle(cmd_buffer);
2061
2062 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2063 radv_emit_sample_locations(cmd_buffer);
2064
2065 cmd_buffer->state.dirty &= ~states;
2066 }
2067
2068 static void
2069 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2070 VkPipelineBindPoint bind_point)
2071 {
2072 struct radv_descriptor_state *descriptors_state =
2073 radv_get_descriptors_state(cmd_buffer, bind_point);
2074 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2075 unsigned bo_offset;
2076
2077 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2078 set->mapped_ptr,
2079 &bo_offset))
2080 return;
2081
2082 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2083 set->va += bo_offset;
2084 }
2085
2086 static void
2087 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2088 VkPipelineBindPoint bind_point)
2089 {
2090 struct radv_descriptor_state *descriptors_state =
2091 radv_get_descriptors_state(cmd_buffer, bind_point);
2092 uint32_t size = MAX_SETS * 4;
2093 uint32_t offset;
2094 void *ptr;
2095
2096 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2097 256, &offset, &ptr))
2098 return;
2099
2100 for (unsigned i = 0; i < MAX_SETS; i++) {
2101 uint32_t *uptr = ((uint32_t *)ptr) + i;
2102 uint64_t set_va = 0;
2103 struct radv_descriptor_set *set = descriptors_state->sets[i];
2104 if (descriptors_state->valid & (1u << i))
2105 set_va = set->va;
2106 uptr[0] = set_va & 0xffffffff;
2107 }
2108
2109 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2110 va += offset;
2111
2112 if (cmd_buffer->state.pipeline) {
2113 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2114 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2115 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2116
2117 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2118 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2119 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2120
2121 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2122 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2123 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2124
2125 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2126 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2127 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2128
2129 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2130 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2131 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2132 }
2133
2134 if (cmd_buffer->state.compute_pipeline)
2135 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2136 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2137 }
2138
2139 static void
2140 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2141 VkShaderStageFlags stages)
2142 {
2143 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2144 VK_PIPELINE_BIND_POINT_COMPUTE :
2145 VK_PIPELINE_BIND_POINT_GRAPHICS;
2146 struct radv_descriptor_state *descriptors_state =
2147 radv_get_descriptors_state(cmd_buffer, bind_point);
2148 struct radv_cmd_state *state = &cmd_buffer->state;
2149 bool flush_indirect_descriptors;
2150
2151 if (!descriptors_state->dirty)
2152 return;
2153
2154 if (descriptors_state->push_dirty)
2155 radv_flush_push_descriptors(cmd_buffer, bind_point);
2156
2157 flush_indirect_descriptors =
2158 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2159 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2160 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2161 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2162
2163 if (flush_indirect_descriptors)
2164 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2165
2166 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2167 cmd_buffer->cs,
2168 MAX_SETS * MESA_SHADER_STAGES * 4);
2169
2170 if (cmd_buffer->state.pipeline) {
2171 radv_foreach_stage(stage, stages) {
2172 if (!cmd_buffer->state.pipeline->shaders[stage])
2173 continue;
2174
2175 radv_emit_descriptor_pointers(cmd_buffer,
2176 cmd_buffer->state.pipeline,
2177 descriptors_state, stage);
2178 }
2179 }
2180
2181 if (cmd_buffer->state.compute_pipeline &&
2182 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2183 radv_emit_descriptor_pointers(cmd_buffer,
2184 cmd_buffer->state.compute_pipeline,
2185 descriptors_state,
2186 MESA_SHADER_COMPUTE);
2187 }
2188
2189 descriptors_state->dirty = 0;
2190 descriptors_state->push_dirty = false;
2191
2192 assert(cmd_buffer->cs->cdw <= cdw_max);
2193
2194 if (unlikely(cmd_buffer->device->trace_bo))
2195 radv_save_descriptors(cmd_buffer, bind_point);
2196 }
2197
2198 static void
2199 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2200 VkShaderStageFlags stages)
2201 {
2202 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2203 ? cmd_buffer->state.compute_pipeline
2204 : cmd_buffer->state.pipeline;
2205 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2206 VK_PIPELINE_BIND_POINT_COMPUTE :
2207 VK_PIPELINE_BIND_POINT_GRAPHICS;
2208 struct radv_descriptor_state *descriptors_state =
2209 radv_get_descriptors_state(cmd_buffer, bind_point);
2210 struct radv_pipeline_layout *layout = pipeline->layout;
2211 struct radv_shader_variant *shader, *prev_shader;
2212 bool need_push_constants = false;
2213 unsigned offset;
2214 void *ptr;
2215 uint64_t va;
2216
2217 stages &= cmd_buffer->push_constant_stages;
2218 if (!stages ||
2219 (!layout->push_constant_size && !layout->dynamic_offset_count))
2220 return;
2221
2222 radv_foreach_stage(stage, stages) {
2223 if (!pipeline->shaders[stage])
2224 continue;
2225
2226 need_push_constants |= pipeline->shaders[stage]->info.info.loads_push_constants;
2227 need_push_constants |= pipeline->shaders[stage]->info.info.loads_dynamic_offsets;
2228
2229 uint8_t base = pipeline->shaders[stage]->info.info.base_inline_push_consts;
2230 uint8_t count = pipeline->shaders[stage]->info.info.num_inline_push_consts;
2231
2232 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2233 AC_UD_INLINE_PUSH_CONSTANTS,
2234 count,
2235 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2236 }
2237
2238 if (need_push_constants) {
2239 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2240 16 * layout->dynamic_offset_count,
2241 256, &offset, &ptr))
2242 return;
2243
2244 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2245 memcpy((char*)ptr + layout->push_constant_size,
2246 descriptors_state->dynamic_buffers,
2247 16 * layout->dynamic_offset_count);
2248
2249 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2250 va += offset;
2251
2252 MAYBE_UNUSED unsigned cdw_max =
2253 radeon_check_space(cmd_buffer->device->ws,
2254 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2255
2256 prev_shader = NULL;
2257 radv_foreach_stage(stage, stages) {
2258 shader = radv_get_shader(pipeline, stage);
2259
2260 /* Avoid redundantly emitting the address for merged stages. */
2261 if (shader && shader != prev_shader) {
2262 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2263 AC_UD_PUSH_CONSTANTS, va);
2264
2265 prev_shader = shader;
2266 }
2267 }
2268 assert(cmd_buffer->cs->cdw <= cdw_max);
2269 }
2270
2271 cmd_buffer->push_constant_stages &= ~stages;
2272 }
2273
2274 static void
2275 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2276 bool pipeline_is_dirty)
2277 {
2278 if ((pipeline_is_dirty ||
2279 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2280 cmd_buffer->state.pipeline->num_vertex_bindings &&
2281 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
2282 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
2283 unsigned vb_offset;
2284 void *vb_ptr;
2285 uint32_t i = 0;
2286 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2287 uint64_t va;
2288
2289 /* allocate some descriptor state for vertex buffers */
2290 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2291 &vb_offset, &vb_ptr))
2292 return;
2293
2294 for (i = 0; i < count; i++) {
2295 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2296 uint32_t offset;
2297 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2298 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2299
2300 if (!buffer)
2301 continue;
2302
2303 va = radv_buffer_get_va(buffer->bo);
2304
2305 offset = cmd_buffer->vertex_bindings[i].offset;
2306 va += offset + buffer->offset;
2307 desc[0] = va;
2308 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2309 if (cmd_buffer->device->physical_device->rad_info.chip_class <= GFX7 && stride)
2310 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
2311 else
2312 desc[2] = buffer->size - offset;
2313 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2314 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2315 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2316 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2317
2318 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2319 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
2320 S_008F0C_OOB_SELECT(1) |
2321 S_008F0C_RESOURCE_LEVEL(1);
2322 } else {
2323 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2324 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2325 }
2326 }
2327
2328 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2329 va += vb_offset;
2330
2331 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2332 AC_UD_VS_VERTEX_BUFFERS, va);
2333
2334 cmd_buffer->state.vb_va = va;
2335 cmd_buffer->state.vb_size = count * 16;
2336 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2337 }
2338 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2339 }
2340
2341 static void
2342 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2343 {
2344 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2345 struct radv_userdata_info *loc;
2346 uint32_t base_reg;
2347
2348 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2349 if (!radv_get_shader(pipeline, stage))
2350 continue;
2351
2352 loc = radv_lookup_user_sgpr(pipeline, stage,
2353 AC_UD_STREAMOUT_BUFFERS);
2354 if (loc->sgpr_idx == -1)
2355 continue;
2356
2357 base_reg = pipeline->user_data_0[stage];
2358
2359 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2360 base_reg + loc->sgpr_idx * 4, va, false);
2361 }
2362
2363 if (pipeline->gs_copy_shader) {
2364 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2365 if (loc->sgpr_idx != -1) {
2366 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2367
2368 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2369 base_reg + loc->sgpr_idx * 4, va, false);
2370 }
2371 }
2372 }
2373
2374 static void
2375 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2376 {
2377 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2378 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2379 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2380 unsigned so_offset;
2381 void *so_ptr;
2382 uint64_t va;
2383
2384 /* Allocate some descriptor state for streamout buffers. */
2385 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2386 MAX_SO_BUFFERS * 16, 256,
2387 &so_offset, &so_ptr))
2388 return;
2389
2390 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2391 struct radv_buffer *buffer = sb[i].buffer;
2392 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2393
2394 if (!(so->enabled_mask & (1 << i)))
2395 continue;
2396
2397 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2398
2399 va += sb[i].offset;
2400
2401 /* Set the descriptor.
2402 *
2403 * On GFX8, the format must be non-INVALID, otherwise
2404 * the buffer will be considered not bound and store
2405 * instructions will be no-ops.
2406 */
2407 desc[0] = va;
2408 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2409 desc[2] = 0xffffffff;
2410 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2411 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2412 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2413 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2414 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2415 }
2416
2417 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2418 va += so_offset;
2419
2420 radv_emit_streamout_buffers(cmd_buffer, va);
2421 }
2422
2423 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2424 }
2425
2426 static void
2427 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2428 {
2429 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2430 radv_flush_streamout_descriptors(cmd_buffer);
2431 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2432 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2433 }
2434
2435 struct radv_draw_info {
2436 /**
2437 * Number of vertices.
2438 */
2439 uint32_t count;
2440
2441 /**
2442 * Index of the first vertex.
2443 */
2444 int32_t vertex_offset;
2445
2446 /**
2447 * First instance id.
2448 */
2449 uint32_t first_instance;
2450
2451 /**
2452 * Number of instances.
2453 */
2454 uint32_t instance_count;
2455
2456 /**
2457 * First index (indexed draws only).
2458 */
2459 uint32_t first_index;
2460
2461 /**
2462 * Whether it's an indexed draw.
2463 */
2464 bool indexed;
2465
2466 /**
2467 * Indirect draw parameters resource.
2468 */
2469 struct radv_buffer *indirect;
2470 uint64_t indirect_offset;
2471 uint32_t stride;
2472
2473 /**
2474 * Draw count parameters resource.
2475 */
2476 struct radv_buffer *count_buffer;
2477 uint64_t count_buffer_offset;
2478
2479 /**
2480 * Stream output parameters resource.
2481 */
2482 struct radv_buffer *strmout_buffer;
2483 uint64_t strmout_buffer_offset;
2484 };
2485
2486 static void
2487 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
2488 bool instanced_draw, bool indirect_draw,
2489 bool count_from_stream_output,
2490 uint32_t draw_vertex_count)
2491 {
2492 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2493 struct radv_cmd_state *state = &cmd_buffer->state;
2494 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2495 unsigned ia_multi_vgt_param;
2496
2497 ia_multi_vgt_param =
2498 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2499 indirect_draw,
2500 count_from_stream_output,
2501 draw_vertex_count);
2502
2503 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2504 if (info->chip_class >= GFX9) {
2505 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2506 cs,
2507 R_030960_IA_MULTI_VGT_PARAM,
2508 4, ia_multi_vgt_param);
2509 } else if (info->chip_class >= GFX7) {
2510 radeon_set_context_reg_idx(cs,
2511 R_028AA8_IA_MULTI_VGT_PARAM,
2512 1, ia_multi_vgt_param);
2513 } else {
2514 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2515 ia_multi_vgt_param);
2516 }
2517 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2518 }
2519 }
2520
2521 static void
2522 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2523 const struct radv_draw_info *draw_info)
2524 {
2525 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2526 struct radv_cmd_state *state = &cmd_buffer->state;
2527 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2528 int32_t primitive_reset_en;
2529
2530 /* Draw state. */
2531 if (info->chip_class < GFX10) {
2532 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2533 draw_info->indirect,
2534 !!draw_info->strmout_buffer,
2535 draw_info->indirect ? 0 : draw_info->count);
2536 }
2537
2538 /* Primitive restart. */
2539 primitive_reset_en =
2540 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2541
2542 if (primitive_reset_en != state->last_primitive_reset_en) {
2543 state->last_primitive_reset_en = primitive_reset_en;
2544 if (info->chip_class >= GFX9) {
2545 radeon_set_uconfig_reg(cs,
2546 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2547 primitive_reset_en);
2548 } else {
2549 radeon_set_context_reg(cs,
2550 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2551 primitive_reset_en);
2552 }
2553 }
2554
2555 if (primitive_reset_en) {
2556 uint32_t primitive_reset_index =
2557 state->index_type ? 0xffffffffu : 0xffffu;
2558
2559 if (primitive_reset_index != state->last_primitive_reset_index) {
2560 radeon_set_context_reg(cs,
2561 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2562 primitive_reset_index);
2563 state->last_primitive_reset_index = primitive_reset_index;
2564 }
2565 }
2566
2567 if (draw_info->strmout_buffer) {
2568 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2569
2570 va += draw_info->strmout_buffer->offset +
2571 draw_info->strmout_buffer_offset;
2572
2573 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2574 draw_info->stride);
2575
2576 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2577 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2578 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2579 COPY_DATA_WR_CONFIRM);
2580 radeon_emit(cs, va);
2581 radeon_emit(cs, va >> 32);
2582 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2583 radeon_emit(cs, 0); /* unused */
2584
2585 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2586 }
2587 }
2588
2589 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2590 VkPipelineStageFlags src_stage_mask)
2591 {
2592 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2593 VK_PIPELINE_STAGE_TRANSFER_BIT |
2594 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2595 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2596 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2597 }
2598
2599 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2600 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2601 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2602 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2603 VK_PIPELINE_STAGE_TRANSFER_BIT |
2604 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2605 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2606 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2607 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2608 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2609 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2610 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2611 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2612 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2613 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2614 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2615 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2616 }
2617 }
2618
2619 static enum radv_cmd_flush_bits
2620 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2621 VkAccessFlags src_flags,
2622 struct radv_image *image)
2623 {
2624 bool flush_CB_meta = true, flush_DB_meta = true;
2625 enum radv_cmd_flush_bits flush_bits = 0;
2626 uint32_t b;
2627
2628 if (image) {
2629 if (!radv_image_has_CB_metadata(image))
2630 flush_CB_meta = false;
2631 if (!radv_image_has_htile(image))
2632 flush_DB_meta = false;
2633 }
2634
2635 for_each_bit(b, src_flags) {
2636 switch ((VkAccessFlagBits)(1 << b)) {
2637 case VK_ACCESS_SHADER_WRITE_BIT:
2638 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2639 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2640 flush_bits |= RADV_CMD_FLAG_WB_L2;
2641 break;
2642 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2643 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2644 if (flush_CB_meta)
2645 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2646 break;
2647 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2648 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2649 if (flush_DB_meta)
2650 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2651 break;
2652 case VK_ACCESS_TRANSFER_WRITE_BIT:
2653 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2654 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2655 RADV_CMD_FLAG_INV_L2;
2656
2657 if (flush_CB_meta)
2658 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2659 if (flush_DB_meta)
2660 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2661 break;
2662 default:
2663 break;
2664 }
2665 }
2666 return flush_bits;
2667 }
2668
2669 static enum radv_cmd_flush_bits
2670 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2671 VkAccessFlags dst_flags,
2672 struct radv_image *image)
2673 {
2674 bool flush_CB_meta = true, flush_DB_meta = true;
2675 enum radv_cmd_flush_bits flush_bits = 0;
2676 bool flush_CB = true, flush_DB = true;
2677 bool image_is_coherent = false;
2678 uint32_t b;
2679
2680 if (image) {
2681 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2682 flush_CB = false;
2683 flush_DB = false;
2684 }
2685
2686 if (!radv_image_has_CB_metadata(image))
2687 flush_CB_meta = false;
2688 if (!radv_image_has_htile(image))
2689 flush_DB_meta = false;
2690
2691 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2692 if (image->info.samples == 1 &&
2693 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2694 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2695 !vk_format_is_stencil(image->vk_format)) {
2696 /* Single-sample color and single-sample depth
2697 * (not stencil) are coherent with shaders on
2698 * GFX9.
2699 */
2700 image_is_coherent = true;
2701 }
2702 }
2703 }
2704
2705 for_each_bit(b, dst_flags) {
2706 switch ((VkAccessFlagBits)(1 << b)) {
2707 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2708 case VK_ACCESS_INDEX_READ_BIT:
2709 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2710 break;
2711 case VK_ACCESS_UNIFORM_READ_BIT:
2712 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
2713 break;
2714 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2715 case VK_ACCESS_TRANSFER_READ_BIT:
2716 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2717 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
2718 RADV_CMD_FLAG_INV_L2;
2719 break;
2720 case VK_ACCESS_SHADER_READ_BIT:
2721 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
2722
2723 if (!image_is_coherent)
2724 flush_bits |= RADV_CMD_FLAG_INV_L2;
2725 break;
2726 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2727 if (flush_CB)
2728 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2729 if (flush_CB_meta)
2730 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2731 break;
2732 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2733 if (flush_DB)
2734 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2735 if (flush_DB_meta)
2736 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2737 break;
2738 default:
2739 break;
2740 }
2741 }
2742 return flush_bits;
2743 }
2744
2745 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2746 const struct radv_subpass_barrier *barrier)
2747 {
2748 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2749 NULL);
2750 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2751 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2752 NULL);
2753 }
2754
2755 uint32_t
2756 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
2757 {
2758 struct radv_cmd_state *state = &cmd_buffer->state;
2759 uint32_t subpass_id = state->subpass - state->pass->subpasses;
2760
2761 /* The id of this subpass shouldn't exceed the number of subpasses in
2762 * this render pass minus 1.
2763 */
2764 assert(subpass_id < state->pass->subpass_count);
2765 return subpass_id;
2766 }
2767
2768 static struct radv_sample_locations_state *
2769 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2770 uint32_t att_idx,
2771 bool begin_subpass)
2772 {
2773 struct radv_cmd_state *state = &cmd_buffer->state;
2774 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
2775 struct radv_image_view *view = state->framebuffer->attachments[att_idx].attachment;
2776
2777 if (view->image->info.samples == 1)
2778 return NULL;
2779
2780 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
2781 /* Return the initial sample locations if this is the initial
2782 * layout transition of the given subpass attachemnt.
2783 */
2784 if (state->attachments[att_idx].sample_location.count > 0)
2785 return &state->attachments[att_idx].sample_location;
2786 } else {
2787 /* Otherwise return the subpass sample locations if defined. */
2788 if (state->subpass_sample_locs) {
2789 /* Because the driver sets the current subpass before
2790 * initial layout transitions, we should use the sample
2791 * locations from the previous subpass to avoid an
2792 * off-by-one problem. Otherwise, use the sample
2793 * locations for the current subpass for final layout
2794 * transitions.
2795 */
2796 if (begin_subpass)
2797 subpass_id--;
2798
2799 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
2800 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
2801 return &state->subpass_sample_locs[i].sample_location;
2802 }
2803 }
2804 }
2805
2806 return NULL;
2807 }
2808
2809 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2810 struct radv_subpass_attachment att,
2811 bool begin_subpass)
2812 {
2813 unsigned idx = att.attachment;
2814 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2815 struct radv_sample_locations_state *sample_locs;
2816 VkImageSubresourceRange range;
2817 range.aspectMask = 0;
2818 range.baseMipLevel = view->base_mip;
2819 range.levelCount = 1;
2820 range.baseArrayLayer = view->base_layer;
2821 range.layerCount = cmd_buffer->state.framebuffer->layers;
2822
2823 if (cmd_buffer->state.subpass->view_mask) {
2824 /* If the current subpass uses multiview, the driver might have
2825 * performed a fast color/depth clear to the whole image
2826 * (including all layers). To make sure the driver will
2827 * decompress the image correctly (if needed), we have to
2828 * account for the "real" number of layers. If the view mask is
2829 * sparse, this will decompress more layers than needed.
2830 */
2831 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
2832 }
2833
2834 /* Get the subpass sample locations for the given attachment, if NULL
2835 * is returned the driver will use the default HW locations.
2836 */
2837 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
2838 begin_subpass);
2839
2840 radv_handle_image_transition(cmd_buffer,
2841 view->image,
2842 cmd_buffer->state.attachments[idx].current_layout,
2843 att.layout, 0, 0, &range, sample_locs);
2844
2845 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2846
2847
2848 }
2849
2850 void
2851 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2852 const struct radv_subpass *subpass)
2853 {
2854 cmd_buffer->state.subpass = subpass;
2855
2856 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2857 }
2858
2859 static VkResult
2860 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2861 struct radv_render_pass *pass,
2862 const VkRenderPassBeginInfo *info)
2863 {
2864 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
2865 vk_find_struct_const(info->pNext,
2866 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
2867 struct radv_cmd_state *state = &cmd_buffer->state;
2868 struct radv_framebuffer *framebuffer = state->framebuffer;
2869
2870 if (!sample_locs) {
2871 state->subpass_sample_locs = NULL;
2872 return VK_SUCCESS;
2873 }
2874
2875 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
2876 const VkAttachmentSampleLocationsEXT *att_sample_locs =
2877 &sample_locs->pAttachmentInitialSampleLocations[i];
2878 uint32_t att_idx = att_sample_locs->attachmentIndex;
2879 struct radv_attachment_info *att = &framebuffer->attachments[att_idx];
2880 struct radv_image *image = att->attachment->image;
2881
2882 assert(vk_format_is_depth_or_stencil(image->vk_format));
2883
2884 /* From the Vulkan spec 1.1.108:
2885 *
2886 * "If the image referenced by the framebuffer attachment at
2887 * index attachmentIndex was not created with
2888 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
2889 * then the values specified in sampleLocationsInfo are
2890 * ignored."
2891 */
2892 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
2893 continue;
2894
2895 const VkSampleLocationsInfoEXT *sample_locs_info =
2896 &att_sample_locs->sampleLocationsInfo;
2897
2898 state->attachments[att_idx].sample_location.per_pixel =
2899 sample_locs_info->sampleLocationsPerPixel;
2900 state->attachments[att_idx].sample_location.grid_size =
2901 sample_locs_info->sampleLocationGridSize;
2902 state->attachments[att_idx].sample_location.count =
2903 sample_locs_info->sampleLocationsCount;
2904 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
2905 sample_locs_info->pSampleLocations,
2906 sample_locs_info->sampleLocationsCount);
2907 }
2908
2909 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
2910 sample_locs->postSubpassSampleLocationsCount *
2911 sizeof(state->subpass_sample_locs[0]),
2912 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2913 if (state->subpass_sample_locs == NULL) {
2914 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2915 return cmd_buffer->record_result;
2916 }
2917
2918 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
2919
2920 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
2921 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
2922 &sample_locs->pPostSubpassSampleLocations[i];
2923 const VkSampleLocationsInfoEXT *sample_locs_info =
2924 &subpass_sample_locs_info->sampleLocationsInfo;
2925
2926 state->subpass_sample_locs[i].subpass_idx =
2927 subpass_sample_locs_info->subpassIndex;
2928 state->subpass_sample_locs[i].sample_location.per_pixel =
2929 sample_locs_info->sampleLocationsPerPixel;
2930 state->subpass_sample_locs[i].sample_location.grid_size =
2931 sample_locs_info->sampleLocationGridSize;
2932 state->subpass_sample_locs[i].sample_location.count =
2933 sample_locs_info->sampleLocationsCount;
2934 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
2935 sample_locs_info->pSampleLocations,
2936 sample_locs_info->sampleLocationsCount);
2937 }
2938
2939 return VK_SUCCESS;
2940 }
2941
2942 static VkResult
2943 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2944 struct radv_render_pass *pass,
2945 const VkRenderPassBeginInfo *info)
2946 {
2947 struct radv_cmd_state *state = &cmd_buffer->state;
2948
2949 if (pass->attachment_count == 0) {
2950 state->attachments = NULL;
2951 return VK_SUCCESS;
2952 }
2953
2954 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2955 pass->attachment_count *
2956 sizeof(state->attachments[0]),
2957 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2958 if (state->attachments == NULL) {
2959 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2960 return cmd_buffer->record_result;
2961 }
2962
2963 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2964 struct radv_render_pass_attachment *att = &pass->attachments[i];
2965 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2966 VkImageAspectFlags clear_aspects = 0;
2967
2968 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2969 /* color attachment */
2970 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2971 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2972 }
2973 } else {
2974 /* depthstencil attachment */
2975 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2976 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2977 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2978 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2979 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2980 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2981 }
2982 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2983 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2984 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2985 }
2986 }
2987
2988 state->attachments[i].pending_clear_aspects = clear_aspects;
2989 state->attachments[i].cleared_views = 0;
2990 if (clear_aspects && info) {
2991 assert(info->clearValueCount > i);
2992 state->attachments[i].clear_value = info->pClearValues[i];
2993 }
2994
2995 state->attachments[i].current_layout = att->initial_layout;
2996 state->attachments[i].sample_location.count = 0;
2997 }
2998
2999 return VK_SUCCESS;
3000 }
3001
3002 VkResult radv_AllocateCommandBuffers(
3003 VkDevice _device,
3004 const VkCommandBufferAllocateInfo *pAllocateInfo,
3005 VkCommandBuffer *pCommandBuffers)
3006 {
3007 RADV_FROM_HANDLE(radv_device, device, _device);
3008 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
3009
3010 VkResult result = VK_SUCCESS;
3011 uint32_t i;
3012
3013 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
3014
3015 if (!list_empty(&pool->free_cmd_buffers)) {
3016 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
3017
3018 list_del(&cmd_buffer->pool_link);
3019 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
3020
3021 result = radv_reset_cmd_buffer(cmd_buffer);
3022 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
3023 cmd_buffer->level = pAllocateInfo->level;
3024
3025 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
3026 } else {
3027 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
3028 &pCommandBuffers[i]);
3029 }
3030 if (result != VK_SUCCESS)
3031 break;
3032 }
3033
3034 if (result != VK_SUCCESS) {
3035 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
3036 i, pCommandBuffers);
3037
3038 /* From the Vulkan 1.0.66 spec:
3039 *
3040 * "vkAllocateCommandBuffers can be used to create multiple
3041 * command buffers. If the creation of any of those command
3042 * buffers fails, the implementation must destroy all
3043 * successfully created command buffer objects from this
3044 * command, set all entries of the pCommandBuffers array to
3045 * NULL and return the error."
3046 */
3047 memset(pCommandBuffers, 0,
3048 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
3049 }
3050
3051 return result;
3052 }
3053
3054 void radv_FreeCommandBuffers(
3055 VkDevice device,
3056 VkCommandPool commandPool,
3057 uint32_t commandBufferCount,
3058 const VkCommandBuffer *pCommandBuffers)
3059 {
3060 for (uint32_t i = 0; i < commandBufferCount; i++) {
3061 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
3062
3063 if (cmd_buffer) {
3064 if (cmd_buffer->pool) {
3065 list_del(&cmd_buffer->pool_link);
3066 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3067 } else
3068 radv_cmd_buffer_destroy(cmd_buffer);
3069
3070 }
3071 }
3072 }
3073
3074 VkResult radv_ResetCommandBuffer(
3075 VkCommandBuffer commandBuffer,
3076 VkCommandBufferResetFlags flags)
3077 {
3078 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3079 return radv_reset_cmd_buffer(cmd_buffer);
3080 }
3081
3082 VkResult radv_BeginCommandBuffer(
3083 VkCommandBuffer commandBuffer,
3084 const VkCommandBufferBeginInfo *pBeginInfo)
3085 {
3086 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3087 VkResult result = VK_SUCCESS;
3088
3089 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3090 /* If the command buffer has already been resetted with
3091 * vkResetCommandBuffer, no need to do it again.
3092 */
3093 result = radv_reset_cmd_buffer(cmd_buffer);
3094 if (result != VK_SUCCESS)
3095 return result;
3096 }
3097
3098 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3099 cmd_buffer->state.last_primitive_reset_en = -1;
3100 cmd_buffer->state.last_index_type = -1;
3101 cmd_buffer->state.last_num_instances = -1;
3102 cmd_buffer->state.last_vertex_offset = -1;
3103 cmd_buffer->state.last_first_instance = -1;
3104 cmd_buffer->state.predication_type = -1;
3105 cmd_buffer->usage_flags = pBeginInfo->flags;
3106
3107 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3108 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3109 assert(pBeginInfo->pInheritanceInfo);
3110 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3111 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3112
3113 struct radv_subpass *subpass =
3114 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3115
3116 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3117 if (result != VK_SUCCESS)
3118 return result;
3119
3120 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3121 }
3122
3123 if (unlikely(cmd_buffer->device->trace_bo)) {
3124 struct radv_device *device = cmd_buffer->device;
3125
3126 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
3127 device->trace_bo);
3128
3129 radv_cmd_buffer_trace_emit(cmd_buffer);
3130 }
3131
3132 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3133
3134 return result;
3135 }
3136
3137 void radv_CmdBindVertexBuffers(
3138 VkCommandBuffer commandBuffer,
3139 uint32_t firstBinding,
3140 uint32_t bindingCount,
3141 const VkBuffer* pBuffers,
3142 const VkDeviceSize* pOffsets)
3143 {
3144 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3145 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3146 bool changed = false;
3147
3148 /* We have to defer setting up vertex buffer since we need the buffer
3149 * stride from the pipeline. */
3150
3151 assert(firstBinding + bindingCount <= MAX_VBS);
3152 for (uint32_t i = 0; i < bindingCount; i++) {
3153 uint32_t idx = firstBinding + i;
3154
3155 if (!changed &&
3156 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
3157 vb[idx].offset != pOffsets[i])) {
3158 changed = true;
3159 }
3160
3161 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
3162 vb[idx].offset = pOffsets[i];
3163
3164 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3165 vb[idx].buffer->bo);
3166 }
3167
3168 if (!changed) {
3169 /* No state changes. */
3170 return;
3171 }
3172
3173 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3174 }
3175
3176 void radv_CmdBindIndexBuffer(
3177 VkCommandBuffer commandBuffer,
3178 VkBuffer buffer,
3179 VkDeviceSize offset,
3180 VkIndexType indexType)
3181 {
3182 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3183 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3184
3185 if (cmd_buffer->state.index_buffer == index_buffer &&
3186 cmd_buffer->state.index_offset == offset &&
3187 cmd_buffer->state.index_type == indexType) {
3188 /* No state changes. */
3189 return;
3190 }
3191
3192 cmd_buffer->state.index_buffer = index_buffer;
3193 cmd_buffer->state.index_offset = offset;
3194 cmd_buffer->state.index_type = indexType; /* vk matches hw */
3195 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3196 cmd_buffer->state.index_va += index_buffer->offset + offset;
3197
3198 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
3199 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
3200 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3201 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3202 }
3203
3204
3205 static void
3206 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3207 VkPipelineBindPoint bind_point,
3208 struct radv_descriptor_set *set, unsigned idx)
3209 {
3210 struct radeon_winsys *ws = cmd_buffer->device->ws;
3211
3212 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3213
3214 assert(set);
3215 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3216
3217 if (!cmd_buffer->device->use_global_bo_list) {
3218 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3219 if (set->descriptors[j])
3220 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3221 }
3222
3223 if(set->bo)
3224 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3225 }
3226
3227 void radv_CmdBindDescriptorSets(
3228 VkCommandBuffer commandBuffer,
3229 VkPipelineBindPoint pipelineBindPoint,
3230 VkPipelineLayout _layout,
3231 uint32_t firstSet,
3232 uint32_t descriptorSetCount,
3233 const VkDescriptorSet* pDescriptorSets,
3234 uint32_t dynamicOffsetCount,
3235 const uint32_t* pDynamicOffsets)
3236 {
3237 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3238 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3239 unsigned dyn_idx = 0;
3240
3241 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3242 struct radv_descriptor_state *descriptors_state =
3243 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3244
3245 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3246 unsigned idx = i + firstSet;
3247 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3248 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3249
3250 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3251 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3252 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3253 assert(dyn_idx < dynamicOffsetCount);
3254
3255 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3256 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3257 dst[0] = va;
3258 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3259 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3260 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3261 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3262 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3263 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3264
3265 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
3266 dst[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3267 S_008F0C_OOB_SELECT(3) |
3268 S_008F0C_RESOURCE_LEVEL(1);
3269 } else {
3270 dst[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3271 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3272 }
3273
3274 cmd_buffer->push_constant_stages |=
3275 set->layout->dynamic_shader_stages;
3276 }
3277 }
3278 }
3279
3280 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3281 struct radv_descriptor_set *set,
3282 struct radv_descriptor_set_layout *layout,
3283 VkPipelineBindPoint bind_point)
3284 {
3285 struct radv_descriptor_state *descriptors_state =
3286 radv_get_descriptors_state(cmd_buffer, bind_point);
3287 set->size = layout->size;
3288 set->layout = layout;
3289
3290 if (descriptors_state->push_set.capacity < set->size) {
3291 size_t new_size = MAX2(set->size, 1024);
3292 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3293 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3294
3295 free(set->mapped_ptr);
3296 set->mapped_ptr = malloc(new_size);
3297
3298 if (!set->mapped_ptr) {
3299 descriptors_state->push_set.capacity = 0;
3300 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3301 return false;
3302 }
3303
3304 descriptors_state->push_set.capacity = new_size;
3305 }
3306
3307 return true;
3308 }
3309
3310 void radv_meta_push_descriptor_set(
3311 struct radv_cmd_buffer* cmd_buffer,
3312 VkPipelineBindPoint pipelineBindPoint,
3313 VkPipelineLayout _layout,
3314 uint32_t set,
3315 uint32_t descriptorWriteCount,
3316 const VkWriteDescriptorSet* pDescriptorWrites)
3317 {
3318 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3319 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3320 unsigned bo_offset;
3321
3322 assert(set == 0);
3323 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3324
3325 push_set->size = layout->set[set].layout->size;
3326 push_set->layout = layout->set[set].layout;
3327
3328 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3329 &bo_offset,
3330 (void**) &push_set->mapped_ptr))
3331 return;
3332
3333 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3334 push_set->va += bo_offset;
3335
3336 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3337 radv_descriptor_set_to_handle(push_set),
3338 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3339
3340 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3341 }
3342
3343 void radv_CmdPushDescriptorSetKHR(
3344 VkCommandBuffer commandBuffer,
3345 VkPipelineBindPoint pipelineBindPoint,
3346 VkPipelineLayout _layout,
3347 uint32_t set,
3348 uint32_t descriptorWriteCount,
3349 const VkWriteDescriptorSet* pDescriptorWrites)
3350 {
3351 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3352 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3353 struct radv_descriptor_state *descriptors_state =
3354 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3355 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3356
3357 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3358
3359 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3360 layout->set[set].layout,
3361 pipelineBindPoint))
3362 return;
3363
3364 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3365 * because it is invalid, according to Vulkan spec.
3366 */
3367 for (int i = 0; i < descriptorWriteCount; i++) {
3368 MAYBE_UNUSED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
3369 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
3370 }
3371
3372 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3373 radv_descriptor_set_to_handle(push_set),
3374 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3375
3376 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3377 descriptors_state->push_dirty = true;
3378 }
3379
3380 void radv_CmdPushDescriptorSetWithTemplateKHR(
3381 VkCommandBuffer commandBuffer,
3382 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
3383 VkPipelineLayout _layout,
3384 uint32_t set,
3385 const void* pData)
3386 {
3387 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3388 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3389 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
3390 struct radv_descriptor_state *descriptors_state =
3391 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
3392 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3393
3394 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3395
3396 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3397 layout->set[set].layout,
3398 templ->bind_point))
3399 return;
3400
3401 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
3402 descriptorUpdateTemplate, pData);
3403
3404 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
3405 descriptors_state->push_dirty = true;
3406 }
3407
3408 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
3409 VkPipelineLayout layout,
3410 VkShaderStageFlags stageFlags,
3411 uint32_t offset,
3412 uint32_t size,
3413 const void* pValues)
3414 {
3415 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3416 memcpy(cmd_buffer->push_constants + offset, pValues, size);
3417 cmd_buffer->push_constant_stages |= stageFlags;
3418 }
3419
3420 VkResult radv_EndCommandBuffer(
3421 VkCommandBuffer commandBuffer)
3422 {
3423 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3424
3425 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
3426 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
3427 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
3428
3429 /* Make sure to sync all pending active queries at the end of
3430 * command buffer.
3431 */
3432 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
3433
3434 si_emit_cache_flush(cmd_buffer);
3435 }
3436
3437 /* Make sure CP DMA is idle at the end of IBs because the kernel
3438 * doesn't wait for it.
3439 */
3440 si_cp_dma_wait_for_idle(cmd_buffer);
3441
3442 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3443 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
3444
3445 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
3446 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3447
3448 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
3449
3450 return cmd_buffer->record_result;
3451 }
3452
3453 static void
3454 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
3455 {
3456 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3457
3458 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
3459 return;
3460
3461 assert(!pipeline->ctx_cs.cdw);
3462
3463 cmd_buffer->state.emitted_compute_pipeline = pipeline;
3464
3465 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
3466 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
3467
3468 cmd_buffer->compute_scratch_size_needed =
3469 MAX2(cmd_buffer->compute_scratch_size_needed,
3470 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
3471
3472 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3473 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
3474
3475 if (unlikely(cmd_buffer->device->trace_bo))
3476 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
3477 }
3478
3479 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
3480 VkPipelineBindPoint bind_point)
3481 {
3482 struct radv_descriptor_state *descriptors_state =
3483 radv_get_descriptors_state(cmd_buffer, bind_point);
3484
3485 descriptors_state->dirty |= descriptors_state->valid;
3486 }
3487
3488 void radv_CmdBindPipeline(
3489 VkCommandBuffer commandBuffer,
3490 VkPipelineBindPoint pipelineBindPoint,
3491 VkPipeline _pipeline)
3492 {
3493 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3494 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3495
3496 switch (pipelineBindPoint) {
3497 case VK_PIPELINE_BIND_POINT_COMPUTE:
3498 if (cmd_buffer->state.compute_pipeline == pipeline)
3499 return;
3500 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3501
3502 cmd_buffer->state.compute_pipeline = pipeline;
3503 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3504 break;
3505 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3506 if (cmd_buffer->state.pipeline == pipeline)
3507 return;
3508 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3509
3510 cmd_buffer->state.pipeline = pipeline;
3511 if (!pipeline)
3512 break;
3513
3514 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3515 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3516
3517 /* the new vertex shader might not have the same user regs */
3518 cmd_buffer->state.last_first_instance = -1;
3519 cmd_buffer->state.last_vertex_offset = -1;
3520
3521 /* Prefetch all pipeline shaders at first draw time. */
3522 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3523
3524 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3525 radv_bind_streamout_state(cmd_buffer, pipeline);
3526
3527 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3528 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3529 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3530 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3531
3532 if (radv_pipeline_has_tess(pipeline))
3533 cmd_buffer->tess_rings_needed = true;
3534 break;
3535 default:
3536 assert(!"invalid bind point");
3537 break;
3538 }
3539 }
3540
3541 void radv_CmdSetViewport(
3542 VkCommandBuffer commandBuffer,
3543 uint32_t firstViewport,
3544 uint32_t viewportCount,
3545 const VkViewport* pViewports)
3546 {
3547 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3548 struct radv_cmd_state *state = &cmd_buffer->state;
3549 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
3550
3551 assert(firstViewport < MAX_VIEWPORTS);
3552 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3553
3554 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3555 pViewports, viewportCount * sizeof(*pViewports))) {
3556 return;
3557 }
3558
3559 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3560 viewportCount * sizeof(*pViewports));
3561
3562 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3563 }
3564
3565 void radv_CmdSetScissor(
3566 VkCommandBuffer commandBuffer,
3567 uint32_t firstScissor,
3568 uint32_t scissorCount,
3569 const VkRect2D* pScissors)
3570 {
3571 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3572 struct radv_cmd_state *state = &cmd_buffer->state;
3573 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
3574
3575 assert(firstScissor < MAX_SCISSORS);
3576 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3577
3578 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3579 scissorCount * sizeof(*pScissors))) {
3580 return;
3581 }
3582
3583 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3584 scissorCount * sizeof(*pScissors));
3585
3586 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3587 }
3588
3589 void radv_CmdSetLineWidth(
3590 VkCommandBuffer commandBuffer,
3591 float lineWidth)
3592 {
3593 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3594
3595 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3596 return;
3597
3598 cmd_buffer->state.dynamic.line_width = lineWidth;
3599 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3600 }
3601
3602 void radv_CmdSetDepthBias(
3603 VkCommandBuffer commandBuffer,
3604 float depthBiasConstantFactor,
3605 float depthBiasClamp,
3606 float depthBiasSlopeFactor)
3607 {
3608 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3609 struct radv_cmd_state *state = &cmd_buffer->state;
3610
3611 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3612 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3613 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3614 return;
3615 }
3616
3617 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3618 state->dynamic.depth_bias.clamp = depthBiasClamp;
3619 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3620
3621 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3622 }
3623
3624 void radv_CmdSetBlendConstants(
3625 VkCommandBuffer commandBuffer,
3626 const float blendConstants[4])
3627 {
3628 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3629 struct radv_cmd_state *state = &cmd_buffer->state;
3630
3631 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3632 return;
3633
3634 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
3635
3636 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3637 }
3638
3639 void radv_CmdSetDepthBounds(
3640 VkCommandBuffer commandBuffer,
3641 float minDepthBounds,
3642 float maxDepthBounds)
3643 {
3644 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3645 struct radv_cmd_state *state = &cmd_buffer->state;
3646
3647 if (state->dynamic.depth_bounds.min == minDepthBounds &&
3648 state->dynamic.depth_bounds.max == maxDepthBounds) {
3649 return;
3650 }
3651
3652 state->dynamic.depth_bounds.min = minDepthBounds;
3653 state->dynamic.depth_bounds.max = maxDepthBounds;
3654
3655 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
3656 }
3657
3658 void radv_CmdSetStencilCompareMask(
3659 VkCommandBuffer commandBuffer,
3660 VkStencilFaceFlags faceMask,
3661 uint32_t compareMask)
3662 {
3663 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3664 struct radv_cmd_state *state = &cmd_buffer->state;
3665 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
3666 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
3667
3668 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3669 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3670 return;
3671 }
3672
3673 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3674 state->dynamic.stencil_compare_mask.front = compareMask;
3675 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3676 state->dynamic.stencil_compare_mask.back = compareMask;
3677
3678 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
3679 }
3680
3681 void radv_CmdSetStencilWriteMask(
3682 VkCommandBuffer commandBuffer,
3683 VkStencilFaceFlags faceMask,
3684 uint32_t writeMask)
3685 {
3686 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3687 struct radv_cmd_state *state = &cmd_buffer->state;
3688 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
3689 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
3690
3691 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3692 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3693 return;
3694 }
3695
3696 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3697 state->dynamic.stencil_write_mask.front = writeMask;
3698 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3699 state->dynamic.stencil_write_mask.back = writeMask;
3700
3701 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
3702 }
3703
3704 void radv_CmdSetStencilReference(
3705 VkCommandBuffer commandBuffer,
3706 VkStencilFaceFlags faceMask,
3707 uint32_t reference)
3708 {
3709 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3710 struct radv_cmd_state *state = &cmd_buffer->state;
3711 bool front_same = state->dynamic.stencil_reference.front == reference;
3712 bool back_same = state->dynamic.stencil_reference.back == reference;
3713
3714 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3715 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3716 return;
3717 }
3718
3719 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3720 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3721 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3722 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3723
3724 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3725 }
3726
3727 void radv_CmdSetDiscardRectangleEXT(
3728 VkCommandBuffer commandBuffer,
3729 uint32_t firstDiscardRectangle,
3730 uint32_t discardRectangleCount,
3731 const VkRect2D* pDiscardRectangles)
3732 {
3733 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3734 struct radv_cmd_state *state = &cmd_buffer->state;
3735 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3736
3737 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3738 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3739
3740 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
3741 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
3742 return;
3743 }
3744
3745 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3746 pDiscardRectangles, discardRectangleCount);
3747
3748 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3749 }
3750
3751 void radv_CmdSetSampleLocationsEXT(
3752 VkCommandBuffer commandBuffer,
3753 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
3754 {
3755 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3756 struct radv_cmd_state *state = &cmd_buffer->state;
3757
3758 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
3759
3760 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
3761 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
3762 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
3763 typed_memcpy(&state->dynamic.sample_location.locations[0],
3764 pSampleLocationsInfo->pSampleLocations,
3765 pSampleLocationsInfo->sampleLocationsCount);
3766
3767 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
3768 }
3769
3770 void radv_CmdExecuteCommands(
3771 VkCommandBuffer commandBuffer,
3772 uint32_t commandBufferCount,
3773 const VkCommandBuffer* pCmdBuffers)
3774 {
3775 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3776
3777 assert(commandBufferCount > 0);
3778
3779 /* Emit pending flushes on primary prior to executing secondary */
3780 si_emit_cache_flush(primary);
3781
3782 for (uint32_t i = 0; i < commandBufferCount; i++) {
3783 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3784
3785 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3786 secondary->scratch_size_needed);
3787 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3788 secondary->compute_scratch_size_needed);
3789
3790 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
3791 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
3792 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
3793 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
3794 if (secondary->tess_rings_needed)
3795 primary->tess_rings_needed = true;
3796 if (secondary->sample_positions_needed)
3797 primary->sample_positions_needed = true;
3798
3799 if (!secondary->state.framebuffer &&
3800 (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
3801 /* Emit the framebuffer state from primary if secondary
3802 * has been recorded without a framebuffer, otherwise
3803 * fast color/depth clears can't work.
3804 */
3805 radv_emit_framebuffer_state(primary);
3806 }
3807
3808 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
3809
3810
3811 /* When the secondary command buffer is compute only we don't
3812 * need to re-emit the current graphics pipeline.
3813 */
3814 if (secondary->state.emitted_pipeline) {
3815 primary->state.emitted_pipeline =
3816 secondary->state.emitted_pipeline;
3817 }
3818
3819 /* When the secondary command buffer is graphics only we don't
3820 * need to re-emit the current compute pipeline.
3821 */
3822 if (secondary->state.emitted_compute_pipeline) {
3823 primary->state.emitted_compute_pipeline =
3824 secondary->state.emitted_compute_pipeline;
3825 }
3826
3827 /* Only re-emit the draw packets when needed. */
3828 if (secondary->state.last_primitive_reset_en != -1) {
3829 primary->state.last_primitive_reset_en =
3830 secondary->state.last_primitive_reset_en;
3831 }
3832
3833 if (secondary->state.last_primitive_reset_index) {
3834 primary->state.last_primitive_reset_index =
3835 secondary->state.last_primitive_reset_index;
3836 }
3837
3838 if (secondary->state.last_ia_multi_vgt_param) {
3839 primary->state.last_ia_multi_vgt_param =
3840 secondary->state.last_ia_multi_vgt_param;
3841 }
3842
3843 primary->state.last_first_instance = secondary->state.last_first_instance;
3844 primary->state.last_num_instances = secondary->state.last_num_instances;
3845 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
3846
3847 if (secondary->state.last_index_type != -1) {
3848 primary->state.last_index_type =
3849 secondary->state.last_index_type;
3850 }
3851 }
3852
3853 /* After executing commands from secondary buffers we have to dirty
3854 * some states.
3855 */
3856 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
3857 RADV_CMD_DIRTY_INDEX_BUFFER |
3858 RADV_CMD_DIRTY_DYNAMIC_ALL;
3859 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
3860 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
3861 }
3862
3863 VkResult radv_CreateCommandPool(
3864 VkDevice _device,
3865 const VkCommandPoolCreateInfo* pCreateInfo,
3866 const VkAllocationCallbacks* pAllocator,
3867 VkCommandPool* pCmdPool)
3868 {
3869 RADV_FROM_HANDLE(radv_device, device, _device);
3870 struct radv_cmd_pool *pool;
3871
3872 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3873 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3874 if (pool == NULL)
3875 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3876
3877 if (pAllocator)
3878 pool->alloc = *pAllocator;
3879 else
3880 pool->alloc = device->alloc;
3881
3882 list_inithead(&pool->cmd_buffers);
3883 list_inithead(&pool->free_cmd_buffers);
3884
3885 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3886
3887 *pCmdPool = radv_cmd_pool_to_handle(pool);
3888
3889 return VK_SUCCESS;
3890
3891 }
3892
3893 void radv_DestroyCommandPool(
3894 VkDevice _device,
3895 VkCommandPool commandPool,
3896 const VkAllocationCallbacks* pAllocator)
3897 {
3898 RADV_FROM_HANDLE(radv_device, device, _device);
3899 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3900
3901 if (!pool)
3902 return;
3903
3904 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3905 &pool->cmd_buffers, pool_link) {
3906 radv_cmd_buffer_destroy(cmd_buffer);
3907 }
3908
3909 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3910 &pool->free_cmd_buffers, pool_link) {
3911 radv_cmd_buffer_destroy(cmd_buffer);
3912 }
3913
3914 vk_free2(&device->alloc, pAllocator, pool);
3915 }
3916
3917 VkResult radv_ResetCommandPool(
3918 VkDevice device,
3919 VkCommandPool commandPool,
3920 VkCommandPoolResetFlags flags)
3921 {
3922 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3923 VkResult result;
3924
3925 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3926 &pool->cmd_buffers, pool_link) {
3927 result = radv_reset_cmd_buffer(cmd_buffer);
3928 if (result != VK_SUCCESS)
3929 return result;
3930 }
3931
3932 return VK_SUCCESS;
3933 }
3934
3935 void radv_TrimCommandPool(
3936 VkDevice device,
3937 VkCommandPool commandPool,
3938 VkCommandPoolTrimFlags flags)
3939 {
3940 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3941
3942 if (!pool)
3943 return;
3944
3945 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3946 &pool->free_cmd_buffers, pool_link) {
3947 radv_cmd_buffer_destroy(cmd_buffer);
3948 }
3949 }
3950
3951 static void
3952 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
3953 uint32_t subpass_id)
3954 {
3955 struct radv_cmd_state *state = &cmd_buffer->state;
3956 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
3957
3958 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3959 cmd_buffer->cs, 4096);
3960
3961 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
3962
3963 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3964
3965 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
3966 const uint32_t a = subpass->attachments[i].attachment;
3967 if (a == VK_ATTACHMENT_UNUSED)
3968 continue;
3969
3970 radv_handle_subpass_image_transition(cmd_buffer,
3971 subpass->attachments[i],
3972 true);
3973 }
3974
3975 radv_cmd_buffer_clear_subpass(cmd_buffer);
3976
3977 assert(cmd_buffer->cs->cdw <= cdw_max);
3978 }
3979
3980 static void
3981 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
3982 {
3983 struct radv_cmd_state *state = &cmd_buffer->state;
3984 const struct radv_subpass *subpass = state->subpass;
3985 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
3986
3987 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3988
3989 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
3990 const uint32_t a = subpass->attachments[i].attachment;
3991 if (a == VK_ATTACHMENT_UNUSED)
3992 continue;
3993
3994 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
3995 continue;
3996
3997 VkImageLayout layout = state->pass->attachments[a].final_layout;
3998 struct radv_subpass_attachment att = { a, layout };
3999 radv_handle_subpass_image_transition(cmd_buffer, att, false);
4000 }
4001 }
4002
4003 void radv_CmdBeginRenderPass(
4004 VkCommandBuffer commandBuffer,
4005 const VkRenderPassBeginInfo* pRenderPassBegin,
4006 VkSubpassContents contents)
4007 {
4008 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4009 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
4010 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
4011 VkResult result;
4012
4013 cmd_buffer->state.framebuffer = framebuffer;
4014 cmd_buffer->state.pass = pass;
4015 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
4016
4017 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
4018 if (result != VK_SUCCESS)
4019 return;
4020
4021 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
4022 if (result != VK_SUCCESS)
4023 return;
4024
4025 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
4026 }
4027
4028 void radv_CmdBeginRenderPass2KHR(
4029 VkCommandBuffer commandBuffer,
4030 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
4031 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
4032 {
4033 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
4034 pSubpassBeginInfo->contents);
4035 }
4036
4037 void radv_CmdNextSubpass(
4038 VkCommandBuffer commandBuffer,
4039 VkSubpassContents contents)
4040 {
4041 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4042
4043 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
4044 radv_cmd_buffer_end_subpass(cmd_buffer);
4045 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
4046 }
4047
4048 void radv_CmdNextSubpass2KHR(
4049 VkCommandBuffer commandBuffer,
4050 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
4051 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4052 {
4053 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
4054 }
4055
4056 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
4057 {
4058 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
4059 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
4060 if (!radv_get_shader(pipeline, stage))
4061 continue;
4062
4063 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
4064 if (loc->sgpr_idx == -1)
4065 continue;
4066 uint32_t base_reg = pipeline->user_data_0[stage];
4067 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4068
4069 }
4070 if (pipeline->gs_copy_shader) {
4071 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
4072 if (loc->sgpr_idx != -1) {
4073 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
4074 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4075 }
4076 }
4077 }
4078
4079 static void
4080 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4081 uint32_t vertex_count,
4082 bool use_opaque)
4083 {
4084 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
4085 radeon_emit(cmd_buffer->cs, vertex_count);
4086 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
4087 S_0287F0_USE_OPAQUE(use_opaque));
4088 }
4089
4090 static void
4091 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
4092 uint64_t index_va,
4093 uint32_t index_count)
4094 {
4095 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
4096 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
4097 radeon_emit(cmd_buffer->cs, index_va);
4098 radeon_emit(cmd_buffer->cs, index_va >> 32);
4099 radeon_emit(cmd_buffer->cs, index_count);
4100 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
4101 }
4102
4103 static void
4104 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4105 bool indexed,
4106 uint32_t draw_count,
4107 uint64_t count_va,
4108 uint32_t stride)
4109 {
4110 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4111 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
4112 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
4113 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
4114 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
4115 bool predicating = cmd_buffer->state.predicating;
4116 assert(base_reg);
4117
4118 /* just reset draw state for vertex data */
4119 cmd_buffer->state.last_first_instance = -1;
4120 cmd_buffer->state.last_num_instances = -1;
4121 cmd_buffer->state.last_vertex_offset = -1;
4122
4123 if (draw_count == 1 && !count_va && !draw_id_enable) {
4124 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
4125 PKT3_DRAW_INDIRECT, 3, predicating));
4126 radeon_emit(cs, 0);
4127 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4128 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4129 radeon_emit(cs, di_src_sel);
4130 } else {
4131 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
4132 PKT3_DRAW_INDIRECT_MULTI,
4133 8, predicating));
4134 radeon_emit(cs, 0);
4135 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4136 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4137 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
4138 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
4139 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
4140 radeon_emit(cs, draw_count); /* count */
4141 radeon_emit(cs, count_va); /* count_addr */
4142 radeon_emit(cs, count_va >> 32);
4143 radeon_emit(cs, stride); /* stride */
4144 radeon_emit(cs, di_src_sel);
4145 }
4146 }
4147
4148 static void
4149 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
4150 const struct radv_draw_info *info)
4151 {
4152 struct radv_cmd_state *state = &cmd_buffer->state;
4153 struct radeon_winsys *ws = cmd_buffer->device->ws;
4154 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4155
4156 if (info->indirect) {
4157 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4158 uint64_t count_va = 0;
4159
4160 va += info->indirect->offset + info->indirect_offset;
4161
4162 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4163
4164 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
4165 radeon_emit(cs, 1);
4166 radeon_emit(cs, va);
4167 radeon_emit(cs, va >> 32);
4168
4169 if (info->count_buffer) {
4170 count_va = radv_buffer_get_va(info->count_buffer->bo);
4171 count_va += info->count_buffer->offset +
4172 info->count_buffer_offset;
4173
4174 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
4175 }
4176
4177 if (!state->subpass->view_mask) {
4178 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4179 info->indexed,
4180 info->count,
4181 count_va,
4182 info->stride);
4183 } else {
4184 unsigned i;
4185 for_each_bit(i, state->subpass->view_mask) {
4186 radv_emit_view_index(cmd_buffer, i);
4187
4188 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4189 info->indexed,
4190 info->count,
4191 count_va,
4192 info->stride);
4193 }
4194 }
4195 } else {
4196 assert(state->pipeline->graphics.vtx_base_sgpr);
4197
4198 if (info->vertex_offset != state->last_vertex_offset ||
4199 info->first_instance != state->last_first_instance) {
4200 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
4201 state->pipeline->graphics.vtx_emit_num);
4202
4203 radeon_emit(cs, info->vertex_offset);
4204 radeon_emit(cs, info->first_instance);
4205 if (state->pipeline->graphics.vtx_emit_num == 3)
4206 radeon_emit(cs, 0);
4207 state->last_first_instance = info->first_instance;
4208 state->last_vertex_offset = info->vertex_offset;
4209 }
4210
4211 if (state->last_num_instances != info->instance_count) {
4212 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
4213 radeon_emit(cs, info->instance_count);
4214 state->last_num_instances = info->instance_count;
4215 }
4216
4217 if (info->indexed) {
4218 int index_size = state->index_type ? 4 : 2;
4219 uint64_t index_va;
4220
4221 index_va = state->index_va;
4222 index_va += info->first_index * index_size;
4223
4224 if (!state->subpass->view_mask) {
4225 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4226 index_va,
4227 info->count);
4228 } else {
4229 unsigned i;
4230 for_each_bit(i, state->subpass->view_mask) {
4231 radv_emit_view_index(cmd_buffer, i);
4232
4233 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4234 index_va,
4235 info->count);
4236 }
4237 }
4238 } else {
4239 if (!state->subpass->view_mask) {
4240 radv_cs_emit_draw_packet(cmd_buffer,
4241 info->count,
4242 !!info->strmout_buffer);
4243 } else {
4244 unsigned i;
4245 for_each_bit(i, state->subpass->view_mask) {
4246 radv_emit_view_index(cmd_buffer, i);
4247
4248 radv_cs_emit_draw_packet(cmd_buffer,
4249 info->count,
4250 !!info->strmout_buffer);
4251 }
4252 }
4253 }
4254 }
4255 }
4256
4257 /*
4258 * Vega and raven have a bug which triggers if there are multiple context
4259 * register contexts active at the same time with different scissor values.
4260 *
4261 * There are two possible workarounds:
4262 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4263 * there is only ever 1 active set of scissor values at the same time.
4264 *
4265 * 2) Whenever the hardware switches contexts we have to set the scissor
4266 * registers again even if it is a noop. That way the new context gets
4267 * the correct scissor values.
4268 *
4269 * This implements option 2. radv_need_late_scissor_emission needs to
4270 * return true on affected HW if radv_emit_all_graphics_states sets
4271 * any context registers.
4272 */
4273 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
4274 const struct radv_draw_info *info)
4275 {
4276 struct radv_cmd_state *state = &cmd_buffer->state;
4277
4278 if (!cmd_buffer->device->physical_device->has_scissor_bug)
4279 return false;
4280
4281 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
4282 return true;
4283
4284 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
4285
4286 /* Index, vertex and streamout buffers don't change context regs, and
4287 * pipeline is already handled.
4288 */
4289 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
4290 RADV_CMD_DIRTY_VERTEX_BUFFER |
4291 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
4292 RADV_CMD_DIRTY_PIPELINE);
4293
4294 if (cmd_buffer->state.dirty & used_states)
4295 return true;
4296
4297 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
4298 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
4299 return true;
4300
4301 return false;
4302 }
4303
4304 static void
4305 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
4306 const struct radv_draw_info *info)
4307 {
4308 bool late_scissor_emission;
4309
4310 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
4311 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
4312 radv_emit_rbplus_state(cmd_buffer);
4313
4314 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
4315 radv_emit_graphics_pipeline(cmd_buffer);
4316
4317 /* This should be before the cmd_buffer->state.dirty is cleared
4318 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4319 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4320 late_scissor_emission =
4321 radv_need_late_scissor_emission(cmd_buffer, info);
4322
4323 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
4324 radv_emit_framebuffer_state(cmd_buffer);
4325
4326 if (info->indexed) {
4327 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
4328 radv_emit_index_buffer(cmd_buffer);
4329 } else {
4330 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4331 * so the state must be re-emitted before the next indexed
4332 * draw.
4333 */
4334 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
4335 cmd_buffer->state.last_index_type = -1;
4336 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
4337 }
4338 }
4339
4340 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
4341
4342 radv_emit_draw_registers(cmd_buffer, info);
4343
4344 if (late_scissor_emission)
4345 radv_emit_scissor(cmd_buffer);
4346 }
4347
4348 static void
4349 radv_draw(struct radv_cmd_buffer *cmd_buffer,
4350 const struct radv_draw_info *info)
4351 {
4352 struct radeon_info *rad_info =
4353 &cmd_buffer->device->physical_device->rad_info;
4354 bool has_prefetch =
4355 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4356 bool pipeline_is_dirty =
4357 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
4358 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
4359
4360 MAYBE_UNUSED unsigned cdw_max =
4361 radeon_check_space(cmd_buffer->device->ws,
4362 cmd_buffer->cs, 4096);
4363
4364 if (likely(!info->indirect)) {
4365 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4366 * no workaround for indirect draws, but we can at least skip
4367 * direct draws.
4368 */
4369 if (unlikely(!info->instance_count))
4370 return;
4371
4372 /* Handle count == 0. */
4373 if (unlikely(!info->count && !info->strmout_buffer))
4374 return;
4375 }
4376
4377 /* Use optimal packet order based on whether we need to sync the
4378 * pipeline.
4379 */
4380 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4381 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4382 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4383 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4384 /* If we have to wait for idle, set all states first, so that
4385 * all SET packets are processed in parallel with previous draw
4386 * calls. Then upload descriptors, set shader pointers, and
4387 * draw, and prefetch at the end. This ensures that the time
4388 * the CUs are idle is very short. (there are only SET_SH
4389 * packets between the wait and the draw)
4390 */
4391 radv_emit_all_graphics_states(cmd_buffer, info);
4392 si_emit_cache_flush(cmd_buffer);
4393 /* <-- CUs are idle here --> */
4394
4395 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4396
4397 radv_emit_draw_packets(cmd_buffer, info);
4398 /* <-- CUs are busy here --> */
4399
4400 /* Start prefetches after the draw has been started. Both will
4401 * run in parallel, but starting the draw first is more
4402 * important.
4403 */
4404 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4405 radv_emit_prefetch_L2(cmd_buffer,
4406 cmd_buffer->state.pipeline, false);
4407 }
4408 } else {
4409 /* If we don't wait for idle, start prefetches first, then set
4410 * states, and draw at the end.
4411 */
4412 si_emit_cache_flush(cmd_buffer);
4413
4414 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4415 /* Only prefetch the vertex shader and VBO descriptors
4416 * in order to start the draw as soon as possible.
4417 */
4418 radv_emit_prefetch_L2(cmd_buffer,
4419 cmd_buffer->state.pipeline, true);
4420 }
4421
4422 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4423
4424 radv_emit_all_graphics_states(cmd_buffer, info);
4425 radv_emit_draw_packets(cmd_buffer, info);
4426
4427 /* Prefetch the remaining shaders after the draw has been
4428 * started.
4429 */
4430 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4431 radv_emit_prefetch_L2(cmd_buffer,
4432 cmd_buffer->state.pipeline, false);
4433 }
4434 }
4435
4436 /* Workaround for a VGT hang when streamout is enabled.
4437 * It must be done after drawing.
4438 */
4439 if (cmd_buffer->state.streamout.streamout_enabled &&
4440 (rad_info->family == CHIP_HAWAII ||
4441 rad_info->family == CHIP_TONGA ||
4442 rad_info->family == CHIP_FIJI)) {
4443 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
4444 }
4445
4446 assert(cmd_buffer->cs->cdw <= cdw_max);
4447 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
4448 }
4449
4450 void radv_CmdDraw(
4451 VkCommandBuffer commandBuffer,
4452 uint32_t vertexCount,
4453 uint32_t instanceCount,
4454 uint32_t firstVertex,
4455 uint32_t firstInstance)
4456 {
4457 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4458 struct radv_draw_info info = {};
4459
4460 info.count = vertexCount;
4461 info.instance_count = instanceCount;
4462 info.first_instance = firstInstance;
4463 info.vertex_offset = firstVertex;
4464
4465 radv_draw(cmd_buffer, &info);
4466 }
4467
4468 void radv_CmdDrawIndexed(
4469 VkCommandBuffer commandBuffer,
4470 uint32_t indexCount,
4471 uint32_t instanceCount,
4472 uint32_t firstIndex,
4473 int32_t vertexOffset,
4474 uint32_t firstInstance)
4475 {
4476 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4477 struct radv_draw_info info = {};
4478
4479 info.indexed = true;
4480 info.count = indexCount;
4481 info.instance_count = instanceCount;
4482 info.first_index = firstIndex;
4483 info.vertex_offset = vertexOffset;
4484 info.first_instance = firstInstance;
4485
4486 radv_draw(cmd_buffer, &info);
4487 }
4488
4489 void radv_CmdDrawIndirect(
4490 VkCommandBuffer commandBuffer,
4491 VkBuffer _buffer,
4492 VkDeviceSize offset,
4493 uint32_t drawCount,
4494 uint32_t stride)
4495 {
4496 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4497 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4498 struct radv_draw_info info = {};
4499
4500 info.count = drawCount;
4501 info.indirect = buffer;
4502 info.indirect_offset = offset;
4503 info.stride = stride;
4504
4505 radv_draw(cmd_buffer, &info);
4506 }
4507
4508 void radv_CmdDrawIndexedIndirect(
4509 VkCommandBuffer commandBuffer,
4510 VkBuffer _buffer,
4511 VkDeviceSize offset,
4512 uint32_t drawCount,
4513 uint32_t stride)
4514 {
4515 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4516 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4517 struct radv_draw_info info = {};
4518
4519 info.indexed = true;
4520 info.count = drawCount;
4521 info.indirect = buffer;
4522 info.indirect_offset = offset;
4523 info.stride = stride;
4524
4525 radv_draw(cmd_buffer, &info);
4526 }
4527
4528 void radv_CmdDrawIndirectCountKHR(
4529 VkCommandBuffer commandBuffer,
4530 VkBuffer _buffer,
4531 VkDeviceSize offset,
4532 VkBuffer _countBuffer,
4533 VkDeviceSize countBufferOffset,
4534 uint32_t maxDrawCount,
4535 uint32_t stride)
4536 {
4537 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4538 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4539 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4540 struct radv_draw_info info = {};
4541
4542 info.count = maxDrawCount;
4543 info.indirect = buffer;
4544 info.indirect_offset = offset;
4545 info.count_buffer = count_buffer;
4546 info.count_buffer_offset = countBufferOffset;
4547 info.stride = stride;
4548
4549 radv_draw(cmd_buffer, &info);
4550 }
4551
4552 void radv_CmdDrawIndexedIndirectCountKHR(
4553 VkCommandBuffer commandBuffer,
4554 VkBuffer _buffer,
4555 VkDeviceSize offset,
4556 VkBuffer _countBuffer,
4557 VkDeviceSize countBufferOffset,
4558 uint32_t maxDrawCount,
4559 uint32_t stride)
4560 {
4561 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4562 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4563 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4564 struct radv_draw_info info = {};
4565
4566 info.indexed = true;
4567 info.count = maxDrawCount;
4568 info.indirect = buffer;
4569 info.indirect_offset = offset;
4570 info.count_buffer = count_buffer;
4571 info.count_buffer_offset = countBufferOffset;
4572 info.stride = stride;
4573
4574 radv_draw(cmd_buffer, &info);
4575 }
4576
4577 struct radv_dispatch_info {
4578 /**
4579 * Determine the layout of the grid (in block units) to be used.
4580 */
4581 uint32_t blocks[3];
4582
4583 /**
4584 * A starting offset for the grid. If unaligned is set, the offset
4585 * must still be aligned.
4586 */
4587 uint32_t offsets[3];
4588 /**
4589 * Whether it's an unaligned compute dispatch.
4590 */
4591 bool unaligned;
4592
4593 /**
4594 * Indirect compute parameters resource.
4595 */
4596 struct radv_buffer *indirect;
4597 uint64_t indirect_offset;
4598 };
4599
4600 static void
4601 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
4602 const struct radv_dispatch_info *info)
4603 {
4604 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4605 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4606 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
4607 struct radeon_winsys *ws = cmd_buffer->device->ws;
4608 bool predicating = cmd_buffer->state.predicating;
4609 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4610 struct radv_userdata_info *loc;
4611
4612 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
4613 AC_UD_CS_GRID_SIZE);
4614
4615 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
4616
4617 if (info->indirect) {
4618 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4619
4620 va += info->indirect->offset + info->indirect_offset;
4621
4622 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4623
4624 if (loc->sgpr_idx != -1) {
4625 for (unsigned i = 0; i < 3; ++i) {
4626 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4627 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4628 COPY_DATA_DST_SEL(COPY_DATA_REG));
4629 radeon_emit(cs, (va + 4 * i));
4630 radeon_emit(cs, (va + 4 * i) >> 32);
4631 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
4632 + loc->sgpr_idx * 4) >> 2) + i);
4633 radeon_emit(cs, 0);
4634 }
4635 }
4636
4637 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
4638 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
4639 PKT3_SHADER_TYPE_S(1));
4640 radeon_emit(cs, va);
4641 radeon_emit(cs, va >> 32);
4642 radeon_emit(cs, dispatch_initiator);
4643 } else {
4644 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
4645 PKT3_SHADER_TYPE_S(1));
4646 radeon_emit(cs, 1);
4647 radeon_emit(cs, va);
4648 radeon_emit(cs, va >> 32);
4649
4650 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
4651 PKT3_SHADER_TYPE_S(1));
4652 radeon_emit(cs, 0);
4653 radeon_emit(cs, dispatch_initiator);
4654 }
4655 } else {
4656 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
4657 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
4658
4659 if (info->unaligned) {
4660 unsigned *cs_block_size = compute_shader->info.cs.block_size;
4661 unsigned remainder[3];
4662
4663 /* If aligned, these should be an entire block size,
4664 * not 0.
4665 */
4666 remainder[0] = blocks[0] + cs_block_size[0] -
4667 align_u32_npot(blocks[0], cs_block_size[0]);
4668 remainder[1] = blocks[1] + cs_block_size[1] -
4669 align_u32_npot(blocks[1], cs_block_size[1]);
4670 remainder[2] = blocks[2] + cs_block_size[2] -
4671 align_u32_npot(blocks[2], cs_block_size[2]);
4672
4673 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
4674 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
4675 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
4676
4677 for(unsigned i = 0; i < 3; ++i) {
4678 assert(offsets[i] % cs_block_size[i] == 0);
4679 offsets[i] /= cs_block_size[i];
4680 }
4681
4682 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4683 radeon_emit(cs,
4684 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
4685 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4686 radeon_emit(cs,
4687 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4688 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4689 radeon_emit(cs,
4690 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4691 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4692
4693 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4694 }
4695
4696 if (loc->sgpr_idx != -1) {
4697 assert(loc->num_sgprs == 3);
4698
4699 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4700 loc->sgpr_idx * 4, 3);
4701 radeon_emit(cs, blocks[0]);
4702 radeon_emit(cs, blocks[1]);
4703 radeon_emit(cs, blocks[2]);
4704 }
4705
4706 if (offsets[0] || offsets[1] || offsets[2]) {
4707 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4708 radeon_emit(cs, offsets[0]);
4709 radeon_emit(cs, offsets[1]);
4710 radeon_emit(cs, offsets[2]);
4711
4712 /* The blocks in the packet are not counts but end values. */
4713 for (unsigned i = 0; i < 3; ++i)
4714 blocks[i] += offsets[i];
4715 } else {
4716 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4717 }
4718
4719 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4720 PKT3_SHADER_TYPE_S(1));
4721 radeon_emit(cs, blocks[0]);
4722 radeon_emit(cs, blocks[1]);
4723 radeon_emit(cs, blocks[2]);
4724 radeon_emit(cs, dispatch_initiator);
4725 }
4726
4727 assert(cmd_buffer->cs->cdw <= cdw_max);
4728 }
4729
4730 static void
4731 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4732 {
4733 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4734 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4735 }
4736
4737 static void
4738 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4739 const struct radv_dispatch_info *info)
4740 {
4741 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4742 bool has_prefetch =
4743 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4744 bool pipeline_is_dirty = pipeline &&
4745 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4746
4747 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4748 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4749 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4750 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4751 /* If we have to wait for idle, set all states first, so that
4752 * all SET packets are processed in parallel with previous draw
4753 * calls. Then upload descriptors, set shader pointers, and
4754 * dispatch, and prefetch at the end. This ensures that the
4755 * time the CUs are idle is very short. (there are only SET_SH
4756 * packets between the wait and the draw)
4757 */
4758 radv_emit_compute_pipeline(cmd_buffer);
4759 si_emit_cache_flush(cmd_buffer);
4760 /* <-- CUs are idle here --> */
4761
4762 radv_upload_compute_shader_descriptors(cmd_buffer);
4763
4764 radv_emit_dispatch_packets(cmd_buffer, info);
4765 /* <-- CUs are busy here --> */
4766
4767 /* Start prefetches after the dispatch has been started. Both
4768 * will run in parallel, but starting the dispatch first is
4769 * more important.
4770 */
4771 if (has_prefetch && pipeline_is_dirty) {
4772 radv_emit_shader_prefetch(cmd_buffer,
4773 pipeline->shaders[MESA_SHADER_COMPUTE]);
4774 }
4775 } else {
4776 /* If we don't wait for idle, start prefetches first, then set
4777 * states, and dispatch at the end.
4778 */
4779 si_emit_cache_flush(cmd_buffer);
4780
4781 if (has_prefetch && pipeline_is_dirty) {
4782 radv_emit_shader_prefetch(cmd_buffer,
4783 pipeline->shaders[MESA_SHADER_COMPUTE]);
4784 }
4785
4786 radv_upload_compute_shader_descriptors(cmd_buffer);
4787
4788 radv_emit_compute_pipeline(cmd_buffer);
4789 radv_emit_dispatch_packets(cmd_buffer, info);
4790 }
4791
4792 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
4793 }
4794
4795 void radv_CmdDispatchBase(
4796 VkCommandBuffer commandBuffer,
4797 uint32_t base_x,
4798 uint32_t base_y,
4799 uint32_t base_z,
4800 uint32_t x,
4801 uint32_t y,
4802 uint32_t z)
4803 {
4804 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4805 struct radv_dispatch_info info = {};
4806
4807 info.blocks[0] = x;
4808 info.blocks[1] = y;
4809 info.blocks[2] = z;
4810
4811 info.offsets[0] = base_x;
4812 info.offsets[1] = base_y;
4813 info.offsets[2] = base_z;
4814 radv_dispatch(cmd_buffer, &info);
4815 }
4816
4817 void radv_CmdDispatch(
4818 VkCommandBuffer commandBuffer,
4819 uint32_t x,
4820 uint32_t y,
4821 uint32_t z)
4822 {
4823 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4824 }
4825
4826 void radv_CmdDispatchIndirect(
4827 VkCommandBuffer commandBuffer,
4828 VkBuffer _buffer,
4829 VkDeviceSize offset)
4830 {
4831 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4832 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4833 struct radv_dispatch_info info = {};
4834
4835 info.indirect = buffer;
4836 info.indirect_offset = offset;
4837
4838 radv_dispatch(cmd_buffer, &info);
4839 }
4840
4841 void radv_unaligned_dispatch(
4842 struct radv_cmd_buffer *cmd_buffer,
4843 uint32_t x,
4844 uint32_t y,
4845 uint32_t z)
4846 {
4847 struct radv_dispatch_info info = {};
4848
4849 info.blocks[0] = x;
4850 info.blocks[1] = y;
4851 info.blocks[2] = z;
4852 info.unaligned = 1;
4853
4854 radv_dispatch(cmd_buffer, &info);
4855 }
4856
4857 void radv_CmdEndRenderPass(
4858 VkCommandBuffer commandBuffer)
4859 {
4860 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4861
4862 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
4863
4864 radv_cmd_buffer_end_subpass(cmd_buffer);
4865
4866 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4867 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
4868
4869 cmd_buffer->state.pass = NULL;
4870 cmd_buffer->state.subpass = NULL;
4871 cmd_buffer->state.attachments = NULL;
4872 cmd_buffer->state.framebuffer = NULL;
4873 cmd_buffer->state.subpass_sample_locs = NULL;
4874 }
4875
4876 void radv_CmdEndRenderPass2KHR(
4877 VkCommandBuffer commandBuffer,
4878 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4879 {
4880 radv_CmdEndRenderPass(commandBuffer);
4881 }
4882
4883 /*
4884 * For HTILE we have the following interesting clear words:
4885 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4886 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4887 * 0xfffffff0: Clear depth to 1.0
4888 * 0x00000000: Clear depth to 0.0
4889 */
4890 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
4891 struct radv_image *image,
4892 const VkImageSubresourceRange *range,
4893 uint32_t clear_word)
4894 {
4895 assert(range->baseMipLevel == 0);
4896 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
4897 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
4898 struct radv_cmd_state *state = &cmd_buffer->state;
4899 VkClearDepthStencilValue value = {};
4900
4901 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4902 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4903
4904 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, clear_word);
4905
4906 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4907
4908 if (vk_format_is_stencil(image->vk_format))
4909 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4910
4911 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4912
4913 if (radv_image_is_tc_compat_htile(image)) {
4914 /* Initialize the TC-compat metada value to 0 because by
4915 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
4916 * need have to conditionally update its value when performing
4917 * a fast depth clear.
4918 */
4919 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, 0);
4920 }
4921 }
4922
4923 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4924 struct radv_image *image,
4925 VkImageLayout src_layout,
4926 VkImageLayout dst_layout,
4927 unsigned src_queue_mask,
4928 unsigned dst_queue_mask,
4929 const VkImageSubresourceRange *range,
4930 struct radv_sample_locations_state *sample_locs)
4931 {
4932 if (!radv_image_has_htile(image))
4933 return;
4934
4935 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4936 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4937
4938 if (radv_layout_is_htile_compressed(image, dst_layout,
4939 dst_queue_mask)) {
4940 clear_value = 0;
4941 }
4942
4943 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4944 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4945 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4946 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4947 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4948 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4949 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4950 VkImageSubresourceRange local_range = *range;
4951 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4952 local_range.baseMipLevel = 0;
4953 local_range.levelCount = 1;
4954
4955 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4956 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4957
4958 radv_decompress_depth_image_inplace(cmd_buffer, image,
4959 &local_range, sample_locs);
4960
4961 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4962 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4963 }
4964 }
4965
4966 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4967 struct radv_image *image,
4968 const VkImageSubresourceRange *range,
4969 uint32_t value)
4970 {
4971 struct radv_cmd_state *state = &cmd_buffer->state;
4972
4973 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4974 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4975
4976 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
4977
4978 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4979 }
4980
4981 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
4982 struct radv_image *image,
4983 const VkImageSubresourceRange *range)
4984 {
4985 struct radv_cmd_state *state = &cmd_buffer->state;
4986 static const uint32_t fmask_clear_values[4] = {
4987 0x00000000,
4988 0x02020202,
4989 0xE4E4E4E4,
4990 0x76543210
4991 };
4992 uint32_t log2_samples = util_logbase2(image->info.samples);
4993 uint32_t value = fmask_clear_values[log2_samples];
4994
4995 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4996 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4997
4998 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
4999
5000 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5001 }
5002
5003 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
5004 struct radv_image *image,
5005 const VkImageSubresourceRange *range, uint32_t value)
5006 {
5007 struct radv_cmd_state *state = &cmd_buffer->state;
5008 unsigned size = 0;
5009
5010 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5011 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5012
5013 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
5014
5015 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
5016 /* When DCC is enabled with mipmaps, some levels might not
5017 * support fast clears and we have to initialize them as "fully
5018 * expanded".
5019 */
5020 /* Compute the size of all fast clearable DCC levels. */
5021 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
5022 struct legacy_surf_level *surf_level =
5023 &image->planes[0].surface.u.legacy.level[i];
5024 unsigned dcc_fast_clear_size =
5025 surf_level->dcc_slice_fast_clear_size * image->info.array_size;
5026
5027 if (!dcc_fast_clear_size)
5028 break;
5029
5030 size = surf_level->dcc_offset + dcc_fast_clear_size;
5031 }
5032
5033 /* Initialize the mipmap levels without DCC. */
5034 if (size != image->planes[0].surface.dcc_size) {
5035 state->flush_bits |=
5036 radv_fill_buffer(cmd_buffer, image->bo,
5037 image->offset + image->dcc_offset + size,
5038 image->planes[0].surface.dcc_size - size,
5039 0xffffffff);
5040 }
5041 }
5042
5043 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5044 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5045 }
5046
5047 /**
5048 * Initialize DCC/FMASK/CMASK metadata for a color image.
5049 */
5050 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
5051 struct radv_image *image,
5052 VkImageLayout src_layout,
5053 VkImageLayout dst_layout,
5054 unsigned src_queue_mask,
5055 unsigned dst_queue_mask,
5056 const VkImageSubresourceRange *range)
5057 {
5058 if (radv_image_has_cmask(image)) {
5059 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5060
5061 /* TODO: clarify this. */
5062 if (radv_image_has_fmask(image)) {
5063 value = 0xccccccccu;
5064 }
5065
5066 radv_initialise_cmask(cmd_buffer, image, range, value);
5067 }
5068
5069 if (radv_image_has_fmask(image)) {
5070 radv_initialize_fmask(cmd_buffer, image, range);
5071 }
5072
5073 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5074 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5075 bool need_decompress_pass = false;
5076
5077 if (radv_layout_dcc_compressed(image, dst_layout,
5078 dst_queue_mask)) {
5079 value = 0x20202020u;
5080 need_decompress_pass = true;
5081 }
5082
5083 radv_initialize_dcc(cmd_buffer, image, range, value);
5084
5085 radv_update_fce_metadata(cmd_buffer, image, range,
5086 need_decompress_pass);
5087 }
5088
5089 if (radv_image_has_cmask(image) ||
5090 radv_dcc_enabled(image, range->baseMipLevel)) {
5091 uint32_t color_values[2] = {};
5092 radv_set_color_clear_metadata(cmd_buffer, image, range,
5093 color_values);
5094 }
5095 }
5096
5097 /**
5098 * Handle color image transitions for DCC/FMASK/CMASK.
5099 */
5100 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
5101 struct radv_image *image,
5102 VkImageLayout src_layout,
5103 VkImageLayout dst_layout,
5104 unsigned src_queue_mask,
5105 unsigned dst_queue_mask,
5106 const VkImageSubresourceRange *range)
5107 {
5108 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5109 radv_init_color_image_metadata(cmd_buffer, image,
5110 src_layout, dst_layout,
5111 src_queue_mask, dst_queue_mask,
5112 range);
5113 return;
5114 }
5115
5116 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5117 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
5118 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
5119 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
5120 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
5121 radv_decompress_dcc(cmd_buffer, image, range);
5122 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
5123 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
5124 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5125 }
5126 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
5127 bool fce_eliminate = false, fmask_expand = false;
5128
5129 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
5130 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
5131 fce_eliminate = true;
5132 }
5133
5134 if (radv_image_has_fmask(image)) {
5135 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
5136 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
5137 /* A FMASK decompress is required before doing
5138 * a MSAA decompress using FMASK.
5139 */
5140 fmask_expand = true;
5141 }
5142 }
5143
5144 if (fce_eliminate || fmask_expand)
5145 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5146
5147 if (fmask_expand)
5148 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
5149 }
5150 }
5151
5152 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
5153 struct radv_image *image,
5154 VkImageLayout src_layout,
5155 VkImageLayout dst_layout,
5156 uint32_t src_family,
5157 uint32_t dst_family,
5158 const VkImageSubresourceRange *range,
5159 struct radv_sample_locations_state *sample_locs)
5160 {
5161 if (image->exclusive && src_family != dst_family) {
5162 /* This is an acquire or a release operation and there will be
5163 * a corresponding release/acquire. Do the transition in the
5164 * most flexible queue. */
5165
5166 assert(src_family == cmd_buffer->queue_family_index ||
5167 dst_family == cmd_buffer->queue_family_index);
5168
5169 if (src_family == VK_QUEUE_FAMILY_EXTERNAL ||
5170 src_family == VK_QUEUE_FAMILY_FOREIGN_EXT)
5171 return;
5172
5173 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
5174 return;
5175
5176 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
5177 (src_family == RADV_QUEUE_GENERAL ||
5178 dst_family == RADV_QUEUE_GENERAL))
5179 return;
5180 }
5181
5182 if (src_layout == dst_layout)
5183 return;
5184
5185 unsigned src_queue_mask =
5186 radv_image_queue_family_mask(image, src_family,
5187 cmd_buffer->queue_family_index);
5188 unsigned dst_queue_mask =
5189 radv_image_queue_family_mask(image, dst_family,
5190 cmd_buffer->queue_family_index);
5191
5192 if (vk_format_is_depth(image->vk_format)) {
5193 radv_handle_depth_image_transition(cmd_buffer, image,
5194 src_layout, dst_layout,
5195 src_queue_mask, dst_queue_mask,
5196 range, sample_locs);
5197 } else {
5198 radv_handle_color_image_transition(cmd_buffer, image,
5199 src_layout, dst_layout,
5200 src_queue_mask, dst_queue_mask,
5201 range);
5202 }
5203 }
5204
5205 struct radv_barrier_info {
5206 uint32_t eventCount;
5207 const VkEvent *pEvents;
5208 VkPipelineStageFlags srcStageMask;
5209 VkPipelineStageFlags dstStageMask;
5210 };
5211
5212 static void
5213 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
5214 uint32_t memoryBarrierCount,
5215 const VkMemoryBarrier *pMemoryBarriers,
5216 uint32_t bufferMemoryBarrierCount,
5217 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
5218 uint32_t imageMemoryBarrierCount,
5219 const VkImageMemoryBarrier *pImageMemoryBarriers,
5220 const struct radv_barrier_info *info)
5221 {
5222 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5223 enum radv_cmd_flush_bits src_flush_bits = 0;
5224 enum radv_cmd_flush_bits dst_flush_bits = 0;
5225
5226 for (unsigned i = 0; i < info->eventCount; ++i) {
5227 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
5228 uint64_t va = radv_buffer_get_va(event->bo);
5229
5230 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5231
5232 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
5233
5234 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
5235 assert(cmd_buffer->cs->cdw <= cdw_max);
5236 }
5237
5238 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
5239 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
5240 NULL);
5241 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
5242 NULL);
5243 }
5244
5245 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
5246 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
5247 NULL);
5248 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
5249 NULL);
5250 }
5251
5252 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5253 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5254
5255 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
5256 image);
5257 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
5258 image);
5259 }
5260
5261 /* The Vulkan spec 1.1.98 says:
5262 *
5263 * "An execution dependency with only
5264 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5265 * will only prevent that stage from executing in subsequently
5266 * submitted commands. As this stage does not perform any actual
5267 * execution, this is not observable - in effect, it does not delay
5268 * processing of subsequent commands. Similarly an execution dependency
5269 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5270 * will effectively not wait for any prior commands to complete."
5271 */
5272 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
5273 radv_stage_flush(cmd_buffer, info->srcStageMask);
5274 cmd_buffer->state.flush_bits |= src_flush_bits;
5275
5276 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5277 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5278
5279 const struct VkSampleLocationsInfoEXT *sample_locs_info =
5280 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
5281 SAMPLE_LOCATIONS_INFO_EXT);
5282 struct radv_sample_locations_state sample_locations = {};
5283
5284 if (sample_locs_info) {
5285 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
5286 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
5287 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
5288 sample_locations.count = sample_locs_info->sampleLocationsCount;
5289 typed_memcpy(&sample_locations.locations[0],
5290 sample_locs_info->pSampleLocations,
5291 sample_locs_info->sampleLocationsCount);
5292 }
5293
5294 radv_handle_image_transition(cmd_buffer, image,
5295 pImageMemoryBarriers[i].oldLayout,
5296 pImageMemoryBarriers[i].newLayout,
5297 pImageMemoryBarriers[i].srcQueueFamilyIndex,
5298 pImageMemoryBarriers[i].dstQueueFamilyIndex,
5299 &pImageMemoryBarriers[i].subresourceRange,
5300 sample_locs_info ? &sample_locations : NULL);
5301 }
5302
5303 /* Make sure CP DMA is idle because the driver might have performed a
5304 * DMA operation for copying or filling buffers/images.
5305 */
5306 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5307 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5308 si_cp_dma_wait_for_idle(cmd_buffer);
5309
5310 cmd_buffer->state.flush_bits |= dst_flush_bits;
5311 }
5312
5313 void radv_CmdPipelineBarrier(
5314 VkCommandBuffer commandBuffer,
5315 VkPipelineStageFlags srcStageMask,
5316 VkPipelineStageFlags destStageMask,
5317 VkBool32 byRegion,
5318 uint32_t memoryBarrierCount,
5319 const VkMemoryBarrier* pMemoryBarriers,
5320 uint32_t bufferMemoryBarrierCount,
5321 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5322 uint32_t imageMemoryBarrierCount,
5323 const VkImageMemoryBarrier* pImageMemoryBarriers)
5324 {
5325 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5326 struct radv_barrier_info info;
5327
5328 info.eventCount = 0;
5329 info.pEvents = NULL;
5330 info.srcStageMask = srcStageMask;
5331 info.dstStageMask = destStageMask;
5332
5333 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5334 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5335 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5336 }
5337
5338
5339 static void write_event(struct radv_cmd_buffer *cmd_buffer,
5340 struct radv_event *event,
5341 VkPipelineStageFlags stageMask,
5342 unsigned value)
5343 {
5344 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5345 uint64_t va = radv_buffer_get_va(event->bo);
5346
5347 si_emit_cache_flush(cmd_buffer);
5348
5349 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5350
5351 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
5352
5353 /* Flags that only require a top-of-pipe event. */
5354 VkPipelineStageFlags top_of_pipe_flags =
5355 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
5356
5357 /* Flags that only require a post-index-fetch event. */
5358 VkPipelineStageFlags post_index_fetch_flags =
5359 top_of_pipe_flags |
5360 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
5361 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
5362
5363 /* Make sure CP DMA is idle because the driver might have performed a
5364 * DMA operation for copying or filling buffers/images.
5365 */
5366 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5367 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5368 si_cp_dma_wait_for_idle(cmd_buffer);
5369
5370 /* TODO: Emit EOS events for syncing PS/CS stages. */
5371
5372 if (!(stageMask & ~top_of_pipe_flags)) {
5373 /* Just need to sync the PFP engine. */
5374 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5375 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5376 S_370_WR_CONFIRM(1) |
5377 S_370_ENGINE_SEL(V_370_PFP));
5378 radeon_emit(cs, va);
5379 radeon_emit(cs, va >> 32);
5380 radeon_emit(cs, value);
5381 } else if (!(stageMask & ~post_index_fetch_flags)) {
5382 /* Sync ME because PFP reads index and indirect buffers. */
5383 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5384 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5385 S_370_WR_CONFIRM(1) |
5386 S_370_ENGINE_SEL(V_370_ME));
5387 radeon_emit(cs, va);
5388 radeon_emit(cs, va >> 32);
5389 radeon_emit(cs, value);
5390 } else {
5391 /* Otherwise, sync all prior GPU work using an EOP event. */
5392 si_cs_emit_write_event_eop(cs,
5393 cmd_buffer->device->physical_device->rad_info.chip_class,
5394 radv_cmd_buffer_uses_mec(cmd_buffer),
5395 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5396 EOP_DATA_SEL_VALUE_32BIT, va, value,
5397 cmd_buffer->gfx9_eop_bug_va);
5398 }
5399
5400 assert(cmd_buffer->cs->cdw <= cdw_max);
5401 }
5402
5403 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
5404 VkEvent _event,
5405 VkPipelineStageFlags stageMask)
5406 {
5407 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5408 RADV_FROM_HANDLE(radv_event, event, _event);
5409
5410 write_event(cmd_buffer, event, stageMask, 1);
5411 }
5412
5413 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
5414 VkEvent _event,
5415 VkPipelineStageFlags stageMask)
5416 {
5417 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5418 RADV_FROM_HANDLE(radv_event, event, _event);
5419
5420 write_event(cmd_buffer, event, stageMask, 0);
5421 }
5422
5423 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
5424 uint32_t eventCount,
5425 const VkEvent* pEvents,
5426 VkPipelineStageFlags srcStageMask,
5427 VkPipelineStageFlags dstStageMask,
5428 uint32_t memoryBarrierCount,
5429 const VkMemoryBarrier* pMemoryBarriers,
5430 uint32_t bufferMemoryBarrierCount,
5431 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5432 uint32_t imageMemoryBarrierCount,
5433 const VkImageMemoryBarrier* pImageMemoryBarriers)
5434 {
5435 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5436 struct radv_barrier_info info;
5437
5438 info.eventCount = eventCount;
5439 info.pEvents = pEvents;
5440 info.srcStageMask = 0;
5441
5442 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5443 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5444 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5445 }
5446
5447
5448 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
5449 uint32_t deviceMask)
5450 {
5451 /* No-op */
5452 }
5453
5454 /* VK_EXT_conditional_rendering */
5455 void radv_CmdBeginConditionalRenderingEXT(
5456 VkCommandBuffer commandBuffer,
5457 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
5458 {
5459 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5460 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
5461 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5462 bool draw_visible = true;
5463 uint64_t pred_value = 0;
5464 uint64_t va, new_va;
5465 unsigned pred_offset;
5466
5467 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
5468
5469 /* By default, if the 32-bit value at offset in buffer memory is zero,
5470 * then the rendering commands are discarded, otherwise they are
5471 * executed as normal. If the inverted flag is set, all commands are
5472 * discarded if the value is non zero.
5473 */
5474 if (pConditionalRenderingBegin->flags &
5475 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
5476 draw_visible = false;
5477 }
5478
5479 si_emit_cache_flush(cmd_buffer);
5480
5481 /* From the Vulkan spec 1.1.107:
5482 *
5483 * "If the 32-bit value at offset in buffer memory is zero, then the
5484 * rendering commands are discarded, otherwise they are executed as
5485 * normal. If the value of the predicate in buffer memory changes while
5486 * conditional rendering is active, the rendering commands may be
5487 * discarded in an implementation-dependent way. Some implementations
5488 * may latch the value of the predicate upon beginning conditional
5489 * rendering while others may read it before every rendering command."
5490 *
5491 * But, the AMD hardware treats the predicate as a 64-bit value which
5492 * means we need a workaround in the driver. Luckily, it's not required
5493 * to support if the value changes when predication is active.
5494 *
5495 * The workaround is as follows:
5496 * 1) allocate a 64-value in the upload BO and initialize it to 0
5497 * 2) copy the 32-bit predicate value to the upload BO
5498 * 3) use the new allocated VA address for predication
5499 *
5500 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5501 * in ME (+ sync PFP) instead of PFP.
5502 */
5503 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
5504
5505 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
5506
5507 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5508 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5509 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5510 COPY_DATA_WR_CONFIRM);
5511 radeon_emit(cs, va);
5512 radeon_emit(cs, va >> 32);
5513 radeon_emit(cs, new_va);
5514 radeon_emit(cs, new_va >> 32);
5515
5516 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
5517 radeon_emit(cs, 0);
5518
5519 /* Enable predication for this command buffer. */
5520 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
5521 cmd_buffer->state.predicating = true;
5522
5523 /* Store conditional rendering user info. */
5524 cmd_buffer->state.predication_type = draw_visible;
5525 cmd_buffer->state.predication_va = new_va;
5526 }
5527
5528 void radv_CmdEndConditionalRenderingEXT(
5529 VkCommandBuffer commandBuffer)
5530 {
5531 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5532
5533 /* Disable predication for this command buffer. */
5534 si_emit_set_predication_state(cmd_buffer, false, 0);
5535 cmd_buffer->state.predicating = false;
5536
5537 /* Reset conditional rendering user info. */
5538 cmd_buffer->state.predication_type = -1;
5539 cmd_buffer->state.predication_va = 0;
5540 }
5541
5542 /* VK_EXT_transform_feedback */
5543 void radv_CmdBindTransformFeedbackBuffersEXT(
5544 VkCommandBuffer commandBuffer,
5545 uint32_t firstBinding,
5546 uint32_t bindingCount,
5547 const VkBuffer* pBuffers,
5548 const VkDeviceSize* pOffsets,
5549 const VkDeviceSize* pSizes)
5550 {
5551 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5552 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5553 uint8_t enabled_mask = 0;
5554
5555 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
5556 for (uint32_t i = 0; i < bindingCount; i++) {
5557 uint32_t idx = firstBinding + i;
5558
5559 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
5560 sb[idx].offset = pOffsets[i];
5561 sb[idx].size = pSizes[i];
5562
5563 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
5564 sb[idx].buffer->bo);
5565
5566 enabled_mask |= 1 << idx;
5567 }
5568
5569 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
5570
5571 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
5572 }
5573
5574 static void
5575 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
5576 {
5577 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5578 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5579
5580 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
5581 radeon_emit(cs,
5582 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
5583 S_028B94_RAST_STREAM(0) |
5584 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
5585 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
5586 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
5587 radeon_emit(cs, so->hw_enabled_mask &
5588 so->enabled_stream_buffers_mask);
5589
5590 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5591 }
5592
5593 static void
5594 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
5595 {
5596 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5597 bool old_streamout_enabled = so->streamout_enabled;
5598 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
5599
5600 so->streamout_enabled = enable;
5601
5602 so->hw_enabled_mask = so->enabled_mask |
5603 (so->enabled_mask << 4) |
5604 (so->enabled_mask << 8) |
5605 (so->enabled_mask << 12);
5606
5607 if ((old_streamout_enabled != so->streamout_enabled) ||
5608 (old_hw_enabled_mask != so->hw_enabled_mask))
5609 radv_emit_streamout_enable(cmd_buffer);
5610 }
5611
5612 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
5613 {
5614 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5615 unsigned reg_strmout_cntl;
5616
5617 /* The register is at different places on different ASICs. */
5618 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
5619 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
5620 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
5621 } else {
5622 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
5623 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
5624 }
5625
5626 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
5627 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
5628
5629 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
5630 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
5631 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
5632 radeon_emit(cs, 0);
5633 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5634 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5635 radeon_emit(cs, 4); /* poll interval */
5636 }
5637
5638 void radv_CmdBeginTransformFeedbackEXT(
5639 VkCommandBuffer commandBuffer,
5640 uint32_t firstCounterBuffer,
5641 uint32_t counterBufferCount,
5642 const VkBuffer* pCounterBuffers,
5643 const VkDeviceSize* pCounterBufferOffsets)
5644 {
5645 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5646 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5647 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5648 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5649 uint32_t i;
5650
5651 radv_flush_vgt_streamout(cmd_buffer);
5652
5653 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5654 for_each_bit(i, so->enabled_mask) {
5655 int32_t counter_buffer_idx = i - firstCounterBuffer;
5656 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5657 counter_buffer_idx = -1;
5658
5659 /* AMD GCN binds streamout buffers as shader resources.
5660 * VGT only counts primitives and tells the shader through
5661 * SGPRs what to do.
5662 */
5663 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
5664 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
5665 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
5666
5667 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5668
5669 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5670 /* The array of counter buffers is optional. */
5671 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5672 uint64_t va = radv_buffer_get_va(buffer->bo);
5673
5674 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5675
5676 /* Append */
5677 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5678 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5679 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5680 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
5681 radeon_emit(cs, 0); /* unused */
5682 radeon_emit(cs, 0); /* unused */
5683 radeon_emit(cs, va); /* src address lo */
5684 radeon_emit(cs, va >> 32); /* src address hi */
5685
5686 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5687 } else {
5688 /* Start from the beginning. */
5689 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5690 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5691 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5692 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
5693 radeon_emit(cs, 0); /* unused */
5694 radeon_emit(cs, 0); /* unused */
5695 radeon_emit(cs, 0); /* unused */
5696 radeon_emit(cs, 0); /* unused */
5697 }
5698 }
5699
5700 radv_set_streamout_enable(cmd_buffer, true);
5701 }
5702
5703 void radv_CmdEndTransformFeedbackEXT(
5704 VkCommandBuffer commandBuffer,
5705 uint32_t firstCounterBuffer,
5706 uint32_t counterBufferCount,
5707 const VkBuffer* pCounterBuffers,
5708 const VkDeviceSize* pCounterBufferOffsets)
5709 {
5710 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5711 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5712 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5713 uint32_t i;
5714
5715 radv_flush_vgt_streamout(cmd_buffer);
5716
5717 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5718 for_each_bit(i, so->enabled_mask) {
5719 int32_t counter_buffer_idx = i - firstCounterBuffer;
5720 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5721 counter_buffer_idx = -1;
5722
5723 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5724 /* The array of counters buffer is optional. */
5725 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5726 uint64_t va = radv_buffer_get_va(buffer->bo);
5727
5728 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5729
5730 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5731 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5732 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5733 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
5734 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
5735 radeon_emit(cs, va); /* dst address lo */
5736 radeon_emit(cs, va >> 32); /* dst address hi */
5737 radeon_emit(cs, 0); /* unused */
5738 radeon_emit(cs, 0); /* unused */
5739
5740 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5741 }
5742
5743 /* Deactivate transform feedback by zeroing the buffer size.
5744 * The counters (primitives generated, primitives emitted) may
5745 * be enabled even if there is not buffer bound. This ensures
5746 * that the primitives-emitted query won't increment.
5747 */
5748 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
5749
5750 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5751 }
5752
5753 radv_set_streamout_enable(cmd_buffer, false);
5754 }
5755
5756 void radv_CmdDrawIndirectByteCountEXT(
5757 VkCommandBuffer commandBuffer,
5758 uint32_t instanceCount,
5759 uint32_t firstInstance,
5760 VkBuffer _counterBuffer,
5761 VkDeviceSize counterBufferOffset,
5762 uint32_t counterOffset,
5763 uint32_t vertexStride)
5764 {
5765 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5766 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
5767 struct radv_draw_info info = {};
5768
5769 info.instance_count = instanceCount;
5770 info.first_instance = firstInstance;
5771 info.strmout_buffer = counterBuffer;
5772 info.strmout_buffer_offset = counterBufferOffset;
5773 info.stride = vertexStride;
5774
5775 radv_draw(cmd_buffer, &info);
5776 }
5777
5778 /* VK_AMD_buffer_marker */
5779 void radv_CmdWriteBufferMarkerAMD(
5780 VkCommandBuffer commandBuffer,
5781 VkPipelineStageFlagBits pipelineStage,
5782 VkBuffer dstBuffer,
5783 VkDeviceSize dstOffset,
5784 uint32_t marker)
5785 {
5786 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5787 RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
5788 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5789 uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
5790
5791 si_emit_cache_flush(cmd_buffer);
5792
5793 if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
5794 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5795 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
5796 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5797 COPY_DATA_WR_CONFIRM);
5798 radeon_emit(cs, marker);
5799 radeon_emit(cs, 0);
5800 radeon_emit(cs, va);
5801 radeon_emit(cs, va >> 32);
5802 } else {
5803 si_cs_emit_write_event_eop(cs,
5804 cmd_buffer->device->physical_device->rad_info.chip_class,
5805 radv_cmd_buffer_uses_mec(cmd_buffer),
5806 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5807 EOP_DATA_SEL_VALUE_32BIT,
5808 va, marker,
5809 cmd_buffer->gfx9_eop_bug_va);
5810 }
5811 }