2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "r600d_common.h"
33 static inline unsigned radeon_check_space(struct radeon_winsys
*ws
,
34 struct radeon_winsys_cs
*cs
,
37 if (cs
->max_dw
- cs
->cdw
< needed
)
38 ws
->cs_grow(cs
, needed
);
39 return cs
->cdw
+ needed
;
42 static inline void radeon_set_config_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
44 assert(reg
< R600_CONTEXT_REG_OFFSET
);
45 assert(cs
->cdw
+ 2 + num
<= cs
->max_dw
);
46 radeon_emit(cs
, PKT3(PKT3_SET_CONFIG_REG
, num
, 0));
47 radeon_emit(cs
, (reg
- R600_CONFIG_REG_OFFSET
) >> 2);
50 static inline void radeon_set_config_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
52 radeon_set_config_reg_seq(cs
, reg
, 1);
53 radeon_emit(cs
, value
);
56 static inline void radeon_set_context_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
58 assert(reg
>= R600_CONTEXT_REG_OFFSET
);
59 assert(cs
->cdw
+ 2 + num
<= cs
->max_dw
);
60 radeon_emit(cs
, PKT3(PKT3_SET_CONTEXT_REG
, num
, 0));
61 radeon_emit(cs
, (reg
- R600_CONTEXT_REG_OFFSET
) >> 2);
64 static inline void radeon_set_context_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
66 radeon_set_context_reg_seq(cs
, reg
, 1);
67 radeon_emit(cs
, value
);
71 static inline void radeon_set_context_reg_idx(struct radeon_winsys_cs
*cs
,
72 unsigned reg
, unsigned idx
,
75 assert(reg
>= R600_CONTEXT_REG_OFFSET
);
76 assert(cs
->cdw
+ 3 <= cs
->max_dw
);
77 radeon_emit(cs
, PKT3(PKT3_SET_CONTEXT_REG
, 1, 0));
78 radeon_emit(cs
, (reg
- R600_CONTEXT_REG_OFFSET
) >> 2 | (idx
<< 28));
79 radeon_emit(cs
, value
);
82 static inline void radeon_set_sh_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
84 assert(reg
>= SI_SH_REG_OFFSET
&& reg
< SI_SH_REG_END
);
85 assert(cs
->cdw
+ 2 + num
<= cs
->max_dw
);
86 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, num
, 0));
87 radeon_emit(cs
, (reg
- SI_SH_REG_OFFSET
) >> 2);
90 static inline void radeon_set_sh_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
92 radeon_set_sh_reg_seq(cs
, reg
, 1);
93 radeon_emit(cs
, value
);
96 static inline void radeon_set_uconfig_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
98 assert(reg
>= CIK_UCONFIG_REG_OFFSET
&& reg
< CIK_UCONFIG_REG_END
);
99 assert(cs
->cdw
+ 2 + num
<= cs
->max_dw
);
100 radeon_emit(cs
, PKT3(PKT3_SET_UCONFIG_REG
, num
, 0));
101 radeon_emit(cs
, (reg
- CIK_UCONFIG_REG_OFFSET
) >> 2);
104 static inline void radeon_set_uconfig_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
106 radeon_set_uconfig_reg_seq(cs
, reg
, 1);
107 radeon_emit(cs
, value
);
110 static inline void radeon_set_uconfig_reg_idx(struct radeon_winsys_cs
*cs
,
111 unsigned reg
, unsigned idx
,
114 assert(reg
>= CIK_UCONFIG_REG_OFFSET
&& reg
< CIK_UCONFIG_REG_END
);
115 assert(cs
->cdw
+ 3 <= cs
->max_dw
);
116 radeon_emit(cs
, PKT3(PKT3_SET_UCONFIG_REG
, 1, 0));
117 radeon_emit(cs
, (reg
- CIK_UCONFIG_REG_OFFSET
) >> 2 | (idx
<< 28));
118 radeon_emit(cs
, value
);
121 #endif /* RADV_CS_H */