src/amd/vulkan/radv_cs.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #ifndef RADV_CS_H
  26 #define RADV_CS_H
  27
  28 #include <string.h>
  29 #include <stdint.h>
  30 #include <assert.h>
  31 #include "radv_private.h"
  32 #include "sid.h"
  33
  34 static inline unsigned radeon_check_space(struct radeon_winsys *ws,
  35                                       struct radeon_cmdbuf *cs,
  36                                       unsigned needed)
  37 {
  38         if (cs->max_dw - cs->cdw < needed)
  39                 ws->cs_grow(cs, needed);
  40         return cs->cdw + needed;
  41 }
  42
  43 static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
  44 {
  45         assert(reg >= SI_CONTEXT_REG_OFFSET && reg < SI_CONFIG_REG_END);
  46         assert(cs->cdw + 2 + num <= cs->max_dw);
  47         assert(num);
  48         radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));
  49         radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2);
  50 }
  51
  52 static inline void radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
  53 {
  54         radeon_set_config_reg_seq(cs, reg, 1);
  55         radeon_emit(cs, value);
  56 }
  57
  58 static inline void radeon_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
  59 {
  60         assert(reg >= SI_CONTEXT_REG_OFFSET && reg < SI_CONTEXT_REG_END);
  61         assert(cs->cdw + 2 + num <= cs->max_dw);
  62         assert(num);
  63         radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0));
  64         radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
  65 }
  66
  67 static inline void radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
  68 {
  69         radeon_set_context_reg_seq(cs, reg, 1);
  70         radeon_emit(cs, value);
  71 }
  72
  73
  74 static inline void radeon_set_context_reg_idx(struct radeon_cmdbuf *cs,
  75                                               unsigned reg, unsigned idx,
  76                                               unsigned value)
  77 {
  78         assert(reg >= SI_CONTEXT_REG_OFFSET && reg < SI_CONTEXT_REG_END);
  79         assert(cs->cdw + 3 <= cs->max_dw);
  80         radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0));
  81         radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2 | (idx << 28));
  82         radeon_emit(cs, value);
  83 }
  84
  85 static inline void radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
  86 {
  87         assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
  88         assert(cs->cdw + 2 + num <= cs->max_dw);
  89         assert(num);
  90         radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0));
  91         radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2);
  92 }
  93
  94 static inline void radeon_set_sh_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
  95 {
  96         radeon_set_sh_reg_seq(cs, reg, 1);
  97         radeon_emit(cs, value);
  98 }
  99
 100 static inline void radeon_set_sh_reg_idx(const struct radv_physical_device *pdevice,
 101                                          struct radeon_cmdbuf *cs,
 102                                          unsigned reg, unsigned idx,
 103                                          unsigned value)
 104 {
 105         assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
 106         assert(cs->cdw + 3 <= cs->max_dw);
 107         assert(idx);
 108
 109         unsigned opcode = PKT3_SET_SH_REG_INDEX;
 110         if (pdevice->rad_info.chip_class < GFX10)
 111                 opcode = PKT3_SET_SH_REG;
 112
 113         radeon_emit(cs, PKT3(opcode, 1, 0));
 114         radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2 | (idx << 28));
 115         radeon_emit(cs, value);
 116 }
 117
 118 static inline void radeon_set_uconfig_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
 119 {
 120         assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
 121         assert(cs->cdw + 2 + num <= cs->max_dw);
 122         assert(num);
 123         radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0));
 124         radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
 125 }
 126
 127 static inline void radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
 128 {
 129         radeon_set_uconfig_reg_seq(cs, reg, 1);
 130         radeon_emit(cs, value);
 131 }
 132
 133 static inline void radeon_set_uconfig_reg_idx(const struct radv_physical_device *pdevice,
 134                                               struct radeon_cmdbuf *cs,
 135                                               unsigned reg, unsigned idx,
 136                                               unsigned value)
 137 {
 138         assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
 139         assert(cs->cdw + 3 <= cs->max_dw);
 140         assert(idx);
 141
 142         unsigned opcode = PKT3_SET_UCONFIG_REG_INDEX;
 143         if (pdevice->rad_info.chip_class < GFX9 ||
 144             (pdevice->rad_info.chip_class == GFX9 && pdevice->rad_info.me_fw_version < 26))
 145                 opcode = PKT3_SET_UCONFIG_REG;
 146
 147         radeon_emit(cs, PKT3(opcode, 1, 0));
 148         radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28));
 149         radeon_emit(cs, value);
 150 }
 151
 152 #endif /* RADV_CS_H */