src/amd/vulkan/radv_debug.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #include <stdlib.h>
  29 #include <stdio.h>
  30
  31 #include "sid.h"
  32 #include "gfx9d.h"
  33 #include "ac_debug.h"
  34 #include "radv_debug.h"
  35 #include "radv_shader.h"
  36
  37 #define TRACE_BO_SIZE 4096
  38
  39 #define COLOR_RESET     "\033[0m"
  40 #define COLOR_RED       "\033[31m"
  41 #define COLOR_GREEN     "\033[1;32m"
  42 #define COLOR_YELLOW    "\033[1;33m"
  43 #define COLOR_CYAN      "\033[1;36m"
  44
  45 /* Trace BO layout (offsets are 4 bytes):
  46  *
  47  * [0]: primary trace ID
  48  * [1]: secondary trace ID
  49  * [2-3]: 64-bit GFX pipeline pointer
  50  * [4-5]: 64-bit COMPUTE pipeline pointer
  51  */
  52
  53 bool
  54 radv_init_trace(struct radv_device *device)
  55 {
  56         struct radeon_winsys *ws = device->ws;
  57
  58         device->trace_bo = ws->buffer_create(ws, TRACE_BO_SIZE, 8,
  59                                              RADEON_DOMAIN_VRAM,
  60                                              RADEON_FLAG_CPU_ACCESS);
  61         if (!device->trace_bo)
  62                 return false;
  63
  64         device->trace_id_ptr = ws->buffer_map(device->trace_bo);
  65         if (!device->trace_id_ptr)
  66                 return false;
  67
  68         memset(device->trace_id_ptr, 0, TRACE_BO_SIZE);
  69
  70         ac_vm_fault_occured(device->physical_device->rad_info.chip_class,
  71                             &device->dmesg_timestamp, NULL);
  72
  73         return true;
  74 }
  75
  76 static void
  77 radv_dump_trace(struct radv_device *device, struct radeon_winsys_cs *cs)
  78 {
  79         const char *filename = getenv("RADV_TRACE_FILE");
  80         FILE *f = fopen(filename, "w");
  81
  82         if (!f) {
  83                 fprintf(stderr, "Failed to write trace dump to %s\n", filename);
  84                 return;
  85         }
  86
  87         fprintf(f, "Trace ID: %x\n", *device->trace_id_ptr);
  88         device->ws->cs_dump(cs, f, (const int*)device->trace_id_ptr, 2);
  89         fclose(f);
  90 }
  91
  92 static void
  93 radv_dump_mmapped_reg(struct radv_device *device, FILE *f, unsigned offset)
  94 {
  95         struct radeon_winsys *ws = device->ws;
  96         uint32_t value;
  97
  98         if (ws->read_registers(ws, offset, 1, &value))
  99                 ac_dump_reg(f, device->physical_device->rad_info.chip_class,
 100                             offset, value, ~0);
 101 }
 102
 103 static void
 104 radv_dump_debug_registers(struct radv_device *device, FILE *f)
 105 {
 106         struct radeon_info *info = &device->physical_device->rad_info;
 107
 108         if (info->drm_major == 2 && info->drm_minor < 42)
 109                 return; /* no radeon support */
 110
 111         fprintf(f, "Memory-mapped registers:\n");
 112         radv_dump_mmapped_reg(device, f, R_008010_GRBM_STATUS);
 113
 114         /* No other registers can be read on DRM < 3.1.0. */
 115         if (info->drm_major < 3 || info->drm_minor < 1) {
 116                 fprintf(f, "\n");
 117                 return;
 118         }
 119
 120         radv_dump_mmapped_reg(device, f, R_008008_GRBM_STATUS2);
 121         radv_dump_mmapped_reg(device, f, R_008014_GRBM_STATUS_SE0);
 122         radv_dump_mmapped_reg(device, f, R_008018_GRBM_STATUS_SE1);
 123         radv_dump_mmapped_reg(device, f, R_008038_GRBM_STATUS_SE2);
 124         radv_dump_mmapped_reg(device, f, R_00803C_GRBM_STATUS_SE3);
 125         radv_dump_mmapped_reg(device, f, R_00D034_SDMA0_STATUS_REG);
 126         radv_dump_mmapped_reg(device, f, R_00D834_SDMA1_STATUS_REG);
 127         if (info->chip_class <= VI) {
 128                 radv_dump_mmapped_reg(device, f, R_000E50_SRBM_STATUS);
 129                 radv_dump_mmapped_reg(device, f, R_000E4C_SRBM_STATUS2);
 130                 radv_dump_mmapped_reg(device, f, R_000E54_SRBM_STATUS3);
 131         }
 132         radv_dump_mmapped_reg(device, f, R_008680_CP_STAT);
 133         radv_dump_mmapped_reg(device, f, R_008674_CP_STALLED_STAT1);
 134         radv_dump_mmapped_reg(device, f, R_008678_CP_STALLED_STAT2);
 135         radv_dump_mmapped_reg(device, f, R_008670_CP_STALLED_STAT3);
 136         radv_dump_mmapped_reg(device, f, R_008210_CP_CPC_STATUS);
 137         radv_dump_mmapped_reg(device, f, R_008214_CP_CPC_BUSY_STAT);
 138         radv_dump_mmapped_reg(device, f, R_008218_CP_CPC_STALLED_STAT1);
 139         radv_dump_mmapped_reg(device, f, R_00821C_CP_CPF_STATUS);
 140         radv_dump_mmapped_reg(device, f, R_008220_CP_CPF_BUSY_STAT);
 141         radv_dump_mmapped_reg(device, f, R_008224_CP_CPF_STALLED_STAT1);
 142         fprintf(f, "\n");
 143 }
 144
 145 struct radv_shader_inst {
 146         char text[160];  /* one disasm line */
 147         unsigned offset; /* instruction offset */
 148         unsigned size;   /* instruction size = 4 or 8 */
 149 };
 150
 151 /* Split a disassembly string into lines and add them to the array pointed
 152  * to by "instructions". */
 153 static void si_add_split_disasm(const char *disasm,
 154                                 uint64_t start_addr,
 155                                 unsigned *num,
 156                                 struct radv_shader_inst *instructions)
 157 {
 158         struct radv_shader_inst *last_inst = *num ? &instructions[*num - 1] : NULL;
 159         char *next;
 160
 161         while ((next = strchr(disasm, '\n'))) {
 162                 struct radv_shader_inst *inst = &instructions[*num];
 163                 unsigned len = next - disasm;
 164
 165                 assert(len < ARRAY_SIZE(inst->text));
 166                 memcpy(inst->text, disasm, len);
 167                 inst->text[len] = 0;
 168                 inst->offset = last_inst ? last_inst->offset + last_inst->size : 0;
 169
 170                 const char *semicolon = strchr(disasm, ';');
 171                 assert(semicolon);
 172                 /* More than 16 chars after ";" means the instruction is 8 bytes long. */
 173                 inst->size = next - semicolon > 16 ? 8 : 4;
 174
 175                 snprintf(inst->text + len, ARRAY_SIZE(inst->text) - len,
 176                         " [PC=0x%"PRIx64", off=%u, size=%u]",
 177                         start_addr + inst->offset, inst->offset, inst->size);
 178
 179                 last_inst = inst;
 180                 (*num)++;
 181                 disasm = next + 1;
 182         }
 183 }
 184
 185 static void
 186 radv_dump_annotated_shader(struct radv_pipeline *pipeline,
 187                            struct radv_shader_variant *shader,
 188                            gl_shader_stage stage,
 189                            struct ac_wave_info *waves, unsigned num_waves,
 190                            FILE *f)
 191 {
 192         struct radv_device *device = pipeline->device;
 193         uint64_t start_addr, end_addr;
 194         unsigned i;
 195
 196         if (!shader)
 197                 return;
 198
 199         start_addr = device->ws->buffer_get_va(shader->bo) + shader->bo_offset;
 200         end_addr = start_addr + shader->code_size;
 201
 202         /* See if any wave executes the shader. */
 203         for (i = 0; i < num_waves; i++) {
 204                 if (start_addr <= waves[i].pc && waves[i].pc <= end_addr)
 205                         break;
 206         }
 207
 208         if (i == num_waves)
 209                 return; /* the shader is not being executed */
 210
 211         /* Remember the first found wave. The waves are sorted according to PC. */
 212         waves = &waves[i];
 213         num_waves -= i;
 214
 215         /* Get the list of instructions.
 216          * Buffer size / 4 is the upper bound of the instruction count.
 217          */
 218         unsigned num_inst = 0;
 219         struct radv_shader_inst *instructions =
 220                 calloc(shader->code_size / 4, sizeof(struct radv_shader_inst));
 221
 222         si_add_split_disasm(shader->disasm_string,
 223                             start_addr, &num_inst, instructions);
 224
 225         fprintf(f, COLOR_YELLOW "%s - annotated disassembly:" COLOR_RESET "\n",
 226                 radv_get_shader_name(shader, stage));
 227
 228         /* Print instructions with annotations. */
 229         for (i = 0; i < num_inst; i++) {
 230                 struct radv_shader_inst *inst = &instructions[i];
 231
 232                 fprintf(f, "%s\n", inst->text);
 233
 234                 /* Print which waves execute the instruction right now. */
 235                 while (num_waves && start_addr + inst->offset == waves->pc) {
 236                         fprintf(f,
 237                                 "          " COLOR_GREEN "^ SE%u SH%u CU%u "
 238                                 "SIMD%u WAVE%u  EXEC=%016"PRIx64 "  ",
 239                                 waves->se, waves->sh, waves->cu, waves->simd,
 240                                 waves->wave, waves->exec);
 241
 242                         if (inst->size == 4) {
 243                                 fprintf(f, "INST32=%08X" COLOR_RESET "\n",
 244                                         waves->inst_dw0);
 245                         } else {
 246                                 fprintf(f, "INST64=%08X %08X" COLOR_RESET "\n",
 247                                         waves->inst_dw0, waves->inst_dw1);
 248                         }
 249
 250                         waves->matched = true;
 251                         waves = &waves[1];
 252                         num_waves--;
 253                 }
 254         }
 255
 256         fprintf(f, "\n\n");
 257         free(instructions);
 258 }
 259
 260 static void
 261 radv_dump_annotated_shaders(struct radv_pipeline *pipeline,
 262                             struct radv_shader_variant *compute_shader,
 263                             FILE *f)
 264 {
 265         struct ac_wave_info waves[AC_MAX_WAVES_PER_CHIP];
 266         unsigned num_waves = ac_get_wave_info(waves);
 267         unsigned mask;
 268
 269         fprintf(f, COLOR_CYAN "The number of active waves = %u" COLOR_RESET
 270                 "\n\n", num_waves);
 271
 272         /* Dump annotated active graphics shaders. */
 273         mask = pipeline->active_stages;
 274         while (mask) {
 275                 int stage = u_bit_scan(&mask);
 276
 277                 radv_dump_annotated_shader(pipeline, pipeline->shaders[stage],
 278                                            stage, waves, num_waves, f);
 279         }
 280
 281         radv_dump_annotated_shader(pipeline, compute_shader,
 282                                    MESA_SHADER_COMPUTE, waves, num_waves, f);
 283
 284         /* Print waves executing shaders that are not currently bound. */
 285         unsigned i;
 286         bool found = false;
 287         for (i = 0; i < num_waves; i++) {
 288                 if (waves[i].matched)
 289                         continue;
 290
 291                 if (!found) {
 292                         fprintf(f, COLOR_CYAN
 293                                 "Waves not executing currently-bound shaders:"
 294                                 COLOR_RESET "\n");
 295                         found = true;
 296                 }
 297                 fprintf(f, "    SE%u SH%u CU%u SIMD%u WAVE%u  EXEC=%016"PRIx64
 298                         "  INST=%08X %08X  PC=%"PRIx64"\n",
 299                         waves[i].se, waves[i].sh, waves[i].cu, waves[i].simd,
 300                         waves[i].wave, waves[i].exec, waves[i].inst_dw0,
 301                         waves[i].inst_dw1, waves[i].pc);
 302         }
 303         if (found)
 304                 fprintf(f, "\n\n");
 305 }
 306
 307 static void
 308 radv_dump_shader(struct radv_pipeline *pipeline,
 309                  struct radv_shader_variant *shader, gl_shader_stage stage,
 310                  FILE *f)
 311 {
 312         if (!shader)
 313                 return;
 314
 315         fprintf(f, "%s:\n%s\n\n", radv_get_shader_name(shader, stage),
 316                 shader->disasm_string);
 317
 318         radv_shader_dump_stats(pipeline->device, shader, stage, f);
 319 }
 320
 321 static void
 322 radv_dump_shaders(struct radv_pipeline *pipeline,
 323                   struct radv_shader_variant *compute_shader, FILE *f)
 324 {
 325         unsigned mask;
 326
 327         /* Dump active graphics shaders. */
 328         mask = pipeline->active_stages;
 329         while (mask) {
 330                 int stage = u_bit_scan(&mask);
 331
 332                 radv_dump_shader(pipeline, pipeline->shaders[stage], stage, f);
 333         }
 334
 335         radv_dump_shader(pipeline, compute_shader, MESA_SHADER_COMPUTE, f);
 336 }
 337
 338 static void
 339 radv_dump_graphics_state(struct radv_pipeline *graphics_pipeline,
 340                          struct radv_pipeline *compute_pipeline, FILE *f)
 341 {
 342         struct radv_shader_variant *compute_shader =
 343                 compute_pipeline ? compute_pipeline->shaders[MESA_SHADER_COMPUTE] : NULL;
 344
 345         if (!graphics_pipeline)
 346                 return;
 347
 348         radv_dump_shaders(graphics_pipeline, compute_shader, f);
 349         radv_dump_annotated_shaders(graphics_pipeline, compute_shader, f);
 350 }
 351
 352 static void
 353 radv_dump_compute_state(struct radv_pipeline *compute_pipeline, FILE *f)
 354 {
 355         if (!compute_pipeline)
 356                 return;
 357
 358         radv_dump_shaders(compute_pipeline,
 359                           compute_pipeline->shaders[MESA_SHADER_COMPUTE], f);
 360         radv_dump_annotated_shaders(compute_pipeline,
 361                                     compute_pipeline->shaders[MESA_SHADER_COMPUTE],
 362                                     f);
 363 }
 364
 365 static struct radv_pipeline *
 366 radv_get_saved_graphics_pipeline(struct radv_device *device)
 367 {
 368         uint64_t *ptr = (uint64_t *)device->trace_id_ptr;
 369
 370         return (struct radv_pipeline *)ptr[1];
 371 }
 372
 373 static struct radv_pipeline *
 374 radv_get_saved_compute_pipeline(struct radv_device *device)
 375 {
 376         uint64_t *ptr = (uint64_t *)device->trace_id_ptr;
 377
 378         return (struct radv_pipeline *)ptr[2];
 379 }
 380
 381 static bool
 382 radv_gpu_hang_occured(struct radv_queue *queue, enum ring_type ring)
 383 {
 384         struct radeon_winsys *ws = queue->device->ws;
 385
 386         if (!ws->ctx_wait_idle(queue->hw_ctx, ring, queue->queue_idx))
 387                 return true;
 388
 389         return false;
 390 }
 391
 392 void
 393 radv_check_gpu_hangs(struct radv_queue *queue, struct radeon_winsys_cs *cs)
 394 {
 395         struct radv_pipeline *graphics_pipeline, *compute_pipeline;
 396         struct radv_device *device = queue->device;
 397         enum ring_type ring;
 398         uint64_t addr;
 399
 400         ring = radv_queue_family_to_ring(queue->queue_family_index);
 401
 402         bool hang_occurred = radv_gpu_hang_occured(queue, ring);
 403         bool vm_fault_occurred = false;
 404         if (queue->device->instance->debug_flags & RADV_DEBUG_VM_FAULTS)
 405                 vm_fault_occurred = ac_vm_fault_occured(device->physical_device->rad_info.chip_class,
 406                                                         &device->dmesg_timestamp, &addr);
 407         if (!hang_occurred && !vm_fault_occurred)
 408                 return;
 409
 410         graphics_pipeline = radv_get_saved_graphics_pipeline(device);
 411         compute_pipeline = radv_get_saved_compute_pipeline(device);
 412
 413         if (vm_fault_occurred) {
 414                 fprintf(stderr, "VM fault report.\n\n");
 415                 fprintf(stderr, "Failing VM page: 0x%08"PRIx64"\n\n", addr);
 416         }
 417
 418         radv_dump_debug_registers(device, stderr);
 419
 420         switch (ring) {
 421         case RING_GFX:
 422                 radv_dump_graphics_state(graphics_pipeline, compute_pipeline,
 423                                          stderr);
 424                 break;
 425         case RING_COMPUTE:
 426                 radv_dump_compute_state(compute_pipeline, stderr);
 427                 break;
 428         default:
 429                 assert(0);
 430                 break;
 431         }
 432
 433         radv_dump_trace(queue->device, cs);
 434         abort();
 435 }
 436
 437 void
 438 radv_print_spirv(struct radv_shader_module *module, FILE *fp)
 439 {
 440         char path[] = "/tmp/fileXXXXXX";
 441         char line[2048], command[128];
 442         FILE *p;
 443         int fd;
 444
 445         /* Dump the binary into a temporary file. */
 446         fd = mkstemp(path);
 447         if (fd < 0)
 448                 return;
 449
 450         if (write(fd, module->data, module->size) == -1)
 451                 goto fail;
 452
 453         sprintf(command, "spirv-dis %s", path);
 454
 455         /* Disassemble using spirv-dis if installed. */
 456         p = popen(command, "r");
 457         if (p) {
 458                 while (fgets(line, sizeof(line), p))
 459                         fprintf(fp, "%s", line);
 460                 pclose(p);
 461         }
 462
 463 fail:
 464         close(fd);
 465         unlink(path);
 466 }