2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include <sys/utsname.h>
32 #include "util/mesa-sha1.h"
35 #include "radv_debug.h"
36 #include "radv_shader.h"
38 #define TRACE_BO_SIZE 4096
40 #define COLOR_RESET "\033[0m"
41 #define COLOR_RED "\033[31m"
42 #define COLOR_GREEN "\033[1;32m"
43 #define COLOR_YELLOW "\033[1;33m"
44 #define COLOR_CYAN "\033[1;36m"
46 /* Trace BO layout (offsets are 4 bytes):
48 * [0]: primary trace ID
49 * [1]: secondary trace ID
50 * [2-3]: 64-bit GFX pipeline pointer
51 * [4-5]: 64-bit COMPUTE pipeline pointer
52 * [6-7]: 64-bit descriptor set #0 pointer
54 * [68-69]: 64-bit descriptor set #31 pointer
58 radv_init_trace(struct radv_device
*device
)
60 struct radeon_winsys
*ws
= device
->ws
;
62 device
->trace_bo
= ws
->buffer_create(ws
, TRACE_BO_SIZE
, 8,
64 RADEON_FLAG_CPU_ACCESS
|
65 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
66 RADEON_FLAG_ZERO_VRAM
,
67 RADV_BO_PRIORITY_UPLOAD_BUFFER
);
68 if (!device
->trace_bo
)
71 device
->trace_id_ptr
= ws
->buffer_map(device
->trace_bo
);
72 if (!device
->trace_id_ptr
)
75 ac_vm_fault_occured(device
->physical_device
->rad_info
.chip_class
,
76 &device
->dmesg_timestamp
, NULL
);
82 radv_dump_trace(struct radv_device
*device
, struct radeon_cmdbuf
*cs
)
84 const char *filename
= getenv("RADV_TRACE_FILE");
85 FILE *f
= fopen(filename
, "w");
88 fprintf(stderr
, "Failed to write trace dump to %s\n", filename
);
92 fprintf(f
, "Trace ID: %x\n", *device
->trace_id_ptr
);
93 device
->ws
->cs_dump(cs
, f
, (const int*)device
->trace_id_ptr
, 2);
98 radv_dump_mmapped_reg(struct radv_device
*device
, FILE *f
, unsigned offset
)
100 struct radeon_winsys
*ws
= device
->ws
;
103 if (ws
->read_registers(ws
, offset
, 1, &value
))
104 ac_dump_reg(f
, device
->physical_device
->rad_info
.chip_class
,
109 radv_dump_debug_registers(struct radv_device
*device
, FILE *f
)
111 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
113 fprintf(f
, "Memory-mapped registers:\n");
114 radv_dump_mmapped_reg(device
, f
, R_008010_GRBM_STATUS
);
116 /* No other registers can be read on DRM < 3.1.0. */
117 if (info
->drm_minor
< 1) {
122 radv_dump_mmapped_reg(device
, f
, R_008008_GRBM_STATUS2
);
123 radv_dump_mmapped_reg(device
, f
, R_008014_GRBM_STATUS_SE0
);
124 radv_dump_mmapped_reg(device
, f
, R_008018_GRBM_STATUS_SE1
);
125 radv_dump_mmapped_reg(device
, f
, R_008038_GRBM_STATUS_SE2
);
126 radv_dump_mmapped_reg(device
, f
, R_00803C_GRBM_STATUS_SE3
);
127 radv_dump_mmapped_reg(device
, f
, R_00D034_SDMA0_STATUS_REG
);
128 radv_dump_mmapped_reg(device
, f
, R_00D834_SDMA1_STATUS_REG
);
129 if (info
->chip_class
<= GFX8
) {
130 radv_dump_mmapped_reg(device
, f
, R_000E50_SRBM_STATUS
);
131 radv_dump_mmapped_reg(device
, f
, R_000E4C_SRBM_STATUS2
);
132 radv_dump_mmapped_reg(device
, f
, R_000E54_SRBM_STATUS3
);
134 radv_dump_mmapped_reg(device
, f
, R_008680_CP_STAT
);
135 radv_dump_mmapped_reg(device
, f
, R_008674_CP_STALLED_STAT1
);
136 radv_dump_mmapped_reg(device
, f
, R_008678_CP_STALLED_STAT2
);
137 radv_dump_mmapped_reg(device
, f
, R_008670_CP_STALLED_STAT3
);
138 radv_dump_mmapped_reg(device
, f
, R_008210_CP_CPC_STATUS
);
139 radv_dump_mmapped_reg(device
, f
, R_008214_CP_CPC_BUSY_STAT
);
140 radv_dump_mmapped_reg(device
, f
, R_008218_CP_CPC_STALLED_STAT1
);
141 radv_dump_mmapped_reg(device
, f
, R_00821C_CP_CPF_STATUS
);
142 radv_dump_mmapped_reg(device
, f
, R_008220_CP_CPF_BUSY_STAT
);
143 radv_dump_mmapped_reg(device
, f
, R_008224_CP_CPF_STALLED_STAT1
);
148 radv_dump_buffer_descriptor(enum chip_class chip_class
, const uint32_t *desc
,
151 fprintf(f
, COLOR_CYAN
" Buffer:" COLOR_RESET
"\n");
152 for (unsigned j
= 0; j
< 4; j
++)
153 ac_dump_reg(f
, chip_class
, R_008F00_SQ_BUF_RSRC_WORD0
+ j
* 4,
154 desc
[j
], 0xffffffff);
158 radv_dump_image_descriptor(enum chip_class chip_class
, const uint32_t *desc
,
161 unsigned sq_img_rsrc_word0
= chip_class
>= GFX10
? R_00A000_SQ_IMG_RSRC_WORD0
162 : R_008F10_SQ_IMG_RSRC_WORD0
;
164 fprintf(f
, COLOR_CYAN
" Image:" COLOR_RESET
"\n");
165 for (unsigned j
= 0; j
< 8; j
++)
166 ac_dump_reg(f
, chip_class
, sq_img_rsrc_word0
+ j
* 4,
167 desc
[j
], 0xffffffff);
169 fprintf(f
, COLOR_CYAN
" FMASK:" COLOR_RESET
"\n");
170 for (unsigned j
= 0; j
< 8; j
++)
171 ac_dump_reg(f
, chip_class
, sq_img_rsrc_word0
+ j
* 4,
172 desc
[8 + j
], 0xffffffff);
176 radv_dump_sampler_descriptor(enum chip_class chip_class
, const uint32_t *desc
,
179 fprintf(f
, COLOR_CYAN
" Sampler state:" COLOR_RESET
"\n");
180 for (unsigned j
= 0; j
< 4; j
++) {
181 ac_dump_reg(f
, chip_class
, R_008F30_SQ_IMG_SAMP_WORD0
+ j
* 4,
182 desc
[j
], 0xffffffff);
187 radv_dump_combined_image_sampler_descriptor(enum chip_class chip_class
,
188 const uint32_t *desc
, FILE *f
)
190 radv_dump_image_descriptor(chip_class
, desc
, f
);
191 radv_dump_sampler_descriptor(chip_class
, desc
+ 16, f
);
195 radv_dump_descriptor_set(struct radv_device
*device
,
196 struct radv_descriptor_set
*set
, unsigned id
, FILE *f
)
198 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
199 const struct radv_descriptor_set_layout
*layout
;
204 layout
= set
->layout
;
206 for (i
= 0; i
< set
->layout
->binding_count
; i
++) {
208 set
->mapped_ptr
+ layout
->binding
[i
].offset
/ 4;
210 switch (layout
->binding
[i
].type
) {
211 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
212 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
213 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
214 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
215 radv_dump_buffer_descriptor(chip_class
, desc
, f
);
217 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
:
218 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
:
219 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
220 radv_dump_image_descriptor(chip_class
, desc
, f
);
222 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
223 radv_dump_combined_image_sampler_descriptor(chip_class
, desc
, f
);
225 case VK_DESCRIPTOR_TYPE_SAMPLER
:
226 radv_dump_sampler_descriptor(chip_class
, desc
, f
);
228 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
229 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
:
233 assert(!"unknown descriptor type");
242 radv_dump_descriptors(struct radv_device
*device
, FILE *f
)
244 uint64_t *ptr
= (uint64_t *)device
->trace_id_ptr
;
247 fprintf(f
, "Descriptors:\n");
248 for (i
= 0; i
< MAX_SETS
; i
++) {
249 struct radv_descriptor_set
*set
=
250 *(struct radv_descriptor_set
**)(ptr
+ i
+ 3);
252 radv_dump_descriptor_set(device
, set
, i
, f
);
256 struct radv_shader_inst
{
257 char text
[160]; /* one disasm line */
258 unsigned offset
; /* instruction offset */
259 unsigned size
; /* instruction size = 4 or 8 */
262 /* Split a disassembly string into lines and add them to the array pointed
263 * to by "instructions". */
264 static void si_add_split_disasm(const char *disasm
,
267 struct radv_shader_inst
*instructions
)
269 struct radv_shader_inst
*last_inst
= *num
? &instructions
[*num
- 1] : NULL
;
272 while ((next
= strchr(disasm
, '\n'))) {
273 struct radv_shader_inst
*inst
= &instructions
[*num
];
274 unsigned len
= next
- disasm
;
276 assert(len
< ARRAY_SIZE(inst
->text
));
277 memcpy(inst
->text
, disasm
, len
);
279 inst
->offset
= last_inst
? last_inst
->offset
+ last_inst
->size
: 0;
281 const char *semicolon
= strchr(disasm
, ';');
283 /* More than 16 chars after ";" means the instruction is 8 bytes long. */
284 inst
->size
= next
- semicolon
> 16 ? 8 : 4;
286 snprintf(inst
->text
+ len
, ARRAY_SIZE(inst
->text
) - len
,
287 " [PC=0x%"PRIx64
", off=%u, size=%u]",
288 start_addr
+ inst
->offset
, inst
->offset
, inst
->size
);
297 radv_dump_annotated_shader(struct radv_shader_variant
*shader
,
298 gl_shader_stage stage
, struct ac_wave_info
*waves
,
299 unsigned num_waves
, FILE *f
)
301 uint64_t start_addr
, end_addr
;
307 start_addr
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
308 end_addr
= start_addr
+ shader
->code_size
;
310 /* See if any wave executes the shader. */
311 for (i
= 0; i
< num_waves
; i
++) {
312 if (start_addr
<= waves
[i
].pc
&& waves
[i
].pc
<= end_addr
)
317 return; /* the shader is not being executed */
319 /* Remember the first found wave. The waves are sorted according to PC. */
323 /* Get the list of instructions.
324 * Buffer size / 4 is the upper bound of the instruction count.
326 unsigned num_inst
= 0;
327 struct radv_shader_inst
*instructions
=
328 calloc(shader
->code_size
/ 4, sizeof(struct radv_shader_inst
));
330 si_add_split_disasm(shader
->disasm_string
,
331 start_addr
, &num_inst
, instructions
);
333 fprintf(f
, COLOR_YELLOW
"%s - annotated disassembly:" COLOR_RESET
"\n",
334 radv_get_shader_name(&shader
->info
, stage
));
336 /* Print instructions with annotations. */
337 for (i
= 0; i
< num_inst
; i
++) {
338 struct radv_shader_inst
*inst
= &instructions
[i
];
340 fprintf(f
, "%s\n", inst
->text
);
342 /* Print which waves execute the instruction right now. */
343 while (num_waves
&& start_addr
+ inst
->offset
== waves
->pc
) {
345 " " COLOR_GREEN
"^ SE%u SH%u CU%u "
346 "SIMD%u WAVE%u EXEC=%016"PRIx64
" ",
347 waves
->se
, waves
->sh
, waves
->cu
, waves
->simd
,
348 waves
->wave
, waves
->exec
);
350 if (inst
->size
== 4) {
351 fprintf(f
, "INST32=%08X" COLOR_RESET
"\n",
354 fprintf(f
, "INST64=%08X %08X" COLOR_RESET
"\n",
355 waves
->inst_dw0
, waves
->inst_dw1
);
358 waves
->matched
= true;
369 radv_dump_annotated_shaders(struct radv_pipeline
*pipeline
,
370 VkShaderStageFlagBits active_stages
, FILE *f
)
372 struct ac_wave_info waves
[AC_MAX_WAVES_PER_CHIP
];
373 enum chip_class chip_class
= pipeline
->device
->physical_device
->rad_info
.chip_class
;
374 unsigned num_waves
= ac_get_wave_info(chip_class
, waves
);
376 fprintf(f
, COLOR_CYAN
"The number of active waves = %u" COLOR_RESET
379 /* Dump annotated active graphics shaders. */
380 while (active_stages
) {
381 int stage
= u_bit_scan(&active_stages
);
383 radv_dump_annotated_shader(pipeline
->shaders
[stage
],
384 stage
, waves
, num_waves
, f
);
387 /* Print waves executing shaders that are not currently bound. */
390 for (i
= 0; i
< num_waves
; i
++) {
391 if (waves
[i
].matched
)
395 fprintf(f
, COLOR_CYAN
396 "Waves not executing currently-bound shaders:"
400 fprintf(f
, " SE%u SH%u CU%u SIMD%u WAVE%u EXEC=%016"PRIx64
401 " INST=%08X %08X PC=%"PRIx64
"\n",
402 waves
[i
].se
, waves
[i
].sh
, waves
[i
].cu
, waves
[i
].simd
,
403 waves
[i
].wave
, waves
[i
].exec
, waves
[i
].inst_dw0
,
404 waves
[i
].inst_dw1
, waves
[i
].pc
);
411 radv_dump_shader(struct radv_pipeline
*pipeline
,
412 struct radv_shader_variant
*shader
, gl_shader_stage stage
,
418 fprintf(f
, "%s:\n\n", radv_get_shader_name(&shader
->info
, stage
));
421 unsigned char sha1
[21];
424 _mesa_sha1_compute(shader
->spirv
, shader
->spirv_size
, sha1
);
425 _mesa_sha1_format(sha1buf
, sha1
);
427 fprintf(f
, "SPIRV (sha1: %s):\n", sha1buf
);
428 radv_print_spirv(shader
->spirv
, shader
->spirv_size
, f
);
431 if (shader
->nir_string
) {
432 fprintf(f
, "NIR:\n%s\n", shader
->nir_string
);
435 fprintf(f
, "%s IR:\n%s\n",
436 pipeline
->device
->physical_device
->use_llvm
? "LLVM" : "ACO",
438 fprintf(f
, "DISASM:\n%s\n", shader
->disasm_string
);
440 radv_shader_dump_stats(pipeline
->device
, shader
, stage
, f
);
444 radv_dump_shaders(struct radv_pipeline
*pipeline
,
445 VkShaderStageFlagBits active_stages
, FILE *f
)
447 /* Dump active graphics shaders. */
448 while (active_stages
) {
449 int stage
= u_bit_scan(&active_stages
);
451 radv_dump_shader(pipeline
, pipeline
->shaders
[stage
], stage
, f
);
456 radv_dump_pipeline_state(struct radv_pipeline
*pipeline
,
457 VkShaderStageFlagBits active_stages
, FILE *f
)
459 radv_dump_shaders(pipeline
, active_stages
, f
);
460 radv_dump_annotated_shaders(pipeline
, active_stages
, f
);
464 radv_dump_graphics_state(struct radv_device
*device
,
465 struct radv_pipeline
*graphics_pipeline
,
466 struct radv_pipeline
*compute_pipeline
, FILE *f
)
468 VkShaderStageFlagBits active_stages
;
470 if (graphics_pipeline
) {
471 active_stages
= graphics_pipeline
->active_stages
;
472 radv_dump_pipeline_state(graphics_pipeline
, active_stages
, f
);
475 if (compute_pipeline
) {
476 active_stages
= VK_SHADER_STAGE_COMPUTE_BIT
;
477 radv_dump_pipeline_state(compute_pipeline
, active_stages
, f
);
480 radv_dump_descriptors(device
, f
);
484 radv_dump_compute_state(struct radv_device
*device
,
485 struct radv_pipeline
*compute_pipeline
, FILE *f
)
487 VkShaderStageFlagBits active_stages
= VK_SHADER_STAGE_COMPUTE_BIT
;
489 if (!compute_pipeline
)
492 radv_dump_pipeline_state(compute_pipeline
, active_stages
, f
);
493 radv_dump_descriptors(device
, f
);
496 static struct radv_pipeline
*
497 radv_get_saved_graphics_pipeline(struct radv_device
*device
)
499 uint64_t *ptr
= (uint64_t *)device
->trace_id_ptr
;
501 return *(struct radv_pipeline
**)(ptr
+ 1);
504 static struct radv_pipeline
*
505 radv_get_saved_compute_pipeline(struct radv_device
*device
)
507 uint64_t *ptr
= (uint64_t *)device
->trace_id_ptr
;
509 return *(struct radv_pipeline
**)(ptr
+ 2);
513 radv_dump_dmesg(FILE *f
)
518 p
= popen("dmesg | tail -n60", "r");
522 fprintf(f
, "\nLast 60 lines of dmesg:\n\n");
523 while (fgets(line
, sizeof(line
), p
))
531 radv_dump_enabled_options(struct radv_device
*device
, FILE *f
)
535 if (device
->instance
->debug_flags
) {
536 fprintf(f
, "Enabled debug options: ");
538 mask
= device
->instance
->debug_flags
;
540 int i
= u_bit_scan64(&mask
);
541 fprintf(f
, "%s, ", radv_get_debug_option_name(i
));
546 if (device
->instance
->perftest_flags
) {
547 fprintf(f
, "Enabled perftest options: ");
549 mask
= device
->instance
->perftest_flags
;
551 int i
= u_bit_scan64(&mask
);
552 fprintf(f
, "%s, ", radv_get_perftest_option_name(i
));
559 radv_dump_device_name(struct radv_device
*device
, FILE *f
)
561 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
562 char kernel_version
[128] = {};
563 struct utsname uname_data
;
564 const char *chip_name
;
566 chip_name
= device
->ws
->get_chip_name(device
->ws
);
568 if (uname(&uname_data
) == 0)
569 snprintf(kernel_version
, sizeof(kernel_version
),
570 " / %s", uname_data
.release
);
572 fprintf(f
, "Device name: %s (%s / DRM %i.%i.%i%s)\n\n",
573 chip_name
, device
->physical_device
->name
,
574 info
->drm_major
, info
->drm_minor
, info
->drm_patchlevel
,
579 radv_gpu_hang_occured(struct radv_queue
*queue
, enum ring_type ring
)
581 struct radeon_winsys
*ws
= queue
->device
->ws
;
583 if (!ws
->ctx_wait_idle(queue
->hw_ctx
, ring
, queue
->queue_idx
))
590 radv_check_gpu_hangs(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
)
592 struct radv_pipeline
*graphics_pipeline
, *compute_pipeline
;
593 struct radv_device
*device
= queue
->device
;
597 ring
= radv_queue_family_to_ring(queue
->queue_family_index
);
599 bool hang_occurred
= radv_gpu_hang_occured(queue
, ring
);
600 bool vm_fault_occurred
= false;
601 if (queue
->device
->instance
->debug_flags
& RADV_DEBUG_VM_FAULTS
)
602 vm_fault_occurred
= ac_vm_fault_occured(device
->physical_device
->rad_info
.chip_class
,
603 &device
->dmesg_timestamp
, &addr
);
604 if (!hang_occurred
&& !vm_fault_occurred
)
607 graphics_pipeline
= radv_get_saved_graphics_pipeline(device
);
608 compute_pipeline
= radv_get_saved_compute_pipeline(device
);
610 radv_dump_trace(queue
->device
, cs
);
612 fprintf(stderr
, "GPU hang report:\n\n");
613 radv_dump_device_name(device
, stderr
);
615 radv_dump_enabled_options(device
, stderr
);
616 radv_dump_dmesg(stderr
);
618 if (vm_fault_occurred
) {
619 fprintf(stderr
, "VM fault report.\n\n");
620 fprintf(stderr
, "Failing VM page: 0x%08"PRIx64
"\n\n", addr
);
623 radv_dump_debug_registers(device
, stderr
);
627 fprintf(stderr
, "RING_GFX:\n");
628 radv_dump_graphics_state(queue
->device
,
629 graphics_pipeline
, compute_pipeline
,
633 fprintf(stderr
, "RING_COMPUTE:\n");
634 radv_dump_compute_state(queue
->device
,
635 compute_pipeline
, stderr
);
646 radv_print_spirv(const char *data
, uint32_t size
, FILE *fp
)
648 char path
[] = "/tmp/fileXXXXXX";
649 char line
[2048], command
[128];
653 /* Dump the binary into a temporary file. */
658 if (write(fd
, data
, size
) == -1)
661 sprintf(command
, "spirv-dis %s", path
);
663 /* Disassemble using spirv-dis if installed. */
664 p
= popen(command
, "r");
666 while (fgets(line
, sizeof(line
), p
))
667 fprintf(fp
, "%s", line
);