src/amd/vulkan/radv_debug.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #include <stdlib.h>
  29 #include <stdio.h>
  30 #include <sys/utsname.h>
  31
  32 #include "sid.h"
  33 #include "gfx9d.h"
  34 #include "ac_debug.h"
  35 #include "radv_debug.h"
  36 #include "radv_shader.h"
  37
  38 #define TRACE_BO_SIZE 4096
  39
  40 #define COLOR_RESET     "\033[0m"
  41 #define COLOR_RED       "\033[31m"
  42 #define COLOR_GREEN     "\033[1;32m"
  43 #define COLOR_YELLOW    "\033[1;33m"
  44 #define COLOR_CYAN      "\033[1;36m"
  45
  46 /* Trace BO layout (offsets are 4 bytes):
  47  *
  48  * [0]: primary trace ID
  49  * [1]: secondary trace ID
  50  * [2-3]: 64-bit GFX pipeline pointer
  51  * [4-5]: 64-bit COMPUTE pipeline pointer
  52  * [6-7]: 64-bit descriptor set #0 pointer
  53  * ...
  54  * [68-69]: 64-bit descriptor set #31 pointer
  55  */
  56
  57 bool
  58 radv_init_trace(struct radv_device *device)
  59 {
  60         struct radeon_winsys *ws = device->ws;
  61
  62         device->trace_bo = ws->buffer_create(ws, TRACE_BO_SIZE, 8,
  63                                              RADEON_DOMAIN_VRAM,
  64                                              RADEON_FLAG_CPU_ACCESS|
  65                                              RADEON_FLAG_NO_INTERPROCESS_SHARING);
  66         if (!device->trace_bo)
  67                 return false;
  68
  69         device->trace_id_ptr = ws->buffer_map(device->trace_bo);
  70         if (!device->trace_id_ptr)
  71                 return false;
  72
  73         memset(device->trace_id_ptr, 0, TRACE_BO_SIZE);
  74
  75         ac_vm_fault_occured(device->physical_device->rad_info.chip_class,
  76                             &device->dmesg_timestamp, NULL);
  77
  78         return true;
  79 }
  80
  81 static void
  82 radv_dump_trace(struct radv_device *device, struct radeon_winsys_cs *cs)
  83 {
  84         const char *filename = getenv("RADV_TRACE_FILE");
  85         FILE *f = fopen(filename, "w");
  86
  87         if (!f) {
  88                 fprintf(stderr, "Failed to write trace dump to %s\n", filename);
  89                 return;
  90         }
  91
  92         fprintf(f, "Trace ID: %x\n", *device->trace_id_ptr);
  93         device->ws->cs_dump(cs, f, (const int*)device->trace_id_ptr, 2);
  94         fclose(f);
  95 }
  96
  97 static void
  98 radv_dump_mmapped_reg(struct radv_device *device, FILE *f, unsigned offset)
  99 {
 100         struct radeon_winsys *ws = device->ws;
 101         uint32_t value;
 102
 103         if (ws->read_registers(ws, offset, 1, &value))
 104                 ac_dump_reg(f, device->physical_device->rad_info.chip_class,
 105                             offset, value, ~0);
 106 }
 107
 108 static void
 109 radv_dump_debug_registers(struct radv_device *device, FILE *f)
 110 {
 111         struct radeon_info *info = &device->physical_device->rad_info;
 112
 113         if (info->drm_major == 2 && info->drm_minor < 42)
 114                 return; /* no radeon support */
 115
 116         fprintf(f, "Memory-mapped registers:\n");
 117         radv_dump_mmapped_reg(device, f, R_008010_GRBM_STATUS);
 118
 119         /* No other registers can be read on DRM < 3.1.0. */
 120         if (info->drm_major < 3 || info->drm_minor < 1) {
 121                 fprintf(f, "\n");
 122                 return;
 123         }
 124
 125         radv_dump_mmapped_reg(device, f, R_008008_GRBM_STATUS2);
 126         radv_dump_mmapped_reg(device, f, R_008014_GRBM_STATUS_SE0);
 127         radv_dump_mmapped_reg(device, f, R_008018_GRBM_STATUS_SE1);
 128         radv_dump_mmapped_reg(device, f, R_008038_GRBM_STATUS_SE2);
 129         radv_dump_mmapped_reg(device, f, R_00803C_GRBM_STATUS_SE3);
 130         radv_dump_mmapped_reg(device, f, R_00D034_SDMA0_STATUS_REG);
 131         radv_dump_mmapped_reg(device, f, R_00D834_SDMA1_STATUS_REG);
 132         if (info->chip_class <= VI) {
 133                 radv_dump_mmapped_reg(device, f, R_000E50_SRBM_STATUS);
 134                 radv_dump_mmapped_reg(device, f, R_000E4C_SRBM_STATUS2);
 135                 radv_dump_mmapped_reg(device, f, R_000E54_SRBM_STATUS3);
 136         }
 137         radv_dump_mmapped_reg(device, f, R_008680_CP_STAT);
 138         radv_dump_mmapped_reg(device, f, R_008674_CP_STALLED_STAT1);
 139         radv_dump_mmapped_reg(device, f, R_008678_CP_STALLED_STAT2);
 140         radv_dump_mmapped_reg(device, f, R_008670_CP_STALLED_STAT3);
 141         radv_dump_mmapped_reg(device, f, R_008210_CP_CPC_STATUS);
 142         radv_dump_mmapped_reg(device, f, R_008214_CP_CPC_BUSY_STAT);
 143         radv_dump_mmapped_reg(device, f, R_008218_CP_CPC_STALLED_STAT1);
 144         radv_dump_mmapped_reg(device, f, R_00821C_CP_CPF_STATUS);
 145         radv_dump_mmapped_reg(device, f, R_008220_CP_CPF_BUSY_STAT);
 146         radv_dump_mmapped_reg(device, f, R_008224_CP_CPF_STALLED_STAT1);
 147         fprintf(f, "\n");
 148 }
 149
 150 static const char *
 151 radv_get_descriptor_name(enum VkDescriptorType type)
 152 {
 153         switch (type) {
 154         case VK_DESCRIPTOR_TYPE_SAMPLER:
 155                 return "SAMPLER";
 156         case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
 157                 return "COMBINED_IMAGE_SAMPLER";
 158         case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
 159                 return "SAMPLED_IMAGE";
 160         case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
 161                 return "STORAGE_IMAGE";
 162         case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
 163                 return "UNIFORM_TEXEL_BUFFER";
 164         case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
 165                 return "STORAGE_TEXEL_BUFFER";
 166         case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
 167                 return "UNIFORM_BUFFER";
 168         case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
 169                 return "STORAGE_BUFFER";
 170         case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
 171                 return "UNIFORM_BUFFER_DYNAMIC";
 172         case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
 173                 return "STORAGE_BUFFER_DYNAMIC";
 174         case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
 175                 return "INPUT_ATTACHMENT";
 176         default:
 177                 return "UNKNOWN";
 178         }
 179 }
 180
 181 static void
 182 radv_dump_buffer_descriptor(enum chip_class chip_class, const uint32_t *desc,
 183                             FILE *f)
 184 {
 185         fprintf(f, COLOR_CYAN "    Buffer:" COLOR_RESET "\n");
 186         for (unsigned j = 0; j < 4; j++)
 187                 ac_dump_reg(f, chip_class, R_008F00_SQ_BUF_RSRC_WORD0 + j * 4,
 188                             desc[j], 0xffffffff);
 189 }
 190
 191 static void
 192 radv_dump_image_descriptor(enum chip_class chip_class, const uint32_t *desc,
 193                            FILE *f)
 194 {
 195         fprintf(f, COLOR_CYAN "    Image:" COLOR_RESET "\n");
 196         for (unsigned j = 0; j < 8; j++)
 197                 ac_dump_reg(f, chip_class, R_008F10_SQ_IMG_RSRC_WORD0 + j * 4,
 198                             desc[j], 0xffffffff);
 199
 200         fprintf(f, COLOR_CYAN "    FMASK:" COLOR_RESET "\n");
 201         for (unsigned j = 0; j < 8; j++)
 202                 ac_dump_reg(f, chip_class, R_008F10_SQ_IMG_RSRC_WORD0 + j * 4,
 203                             desc[8 + j], 0xffffffff);
 204 }
 205
 206 static void
 207 radv_dump_sampler_descriptor(enum chip_class chip_class, const uint32_t *desc,
 208                              FILE *f)
 209 {
 210         fprintf(f, COLOR_CYAN "    Sampler state:" COLOR_RESET "\n");
 211         for (unsigned j = 0; j < 4; j++) {
 212                 ac_dump_reg(f, chip_class, R_008F30_SQ_IMG_SAMP_WORD0 + j * 4,
 213                             desc[j], 0xffffffff);
 214         }
 215 }
 216
 217 static void
 218 radv_dump_combined_image_sampler_descriptor(enum chip_class chip_class,
 219                                             const uint32_t *desc, FILE *f)
 220 {
 221         radv_dump_image_descriptor(chip_class, desc, f);
 222         radv_dump_sampler_descriptor(chip_class, desc + 16, f);
 223 }
 224
 225 static void
 226 radv_dump_descriptor_set(enum chip_class chip_class,
 227                          struct radv_descriptor_set *set, unsigned id, FILE *f)
 228 {
 229         const struct radv_descriptor_set_layout *layout;
 230         int i;
 231
 232         if (!set)
 233                 return;
 234         layout = set->layout;
 235
 236         fprintf(f, "** descriptor set (%d) **\n", id);
 237         fprintf(f, "va: 0x%"PRIx64"\n", set->va);
 238         fprintf(f, "size: %d\n", set->size);
 239         fprintf(f, "mapped_ptr:\n");
 240
 241         for (i = 0; i < set->size / 4; i++) {
 242                 fprintf(f, "\t[0x%x] = 0x%08x\n", i, set->mapped_ptr[i]);
 243         }
 244         fprintf(f, "\n");
 245
 246         fprintf(f, "\t*** layout ***\n");
 247         fprintf(f, "\tbinding_count: %d\n", layout->binding_count);
 248         fprintf(f, "\tsize: %d\n", layout->size);
 249         fprintf(f, "\tshader_stages: %x\n", layout->shader_stages);
 250         fprintf(f, "\tdynamic_shader_stages: %x\n",
 251                 layout->dynamic_shader_stages);
 252         fprintf(f, "\tdynamic_offset_count: %d\n",
 253                 layout->dynamic_offset_count);
 254         fprintf(f, "\n");
 255
 256         for (i = 0; i < set->layout->binding_count; i++) {
 257                 uint32_t *desc =
 258                         set->mapped_ptr + layout->binding[i].offset / 4;
 259
 260                 fprintf(f, "\t\t**** binding layout (%d) ****\n", i);
 261                 fprintf(f, "\t\ttype: %s\n",
 262                         radv_get_descriptor_name(layout->binding[i].type));
 263                 fprintf(f, "\t\tarray_size: %d\n",
 264                         layout->binding[i].array_size);
 265                 fprintf(f, "\t\toffset: %d\n",
 266                         layout->binding[i].offset);
 267                 fprintf(f, "\t\tdynamic_offset_offset: %d\n",
 268                         layout->binding[i].dynamic_offset_offset);
 269                 fprintf(f, "\t\tdynamic_offset_count: %d\n",
 270                         layout->binding[i].dynamic_offset_count);
 271                 fprintf(f, "\t\tsize: %d\n",
 272                         layout->binding[i].size);
 273                 fprintf(f, "\t\timmutable_samplers_offset: %d\n",
 274                         layout->binding[i].immutable_samplers_offset);
 275                 fprintf(f, "\t\timmutable_samplers_equal: %d\n",
 276                         layout->binding[i].immutable_samplers_equal);
 277                 fprintf(f, "\n");
 278
 279                 switch (layout->binding[i].type) {
 280                 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
 281                 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
 282                 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
 283                 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
 284                         radv_dump_buffer_descriptor(chip_class, desc, f);
 285                         break;
 286                 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
 287                 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
 288                 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
 289                         radv_dump_image_descriptor(chip_class, desc, f);
 290                         break;
 291                 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
 292                         radv_dump_combined_image_sampler_descriptor(chip_class, desc, f);
 293                         break;
 294                 case VK_DESCRIPTOR_TYPE_SAMPLER:
 295                         radv_dump_sampler_descriptor(chip_class, desc, f);
 296                         break;
 297                 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
 298                 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
 299                         /* todo */
 300                         break;
 301                 default:
 302                         assert(!"unknown descriptor type");
 303                         break;
 304                 }
 305                 fprintf(f, "\n");
 306         }
 307         fprintf(f, "\n\n");
 308 }
 309
 310 static void
 311 radv_dump_descriptors(struct radv_pipeline *pipeline, FILE *f)
 312 {
 313         struct radv_device *device = pipeline->device;
 314         enum chip_class chip_class = device->physical_device->rad_info.chip_class;
 315         uint64_t *ptr = (uint64_t *)device->trace_id_ptr;
 316         int i;
 317
 318         fprintf(f, "List of descriptors:\n");
 319         for (i = 0; i < MAX_SETS; i++) {
 320                 struct radv_descriptor_set *set =
 321                         (struct radv_descriptor_set *)ptr[i + 3];
 322
 323                 radv_dump_descriptor_set(chip_class, set, i, f);
 324         }
 325 }
 326
 327 struct radv_shader_inst {
 328         char text[160];  /* one disasm line */
 329         unsigned offset; /* instruction offset */
 330         unsigned size;   /* instruction size = 4 or 8 */
 331 };
 332
 333 /* Split a disassembly string into lines and add them to the array pointed
 334  * to by "instructions". */
 335 static void si_add_split_disasm(const char *disasm,
 336                                 uint64_t start_addr,
 337                                 unsigned *num,
 338                                 struct radv_shader_inst *instructions)
 339 {
 340         struct radv_shader_inst *last_inst = *num ? &instructions[*num - 1] : NULL;
 341         char *next;
 342
 343         while ((next = strchr(disasm, '\n'))) {
 344                 struct radv_shader_inst *inst = &instructions[*num];
 345                 unsigned len = next - disasm;
 346
 347                 assert(len < ARRAY_SIZE(inst->text));
 348                 memcpy(inst->text, disasm, len);
 349                 inst->text[len] = 0;
 350                 inst->offset = last_inst ? last_inst->offset + last_inst->size : 0;
 351
 352                 const char *semicolon = strchr(disasm, ';');
 353                 assert(semicolon);
 354                 /* More than 16 chars after ";" means the instruction is 8 bytes long. */
 355                 inst->size = next - semicolon > 16 ? 8 : 4;
 356
 357                 snprintf(inst->text + len, ARRAY_SIZE(inst->text) - len,
 358                         " [PC=0x%"PRIx64", off=%u, size=%u]",
 359                         start_addr + inst->offset, inst->offset, inst->size);
 360
 361                 last_inst = inst;
 362                 (*num)++;
 363                 disasm = next + 1;
 364         }
 365 }
 366
 367 static void
 368 radv_dump_annotated_shader(struct radv_pipeline *pipeline,
 369                            struct radv_shader_variant *shader,
 370                            gl_shader_stage stage,
 371                            struct ac_wave_info *waves, unsigned num_waves,
 372                            FILE *f)
 373 {
 374         uint64_t start_addr, end_addr;
 375         unsigned i;
 376
 377         if (!shader)
 378                 return;
 379
 380         start_addr = radv_buffer_get_va(shader->bo) + shader->bo_offset;
 381         end_addr = start_addr + shader->code_size;
 382
 383         /* See if any wave executes the shader. */
 384         for (i = 0; i < num_waves; i++) {
 385                 if (start_addr <= waves[i].pc && waves[i].pc <= end_addr)
 386                         break;
 387         }
 388
 389         if (i == num_waves)
 390                 return; /* the shader is not being executed */
 391
 392         /* Remember the first found wave. The waves are sorted according to PC. */
 393         waves = &waves[i];
 394         num_waves -= i;
 395
 396         /* Get the list of instructions.
 397          * Buffer size / 4 is the upper bound of the instruction count.
 398          */
 399         unsigned num_inst = 0;
 400         struct radv_shader_inst *instructions =
 401                 calloc(shader->code_size / 4, sizeof(struct radv_shader_inst));
 402
 403         si_add_split_disasm(shader->disasm_string,
 404                             start_addr, &num_inst, instructions);
 405
 406         fprintf(f, COLOR_YELLOW "%s - annotated disassembly:" COLOR_RESET "\n",
 407                 radv_get_shader_name(shader, stage));
 408
 409         /* Print instructions with annotations. */
 410         for (i = 0; i < num_inst; i++) {
 411                 struct radv_shader_inst *inst = &instructions[i];
 412
 413                 fprintf(f, "%s\n", inst->text);
 414
 415                 /* Print which waves execute the instruction right now. */
 416                 while (num_waves && start_addr + inst->offset == waves->pc) {
 417                         fprintf(f,
 418                                 "          " COLOR_GREEN "^ SE%u SH%u CU%u "
 419                                 "SIMD%u WAVE%u  EXEC=%016"PRIx64 "  ",
 420                                 waves->se, waves->sh, waves->cu, waves->simd,
 421                                 waves->wave, waves->exec);
 422
 423                         if (inst->size == 4) {
 424                                 fprintf(f, "INST32=%08X" COLOR_RESET "\n",
 425                                         waves->inst_dw0);
 426                         } else {
 427                                 fprintf(f, "INST64=%08X %08X" COLOR_RESET "\n",
 428                                         waves->inst_dw0, waves->inst_dw1);
 429                         }
 430
 431                         waves->matched = true;
 432                         waves = &waves[1];
 433                         num_waves--;
 434                 }
 435         }
 436
 437         fprintf(f, "\n\n");
 438         free(instructions);
 439 }
 440
 441 static void
 442 radv_dump_annotated_shaders(struct radv_pipeline *pipeline,
 443                             struct radv_shader_variant *compute_shader,
 444                             FILE *f)
 445 {
 446         struct ac_wave_info waves[AC_MAX_WAVES_PER_CHIP];
 447         unsigned num_waves = ac_get_wave_info(waves);
 448         unsigned mask;
 449
 450         fprintf(f, COLOR_CYAN "The number of active waves = %u" COLOR_RESET
 451                 "\n\n", num_waves);
 452
 453         /* Dump annotated active graphics shaders. */
 454         mask = pipeline->active_stages;
 455         while (mask) {
 456                 int stage = u_bit_scan(&mask);
 457
 458                 radv_dump_annotated_shader(pipeline, pipeline->shaders[stage],
 459                                            stage, waves, num_waves, f);
 460         }
 461
 462         radv_dump_annotated_shader(pipeline, compute_shader,
 463                                    MESA_SHADER_COMPUTE, waves, num_waves, f);
 464
 465         /* Print waves executing shaders that are not currently bound. */
 466         unsigned i;
 467         bool found = false;
 468         for (i = 0; i < num_waves; i++) {
 469                 if (waves[i].matched)
 470                         continue;
 471
 472                 if (!found) {
 473                         fprintf(f, COLOR_CYAN
 474                                 "Waves not executing currently-bound shaders:"
 475                                 COLOR_RESET "\n");
 476                         found = true;
 477                 }
 478                 fprintf(f, "    SE%u SH%u CU%u SIMD%u WAVE%u  EXEC=%016"PRIx64
 479                         "  INST=%08X %08X  PC=%"PRIx64"\n",
 480                         waves[i].se, waves[i].sh, waves[i].cu, waves[i].simd,
 481                         waves[i].wave, waves[i].exec, waves[i].inst_dw0,
 482                         waves[i].inst_dw1, waves[i].pc);
 483         }
 484         if (found)
 485                 fprintf(f, "\n\n");
 486 }
 487
 488 static void
 489 radv_dump_shader(struct radv_pipeline *pipeline,
 490                  struct radv_shader_variant *shader, gl_shader_stage stage,
 491                  FILE *f)
 492 {
 493         if (!shader)
 494                 return;
 495
 496         fprintf(f, "%s:\n\n", radv_get_shader_name(shader, stage));
 497
 498         if (shader->spirv) {
 499                 fprintf(f, "SPIRV:\n");
 500                 radv_print_spirv(shader->spirv, shader->spirv_size, f);
 501         }
 502
 503         if (shader->nir) {
 504                 fprintf(f, "NIR:\n");
 505                 nir_print_shader(shader->nir, f);
 506         }
 507
 508         fprintf(f, "LLVM IR:\n%s\n", shader->llvm_ir_string);
 509         fprintf(f, "DISASM:\n%s\n", shader->disasm_string);
 510
 511         radv_shader_dump_stats(pipeline->device, shader, stage, f);
 512 }
 513
 514 static void
 515 radv_dump_shaders(struct radv_pipeline *pipeline,
 516                   struct radv_shader_variant *compute_shader, FILE *f)
 517 {
 518         unsigned mask;
 519
 520         /* Dump active graphics shaders. */
 521         mask = pipeline->active_stages;
 522         while (mask) {
 523                 int stage = u_bit_scan(&mask);
 524
 525                 radv_dump_shader(pipeline, pipeline->shaders[stage], stage, f);
 526         }
 527
 528         radv_dump_shader(pipeline, compute_shader, MESA_SHADER_COMPUTE, f);
 529 }
 530
 531 static void
 532 radv_dump_graphics_state(struct radv_pipeline *graphics_pipeline,
 533                          struct radv_pipeline *compute_pipeline, FILE *f)
 534 {
 535         struct radv_shader_variant *compute_shader =
 536                 compute_pipeline ? compute_pipeline->shaders[MESA_SHADER_COMPUTE] : NULL;
 537
 538         if (!graphics_pipeline)
 539                 return;
 540
 541         radv_dump_shaders(graphics_pipeline, compute_shader, f);
 542         radv_dump_annotated_shaders(graphics_pipeline, compute_shader, f);
 543         radv_dump_descriptors(graphics_pipeline, f);
 544 }
 545
 546 static void
 547 radv_dump_compute_state(struct radv_pipeline *compute_pipeline, FILE *f)
 548 {
 549         if (!compute_pipeline)
 550                 return;
 551
 552         radv_dump_shaders(compute_pipeline,
 553                           compute_pipeline->shaders[MESA_SHADER_COMPUTE], f);
 554         radv_dump_annotated_shaders(compute_pipeline,
 555                                     compute_pipeline->shaders[MESA_SHADER_COMPUTE],
 556                                     f);
 557         radv_dump_descriptors(compute_pipeline, f);
 558 }
 559
 560 static struct radv_pipeline *
 561 radv_get_saved_graphics_pipeline(struct radv_device *device)
 562 {
 563         uint64_t *ptr = (uint64_t *)device->trace_id_ptr;
 564
 565         return (struct radv_pipeline *)ptr[1];
 566 }
 567
 568 static struct radv_pipeline *
 569 radv_get_saved_compute_pipeline(struct radv_device *device)
 570 {
 571         uint64_t *ptr = (uint64_t *)device->trace_id_ptr;
 572
 573         return (struct radv_pipeline *)ptr[2];
 574 }
 575
 576 static void
 577 radv_dump_dmesg(FILE *f)
 578 {
 579         char line[2000];
 580         FILE *p;
 581
 582         p = popen("dmesg | tail -n60", "r");
 583         if (!p)
 584                 return;
 585
 586         fprintf(f, "\nLast 60 lines of dmesg:\n\n");
 587         while (fgets(line, sizeof(line), p))
 588                 fputs(line, f);
 589         fprintf(f, "\n");
 590
 591         pclose(p);
 592 }
 593
 594 void
 595 radv_dump_enabled_options(struct radv_device *device, FILE *f)
 596 {
 597         uint64_t mask;
 598
 599         if (device->instance->debug_flags) {
 600                 fprintf(f, "Enabled debug options: ");
 601
 602                 mask = device->instance->debug_flags;
 603                 while (mask) {
 604                         int i = u_bit_scan64(&mask);
 605                         fprintf(f, "%s, ", radv_get_debug_option_name(i));
 606                 }
 607                 fprintf(f, "\n");
 608         }
 609
 610         if (device->instance->perftest_flags) {
 611                 fprintf(f, "Enabled perftest options: ");
 612
 613                 mask = device->instance->perftest_flags;
 614                 while (mask) {
 615                         int i = u_bit_scan64(&mask);
 616                         fprintf(f, "%s, ", radv_get_perftest_option_name(i));
 617                 }
 618                 fprintf(f, "\n");
 619         }
 620 }
 621
 622 static void
 623 radv_dump_device_name(struct radv_device *device, FILE *f)
 624 {
 625         struct radeon_info *info = &device->physical_device->rad_info;
 626         char llvm_string[32] = {}, kernel_version[128] = {};
 627         struct utsname uname_data;
 628         const char *chip_name;
 629
 630         chip_name = device->ws->get_chip_name(device->ws);
 631
 632         if (uname(&uname_data) == 0)
 633                 snprintf(kernel_version, sizeof(kernel_version),
 634                          " / %s", uname_data.release);
 635
 636         if (HAVE_LLVM > 0) {
 637                 snprintf(llvm_string, sizeof(llvm_string),
 638                          ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
 639                          HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
 640         }
 641
 642         fprintf(f, "Device name: %s (%s DRM %i.%i.%i%s%s)\n\n",
 643                 chip_name, device->physical_device->name,
 644                 info->drm_major, info->drm_minor, info->drm_patchlevel,
 645                 kernel_version, llvm_string);
 646 }
 647
 648 static bool
 649 radv_gpu_hang_occured(struct radv_queue *queue, enum ring_type ring)
 650 {
 651         struct radeon_winsys *ws = queue->device->ws;
 652
 653         if (!ws->ctx_wait_idle(queue->hw_ctx, ring, queue->queue_idx))
 654                 return true;
 655
 656         return false;
 657 }
 658
 659 void
 660 radv_check_gpu_hangs(struct radv_queue *queue, struct radeon_winsys_cs *cs)
 661 {
 662         struct radv_pipeline *graphics_pipeline, *compute_pipeline;
 663         struct radv_device *device = queue->device;
 664         enum ring_type ring;
 665         uint64_t addr;
 666
 667         ring = radv_queue_family_to_ring(queue->queue_family_index);
 668
 669         bool hang_occurred = radv_gpu_hang_occured(queue, ring);
 670         bool vm_fault_occurred = false;
 671         if (queue->device->instance->debug_flags & RADV_DEBUG_VM_FAULTS)
 672                 vm_fault_occurred = ac_vm_fault_occured(device->physical_device->rad_info.chip_class,
 673                                                         &device->dmesg_timestamp, &addr);
 674         if (!hang_occurred && !vm_fault_occurred)
 675                 return;
 676
 677         graphics_pipeline = radv_get_saved_graphics_pipeline(device);
 678         compute_pipeline = radv_get_saved_compute_pipeline(device);
 679
 680         fprintf(stderr, "GPU hang report:\n\n");
 681         radv_dump_device_name(device, stderr);
 682
 683         radv_dump_enabled_options(device, stderr);
 684         radv_dump_dmesg(stderr);
 685
 686         if (vm_fault_occurred) {
 687                 fprintf(stderr, "VM fault report.\n\n");
 688                 fprintf(stderr, "Failing VM page: 0x%08"PRIx64"\n\n", addr);
 689         }
 690
 691         radv_dump_debug_registers(device, stderr);
 692
 693         switch (ring) {
 694         case RING_GFX:
 695                 radv_dump_graphics_state(graphics_pipeline, compute_pipeline,
 696                                          stderr);
 697                 break;
 698         case RING_COMPUTE:
 699                 radv_dump_compute_state(compute_pipeline, stderr);
 700                 break;
 701         default:
 702                 assert(0);
 703                 break;
 704         }
 705
 706         radv_dump_trace(queue->device, cs);
 707         abort();
 708 }
 709
 710 void
 711 radv_print_spirv(uint32_t *data, uint32_t size, FILE *fp)
 712 {
 713         char path[] = "/tmp/fileXXXXXX";
 714         char line[2048], command[128];
 715         FILE *p;
 716         int fd;
 717
 718         /* Dump the binary into a temporary file. */
 719         fd = mkstemp(path);
 720         if (fd < 0)
 721                 return;
 722
 723         if (write(fd, data, size) == -1)
 724                 goto fail;
 725
 726         sprintf(command, "spirv-dis %s", path);
 727
 728         /* Disassemble using spirv-dis if installed. */
 729         p = popen(command, "r");
 730         if (p) {
 731                 while (fgets(line, sizeof(line), p))
 732                         fprintf(fp, "%s", line);
 733                 pclose(p);
 734         }
 735
 736 fail:
 737         close(fd);
 738         unlink(path);
 739 }