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radv: add support for shader stats dump
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <dlfcn.h>
29 #include <stdbool.h>
30 #include <string.h>
31 #include <unistd.h>
32 #include <fcntl.h>
33 #include <sys/stat.h>
34 #include "radv_private.h"
35 #include "util/strtod.h"
36
37 #include <xf86drm.h>
38 #include <amdgpu.h>
39 #include <amdgpu_drm.h>
40 #include "amdgpu_id.h"
41 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
42 #include "ac_llvm_util.h"
43 #include "vk_format.h"
44 #include "sid.h"
45 #include "util/debug.h"
46 struct radv_dispatch_table dtable;
47
48 static int
49 radv_get_function_timestamp(void *ptr, uint32_t* timestamp)
50 {
51 Dl_info info;
52 struct stat st;
53 if (!dladdr(ptr, &info) || !info.dli_fname) {
54 return -1;
55 }
56 if (stat(info.dli_fname, &st)) {
57 return -1;
58 }
59 *timestamp = st.st_mtim.tv_sec;
60 return 0;
61 }
62
63 static int
64 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
65 {
66 uint32_t mesa_timestamp, llvm_timestamp;
67 uint16_t f = family;
68 memset(uuid, 0, VK_UUID_SIZE);
69 if (radv_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
70 radv_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
71 return -1;
72
73 memcpy(uuid, &mesa_timestamp, 4);
74 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
75 memcpy((char*)uuid + 8, &f, 2);
76 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
77 return 0;
78 }
79
80 static VkResult
81 radv_physical_device_init(struct radv_physical_device *device,
82 struct radv_instance *instance,
83 const char *path)
84 {
85 VkResult result;
86 drmVersionPtr version;
87 int fd;
88
89 fd = open(path, O_RDWR | O_CLOEXEC);
90 if (fd < 0)
91 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
92 "failed to open %s: %m", path);
93
94 version = drmGetVersion(fd);
95 if (!version) {
96 close(fd);
97 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
98 "failed to get version %s: %m", path);
99 }
100
101 if (strcmp(version->name, "amdgpu")) {
102 drmFreeVersion(version);
103 close(fd);
104 return VK_ERROR_INCOMPATIBLE_DRIVER;
105 }
106 drmFreeVersion(version);
107
108 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
109 device->instance = instance;
110 assert(strlen(path) < ARRAY_SIZE(device->path));
111 strncpy(device->path, path, ARRAY_SIZE(device->path));
112
113 device->ws = radv_amdgpu_winsys_create(fd);
114 if (!device->ws) {
115 result = VK_ERROR_INCOMPATIBLE_DRIVER;
116 goto fail;
117 }
118 device->ws->query_info(device->ws, &device->rad_info);
119 result = radv_init_wsi(device);
120 if (result != VK_SUCCESS) {
121 device->ws->destroy(device->ws);
122 goto fail;
123 }
124
125 if (radv_device_get_cache_uuid(device->rad_info.family, device->uuid)) {
126 radv_finish_wsi(device);
127 device->ws->destroy(device->ws);
128 goto fail;
129 }
130
131 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
132 device->name = device->rad_info.name;
133 return VK_SUCCESS;
134
135 fail:
136 close(fd);
137 return result;
138 }
139
140 static void
141 radv_physical_device_finish(struct radv_physical_device *device)
142 {
143 radv_finish_wsi(device);
144 device->ws->destroy(device->ws);
145 }
146
147 static const VkExtensionProperties global_extensions[] = {
148 {
149 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
150 .specVersion = 25,
151 },
152 #ifdef VK_USE_PLATFORM_XCB_KHR
153 {
154 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
155 .specVersion = 6,
156 },
157 #endif
158 #ifdef VK_USE_PLATFORM_XLIB_KHR
159 {
160 .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
161 .specVersion = 6,
162 },
163 #endif
164 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
165 {
166 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
167 .specVersion = 5,
168 },
169 #endif
170 };
171
172 static const VkExtensionProperties device_extensions[] = {
173 {
174 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
175 .specVersion = 68,
176 },
177 };
178
179 static void *
180 default_alloc_func(void *pUserData, size_t size, size_t align,
181 VkSystemAllocationScope allocationScope)
182 {
183 return malloc(size);
184 }
185
186 static void *
187 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
188 size_t align, VkSystemAllocationScope allocationScope)
189 {
190 return realloc(pOriginal, size);
191 }
192
193 static void
194 default_free_func(void *pUserData, void *pMemory)
195 {
196 free(pMemory);
197 }
198
199 static const VkAllocationCallbacks default_alloc = {
200 .pUserData = NULL,
201 .pfnAllocation = default_alloc_func,
202 .pfnReallocation = default_realloc_func,
203 .pfnFree = default_free_func,
204 };
205
206 VkResult radv_CreateInstance(
207 const VkInstanceCreateInfo* pCreateInfo,
208 const VkAllocationCallbacks* pAllocator,
209 VkInstance* pInstance)
210 {
211 struct radv_instance *instance;
212
213 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
214
215 uint32_t client_version;
216 if (pCreateInfo->pApplicationInfo &&
217 pCreateInfo->pApplicationInfo->apiVersion != 0) {
218 client_version = pCreateInfo->pApplicationInfo->apiVersion;
219 } else {
220 client_version = VK_MAKE_VERSION(1, 0, 0);
221 }
222
223 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
224 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
225 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
226 "Client requested version %d.%d.%d",
227 VK_VERSION_MAJOR(client_version),
228 VK_VERSION_MINOR(client_version),
229 VK_VERSION_PATCH(client_version));
230 }
231
232 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
233 bool found = false;
234 for (uint32_t j = 0; j < ARRAY_SIZE(global_extensions); j++) {
235 if (strcmp(pCreateInfo->ppEnabledExtensionNames[i],
236 global_extensions[j].extensionName) == 0) {
237 found = true;
238 break;
239 }
240 }
241 if (!found)
242 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
243 }
244
245 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
246 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
247 if (!instance)
248 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
249
250 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
251
252 if (pAllocator)
253 instance->alloc = *pAllocator;
254 else
255 instance->alloc = default_alloc;
256
257 instance->apiVersion = client_version;
258 instance->physicalDeviceCount = -1;
259
260 _mesa_locale_init();
261
262 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
263
264 *pInstance = radv_instance_to_handle(instance);
265
266 return VK_SUCCESS;
267 }
268
269 void radv_DestroyInstance(
270 VkInstance _instance,
271 const VkAllocationCallbacks* pAllocator)
272 {
273 RADV_FROM_HANDLE(radv_instance, instance, _instance);
274
275 if (instance->physicalDeviceCount > 0) {
276 /* We support at most one physical device. */
277 assert(instance->physicalDeviceCount == 1);
278 radv_physical_device_finish(&instance->physicalDevice);
279 }
280
281 VG(VALGRIND_DESTROY_MEMPOOL(instance));
282
283 _mesa_locale_fini();
284
285 vk_free(&instance->alloc, instance);
286 }
287
288 VkResult radv_EnumeratePhysicalDevices(
289 VkInstance _instance,
290 uint32_t* pPhysicalDeviceCount,
291 VkPhysicalDevice* pPhysicalDevices)
292 {
293 RADV_FROM_HANDLE(radv_instance, instance, _instance);
294 VkResult result;
295
296 if (instance->physicalDeviceCount < 0) {
297 char path[20];
298 for (unsigned i = 0; i < 8; i++) {
299 snprintf(path, sizeof(path), "/dev/dri/renderD%d", 128 + i);
300 result = radv_physical_device_init(&instance->physicalDevice,
301 instance, path);
302 if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
303 break;
304 }
305
306 if (result == VK_ERROR_INCOMPATIBLE_DRIVER) {
307 instance->physicalDeviceCount = 0;
308 } else if (result == VK_SUCCESS) {
309 instance->physicalDeviceCount = 1;
310 } else {
311 return result;
312 }
313 }
314
315 /* pPhysicalDeviceCount is an out parameter if pPhysicalDevices is NULL;
316 * otherwise it's an inout parameter.
317 *
318 * The Vulkan spec (git aaed022) says:
319 *
320 * pPhysicalDeviceCount is a pointer to an unsigned integer variable
321 * that is initialized with the number of devices the application is
322 * prepared to receive handles to. pname:pPhysicalDevices is pointer to
323 * an array of at least this many VkPhysicalDevice handles [...].
324 *
325 * Upon success, if pPhysicalDevices is NULL, vkEnumeratePhysicalDevices
326 * overwrites the contents of the variable pointed to by
327 * pPhysicalDeviceCount with the number of physical devices in in the
328 * instance; otherwise, vkEnumeratePhysicalDevices overwrites
329 * pPhysicalDeviceCount with the number of physical handles written to
330 * pPhysicalDevices.
331 */
332 if (!pPhysicalDevices) {
333 *pPhysicalDeviceCount = instance->physicalDeviceCount;
334 } else if (*pPhysicalDeviceCount >= 1) {
335 pPhysicalDevices[0] = radv_physical_device_to_handle(&instance->physicalDevice);
336 *pPhysicalDeviceCount = 1;
337 } else if (*pPhysicalDeviceCount < instance->physicalDeviceCount) {
338 return VK_INCOMPLETE;
339 } else {
340 *pPhysicalDeviceCount = 0;
341 }
342
343 return VK_SUCCESS;
344 }
345
346 void radv_GetPhysicalDeviceFeatures(
347 VkPhysicalDevice physicalDevice,
348 VkPhysicalDeviceFeatures* pFeatures)
349 {
350 // RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
351
352 memset(pFeatures, 0, sizeof(*pFeatures));
353
354 *pFeatures = (VkPhysicalDeviceFeatures) {
355 .robustBufferAccess = true,
356 .fullDrawIndexUint32 = true,
357 .imageCubeArray = true,
358 .independentBlend = true,
359 .geometryShader = false,
360 .tessellationShader = false,
361 .sampleRateShading = false,
362 .dualSrcBlend = true,
363 .logicOp = true,
364 .multiDrawIndirect = true,
365 .drawIndirectFirstInstance = true,
366 .depthClamp = true,
367 .depthBiasClamp = true,
368 .fillModeNonSolid = true,
369 .depthBounds = true,
370 .wideLines = true,
371 .largePoints = true,
372 .alphaToOne = true,
373 .multiViewport = false,
374 .samplerAnisotropy = false, /* FINISHME */
375 .textureCompressionETC2 = false,
376 .textureCompressionASTC_LDR = false,
377 .textureCompressionBC = true,
378 .occlusionQueryPrecise = true,
379 .pipelineStatisticsQuery = false,
380 .vertexPipelineStoresAndAtomics = true,
381 .fragmentStoresAndAtomics = true,
382 .shaderTessellationAndGeometryPointSize = true,
383 .shaderImageGatherExtended = false,
384 .shaderStorageImageExtendedFormats = false,
385 .shaderStorageImageMultisample = false,
386 .shaderUniformBufferArrayDynamicIndexing = true,
387 .shaderSampledImageArrayDynamicIndexing = true,
388 .shaderStorageBufferArrayDynamicIndexing = true,
389 .shaderStorageImageArrayDynamicIndexing = true,
390 .shaderStorageImageReadWithoutFormat = false,
391 .shaderStorageImageWriteWithoutFormat = true,
392 .shaderClipDistance = true,
393 .shaderCullDistance = true,
394 .shaderFloat64 = false,
395 .shaderInt64 = false,
396 .shaderInt16 = false,
397 .alphaToOne = true,
398 .variableMultisampleRate = false,
399 .inheritedQueries = false,
400 };
401 }
402
403 void radv_GetPhysicalDeviceProperties(
404 VkPhysicalDevice physicalDevice,
405 VkPhysicalDeviceProperties* pProperties)
406 {
407 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
408 VkSampleCountFlags sample_counts = 0xf;
409 VkPhysicalDeviceLimits limits = {
410 .maxImageDimension1D = (1 << 14),
411 .maxImageDimension2D = (1 << 14),
412 .maxImageDimension3D = (1 << 11),
413 .maxImageDimensionCube = (1 << 14),
414 .maxImageArrayLayers = (1 << 11),
415 .maxTexelBufferElements = 128 * 1024 * 1024,
416 .maxUniformBufferRange = UINT32_MAX,
417 .maxStorageBufferRange = UINT32_MAX,
418 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
419 .maxMemoryAllocationCount = UINT32_MAX,
420 .maxSamplerAllocationCount = 64 * 1024,
421 .bufferImageGranularity = 64, /* A cache line */
422 .sparseAddressSpaceSize = 0,
423 .maxBoundDescriptorSets = MAX_SETS,
424 .maxPerStageDescriptorSamplers = 64,
425 .maxPerStageDescriptorUniformBuffers = 64,
426 .maxPerStageDescriptorStorageBuffers = 64,
427 .maxPerStageDescriptorSampledImages = 64,
428 .maxPerStageDescriptorStorageImages = 64,
429 .maxPerStageDescriptorInputAttachments = 64,
430 .maxPerStageResources = 128,
431 .maxDescriptorSetSamplers = 256,
432 .maxDescriptorSetUniformBuffers = 256,
433 .maxDescriptorSetUniformBuffersDynamic = 256,
434 .maxDescriptorSetStorageBuffers = 256,
435 .maxDescriptorSetStorageBuffersDynamic = 256,
436 .maxDescriptorSetSampledImages = 256,
437 .maxDescriptorSetStorageImages = 256,
438 .maxDescriptorSetInputAttachments = 256,
439 .maxVertexInputAttributes = 32,
440 .maxVertexInputBindings = 32,
441 .maxVertexInputAttributeOffset = 2047,
442 .maxVertexInputBindingStride = 2048,
443 .maxVertexOutputComponents = 128,
444 .maxTessellationGenerationLevel = 0,
445 .maxTessellationPatchSize = 0,
446 .maxTessellationControlPerVertexInputComponents = 0,
447 .maxTessellationControlPerVertexOutputComponents = 0,
448 .maxTessellationControlPerPatchOutputComponents = 0,
449 .maxTessellationControlTotalOutputComponents = 0,
450 .maxTessellationEvaluationInputComponents = 0,
451 .maxTessellationEvaluationOutputComponents = 0,
452 .maxGeometryShaderInvocations = 32,
453 .maxGeometryInputComponents = 64,
454 .maxGeometryOutputComponents = 128,
455 .maxGeometryOutputVertices = 256,
456 .maxGeometryTotalOutputComponents = 1024,
457 .maxFragmentInputComponents = 128,
458 .maxFragmentOutputAttachments = 8,
459 .maxFragmentDualSrcAttachments = 2,
460 .maxFragmentCombinedOutputResources = 8,
461 .maxComputeSharedMemorySize = 32768,
462 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
463 .maxComputeWorkGroupInvocations = 16 * 1024,
464 .maxComputeWorkGroupSize = {
465 16 * 1024/*devinfo->max_cs_threads*/,
466 16 * 1024,
467 16 * 1024
468 },
469 .subPixelPrecisionBits = 4 /* FIXME */,
470 .subTexelPrecisionBits = 4 /* FIXME */,
471 .mipmapPrecisionBits = 4 /* FIXME */,
472 .maxDrawIndexedIndexValue = UINT32_MAX,
473 .maxDrawIndirectCount = UINT32_MAX,
474 .maxSamplerLodBias = 16,
475 .maxSamplerAnisotropy = 16,
476 .maxViewports = MAX_VIEWPORTS,
477 .maxViewportDimensions = { (1 << 14), (1 << 14) },
478 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
479 .viewportSubPixelBits = 13, /* We take a float? */
480 .minMemoryMapAlignment = 4096, /* A page */
481 .minTexelBufferOffsetAlignment = 1,
482 .minUniformBufferOffsetAlignment = 4,
483 .minStorageBufferOffsetAlignment = 4,
484 .minTexelOffset = -8,
485 .maxTexelOffset = 7,
486 .minTexelGatherOffset = -8,
487 .maxTexelGatherOffset = 7,
488 .minInterpolationOffset = 0, /* FIXME */
489 .maxInterpolationOffset = 0, /* FIXME */
490 .subPixelInterpolationOffsetBits = 0, /* FIXME */
491 .maxFramebufferWidth = (1 << 14),
492 .maxFramebufferHeight = (1 << 14),
493 .maxFramebufferLayers = (1 << 10),
494 .framebufferColorSampleCounts = sample_counts,
495 .framebufferDepthSampleCounts = sample_counts,
496 .framebufferStencilSampleCounts = sample_counts,
497 .framebufferNoAttachmentsSampleCounts = sample_counts,
498 .maxColorAttachments = MAX_RTS,
499 .sampledImageColorSampleCounts = sample_counts,
500 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
501 .sampledImageDepthSampleCounts = sample_counts,
502 .sampledImageStencilSampleCounts = sample_counts,
503 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
504 .maxSampleMaskWords = 1,
505 .timestampComputeAndGraphics = false,
506 .timestampPeriod = 100000.0 / pdevice->rad_info.clock_crystal_freq,
507 .maxClipDistances = 8,
508 .maxCullDistances = 8,
509 .maxCombinedClipAndCullDistances = 8,
510 .discreteQueuePriorities = 1,
511 .pointSizeRange = { 0.125, 255.875 },
512 .lineWidthRange = { 0.0, 7.9921875 },
513 .pointSizeGranularity = (1.0 / 8.0),
514 .lineWidthGranularity = (1.0 / 128.0),
515 .strictLines = false, /* FINISHME */
516 .standardSampleLocations = true,
517 .optimalBufferCopyOffsetAlignment = 128,
518 .optimalBufferCopyRowPitchAlignment = 128,
519 .nonCoherentAtomSize = 64,
520 };
521
522 *pProperties = (VkPhysicalDeviceProperties) {
523 .apiVersion = VK_MAKE_VERSION(1, 0, 5),
524 .driverVersion = 1,
525 .vendorID = 0x1002,
526 .deviceID = pdevice->rad_info.pci_id,
527 .deviceType = VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU,
528 .limits = limits,
529 .sparseProperties = {0}, /* Broadwell doesn't do sparse. */
530 };
531
532 strcpy(pProperties->deviceName, pdevice->name);
533 memcpy(pProperties->pipelineCacheUUID, pdevice->uuid, VK_UUID_SIZE);
534 }
535
536 void radv_GetPhysicalDeviceQueueFamilyProperties(
537 VkPhysicalDevice physicalDevice,
538 uint32_t* pCount,
539 VkQueueFamilyProperties* pQueueFamilyProperties)
540 {
541 if (pQueueFamilyProperties == NULL) {
542 *pCount = 1;
543 return;
544 }
545 assert(*pCount >= 1);
546
547 *pQueueFamilyProperties = (VkQueueFamilyProperties) {
548 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
549 VK_QUEUE_COMPUTE_BIT |
550 VK_QUEUE_TRANSFER_BIT,
551 .queueCount = 1,
552 .timestampValidBits = 64,
553 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
554 };
555 }
556
557 void radv_GetPhysicalDeviceMemoryProperties(
558 VkPhysicalDevice physicalDevice,
559 VkPhysicalDeviceMemoryProperties* pMemoryProperties)
560 {
561 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
562
563 pMemoryProperties->memoryTypeCount = 4;
564 pMemoryProperties->memoryTypes[0] = (VkMemoryType) {
565 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
566 .heapIndex = 0,
567 };
568 pMemoryProperties->memoryTypes[1] = (VkMemoryType) {
569 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
570 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
571 .heapIndex = 2,
572 };
573 pMemoryProperties->memoryTypes[2] = (VkMemoryType) {
574 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
575 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
576 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
577 .heapIndex = 1,
578 };
579 pMemoryProperties->memoryTypes[3] = (VkMemoryType) {
580 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
581 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
582 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
583 .heapIndex = 2,
584 };
585
586 pMemoryProperties->memoryHeapCount = 3;
587 pMemoryProperties->memoryHeaps[0] = (VkMemoryHeap) {
588 .size = physical_device->rad_info.vram_size -
589 physical_device->rad_info.visible_vram_size,
590 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
591 };
592 pMemoryProperties->memoryHeaps[1] = (VkMemoryHeap) {
593 .size = physical_device->rad_info.visible_vram_size,
594 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
595 };
596 pMemoryProperties->memoryHeaps[2] = (VkMemoryHeap) {
597 .size = physical_device->rad_info.gart_size,
598 .flags = 0,
599 };
600 }
601
602 static VkResult
603 radv_queue_init(struct radv_device *device, struct radv_queue *queue)
604 {
605 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
606 queue->device = device;
607
608 return VK_SUCCESS;
609 }
610
611 static void
612 radv_queue_finish(struct radv_queue *queue)
613 {
614 }
615
616 VkResult radv_CreateDevice(
617 VkPhysicalDevice physicalDevice,
618 const VkDeviceCreateInfo* pCreateInfo,
619 const VkAllocationCallbacks* pAllocator,
620 VkDevice* pDevice)
621 {
622 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
623 VkResult result;
624 struct radv_device *device;
625
626 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
627 bool found = false;
628 for (uint32_t j = 0; j < ARRAY_SIZE(device_extensions); j++) {
629 if (strcmp(pCreateInfo->ppEnabledExtensionNames[i],
630 device_extensions[j].extensionName) == 0) {
631 found = true;
632 break;
633 }
634 }
635 if (!found)
636 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
637 }
638
639 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
640 sizeof(*device), 8,
641 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
642 if (!device)
643 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
644
645 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
646 device->instance = physical_device->instance;
647
648 device->ws = physical_device->ws;
649 if (pAllocator)
650 device->alloc = *pAllocator;
651 else
652 device->alloc = physical_device->instance->alloc;
653
654 device->hw_ctx = device->ws->ctx_create(device->ws);
655 if (!device->hw_ctx) {
656 result = VK_ERROR_OUT_OF_HOST_MEMORY;
657 goto fail_free;
658 }
659
660 radv_queue_init(device, &device->queue);
661
662 result = radv_device_init_meta(device);
663 if (result != VK_SUCCESS) {
664 device->ws->ctx_destroy(device->hw_ctx);
665 goto fail_free;
666 }
667 device->allow_fast_clears = env_var_as_boolean("RADV_FAST_CLEARS", false);
668 device->allow_dcc = !env_var_as_boolean("RADV_DCC_DISABLE", false);
669 device->shader_stats_dump = env_var_as_boolean("RADV_SHADER_STATS", false);
670
671 if (device->allow_fast_clears && device->allow_dcc)
672 radv_finishme("DCC fast clears have not been tested\n");
673
674 radv_device_init_msaa(device);
675 device->empty_cs = device->ws->cs_create(device->ws, RING_GFX);
676 radeon_emit(device->empty_cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
677 radeon_emit(device->empty_cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
678 radeon_emit(device->empty_cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
679 device->ws->cs_finalize(device->empty_cs);
680 *pDevice = radv_device_to_handle(device);
681 return VK_SUCCESS;
682 fail_free:
683 vk_free(&device->alloc, device);
684 return result;
685 }
686
687 void radv_DestroyDevice(
688 VkDevice _device,
689 const VkAllocationCallbacks* pAllocator)
690 {
691 RADV_FROM_HANDLE(radv_device, device, _device);
692
693 device->ws->ctx_destroy(device->hw_ctx);
694 radv_queue_finish(&device->queue);
695 radv_device_finish_meta(device);
696
697 vk_free(&device->alloc, device);
698 }
699
700 VkResult radv_EnumerateInstanceExtensionProperties(
701 const char* pLayerName,
702 uint32_t* pPropertyCount,
703 VkExtensionProperties* pProperties)
704 {
705 unsigned i;
706 if (pProperties == NULL) {
707 *pPropertyCount = ARRAY_SIZE(global_extensions);
708 return VK_SUCCESS;
709 }
710
711 for (i = 0; i < *pPropertyCount; i++)
712 memcpy(&pProperties[i], &global_extensions[i], sizeof(VkExtensionProperties));
713
714 *pPropertyCount = i;
715 if (i < ARRAY_SIZE(global_extensions))
716 return VK_INCOMPLETE;
717
718 return VK_SUCCESS;
719 }
720
721 VkResult radv_EnumerateDeviceExtensionProperties(
722 VkPhysicalDevice physicalDevice,
723 const char* pLayerName,
724 uint32_t* pPropertyCount,
725 VkExtensionProperties* pProperties)
726 {
727 unsigned i;
728
729 if (pProperties == NULL) {
730 *pPropertyCount = ARRAY_SIZE(device_extensions);
731 return VK_SUCCESS;
732 }
733
734 for (i = 0; i < *pPropertyCount; i++)
735 memcpy(&pProperties[i], &device_extensions[i], sizeof(VkExtensionProperties));
736
737 *pPropertyCount = i;
738 if (i < ARRAY_SIZE(device_extensions))
739 return VK_INCOMPLETE;
740 return VK_SUCCESS;
741 }
742
743 VkResult radv_EnumerateInstanceLayerProperties(
744 uint32_t* pPropertyCount,
745 VkLayerProperties* pProperties)
746 {
747 if (pProperties == NULL) {
748 *pPropertyCount = 0;
749 return VK_SUCCESS;
750 }
751
752 /* None supported at this time */
753 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
754 }
755
756 VkResult radv_EnumerateDeviceLayerProperties(
757 VkPhysicalDevice physicalDevice,
758 uint32_t* pPropertyCount,
759 VkLayerProperties* pProperties)
760 {
761 if (pProperties == NULL) {
762 *pPropertyCount = 0;
763 return VK_SUCCESS;
764 }
765
766 /* None supported at this time */
767 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
768 }
769
770 void radv_GetDeviceQueue(
771 VkDevice _device,
772 uint32_t queueNodeIndex,
773 uint32_t queueIndex,
774 VkQueue* pQueue)
775 {
776 RADV_FROM_HANDLE(radv_device, device, _device);
777
778 assert(queueIndex == 0);
779
780 *pQueue = radv_queue_to_handle(&device->queue);
781 }
782
783 VkResult radv_QueueSubmit(
784 VkQueue _queue,
785 uint32_t submitCount,
786 const VkSubmitInfo* pSubmits,
787 VkFence _fence)
788 {
789 RADV_FROM_HANDLE(radv_queue, queue, _queue);
790 RADV_FROM_HANDLE(radv_fence, fence, _fence);
791 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
792 struct radeon_winsys_ctx *ctx = queue->device->hw_ctx;
793 int ret;
794
795 for (uint32_t i = 0; i < submitCount; i++) {
796 struct radeon_winsys_cs **cs_array;
797 bool can_patch = true;
798
799 if (!pSubmits[i].commandBufferCount)
800 continue;
801
802 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
803 pSubmits[i].commandBufferCount);
804
805 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
806 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
807 pSubmits[i].pCommandBuffers[j]);
808 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
809
810 cs_array[j] = cmd_buffer->cs;
811 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
812 can_patch = false;
813 }
814 ret = queue->device->ws->cs_submit(ctx, cs_array,
815 pSubmits[i].commandBufferCount,
816 can_patch, base_fence);
817 if (ret)
818 radv_loge("failed to submit CS %d\n", i);
819 free(cs_array);
820 }
821
822 if (fence) {
823 if (!submitCount)
824 ret = queue->device->ws->cs_submit(ctx, &queue->device->empty_cs,
825 1, false, base_fence);
826
827 fence->submitted = true;
828 }
829
830 return VK_SUCCESS;
831 }
832
833 VkResult radv_QueueWaitIdle(
834 VkQueue _queue)
835 {
836 RADV_FROM_HANDLE(radv_queue, queue, _queue);
837
838 queue->device->ws->ctx_wait_idle(queue->device->hw_ctx);
839 return VK_SUCCESS;
840 }
841
842 VkResult radv_DeviceWaitIdle(
843 VkDevice _device)
844 {
845 RADV_FROM_HANDLE(radv_device, device, _device);
846
847 device->ws->ctx_wait_idle(device->hw_ctx);
848 return VK_SUCCESS;
849 }
850
851 PFN_vkVoidFunction radv_GetInstanceProcAddr(
852 VkInstance instance,
853 const char* pName)
854 {
855 return radv_lookup_entrypoint(pName);
856 }
857
858 /* The loader wants us to expose a second GetInstanceProcAddr function
859 * to work around certain LD_PRELOAD issues seen in apps.
860 */
861 PUBLIC
862 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
863 VkInstance instance,
864 const char* pName);
865
866 PUBLIC
867 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
868 VkInstance instance,
869 const char* pName)
870 {
871 return radv_GetInstanceProcAddr(instance, pName);
872 }
873
874 PFN_vkVoidFunction radv_GetDeviceProcAddr(
875 VkDevice device,
876 const char* pName)
877 {
878 return radv_lookup_entrypoint(pName);
879 }
880
881 VkResult radv_AllocateMemory(
882 VkDevice _device,
883 const VkMemoryAllocateInfo* pAllocateInfo,
884 const VkAllocationCallbacks* pAllocator,
885 VkDeviceMemory* pMem)
886 {
887 RADV_FROM_HANDLE(radv_device, device, _device);
888 struct radv_device_memory *mem;
889 VkResult result;
890 enum radeon_bo_domain domain;
891 uint32_t flags = 0;
892 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
893
894 if (pAllocateInfo->allocationSize == 0) {
895 /* Apparently, this is allowed */
896 *pMem = VK_NULL_HANDLE;
897 return VK_SUCCESS;
898 }
899
900 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
901 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
902 if (mem == NULL)
903 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
904
905 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
906 if (pAllocateInfo->memoryTypeIndex == 1 || pAllocateInfo->memoryTypeIndex == 3)
907 domain = RADEON_DOMAIN_GTT;
908 else
909 domain = RADEON_DOMAIN_VRAM;
910
911 if (pAllocateInfo->memoryTypeIndex == 0)
912 flags |= RADEON_FLAG_NO_CPU_ACCESS;
913 else
914 flags |= RADEON_FLAG_CPU_ACCESS;
915
916 if (pAllocateInfo->memoryTypeIndex == 1)
917 flags |= RADEON_FLAG_GTT_WC;
918
919 mem->bo = device->ws->buffer_create(device->ws, alloc_size, 32768,
920 domain, flags);
921
922 if (!mem->bo) {
923 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
924 goto fail;
925 }
926 mem->type_index = pAllocateInfo->memoryTypeIndex;
927
928 *pMem = radv_device_memory_to_handle(mem);
929
930 return VK_SUCCESS;
931
932 fail:
933 vk_free2(&device->alloc, pAllocator, mem);
934
935 return result;
936 }
937
938 void radv_FreeMemory(
939 VkDevice _device,
940 VkDeviceMemory _mem,
941 const VkAllocationCallbacks* pAllocator)
942 {
943 RADV_FROM_HANDLE(radv_device, device, _device);
944 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
945
946 if (mem == NULL)
947 return;
948
949 device->ws->buffer_destroy(mem->bo);
950 mem->bo = NULL;
951
952 vk_free2(&device->alloc, pAllocator, mem);
953 }
954
955 VkResult radv_MapMemory(
956 VkDevice _device,
957 VkDeviceMemory _memory,
958 VkDeviceSize offset,
959 VkDeviceSize size,
960 VkMemoryMapFlags flags,
961 void** ppData)
962 {
963 RADV_FROM_HANDLE(radv_device, device, _device);
964 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
965
966 if (mem == NULL) {
967 *ppData = NULL;
968 return VK_SUCCESS;
969 }
970
971 *ppData = device->ws->buffer_map(mem->bo);
972 if (*ppData) {
973 *ppData += offset;
974 return VK_SUCCESS;
975 }
976
977 return VK_ERROR_MEMORY_MAP_FAILED;
978 }
979
980 void radv_UnmapMemory(
981 VkDevice _device,
982 VkDeviceMemory _memory)
983 {
984 RADV_FROM_HANDLE(radv_device, device, _device);
985 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
986
987 if (mem == NULL)
988 return;
989
990 device->ws->buffer_unmap(mem->bo);
991 }
992
993 VkResult radv_FlushMappedMemoryRanges(
994 VkDevice _device,
995 uint32_t memoryRangeCount,
996 const VkMappedMemoryRange* pMemoryRanges)
997 {
998 return VK_SUCCESS;
999 }
1000
1001 VkResult radv_InvalidateMappedMemoryRanges(
1002 VkDevice _device,
1003 uint32_t memoryRangeCount,
1004 const VkMappedMemoryRange* pMemoryRanges)
1005 {
1006 return VK_SUCCESS;
1007 }
1008
1009 void radv_GetBufferMemoryRequirements(
1010 VkDevice device,
1011 VkBuffer _buffer,
1012 VkMemoryRequirements* pMemoryRequirements)
1013 {
1014 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1015
1016 /* The Vulkan spec (git aaed022) says:
1017 *
1018 * memoryTypeBits is a bitfield and contains one bit set for every
1019 * supported memory type for the resource. The bit `1<<i` is set if and
1020 * only if the memory type `i` in the VkPhysicalDeviceMemoryProperties
1021 * structure for the physical device is supported.
1022 *
1023 * We support exactly one memory type.
1024 */
1025 pMemoryRequirements->memoryTypeBits = 0x7;
1026
1027 pMemoryRequirements->size = buffer->size;
1028 pMemoryRequirements->alignment = 16;
1029 }
1030
1031 void radv_GetImageMemoryRequirements(
1032 VkDevice device,
1033 VkImage _image,
1034 VkMemoryRequirements* pMemoryRequirements)
1035 {
1036 RADV_FROM_HANDLE(radv_image, image, _image);
1037
1038 /* The Vulkan spec (git aaed022) says:
1039 *
1040 * memoryTypeBits is a bitfield and contains one bit set for every
1041 * supported memory type for the resource. The bit `1<<i` is set if and
1042 * only if the memory type `i` in the VkPhysicalDeviceMemoryProperties
1043 * structure for the physical device is supported.
1044 *
1045 * We support exactly one memory type.
1046 */
1047 pMemoryRequirements->memoryTypeBits = 0x7;
1048
1049 pMemoryRequirements->size = image->size;
1050 pMemoryRequirements->alignment = image->alignment;
1051 }
1052
1053 void radv_GetImageSparseMemoryRequirements(
1054 VkDevice device,
1055 VkImage image,
1056 uint32_t* pSparseMemoryRequirementCount,
1057 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
1058 {
1059 stub();
1060 }
1061
1062 void radv_GetDeviceMemoryCommitment(
1063 VkDevice device,
1064 VkDeviceMemory memory,
1065 VkDeviceSize* pCommittedMemoryInBytes)
1066 {
1067 *pCommittedMemoryInBytes = 0;
1068 }
1069
1070 VkResult radv_BindBufferMemory(
1071 VkDevice device,
1072 VkBuffer _buffer,
1073 VkDeviceMemory _memory,
1074 VkDeviceSize memoryOffset)
1075 {
1076 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1077 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1078
1079 if (mem) {
1080 buffer->bo = mem->bo;
1081 buffer->offset = memoryOffset;
1082 } else {
1083 buffer->bo = NULL;
1084 buffer->offset = 0;
1085 }
1086
1087 return VK_SUCCESS;
1088 }
1089
1090 VkResult radv_BindImageMemory(
1091 VkDevice device,
1092 VkImage _image,
1093 VkDeviceMemory _memory,
1094 VkDeviceSize memoryOffset)
1095 {
1096 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1097 RADV_FROM_HANDLE(radv_image, image, _image);
1098
1099 if (mem) {
1100 image->bo = mem->bo;
1101 image->offset = memoryOffset;
1102 } else {
1103 image->bo = NULL;
1104 image->offset = 0;
1105 }
1106
1107 return VK_SUCCESS;
1108 }
1109
1110 VkResult radv_QueueBindSparse(
1111 VkQueue queue,
1112 uint32_t bindInfoCount,
1113 const VkBindSparseInfo* pBindInfo,
1114 VkFence fence)
1115 {
1116 stub_return(VK_ERROR_INCOMPATIBLE_DRIVER);
1117 }
1118
1119 VkResult radv_CreateFence(
1120 VkDevice _device,
1121 const VkFenceCreateInfo* pCreateInfo,
1122 const VkAllocationCallbacks* pAllocator,
1123 VkFence* pFence)
1124 {
1125 RADV_FROM_HANDLE(radv_device, device, _device);
1126 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
1127 sizeof(*fence), 8,
1128 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1129
1130 if (!fence)
1131 return VK_ERROR_OUT_OF_HOST_MEMORY;
1132
1133 memset(fence, 0, sizeof(*fence));
1134 fence->submitted = false;
1135 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
1136 fence->fence = device->ws->create_fence();
1137
1138
1139 *pFence = radv_fence_to_handle(fence);
1140
1141 return VK_SUCCESS;
1142 }
1143
1144 void radv_DestroyFence(
1145 VkDevice _device,
1146 VkFence _fence,
1147 const VkAllocationCallbacks* pAllocator)
1148 {
1149 RADV_FROM_HANDLE(radv_device, device, _device);
1150 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1151
1152 if (!fence)
1153 return;
1154 device->ws->destroy_fence(fence->fence);
1155 vk_free2(&device->alloc, pAllocator, fence);
1156 }
1157
1158 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
1159 {
1160 uint64_t current_time;
1161 struct timespec tv;
1162
1163 clock_gettime(CLOCK_MONOTONIC, &tv);
1164 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
1165
1166 timeout = MIN2(UINT64_MAX - current_time, timeout);
1167
1168 return current_time + timeout;
1169 }
1170
1171 VkResult radv_WaitForFences(
1172 VkDevice _device,
1173 uint32_t fenceCount,
1174 const VkFence* pFences,
1175 VkBool32 waitAll,
1176 uint64_t timeout)
1177 {
1178 RADV_FROM_HANDLE(radv_device, device, _device);
1179 timeout = radv_get_absolute_timeout(timeout);
1180
1181 if (!waitAll && fenceCount > 1) {
1182 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
1183 }
1184
1185 for (uint32_t i = 0; i < fenceCount; ++i) {
1186 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1187 bool expired = false;
1188
1189 if (fence->signalled)
1190 continue;
1191
1192 if (!fence->submitted)
1193 return VK_TIMEOUT;
1194
1195 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
1196 if (!expired)
1197 return VK_TIMEOUT;
1198
1199 fence->signalled = true;
1200 }
1201
1202 return VK_SUCCESS;
1203 }
1204
1205 VkResult radv_ResetFences(VkDevice device,
1206 uint32_t fenceCount,
1207 const VkFence *pFences)
1208 {
1209 for (unsigned i = 0; i < fenceCount; ++i) {
1210 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1211 fence->submitted = fence->signalled = false;
1212 }
1213
1214 return VK_SUCCESS;
1215 }
1216
1217 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
1218 {
1219 RADV_FROM_HANDLE(radv_device, device, _device);
1220 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1221
1222 if (fence->signalled)
1223 return VK_SUCCESS;
1224 if (!fence->submitted)
1225 return VK_NOT_READY;
1226
1227 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
1228 return VK_NOT_READY;
1229
1230 return VK_SUCCESS;
1231 }
1232
1233
1234 // Queue semaphore functions
1235
1236 VkResult radv_CreateSemaphore(
1237 VkDevice device,
1238 const VkSemaphoreCreateInfo* pCreateInfo,
1239 const VkAllocationCallbacks* pAllocator,
1240 VkSemaphore* pSemaphore)
1241 {
1242 /* The DRM execbuffer ioctl always execute in-oder, even between different
1243 * rings. As such, there's nothing to do for the user space semaphore.
1244 */
1245
1246 *pSemaphore = (VkSemaphore)1;
1247
1248 return VK_SUCCESS;
1249 }
1250
1251 void radv_DestroySemaphore(
1252 VkDevice device,
1253 VkSemaphore semaphore,
1254 const VkAllocationCallbacks* pAllocator)
1255 {
1256 }
1257
1258 VkResult radv_CreateEvent(
1259 VkDevice _device,
1260 const VkEventCreateInfo* pCreateInfo,
1261 const VkAllocationCallbacks* pAllocator,
1262 VkEvent* pEvent)
1263 {
1264 RADV_FROM_HANDLE(radv_device, device, _device);
1265 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
1266 sizeof(*event), 8,
1267 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1268
1269 if (!event)
1270 return VK_ERROR_OUT_OF_HOST_MEMORY;
1271
1272 event->bo = device->ws->buffer_create(device->ws, 8, 8,
1273 RADEON_DOMAIN_GTT,
1274 RADEON_FLAG_CPU_ACCESS);
1275 if (!event->bo) {
1276 vk_free2(&device->alloc, pAllocator, event);
1277 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1278 }
1279
1280 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
1281
1282 *pEvent = radv_event_to_handle(event);
1283
1284 return VK_SUCCESS;
1285 }
1286
1287 void radv_DestroyEvent(
1288 VkDevice _device,
1289 VkEvent _event,
1290 const VkAllocationCallbacks* pAllocator)
1291 {
1292 RADV_FROM_HANDLE(radv_device, device, _device);
1293 RADV_FROM_HANDLE(radv_event, event, _event);
1294
1295 if (!event)
1296 return;
1297 device->ws->buffer_destroy(event->bo);
1298 vk_free2(&device->alloc, pAllocator, event);
1299 }
1300
1301 VkResult radv_GetEventStatus(
1302 VkDevice _device,
1303 VkEvent _event)
1304 {
1305 RADV_FROM_HANDLE(radv_event, event, _event);
1306
1307 if (*event->map == 1)
1308 return VK_EVENT_SET;
1309 return VK_EVENT_RESET;
1310 }
1311
1312 VkResult radv_SetEvent(
1313 VkDevice _device,
1314 VkEvent _event)
1315 {
1316 RADV_FROM_HANDLE(radv_event, event, _event);
1317 *event->map = 1;
1318
1319 return VK_SUCCESS;
1320 }
1321
1322 VkResult radv_ResetEvent(
1323 VkDevice _device,
1324 VkEvent _event)
1325 {
1326 RADV_FROM_HANDLE(radv_event, event, _event);
1327 *event->map = 0;
1328
1329 return VK_SUCCESS;
1330 }
1331
1332 VkResult radv_CreateBuffer(
1333 VkDevice _device,
1334 const VkBufferCreateInfo* pCreateInfo,
1335 const VkAllocationCallbacks* pAllocator,
1336 VkBuffer* pBuffer)
1337 {
1338 RADV_FROM_HANDLE(radv_device, device, _device);
1339 struct radv_buffer *buffer;
1340
1341 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
1342
1343 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
1344 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1345 if (buffer == NULL)
1346 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1347
1348 buffer->size = pCreateInfo->size;
1349 buffer->usage = pCreateInfo->usage;
1350 buffer->bo = NULL;
1351 buffer->offset = 0;
1352
1353 *pBuffer = radv_buffer_to_handle(buffer);
1354
1355 return VK_SUCCESS;
1356 }
1357
1358 void radv_DestroyBuffer(
1359 VkDevice _device,
1360 VkBuffer _buffer,
1361 const VkAllocationCallbacks* pAllocator)
1362 {
1363 RADV_FROM_HANDLE(radv_device, device, _device);
1364 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1365
1366 if (!buffer)
1367 return;
1368
1369 vk_free2(&device->alloc, pAllocator, buffer);
1370 }
1371
1372 static inline unsigned
1373 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
1374 {
1375 if (stencil)
1376 return image->surface.stencil_tiling_index[level];
1377 else
1378 return image->surface.tiling_index[level];
1379 }
1380
1381 static void
1382 radv_initialise_color_surface(struct radv_device *device,
1383 struct radv_color_buffer_info *cb,
1384 struct radv_image_view *iview)
1385 {
1386 const struct vk_format_description *desc;
1387 unsigned ntype, format, swap, endian;
1388 unsigned blend_clamp = 0, blend_bypass = 0;
1389 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
1390 uint64_t va;
1391 const struct radeon_surf *surf = &iview->image->surface;
1392 const struct radeon_surf_level *level_info = &surf->level[iview->base_mip];
1393
1394 desc = vk_format_description(iview->vk_format);
1395
1396 memset(cb, 0, sizeof(*cb));
1397
1398 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1399 va += level_info->offset;
1400 cb->cb_color_base = va >> 8;
1401
1402 /* CMASK variables */
1403 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1404 va += iview->image->cmask.offset;
1405 cb->cb_color_cmask = va >> 8;
1406 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
1407
1408 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1409 va += iview->image->dcc_offset;
1410 cb->cb_dcc_base = va >> 8;
1411
1412 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
1413 S_028C6C_SLICE_MAX(iview->base_layer + iview->extent.depth - 1);
1414
1415 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
1416 pitch_tile_max = level_info->nblk_x / 8 - 1;
1417 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
1418 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
1419
1420 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
1421 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
1422
1423 /* Intensity is implemented as Red, so treat it that way. */
1424 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1) |
1425 S_028C74_TILE_MODE_INDEX(tile_mode_index);
1426
1427 if (iview->image->samples > 1) {
1428 unsigned log_samples = util_logbase2(iview->image->samples);
1429
1430 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1431 S_028C74_NUM_FRAGMENTS(log_samples);
1432 }
1433
1434 if (iview->image->fmask.size) {
1435 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
1436 if (device->instance->physicalDevice.rad_info.chip_class >= CIK)
1437 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
1438 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
1439 cb->cb_color_fmask = va >> 8;
1440 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
1441 } else {
1442 /* This must be set for fast clear to work without FMASK. */
1443 if (device->instance->physicalDevice.rad_info.chip_class >= CIK)
1444 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
1445 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
1446 cb->cb_color_fmask = cb->cb_color_base;
1447 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
1448 }
1449
1450 ntype = radv_translate_color_numformat(iview->vk_format,
1451 desc,
1452 vk_format_get_first_non_void_channel(iview->vk_format));
1453 format = radv_translate_colorformat(iview->vk_format);
1454 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
1455 radv_finishme("Illegal color\n");
1456 swap = radv_translate_colorswap(iview->vk_format, FALSE);
1457 endian = radv_colorformat_endian_swap(format);
1458
1459 /* blend clamp should be set for all NORM/SRGB types */
1460 if (ntype == V_028C70_NUMBER_UNORM ||
1461 ntype == V_028C70_NUMBER_SNORM ||
1462 ntype == V_028C70_NUMBER_SRGB)
1463 blend_clamp = 1;
1464
1465 /* set blend bypass according to docs if SINT/UINT or
1466 8/24 COLOR variants */
1467 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1468 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1469 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1470 blend_clamp = 0;
1471 blend_bypass = 1;
1472 }
1473 #if 0
1474 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
1475 (format == V_028C70_COLOR_8 ||
1476 format == V_028C70_COLOR_8_8 ||
1477 format == V_028C70_COLOR_8_8_8_8))
1478 ->color_is_int8 = true;
1479 #endif
1480 cb->cb_color_info = S_028C70_FORMAT(format) |
1481 S_028C70_COMP_SWAP(swap) |
1482 S_028C70_BLEND_CLAMP(blend_clamp) |
1483 S_028C70_BLEND_BYPASS(blend_bypass) |
1484 S_028C70_SIMPLE_FLOAT(1) |
1485 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
1486 ntype != V_028C70_NUMBER_SNORM &&
1487 ntype != V_028C70_NUMBER_SRGB &&
1488 format != V_028C70_COLOR_8_24 &&
1489 format != V_028C70_COLOR_24_8) |
1490 S_028C70_NUMBER_TYPE(ntype) |
1491 S_028C70_ENDIAN(endian);
1492 if (iview->image->samples > 1)
1493 if (iview->image->fmask.size)
1494 cb->cb_color_info |= S_028C70_COMPRESSION(1);
1495
1496 if (iview->image->cmask.size && device->allow_fast_clears)
1497 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
1498
1499 if (iview->image->surface.dcc_size && level_info->dcc_enabled)
1500 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
1501
1502 if (device->instance->physicalDevice.rad_info.chip_class >= VI) {
1503 unsigned max_uncompressed_block_size = 2;
1504 if (iview->image->samples > 1) {
1505 if (iview->image->surface.bpe == 1)
1506 max_uncompressed_block_size = 0;
1507 else if (iview->image->surface.bpe == 2)
1508 max_uncompressed_block_size = 1;
1509 }
1510
1511 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
1512 S_028C78_INDEPENDENT_64B_BLOCKS(1);
1513 }
1514
1515 /* This must be set for fast clear to work without FMASK. */
1516 if (!iview->image->fmask.size &&
1517 device->instance->physicalDevice.rad_info.chip_class == SI) {
1518 unsigned bankh = util_logbase2(iview->image->surface.bankh);
1519 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
1520 }
1521 }
1522
1523 static void
1524 radv_initialise_ds_surface(struct radv_device *device,
1525 struct radv_ds_buffer_info *ds,
1526 struct radv_image_view *iview)
1527 {
1528 unsigned level = iview->base_mip;
1529 unsigned format;
1530 uint64_t va, s_offs, z_offs;
1531 const struct radeon_surf_level *level_info = &iview->image->surface.level[level];
1532 memset(ds, 0, sizeof(*ds));
1533 switch (iview->vk_format) {
1534 case VK_FORMAT_D24_UNORM_S8_UINT:
1535 case VK_FORMAT_X8_D24_UNORM_PACK32:
1536 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1537 ds->offset_scale = 2.0f;
1538 break;
1539 case VK_FORMAT_D16_UNORM:
1540 case VK_FORMAT_D16_UNORM_S8_UINT:
1541 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1542 ds->offset_scale = 4.0f;
1543 break;
1544 case VK_FORMAT_D32_SFLOAT:
1545 case VK_FORMAT_D32_SFLOAT_S8_UINT:
1546 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1547 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1548 ds->offset_scale = 1.0f;
1549 break;
1550 default:
1551 break;
1552 }
1553
1554 format = radv_translate_dbformat(iview->vk_format);
1555 if (format == V_028040_Z_INVALID) {
1556 fprintf(stderr, "Invalid DB format: %d, disabling DB.\n", iview->vk_format);
1557 }
1558
1559 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1560 s_offs = z_offs = va;
1561 z_offs += iview->image->surface.level[level].offset;
1562 s_offs += iview->image->surface.stencil_level[level].offset;
1563
1564 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
1565 S_028008_SLICE_MAX(iview->base_layer + iview->extent.depth - 1);
1566 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1567 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
1568
1569 if (iview->image->samples > 1)
1570 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->samples));
1571
1572 if (iview->image->surface.flags & RADEON_SURF_SBUFFER)
1573 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8);
1574 else
1575 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1576
1577 if (device->instance->physicalDevice.rad_info.chip_class >= CIK) {
1578 struct radeon_info *info = &device->instance->physicalDevice.rad_info;
1579 unsigned tiling_index = iview->image->surface.tiling_index[level];
1580 unsigned stencil_index = iview->image->surface.stencil_tiling_index[level];
1581 unsigned macro_index = iview->image->surface.macro_tile_index;
1582 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
1583 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
1584 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
1585
1586 ds->db_depth_info |=
1587 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
1588 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
1589 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
1590 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
1591 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
1592 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
1593 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
1594 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
1595 } else {
1596 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
1597 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1598 tile_mode_index = si_tile_mode_index(iview->image, level, true);
1599 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1600 }
1601
1602 if (iview->image->htile.size && !level) {
1603 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
1604 S_028040_ALLOW_EXPCLEAR(1);
1605
1606 if (iview->image->surface.flags & RADEON_SURF_SBUFFER) {
1607 /* Workaround: For a not yet understood reason, the
1608 * combination of MSAA, fast stencil clear and stencil
1609 * decompress messes with subsequent stencil buffer
1610 * uses. Problem was reproduced on Verde, Bonaire,
1611 * Tonga, and Carrizo.
1612 *
1613 * Disabling EXPCLEAR works around the problem.
1614 *
1615 * Check piglit's arb_texture_multisample-stencil-clear
1616 * test if you want to try changing this.
1617 */
1618 if (iview->image->samples <= 1)
1619 ds->db_stencil_info |= S_028044_ALLOW_EXPCLEAR(1);
1620 } else
1621 /* Use all of the htile_buffer for depth if there's no stencil. */
1622 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1623
1624 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
1625 iview->image->htile.offset;
1626 ds->db_htile_data_base = va >> 8;
1627 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
1628 } else {
1629 ds->db_htile_data_base = 0;
1630 ds->db_htile_surface = 0;
1631 }
1632
1633 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
1634 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
1635
1636 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
1637 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
1638 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
1639 }
1640
1641 VkResult radv_CreateFramebuffer(
1642 VkDevice _device,
1643 const VkFramebufferCreateInfo* pCreateInfo,
1644 const VkAllocationCallbacks* pAllocator,
1645 VkFramebuffer* pFramebuffer)
1646 {
1647 RADV_FROM_HANDLE(radv_device, device, _device);
1648 struct radv_framebuffer *framebuffer;
1649
1650 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
1651
1652 size_t size = sizeof(*framebuffer) +
1653 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
1654 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
1655 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1656 if (framebuffer == NULL)
1657 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1658
1659 framebuffer->attachment_count = pCreateInfo->attachmentCount;
1660 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
1661 VkImageView _iview = pCreateInfo->pAttachments[i];
1662 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
1663 framebuffer->attachments[i].attachment = iview;
1664 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
1665 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
1666 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
1667 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
1668 }
1669 }
1670
1671 framebuffer->width = pCreateInfo->width;
1672 framebuffer->height = pCreateInfo->height;
1673 framebuffer->layers = pCreateInfo->layers;
1674
1675 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
1676 return VK_SUCCESS;
1677 }
1678
1679 void radv_DestroyFramebuffer(
1680 VkDevice _device,
1681 VkFramebuffer _fb,
1682 const VkAllocationCallbacks* pAllocator)
1683 {
1684 RADV_FROM_HANDLE(radv_device, device, _device);
1685 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
1686
1687 if (!fb)
1688 return;
1689 vk_free2(&device->alloc, pAllocator, fb);
1690 }
1691
1692 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
1693 {
1694 switch (address_mode) {
1695 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
1696 return V_008F30_SQ_TEX_WRAP;
1697 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
1698 return V_008F30_SQ_TEX_MIRROR;
1699 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
1700 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1701 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
1702 return V_008F30_SQ_TEX_CLAMP_BORDER;
1703 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
1704 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1705 default:
1706 unreachable("illegal tex wrap mode");
1707 break;
1708 }
1709 }
1710
1711 static unsigned
1712 radv_tex_compare(VkCompareOp op)
1713 {
1714 switch (op) {
1715 case VK_COMPARE_OP_NEVER:
1716 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1717 case VK_COMPARE_OP_LESS:
1718 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1719 case VK_COMPARE_OP_EQUAL:
1720 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1721 case VK_COMPARE_OP_LESS_OR_EQUAL:
1722 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1723 case VK_COMPARE_OP_GREATER:
1724 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1725 case VK_COMPARE_OP_NOT_EQUAL:
1726 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1727 case VK_COMPARE_OP_GREATER_OR_EQUAL:
1728 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1729 case VK_COMPARE_OP_ALWAYS:
1730 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1731 default:
1732 unreachable("illegal compare mode");
1733 break;
1734 }
1735 }
1736
1737 static unsigned
1738 radv_tex_filter(VkFilter filter, unsigned max_ansio)
1739 {
1740 switch (filter) {
1741 case VK_FILTER_NEAREST:
1742 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
1743 V_008F38_SQ_TEX_XY_FILTER_POINT);
1744 case VK_FILTER_LINEAR:
1745 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
1746 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
1747 case VK_FILTER_CUBIC_IMG:
1748 default:
1749 fprintf(stderr, "illegal texture filter");
1750 return 0;
1751 }
1752 }
1753
1754 static unsigned
1755 radv_tex_mipfilter(VkSamplerMipmapMode mode)
1756 {
1757 switch (mode) {
1758 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
1759 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1760 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
1761 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1762 default:
1763 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1764 }
1765 }
1766
1767 static unsigned
1768 radv_tex_bordercolor(VkBorderColor bcolor)
1769 {
1770 switch (bcolor) {
1771 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
1772 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
1773 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
1774 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
1775 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
1776 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
1777 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
1778 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
1779 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
1780 default:
1781 break;
1782 }
1783 return 0;
1784 }
1785
1786 static unsigned
1787 radv_tex_aniso_filter(unsigned filter)
1788 {
1789 if (filter < 2)
1790 return 0;
1791 if (filter < 4)
1792 return 1;
1793 if (filter < 8)
1794 return 2;
1795 if (filter < 16)
1796 return 3;
1797 return 4;
1798 }
1799
1800 static void
1801 radv_init_sampler(struct radv_device *device,
1802 struct radv_sampler *sampler,
1803 const VkSamplerCreateInfo *pCreateInfo)
1804 {
1805 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
1806 (uint32_t) pCreateInfo->maxAnisotropy : 0;
1807 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
1808 bool is_vi;
1809 is_vi = (device->instance->physicalDevice.rad_info.chip_class >= VI);
1810
1811 if (!is_vi && max_aniso > 0) {
1812 radv_finishme("Anisotropic filtering must be disabled manually "
1813 "by the shader on SI-CI when BASE_LEVEL == LAST_LEVEL\n");
1814 max_aniso = max_aniso_ratio = 0;
1815 }
1816
1817 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
1818 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
1819 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
1820 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
1821 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
1822 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
1823 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
1824 S_008F30_ANISO_BIAS(max_aniso_ratio) |
1825 S_008F30_DISABLE_CUBE_WRAP(0) |
1826 S_008F30_COMPAT_MODE(is_vi));
1827 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
1828 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
1829 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
1830 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
1831 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
1832 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
1833 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
1834 S_008F38_MIP_POINT_PRECLAMP(1) |
1835 S_008F38_DISABLE_LSB_CEIL(1) |
1836 S_008F38_FILTER_PREC_FIX(1) |
1837 S_008F38_ANISO_OVERRIDE(is_vi));
1838 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
1839 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
1840 }
1841
1842 VkResult radv_CreateSampler(
1843 VkDevice _device,
1844 const VkSamplerCreateInfo* pCreateInfo,
1845 const VkAllocationCallbacks* pAllocator,
1846 VkSampler* pSampler)
1847 {
1848 RADV_FROM_HANDLE(radv_device, device, _device);
1849 struct radv_sampler *sampler;
1850
1851 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
1852
1853 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
1854 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1855 if (!sampler)
1856 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1857
1858 radv_init_sampler(device, sampler, pCreateInfo);
1859 *pSampler = radv_sampler_to_handle(sampler);
1860
1861 return VK_SUCCESS;
1862 }
1863
1864 void radv_DestroySampler(
1865 VkDevice _device,
1866 VkSampler _sampler,
1867 const VkAllocationCallbacks* pAllocator)
1868 {
1869 RADV_FROM_HANDLE(radv_device, device, _device);
1870 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
1871
1872 if (!sampler)
1873 return;
1874 vk_free2(&device->alloc, pAllocator, sampler);
1875 }