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Revert "radv/gfx10: Enable DCC for storage images."
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "git_sha1.h"
47 #include "util/build_id.h"
48 #include "util/debug.h"
49 #include "util/mesa-sha1.h"
50 #include "compiler/glsl_types.h"
51 #include "util/xmlpool.h"
52
53 static int
54 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
55 {
56 struct mesa_sha1 ctx;
57 unsigned char sha1[20];
58 unsigned ptr_size = sizeof(void*);
59
60 memset(uuid, 0, VK_UUID_SIZE);
61 _mesa_sha1_init(&ctx);
62
63 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
64 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
65 return -1;
66
67 _mesa_sha1_update(&ctx, &family, sizeof(family));
68 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
69 _mesa_sha1_final(&ctx, sha1);
70
71 memcpy(uuid, sha1, VK_UUID_SIZE);
72 return 0;
73 }
74
75 static void
76 radv_get_driver_uuid(void *uuid)
77 {
78 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
79 }
80
81 static void
82 radv_get_device_uuid(struct radeon_info *info, void *uuid)
83 {
84 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
85 }
86
87 static void
88 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
89 {
90 const char *chip_string;
91
92 switch (family) {
93 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
94 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
95 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
96 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
97 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
98 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
99 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
100 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
101 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
102 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
103 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
104 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
105 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
106 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
107 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
108 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
109 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
110 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
111 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
112 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
113 case CHIP_VEGA20: chip_string = "AMD RADV VEGA20"; break;
114 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
115 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
116 case CHIP_NAVI10: chip_string = "AMD RADV NAVI10"; break;
117 case CHIP_NAVI12: chip_string = "AMD RADV NAVI12"; break;
118 case CHIP_NAVI14: chip_string = "AMD RADV NAVI14"; break;
119 default: chip_string = "AMD RADV unknown"; break;
120 }
121
122 snprintf(name, name_len, "%s (LLVM " MESA_LLVM_VERSION_STRING ")", chip_string);
123 }
124
125 static uint64_t
126 radv_get_visible_vram_size(struct radv_physical_device *device)
127 {
128 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
129 }
130
131 static uint64_t
132 radv_get_vram_size(struct radv_physical_device *device)
133 {
134 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
135 }
136
137 static void
138 radv_physical_device_init_mem_types(struct radv_physical_device *device)
139 {
140 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
141 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
142 uint64_t vram_size = radv_get_vram_size(device);
143 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
144 device->memory_properties.memoryHeapCount = 0;
145 if (vram_size > 0) {
146 vram_index = device->memory_properties.memoryHeapCount++;
147 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
148 .size = vram_size,
149 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
150 };
151 }
152 if (visible_vram_size) {
153 visible_vram_index = device->memory_properties.memoryHeapCount++;
154 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
155 .size = visible_vram_size,
156 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
157 };
158 }
159 if (device->rad_info.gart_size > 0) {
160 gart_index = device->memory_properties.memoryHeapCount++;
161 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
162 .size = device->rad_info.gart_size,
163 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
164 };
165 }
166
167 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
168 unsigned type_count = 0;
169 if (vram_index >= 0) {
170 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
171 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
172 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
173 .heapIndex = vram_index,
174 };
175 }
176 if (gart_index >= 0) {
177 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
178 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
179 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
180 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
181 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
182 .heapIndex = gart_index,
183 };
184 }
185 if (visible_vram_index >= 0) {
186 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
187 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
188 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
189 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
190 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
191 .heapIndex = visible_vram_index,
192 };
193 }
194 if (gart_index >= 0) {
195 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
196 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
197 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
198 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
199 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
200 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
201 .heapIndex = gart_index,
202 };
203 }
204 device->memory_properties.memoryTypeCount = type_count;
205 }
206
207 static void
208 radv_handle_env_var_force_family(struct radv_physical_device *device)
209 {
210 const char *family = getenv("RADV_FORCE_FAMILY");
211 unsigned i;
212
213 if (!family)
214 return;
215
216 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
217 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
218 /* Override family and chip_class. */
219 device->rad_info.family = i;
220
221 if (i >= CHIP_NAVI10)
222 device->rad_info.chip_class = GFX10;
223 else if (i >= CHIP_VEGA10)
224 device->rad_info.chip_class = GFX9;
225 else if (i >= CHIP_TONGA)
226 device->rad_info.chip_class = GFX8;
227 else if (i >= CHIP_BONAIRE)
228 device->rad_info.chip_class = GFX7;
229 else
230 device->rad_info.chip_class = GFX6;
231
232 return;
233 }
234 }
235
236 fprintf(stderr, "radv: Unknown family: %s\n", family);
237 exit(1);
238 }
239
240 static VkResult
241 radv_physical_device_init(struct radv_physical_device *device,
242 struct radv_instance *instance,
243 drmDevicePtr drm_device)
244 {
245 const char *path = drm_device->nodes[DRM_NODE_RENDER];
246 VkResult result;
247 drmVersionPtr version;
248 int fd;
249 int master_fd = -1;
250
251 fd = open(path, O_RDWR | O_CLOEXEC);
252 if (fd < 0) {
253 if (instance->debug_flags & RADV_DEBUG_STARTUP)
254 radv_logi("Could not open device '%s'", path);
255
256 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
257 }
258
259 version = drmGetVersion(fd);
260 if (!version) {
261 close(fd);
262
263 if (instance->debug_flags & RADV_DEBUG_STARTUP)
264 radv_logi("Could not get the kernel driver version for device '%s'", path);
265
266 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
267 "failed to get version %s: %m", path);
268 }
269
270 if (strcmp(version->name, "amdgpu")) {
271 drmFreeVersion(version);
272 close(fd);
273
274 if (instance->debug_flags & RADV_DEBUG_STARTUP)
275 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
276
277 return VK_ERROR_INCOMPATIBLE_DRIVER;
278 }
279 drmFreeVersion(version);
280
281 if (instance->debug_flags & RADV_DEBUG_STARTUP)
282 radv_logi("Found compatible device '%s'.", path);
283
284 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
285 device->instance = instance;
286
287 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
288 instance->perftest_flags);
289 if (!device->ws) {
290 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
291 goto fail;
292 }
293
294 if (instance->enabled_extensions.KHR_display) {
295 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
296 if (master_fd >= 0) {
297 uint32_t accel_working = 0;
298 struct drm_amdgpu_info request = {
299 .return_pointer = (uintptr_t)&accel_working,
300 .return_size = sizeof(accel_working),
301 .query = AMDGPU_INFO_ACCEL_WORKING
302 };
303
304 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
305 close(master_fd);
306 master_fd = -1;
307 }
308 }
309 }
310
311 device->master_fd = master_fd;
312 device->local_fd = fd;
313 device->ws->query_info(device->ws, &device->rad_info);
314
315 radv_handle_env_var_force_family(device);
316
317 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
318
319 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
320 device->ws->destroy(device->ws);
321 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
322 "cannot generate UUID");
323 goto fail;
324 }
325
326 /* These flags affect shader compilation. */
327 uint64_t shader_env_flags =
328 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
329 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
330
331 /* The gpu id is already embedded in the uuid so we just pass "radv"
332 * when creating the cache.
333 */
334 char buf[VK_UUID_SIZE * 2 + 1];
335 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
336 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
337
338 if (device->rad_info.chip_class < GFX8 ||
339 device->rad_info.chip_class > GFX9)
340 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
341
342 radv_get_driver_uuid(&device->driver_uuid);
343 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
344
345 if (device->rad_info.family == CHIP_STONEY ||
346 device->rad_info.chip_class >= GFX9) {
347 device->has_rbplus = true;
348 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
349 device->rad_info.family == CHIP_VEGA12 ||
350 device->rad_info.family == CHIP_RAVEN ||
351 device->rad_info.family == CHIP_RAVEN2;
352 }
353
354 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
355 * on GFX6.
356 */
357 device->has_clear_state = device->rad_info.chip_class >= GFX7;
358
359 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= GFX8;
360
361 /* Vega10/Raven need a special workaround for a hardware bug. */
362 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
363 device->rad_info.family == CHIP_RAVEN;
364
365 device->has_tc_compat_zrange_bug = device->rad_info.chip_class < GFX10;
366
367 /* Out-of-order primitive rasterization. */
368 device->has_out_of_order_rast = device->rad_info.chip_class >= GFX8 &&
369 device->rad_info.max_se >= 2;
370 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
371 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
372
373 device->dcc_msaa_allowed =
374 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
375
376 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
377 device->has_load_ctx_reg_pkt = device->rad_info.chip_class >= GFX9 ||
378 (device->rad_info.chip_class >= GFX8 &&
379 device->rad_info.me_fw_feature >= 41);
380
381 device->has_dcc_constant_encode = device->rad_info.family == CHIP_RAVEN2 ||
382 device->rad_info.chip_class >= GFX10;
383
384 device->use_shader_ballot = device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT;
385
386 /* Determine the number of threads per wave for all stages. */
387 device->cs_wave_size = 64;
388 device->ps_wave_size = 64;
389 device->ge_wave_size = 64;
390
391 if (device->rad_info.chip_class >= GFX10) {
392 if (device->instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32)
393 device->cs_wave_size = 32;
394
395 /* For pixel shaders, wave64 is recommanded. */
396 if (device->instance->perftest_flags & RADV_PERFTEST_PS_WAVE_32)
397 device->ps_wave_size = 32;
398
399 if (device->instance->perftest_flags & RADV_PERFTEST_GE_WAVE_32)
400 device->ge_wave_size = 32;
401 }
402
403 radv_physical_device_init_mem_types(device);
404 radv_fill_device_extension_table(device, &device->supported_extensions);
405
406 device->bus_info = *drm_device->businfo.pci;
407
408 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
409 ac_print_gpu_info(&device->rad_info);
410
411 /* The WSI is structured as a layer on top of the driver, so this has
412 * to be the last part of initialization (at least until we get other
413 * semi-layers).
414 */
415 result = radv_init_wsi(device);
416 if (result != VK_SUCCESS) {
417 device->ws->destroy(device->ws);
418 vk_error(instance, result);
419 goto fail;
420 }
421
422 return VK_SUCCESS;
423
424 fail:
425 close(fd);
426 if (master_fd != -1)
427 close(master_fd);
428 return result;
429 }
430
431 static void
432 radv_physical_device_finish(struct radv_physical_device *device)
433 {
434 radv_finish_wsi(device);
435 device->ws->destroy(device->ws);
436 disk_cache_destroy(device->disk_cache);
437 close(device->local_fd);
438 if (device->master_fd != -1)
439 close(device->master_fd);
440 }
441
442 static void *
443 default_alloc_func(void *pUserData, size_t size, size_t align,
444 VkSystemAllocationScope allocationScope)
445 {
446 return malloc(size);
447 }
448
449 static void *
450 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
451 size_t align, VkSystemAllocationScope allocationScope)
452 {
453 return realloc(pOriginal, size);
454 }
455
456 static void
457 default_free_func(void *pUserData, void *pMemory)
458 {
459 free(pMemory);
460 }
461
462 static const VkAllocationCallbacks default_alloc = {
463 .pUserData = NULL,
464 .pfnAllocation = default_alloc_func,
465 .pfnReallocation = default_realloc_func,
466 .pfnFree = default_free_func,
467 };
468
469 static const struct debug_control radv_debug_options[] = {
470 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
471 {"nodcc", RADV_DEBUG_NO_DCC},
472 {"shaders", RADV_DEBUG_DUMP_SHADERS},
473 {"nocache", RADV_DEBUG_NO_CACHE},
474 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
475 {"nohiz", RADV_DEBUG_NO_HIZ},
476 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
477 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
478 {"allbos", RADV_DEBUG_ALL_BOS},
479 {"noibs", RADV_DEBUG_NO_IBS},
480 {"spirv", RADV_DEBUG_DUMP_SPIRV},
481 {"vmfaults", RADV_DEBUG_VM_FAULTS},
482 {"zerovram", RADV_DEBUG_ZERO_VRAM},
483 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
484 {"nosisched", RADV_DEBUG_NO_SISCHED},
485 {"preoptir", RADV_DEBUG_PREOPTIR},
486 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
487 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
488 {"info", RADV_DEBUG_INFO},
489 {"errors", RADV_DEBUG_ERRORS},
490 {"startup", RADV_DEBUG_STARTUP},
491 {"checkir", RADV_DEBUG_CHECKIR},
492 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
493 {"nobinning", RADV_DEBUG_NOBINNING},
494 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT},
495 {"nongg", RADV_DEBUG_NO_NGG},
496 {NULL, 0}
497 };
498
499 const char *
500 radv_get_debug_option_name(int id)
501 {
502 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
503 return radv_debug_options[id].string;
504 }
505
506 static const struct debug_control radv_perftest_options[] = {
507 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
508 {"sisched", RADV_PERFTEST_SISCHED},
509 {"localbos", RADV_PERFTEST_LOCAL_BOS},
510 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
511 {"bolist", RADV_PERFTEST_BO_LIST},
512 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT},
513 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
514 {"cswave32", RADV_PERFTEST_CS_WAVE_32},
515 {"pswave32", RADV_PERFTEST_PS_WAVE_32},
516 {"gewave32", RADV_PERFTEST_GE_WAVE_32},
517 {NULL, 0}
518 };
519
520 const char *
521 radv_get_perftest_option_name(int id)
522 {
523 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
524 return radv_perftest_options[id].string;
525 }
526
527 static void
528 radv_handle_per_app_options(struct radv_instance *instance,
529 const VkApplicationInfo *info)
530 {
531 const char *name = info ? info->pApplicationName : NULL;
532
533 if (!name)
534 return;
535
536 if (!strcmp(name, "Talos - Linux - 32bit") ||
537 !strcmp(name, "Talos - Linux - 64bit")) {
538 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
539 /* Force enable LLVM sisched for Talos because it looks
540 * safe and it gives few more FPS.
541 */
542 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
543 }
544 } else if (!strcmp(name, "DOOM_VFR")) {
545 /* Work around a Doom VFR game bug */
546 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
547 } else if (!strcmp(name, "MonsterHunterWorld.exe")) {
548 /* Workaround for a WaW hazard when LLVM moves/merges
549 * load/store memory operations.
550 * See https://reviews.llvm.org/D61313
551 */
552 if (HAVE_LLVM < 0x900)
553 instance->debug_flags |= RADV_DEBUG_NO_LOAD_STORE_OPT;
554 }
555 }
556
557 static int radv_get_instance_extension_index(const char *name)
558 {
559 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
560 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
561 return i;
562 }
563 return -1;
564 }
565
566 static const char radv_dri_options_xml[] =
567 DRI_CONF_BEGIN
568 DRI_CONF_SECTION_QUALITY
569 DRI_CONF_ADAPTIVE_SYNC("true")
570 DRI_CONF_SECTION_END
571 DRI_CONF_END;
572
573 static void radv_init_dri_options(struct radv_instance *instance)
574 {
575 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
576 driParseConfigFiles(&instance->dri_options,
577 &instance->available_dri_options,
578 0, "radv", NULL);
579 }
580
581 VkResult radv_CreateInstance(
582 const VkInstanceCreateInfo* pCreateInfo,
583 const VkAllocationCallbacks* pAllocator,
584 VkInstance* pInstance)
585 {
586 struct radv_instance *instance;
587 VkResult result;
588
589 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
590
591 uint32_t client_version;
592 if (pCreateInfo->pApplicationInfo &&
593 pCreateInfo->pApplicationInfo->apiVersion != 0) {
594 client_version = pCreateInfo->pApplicationInfo->apiVersion;
595 } else {
596 client_version = VK_API_VERSION_1_0;
597 }
598
599 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
600 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
601 if (!instance)
602 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
603
604 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
605
606 if (pAllocator)
607 instance->alloc = *pAllocator;
608 else
609 instance->alloc = default_alloc;
610
611 instance->apiVersion = client_version;
612 instance->physicalDeviceCount = -1;
613
614 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
615 radv_debug_options);
616
617 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
618 radv_perftest_options);
619
620
621 if (instance->debug_flags & RADV_DEBUG_STARTUP)
622 radv_logi("Created an instance");
623
624 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
625 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
626 int index = radv_get_instance_extension_index(ext_name);
627
628 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
629 vk_free2(&default_alloc, pAllocator, instance);
630 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
631 }
632
633 instance->enabled_extensions.extensions[index] = true;
634 }
635
636 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
637 if (result != VK_SUCCESS) {
638 vk_free2(&default_alloc, pAllocator, instance);
639 return vk_error(instance, result);
640 }
641
642 _mesa_locale_init();
643 glsl_type_singleton_init_or_ref();
644
645 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
646
647 radv_init_dri_options(instance);
648 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
649
650 *pInstance = radv_instance_to_handle(instance);
651
652 return VK_SUCCESS;
653 }
654
655 void radv_DestroyInstance(
656 VkInstance _instance,
657 const VkAllocationCallbacks* pAllocator)
658 {
659 RADV_FROM_HANDLE(radv_instance, instance, _instance);
660
661 if (!instance)
662 return;
663
664 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
665 radv_physical_device_finish(instance->physicalDevices + i);
666 }
667
668 VG(VALGRIND_DESTROY_MEMPOOL(instance));
669
670 glsl_type_singleton_decref();
671 _mesa_locale_fini();
672
673 driDestroyOptionCache(&instance->dri_options);
674 driDestroyOptionInfo(&instance->available_dri_options);
675
676 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
677
678 vk_free(&instance->alloc, instance);
679 }
680
681 static VkResult
682 radv_enumerate_devices(struct radv_instance *instance)
683 {
684 /* TODO: Check for more devices ? */
685 drmDevicePtr devices[8];
686 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
687 int max_devices;
688
689 instance->physicalDeviceCount = 0;
690
691 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
692
693 if (instance->debug_flags & RADV_DEBUG_STARTUP)
694 radv_logi("Found %d drm nodes", max_devices);
695
696 if (max_devices < 1)
697 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
698
699 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
700 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
701 devices[i]->bustype == DRM_BUS_PCI &&
702 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
703
704 result = radv_physical_device_init(instance->physicalDevices +
705 instance->physicalDeviceCount,
706 instance,
707 devices[i]);
708 if (result == VK_SUCCESS)
709 ++instance->physicalDeviceCount;
710 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
711 break;
712 }
713 }
714 drmFreeDevices(devices, max_devices);
715
716 return result;
717 }
718
719 VkResult radv_EnumeratePhysicalDevices(
720 VkInstance _instance,
721 uint32_t* pPhysicalDeviceCount,
722 VkPhysicalDevice* pPhysicalDevices)
723 {
724 RADV_FROM_HANDLE(radv_instance, instance, _instance);
725 VkResult result;
726
727 if (instance->physicalDeviceCount < 0) {
728 result = radv_enumerate_devices(instance);
729 if (result != VK_SUCCESS &&
730 result != VK_ERROR_INCOMPATIBLE_DRIVER)
731 return result;
732 }
733
734 if (!pPhysicalDevices) {
735 *pPhysicalDeviceCount = instance->physicalDeviceCount;
736 } else {
737 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
738 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
739 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
740 }
741
742 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
743 : VK_SUCCESS;
744 }
745
746 VkResult radv_EnumeratePhysicalDeviceGroups(
747 VkInstance _instance,
748 uint32_t* pPhysicalDeviceGroupCount,
749 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
750 {
751 RADV_FROM_HANDLE(radv_instance, instance, _instance);
752 VkResult result;
753
754 if (instance->physicalDeviceCount < 0) {
755 result = radv_enumerate_devices(instance);
756 if (result != VK_SUCCESS &&
757 result != VK_ERROR_INCOMPATIBLE_DRIVER)
758 return result;
759 }
760
761 if (!pPhysicalDeviceGroupProperties) {
762 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
763 } else {
764 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
765 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
766 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
767 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
768 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
769 }
770 }
771 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
772 : VK_SUCCESS;
773 }
774
775 void radv_GetPhysicalDeviceFeatures(
776 VkPhysicalDevice physicalDevice,
777 VkPhysicalDeviceFeatures* pFeatures)
778 {
779 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
780 memset(pFeatures, 0, sizeof(*pFeatures));
781
782 *pFeatures = (VkPhysicalDeviceFeatures) {
783 .robustBufferAccess = true,
784 .fullDrawIndexUint32 = true,
785 .imageCubeArray = true,
786 .independentBlend = true,
787 .geometryShader = true,
788 .tessellationShader = true,
789 .sampleRateShading = true,
790 .dualSrcBlend = true,
791 .logicOp = true,
792 .multiDrawIndirect = true,
793 .drawIndirectFirstInstance = true,
794 .depthClamp = true,
795 .depthBiasClamp = true,
796 .fillModeNonSolid = true,
797 .depthBounds = true,
798 .wideLines = true,
799 .largePoints = true,
800 .alphaToOne = true,
801 .multiViewport = true,
802 .samplerAnisotropy = true,
803 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
804 .textureCompressionASTC_LDR = false,
805 .textureCompressionBC = true,
806 .occlusionQueryPrecise = true,
807 .pipelineStatisticsQuery = true,
808 .vertexPipelineStoresAndAtomics = true,
809 .fragmentStoresAndAtomics = true,
810 .shaderTessellationAndGeometryPointSize = true,
811 .shaderImageGatherExtended = true,
812 .shaderStorageImageExtendedFormats = true,
813 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= GFX8,
814 .shaderUniformBufferArrayDynamicIndexing = true,
815 .shaderSampledImageArrayDynamicIndexing = true,
816 .shaderStorageBufferArrayDynamicIndexing = true,
817 .shaderStorageImageArrayDynamicIndexing = true,
818 .shaderStorageImageReadWithoutFormat = true,
819 .shaderStorageImageWriteWithoutFormat = true,
820 .shaderClipDistance = true,
821 .shaderCullDistance = true,
822 .shaderFloat64 = true,
823 .shaderInt64 = true,
824 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
825 .sparseBinding = true,
826 .variableMultisampleRate = true,
827 .inheritedQueries = true,
828 };
829 }
830
831 void radv_GetPhysicalDeviceFeatures2(
832 VkPhysicalDevice physicalDevice,
833 VkPhysicalDeviceFeatures2 *pFeatures)
834 {
835 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
836 vk_foreach_struct(ext, pFeatures->pNext) {
837 switch (ext->sType) {
838 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
839 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
840 features->variablePointersStorageBuffer = true;
841 features->variablePointers = true;
842 break;
843 }
844 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
845 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
846 features->multiview = true;
847 features->multiviewGeometryShader = true;
848 features->multiviewTessellationShader = true;
849 break;
850 }
851 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
852 VkPhysicalDeviceShaderDrawParametersFeatures *features =
853 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
854 features->shaderDrawParameters = true;
855 break;
856 }
857 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
858 VkPhysicalDeviceProtectedMemoryFeatures *features =
859 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
860 features->protectedMemory = false;
861 break;
862 }
863 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
864 VkPhysicalDevice16BitStorageFeatures *features =
865 (VkPhysicalDevice16BitStorageFeatures*)ext;
866 bool enabled = pdevice->rad_info.chip_class >= GFX8;
867 features->storageBuffer16BitAccess = enabled;
868 features->uniformAndStorageBuffer16BitAccess = enabled;
869 features->storagePushConstant16 = enabled;
870 features->storageInputOutput16 = enabled && HAVE_LLVM >= 0x900;
871 break;
872 }
873 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
874 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
875 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
876 features->samplerYcbcrConversion = true;
877 break;
878 }
879 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
880 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
881 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
882 features->shaderInputAttachmentArrayDynamicIndexing = true;
883 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
884 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
885 features->shaderUniformBufferArrayNonUniformIndexing = true;
886 features->shaderSampledImageArrayNonUniformIndexing = true;
887 features->shaderStorageBufferArrayNonUniformIndexing = true;
888 features->shaderStorageImageArrayNonUniformIndexing = true;
889 features->shaderInputAttachmentArrayNonUniformIndexing = true;
890 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
891 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
892 features->descriptorBindingUniformBufferUpdateAfterBind = true;
893 features->descriptorBindingSampledImageUpdateAfterBind = true;
894 features->descriptorBindingStorageImageUpdateAfterBind = true;
895 features->descriptorBindingStorageBufferUpdateAfterBind = true;
896 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
897 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
898 features->descriptorBindingUpdateUnusedWhilePending = true;
899 features->descriptorBindingPartiallyBound = true;
900 features->descriptorBindingVariableDescriptorCount = true;
901 features->runtimeDescriptorArray = true;
902 break;
903 }
904 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
905 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
906 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
907 features->conditionalRendering = true;
908 features->inheritedConditionalRendering = false;
909 break;
910 }
911 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
912 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
913 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
914 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
915 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
916 break;
917 }
918 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
919 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
920 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
921 features->transformFeedback = true;
922 features->geometryStreams = true;
923 break;
924 }
925 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
926 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
927 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
928 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
929 break;
930 }
931 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
932 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
933 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
934 features->memoryPriority = VK_TRUE;
935 break;
936 }
937 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
938 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
939 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
940 features->bufferDeviceAddress = true;
941 features->bufferDeviceAddressCaptureReplay = false;
942 features->bufferDeviceAddressMultiDevice = false;
943 break;
944 }
945 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
946 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
947 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
948 features->depthClipEnable = true;
949 break;
950 }
951 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT: {
952 VkPhysicalDeviceHostQueryResetFeaturesEXT *features =
953 (VkPhysicalDeviceHostQueryResetFeaturesEXT *)ext;
954 features->hostQueryReset = true;
955 break;
956 }
957 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: {
958 VkPhysicalDevice8BitStorageFeaturesKHR *features =
959 (VkPhysicalDevice8BitStorageFeaturesKHR*)ext;
960 bool enabled = pdevice->rad_info.chip_class >= GFX8;
961 features->storageBuffer8BitAccess = enabled;
962 features->uniformAndStorageBuffer8BitAccess = enabled;
963 features->storagePushConstant8 = enabled;
964 break;
965 }
966 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR: {
967 VkPhysicalDeviceFloat16Int8FeaturesKHR *features =
968 (VkPhysicalDeviceFloat16Int8FeaturesKHR*)ext;
969 features->shaderFloat16 = pdevice->rad_info.chip_class >= GFX8 && HAVE_LLVM >= 0x0800;
970 features->shaderInt8 = true;
971 break;
972 }
973 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR: {
974 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *features =
975 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *)ext;
976 features->shaderBufferInt64Atomics = HAVE_LLVM >= 0x0900;
977 features->shaderSharedInt64Atomics = HAVE_LLVM >= 0x0900;
978 break;
979 }
980 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
981 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
982 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
983
984 features->inlineUniformBlock = true;
985 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
986 break;
987 }
988 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
989 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
990 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
991 features->computeDerivativeGroupQuads = false;
992 features->computeDerivativeGroupLinear = true;
993 break;
994 }
995 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
996 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
997 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
998 features->ycbcrImageArrays = true;
999 break;
1000 }
1001 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR: {
1002 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *features =
1003 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *)ext;
1004 features->uniformBufferStandardLayout = true;
1005 break;
1006 }
1007 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT: {
1008 VkPhysicalDeviceIndexTypeUint8FeaturesEXT *features =
1009 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT *)ext;
1010 features->indexTypeUint8 = pdevice->rad_info.chip_class >= GFX8;
1011 break;
1012 }
1013 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES_KHR: {
1014 VkPhysicalDeviceImagelessFramebufferFeaturesKHR *features =
1015 (VkPhysicalDeviceImagelessFramebufferFeaturesKHR *)ext;
1016 features->imagelessFramebuffer = true;
1017 break;
1018 }
1019 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR: {
1020 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *features =
1021 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *)ext;
1022 features->pipelineExecutableInfo = true;
1023 break;
1024 }
1025 default:
1026 break;
1027 }
1028 }
1029 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
1030 }
1031
1032 void radv_GetPhysicalDeviceProperties(
1033 VkPhysicalDevice physicalDevice,
1034 VkPhysicalDeviceProperties* pProperties)
1035 {
1036 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1037 VkSampleCountFlags sample_counts = 0xf;
1038
1039 /* make sure that the entire descriptor set is addressable with a signed
1040 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1041 * be at most 2 GiB. the combined image & samples object count as one of
1042 * both. This limit is for the pipeline layout, not for the set layout, but
1043 * there is no set limit, so we just set a pipeline limit. I don't think
1044 * any app is going to hit this soon. */
1045 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1046 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1047 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1048 32 /* sampler, largest when combined with image */ +
1049 64 /* sampled image */ +
1050 64 /* storage image */);
1051
1052 VkPhysicalDeviceLimits limits = {
1053 .maxImageDimension1D = (1 << 14),
1054 .maxImageDimension2D = (1 << 14),
1055 .maxImageDimension3D = (1 << 11),
1056 .maxImageDimensionCube = (1 << 14),
1057 .maxImageArrayLayers = (1 << 11),
1058 .maxTexelBufferElements = 128 * 1024 * 1024,
1059 .maxUniformBufferRange = UINT32_MAX,
1060 .maxStorageBufferRange = UINT32_MAX,
1061 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1062 .maxMemoryAllocationCount = UINT32_MAX,
1063 .maxSamplerAllocationCount = 64 * 1024,
1064 .bufferImageGranularity = 64, /* A cache line */
1065 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
1066 .maxBoundDescriptorSets = MAX_SETS,
1067 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1068 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1069 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1070 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1071 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1072 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1073 .maxPerStageResources = max_descriptor_set_size,
1074 .maxDescriptorSetSamplers = max_descriptor_set_size,
1075 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1076 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1077 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1078 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1079 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1080 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1081 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1082 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1083 .maxVertexInputBindings = MAX_VBS,
1084 .maxVertexInputAttributeOffset = 2047,
1085 .maxVertexInputBindingStride = 2048,
1086 .maxVertexOutputComponents = 128,
1087 .maxTessellationGenerationLevel = 64,
1088 .maxTessellationPatchSize = 32,
1089 .maxTessellationControlPerVertexInputComponents = 128,
1090 .maxTessellationControlPerVertexOutputComponents = 128,
1091 .maxTessellationControlPerPatchOutputComponents = 120,
1092 .maxTessellationControlTotalOutputComponents = 4096,
1093 .maxTessellationEvaluationInputComponents = 128,
1094 .maxTessellationEvaluationOutputComponents = 128,
1095 .maxGeometryShaderInvocations = 127,
1096 .maxGeometryInputComponents = 64,
1097 .maxGeometryOutputComponents = 128,
1098 .maxGeometryOutputVertices = 256,
1099 .maxGeometryTotalOutputComponents = 1024,
1100 .maxFragmentInputComponents = 128,
1101 .maxFragmentOutputAttachments = 8,
1102 .maxFragmentDualSrcAttachments = 1,
1103 .maxFragmentCombinedOutputResources = 8,
1104 .maxComputeSharedMemorySize = 32768,
1105 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1106 .maxComputeWorkGroupInvocations = 2048,
1107 .maxComputeWorkGroupSize = {
1108 2048,
1109 2048,
1110 2048
1111 },
1112 .subPixelPrecisionBits = 8,
1113 .subTexelPrecisionBits = 8,
1114 .mipmapPrecisionBits = 8,
1115 .maxDrawIndexedIndexValue = UINT32_MAX,
1116 .maxDrawIndirectCount = UINT32_MAX,
1117 .maxSamplerLodBias = 16,
1118 .maxSamplerAnisotropy = 16,
1119 .maxViewports = MAX_VIEWPORTS,
1120 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1121 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1122 .viewportSubPixelBits = 8,
1123 .minMemoryMapAlignment = 4096, /* A page */
1124 .minTexelBufferOffsetAlignment = 1,
1125 .minUniformBufferOffsetAlignment = 4,
1126 .minStorageBufferOffsetAlignment = 4,
1127 .minTexelOffset = -32,
1128 .maxTexelOffset = 31,
1129 .minTexelGatherOffset = -32,
1130 .maxTexelGatherOffset = 31,
1131 .minInterpolationOffset = -2,
1132 .maxInterpolationOffset = 2,
1133 .subPixelInterpolationOffsetBits = 8,
1134 .maxFramebufferWidth = (1 << 14),
1135 .maxFramebufferHeight = (1 << 14),
1136 .maxFramebufferLayers = (1 << 10),
1137 .framebufferColorSampleCounts = sample_counts,
1138 .framebufferDepthSampleCounts = sample_counts,
1139 .framebufferStencilSampleCounts = sample_counts,
1140 .framebufferNoAttachmentsSampleCounts = sample_counts,
1141 .maxColorAttachments = MAX_RTS,
1142 .sampledImageColorSampleCounts = sample_counts,
1143 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1144 .sampledImageDepthSampleCounts = sample_counts,
1145 .sampledImageStencilSampleCounts = sample_counts,
1146 .storageImageSampleCounts = pdevice->rad_info.chip_class >= GFX8 ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1147 .maxSampleMaskWords = 1,
1148 .timestampComputeAndGraphics = true,
1149 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1150 .maxClipDistances = 8,
1151 .maxCullDistances = 8,
1152 .maxCombinedClipAndCullDistances = 8,
1153 .discreteQueuePriorities = 2,
1154 .pointSizeRange = { 0.0, 8192.0 },
1155 .lineWidthRange = { 0.0, 7.9921875 },
1156 .pointSizeGranularity = (1.0 / 8.0),
1157 .lineWidthGranularity = (1.0 / 128.0),
1158 .strictLines = false, /* FINISHME */
1159 .standardSampleLocations = true,
1160 .optimalBufferCopyOffsetAlignment = 128,
1161 .optimalBufferCopyRowPitchAlignment = 128,
1162 .nonCoherentAtomSize = 64,
1163 };
1164
1165 *pProperties = (VkPhysicalDeviceProperties) {
1166 .apiVersion = radv_physical_device_api_version(pdevice),
1167 .driverVersion = vk_get_driver_version(),
1168 .vendorID = ATI_VENDOR_ID,
1169 .deviceID = pdevice->rad_info.pci_id,
1170 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1171 .limits = limits,
1172 .sparseProperties = {0},
1173 };
1174
1175 strcpy(pProperties->deviceName, pdevice->name);
1176 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1177 }
1178
1179 void radv_GetPhysicalDeviceProperties2(
1180 VkPhysicalDevice physicalDevice,
1181 VkPhysicalDeviceProperties2 *pProperties)
1182 {
1183 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1184 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1185
1186 vk_foreach_struct(ext, pProperties->pNext) {
1187 switch (ext->sType) {
1188 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1189 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1190 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1191 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1192 break;
1193 }
1194 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1195 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1196 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1197 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1198 properties->deviceLUIDValid = false;
1199 break;
1200 }
1201 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1202 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1203 properties->maxMultiviewViewCount = MAX_VIEWS;
1204 properties->maxMultiviewInstanceIndex = INT_MAX;
1205 break;
1206 }
1207 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1208 VkPhysicalDevicePointClippingProperties *properties =
1209 (VkPhysicalDevicePointClippingProperties*)ext;
1210 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1211 break;
1212 }
1213 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1214 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1215 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1216 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1217 break;
1218 }
1219 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1220 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1221 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1222 properties->minImportedHostPointerAlignment = 4096;
1223 break;
1224 }
1225 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1226 VkPhysicalDeviceSubgroupProperties *properties =
1227 (VkPhysicalDeviceSubgroupProperties*)ext;
1228 properties->subgroupSize = 64;
1229 properties->supportedStages = VK_SHADER_STAGE_ALL;
1230 properties->supportedOperations =
1231 VK_SUBGROUP_FEATURE_BASIC_BIT |
1232 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1233 VK_SUBGROUP_FEATURE_QUAD_BIT |
1234 VK_SUBGROUP_FEATURE_VOTE_BIT;
1235 if (pdevice->rad_info.chip_class >= GFX8) {
1236 properties->supportedOperations |=
1237 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1238 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1239 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1240 }
1241 properties->quadOperationsInAllStages = true;
1242 break;
1243 }
1244 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1245 VkPhysicalDeviceMaintenance3Properties *properties =
1246 (VkPhysicalDeviceMaintenance3Properties*)ext;
1247 /* Make sure everything is addressable by a signed 32-bit int, and
1248 * our largest descriptors are 96 bytes. */
1249 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1250 /* Our buffer size fields allow only this much */
1251 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1252 break;
1253 }
1254 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1255 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1256 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1257 /* GFX6-8 only support single channel min/max filter. */
1258 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1259 properties->filterMinmaxSingleComponentFormats = true;
1260 break;
1261 }
1262 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1263 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1264 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1265
1266 /* Shader engines. */
1267 properties->shaderEngineCount =
1268 pdevice->rad_info.max_se;
1269 properties->shaderArraysPerEngineCount =
1270 pdevice->rad_info.max_sh_per_se;
1271 properties->computeUnitsPerShaderArray =
1272 pdevice->rad_info.num_good_cu_per_sh;
1273 properties->simdPerComputeUnit = 4;
1274 properties->wavefrontsPerSimd =
1275 pdevice->rad_info.family == CHIP_TONGA ||
1276 pdevice->rad_info.family == CHIP_ICELAND ||
1277 pdevice->rad_info.family == CHIP_POLARIS10 ||
1278 pdevice->rad_info.family == CHIP_POLARIS11 ||
1279 pdevice->rad_info.family == CHIP_POLARIS12 ||
1280 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1281 properties->wavefrontSize = 64;
1282
1283 /* SGPR. */
1284 properties->sgprsPerSimd =
1285 ac_get_num_physical_sgprs(pdevice->rad_info.chip_class);
1286 properties->minSgprAllocation =
1287 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1288 properties->maxSgprAllocation =
1289 pdevice->rad_info.family == CHIP_TONGA ||
1290 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1291 properties->sgprAllocationGranularity =
1292 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1293
1294 /* VGPR. */
1295 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1296 properties->minVgprAllocation = 4;
1297 properties->maxVgprAllocation = 256;
1298 properties->vgprAllocationGranularity = 4;
1299 break;
1300 }
1301 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1302 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1303 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1304 properties->maxVertexAttribDivisor = UINT32_MAX;
1305 break;
1306 }
1307 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1308 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1309 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1310 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1311 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1312 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1313 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1314 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1315 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1316 properties->robustBufferAccessUpdateAfterBind = false;
1317 properties->quadDivergentImplicitLod = false;
1318
1319 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1320 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1321 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1322 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1323 32 /* sampler, largest when combined with image */ +
1324 64 /* sampled image */ +
1325 64 /* storage image */);
1326 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1327 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1328 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1329 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1330 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1331 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1332 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1333 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1334 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1335 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1336 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1337 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1338 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1339 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1340 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1341 break;
1342 }
1343 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1344 VkPhysicalDeviceProtectedMemoryProperties *properties =
1345 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1346 properties->protectedNoFault = false;
1347 break;
1348 }
1349 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1350 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1351 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1352 properties->primitiveOverestimationSize = 0;
1353 properties->maxExtraPrimitiveOverestimationSize = 0;
1354 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1355 properties->primitiveUnderestimation = VK_FALSE;
1356 properties->conservativePointAndLineRasterization = VK_FALSE;
1357 properties->degenerateTrianglesRasterized = VK_FALSE;
1358 properties->degenerateLinesRasterized = VK_FALSE;
1359 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1360 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1361 break;
1362 }
1363 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1364 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1365 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1366 properties->pciDomain = pdevice->bus_info.domain;
1367 properties->pciBus = pdevice->bus_info.bus;
1368 properties->pciDevice = pdevice->bus_info.dev;
1369 properties->pciFunction = pdevice->bus_info.func;
1370 break;
1371 }
1372 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1373 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1374 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1375
1376 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1377 snprintf(driver_props->driverName, VK_MAX_DRIVER_NAME_SIZE_KHR, "radv");
1378 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1379 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1380 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1381
1382 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1383 .major = 1,
1384 .minor = 1,
1385 .subminor = 2,
1386 .patch = 0,
1387 };
1388 break;
1389 }
1390 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1391 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1392 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1393 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1394 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1395 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1396 properties->maxTransformFeedbackStreamDataSize = 512;
1397 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1398 properties->maxTransformFeedbackBufferDataStride = 512;
1399 properties->transformFeedbackQueries = true;
1400 properties->transformFeedbackStreamsLinesTriangles = true;
1401 properties->transformFeedbackRasterizationStreamSelect = false;
1402 properties->transformFeedbackDraw = true;
1403 break;
1404 }
1405 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1406 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1407 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1408
1409 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1410 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1411 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1412 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1413 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1414 break;
1415 }
1416 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1417 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1418 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1419 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1420 VK_SAMPLE_COUNT_4_BIT |
1421 VK_SAMPLE_COUNT_8_BIT;
1422 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1423 properties->sampleLocationCoordinateRange[0] = 0.0f;
1424 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1425 properties->sampleLocationSubPixelBits = 4;
1426 properties->variableSampleLocations = VK_FALSE;
1427 break;
1428 }
1429 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES_KHR: {
1430 VkPhysicalDeviceDepthStencilResolvePropertiesKHR *properties =
1431 (VkPhysicalDeviceDepthStencilResolvePropertiesKHR *)ext;
1432
1433 /* We support all of the depth resolve modes */
1434 properties->supportedDepthResolveModes =
1435 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1436 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1437 VK_RESOLVE_MODE_MIN_BIT_KHR |
1438 VK_RESOLVE_MODE_MAX_BIT_KHR;
1439
1440 /* Average doesn't make sense for stencil so we don't support that */
1441 properties->supportedStencilResolveModes =
1442 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1443 VK_RESOLVE_MODE_MIN_BIT_KHR |
1444 VK_RESOLVE_MODE_MAX_BIT_KHR;
1445
1446 properties->independentResolveNone = VK_TRUE;
1447 properties->independentResolve = VK_TRUE;
1448 break;
1449 }
1450 default:
1451 break;
1452 }
1453 }
1454 }
1455
1456 static void radv_get_physical_device_queue_family_properties(
1457 struct radv_physical_device* pdevice,
1458 uint32_t* pCount,
1459 VkQueueFamilyProperties** pQueueFamilyProperties)
1460 {
1461 int num_queue_families = 1;
1462 int idx;
1463 if (pdevice->rad_info.num_compute_rings > 0 &&
1464 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1465 num_queue_families++;
1466
1467 if (pQueueFamilyProperties == NULL) {
1468 *pCount = num_queue_families;
1469 return;
1470 }
1471
1472 if (!*pCount)
1473 return;
1474
1475 idx = 0;
1476 if (*pCount >= 1) {
1477 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1478 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1479 VK_QUEUE_COMPUTE_BIT |
1480 VK_QUEUE_TRANSFER_BIT |
1481 VK_QUEUE_SPARSE_BINDING_BIT,
1482 .queueCount = 1,
1483 .timestampValidBits = 64,
1484 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1485 };
1486 idx++;
1487 }
1488
1489 if (pdevice->rad_info.num_compute_rings > 0 &&
1490 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1491 if (*pCount > idx) {
1492 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1493 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1494 VK_QUEUE_TRANSFER_BIT |
1495 VK_QUEUE_SPARSE_BINDING_BIT,
1496 .queueCount = pdevice->rad_info.num_compute_rings,
1497 .timestampValidBits = 64,
1498 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1499 };
1500 idx++;
1501 }
1502 }
1503 *pCount = idx;
1504 }
1505
1506 void radv_GetPhysicalDeviceQueueFamilyProperties(
1507 VkPhysicalDevice physicalDevice,
1508 uint32_t* pCount,
1509 VkQueueFamilyProperties* pQueueFamilyProperties)
1510 {
1511 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1512 if (!pQueueFamilyProperties) {
1513 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1514 return;
1515 }
1516 VkQueueFamilyProperties *properties[] = {
1517 pQueueFamilyProperties + 0,
1518 pQueueFamilyProperties + 1,
1519 pQueueFamilyProperties + 2,
1520 };
1521 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1522 assert(*pCount <= 3);
1523 }
1524
1525 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1526 VkPhysicalDevice physicalDevice,
1527 uint32_t* pCount,
1528 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1529 {
1530 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1531 if (!pQueueFamilyProperties) {
1532 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1533 return;
1534 }
1535 VkQueueFamilyProperties *properties[] = {
1536 &pQueueFamilyProperties[0].queueFamilyProperties,
1537 &pQueueFamilyProperties[1].queueFamilyProperties,
1538 &pQueueFamilyProperties[2].queueFamilyProperties,
1539 };
1540 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1541 assert(*pCount <= 3);
1542 }
1543
1544 void radv_GetPhysicalDeviceMemoryProperties(
1545 VkPhysicalDevice physicalDevice,
1546 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1547 {
1548 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1549
1550 *pMemoryProperties = physical_device->memory_properties;
1551 }
1552
1553 static void
1554 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1555 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1556 {
1557 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1558 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1559 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1560 uint64_t vram_size = radv_get_vram_size(device);
1561 uint64_t gtt_size = device->rad_info.gart_size;
1562 uint64_t heap_budget, heap_usage;
1563
1564 /* For all memory heaps, the computation of budget is as follow:
1565 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1566 *
1567 * The Vulkan spec 1.1.97 says that the budget should include any
1568 * currently allocated device memory.
1569 *
1570 * Note that the application heap usages are not really accurate (eg.
1571 * in presence of shared buffers).
1572 */
1573 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
1574 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
1575
1576 switch (device->mem_type_indices[i]) {
1577 case RADV_MEM_TYPE_VRAM:
1578 heap_usage = device->ws->query_value(device->ws,
1579 RADEON_ALLOCATED_VRAM);
1580
1581 heap_budget = vram_size -
1582 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1583 heap_usage;
1584
1585 memoryBudget->heapBudget[heap_index] = heap_budget;
1586 memoryBudget->heapUsage[heap_index] = heap_usage;
1587 break;
1588 case RADV_MEM_TYPE_VRAM_CPU_ACCESS:
1589 heap_usage = device->ws->query_value(device->ws,
1590 RADEON_ALLOCATED_VRAM_VIS);
1591
1592 heap_budget = visible_vram_size -
1593 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1594 heap_usage;
1595
1596 memoryBudget->heapBudget[heap_index] = heap_budget;
1597 memoryBudget->heapUsage[heap_index] = heap_usage;
1598 break;
1599 case RADV_MEM_TYPE_GTT_WRITE_COMBINE:
1600 heap_usage = device->ws->query_value(device->ws,
1601 RADEON_ALLOCATED_GTT);
1602
1603 heap_budget = gtt_size -
1604 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1605 heap_usage;
1606
1607 memoryBudget->heapBudget[heap_index] = heap_budget;
1608 memoryBudget->heapUsage[heap_index] = heap_usage;
1609 break;
1610 default:
1611 break;
1612 }
1613 }
1614
1615 /* The heapBudget and heapUsage values must be zero for array elements
1616 * greater than or equal to
1617 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1618 */
1619 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1620 memoryBudget->heapBudget[i] = 0;
1621 memoryBudget->heapUsage[i] = 0;
1622 }
1623 }
1624
1625 void radv_GetPhysicalDeviceMemoryProperties2(
1626 VkPhysicalDevice physicalDevice,
1627 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1628 {
1629 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1630 &pMemoryProperties->memoryProperties);
1631
1632 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1633 vk_find_struct(pMemoryProperties->pNext,
1634 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1635 if (memory_budget)
1636 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1637 }
1638
1639 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1640 VkDevice _device,
1641 VkExternalMemoryHandleTypeFlagBits handleType,
1642 const void *pHostPointer,
1643 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1644 {
1645 RADV_FROM_HANDLE(radv_device, device, _device);
1646
1647 switch (handleType)
1648 {
1649 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1650 const struct radv_physical_device *physical_device = device->physical_device;
1651 uint32_t memoryTypeBits = 0;
1652 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1653 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1654 memoryTypeBits = (1 << i);
1655 break;
1656 }
1657 }
1658 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1659 return VK_SUCCESS;
1660 }
1661 default:
1662 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1663 }
1664 }
1665
1666 static enum radeon_ctx_priority
1667 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1668 {
1669 /* Default to MEDIUM when a specific global priority isn't requested */
1670 if (!pObj)
1671 return RADEON_CTX_PRIORITY_MEDIUM;
1672
1673 switch(pObj->globalPriority) {
1674 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1675 return RADEON_CTX_PRIORITY_REALTIME;
1676 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1677 return RADEON_CTX_PRIORITY_HIGH;
1678 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1679 return RADEON_CTX_PRIORITY_MEDIUM;
1680 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1681 return RADEON_CTX_PRIORITY_LOW;
1682 default:
1683 unreachable("Illegal global priority value");
1684 return RADEON_CTX_PRIORITY_INVALID;
1685 }
1686 }
1687
1688 static int
1689 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1690 uint32_t queue_family_index, int idx,
1691 VkDeviceQueueCreateFlags flags,
1692 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1693 {
1694 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1695 queue->device = device;
1696 queue->queue_family_index = queue_family_index;
1697 queue->queue_idx = idx;
1698 queue->priority = radv_get_queue_global_priority(global_priority);
1699 queue->flags = flags;
1700
1701 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1702 if (!queue->hw_ctx)
1703 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1704
1705 return VK_SUCCESS;
1706 }
1707
1708 static void
1709 radv_queue_finish(struct radv_queue *queue)
1710 {
1711 if (queue->hw_ctx)
1712 queue->device->ws->ctx_destroy(queue->hw_ctx);
1713
1714 if (queue->initial_full_flush_preamble_cs)
1715 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1716 if (queue->initial_preamble_cs)
1717 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1718 if (queue->continue_preamble_cs)
1719 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1720 if (queue->descriptor_bo)
1721 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1722 if (queue->scratch_bo)
1723 queue->device->ws->buffer_destroy(queue->scratch_bo);
1724 if (queue->esgs_ring_bo)
1725 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1726 if (queue->gsvs_ring_bo)
1727 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1728 if (queue->tess_rings_bo)
1729 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1730 if (queue->compute_scratch_bo)
1731 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1732 }
1733
1734 static void
1735 radv_bo_list_init(struct radv_bo_list *bo_list)
1736 {
1737 pthread_mutex_init(&bo_list->mutex, NULL);
1738 bo_list->list.count = bo_list->capacity = 0;
1739 bo_list->list.bos = NULL;
1740 }
1741
1742 static void
1743 radv_bo_list_finish(struct radv_bo_list *bo_list)
1744 {
1745 free(bo_list->list.bos);
1746 pthread_mutex_destroy(&bo_list->mutex);
1747 }
1748
1749 static VkResult radv_bo_list_add(struct radv_device *device,
1750 struct radeon_winsys_bo *bo)
1751 {
1752 struct radv_bo_list *bo_list = &device->bo_list;
1753
1754 if (bo->is_local)
1755 return VK_SUCCESS;
1756
1757 if (unlikely(!device->use_global_bo_list))
1758 return VK_SUCCESS;
1759
1760 pthread_mutex_lock(&bo_list->mutex);
1761 if (bo_list->list.count == bo_list->capacity) {
1762 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1763 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1764
1765 if (!data) {
1766 pthread_mutex_unlock(&bo_list->mutex);
1767 return VK_ERROR_OUT_OF_HOST_MEMORY;
1768 }
1769
1770 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1771 bo_list->capacity = capacity;
1772 }
1773
1774 bo_list->list.bos[bo_list->list.count++] = bo;
1775 pthread_mutex_unlock(&bo_list->mutex);
1776 return VK_SUCCESS;
1777 }
1778
1779 static void radv_bo_list_remove(struct radv_device *device,
1780 struct radeon_winsys_bo *bo)
1781 {
1782 struct radv_bo_list *bo_list = &device->bo_list;
1783
1784 if (bo->is_local)
1785 return;
1786
1787 if (unlikely(!device->use_global_bo_list))
1788 return;
1789
1790 pthread_mutex_lock(&bo_list->mutex);
1791 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1792 if (bo_list->list.bos[i] == bo) {
1793 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1794 --bo_list->list.count;
1795 break;
1796 }
1797 }
1798 pthread_mutex_unlock(&bo_list->mutex);
1799 }
1800
1801 static void
1802 radv_device_init_gs_info(struct radv_device *device)
1803 {
1804 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1805 device->physical_device->rad_info.family);
1806 }
1807
1808 static int radv_get_device_extension_index(const char *name)
1809 {
1810 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1811 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1812 return i;
1813 }
1814 return -1;
1815 }
1816
1817 static int
1818 radv_get_int_debug_option(const char *name, int default_value)
1819 {
1820 const char *str;
1821 int result;
1822
1823 str = getenv(name);
1824 if (!str) {
1825 result = default_value;
1826 } else {
1827 char *endptr;
1828
1829 result = strtol(str, &endptr, 0);
1830 if (str == endptr) {
1831 /* No digits founs. */
1832 result = default_value;
1833 }
1834 }
1835
1836 return result;
1837 }
1838
1839 VkResult radv_CreateDevice(
1840 VkPhysicalDevice physicalDevice,
1841 const VkDeviceCreateInfo* pCreateInfo,
1842 const VkAllocationCallbacks* pAllocator,
1843 VkDevice* pDevice)
1844 {
1845 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1846 VkResult result;
1847 struct radv_device *device;
1848
1849 bool keep_shader_info = false;
1850
1851 /* Check enabled features */
1852 if (pCreateInfo->pEnabledFeatures) {
1853 VkPhysicalDeviceFeatures supported_features;
1854 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1855 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1856 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1857 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1858 for (uint32_t i = 0; i < num_features; i++) {
1859 if (enabled_feature[i] && !supported_feature[i])
1860 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1861 }
1862 }
1863
1864 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1865 sizeof(*device), 8,
1866 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1867 if (!device)
1868 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1869
1870 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1871 device->instance = physical_device->instance;
1872 device->physical_device = physical_device;
1873
1874 device->ws = physical_device->ws;
1875 if (pAllocator)
1876 device->alloc = *pAllocator;
1877 else
1878 device->alloc = physical_device->instance->alloc;
1879
1880 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1881 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1882 int index = radv_get_device_extension_index(ext_name);
1883 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1884 vk_free(&device->alloc, device);
1885 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1886 }
1887
1888 device->enabled_extensions.extensions[index] = true;
1889 }
1890
1891 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1892
1893 /* With update after bind we can't attach bo's to the command buffer
1894 * from the descriptor set anymore, so we have to use a global BO list.
1895 */
1896 device->use_global_bo_list =
1897 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
1898 device->enabled_extensions.EXT_descriptor_indexing ||
1899 device->enabled_extensions.EXT_buffer_device_address;
1900
1901 device->robust_buffer_access = pCreateInfo->pEnabledFeatures &&
1902 pCreateInfo->pEnabledFeatures->robustBufferAccess;
1903
1904 mtx_init(&device->shader_slab_mutex, mtx_plain);
1905 list_inithead(&device->shader_slabs);
1906
1907 radv_bo_list_init(&device->bo_list);
1908
1909 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1910 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1911 uint32_t qfi = queue_create->queueFamilyIndex;
1912 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1913 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1914
1915 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1916
1917 device->queues[qfi] = vk_alloc(&device->alloc,
1918 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1919 if (!device->queues[qfi]) {
1920 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1921 goto fail;
1922 }
1923
1924 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1925
1926 device->queue_count[qfi] = queue_create->queueCount;
1927
1928 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1929 result = radv_queue_init(device, &device->queues[qfi][q],
1930 qfi, q, queue_create->flags,
1931 global_priority);
1932 if (result != VK_SUCCESS)
1933 goto fail;
1934 }
1935 }
1936
1937 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1938 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1939
1940 /* Disabled and not implemented for now. */
1941 device->dfsm_allowed = device->pbb_allowed &&
1942 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1943 device->physical_device->rad_info.family == CHIP_RAVEN2);
1944
1945 #ifdef ANDROID
1946 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1947 #endif
1948
1949 /* The maximum number of scratch waves. Scratch space isn't divided
1950 * evenly between CUs. The number is only a function of the number of CUs.
1951 * We can decrease the constant to decrease the scratch buffer size.
1952 *
1953 * sctx->scratch_waves must be >= the maximum possible size of
1954 * 1 threadgroup, so that the hw doesn't hang from being unable
1955 * to start any.
1956 *
1957 * The recommended value is 4 per CU at most. Higher numbers don't
1958 * bring much benefit, but they still occupy chip resources (think
1959 * async compute). I've seen ~2% performance difference between 4 and 32.
1960 */
1961 uint32_t max_threads_per_block = 2048;
1962 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1963 max_threads_per_block / 64);
1964
1965 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) |
1966 S_00B800_CS_W32_EN(device->physical_device->cs_wave_size == 32);
1967
1968 if (device->physical_device->rad_info.chip_class >= GFX7) {
1969 /* If the KMD allows it (there is a KMD hw register for it),
1970 * allow launching waves out-of-order.
1971 */
1972 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1973 }
1974
1975 radv_device_init_gs_info(device);
1976
1977 device->tess_offchip_block_dw_size =
1978 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1979 device->has_distributed_tess =
1980 device->physical_device->rad_info.chip_class >= GFX8 &&
1981 device->physical_device->rad_info.max_se >= 2;
1982
1983 if (getenv("RADV_TRACE_FILE")) {
1984 const char *filename = getenv("RADV_TRACE_FILE");
1985
1986 keep_shader_info = true;
1987
1988 if (!radv_init_trace(device))
1989 goto fail;
1990
1991 fprintf(stderr, "*****************************************************************************\n");
1992 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1993 fprintf(stderr, "*****************************************************************************\n");
1994
1995 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1996 radv_dump_enabled_options(device, stderr);
1997 }
1998
1999 device->keep_shader_info = keep_shader_info;
2000
2001 result = radv_device_init_meta(device);
2002 if (result != VK_SUCCESS)
2003 goto fail;
2004
2005 radv_device_init_msaa(device);
2006
2007 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
2008 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
2009 switch (family) {
2010 case RADV_QUEUE_GENERAL:
2011 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2012 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
2013 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
2014 break;
2015 case RADV_QUEUE_COMPUTE:
2016 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
2017 radeon_emit(device->empty_cs[family], 0);
2018 break;
2019 }
2020 device->ws->cs_finalize(device->empty_cs[family]);
2021 }
2022
2023 if (device->physical_device->rad_info.chip_class >= GFX7)
2024 cik_create_gfx_config(device);
2025
2026 VkPipelineCacheCreateInfo ci;
2027 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
2028 ci.pNext = NULL;
2029 ci.flags = 0;
2030 ci.pInitialData = NULL;
2031 ci.initialDataSize = 0;
2032 VkPipelineCache pc;
2033 result = radv_CreatePipelineCache(radv_device_to_handle(device),
2034 &ci, NULL, &pc);
2035 if (result != VK_SUCCESS)
2036 goto fail_meta;
2037
2038 device->mem_cache = radv_pipeline_cache_from_handle(pc);
2039
2040 device->force_aniso =
2041 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2042 if (device->force_aniso >= 0) {
2043 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
2044 1 << util_logbase2(device->force_aniso));
2045 }
2046
2047 *pDevice = radv_device_to_handle(device);
2048 return VK_SUCCESS;
2049
2050 fail_meta:
2051 radv_device_finish_meta(device);
2052 fail:
2053 radv_bo_list_finish(&device->bo_list);
2054
2055 if (device->trace_bo)
2056 device->ws->buffer_destroy(device->trace_bo);
2057
2058 if (device->gfx_init)
2059 device->ws->buffer_destroy(device->gfx_init);
2060
2061 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2062 for (unsigned q = 0; q < device->queue_count[i]; q++)
2063 radv_queue_finish(&device->queues[i][q]);
2064 if (device->queue_count[i])
2065 vk_free(&device->alloc, device->queues[i]);
2066 }
2067
2068 vk_free(&device->alloc, device);
2069 return result;
2070 }
2071
2072 void radv_DestroyDevice(
2073 VkDevice _device,
2074 const VkAllocationCallbacks* pAllocator)
2075 {
2076 RADV_FROM_HANDLE(radv_device, device, _device);
2077
2078 if (!device)
2079 return;
2080
2081 if (device->trace_bo)
2082 device->ws->buffer_destroy(device->trace_bo);
2083
2084 if (device->gfx_init)
2085 device->ws->buffer_destroy(device->gfx_init);
2086
2087 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2088 for (unsigned q = 0; q < device->queue_count[i]; q++)
2089 radv_queue_finish(&device->queues[i][q]);
2090 if (device->queue_count[i])
2091 vk_free(&device->alloc, device->queues[i]);
2092 if (device->empty_cs[i])
2093 device->ws->cs_destroy(device->empty_cs[i]);
2094 }
2095 radv_device_finish_meta(device);
2096
2097 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2098 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2099
2100 radv_destroy_shader_slabs(device);
2101
2102 radv_bo_list_finish(&device->bo_list);
2103 vk_free(&device->alloc, device);
2104 }
2105
2106 VkResult radv_EnumerateInstanceLayerProperties(
2107 uint32_t* pPropertyCount,
2108 VkLayerProperties* pProperties)
2109 {
2110 if (pProperties == NULL) {
2111 *pPropertyCount = 0;
2112 return VK_SUCCESS;
2113 }
2114
2115 /* None supported at this time */
2116 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2117 }
2118
2119 VkResult radv_EnumerateDeviceLayerProperties(
2120 VkPhysicalDevice physicalDevice,
2121 uint32_t* pPropertyCount,
2122 VkLayerProperties* pProperties)
2123 {
2124 if (pProperties == NULL) {
2125 *pPropertyCount = 0;
2126 return VK_SUCCESS;
2127 }
2128
2129 /* None supported at this time */
2130 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2131 }
2132
2133 void radv_GetDeviceQueue2(
2134 VkDevice _device,
2135 const VkDeviceQueueInfo2* pQueueInfo,
2136 VkQueue* pQueue)
2137 {
2138 RADV_FROM_HANDLE(radv_device, device, _device);
2139 struct radv_queue *queue;
2140
2141 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2142 if (pQueueInfo->flags != queue->flags) {
2143 /* From the Vulkan 1.1.70 spec:
2144 *
2145 * "The queue returned by vkGetDeviceQueue2 must have the same
2146 * flags value from this structure as that used at device
2147 * creation time in a VkDeviceQueueCreateInfo instance. If no
2148 * matching flags were specified at device creation time then
2149 * pQueue will return VK_NULL_HANDLE."
2150 */
2151 *pQueue = VK_NULL_HANDLE;
2152 return;
2153 }
2154
2155 *pQueue = radv_queue_to_handle(queue);
2156 }
2157
2158 void radv_GetDeviceQueue(
2159 VkDevice _device,
2160 uint32_t queueFamilyIndex,
2161 uint32_t queueIndex,
2162 VkQueue* pQueue)
2163 {
2164 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2165 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2166 .queueFamilyIndex = queueFamilyIndex,
2167 .queueIndex = queueIndex
2168 };
2169
2170 radv_GetDeviceQueue2(_device, &info, pQueue);
2171 }
2172
2173 static void
2174 fill_geom_tess_rings(struct radv_queue *queue,
2175 uint32_t *map,
2176 bool add_sample_positions,
2177 uint32_t esgs_ring_size,
2178 struct radeon_winsys_bo *esgs_ring_bo,
2179 uint32_t gsvs_ring_size,
2180 struct radeon_winsys_bo *gsvs_ring_bo,
2181 uint32_t tess_factor_ring_size,
2182 uint32_t tess_offchip_ring_offset,
2183 uint32_t tess_offchip_ring_size,
2184 struct radeon_winsys_bo *tess_rings_bo)
2185 {
2186 uint32_t *desc = &map[4];
2187
2188 if (esgs_ring_bo) {
2189 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2190
2191 /* stride 0, num records - size, add tid, swizzle, elsize4,
2192 index stride 64 */
2193 desc[0] = esgs_va;
2194 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2195 S_008F04_SWIZZLE_ENABLE(true);
2196 desc[2] = esgs_ring_size;
2197 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2198 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2199 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2200 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2201 S_008F0C_INDEX_STRIDE(3) |
2202 S_008F0C_ADD_TID_ENABLE(1);
2203
2204 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2205 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2206 S_008F0C_OOB_SELECT(2) |
2207 S_008F0C_RESOURCE_LEVEL(1);
2208 } else {
2209 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2210 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2211 S_008F0C_ELEMENT_SIZE(1);
2212 }
2213
2214 /* GS entry for ES->GS ring */
2215 /* stride 0, num records - size, elsize0,
2216 index stride 0 */
2217 desc[4] = esgs_va;
2218 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32);
2219 desc[6] = esgs_ring_size;
2220 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2221 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2222 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2223 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2224
2225 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2226 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2227 S_008F0C_OOB_SELECT(2) |
2228 S_008F0C_RESOURCE_LEVEL(1);
2229 } else {
2230 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2231 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2232 }
2233 }
2234
2235 desc += 8;
2236
2237 if (gsvs_ring_bo) {
2238 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2239
2240 /* VS entry for GS->VS ring */
2241 /* stride 0, num records - size, elsize0,
2242 index stride 0 */
2243 desc[0] = gsvs_va;
2244 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32);
2245 desc[2] = gsvs_ring_size;
2246 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2247 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2248 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2249 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2250
2251 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2252 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2253 S_008F0C_OOB_SELECT(2) |
2254 S_008F0C_RESOURCE_LEVEL(1);
2255 } else {
2256 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2257 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2258 }
2259
2260 /* stride gsvs_itemsize, num records 64
2261 elsize 4, index stride 16 */
2262 /* shader will patch stride and desc[2] */
2263 desc[4] = gsvs_va;
2264 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32) |
2265 S_008F04_SWIZZLE_ENABLE(1);
2266 desc[6] = 0;
2267 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2268 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2269 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2270 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2271 S_008F0C_INDEX_STRIDE(1) |
2272 S_008F0C_ADD_TID_ENABLE(true);
2273
2274 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2275 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2276 S_008F0C_OOB_SELECT(2) |
2277 S_008F0C_RESOURCE_LEVEL(1);
2278 } else {
2279 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2280 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2281 S_008F0C_ELEMENT_SIZE(1);
2282 }
2283
2284 }
2285
2286 desc += 8;
2287
2288 if (tess_rings_bo) {
2289 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2290 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2291
2292 desc[0] = tess_va;
2293 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32);
2294 desc[2] = tess_factor_ring_size;
2295 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2296 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2297 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2298 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2299
2300 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2301 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2302 S_008F0C_OOB_SELECT(3) |
2303 S_008F0C_RESOURCE_LEVEL(1);
2304 } else {
2305 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2306 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2307 }
2308
2309 desc[4] = tess_offchip_va;
2310 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32);
2311 desc[6] = tess_offchip_ring_size;
2312 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2313 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2314 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2315 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2316
2317 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2318 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2319 S_008F0C_OOB_SELECT(3) |
2320 S_008F0C_RESOURCE_LEVEL(1);
2321 } else {
2322 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2323 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2324 }
2325 }
2326
2327 desc += 8;
2328
2329 if (add_sample_positions) {
2330 /* add sample positions after all rings */
2331 memcpy(desc, queue->device->sample_locations_1x, 8);
2332 desc += 2;
2333 memcpy(desc, queue->device->sample_locations_2x, 16);
2334 desc += 4;
2335 memcpy(desc, queue->device->sample_locations_4x, 32);
2336 desc += 8;
2337 memcpy(desc, queue->device->sample_locations_8x, 64);
2338 }
2339 }
2340
2341 static unsigned
2342 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2343 {
2344 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
2345 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2346 device->physical_device->rad_info.family != CHIP_STONEY;
2347 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2348 unsigned max_offchip_buffers;
2349 unsigned offchip_granularity;
2350 unsigned hs_offchip_param;
2351
2352 /*
2353 * Per RadeonSI:
2354 * This must be one less than the maximum number due to a hw limitation.
2355 * Various hardware bugs need thGFX7
2356 *
2357 * Per AMDVLK:
2358 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2359 * Gfx7 should limit max_offchip_buffers to 508
2360 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2361 *
2362 * Follow AMDVLK here.
2363 */
2364 if (device->physical_device->rad_info.chip_class >= GFX10) {
2365 max_offchip_buffers_per_se = 256;
2366 } else if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2367 device->physical_device->rad_info.chip_class == GFX7 ||
2368 device->physical_device->rad_info.chip_class == GFX6)
2369 --max_offchip_buffers_per_se;
2370
2371 max_offchip_buffers = max_offchip_buffers_per_se *
2372 device->physical_device->rad_info.max_se;
2373
2374 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2375 * around by setting 4K granularity.
2376 */
2377 if (device->tess_offchip_block_dw_size == 4096) {
2378 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2379 offchip_granularity = V_03093C_X_4K_DWORDS;
2380 } else {
2381 assert(device->tess_offchip_block_dw_size == 8192);
2382 offchip_granularity = V_03093C_X_8K_DWORDS;
2383 }
2384
2385 switch (device->physical_device->rad_info.chip_class) {
2386 case GFX6:
2387 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2388 break;
2389 case GFX7:
2390 case GFX8:
2391 case GFX9:
2392 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2393 break;
2394 case GFX10:
2395 break;
2396 default:
2397 break;
2398 }
2399
2400 *max_offchip_buffers_p = max_offchip_buffers;
2401 if (device->physical_device->rad_info.chip_class >= GFX7) {
2402 if (device->physical_device->rad_info.chip_class >= GFX8)
2403 --max_offchip_buffers;
2404 hs_offchip_param =
2405 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2406 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2407 } else {
2408 hs_offchip_param =
2409 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2410 }
2411 return hs_offchip_param;
2412 }
2413
2414 static void
2415 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2416 struct radeon_winsys_bo *esgs_ring_bo,
2417 uint32_t esgs_ring_size,
2418 struct radeon_winsys_bo *gsvs_ring_bo,
2419 uint32_t gsvs_ring_size)
2420 {
2421 if (!esgs_ring_bo && !gsvs_ring_bo)
2422 return;
2423
2424 if (esgs_ring_bo)
2425 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2426
2427 if (gsvs_ring_bo)
2428 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2429
2430 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2431 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2432 radeon_emit(cs, esgs_ring_size >> 8);
2433 radeon_emit(cs, gsvs_ring_size >> 8);
2434 } else {
2435 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2436 radeon_emit(cs, esgs_ring_size >> 8);
2437 radeon_emit(cs, gsvs_ring_size >> 8);
2438 }
2439 }
2440
2441 static void
2442 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2443 unsigned hs_offchip_param, unsigned tf_ring_size,
2444 struct radeon_winsys_bo *tess_rings_bo)
2445 {
2446 uint64_t tf_va;
2447
2448 if (!tess_rings_bo)
2449 return;
2450
2451 tf_va = radv_buffer_get_va(tess_rings_bo);
2452
2453 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2454
2455 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2456 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2457 S_030938_SIZE(tf_ring_size / 4));
2458 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2459 tf_va >> 8);
2460
2461 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2462 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
2463 S_030984_BASE_HI(tf_va >> 40));
2464 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
2465 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2466 S_030944_BASE_HI(tf_va >> 40));
2467 }
2468 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2469 hs_offchip_param);
2470 } else {
2471 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2472 S_008988_SIZE(tf_ring_size / 4));
2473 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2474 tf_va >> 8);
2475 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2476 hs_offchip_param);
2477 }
2478 }
2479
2480 static void
2481 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2482 struct radeon_winsys_bo *compute_scratch_bo)
2483 {
2484 uint64_t scratch_va;
2485
2486 if (!compute_scratch_bo)
2487 return;
2488
2489 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2490
2491 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2492
2493 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2494 radeon_emit(cs, scratch_va);
2495 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2496 S_008F04_SWIZZLE_ENABLE(1));
2497 }
2498
2499 static void
2500 radv_emit_global_shader_pointers(struct radv_queue *queue,
2501 struct radeon_cmdbuf *cs,
2502 struct radeon_winsys_bo *descriptor_bo)
2503 {
2504 uint64_t va;
2505
2506 if (!descriptor_bo)
2507 return;
2508
2509 va = radv_buffer_get_va(descriptor_bo);
2510
2511 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2512
2513 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2514 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2515 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2516 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2517 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2518
2519 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2520 radv_emit_shader_pointer(queue->device, cs, regs[i],
2521 va, true);
2522 }
2523 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
2524 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2525 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2526 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2527 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2528
2529 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2530 radv_emit_shader_pointer(queue->device, cs, regs[i],
2531 va, true);
2532 }
2533 } else {
2534 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2535 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2536 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2537 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2538 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2539 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2540
2541 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2542 radv_emit_shader_pointer(queue->device, cs, regs[i],
2543 va, true);
2544 }
2545 }
2546 }
2547
2548 static void
2549 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2550 {
2551 struct radv_device *device = queue->device;
2552
2553 if (device->gfx_init) {
2554 uint64_t va = radv_buffer_get_va(device->gfx_init);
2555
2556 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2557 radeon_emit(cs, va);
2558 radeon_emit(cs, va >> 32);
2559 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2560
2561 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2562 } else {
2563 struct radv_physical_device *physical_device = device->physical_device;
2564 si_emit_graphics(physical_device, cs);
2565 }
2566 }
2567
2568 static void
2569 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2570 {
2571 struct radv_physical_device *physical_device = queue->device->physical_device;
2572 si_emit_compute(physical_device, cs);
2573 }
2574
2575 static VkResult
2576 radv_get_preamble_cs(struct radv_queue *queue,
2577 uint32_t scratch_size,
2578 uint32_t compute_scratch_size,
2579 uint32_t esgs_ring_size,
2580 uint32_t gsvs_ring_size,
2581 bool needs_tess_rings,
2582 bool needs_sample_positions,
2583 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2584 struct radeon_cmdbuf **initial_preamble_cs,
2585 struct radeon_cmdbuf **continue_preamble_cs)
2586 {
2587 struct radeon_winsys_bo *scratch_bo = NULL;
2588 struct radeon_winsys_bo *descriptor_bo = NULL;
2589 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2590 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2591 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2592 struct radeon_winsys_bo *tess_rings_bo = NULL;
2593 struct radeon_cmdbuf *dest_cs[3] = {0};
2594 bool add_tess_rings = false, add_sample_positions = false;
2595 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2596 unsigned max_offchip_buffers;
2597 unsigned hs_offchip_param = 0;
2598 unsigned tess_offchip_ring_offset;
2599 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2600 if (!queue->has_tess_rings) {
2601 if (needs_tess_rings)
2602 add_tess_rings = true;
2603 }
2604 if (!queue->has_sample_positions) {
2605 if (needs_sample_positions)
2606 add_sample_positions = true;
2607 }
2608 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2609 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2610 &max_offchip_buffers);
2611 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2612 tess_offchip_ring_size = max_offchip_buffers *
2613 queue->device->tess_offchip_block_dw_size * 4;
2614
2615 if (scratch_size <= queue->scratch_size &&
2616 compute_scratch_size <= queue->compute_scratch_size &&
2617 esgs_ring_size <= queue->esgs_ring_size &&
2618 gsvs_ring_size <= queue->gsvs_ring_size &&
2619 !add_tess_rings && !add_sample_positions &&
2620 queue->initial_preamble_cs) {
2621 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2622 *initial_preamble_cs = queue->initial_preamble_cs;
2623 *continue_preamble_cs = queue->continue_preamble_cs;
2624 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2625 *continue_preamble_cs = NULL;
2626 return VK_SUCCESS;
2627 }
2628
2629 if (scratch_size > queue->scratch_size) {
2630 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2631 scratch_size,
2632 4096,
2633 RADEON_DOMAIN_VRAM,
2634 ring_bo_flags,
2635 RADV_BO_PRIORITY_SCRATCH);
2636 if (!scratch_bo)
2637 goto fail;
2638 } else
2639 scratch_bo = queue->scratch_bo;
2640
2641 if (compute_scratch_size > queue->compute_scratch_size) {
2642 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2643 compute_scratch_size,
2644 4096,
2645 RADEON_DOMAIN_VRAM,
2646 ring_bo_flags,
2647 RADV_BO_PRIORITY_SCRATCH);
2648 if (!compute_scratch_bo)
2649 goto fail;
2650
2651 } else
2652 compute_scratch_bo = queue->compute_scratch_bo;
2653
2654 if (esgs_ring_size > queue->esgs_ring_size) {
2655 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2656 esgs_ring_size,
2657 4096,
2658 RADEON_DOMAIN_VRAM,
2659 ring_bo_flags,
2660 RADV_BO_PRIORITY_SCRATCH);
2661 if (!esgs_ring_bo)
2662 goto fail;
2663 } else {
2664 esgs_ring_bo = queue->esgs_ring_bo;
2665 esgs_ring_size = queue->esgs_ring_size;
2666 }
2667
2668 if (gsvs_ring_size > queue->gsvs_ring_size) {
2669 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2670 gsvs_ring_size,
2671 4096,
2672 RADEON_DOMAIN_VRAM,
2673 ring_bo_flags,
2674 RADV_BO_PRIORITY_SCRATCH);
2675 if (!gsvs_ring_bo)
2676 goto fail;
2677 } else {
2678 gsvs_ring_bo = queue->gsvs_ring_bo;
2679 gsvs_ring_size = queue->gsvs_ring_size;
2680 }
2681
2682 if (add_tess_rings) {
2683 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2684 tess_offchip_ring_offset + tess_offchip_ring_size,
2685 256,
2686 RADEON_DOMAIN_VRAM,
2687 ring_bo_flags,
2688 RADV_BO_PRIORITY_SCRATCH);
2689 if (!tess_rings_bo)
2690 goto fail;
2691 } else {
2692 tess_rings_bo = queue->tess_rings_bo;
2693 }
2694
2695 if (scratch_bo != queue->scratch_bo ||
2696 esgs_ring_bo != queue->esgs_ring_bo ||
2697 gsvs_ring_bo != queue->gsvs_ring_bo ||
2698 tess_rings_bo != queue->tess_rings_bo ||
2699 add_sample_positions) {
2700 uint32_t size = 0;
2701 if (gsvs_ring_bo || esgs_ring_bo ||
2702 tess_rings_bo || add_sample_positions) {
2703 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2704 if (add_sample_positions)
2705 size += 128; /* 64+32+16+8 = 120 bytes */
2706 }
2707 else if (scratch_bo)
2708 size = 8; /* 2 dword */
2709
2710 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2711 size,
2712 4096,
2713 RADEON_DOMAIN_VRAM,
2714 RADEON_FLAG_CPU_ACCESS |
2715 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2716 RADEON_FLAG_READ_ONLY,
2717 RADV_BO_PRIORITY_DESCRIPTOR);
2718 if (!descriptor_bo)
2719 goto fail;
2720 } else
2721 descriptor_bo = queue->descriptor_bo;
2722
2723 if (descriptor_bo != queue->descriptor_bo) {
2724 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2725
2726 if (scratch_bo) {
2727 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2728 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2729 S_008F04_SWIZZLE_ENABLE(1);
2730 map[0] = scratch_va;
2731 map[1] = rsrc1;
2732 }
2733
2734 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2735 fill_geom_tess_rings(queue, map, add_sample_positions,
2736 esgs_ring_size, esgs_ring_bo,
2737 gsvs_ring_size, gsvs_ring_bo,
2738 tess_factor_ring_size,
2739 tess_offchip_ring_offset,
2740 tess_offchip_ring_size,
2741 tess_rings_bo);
2742
2743 queue->device->ws->buffer_unmap(descriptor_bo);
2744 }
2745
2746 for(int i = 0; i < 3; ++i) {
2747 struct radeon_cmdbuf *cs = NULL;
2748 cs = queue->device->ws->cs_create(queue->device->ws,
2749 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2750 if (!cs)
2751 goto fail;
2752
2753 dest_cs[i] = cs;
2754
2755 if (scratch_bo)
2756 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2757
2758 /* Emit initial configuration. */
2759 switch (queue->queue_family_index) {
2760 case RADV_QUEUE_GENERAL:
2761 radv_init_graphics_state(cs, queue);
2762 break;
2763 case RADV_QUEUE_COMPUTE:
2764 radv_init_compute_state(cs, queue);
2765 break;
2766 case RADV_QUEUE_TRANSFER:
2767 break;
2768 }
2769
2770 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2771 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2772 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2773
2774 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2775 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2776 }
2777
2778 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2779 gsvs_ring_bo, gsvs_ring_size);
2780 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2781 tess_factor_ring_size, tess_rings_bo);
2782 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2783 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2784
2785 if (i == 0) {
2786 si_cs_emit_cache_flush(cs,
2787 queue->device->physical_device->rad_info.chip_class,
2788 NULL, 0,
2789 queue->queue_family_index == RING_COMPUTE &&
2790 queue->device->physical_device->rad_info.chip_class >= GFX7,
2791 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2792 RADV_CMD_FLAG_INV_ICACHE |
2793 RADV_CMD_FLAG_INV_SCACHE |
2794 RADV_CMD_FLAG_INV_VCACHE |
2795 RADV_CMD_FLAG_INV_L2 |
2796 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2797 } else if (i == 1) {
2798 si_cs_emit_cache_flush(cs,
2799 queue->device->physical_device->rad_info.chip_class,
2800 NULL, 0,
2801 queue->queue_family_index == RING_COMPUTE &&
2802 queue->device->physical_device->rad_info.chip_class >= GFX7,
2803 RADV_CMD_FLAG_INV_ICACHE |
2804 RADV_CMD_FLAG_INV_SCACHE |
2805 RADV_CMD_FLAG_INV_VCACHE |
2806 RADV_CMD_FLAG_INV_L2 |
2807 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2808 }
2809
2810 if (!queue->device->ws->cs_finalize(cs))
2811 goto fail;
2812 }
2813
2814 if (queue->initial_full_flush_preamble_cs)
2815 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2816
2817 if (queue->initial_preamble_cs)
2818 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2819
2820 if (queue->continue_preamble_cs)
2821 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2822
2823 queue->initial_full_flush_preamble_cs = dest_cs[0];
2824 queue->initial_preamble_cs = dest_cs[1];
2825 queue->continue_preamble_cs = dest_cs[2];
2826
2827 if (scratch_bo != queue->scratch_bo) {
2828 if (queue->scratch_bo)
2829 queue->device->ws->buffer_destroy(queue->scratch_bo);
2830 queue->scratch_bo = scratch_bo;
2831 queue->scratch_size = scratch_size;
2832 }
2833
2834 if (compute_scratch_bo != queue->compute_scratch_bo) {
2835 if (queue->compute_scratch_bo)
2836 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2837 queue->compute_scratch_bo = compute_scratch_bo;
2838 queue->compute_scratch_size = compute_scratch_size;
2839 }
2840
2841 if (esgs_ring_bo != queue->esgs_ring_bo) {
2842 if (queue->esgs_ring_bo)
2843 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2844 queue->esgs_ring_bo = esgs_ring_bo;
2845 queue->esgs_ring_size = esgs_ring_size;
2846 }
2847
2848 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2849 if (queue->gsvs_ring_bo)
2850 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2851 queue->gsvs_ring_bo = gsvs_ring_bo;
2852 queue->gsvs_ring_size = gsvs_ring_size;
2853 }
2854
2855 if (tess_rings_bo != queue->tess_rings_bo) {
2856 queue->tess_rings_bo = tess_rings_bo;
2857 queue->has_tess_rings = true;
2858 }
2859
2860 if (descriptor_bo != queue->descriptor_bo) {
2861 if (queue->descriptor_bo)
2862 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2863
2864 queue->descriptor_bo = descriptor_bo;
2865 }
2866
2867 if (add_sample_positions)
2868 queue->has_sample_positions = true;
2869
2870 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2871 *initial_preamble_cs = queue->initial_preamble_cs;
2872 *continue_preamble_cs = queue->continue_preamble_cs;
2873 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2874 *continue_preamble_cs = NULL;
2875 return VK_SUCCESS;
2876 fail:
2877 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2878 if (dest_cs[i])
2879 queue->device->ws->cs_destroy(dest_cs[i]);
2880 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2881 queue->device->ws->buffer_destroy(descriptor_bo);
2882 if (scratch_bo && scratch_bo != queue->scratch_bo)
2883 queue->device->ws->buffer_destroy(scratch_bo);
2884 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2885 queue->device->ws->buffer_destroy(compute_scratch_bo);
2886 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2887 queue->device->ws->buffer_destroy(esgs_ring_bo);
2888 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2889 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2890 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2891 queue->device->ws->buffer_destroy(tess_rings_bo);
2892 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2893 }
2894
2895 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2896 struct radv_winsys_sem_counts *counts,
2897 int num_sems,
2898 const VkSemaphore *sems,
2899 VkFence _fence,
2900 bool reset_temp)
2901 {
2902 int syncobj_idx = 0, sem_idx = 0;
2903
2904 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2905 return VK_SUCCESS;
2906
2907 for (uint32_t i = 0; i < num_sems; i++) {
2908 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2909
2910 if (sem->temp_syncobj || sem->syncobj)
2911 counts->syncobj_count++;
2912 else
2913 counts->sem_count++;
2914 }
2915
2916 if (_fence != VK_NULL_HANDLE) {
2917 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2918 if (fence->temp_syncobj || fence->syncobj)
2919 counts->syncobj_count++;
2920 }
2921
2922 if (counts->syncobj_count) {
2923 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2924 if (!counts->syncobj)
2925 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2926 }
2927
2928 if (counts->sem_count) {
2929 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2930 if (!counts->sem) {
2931 free(counts->syncobj);
2932 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2933 }
2934 }
2935
2936 for (uint32_t i = 0; i < num_sems; i++) {
2937 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2938
2939 if (sem->temp_syncobj) {
2940 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2941 }
2942 else if (sem->syncobj)
2943 counts->syncobj[syncobj_idx++] = sem->syncobj;
2944 else {
2945 assert(sem->sem);
2946 counts->sem[sem_idx++] = sem->sem;
2947 }
2948 }
2949
2950 if (_fence != VK_NULL_HANDLE) {
2951 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2952 if (fence->temp_syncobj)
2953 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2954 else if (fence->syncobj)
2955 counts->syncobj[syncobj_idx++] = fence->syncobj;
2956 }
2957
2958 return VK_SUCCESS;
2959 }
2960
2961 static void
2962 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2963 {
2964 free(sem_info->wait.syncobj);
2965 free(sem_info->wait.sem);
2966 free(sem_info->signal.syncobj);
2967 free(sem_info->signal.sem);
2968 }
2969
2970
2971 static void radv_free_temp_syncobjs(struct radv_device *device,
2972 int num_sems,
2973 const VkSemaphore *sems)
2974 {
2975 for (uint32_t i = 0; i < num_sems; i++) {
2976 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2977
2978 if (sem->temp_syncobj) {
2979 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2980 sem->temp_syncobj = 0;
2981 }
2982 }
2983 }
2984
2985 static VkResult
2986 radv_alloc_sem_info(struct radv_instance *instance,
2987 struct radv_winsys_sem_info *sem_info,
2988 int num_wait_sems,
2989 const VkSemaphore *wait_sems,
2990 int num_signal_sems,
2991 const VkSemaphore *signal_sems,
2992 VkFence fence)
2993 {
2994 VkResult ret;
2995 memset(sem_info, 0, sizeof(*sem_info));
2996
2997 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2998 if (ret)
2999 return ret;
3000 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
3001 if (ret)
3002 radv_free_sem_info(sem_info);
3003
3004 /* caller can override these */
3005 sem_info->cs_emit_wait = true;
3006 sem_info->cs_emit_signal = true;
3007 return ret;
3008 }
3009
3010 /* Signals fence as soon as all the work currently put on queue is done. */
3011 static VkResult radv_signal_fence(struct radv_queue *queue,
3012 struct radv_fence *fence)
3013 {
3014 int ret;
3015 VkResult result;
3016 struct radv_winsys_sem_info sem_info;
3017
3018 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
3019 radv_fence_to_handle(fence));
3020 if (result != VK_SUCCESS)
3021 return result;
3022
3023 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3024 &queue->device->empty_cs[queue->queue_family_index],
3025 1, NULL, NULL, &sem_info, NULL,
3026 false, fence->fence);
3027 radv_free_sem_info(&sem_info);
3028
3029 if (ret)
3030 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
3031
3032 return VK_SUCCESS;
3033 }
3034
3035 VkResult radv_QueueSubmit(
3036 VkQueue _queue,
3037 uint32_t submitCount,
3038 const VkSubmitInfo* pSubmits,
3039 VkFence _fence)
3040 {
3041 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3042 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3043 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3044 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
3045 int ret;
3046 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
3047 uint32_t scratch_size = 0;
3048 uint32_t compute_scratch_size = 0;
3049 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
3050 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
3051 VkResult result;
3052 bool fence_emitted = false;
3053 bool tess_rings_needed = false;
3054 bool sample_positions_needed = false;
3055
3056 /* Do this first so failing to allocate scratch buffers can't result in
3057 * partially executed submissions. */
3058 for (uint32_t i = 0; i < submitCount; i++) {
3059 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3060 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3061 pSubmits[i].pCommandBuffers[j]);
3062
3063 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
3064 compute_scratch_size = MAX2(compute_scratch_size,
3065 cmd_buffer->compute_scratch_size_needed);
3066 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
3067 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
3068 tess_rings_needed |= cmd_buffer->tess_rings_needed;
3069 sample_positions_needed |= cmd_buffer->sample_positions_needed;
3070 }
3071 }
3072
3073 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
3074 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
3075 sample_positions_needed, &initial_flush_preamble_cs,
3076 &initial_preamble_cs, &continue_preamble_cs);
3077 if (result != VK_SUCCESS)
3078 return result;
3079
3080 for (uint32_t i = 0; i < submitCount; i++) {
3081 struct radeon_cmdbuf **cs_array;
3082 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
3083 bool can_patch = true;
3084 uint32_t advance;
3085 struct radv_winsys_sem_info sem_info;
3086
3087 result = radv_alloc_sem_info(queue->device->instance,
3088 &sem_info,
3089 pSubmits[i].waitSemaphoreCount,
3090 pSubmits[i].pWaitSemaphores,
3091 pSubmits[i].signalSemaphoreCount,
3092 pSubmits[i].pSignalSemaphores,
3093 _fence);
3094 if (result != VK_SUCCESS)
3095 return result;
3096
3097 if (!pSubmits[i].commandBufferCount) {
3098 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
3099 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
3100 &queue->device->empty_cs[queue->queue_family_index],
3101 1, NULL, NULL,
3102 &sem_info, NULL,
3103 false, base_fence);
3104 if (ret) {
3105 radv_loge("failed to submit CS %d\n", i);
3106 abort();
3107 }
3108 fence_emitted = true;
3109 }
3110 radv_free_sem_info(&sem_info);
3111 continue;
3112 }
3113
3114 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
3115 (pSubmits[i].commandBufferCount));
3116
3117 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3118 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3119 pSubmits[i].pCommandBuffers[j]);
3120 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
3121
3122 cs_array[j] = cmd_buffer->cs;
3123 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
3124 can_patch = false;
3125
3126 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
3127 }
3128
3129 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
3130 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
3131 const struct radv_winsys_bo_list *bo_list = NULL;
3132
3133 advance = MIN2(max_cs_submission,
3134 pSubmits[i].commandBufferCount - j);
3135
3136 if (queue->device->trace_bo)
3137 *queue->device->trace_id_ptr = 0;
3138
3139 sem_info.cs_emit_wait = j == 0;
3140 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
3141
3142 if (unlikely(queue->device->use_global_bo_list)) {
3143 pthread_mutex_lock(&queue->device->bo_list.mutex);
3144 bo_list = &queue->device->bo_list.list;
3145 }
3146
3147 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
3148 advance, initial_preamble, continue_preamble_cs,
3149 &sem_info, bo_list,
3150 can_patch, base_fence);
3151
3152 if (unlikely(queue->device->use_global_bo_list))
3153 pthread_mutex_unlock(&queue->device->bo_list.mutex);
3154
3155 if (ret) {
3156 radv_loge("failed to submit CS %d\n", i);
3157 abort();
3158 }
3159 fence_emitted = true;
3160 if (queue->device->trace_bo) {
3161 radv_check_gpu_hangs(queue, cs_array[j]);
3162 }
3163 }
3164
3165 radv_free_temp_syncobjs(queue->device,
3166 pSubmits[i].waitSemaphoreCount,
3167 pSubmits[i].pWaitSemaphores);
3168 radv_free_sem_info(&sem_info);
3169 free(cs_array);
3170 }
3171
3172 if (fence) {
3173 if (!fence_emitted) {
3174 result = radv_signal_fence(queue, fence);
3175 if (result != VK_SUCCESS)
3176 return result;
3177 }
3178 }
3179
3180 return VK_SUCCESS;
3181 }
3182
3183 VkResult radv_QueueWaitIdle(
3184 VkQueue _queue)
3185 {
3186 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3187
3188 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
3189 radv_queue_family_to_ring(queue->queue_family_index),
3190 queue->queue_idx);
3191 return VK_SUCCESS;
3192 }
3193
3194 VkResult radv_DeviceWaitIdle(
3195 VkDevice _device)
3196 {
3197 RADV_FROM_HANDLE(radv_device, device, _device);
3198
3199 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
3200 for (unsigned q = 0; q < device->queue_count[i]; q++) {
3201 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
3202 }
3203 }
3204 return VK_SUCCESS;
3205 }
3206
3207 VkResult radv_EnumerateInstanceExtensionProperties(
3208 const char* pLayerName,
3209 uint32_t* pPropertyCount,
3210 VkExtensionProperties* pProperties)
3211 {
3212 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3213
3214 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
3215 if (radv_supported_instance_extensions.extensions[i]) {
3216 vk_outarray_append(&out, prop) {
3217 *prop = radv_instance_extensions[i];
3218 }
3219 }
3220 }
3221
3222 return vk_outarray_status(&out);
3223 }
3224
3225 VkResult radv_EnumerateDeviceExtensionProperties(
3226 VkPhysicalDevice physicalDevice,
3227 const char* pLayerName,
3228 uint32_t* pPropertyCount,
3229 VkExtensionProperties* pProperties)
3230 {
3231 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
3232 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3233
3234 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
3235 if (device->supported_extensions.extensions[i]) {
3236 vk_outarray_append(&out, prop) {
3237 *prop = radv_device_extensions[i];
3238 }
3239 }
3240 }
3241
3242 return vk_outarray_status(&out);
3243 }
3244
3245 PFN_vkVoidFunction radv_GetInstanceProcAddr(
3246 VkInstance _instance,
3247 const char* pName)
3248 {
3249 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3250
3251 return radv_lookup_entrypoint_checked(pName,
3252 instance ? instance->apiVersion : 0,
3253 instance ? &instance->enabled_extensions : NULL,
3254 NULL);
3255 }
3256
3257 /* The loader wants us to expose a second GetInstanceProcAddr function
3258 * to work around certain LD_PRELOAD issues seen in apps.
3259 */
3260 PUBLIC
3261 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3262 VkInstance instance,
3263 const char* pName);
3264
3265 PUBLIC
3266 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3267 VkInstance instance,
3268 const char* pName)
3269 {
3270 return radv_GetInstanceProcAddr(instance, pName);
3271 }
3272
3273 PUBLIC
3274 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3275 VkInstance _instance,
3276 const char* pName);
3277
3278 PUBLIC
3279 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3280 VkInstance _instance,
3281 const char* pName)
3282 {
3283 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3284
3285 return radv_lookup_physical_device_entrypoint_checked(pName,
3286 instance ? instance->apiVersion : 0,
3287 instance ? &instance->enabled_extensions : NULL);
3288 }
3289
3290 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3291 VkDevice _device,
3292 const char* pName)
3293 {
3294 RADV_FROM_HANDLE(radv_device, device, _device);
3295
3296 return radv_lookup_entrypoint_checked(pName,
3297 device->instance->apiVersion,
3298 &device->instance->enabled_extensions,
3299 &device->enabled_extensions);
3300 }
3301
3302 bool radv_get_memory_fd(struct radv_device *device,
3303 struct radv_device_memory *memory,
3304 int *pFD)
3305 {
3306 struct radeon_bo_metadata metadata;
3307
3308 if (memory->image) {
3309 radv_init_metadata(device, memory->image, &metadata);
3310 device->ws->buffer_set_metadata(memory->bo, &metadata);
3311 }
3312
3313 return device->ws->buffer_get_fd(device->ws, memory->bo,
3314 pFD);
3315 }
3316
3317 static VkResult radv_alloc_memory(struct radv_device *device,
3318 const VkMemoryAllocateInfo* pAllocateInfo,
3319 const VkAllocationCallbacks* pAllocator,
3320 VkDeviceMemory* pMem)
3321 {
3322 struct radv_device_memory *mem;
3323 VkResult result;
3324 enum radeon_bo_domain domain;
3325 uint32_t flags = 0;
3326 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3327
3328 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3329
3330 if (pAllocateInfo->allocationSize == 0) {
3331 /* Apparently, this is allowed */
3332 *pMem = VK_NULL_HANDLE;
3333 return VK_SUCCESS;
3334 }
3335
3336 const VkImportMemoryFdInfoKHR *import_info =
3337 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3338 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3339 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3340 const VkExportMemoryAllocateInfo *export_info =
3341 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3342 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3343 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3344
3345 const struct wsi_memory_allocate_info *wsi_info =
3346 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3347
3348 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3349 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3350 if (mem == NULL)
3351 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3352
3353 if (wsi_info && wsi_info->implicit_sync)
3354 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3355
3356 if (dedicate_info) {
3357 mem->image = radv_image_from_handle(dedicate_info->image);
3358 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3359 } else {
3360 mem->image = NULL;
3361 mem->buffer = NULL;
3362 }
3363
3364 float priority_float = 0.5;
3365 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3366 vk_find_struct_const(pAllocateInfo->pNext,
3367 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3368 if (priority_ext)
3369 priority_float = priority_ext->priority;
3370
3371 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3372 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3373
3374 mem->user_ptr = NULL;
3375
3376 if (import_info) {
3377 assert(import_info->handleType ==
3378 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3379 import_info->handleType ==
3380 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3381 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3382 priority, NULL, NULL);
3383 if (!mem->bo) {
3384 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3385 goto fail;
3386 } else {
3387 close(import_info->fd);
3388 }
3389 } else if (host_ptr_info) {
3390 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3391 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3392 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3393 pAllocateInfo->allocationSize,
3394 priority);
3395 if (!mem->bo) {
3396 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3397 goto fail;
3398 } else {
3399 mem->user_ptr = host_ptr_info->pHostPointer;
3400 }
3401 } else {
3402 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3403 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3404 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3405 domain = RADEON_DOMAIN_GTT;
3406 else
3407 domain = RADEON_DOMAIN_VRAM;
3408
3409 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3410 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3411 else
3412 flags |= RADEON_FLAG_CPU_ACCESS;
3413
3414 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3415 flags |= RADEON_FLAG_GTT_WC;
3416
3417 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
3418 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3419 if (device->use_global_bo_list) {
3420 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
3421 }
3422 }
3423
3424 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3425 domain, flags, priority);
3426
3427 if (!mem->bo) {
3428 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3429 goto fail;
3430 }
3431 mem->type_index = mem_type_index;
3432 }
3433
3434 result = radv_bo_list_add(device, mem->bo);
3435 if (result != VK_SUCCESS)
3436 goto fail_bo;
3437
3438 *pMem = radv_device_memory_to_handle(mem);
3439
3440 return VK_SUCCESS;
3441
3442 fail_bo:
3443 device->ws->buffer_destroy(mem->bo);
3444 fail:
3445 vk_free2(&device->alloc, pAllocator, mem);
3446
3447 return result;
3448 }
3449
3450 VkResult radv_AllocateMemory(
3451 VkDevice _device,
3452 const VkMemoryAllocateInfo* pAllocateInfo,
3453 const VkAllocationCallbacks* pAllocator,
3454 VkDeviceMemory* pMem)
3455 {
3456 RADV_FROM_HANDLE(radv_device, device, _device);
3457 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3458 }
3459
3460 void radv_FreeMemory(
3461 VkDevice _device,
3462 VkDeviceMemory _mem,
3463 const VkAllocationCallbacks* pAllocator)
3464 {
3465 RADV_FROM_HANDLE(radv_device, device, _device);
3466 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3467
3468 if (mem == NULL)
3469 return;
3470
3471 radv_bo_list_remove(device, mem->bo);
3472 device->ws->buffer_destroy(mem->bo);
3473 mem->bo = NULL;
3474
3475 vk_free2(&device->alloc, pAllocator, mem);
3476 }
3477
3478 VkResult radv_MapMemory(
3479 VkDevice _device,
3480 VkDeviceMemory _memory,
3481 VkDeviceSize offset,
3482 VkDeviceSize size,
3483 VkMemoryMapFlags flags,
3484 void** ppData)
3485 {
3486 RADV_FROM_HANDLE(radv_device, device, _device);
3487 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3488
3489 if (mem == NULL) {
3490 *ppData = NULL;
3491 return VK_SUCCESS;
3492 }
3493
3494 if (mem->user_ptr)
3495 *ppData = mem->user_ptr;
3496 else
3497 *ppData = device->ws->buffer_map(mem->bo);
3498
3499 if (*ppData) {
3500 *ppData += offset;
3501 return VK_SUCCESS;
3502 }
3503
3504 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3505 }
3506
3507 void radv_UnmapMemory(
3508 VkDevice _device,
3509 VkDeviceMemory _memory)
3510 {
3511 RADV_FROM_HANDLE(radv_device, device, _device);
3512 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3513
3514 if (mem == NULL)
3515 return;
3516
3517 if (mem->user_ptr == NULL)
3518 device->ws->buffer_unmap(mem->bo);
3519 }
3520
3521 VkResult radv_FlushMappedMemoryRanges(
3522 VkDevice _device,
3523 uint32_t memoryRangeCount,
3524 const VkMappedMemoryRange* pMemoryRanges)
3525 {
3526 return VK_SUCCESS;
3527 }
3528
3529 VkResult radv_InvalidateMappedMemoryRanges(
3530 VkDevice _device,
3531 uint32_t memoryRangeCount,
3532 const VkMappedMemoryRange* pMemoryRanges)
3533 {
3534 return VK_SUCCESS;
3535 }
3536
3537 void radv_GetBufferMemoryRequirements(
3538 VkDevice _device,
3539 VkBuffer _buffer,
3540 VkMemoryRequirements* pMemoryRequirements)
3541 {
3542 RADV_FROM_HANDLE(radv_device, device, _device);
3543 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3544
3545 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3546
3547 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3548 pMemoryRequirements->alignment = 4096;
3549 else
3550 pMemoryRequirements->alignment = 16;
3551
3552 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3553 }
3554
3555 void radv_GetBufferMemoryRequirements2(
3556 VkDevice device,
3557 const VkBufferMemoryRequirementsInfo2 *pInfo,
3558 VkMemoryRequirements2 *pMemoryRequirements)
3559 {
3560 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3561 &pMemoryRequirements->memoryRequirements);
3562 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3563 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3564 switch (ext->sType) {
3565 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3566 VkMemoryDedicatedRequirements *req =
3567 (VkMemoryDedicatedRequirements *) ext;
3568 req->requiresDedicatedAllocation = buffer->shareable;
3569 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3570 break;
3571 }
3572 default:
3573 break;
3574 }
3575 }
3576 }
3577
3578 void radv_GetImageMemoryRequirements(
3579 VkDevice _device,
3580 VkImage _image,
3581 VkMemoryRequirements* pMemoryRequirements)
3582 {
3583 RADV_FROM_HANDLE(radv_device, device, _device);
3584 RADV_FROM_HANDLE(radv_image, image, _image);
3585
3586 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3587
3588 pMemoryRequirements->size = image->size;
3589 pMemoryRequirements->alignment = image->alignment;
3590 }
3591
3592 void radv_GetImageMemoryRequirements2(
3593 VkDevice device,
3594 const VkImageMemoryRequirementsInfo2 *pInfo,
3595 VkMemoryRequirements2 *pMemoryRequirements)
3596 {
3597 radv_GetImageMemoryRequirements(device, pInfo->image,
3598 &pMemoryRequirements->memoryRequirements);
3599
3600 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3601
3602 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3603 switch (ext->sType) {
3604 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3605 VkMemoryDedicatedRequirements *req =
3606 (VkMemoryDedicatedRequirements *) ext;
3607 req->requiresDedicatedAllocation = image->shareable;
3608 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3609 break;
3610 }
3611 default:
3612 break;
3613 }
3614 }
3615 }
3616
3617 void radv_GetImageSparseMemoryRequirements(
3618 VkDevice device,
3619 VkImage image,
3620 uint32_t* pSparseMemoryRequirementCount,
3621 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3622 {
3623 stub();
3624 }
3625
3626 void radv_GetImageSparseMemoryRequirements2(
3627 VkDevice device,
3628 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3629 uint32_t* pSparseMemoryRequirementCount,
3630 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3631 {
3632 stub();
3633 }
3634
3635 void radv_GetDeviceMemoryCommitment(
3636 VkDevice device,
3637 VkDeviceMemory memory,
3638 VkDeviceSize* pCommittedMemoryInBytes)
3639 {
3640 *pCommittedMemoryInBytes = 0;
3641 }
3642
3643 VkResult radv_BindBufferMemory2(VkDevice device,
3644 uint32_t bindInfoCount,
3645 const VkBindBufferMemoryInfo *pBindInfos)
3646 {
3647 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3648 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3649 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3650
3651 if (mem) {
3652 buffer->bo = mem->bo;
3653 buffer->offset = pBindInfos[i].memoryOffset;
3654 } else {
3655 buffer->bo = NULL;
3656 }
3657 }
3658 return VK_SUCCESS;
3659 }
3660
3661 VkResult radv_BindBufferMemory(
3662 VkDevice device,
3663 VkBuffer buffer,
3664 VkDeviceMemory memory,
3665 VkDeviceSize memoryOffset)
3666 {
3667 const VkBindBufferMemoryInfo info = {
3668 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3669 .buffer = buffer,
3670 .memory = memory,
3671 .memoryOffset = memoryOffset
3672 };
3673
3674 return radv_BindBufferMemory2(device, 1, &info);
3675 }
3676
3677 VkResult radv_BindImageMemory2(VkDevice device,
3678 uint32_t bindInfoCount,
3679 const VkBindImageMemoryInfo *pBindInfos)
3680 {
3681 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3682 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3683 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3684
3685 if (mem) {
3686 image->bo = mem->bo;
3687 image->offset = pBindInfos[i].memoryOffset;
3688 } else {
3689 image->bo = NULL;
3690 image->offset = 0;
3691 }
3692 }
3693 return VK_SUCCESS;
3694 }
3695
3696
3697 VkResult radv_BindImageMemory(
3698 VkDevice device,
3699 VkImage image,
3700 VkDeviceMemory memory,
3701 VkDeviceSize memoryOffset)
3702 {
3703 const VkBindImageMemoryInfo info = {
3704 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3705 .image = image,
3706 .memory = memory,
3707 .memoryOffset = memoryOffset
3708 };
3709
3710 return radv_BindImageMemory2(device, 1, &info);
3711 }
3712
3713
3714 static void
3715 radv_sparse_buffer_bind_memory(struct radv_device *device,
3716 const VkSparseBufferMemoryBindInfo *bind)
3717 {
3718 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3719
3720 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3721 struct radv_device_memory *mem = NULL;
3722
3723 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3724 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3725
3726 device->ws->buffer_virtual_bind(buffer->bo,
3727 bind->pBinds[i].resourceOffset,
3728 bind->pBinds[i].size,
3729 mem ? mem->bo : NULL,
3730 bind->pBinds[i].memoryOffset);
3731 }
3732 }
3733
3734 static void
3735 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3736 const VkSparseImageOpaqueMemoryBindInfo *bind)
3737 {
3738 RADV_FROM_HANDLE(radv_image, image, bind->image);
3739
3740 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3741 struct radv_device_memory *mem = NULL;
3742
3743 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3744 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3745
3746 device->ws->buffer_virtual_bind(image->bo,
3747 bind->pBinds[i].resourceOffset,
3748 bind->pBinds[i].size,
3749 mem ? mem->bo : NULL,
3750 bind->pBinds[i].memoryOffset);
3751 }
3752 }
3753
3754 VkResult radv_QueueBindSparse(
3755 VkQueue _queue,
3756 uint32_t bindInfoCount,
3757 const VkBindSparseInfo* pBindInfo,
3758 VkFence _fence)
3759 {
3760 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3761 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3762 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3763 bool fence_emitted = false;
3764 VkResult result;
3765 int ret;
3766
3767 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3768 struct radv_winsys_sem_info sem_info;
3769 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3770 radv_sparse_buffer_bind_memory(queue->device,
3771 pBindInfo[i].pBufferBinds + j);
3772 }
3773
3774 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3775 radv_sparse_image_opaque_bind_memory(queue->device,
3776 pBindInfo[i].pImageOpaqueBinds + j);
3777 }
3778
3779 VkResult result;
3780 result = radv_alloc_sem_info(queue->device->instance,
3781 &sem_info,
3782 pBindInfo[i].waitSemaphoreCount,
3783 pBindInfo[i].pWaitSemaphores,
3784 pBindInfo[i].signalSemaphoreCount,
3785 pBindInfo[i].pSignalSemaphores,
3786 _fence);
3787 if (result != VK_SUCCESS)
3788 return result;
3789
3790 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3791 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3792 &queue->device->empty_cs[queue->queue_family_index],
3793 1, NULL, NULL,
3794 &sem_info, NULL,
3795 false, base_fence);
3796 if (ret) {
3797 radv_loge("failed to submit CS %d\n", i);
3798 abort();
3799 }
3800
3801 fence_emitted = true;
3802 }
3803
3804 radv_free_sem_info(&sem_info);
3805
3806 }
3807
3808 if (fence) {
3809 if (!fence_emitted) {
3810 result = radv_signal_fence(queue, fence);
3811 if (result != VK_SUCCESS)
3812 return result;
3813 }
3814 }
3815
3816 return VK_SUCCESS;
3817 }
3818
3819 VkResult radv_CreateFence(
3820 VkDevice _device,
3821 const VkFenceCreateInfo* pCreateInfo,
3822 const VkAllocationCallbacks* pAllocator,
3823 VkFence* pFence)
3824 {
3825 RADV_FROM_HANDLE(radv_device, device, _device);
3826 const VkExportFenceCreateInfo *export =
3827 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3828 VkExternalFenceHandleTypeFlags handleTypes =
3829 export ? export->handleTypes : 0;
3830
3831 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3832 sizeof(*fence), 8,
3833 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3834
3835 if (!fence)
3836 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3837
3838 fence->fence_wsi = NULL;
3839 fence->temp_syncobj = 0;
3840 if (device->always_use_syncobj || handleTypes) {
3841 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3842 if (ret) {
3843 vk_free2(&device->alloc, pAllocator, fence);
3844 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3845 }
3846 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3847 device->ws->signal_syncobj(device->ws, fence->syncobj);
3848 }
3849 fence->fence = NULL;
3850 } else {
3851 fence->fence = device->ws->create_fence();
3852 if (!fence->fence) {
3853 vk_free2(&device->alloc, pAllocator, fence);
3854 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3855 }
3856 fence->syncobj = 0;
3857 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
3858 device->ws->signal_fence(fence->fence);
3859 }
3860
3861 *pFence = radv_fence_to_handle(fence);
3862
3863 return VK_SUCCESS;
3864 }
3865
3866 void radv_DestroyFence(
3867 VkDevice _device,
3868 VkFence _fence,
3869 const VkAllocationCallbacks* pAllocator)
3870 {
3871 RADV_FROM_HANDLE(radv_device, device, _device);
3872 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3873
3874 if (!fence)
3875 return;
3876
3877 if (fence->temp_syncobj)
3878 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3879 if (fence->syncobj)
3880 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3881 if (fence->fence)
3882 device->ws->destroy_fence(fence->fence);
3883 if (fence->fence_wsi)
3884 fence->fence_wsi->destroy(fence->fence_wsi);
3885 vk_free2(&device->alloc, pAllocator, fence);
3886 }
3887
3888
3889 uint64_t radv_get_current_time(void)
3890 {
3891 struct timespec tv;
3892 clock_gettime(CLOCK_MONOTONIC, &tv);
3893 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3894 }
3895
3896 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3897 {
3898 uint64_t current_time = radv_get_current_time();
3899
3900 timeout = MIN2(UINT64_MAX - current_time, timeout);
3901
3902 return current_time + timeout;
3903 }
3904
3905
3906 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
3907 uint32_t fenceCount, const VkFence *pFences)
3908 {
3909 for (uint32_t i = 0; i < fenceCount; ++i) {
3910 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3911 if (fence->fence == NULL || fence->syncobj ||
3912 fence->temp_syncobj || fence->fence_wsi ||
3913 (!device->ws->is_fence_waitable(fence->fence)))
3914 return false;
3915 }
3916 return true;
3917 }
3918
3919 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3920 {
3921 for (uint32_t i = 0; i < fenceCount; ++i) {
3922 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3923 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3924 return false;
3925 }
3926 return true;
3927 }
3928
3929 VkResult radv_WaitForFences(
3930 VkDevice _device,
3931 uint32_t fenceCount,
3932 const VkFence* pFences,
3933 VkBool32 waitAll,
3934 uint64_t timeout)
3935 {
3936 RADV_FROM_HANDLE(radv_device, device, _device);
3937 timeout = radv_get_absolute_timeout(timeout);
3938
3939 if (device->always_use_syncobj &&
3940 radv_all_fences_syncobj(fenceCount, pFences))
3941 {
3942 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3943 if (!handles)
3944 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3945
3946 for (uint32_t i = 0; i < fenceCount; ++i) {
3947 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3948 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3949 }
3950
3951 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3952
3953 free(handles);
3954 return success ? VK_SUCCESS : VK_TIMEOUT;
3955 }
3956
3957 if (!waitAll && fenceCount > 1) {
3958 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3959 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
3960 uint32_t wait_count = 0;
3961 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3962 if (!fences)
3963 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3964
3965 for (uint32_t i = 0; i < fenceCount; ++i) {
3966 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3967
3968 if (device->ws->fence_wait(device->ws, fence->fence, false, 0)) {
3969 free(fences);
3970 return VK_SUCCESS;
3971 }
3972
3973 fences[wait_count++] = fence->fence;
3974 }
3975
3976 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3977 waitAll, timeout - radv_get_current_time());
3978
3979 free(fences);
3980 return success ? VK_SUCCESS : VK_TIMEOUT;
3981 }
3982
3983 while(radv_get_current_time() <= timeout) {
3984 for (uint32_t i = 0; i < fenceCount; ++i) {
3985 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3986 return VK_SUCCESS;
3987 }
3988 }
3989 return VK_TIMEOUT;
3990 }
3991
3992 for (uint32_t i = 0; i < fenceCount; ++i) {
3993 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3994 bool expired = false;
3995
3996 if (fence->temp_syncobj) {
3997 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3998 return VK_TIMEOUT;
3999 continue;
4000 }
4001
4002 if (fence->syncobj) {
4003 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
4004 return VK_TIMEOUT;
4005 continue;
4006 }
4007
4008 if (fence->fence) {
4009 if (!device->ws->is_fence_waitable(fence->fence)) {
4010 while(!device->ws->is_fence_waitable(fence->fence) &&
4011 radv_get_current_time() <= timeout)
4012 /* Do nothing */;
4013 }
4014
4015 expired = device->ws->fence_wait(device->ws,
4016 fence->fence,
4017 true, timeout);
4018 if (!expired)
4019 return VK_TIMEOUT;
4020 }
4021
4022 if (fence->fence_wsi) {
4023 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
4024 if (result != VK_SUCCESS)
4025 return result;
4026 }
4027 }
4028
4029 return VK_SUCCESS;
4030 }
4031
4032 VkResult radv_ResetFences(VkDevice _device,
4033 uint32_t fenceCount,
4034 const VkFence *pFences)
4035 {
4036 RADV_FROM_HANDLE(radv_device, device, _device);
4037
4038 for (unsigned i = 0; i < fenceCount; ++i) {
4039 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
4040 if (fence->fence)
4041 device->ws->reset_fence(fence->fence);
4042
4043 /* Per spec, we first restore the permanent payload, and then reset, so
4044 * having a temp syncobj should not skip resetting the permanent syncobj. */
4045 if (fence->temp_syncobj) {
4046 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
4047 fence->temp_syncobj = 0;
4048 }
4049
4050 if (fence->syncobj) {
4051 device->ws->reset_syncobj(device->ws, fence->syncobj);
4052 }
4053 }
4054
4055 return VK_SUCCESS;
4056 }
4057
4058 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
4059 {
4060 RADV_FROM_HANDLE(radv_device, device, _device);
4061 RADV_FROM_HANDLE(radv_fence, fence, _fence);
4062
4063 if (fence->temp_syncobj) {
4064 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
4065 return success ? VK_SUCCESS : VK_NOT_READY;
4066 }
4067
4068 if (fence->syncobj) {
4069 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
4070 return success ? VK_SUCCESS : VK_NOT_READY;
4071 }
4072
4073 if (fence->fence) {
4074 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
4075 return VK_NOT_READY;
4076 }
4077 if (fence->fence_wsi) {
4078 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
4079
4080 if (result != VK_SUCCESS) {
4081 if (result == VK_TIMEOUT)
4082 return VK_NOT_READY;
4083 return result;
4084 }
4085 }
4086 return VK_SUCCESS;
4087 }
4088
4089
4090 // Queue semaphore functions
4091
4092 VkResult radv_CreateSemaphore(
4093 VkDevice _device,
4094 const VkSemaphoreCreateInfo* pCreateInfo,
4095 const VkAllocationCallbacks* pAllocator,
4096 VkSemaphore* pSemaphore)
4097 {
4098 RADV_FROM_HANDLE(radv_device, device, _device);
4099 const VkExportSemaphoreCreateInfo *export =
4100 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
4101 VkExternalSemaphoreHandleTypeFlags handleTypes =
4102 export ? export->handleTypes : 0;
4103
4104 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
4105 sizeof(*sem), 8,
4106 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4107 if (!sem)
4108 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4109
4110 sem->temp_syncobj = 0;
4111 /* create a syncobject if we are going to export this semaphore */
4112 if (device->always_use_syncobj || handleTypes) {
4113 assert (device->physical_device->rad_info.has_syncobj);
4114 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
4115 if (ret) {
4116 vk_free2(&device->alloc, pAllocator, sem);
4117 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4118 }
4119 sem->sem = NULL;
4120 } else {
4121 sem->sem = device->ws->create_sem(device->ws);
4122 if (!sem->sem) {
4123 vk_free2(&device->alloc, pAllocator, sem);
4124 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4125 }
4126 sem->syncobj = 0;
4127 }
4128
4129 *pSemaphore = radv_semaphore_to_handle(sem);
4130 return VK_SUCCESS;
4131 }
4132
4133 void radv_DestroySemaphore(
4134 VkDevice _device,
4135 VkSemaphore _semaphore,
4136 const VkAllocationCallbacks* pAllocator)
4137 {
4138 RADV_FROM_HANDLE(radv_device, device, _device);
4139 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
4140 if (!_semaphore)
4141 return;
4142
4143 if (sem->syncobj)
4144 device->ws->destroy_syncobj(device->ws, sem->syncobj);
4145 else
4146 device->ws->destroy_sem(sem->sem);
4147 vk_free2(&device->alloc, pAllocator, sem);
4148 }
4149
4150 VkResult radv_CreateEvent(
4151 VkDevice _device,
4152 const VkEventCreateInfo* pCreateInfo,
4153 const VkAllocationCallbacks* pAllocator,
4154 VkEvent* pEvent)
4155 {
4156 RADV_FROM_HANDLE(radv_device, device, _device);
4157 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
4158 sizeof(*event), 8,
4159 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4160
4161 if (!event)
4162 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4163
4164 event->bo = device->ws->buffer_create(device->ws, 8, 8,
4165 RADEON_DOMAIN_GTT,
4166 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
4167 RADV_BO_PRIORITY_FENCE);
4168 if (!event->bo) {
4169 vk_free2(&device->alloc, pAllocator, event);
4170 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4171 }
4172
4173 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
4174
4175 *pEvent = radv_event_to_handle(event);
4176
4177 return VK_SUCCESS;
4178 }
4179
4180 void radv_DestroyEvent(
4181 VkDevice _device,
4182 VkEvent _event,
4183 const VkAllocationCallbacks* pAllocator)
4184 {
4185 RADV_FROM_HANDLE(radv_device, device, _device);
4186 RADV_FROM_HANDLE(radv_event, event, _event);
4187
4188 if (!event)
4189 return;
4190 device->ws->buffer_destroy(event->bo);
4191 vk_free2(&device->alloc, pAllocator, event);
4192 }
4193
4194 VkResult radv_GetEventStatus(
4195 VkDevice _device,
4196 VkEvent _event)
4197 {
4198 RADV_FROM_HANDLE(radv_event, event, _event);
4199
4200 if (*event->map == 1)
4201 return VK_EVENT_SET;
4202 return VK_EVENT_RESET;
4203 }
4204
4205 VkResult radv_SetEvent(
4206 VkDevice _device,
4207 VkEvent _event)
4208 {
4209 RADV_FROM_HANDLE(radv_event, event, _event);
4210 *event->map = 1;
4211
4212 return VK_SUCCESS;
4213 }
4214
4215 VkResult radv_ResetEvent(
4216 VkDevice _device,
4217 VkEvent _event)
4218 {
4219 RADV_FROM_HANDLE(radv_event, event, _event);
4220 *event->map = 0;
4221
4222 return VK_SUCCESS;
4223 }
4224
4225 VkResult radv_CreateBuffer(
4226 VkDevice _device,
4227 const VkBufferCreateInfo* pCreateInfo,
4228 const VkAllocationCallbacks* pAllocator,
4229 VkBuffer* pBuffer)
4230 {
4231 RADV_FROM_HANDLE(radv_device, device, _device);
4232 struct radv_buffer *buffer;
4233
4234 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
4235
4236 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
4237 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4238 if (buffer == NULL)
4239 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4240
4241 buffer->size = pCreateInfo->size;
4242 buffer->usage = pCreateInfo->usage;
4243 buffer->bo = NULL;
4244 buffer->offset = 0;
4245 buffer->flags = pCreateInfo->flags;
4246
4247 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
4248 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
4249
4250 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
4251 buffer->bo = device->ws->buffer_create(device->ws,
4252 align64(buffer->size, 4096),
4253 4096, 0, RADEON_FLAG_VIRTUAL,
4254 RADV_BO_PRIORITY_VIRTUAL);
4255 if (!buffer->bo) {
4256 vk_free2(&device->alloc, pAllocator, buffer);
4257 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4258 }
4259 }
4260
4261 *pBuffer = radv_buffer_to_handle(buffer);
4262
4263 return VK_SUCCESS;
4264 }
4265
4266 void radv_DestroyBuffer(
4267 VkDevice _device,
4268 VkBuffer _buffer,
4269 const VkAllocationCallbacks* pAllocator)
4270 {
4271 RADV_FROM_HANDLE(radv_device, device, _device);
4272 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4273
4274 if (!buffer)
4275 return;
4276
4277 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4278 device->ws->buffer_destroy(buffer->bo);
4279
4280 vk_free2(&device->alloc, pAllocator, buffer);
4281 }
4282
4283 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
4284 VkDevice device,
4285 const VkBufferDeviceAddressInfoEXT* pInfo)
4286 {
4287 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4288 return radv_buffer_get_va(buffer->bo) + buffer->offset;
4289 }
4290
4291
4292 static inline unsigned
4293 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
4294 {
4295 if (stencil)
4296 return plane->surface.u.legacy.stencil_tiling_index[level];
4297 else
4298 return plane->surface.u.legacy.tiling_index[level];
4299 }
4300
4301 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4302 {
4303 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4304 }
4305
4306 static uint32_t
4307 radv_init_dcc_control_reg(struct radv_device *device,
4308 struct radv_image_view *iview)
4309 {
4310 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4311 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4312 unsigned max_compressed_block_size;
4313 unsigned independent_128b_blocks;
4314 unsigned independent_64b_blocks;
4315
4316 if (!radv_dcc_enabled(iview->image, iview->base_mip))
4317 return 0;
4318
4319 if (!device->physical_device->rad_info.has_dedicated_vram) {
4320 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4321 * dGPU and 64 for APU because all of our APUs to date use
4322 * DIMMs which have a request granularity size of 64B while all
4323 * other chips have a 32B request size.
4324 */
4325 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4326 }
4327
4328 if (device->physical_device->rad_info.chip_class >= GFX10) {
4329 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4330 independent_64b_blocks = 0;
4331 independent_128b_blocks = 1;
4332 } else {
4333 independent_128b_blocks = 0;
4334
4335 if (iview->image->info.samples > 1) {
4336 if (iview->image->planes[0].surface.bpe == 1)
4337 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4338 else if (iview->image->planes[0].surface.bpe == 2)
4339 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4340 }
4341
4342 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4343 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4344 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4345 /* If this DCC image is potentially going to be used in texture
4346 * fetches, we need some special settings.
4347 */
4348 independent_64b_blocks = 1;
4349 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4350 } else {
4351 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4352 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4353 * big as possible for better compression state.
4354 */
4355 independent_64b_blocks = 0;
4356 max_compressed_block_size = max_uncompressed_block_size;
4357 }
4358 }
4359
4360 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4361 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4362 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4363 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks) |
4364 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks);
4365 }
4366
4367 void
4368 radv_initialise_color_surface(struct radv_device *device,
4369 struct radv_color_buffer_info *cb,
4370 struct radv_image_view *iview)
4371 {
4372 const struct vk_format_description *desc;
4373 unsigned ntype, format, swap, endian;
4374 unsigned blend_clamp = 0, blend_bypass = 0;
4375 uint64_t va;
4376 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
4377 const struct radeon_surf *surf = &plane->surface;
4378
4379 desc = vk_format_description(iview->vk_format);
4380
4381 memset(cb, 0, sizeof(*cb));
4382
4383 /* Intensity is implemented as Red, so treat it that way. */
4384 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4385
4386 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
4387
4388 cb->cb_color_base = va >> 8;
4389
4390 if (device->physical_device->rad_info.chip_class >= GFX9) {
4391 struct gfx9_surf_meta_flags meta;
4392 if (iview->image->dcc_offset)
4393 meta = surf->u.gfx9.dcc;
4394 else
4395 meta = surf->u.gfx9.cmask;
4396
4397 if (device->physical_device->rad_info.chip_class >= GFX10) {
4398 cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4399 S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4400 S_028EE0_CMASK_PIPE_ALIGNED(surf->u.gfx9.cmask.pipe_aligned) |
4401 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.dcc.pipe_aligned);
4402 } else {
4403 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4404 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4405 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4406 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4407 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
4408 }
4409
4410 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
4411 cb->cb_color_base |= surf->tile_swizzle;
4412 } else {
4413 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4414 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4415
4416 cb->cb_color_base += level_info->offset >> 8;
4417 if (level_info->mode == RADEON_SURF_MODE_2D)
4418 cb->cb_color_base |= surf->tile_swizzle;
4419
4420 pitch_tile_max = level_info->nblk_x / 8 - 1;
4421 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4422 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
4423
4424 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4425 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4426 cb->cb_color_cmask_slice = surf->u.legacy.cmask_slice_tile_max;
4427
4428 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4429
4430 if (radv_image_has_fmask(iview->image)) {
4431 if (device->physical_device->rad_info.chip_class >= GFX7)
4432 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(surf->u.legacy.fmask.pitch_in_pixels / 8 - 1);
4433 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(surf->u.legacy.fmask.tiling_index);
4434 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(surf->u.legacy.fmask.slice_tile_max);
4435 } else {
4436 /* This must be set for fast clear to work without FMASK. */
4437 if (device->physical_device->rad_info.chip_class >= GFX7)
4438 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4439 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4440 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4441 }
4442 }
4443
4444 /* CMASK variables */
4445 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4446 va += iview->image->cmask_offset;
4447 cb->cb_color_cmask = va >> 8;
4448
4449 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4450 va += iview->image->dcc_offset;
4451
4452 if (radv_dcc_enabled(iview->image, iview->base_mip) &&
4453 device->physical_device->rad_info.chip_class <= GFX8)
4454 va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
4455
4456 unsigned dcc_tile_swizzle = surf->tile_swizzle;
4457 dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8;
4458
4459 cb->cb_dcc_base = va >> 8;
4460 cb->cb_dcc_base |= dcc_tile_swizzle;
4461
4462 /* GFX10 field has the same base shift as the GFX6 field. */
4463 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4464 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4465 S_028C6C_SLICE_MAX_GFX10(max_slice);
4466
4467 if (iview->image->info.samples > 1) {
4468 unsigned log_samples = util_logbase2(iview->image->info.samples);
4469
4470 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4471 S_028C74_NUM_FRAGMENTS(log_samples);
4472 }
4473
4474 if (radv_image_has_fmask(iview->image)) {
4475 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask_offset;
4476 cb->cb_color_fmask = va >> 8;
4477 cb->cb_color_fmask |= surf->fmask_tile_swizzle;
4478 } else {
4479 cb->cb_color_fmask = cb->cb_color_base;
4480 }
4481
4482 ntype = radv_translate_color_numformat(iview->vk_format,
4483 desc,
4484 vk_format_get_first_non_void_channel(iview->vk_format));
4485 format = radv_translate_colorformat(iview->vk_format);
4486 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4487 radv_finishme("Illegal color\n");
4488 swap = radv_translate_colorswap(iview->vk_format, false);
4489 endian = radv_colorformat_endian_swap(format);
4490
4491 /* blend clamp should be set for all NORM/SRGB types */
4492 if (ntype == V_028C70_NUMBER_UNORM ||
4493 ntype == V_028C70_NUMBER_SNORM ||
4494 ntype == V_028C70_NUMBER_SRGB)
4495 blend_clamp = 1;
4496
4497 /* set blend bypass according to docs if SINT/UINT or
4498 8/24 COLOR variants */
4499 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4500 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4501 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4502 blend_clamp = 0;
4503 blend_bypass = 1;
4504 }
4505 #if 0
4506 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4507 (format == V_028C70_COLOR_8 ||
4508 format == V_028C70_COLOR_8_8 ||
4509 format == V_028C70_COLOR_8_8_8_8))
4510 ->color_is_int8 = true;
4511 #endif
4512 cb->cb_color_info = S_028C70_FORMAT(format) |
4513 S_028C70_COMP_SWAP(swap) |
4514 S_028C70_BLEND_CLAMP(blend_clamp) |
4515 S_028C70_BLEND_BYPASS(blend_bypass) |
4516 S_028C70_SIMPLE_FLOAT(1) |
4517 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4518 ntype != V_028C70_NUMBER_SNORM &&
4519 ntype != V_028C70_NUMBER_SRGB &&
4520 format != V_028C70_COLOR_8_24 &&
4521 format != V_028C70_COLOR_24_8) |
4522 S_028C70_NUMBER_TYPE(ntype) |
4523 S_028C70_ENDIAN(endian);
4524 if (radv_image_has_fmask(iview->image)) {
4525 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4526 if (device->physical_device->rad_info.chip_class == GFX6) {
4527 unsigned fmask_bankh = util_logbase2(surf->u.legacy.fmask.bankh);
4528 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4529 }
4530
4531 if (radv_image_is_tc_compat_cmask(iview->image)) {
4532 /* Allow the texture block to read FMASK directly
4533 * without decompressing it. This bit must be cleared
4534 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
4535 * otherwise the operation doesn't happen.
4536 */
4537 cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
4538
4539 /* Set CMASK into a tiling format that allows the
4540 * texture block to read it.
4541 */
4542 cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
4543 }
4544 }
4545
4546 if (radv_image_has_cmask(iview->image) &&
4547 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4548 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4549
4550 if (radv_dcc_enabled(iview->image, iview->base_mip))
4551 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4552
4553 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4554
4555 /* This must be set for fast clear to work without FMASK. */
4556 if (!radv_image_has_fmask(iview->image) &&
4557 device->physical_device->rad_info.chip_class == GFX6) {
4558 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
4559 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4560 }
4561
4562 if (device->physical_device->rad_info.chip_class >= GFX9) {
4563 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
4564
4565 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4566 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4567 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
4568 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
4569
4570 if (device->physical_device->rad_info.chip_class >= GFX10) {
4571 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip);
4572
4573 cb->cb_color_attrib3 |= S_028EE0_MIP0_DEPTH(mip0_depth) |
4574 S_028EE0_RESOURCE_TYPE(surf->u.gfx9.resource_type) |
4575 S_028EE0_RESOURCE_LEVEL(1);
4576 } else {
4577 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip);
4578 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4579 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
4580 }
4581
4582 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
4583 S_028C68_MIP0_HEIGHT(height - 1) |
4584 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4585 }
4586 }
4587
4588 static unsigned
4589 radv_calc_decompress_on_z_planes(struct radv_device *device,
4590 struct radv_image_view *iview)
4591 {
4592 unsigned max_zplanes = 0;
4593
4594 assert(radv_image_is_tc_compat_htile(iview->image));
4595
4596 if (device->physical_device->rad_info.chip_class >= GFX9) {
4597 /* Default value for 32-bit depth surfaces. */
4598 max_zplanes = 4;
4599
4600 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4601 iview->image->info.samples > 1)
4602 max_zplanes = 2;
4603
4604 max_zplanes = max_zplanes + 1;
4605 } else {
4606 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4607 /* Do not enable Z plane compression for 16-bit depth
4608 * surfaces because isn't supported on GFX8. Only
4609 * 32-bit depth surfaces are supported by the hardware.
4610 * This allows to maintain shader compatibility and to
4611 * reduce the number of depth decompressions.
4612 */
4613 max_zplanes = 1;
4614 } else {
4615 if (iview->image->info.samples <= 1)
4616 max_zplanes = 5;
4617 else if (iview->image->info.samples <= 4)
4618 max_zplanes = 3;
4619 else
4620 max_zplanes = 2;
4621 }
4622 }
4623
4624 return max_zplanes;
4625 }
4626
4627 void
4628 radv_initialise_ds_surface(struct radv_device *device,
4629 struct radv_ds_buffer_info *ds,
4630 struct radv_image_view *iview)
4631 {
4632 unsigned level = iview->base_mip;
4633 unsigned format, stencil_format;
4634 uint64_t va, s_offs, z_offs;
4635 bool stencil_only = false;
4636 const struct radv_image_plane *plane = &iview->image->planes[0];
4637 const struct radeon_surf *surf = &plane->surface;
4638
4639 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
4640
4641 memset(ds, 0, sizeof(*ds));
4642 switch (iview->image->vk_format) {
4643 case VK_FORMAT_D24_UNORM_S8_UINT:
4644 case VK_FORMAT_X8_D24_UNORM_PACK32:
4645 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4646 ds->offset_scale = 2.0f;
4647 break;
4648 case VK_FORMAT_D16_UNORM:
4649 case VK_FORMAT_D16_UNORM_S8_UINT:
4650 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4651 ds->offset_scale = 4.0f;
4652 break;
4653 case VK_FORMAT_D32_SFLOAT:
4654 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4655 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4656 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4657 ds->offset_scale = 1.0f;
4658 break;
4659 case VK_FORMAT_S8_UINT:
4660 stencil_only = true;
4661 break;
4662 default:
4663 break;
4664 }
4665
4666 format = radv_translate_dbformat(iview->image->vk_format);
4667 stencil_format = surf->has_stencil ?
4668 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4669
4670 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4671 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4672 S_028008_SLICE_MAX(max_slice);
4673 if (device->physical_device->rad_info.chip_class >= GFX10) {
4674 ds->db_depth_view |= S_028008_SLICE_START_HI(iview->base_layer >> 11) |
4675 S_028008_SLICE_MAX_HI(max_slice >> 11);
4676 }
4677
4678 ds->db_htile_data_base = 0;
4679 ds->db_htile_surface = 0;
4680
4681 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4682 s_offs = z_offs = va;
4683
4684 if (device->physical_device->rad_info.chip_class >= GFX9) {
4685 assert(surf->u.gfx9.surf_offset == 0);
4686 s_offs += surf->u.gfx9.stencil_offset;
4687
4688 ds->db_z_info = S_028038_FORMAT(format) |
4689 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4690 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4691 S_028038_MAXMIP(iview->image->info.levels - 1) |
4692 S_028038_ZRANGE_PRECISION(1);
4693 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4694 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
4695
4696 if (device->physical_device->rad_info.chip_class == GFX9) {
4697 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
4698 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
4699 }
4700
4701 ds->db_depth_view |= S_028008_MIPID(level);
4702 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4703 S_02801C_Y_MAX(iview->image->info.height - 1);
4704
4705 if (radv_htile_enabled(iview->image, level)) {
4706 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4707
4708 if (radv_image_is_tc_compat_htile(iview->image)) {
4709 unsigned max_zplanes =
4710 radv_calc_decompress_on_z_planes(device, iview);
4711
4712 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4713
4714 if (device->physical_device->rad_info.chip_class >= GFX10) {
4715 ds->db_z_info |= S_028040_ITERATE_FLUSH(1);
4716 ds->db_stencil_info |= S_028044_ITERATE_FLUSH(1);
4717 } else {
4718 ds->db_z_info |= S_028038_ITERATE_FLUSH(1);
4719 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4720 }
4721 }
4722
4723 if (!surf->has_stencil)
4724 /* Use all of the htile_buffer for depth if there's no stencil. */
4725 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4726 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4727 iview->image->htile_offset;
4728 ds->db_htile_data_base = va >> 8;
4729 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4730 S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned);
4731
4732 if (device->physical_device->rad_info.chip_class == GFX9) {
4733 ds->db_htile_surface |= S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
4734 }
4735 }
4736 } else {
4737 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
4738
4739 if (stencil_only)
4740 level_info = &surf->u.legacy.stencil_level[level];
4741
4742 z_offs += surf->u.legacy.level[level].offset;
4743 s_offs += surf->u.legacy.stencil_level[level].offset;
4744
4745 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4746 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4747 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4748
4749 if (iview->image->info.samples > 1)
4750 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4751
4752 if (device->physical_device->rad_info.chip_class >= GFX7) {
4753 struct radeon_info *info = &device->physical_device->rad_info;
4754 unsigned tiling_index = surf->u.legacy.tiling_index[level];
4755 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
4756 unsigned macro_index = surf->u.legacy.macro_tile_index;
4757 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4758 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4759 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4760
4761 if (stencil_only)
4762 tile_mode = stencil_tile_mode;
4763
4764 ds->db_depth_info |=
4765 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4766 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4767 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4768 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4769 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4770 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4771 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4772 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4773 } else {
4774 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
4775 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4776 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
4777 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4778 if (stencil_only)
4779 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4780 }
4781
4782 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4783 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4784 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4785
4786 if (radv_htile_enabled(iview->image, level)) {
4787 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4788
4789 if (!surf->has_stencil &&
4790 !radv_image_is_tc_compat_htile(iview->image))
4791 /* Use all of the htile_buffer for depth if there's no stencil. */
4792 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4793
4794 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4795 iview->image->htile_offset;
4796 ds->db_htile_data_base = va >> 8;
4797 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4798
4799 if (radv_image_is_tc_compat_htile(iview->image)) {
4800 unsigned max_zplanes =
4801 radv_calc_decompress_on_z_planes(device, iview);
4802
4803 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4804 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4805 }
4806 }
4807 }
4808
4809 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4810 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4811 }
4812
4813 VkResult radv_CreateFramebuffer(
4814 VkDevice _device,
4815 const VkFramebufferCreateInfo* pCreateInfo,
4816 const VkAllocationCallbacks* pAllocator,
4817 VkFramebuffer* pFramebuffer)
4818 {
4819 RADV_FROM_HANDLE(radv_device, device, _device);
4820 struct radv_framebuffer *framebuffer;
4821 const VkFramebufferAttachmentsCreateInfoKHR *imageless_create_info =
4822 vk_find_struct_const(pCreateInfo->pNext,
4823 FRAMEBUFFER_ATTACHMENTS_CREATE_INFO_KHR);
4824
4825 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4826
4827 size_t size = sizeof(*framebuffer);
4828 if (!imageless_create_info)
4829 size += sizeof(struct radv_image_view*) * pCreateInfo->attachmentCount;
4830 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4831 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4832 if (framebuffer == NULL)
4833 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4834
4835 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4836 framebuffer->width = pCreateInfo->width;
4837 framebuffer->height = pCreateInfo->height;
4838 framebuffer->layers = pCreateInfo->layers;
4839 if (imageless_create_info) {
4840 for (unsigned i = 0; i < imageless_create_info->attachmentImageInfoCount; ++i) {
4841 const VkFramebufferAttachmentImageInfoKHR *attachment =
4842 imageless_create_info->pAttachmentImageInfos + i;
4843 framebuffer->width = MIN2(framebuffer->width, attachment->width);
4844 framebuffer->height = MIN2(framebuffer->height, attachment->height);
4845 framebuffer->layers = MIN2(framebuffer->layers, attachment->layerCount);
4846 }
4847 } else {
4848 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4849 VkImageView _iview = pCreateInfo->pAttachments[i];
4850 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4851 framebuffer->attachments[i] = iview;
4852 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4853 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4854 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4855 }
4856 }
4857
4858 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4859 return VK_SUCCESS;
4860 }
4861
4862 void radv_DestroyFramebuffer(
4863 VkDevice _device,
4864 VkFramebuffer _fb,
4865 const VkAllocationCallbacks* pAllocator)
4866 {
4867 RADV_FROM_HANDLE(radv_device, device, _device);
4868 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4869
4870 if (!fb)
4871 return;
4872 vk_free2(&device->alloc, pAllocator, fb);
4873 }
4874
4875 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4876 {
4877 switch (address_mode) {
4878 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4879 return V_008F30_SQ_TEX_WRAP;
4880 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4881 return V_008F30_SQ_TEX_MIRROR;
4882 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4883 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4884 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4885 return V_008F30_SQ_TEX_CLAMP_BORDER;
4886 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4887 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4888 default:
4889 unreachable("illegal tex wrap mode");
4890 break;
4891 }
4892 }
4893
4894 static unsigned
4895 radv_tex_compare(VkCompareOp op)
4896 {
4897 switch (op) {
4898 case VK_COMPARE_OP_NEVER:
4899 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4900 case VK_COMPARE_OP_LESS:
4901 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4902 case VK_COMPARE_OP_EQUAL:
4903 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4904 case VK_COMPARE_OP_LESS_OR_EQUAL:
4905 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4906 case VK_COMPARE_OP_GREATER:
4907 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4908 case VK_COMPARE_OP_NOT_EQUAL:
4909 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4910 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4911 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4912 case VK_COMPARE_OP_ALWAYS:
4913 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4914 default:
4915 unreachable("illegal compare mode");
4916 break;
4917 }
4918 }
4919
4920 static unsigned
4921 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4922 {
4923 switch (filter) {
4924 case VK_FILTER_NEAREST:
4925 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4926 V_008F38_SQ_TEX_XY_FILTER_POINT);
4927 case VK_FILTER_LINEAR:
4928 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4929 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4930 case VK_FILTER_CUBIC_IMG:
4931 default:
4932 fprintf(stderr, "illegal texture filter");
4933 return 0;
4934 }
4935 }
4936
4937 static unsigned
4938 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4939 {
4940 switch (mode) {
4941 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4942 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4943 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4944 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4945 default:
4946 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4947 }
4948 }
4949
4950 static unsigned
4951 radv_tex_bordercolor(VkBorderColor bcolor)
4952 {
4953 switch (bcolor) {
4954 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4955 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4956 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4957 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4958 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4959 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4960 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4961 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4962 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4963 default:
4964 break;
4965 }
4966 return 0;
4967 }
4968
4969 static unsigned
4970 radv_tex_aniso_filter(unsigned filter)
4971 {
4972 if (filter < 2)
4973 return 0;
4974 if (filter < 4)
4975 return 1;
4976 if (filter < 8)
4977 return 2;
4978 if (filter < 16)
4979 return 3;
4980 return 4;
4981 }
4982
4983 static unsigned
4984 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4985 {
4986 switch (mode) {
4987 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4988 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4989 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4990 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
4991 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4992 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
4993 default:
4994 break;
4995 }
4996 return 0;
4997 }
4998
4999 static uint32_t
5000 radv_get_max_anisotropy(struct radv_device *device,
5001 const VkSamplerCreateInfo *pCreateInfo)
5002 {
5003 if (device->force_aniso >= 0)
5004 return device->force_aniso;
5005
5006 if (pCreateInfo->anisotropyEnable &&
5007 pCreateInfo->maxAnisotropy > 1.0f)
5008 return (uint32_t)pCreateInfo->maxAnisotropy;
5009
5010 return 0;
5011 }
5012
5013 static void
5014 radv_init_sampler(struct radv_device *device,
5015 struct radv_sampler *sampler,
5016 const VkSamplerCreateInfo *pCreateInfo)
5017 {
5018 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
5019 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
5020 bool compat_mode = device->physical_device->rad_info.chip_class == GFX8 ||
5021 device->physical_device->rad_info.chip_class == GFX9;
5022 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
5023
5024 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
5025 vk_find_struct_const(pCreateInfo->pNext,
5026 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
5027 if (sampler_reduction)
5028 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
5029
5030 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
5031 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
5032 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
5033 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
5034 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
5035 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
5036 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
5037 S_008F30_ANISO_BIAS(max_aniso_ratio) |
5038 S_008F30_DISABLE_CUBE_WRAP(0) |
5039 S_008F30_COMPAT_MODE(compat_mode) |
5040 S_008F30_FILTER_MODE(filter_mode));
5041 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
5042 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
5043 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
5044 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
5045 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
5046 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
5047 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
5048 S_008F38_MIP_POINT_PRECLAMP(0));
5049 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
5050 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
5051
5052 if (device->physical_device->rad_info.chip_class >= GFX10) {
5053 sampler->state[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
5054 } else {
5055 sampler->state[2] |=
5056 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
5057 S_008F38_FILTER_PREC_FIX(1) |
5058 S_008F38_ANISO_OVERRIDE_GFX6(device->physical_device->rad_info.chip_class >= GFX8);
5059 }
5060 }
5061
5062 VkResult radv_CreateSampler(
5063 VkDevice _device,
5064 const VkSamplerCreateInfo* pCreateInfo,
5065 const VkAllocationCallbacks* pAllocator,
5066 VkSampler* pSampler)
5067 {
5068 RADV_FROM_HANDLE(radv_device, device, _device);
5069 struct radv_sampler *sampler;
5070
5071 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
5072 vk_find_struct_const(pCreateInfo->pNext,
5073 SAMPLER_YCBCR_CONVERSION_INFO);
5074
5075 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
5076
5077 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
5078 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5079 if (!sampler)
5080 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5081
5082 radv_init_sampler(device, sampler, pCreateInfo);
5083
5084 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
5085 *pSampler = radv_sampler_to_handle(sampler);
5086
5087 return VK_SUCCESS;
5088 }
5089
5090 void radv_DestroySampler(
5091 VkDevice _device,
5092 VkSampler _sampler,
5093 const VkAllocationCallbacks* pAllocator)
5094 {
5095 RADV_FROM_HANDLE(radv_device, device, _device);
5096 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
5097
5098 if (!sampler)
5099 return;
5100 vk_free2(&device->alloc, pAllocator, sampler);
5101 }
5102
5103 /* vk_icd.h does not declare this function, so we declare it here to
5104 * suppress Wmissing-prototypes.
5105 */
5106 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5107 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
5108
5109 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5110 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
5111 {
5112 /* For the full details on loader interface versioning, see
5113 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
5114 * What follows is a condensed summary, to help you navigate the large and
5115 * confusing official doc.
5116 *
5117 * - Loader interface v0 is incompatible with later versions. We don't
5118 * support it.
5119 *
5120 * - In loader interface v1:
5121 * - The first ICD entrypoint called by the loader is
5122 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
5123 * entrypoint.
5124 * - The ICD must statically expose no other Vulkan symbol unless it is
5125 * linked with -Bsymbolic.
5126 * - Each dispatchable Vulkan handle created by the ICD must be
5127 * a pointer to a struct whose first member is VK_LOADER_DATA. The
5128 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
5129 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
5130 * vkDestroySurfaceKHR(). The ICD must be capable of working with
5131 * such loader-managed surfaces.
5132 *
5133 * - Loader interface v2 differs from v1 in:
5134 * - The first ICD entrypoint called by the loader is
5135 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
5136 * statically expose this entrypoint.
5137 *
5138 * - Loader interface v3 differs from v2 in:
5139 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
5140 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
5141 * because the loader no longer does so.
5142 */
5143 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
5144 return VK_SUCCESS;
5145 }
5146
5147 VkResult radv_GetMemoryFdKHR(VkDevice _device,
5148 const VkMemoryGetFdInfoKHR *pGetFdInfo,
5149 int *pFD)
5150 {
5151 RADV_FROM_HANDLE(radv_device, device, _device);
5152 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
5153
5154 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
5155
5156 /* At the moment, we support only the below handle types. */
5157 assert(pGetFdInfo->handleType ==
5158 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
5159 pGetFdInfo->handleType ==
5160 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
5161
5162 bool ret = radv_get_memory_fd(device, memory, pFD);
5163 if (ret == false)
5164 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
5165 return VK_SUCCESS;
5166 }
5167
5168 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
5169 VkExternalMemoryHandleTypeFlagBits handleType,
5170 int fd,
5171 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
5172 {
5173 RADV_FROM_HANDLE(radv_device, device, _device);
5174
5175 switch (handleType) {
5176 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
5177 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
5178 return VK_SUCCESS;
5179
5180 default:
5181 /* The valid usage section for this function says:
5182 *
5183 * "handleType must not be one of the handle types defined as
5184 * opaque."
5185 *
5186 * So opaque handle types fall into the default "unsupported" case.
5187 */
5188 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5189 }
5190 }
5191
5192 static VkResult radv_import_opaque_fd(struct radv_device *device,
5193 int fd,
5194 uint32_t *syncobj)
5195 {
5196 uint32_t syncobj_handle = 0;
5197 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
5198 if (ret != 0)
5199 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5200
5201 if (*syncobj)
5202 device->ws->destroy_syncobj(device->ws, *syncobj);
5203
5204 *syncobj = syncobj_handle;
5205 close(fd);
5206
5207 return VK_SUCCESS;
5208 }
5209
5210 static VkResult radv_import_sync_fd(struct radv_device *device,
5211 int fd,
5212 uint32_t *syncobj)
5213 {
5214 /* If we create a syncobj we do it locally so that if we have an error, we don't
5215 * leave a syncobj in an undetermined state in the fence. */
5216 uint32_t syncobj_handle = *syncobj;
5217 if (!syncobj_handle) {
5218 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
5219 if (ret) {
5220 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5221 }
5222 }
5223
5224 if (fd == -1) {
5225 device->ws->signal_syncobj(device->ws, syncobj_handle);
5226 } else {
5227 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
5228 if (ret != 0)
5229 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5230 }
5231
5232 *syncobj = syncobj_handle;
5233 if (fd != -1)
5234 close(fd);
5235
5236 return VK_SUCCESS;
5237 }
5238
5239 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
5240 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
5241 {
5242 RADV_FROM_HANDLE(radv_device, device, _device);
5243 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
5244 uint32_t *syncobj_dst = NULL;
5245
5246 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
5247 syncobj_dst = &sem->temp_syncobj;
5248 } else {
5249 syncobj_dst = &sem->syncobj;
5250 }
5251
5252 switch(pImportSemaphoreFdInfo->handleType) {
5253 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5254 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5255 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5256 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5257 default:
5258 unreachable("Unhandled semaphore handle type");
5259 }
5260 }
5261
5262 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
5263 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
5264 int *pFd)
5265 {
5266 RADV_FROM_HANDLE(radv_device, device, _device);
5267 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
5268 int ret;
5269 uint32_t syncobj_handle;
5270
5271 if (sem->temp_syncobj)
5272 syncobj_handle = sem->temp_syncobj;
5273 else
5274 syncobj_handle = sem->syncobj;
5275
5276 switch(pGetFdInfo->handleType) {
5277 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5278 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5279 break;
5280 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5281 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5282 if (!ret) {
5283 if (sem->temp_syncobj) {
5284 close (sem->temp_syncobj);
5285 sem->temp_syncobj = 0;
5286 } else {
5287 device->ws->reset_syncobj(device->ws, syncobj_handle);
5288 }
5289 }
5290 break;
5291 default:
5292 unreachable("Unhandled semaphore handle type");
5293 }
5294
5295 if (ret)
5296 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5297 return VK_SUCCESS;
5298 }
5299
5300 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5301 VkPhysicalDevice physicalDevice,
5302 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
5303 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
5304 {
5305 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5306
5307 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5308 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5309 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5310 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
5311 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5312 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5313 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5314 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5315 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
5316 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5317 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5318 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5319 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5320 } else {
5321 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
5322 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
5323 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
5324 }
5325 }
5326
5327 VkResult radv_ImportFenceFdKHR(VkDevice _device,
5328 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
5329 {
5330 RADV_FROM_HANDLE(radv_device, device, _device);
5331 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
5332 uint32_t *syncobj_dst = NULL;
5333
5334
5335 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
5336 syncobj_dst = &fence->temp_syncobj;
5337 } else {
5338 syncobj_dst = &fence->syncobj;
5339 }
5340
5341 switch(pImportFenceFdInfo->handleType) {
5342 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5343 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5344 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5345 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5346 default:
5347 unreachable("Unhandled fence handle type");
5348 }
5349 }
5350
5351 VkResult radv_GetFenceFdKHR(VkDevice _device,
5352 const VkFenceGetFdInfoKHR *pGetFdInfo,
5353 int *pFd)
5354 {
5355 RADV_FROM_HANDLE(radv_device, device, _device);
5356 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
5357 int ret;
5358 uint32_t syncobj_handle;
5359
5360 if (fence->temp_syncobj)
5361 syncobj_handle = fence->temp_syncobj;
5362 else
5363 syncobj_handle = fence->syncobj;
5364
5365 switch(pGetFdInfo->handleType) {
5366 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5367 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5368 break;
5369 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5370 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5371 if (!ret) {
5372 if (fence->temp_syncobj) {
5373 close (fence->temp_syncobj);
5374 fence->temp_syncobj = 0;
5375 } else {
5376 device->ws->reset_syncobj(device->ws, syncobj_handle);
5377 }
5378 }
5379 break;
5380 default:
5381 unreachable("Unhandled fence handle type");
5382 }
5383
5384 if (ret)
5385 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5386 return VK_SUCCESS;
5387 }
5388
5389 void radv_GetPhysicalDeviceExternalFenceProperties(
5390 VkPhysicalDevice physicalDevice,
5391 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5392 VkExternalFenceProperties *pExternalFenceProperties)
5393 {
5394 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5395
5396 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5397 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5398 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5399 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5400 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5401 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5402 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5403 } else {
5404 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5405 pExternalFenceProperties->compatibleHandleTypes = 0;
5406 pExternalFenceProperties->externalFenceFeatures = 0;
5407 }
5408 }
5409
5410 VkResult
5411 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5412 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5413 const VkAllocationCallbacks* pAllocator,
5414 VkDebugReportCallbackEXT* pCallback)
5415 {
5416 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5417 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5418 pCreateInfo, pAllocator, &instance->alloc,
5419 pCallback);
5420 }
5421
5422 void
5423 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5424 VkDebugReportCallbackEXT _callback,
5425 const VkAllocationCallbacks* pAllocator)
5426 {
5427 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5428 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5429 _callback, pAllocator, &instance->alloc);
5430 }
5431
5432 void
5433 radv_DebugReportMessageEXT(VkInstance _instance,
5434 VkDebugReportFlagsEXT flags,
5435 VkDebugReportObjectTypeEXT objectType,
5436 uint64_t object,
5437 size_t location,
5438 int32_t messageCode,
5439 const char* pLayerPrefix,
5440 const char* pMessage)
5441 {
5442 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5443 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5444 object, location, messageCode, pLayerPrefix, pMessage);
5445 }
5446
5447 void
5448 radv_GetDeviceGroupPeerMemoryFeatures(
5449 VkDevice device,
5450 uint32_t heapIndex,
5451 uint32_t localDeviceIndex,
5452 uint32_t remoteDeviceIndex,
5453 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5454 {
5455 assert(localDeviceIndex == remoteDeviceIndex);
5456
5457 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5458 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5459 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5460 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5461 }
5462
5463 static const VkTimeDomainEXT radv_time_domains[] = {
5464 VK_TIME_DOMAIN_DEVICE_EXT,
5465 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5466 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5467 };
5468
5469 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5470 VkPhysicalDevice physicalDevice,
5471 uint32_t *pTimeDomainCount,
5472 VkTimeDomainEXT *pTimeDomains)
5473 {
5474 int d;
5475 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5476
5477 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5478 vk_outarray_append(&out, i) {
5479 *i = radv_time_domains[d];
5480 }
5481 }
5482
5483 return vk_outarray_status(&out);
5484 }
5485
5486 static uint64_t
5487 radv_clock_gettime(clockid_t clock_id)
5488 {
5489 struct timespec current;
5490 int ret;
5491
5492 ret = clock_gettime(clock_id, &current);
5493 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5494 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5495 if (ret < 0)
5496 return 0;
5497
5498 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5499 }
5500
5501 VkResult radv_GetCalibratedTimestampsEXT(
5502 VkDevice _device,
5503 uint32_t timestampCount,
5504 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5505 uint64_t *pTimestamps,
5506 uint64_t *pMaxDeviation)
5507 {
5508 RADV_FROM_HANDLE(radv_device, device, _device);
5509 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5510 int d;
5511 uint64_t begin, end;
5512 uint64_t max_clock_period = 0;
5513
5514 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5515
5516 for (d = 0; d < timestampCount; d++) {
5517 switch (pTimestampInfos[d].timeDomain) {
5518 case VK_TIME_DOMAIN_DEVICE_EXT:
5519 pTimestamps[d] = device->ws->query_value(device->ws,
5520 RADEON_TIMESTAMP);
5521 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5522 max_clock_period = MAX2(max_clock_period, device_period);
5523 break;
5524 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5525 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5526 max_clock_period = MAX2(max_clock_period, 1);
5527 break;
5528
5529 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5530 pTimestamps[d] = begin;
5531 break;
5532 default:
5533 pTimestamps[d] = 0;
5534 break;
5535 }
5536 }
5537
5538 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5539
5540 /*
5541 * The maximum deviation is the sum of the interval over which we
5542 * perform the sampling and the maximum period of any sampled
5543 * clock. That's because the maximum skew between any two sampled
5544 * clock edges is when the sampled clock with the largest period is
5545 * sampled at the end of that period but right at the beginning of the
5546 * sampling interval and some other clock is sampled right at the
5547 * begining of its sampling period and right at the end of the
5548 * sampling interval. Let's assume the GPU has the longest clock
5549 * period and that the application is sampling GPU and monotonic:
5550 *
5551 * s e
5552 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5553 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5554 *
5555 * g
5556 * 0 1 2 3
5557 * GPU -----_____-----_____-----_____-----_____
5558 *
5559 * m
5560 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5561 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5562 *
5563 * Interval <----------------->
5564 * Deviation <-------------------------->
5565 *
5566 * s = read(raw) 2
5567 * g = read(GPU) 1
5568 * m = read(monotonic) 2
5569 * e = read(raw) b
5570 *
5571 * We round the sample interval up by one tick to cover sampling error
5572 * in the interval clock
5573 */
5574
5575 uint64_t sample_interval = end - begin + 1;
5576
5577 *pMaxDeviation = sample_interval + max_clock_period;
5578
5579 return VK_SUCCESS;
5580 }
5581
5582 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
5583 VkPhysicalDevice physicalDevice,
5584 VkSampleCountFlagBits samples,
5585 VkMultisamplePropertiesEXT* pMultisampleProperties)
5586 {
5587 if (samples & (VK_SAMPLE_COUNT_2_BIT |
5588 VK_SAMPLE_COUNT_4_BIT |
5589 VK_SAMPLE_COUNT_8_BIT)) {
5590 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 };
5591 } else {
5592 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 };
5593 }
5594 }