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09bb382eeb8783faaa872be83bc9b91d58d24aac
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "gfx9d.h"
47 #include "util/debug.h"
48
49 static int
50 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
51 {
52 uint32_t mesa_timestamp, llvm_timestamp;
53 uint16_t f = family;
54 memset(uuid, 0, VK_UUID_SIZE);
55 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
56 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
57 return -1;
58
59 memcpy(uuid, &mesa_timestamp, 4);
60 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
61 memcpy((char*)uuid + 8, &f, 2);
62 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
63 return 0;
64 }
65
66 static void
67 radv_get_driver_uuid(void *uuid)
68 {
69 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
70 }
71
72 static void
73 radv_get_device_uuid(struct radeon_info *info, void *uuid)
74 {
75 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
76 }
77
78 static void
79 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
80 {
81 const char *chip_string;
82 char llvm_string[32] = {};
83
84 switch (family) {
85 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
86 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
87 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
88 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
89 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
90 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
91 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
92 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
93 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
94 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
95 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
96 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
97 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
98 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
99 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
100 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
101 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
102 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
103 case CHIP_VEGA10: chip_string = "AMD RADV VEGA"; break;
104 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
105 default: chip_string = "AMD RADV unknown"; break;
106 }
107
108 if (HAVE_LLVM > 0) {
109 snprintf(llvm_string, sizeof(llvm_string),
110 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
111 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
112 }
113
114 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
115 }
116
117 static void
118 radv_physical_device_init_mem_types(struct radv_physical_device *device)
119 {
120 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
121 uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
122 device->rad_info.vram_vis_size);
123
124 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
125 device->memory_properties.memoryHeapCount = 0;
126 if (device->rad_info.vram_size - visible_vram_size > 0) {
127 vram_index = device->memory_properties.memoryHeapCount++;
128 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
129 .size = device->rad_info.vram_size - visible_vram_size,
130 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
131 };
132 }
133 if (visible_vram_size) {
134 visible_vram_index = device->memory_properties.memoryHeapCount++;
135 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
136 .size = visible_vram_size,
137 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
138 };
139 }
140 if (device->rad_info.gart_size > 0) {
141 gart_index = device->memory_properties.memoryHeapCount++;
142 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
143 .size = device->rad_info.gart_size,
144 .flags = 0,
145 };
146 }
147
148 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
149 unsigned type_count = 0;
150 if (vram_index >= 0) {
151 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
152 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
153 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
154 .heapIndex = vram_index,
155 };
156 }
157 if (gart_index >= 0) {
158 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
159 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
160 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
161 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
162 .heapIndex = gart_index,
163 };
164 }
165 if (visible_vram_index >= 0) {
166 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
167 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
168 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
169 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
170 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
171 .heapIndex = visible_vram_index,
172 };
173 }
174 if (gart_index >= 0) {
175 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
176 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
177 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
178 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
179 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
180 .heapIndex = gart_index,
181 };
182 }
183 device->memory_properties.memoryTypeCount = type_count;
184 }
185
186 static VkResult
187 radv_physical_device_init(struct radv_physical_device *device,
188 struct radv_instance *instance,
189 drmDevicePtr drm_device)
190 {
191 const char *path = drm_device->nodes[DRM_NODE_RENDER];
192 VkResult result;
193 drmVersionPtr version;
194 int fd;
195
196 fd = open(path, O_RDWR | O_CLOEXEC);
197 if (fd < 0)
198 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
199
200 version = drmGetVersion(fd);
201 if (!version) {
202 close(fd);
203 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
204 "failed to get version %s: %m", path);
205 }
206
207 if (strcmp(version->name, "amdgpu")) {
208 drmFreeVersion(version);
209 close(fd);
210 return VK_ERROR_INCOMPATIBLE_DRIVER;
211 }
212 drmFreeVersion(version);
213
214 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
215 device->instance = instance;
216 assert(strlen(path) < ARRAY_SIZE(device->path));
217 strncpy(device->path, path, ARRAY_SIZE(device->path));
218
219 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
220 instance->perftest_flags);
221 if (!device->ws) {
222 result = VK_ERROR_INCOMPATIBLE_DRIVER;
223 goto fail;
224 }
225
226 device->local_fd = fd;
227 device->ws->query_info(device->ws, &device->rad_info);
228
229 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
230
231 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
232 device->ws->destroy(device->ws);
233 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
234 "cannot generate UUID");
235 goto fail;
236 }
237
238 /* These flags affect shader compilation. */
239 uint64_t shader_env_flags =
240 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
241 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
242
243 /* The gpu id is already embeded in the uuid so we just pass "radv"
244 * when creating the cache.
245 */
246 char buf[VK_UUID_SIZE * 2 + 1];
247 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
248 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
249
250 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
251
252 radv_get_driver_uuid(&device->device_uuid);
253 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
254
255 if (device->rad_info.family == CHIP_STONEY ||
256 device->rad_info.chip_class >= GFX9) {
257 device->has_rbplus = true;
258 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY;
259 }
260
261 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
262 * on SI.
263 */
264 device->has_clear_state = device->rad_info.chip_class >= CIK;
265
266 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
267
268 /* Vega10/Raven need a special workaround for a hardware bug. */
269 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
270 device->rad_info.family == CHIP_RAVEN;
271
272 radv_physical_device_init_mem_types(device);
273
274 result = radv_init_wsi(device);
275 if (result != VK_SUCCESS) {
276 device->ws->destroy(device->ws);
277 goto fail;
278 }
279
280 return VK_SUCCESS;
281
282 fail:
283 close(fd);
284 return result;
285 }
286
287 static void
288 radv_physical_device_finish(struct radv_physical_device *device)
289 {
290 radv_finish_wsi(device);
291 device->ws->destroy(device->ws);
292 disk_cache_destroy(device->disk_cache);
293 close(device->local_fd);
294 }
295
296 static void *
297 default_alloc_func(void *pUserData, size_t size, size_t align,
298 VkSystemAllocationScope allocationScope)
299 {
300 return malloc(size);
301 }
302
303 static void *
304 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
305 size_t align, VkSystemAllocationScope allocationScope)
306 {
307 return realloc(pOriginal, size);
308 }
309
310 static void
311 default_free_func(void *pUserData, void *pMemory)
312 {
313 free(pMemory);
314 }
315
316 static const VkAllocationCallbacks default_alloc = {
317 .pUserData = NULL,
318 .pfnAllocation = default_alloc_func,
319 .pfnReallocation = default_realloc_func,
320 .pfnFree = default_free_func,
321 };
322
323 static const struct debug_control radv_debug_options[] = {
324 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
325 {"nodcc", RADV_DEBUG_NO_DCC},
326 {"shaders", RADV_DEBUG_DUMP_SHADERS},
327 {"nocache", RADV_DEBUG_NO_CACHE},
328 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
329 {"nohiz", RADV_DEBUG_NO_HIZ},
330 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
331 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
332 {"allbos", RADV_DEBUG_ALL_BOS},
333 {"noibs", RADV_DEBUG_NO_IBS},
334 {"spirv", RADV_DEBUG_DUMP_SPIRV},
335 {"vmfaults", RADV_DEBUG_VM_FAULTS},
336 {"zerovram", RADV_DEBUG_ZERO_VRAM},
337 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
338 {"nosisched", RADV_DEBUG_NO_SISCHED},
339 {"preoptir", RADV_DEBUG_PREOPTIR},
340 {NULL, 0}
341 };
342
343 const char *
344 radv_get_debug_option_name(int id)
345 {
346 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
347 return radv_debug_options[id].string;
348 }
349
350 static const struct debug_control radv_perftest_options[] = {
351 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
352 {"sisched", RADV_PERFTEST_SISCHED},
353 {"localbos", RADV_PERFTEST_LOCAL_BOS},
354 {"binning", RADV_PERFTEST_BINNING},
355 {NULL, 0}
356 };
357
358 const char *
359 radv_get_perftest_option_name(int id)
360 {
361 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
362 return radv_perftest_options[id].string;
363 }
364
365 static void
366 radv_handle_per_app_options(struct radv_instance *instance,
367 const VkApplicationInfo *info)
368 {
369 const char *name = info ? info->pApplicationName : NULL;
370
371 if (!name)
372 return;
373
374 if (!strcmp(name, "Talos - Linux - 32bit") ||
375 !strcmp(name, "Talos - Linux - 64bit")) {
376 /* Force enable LLVM sisched for Talos because it looks safe
377 * and it gives few more FPS.
378 */
379 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
380 }
381 }
382
383 VkResult radv_CreateInstance(
384 const VkInstanceCreateInfo* pCreateInfo,
385 const VkAllocationCallbacks* pAllocator,
386 VkInstance* pInstance)
387 {
388 struct radv_instance *instance;
389 VkResult result;
390
391 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
392
393 uint32_t client_version;
394 if (pCreateInfo->pApplicationInfo &&
395 pCreateInfo->pApplicationInfo->apiVersion != 0) {
396 client_version = pCreateInfo->pApplicationInfo->apiVersion;
397 } else {
398 client_version = VK_MAKE_VERSION(1, 0, 0);
399 }
400
401 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
402 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
403 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
404 "Client requested version %d.%d.%d",
405 VK_VERSION_MAJOR(client_version),
406 VK_VERSION_MINOR(client_version),
407 VK_VERSION_PATCH(client_version));
408 }
409
410 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
411 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
412 if (!radv_instance_extension_supported(ext_name))
413 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
414 }
415
416 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
417 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
418 if (!instance)
419 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
420
421 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
422
423 if (pAllocator)
424 instance->alloc = *pAllocator;
425 else
426 instance->alloc = default_alloc;
427
428 instance->apiVersion = client_version;
429 instance->physicalDeviceCount = -1;
430
431 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
432 if (result != VK_SUCCESS) {
433 vk_free2(&default_alloc, pAllocator, instance);
434 return vk_error(result);
435 }
436
437 _mesa_locale_init();
438
439 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
440
441 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
442 radv_debug_options);
443
444 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
445 radv_perftest_options);
446
447 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
448
449 if (instance->debug_flags & RADV_DEBUG_NO_SISCHED) {
450 /* Disable sisched when the user requests it, this is mostly
451 * useful when the driver force-enable sisched for the given
452 * application.
453 */
454 instance->perftest_flags &= ~RADV_PERFTEST_SISCHED;
455 }
456
457 *pInstance = radv_instance_to_handle(instance);
458
459 return VK_SUCCESS;
460 }
461
462 void radv_DestroyInstance(
463 VkInstance _instance,
464 const VkAllocationCallbacks* pAllocator)
465 {
466 RADV_FROM_HANDLE(radv_instance, instance, _instance);
467
468 if (!instance)
469 return;
470
471 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
472 radv_physical_device_finish(instance->physicalDevices + i);
473 }
474
475 VG(VALGRIND_DESTROY_MEMPOOL(instance));
476
477 _mesa_locale_fini();
478
479 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
480
481 vk_free(&instance->alloc, instance);
482 }
483
484 static VkResult
485 radv_enumerate_devices(struct radv_instance *instance)
486 {
487 /* TODO: Check for more devices ? */
488 drmDevicePtr devices[8];
489 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
490 int max_devices;
491
492 instance->physicalDeviceCount = 0;
493
494 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
495 if (max_devices < 1)
496 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
497
498 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
499 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
500 devices[i]->bustype == DRM_BUS_PCI &&
501 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
502
503 result = radv_physical_device_init(instance->physicalDevices +
504 instance->physicalDeviceCount,
505 instance,
506 devices[i]);
507 if (result == VK_SUCCESS)
508 ++instance->physicalDeviceCount;
509 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
510 break;
511 }
512 }
513 drmFreeDevices(devices, max_devices);
514
515 return result;
516 }
517
518 VkResult radv_EnumeratePhysicalDevices(
519 VkInstance _instance,
520 uint32_t* pPhysicalDeviceCount,
521 VkPhysicalDevice* pPhysicalDevices)
522 {
523 RADV_FROM_HANDLE(radv_instance, instance, _instance);
524 VkResult result;
525
526 if (instance->physicalDeviceCount < 0) {
527 result = radv_enumerate_devices(instance);
528 if (result != VK_SUCCESS &&
529 result != VK_ERROR_INCOMPATIBLE_DRIVER)
530 return result;
531 }
532
533 if (!pPhysicalDevices) {
534 *pPhysicalDeviceCount = instance->physicalDeviceCount;
535 } else {
536 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
537 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
538 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
539 }
540
541 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
542 : VK_SUCCESS;
543 }
544
545 void radv_GetPhysicalDeviceFeatures(
546 VkPhysicalDevice physicalDevice,
547 VkPhysicalDeviceFeatures* pFeatures)
548 {
549 memset(pFeatures, 0, sizeof(*pFeatures));
550
551 *pFeatures = (VkPhysicalDeviceFeatures) {
552 .robustBufferAccess = true,
553 .fullDrawIndexUint32 = true,
554 .imageCubeArray = true,
555 .independentBlend = true,
556 .geometryShader = true,
557 .tessellationShader = true,
558 .sampleRateShading = true,
559 .dualSrcBlend = true,
560 .logicOp = true,
561 .multiDrawIndirect = true,
562 .drawIndirectFirstInstance = true,
563 .depthClamp = true,
564 .depthBiasClamp = true,
565 .fillModeNonSolid = true,
566 .depthBounds = true,
567 .wideLines = true,
568 .largePoints = true,
569 .alphaToOne = true,
570 .multiViewport = true,
571 .samplerAnisotropy = true,
572 .textureCompressionETC2 = false,
573 .textureCompressionASTC_LDR = false,
574 .textureCompressionBC = true,
575 .occlusionQueryPrecise = true,
576 .pipelineStatisticsQuery = true,
577 .vertexPipelineStoresAndAtomics = true,
578 .fragmentStoresAndAtomics = true,
579 .shaderTessellationAndGeometryPointSize = true,
580 .shaderImageGatherExtended = true,
581 .shaderStorageImageExtendedFormats = true,
582 .shaderStorageImageMultisample = false,
583 .shaderUniformBufferArrayDynamicIndexing = true,
584 .shaderSampledImageArrayDynamicIndexing = true,
585 .shaderStorageBufferArrayDynamicIndexing = true,
586 .shaderStorageImageArrayDynamicIndexing = true,
587 .shaderStorageImageReadWithoutFormat = true,
588 .shaderStorageImageWriteWithoutFormat = true,
589 .shaderClipDistance = true,
590 .shaderCullDistance = true,
591 .shaderFloat64 = true,
592 .shaderInt64 = true,
593 .shaderInt16 = false,
594 .sparseBinding = true,
595 .variableMultisampleRate = true,
596 .inheritedQueries = true,
597 };
598 }
599
600 void radv_GetPhysicalDeviceFeatures2KHR(
601 VkPhysicalDevice physicalDevice,
602 VkPhysicalDeviceFeatures2KHR *pFeatures)
603 {
604 vk_foreach_struct(ext, pFeatures->pNext) {
605 switch (ext->sType) {
606 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
607 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
608 features->variablePointersStorageBuffer = true;
609 features->variablePointers = false;
610 break;
611 }
612 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHX: {
613 VkPhysicalDeviceMultiviewFeaturesKHX *features = (VkPhysicalDeviceMultiviewFeaturesKHX*)ext;
614 features->multiview = true;
615 features->multiviewGeometryShader = true;
616 features->multiviewTessellationShader = true;
617 break;
618 }
619 default:
620 break;
621 }
622 }
623 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
624 }
625
626 void radv_GetPhysicalDeviceProperties(
627 VkPhysicalDevice physicalDevice,
628 VkPhysicalDeviceProperties* pProperties)
629 {
630 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
631 VkSampleCountFlags sample_counts = 0xf;
632
633 /* make sure that the entire descriptor set is addressable with a signed
634 * 32-bit int. So the sum of all limits scaled by descriptor size has to
635 * be at most 2 GiB. the combined image & samples object count as one of
636 * both. This limit is for the pipeline layout, not for the set layout, but
637 * there is no set limit, so we just set a pipeline limit. I don't think
638 * any app is going to hit this soon. */
639 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
640 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
641 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
642 32 /* sampler, largest when combined with image */ +
643 64 /* sampled image */ +
644 64 /* storage image */);
645
646 VkPhysicalDeviceLimits limits = {
647 .maxImageDimension1D = (1 << 14),
648 .maxImageDimension2D = (1 << 14),
649 .maxImageDimension3D = (1 << 11),
650 .maxImageDimensionCube = (1 << 14),
651 .maxImageArrayLayers = (1 << 11),
652 .maxTexelBufferElements = 128 * 1024 * 1024,
653 .maxUniformBufferRange = UINT32_MAX,
654 .maxStorageBufferRange = UINT32_MAX,
655 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
656 .maxMemoryAllocationCount = UINT32_MAX,
657 .maxSamplerAllocationCount = 64 * 1024,
658 .bufferImageGranularity = 64, /* A cache line */
659 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
660 .maxBoundDescriptorSets = MAX_SETS,
661 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
662 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
663 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
664 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
665 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
666 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
667 .maxPerStageResources = max_descriptor_set_size,
668 .maxDescriptorSetSamplers = max_descriptor_set_size,
669 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
670 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
671 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
672 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
673 .maxDescriptorSetSampledImages = max_descriptor_set_size,
674 .maxDescriptorSetStorageImages = max_descriptor_set_size,
675 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
676 .maxVertexInputAttributes = 32,
677 .maxVertexInputBindings = 32,
678 .maxVertexInputAttributeOffset = 2047,
679 .maxVertexInputBindingStride = 2048,
680 .maxVertexOutputComponents = 128,
681 .maxTessellationGenerationLevel = 64,
682 .maxTessellationPatchSize = 32,
683 .maxTessellationControlPerVertexInputComponents = 128,
684 .maxTessellationControlPerVertexOutputComponents = 128,
685 .maxTessellationControlPerPatchOutputComponents = 120,
686 .maxTessellationControlTotalOutputComponents = 4096,
687 .maxTessellationEvaluationInputComponents = 128,
688 .maxTessellationEvaluationOutputComponents = 128,
689 .maxGeometryShaderInvocations = 127,
690 .maxGeometryInputComponents = 64,
691 .maxGeometryOutputComponents = 128,
692 .maxGeometryOutputVertices = 256,
693 .maxGeometryTotalOutputComponents = 1024,
694 .maxFragmentInputComponents = 128,
695 .maxFragmentOutputAttachments = 8,
696 .maxFragmentDualSrcAttachments = 1,
697 .maxFragmentCombinedOutputResources = 8,
698 .maxComputeSharedMemorySize = 32768,
699 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
700 .maxComputeWorkGroupInvocations = 2048,
701 .maxComputeWorkGroupSize = {
702 2048,
703 2048,
704 2048
705 },
706 .subPixelPrecisionBits = 4 /* FIXME */,
707 .subTexelPrecisionBits = 4 /* FIXME */,
708 .mipmapPrecisionBits = 4 /* FIXME */,
709 .maxDrawIndexedIndexValue = UINT32_MAX,
710 .maxDrawIndirectCount = UINT32_MAX,
711 .maxSamplerLodBias = 16,
712 .maxSamplerAnisotropy = 16,
713 .maxViewports = MAX_VIEWPORTS,
714 .maxViewportDimensions = { (1 << 14), (1 << 14) },
715 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
716 .viewportSubPixelBits = 13, /* We take a float? */
717 .minMemoryMapAlignment = 4096, /* A page */
718 .minTexelBufferOffsetAlignment = 1,
719 .minUniformBufferOffsetAlignment = 4,
720 .minStorageBufferOffsetAlignment = 4,
721 .minTexelOffset = -32,
722 .maxTexelOffset = 31,
723 .minTexelGatherOffset = -32,
724 .maxTexelGatherOffset = 31,
725 .minInterpolationOffset = -2,
726 .maxInterpolationOffset = 2,
727 .subPixelInterpolationOffsetBits = 8,
728 .maxFramebufferWidth = (1 << 14),
729 .maxFramebufferHeight = (1 << 14),
730 .maxFramebufferLayers = (1 << 10),
731 .framebufferColorSampleCounts = sample_counts,
732 .framebufferDepthSampleCounts = sample_counts,
733 .framebufferStencilSampleCounts = sample_counts,
734 .framebufferNoAttachmentsSampleCounts = sample_counts,
735 .maxColorAttachments = MAX_RTS,
736 .sampledImageColorSampleCounts = sample_counts,
737 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
738 .sampledImageDepthSampleCounts = sample_counts,
739 .sampledImageStencilSampleCounts = sample_counts,
740 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
741 .maxSampleMaskWords = 1,
742 .timestampComputeAndGraphics = true,
743 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
744 .maxClipDistances = 8,
745 .maxCullDistances = 8,
746 .maxCombinedClipAndCullDistances = 8,
747 .discreteQueuePriorities = 1,
748 .pointSizeRange = { 0.125, 255.875 },
749 .lineWidthRange = { 0.0, 7.9921875 },
750 .pointSizeGranularity = (1.0 / 8.0),
751 .lineWidthGranularity = (1.0 / 128.0),
752 .strictLines = false, /* FINISHME */
753 .standardSampleLocations = true,
754 .optimalBufferCopyOffsetAlignment = 128,
755 .optimalBufferCopyRowPitchAlignment = 128,
756 .nonCoherentAtomSize = 64,
757 };
758
759 *pProperties = (VkPhysicalDeviceProperties) {
760 .apiVersion = radv_physical_device_api_version(pdevice),
761 .driverVersion = vk_get_driver_version(),
762 .vendorID = ATI_VENDOR_ID,
763 .deviceID = pdevice->rad_info.pci_id,
764 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
765 .limits = limits,
766 .sparseProperties = {0},
767 };
768
769 strcpy(pProperties->deviceName, pdevice->name);
770 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
771 }
772
773 void radv_GetPhysicalDeviceProperties2KHR(
774 VkPhysicalDevice physicalDevice,
775 VkPhysicalDeviceProperties2KHR *pProperties)
776 {
777 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
778 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
779
780 vk_foreach_struct(ext, pProperties->pNext) {
781 switch (ext->sType) {
782 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
783 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
784 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
785 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
786 break;
787 }
788 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
789 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
790 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
791 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
792 properties->deviceLUIDValid = false;
793 break;
794 }
795 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHX: {
796 VkPhysicalDeviceMultiviewPropertiesKHX *properties = (VkPhysicalDeviceMultiviewPropertiesKHX*)ext;
797 properties->maxMultiviewViewCount = MAX_VIEWS;
798 properties->maxMultiviewInstanceIndex = INT_MAX;
799 break;
800 }
801 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
802 VkPhysicalDevicePointClippingPropertiesKHR *properties =
803 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
804 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
805 break;
806 }
807 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
808 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
809 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
810 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
811 break;
812 }
813 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
814 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
815 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
816 properties->minImportedHostPointerAlignment = 4096;
817 break;
818 }
819 default:
820 break;
821 }
822 }
823 }
824
825 static void radv_get_physical_device_queue_family_properties(
826 struct radv_physical_device* pdevice,
827 uint32_t* pCount,
828 VkQueueFamilyProperties** pQueueFamilyProperties)
829 {
830 int num_queue_families = 1;
831 int idx;
832 if (pdevice->rad_info.num_compute_rings > 0 &&
833 pdevice->rad_info.chip_class >= CIK &&
834 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
835 num_queue_families++;
836
837 if (pQueueFamilyProperties == NULL) {
838 *pCount = num_queue_families;
839 return;
840 }
841
842 if (!*pCount)
843 return;
844
845 idx = 0;
846 if (*pCount >= 1) {
847 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
848 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
849 VK_QUEUE_COMPUTE_BIT |
850 VK_QUEUE_TRANSFER_BIT |
851 VK_QUEUE_SPARSE_BINDING_BIT,
852 .queueCount = 1,
853 .timestampValidBits = 64,
854 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
855 };
856 idx++;
857 }
858
859 if (pdevice->rad_info.num_compute_rings > 0 &&
860 pdevice->rad_info.chip_class >= CIK &&
861 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
862 if (*pCount > idx) {
863 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
864 .queueFlags = VK_QUEUE_COMPUTE_BIT |
865 VK_QUEUE_TRANSFER_BIT |
866 VK_QUEUE_SPARSE_BINDING_BIT,
867 .queueCount = pdevice->rad_info.num_compute_rings,
868 .timestampValidBits = 64,
869 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
870 };
871 idx++;
872 }
873 }
874 *pCount = idx;
875 }
876
877 void radv_GetPhysicalDeviceQueueFamilyProperties(
878 VkPhysicalDevice physicalDevice,
879 uint32_t* pCount,
880 VkQueueFamilyProperties* pQueueFamilyProperties)
881 {
882 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
883 if (!pQueueFamilyProperties) {
884 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
885 return;
886 }
887 VkQueueFamilyProperties *properties[] = {
888 pQueueFamilyProperties + 0,
889 pQueueFamilyProperties + 1,
890 pQueueFamilyProperties + 2,
891 };
892 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
893 assert(*pCount <= 3);
894 }
895
896 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
897 VkPhysicalDevice physicalDevice,
898 uint32_t* pCount,
899 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
900 {
901 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
902 if (!pQueueFamilyProperties) {
903 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
904 return;
905 }
906 VkQueueFamilyProperties *properties[] = {
907 &pQueueFamilyProperties[0].queueFamilyProperties,
908 &pQueueFamilyProperties[1].queueFamilyProperties,
909 &pQueueFamilyProperties[2].queueFamilyProperties,
910 };
911 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
912 assert(*pCount <= 3);
913 }
914
915 void radv_GetPhysicalDeviceMemoryProperties(
916 VkPhysicalDevice physicalDevice,
917 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
918 {
919 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
920
921 *pMemoryProperties = physical_device->memory_properties;
922 }
923
924 void radv_GetPhysicalDeviceMemoryProperties2KHR(
925 VkPhysicalDevice physicalDevice,
926 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
927 {
928 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
929 &pMemoryProperties->memoryProperties);
930 }
931
932 VkResult radv_GetMemoryHostPointerPropertiesEXT(
933 VkDevice _device,
934 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
935 const void *pHostPointer,
936 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
937 {
938 RADV_FROM_HANDLE(radv_device, device, _device);
939
940 switch (handleType)
941 {
942 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
943 const struct radv_physical_device *physical_device = device->physical_device;
944 uint32_t memoryTypeBits = 0;
945 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
946 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
947 memoryTypeBits = (1 << i);
948 break;
949 }
950 }
951 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
952 return VK_SUCCESS;
953 }
954 default:
955 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
956 }
957 }
958
959 static enum radeon_ctx_priority
960 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
961 {
962 /* Default to MEDIUM when a specific global priority isn't requested */
963 if (!pObj)
964 return RADEON_CTX_PRIORITY_MEDIUM;
965
966 switch(pObj->globalPriority) {
967 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
968 return RADEON_CTX_PRIORITY_REALTIME;
969 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
970 return RADEON_CTX_PRIORITY_HIGH;
971 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
972 return RADEON_CTX_PRIORITY_MEDIUM;
973 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
974 return RADEON_CTX_PRIORITY_LOW;
975 default:
976 unreachable("Illegal global priority value");
977 return RADEON_CTX_PRIORITY_INVALID;
978 }
979 }
980
981 static int
982 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
983 uint32_t queue_family_index, int idx,
984 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
985 {
986 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
987 queue->device = device;
988 queue->queue_family_index = queue_family_index;
989 queue->queue_idx = idx;
990 queue->priority = radv_get_queue_global_priority(global_priority);
991
992 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
993 if (!queue->hw_ctx)
994 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
995
996 return VK_SUCCESS;
997 }
998
999 static void
1000 radv_queue_finish(struct radv_queue *queue)
1001 {
1002 if (queue->hw_ctx)
1003 queue->device->ws->ctx_destroy(queue->hw_ctx);
1004
1005 if (queue->initial_full_flush_preamble_cs)
1006 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1007 if (queue->initial_preamble_cs)
1008 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1009 if (queue->continue_preamble_cs)
1010 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1011 if (queue->descriptor_bo)
1012 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1013 if (queue->scratch_bo)
1014 queue->device->ws->buffer_destroy(queue->scratch_bo);
1015 if (queue->esgs_ring_bo)
1016 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1017 if (queue->gsvs_ring_bo)
1018 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1019 if (queue->tess_factor_ring_bo)
1020 queue->device->ws->buffer_destroy(queue->tess_factor_ring_bo);
1021 if (queue->tess_offchip_ring_bo)
1022 queue->device->ws->buffer_destroy(queue->tess_offchip_ring_bo);
1023 if (queue->compute_scratch_bo)
1024 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1025 }
1026
1027 static void
1028 radv_device_init_gs_info(struct radv_device *device)
1029 {
1030 switch (device->physical_device->rad_info.family) {
1031 case CHIP_OLAND:
1032 case CHIP_HAINAN:
1033 case CHIP_KAVERI:
1034 case CHIP_KABINI:
1035 case CHIP_MULLINS:
1036 case CHIP_ICELAND:
1037 case CHIP_CARRIZO:
1038 case CHIP_STONEY:
1039 device->gs_table_depth = 16;
1040 return;
1041 case CHIP_TAHITI:
1042 case CHIP_PITCAIRN:
1043 case CHIP_VERDE:
1044 case CHIP_BONAIRE:
1045 case CHIP_HAWAII:
1046 case CHIP_TONGA:
1047 case CHIP_FIJI:
1048 case CHIP_POLARIS10:
1049 case CHIP_POLARIS11:
1050 case CHIP_POLARIS12:
1051 case CHIP_VEGA10:
1052 case CHIP_RAVEN:
1053 device->gs_table_depth = 32;
1054 return;
1055 default:
1056 unreachable("unknown GPU");
1057 }
1058 }
1059
1060 VkResult radv_CreateDevice(
1061 VkPhysicalDevice physicalDevice,
1062 const VkDeviceCreateInfo* pCreateInfo,
1063 const VkAllocationCallbacks* pAllocator,
1064 VkDevice* pDevice)
1065 {
1066 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1067 VkResult result;
1068 struct radv_device *device;
1069
1070 bool keep_shader_info = false;
1071
1072 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1073 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1074 if (!radv_physical_device_extension_supported(physical_device, ext_name))
1075 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
1076
1077 if (strcmp(ext_name, VK_AMD_SHADER_INFO_EXTENSION_NAME) == 0)
1078 keep_shader_info = true;
1079 }
1080
1081 /* Check enabled features */
1082 if (pCreateInfo->pEnabledFeatures) {
1083 VkPhysicalDeviceFeatures supported_features;
1084 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1085 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1086 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1087 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1088 for (uint32_t i = 0; i < num_features; i++) {
1089 if (enabled_feature[i] && !supported_feature[i])
1090 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
1091 }
1092 }
1093
1094 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1095 sizeof(*device), 8,
1096 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1097 if (!device)
1098 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1099
1100 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1101 device->instance = physical_device->instance;
1102 device->physical_device = physical_device;
1103
1104 device->ws = physical_device->ws;
1105 if (pAllocator)
1106 device->alloc = *pAllocator;
1107 else
1108 device->alloc = physical_device->instance->alloc;
1109
1110 mtx_init(&device->shader_slab_mutex, mtx_plain);
1111 list_inithead(&device->shader_slabs);
1112
1113 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1114 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1115 uint32_t qfi = queue_create->queueFamilyIndex;
1116 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1117 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1118
1119 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1120
1121 device->queues[qfi] = vk_alloc(&device->alloc,
1122 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1123 if (!device->queues[qfi]) {
1124 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1125 goto fail;
1126 }
1127
1128 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1129
1130 device->queue_count[qfi] = queue_create->queueCount;
1131
1132 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1133 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q, global_priority);
1134 if (result != VK_SUCCESS)
1135 goto fail;
1136 }
1137 }
1138
1139 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1140 (device->instance->perftest_flags & RADV_PERFTEST_BINNING);
1141
1142 /* Disabled and not implemented for now. */
1143 device->dfsm_allowed = device->pbb_allowed && false;
1144
1145 #ifdef ANDROID
1146 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1147 #endif
1148
1149 device->llvm_supports_spill = true;
1150
1151 /* The maximum number of scratch waves. Scratch space isn't divided
1152 * evenly between CUs. The number is only a function of the number of CUs.
1153 * We can decrease the constant to decrease the scratch buffer size.
1154 *
1155 * sctx->scratch_waves must be >= the maximum posible size of
1156 * 1 threadgroup, so that the hw doesn't hang from being unable
1157 * to start any.
1158 *
1159 * The recommended value is 4 per CU at most. Higher numbers don't
1160 * bring much benefit, but they still occupy chip resources (think
1161 * async compute). I've seen ~2% performance difference between 4 and 32.
1162 */
1163 uint32_t max_threads_per_block = 2048;
1164 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1165 max_threads_per_block / 64);
1166
1167 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) |
1168 S_00B800_FORCE_START_AT_000(1);
1169
1170 if (device->physical_device->rad_info.chip_class >= CIK) {
1171 /* If the KMD allows it (there is a KMD hw register for it),
1172 * allow launching waves out-of-order.
1173 */
1174 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1175 }
1176
1177 radv_device_init_gs_info(device);
1178
1179 device->tess_offchip_block_dw_size =
1180 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1181 device->has_distributed_tess =
1182 device->physical_device->rad_info.chip_class >= VI &&
1183 device->physical_device->rad_info.max_se >= 2;
1184
1185 if (getenv("RADV_TRACE_FILE")) {
1186 keep_shader_info = true;
1187
1188 if (!radv_init_trace(device))
1189 goto fail;
1190 }
1191
1192 device->keep_shader_info = keep_shader_info;
1193
1194 result = radv_device_init_meta(device);
1195 if (result != VK_SUCCESS)
1196 goto fail;
1197
1198 radv_device_init_msaa(device);
1199
1200 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1201 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1202 switch (family) {
1203 case RADV_QUEUE_GENERAL:
1204 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1205 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1206 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1207 break;
1208 case RADV_QUEUE_COMPUTE:
1209 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1210 radeon_emit(device->empty_cs[family], 0);
1211 break;
1212 }
1213 device->ws->cs_finalize(device->empty_cs[family]);
1214 }
1215
1216 if (device->physical_device->rad_info.chip_class >= CIK)
1217 cik_create_gfx_config(device);
1218
1219 VkPipelineCacheCreateInfo ci;
1220 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1221 ci.pNext = NULL;
1222 ci.flags = 0;
1223 ci.pInitialData = NULL;
1224 ci.initialDataSize = 0;
1225 VkPipelineCache pc;
1226 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1227 &ci, NULL, &pc);
1228 if (result != VK_SUCCESS)
1229 goto fail_meta;
1230
1231 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1232
1233 *pDevice = radv_device_to_handle(device);
1234 return VK_SUCCESS;
1235
1236 fail_meta:
1237 radv_device_finish_meta(device);
1238 fail:
1239 if (device->trace_bo)
1240 device->ws->buffer_destroy(device->trace_bo);
1241
1242 if (device->gfx_init)
1243 device->ws->buffer_destroy(device->gfx_init);
1244
1245 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1246 for (unsigned q = 0; q < device->queue_count[i]; q++)
1247 radv_queue_finish(&device->queues[i][q]);
1248 if (device->queue_count[i])
1249 vk_free(&device->alloc, device->queues[i]);
1250 }
1251
1252 vk_free(&device->alloc, device);
1253 return result;
1254 }
1255
1256 void radv_DestroyDevice(
1257 VkDevice _device,
1258 const VkAllocationCallbacks* pAllocator)
1259 {
1260 RADV_FROM_HANDLE(radv_device, device, _device);
1261
1262 if (!device)
1263 return;
1264
1265 if (device->trace_bo)
1266 device->ws->buffer_destroy(device->trace_bo);
1267
1268 if (device->gfx_init)
1269 device->ws->buffer_destroy(device->gfx_init);
1270
1271 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1272 for (unsigned q = 0; q < device->queue_count[i]; q++)
1273 radv_queue_finish(&device->queues[i][q]);
1274 if (device->queue_count[i])
1275 vk_free(&device->alloc, device->queues[i]);
1276 if (device->empty_cs[i])
1277 device->ws->cs_destroy(device->empty_cs[i]);
1278 }
1279 radv_device_finish_meta(device);
1280
1281 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1282 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1283
1284 radv_destroy_shader_slabs(device);
1285
1286 vk_free(&device->alloc, device);
1287 }
1288
1289 VkResult radv_EnumerateInstanceLayerProperties(
1290 uint32_t* pPropertyCount,
1291 VkLayerProperties* pProperties)
1292 {
1293 if (pProperties == NULL) {
1294 *pPropertyCount = 0;
1295 return VK_SUCCESS;
1296 }
1297
1298 /* None supported at this time */
1299 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1300 }
1301
1302 VkResult radv_EnumerateDeviceLayerProperties(
1303 VkPhysicalDevice physicalDevice,
1304 uint32_t* pPropertyCount,
1305 VkLayerProperties* pProperties)
1306 {
1307 if (pProperties == NULL) {
1308 *pPropertyCount = 0;
1309 return VK_SUCCESS;
1310 }
1311
1312 /* None supported at this time */
1313 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1314 }
1315
1316 void radv_GetDeviceQueue(
1317 VkDevice _device,
1318 uint32_t queueFamilyIndex,
1319 uint32_t queueIndex,
1320 VkQueue* pQueue)
1321 {
1322 RADV_FROM_HANDLE(radv_device, device, _device);
1323
1324 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
1325 }
1326
1327 static void
1328 fill_geom_tess_rings(struct radv_queue *queue,
1329 uint32_t *map,
1330 bool add_sample_positions,
1331 uint32_t esgs_ring_size,
1332 struct radeon_winsys_bo *esgs_ring_bo,
1333 uint32_t gsvs_ring_size,
1334 struct radeon_winsys_bo *gsvs_ring_bo,
1335 uint32_t tess_factor_ring_size,
1336 struct radeon_winsys_bo *tess_factor_ring_bo,
1337 uint32_t tess_offchip_ring_size,
1338 struct radeon_winsys_bo *tess_offchip_ring_bo)
1339 {
1340 uint64_t esgs_va = 0, gsvs_va = 0;
1341 uint64_t tess_factor_va = 0, tess_offchip_va = 0;
1342 uint32_t *desc = &map[4];
1343
1344 if (esgs_ring_bo)
1345 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1346 if (gsvs_ring_bo)
1347 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1348 if (tess_factor_ring_bo)
1349 tess_factor_va = radv_buffer_get_va(tess_factor_ring_bo);
1350 if (tess_offchip_ring_bo)
1351 tess_offchip_va = radv_buffer_get_va(tess_offchip_ring_bo);
1352
1353 /* stride 0, num records - size, add tid, swizzle, elsize4,
1354 index stride 64 */
1355 desc[0] = esgs_va;
1356 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1357 S_008F04_STRIDE(0) |
1358 S_008F04_SWIZZLE_ENABLE(true);
1359 desc[2] = esgs_ring_size;
1360 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1361 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1362 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1363 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1364 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1365 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1366 S_008F0C_ELEMENT_SIZE(1) |
1367 S_008F0C_INDEX_STRIDE(3) |
1368 S_008F0C_ADD_TID_ENABLE(true);
1369
1370 desc += 4;
1371 /* GS entry for ES->GS ring */
1372 /* stride 0, num records - size, elsize0,
1373 index stride 0 */
1374 desc[0] = esgs_va;
1375 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1376 S_008F04_STRIDE(0) |
1377 S_008F04_SWIZZLE_ENABLE(false);
1378 desc[2] = esgs_ring_size;
1379 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1380 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1381 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1382 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1383 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1384 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1385 S_008F0C_ELEMENT_SIZE(0) |
1386 S_008F0C_INDEX_STRIDE(0) |
1387 S_008F0C_ADD_TID_ENABLE(false);
1388
1389 desc += 4;
1390 /* VS entry for GS->VS ring */
1391 /* stride 0, num records - size, elsize0,
1392 index stride 0 */
1393 desc[0] = gsvs_va;
1394 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1395 S_008F04_STRIDE(0) |
1396 S_008F04_SWIZZLE_ENABLE(false);
1397 desc[2] = gsvs_ring_size;
1398 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1399 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1400 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1401 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1402 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1403 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1404 S_008F0C_ELEMENT_SIZE(0) |
1405 S_008F0C_INDEX_STRIDE(0) |
1406 S_008F0C_ADD_TID_ENABLE(false);
1407 desc += 4;
1408
1409 /* stride gsvs_itemsize, num records 64
1410 elsize 4, index stride 16 */
1411 /* shader will patch stride and desc[2] */
1412 desc[0] = gsvs_va;
1413 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1414 S_008F04_STRIDE(0) |
1415 S_008F04_SWIZZLE_ENABLE(true);
1416 desc[2] = 0;
1417 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1418 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1419 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1420 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1421 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1422 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1423 S_008F0C_ELEMENT_SIZE(1) |
1424 S_008F0C_INDEX_STRIDE(1) |
1425 S_008F0C_ADD_TID_ENABLE(true);
1426 desc += 4;
1427
1428 desc[0] = tess_factor_va;
1429 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va >> 32) |
1430 S_008F04_STRIDE(0) |
1431 S_008F04_SWIZZLE_ENABLE(false);
1432 desc[2] = tess_factor_ring_size;
1433 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1434 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1435 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1436 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1437 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1438 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1439 S_008F0C_ELEMENT_SIZE(0) |
1440 S_008F0C_INDEX_STRIDE(0) |
1441 S_008F0C_ADD_TID_ENABLE(false);
1442 desc += 4;
1443
1444 desc[0] = tess_offchip_va;
1445 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1446 S_008F04_STRIDE(0) |
1447 S_008F04_SWIZZLE_ENABLE(false);
1448 desc[2] = tess_offchip_ring_size;
1449 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1450 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1451 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1452 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1453 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1454 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1455 S_008F0C_ELEMENT_SIZE(0) |
1456 S_008F0C_INDEX_STRIDE(0) |
1457 S_008F0C_ADD_TID_ENABLE(false);
1458 desc += 4;
1459
1460 /* add sample positions after all rings */
1461 memcpy(desc, queue->device->sample_locations_1x, 8);
1462 desc += 2;
1463 memcpy(desc, queue->device->sample_locations_2x, 16);
1464 desc += 4;
1465 memcpy(desc, queue->device->sample_locations_4x, 32);
1466 desc += 8;
1467 memcpy(desc, queue->device->sample_locations_8x, 64);
1468 desc += 16;
1469 memcpy(desc, queue->device->sample_locations_16x, 128);
1470 }
1471
1472 static unsigned
1473 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1474 {
1475 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1476 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1477 device->physical_device->rad_info.family != CHIP_STONEY;
1478 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1479 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1480 device->physical_device->rad_info.max_se;
1481 unsigned offchip_granularity;
1482 unsigned hs_offchip_param;
1483 switch (device->tess_offchip_block_dw_size) {
1484 default:
1485 assert(0);
1486 /* fall through */
1487 case 8192:
1488 offchip_granularity = V_03093C_X_8K_DWORDS;
1489 break;
1490 case 4096:
1491 offchip_granularity = V_03093C_X_4K_DWORDS;
1492 break;
1493 }
1494
1495 switch (device->physical_device->rad_info.chip_class) {
1496 case SI:
1497 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1498 break;
1499 case CIK:
1500 case VI:
1501 case GFX9:
1502 default:
1503 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1504 break;
1505 }
1506
1507 *max_offchip_buffers_p = max_offchip_buffers;
1508 if (device->physical_device->rad_info.chip_class >= CIK) {
1509 if (device->physical_device->rad_info.chip_class >= VI)
1510 --max_offchip_buffers;
1511 hs_offchip_param =
1512 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1513 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1514 } else {
1515 hs_offchip_param =
1516 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1517 }
1518 return hs_offchip_param;
1519 }
1520
1521 static VkResult
1522 radv_get_preamble_cs(struct radv_queue *queue,
1523 uint32_t scratch_size,
1524 uint32_t compute_scratch_size,
1525 uint32_t esgs_ring_size,
1526 uint32_t gsvs_ring_size,
1527 bool needs_tess_rings,
1528 bool needs_sample_positions,
1529 struct radeon_winsys_cs **initial_full_flush_preamble_cs,
1530 struct radeon_winsys_cs **initial_preamble_cs,
1531 struct radeon_winsys_cs **continue_preamble_cs)
1532 {
1533 struct radeon_winsys_bo *scratch_bo = NULL;
1534 struct radeon_winsys_bo *descriptor_bo = NULL;
1535 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1536 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1537 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1538 struct radeon_winsys_bo *tess_factor_ring_bo = NULL;
1539 struct radeon_winsys_bo *tess_offchip_ring_bo = NULL;
1540 struct radeon_winsys_cs *dest_cs[3] = {0};
1541 bool add_tess_rings = false, add_sample_positions = false;
1542 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1543 unsigned max_offchip_buffers;
1544 unsigned hs_offchip_param = 0;
1545 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
1546 if (!queue->has_tess_rings) {
1547 if (needs_tess_rings)
1548 add_tess_rings = true;
1549 }
1550 if (!queue->has_sample_positions) {
1551 if (needs_sample_positions)
1552 add_sample_positions = true;
1553 }
1554 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1555 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1556 &max_offchip_buffers);
1557 tess_offchip_ring_size = max_offchip_buffers *
1558 queue->device->tess_offchip_block_dw_size * 4;
1559
1560 if (scratch_size <= queue->scratch_size &&
1561 compute_scratch_size <= queue->compute_scratch_size &&
1562 esgs_ring_size <= queue->esgs_ring_size &&
1563 gsvs_ring_size <= queue->gsvs_ring_size &&
1564 !add_tess_rings && !add_sample_positions &&
1565 queue->initial_preamble_cs) {
1566 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1567 *initial_preamble_cs = queue->initial_preamble_cs;
1568 *continue_preamble_cs = queue->continue_preamble_cs;
1569 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1570 *continue_preamble_cs = NULL;
1571 return VK_SUCCESS;
1572 }
1573
1574 if (scratch_size > queue->scratch_size) {
1575 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1576 scratch_size,
1577 4096,
1578 RADEON_DOMAIN_VRAM,
1579 ring_bo_flags);
1580 if (!scratch_bo)
1581 goto fail;
1582 } else
1583 scratch_bo = queue->scratch_bo;
1584
1585 if (compute_scratch_size > queue->compute_scratch_size) {
1586 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1587 compute_scratch_size,
1588 4096,
1589 RADEON_DOMAIN_VRAM,
1590 ring_bo_flags);
1591 if (!compute_scratch_bo)
1592 goto fail;
1593
1594 } else
1595 compute_scratch_bo = queue->compute_scratch_bo;
1596
1597 if (esgs_ring_size > queue->esgs_ring_size) {
1598 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1599 esgs_ring_size,
1600 4096,
1601 RADEON_DOMAIN_VRAM,
1602 ring_bo_flags);
1603 if (!esgs_ring_bo)
1604 goto fail;
1605 } else {
1606 esgs_ring_bo = queue->esgs_ring_bo;
1607 esgs_ring_size = queue->esgs_ring_size;
1608 }
1609
1610 if (gsvs_ring_size > queue->gsvs_ring_size) {
1611 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1612 gsvs_ring_size,
1613 4096,
1614 RADEON_DOMAIN_VRAM,
1615 ring_bo_flags);
1616 if (!gsvs_ring_bo)
1617 goto fail;
1618 } else {
1619 gsvs_ring_bo = queue->gsvs_ring_bo;
1620 gsvs_ring_size = queue->gsvs_ring_size;
1621 }
1622
1623 if (add_tess_rings) {
1624 tess_factor_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1625 tess_factor_ring_size,
1626 256,
1627 RADEON_DOMAIN_VRAM,
1628 ring_bo_flags);
1629 if (!tess_factor_ring_bo)
1630 goto fail;
1631 tess_offchip_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1632 tess_offchip_ring_size,
1633 256,
1634 RADEON_DOMAIN_VRAM,
1635 ring_bo_flags);
1636 if (!tess_offchip_ring_bo)
1637 goto fail;
1638 } else {
1639 tess_factor_ring_bo = queue->tess_factor_ring_bo;
1640 tess_offchip_ring_bo = queue->tess_offchip_ring_bo;
1641 }
1642
1643 if (scratch_bo != queue->scratch_bo ||
1644 esgs_ring_bo != queue->esgs_ring_bo ||
1645 gsvs_ring_bo != queue->gsvs_ring_bo ||
1646 tess_factor_ring_bo != queue->tess_factor_ring_bo ||
1647 tess_offchip_ring_bo != queue->tess_offchip_ring_bo || add_sample_positions) {
1648 uint32_t size = 0;
1649 if (gsvs_ring_bo || esgs_ring_bo ||
1650 tess_factor_ring_bo || tess_offchip_ring_bo || add_sample_positions) {
1651 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
1652 if (add_sample_positions)
1653 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1654 }
1655 else if (scratch_bo)
1656 size = 8; /* 2 dword */
1657
1658 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1659 size,
1660 4096,
1661 RADEON_DOMAIN_VRAM,
1662 RADEON_FLAG_CPU_ACCESS |
1663 RADEON_FLAG_NO_INTERPROCESS_SHARING |
1664 RADEON_FLAG_READ_ONLY);
1665 if (!descriptor_bo)
1666 goto fail;
1667 } else
1668 descriptor_bo = queue->descriptor_bo;
1669
1670 for(int i = 0; i < 3; ++i) {
1671 struct radeon_winsys_cs *cs = NULL;
1672 cs = queue->device->ws->cs_create(queue->device->ws,
1673 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1674 if (!cs)
1675 goto fail;
1676
1677 dest_cs[i] = cs;
1678
1679 if (scratch_bo)
1680 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo, 8);
1681
1682 if (esgs_ring_bo)
1683 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo, 8);
1684
1685 if (gsvs_ring_bo)
1686 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo, 8);
1687
1688 if (tess_factor_ring_bo)
1689 radv_cs_add_buffer(queue->device->ws, cs, tess_factor_ring_bo, 8);
1690
1691 if (tess_offchip_ring_bo)
1692 radv_cs_add_buffer(queue->device->ws, cs, tess_offchip_ring_bo, 8);
1693
1694 if (descriptor_bo)
1695 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo, 8);
1696
1697 if (descriptor_bo != queue->descriptor_bo) {
1698 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1699
1700 if (scratch_bo) {
1701 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
1702 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1703 S_008F04_SWIZZLE_ENABLE(1);
1704 map[0] = scratch_va;
1705 map[1] = rsrc1;
1706 }
1707
1708 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo ||
1709 add_sample_positions)
1710 fill_geom_tess_rings(queue, map, add_sample_positions,
1711 esgs_ring_size, esgs_ring_bo,
1712 gsvs_ring_size, gsvs_ring_bo,
1713 tess_factor_ring_size, tess_factor_ring_bo,
1714 tess_offchip_ring_size, tess_offchip_ring_bo);
1715
1716 queue->device->ws->buffer_unmap(descriptor_bo);
1717 }
1718
1719 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo) {
1720 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1721 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1722 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1723 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1724 }
1725
1726 if (esgs_ring_bo || gsvs_ring_bo) {
1727 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1728 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1729 radeon_emit(cs, esgs_ring_size >> 8);
1730 radeon_emit(cs, gsvs_ring_size >> 8);
1731 } else {
1732 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1733 radeon_emit(cs, esgs_ring_size >> 8);
1734 radeon_emit(cs, gsvs_ring_size >> 8);
1735 }
1736 }
1737
1738 if (tess_factor_ring_bo) {
1739 uint64_t tf_va = radv_buffer_get_va(tess_factor_ring_bo);
1740 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1741 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1742 S_030938_SIZE(tess_factor_ring_size / 4));
1743 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1744 tf_va >> 8);
1745 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1746 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1747 tf_va >> 40);
1748 }
1749 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
1750 } else {
1751 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1752 S_008988_SIZE(tess_factor_ring_size / 4));
1753 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1754 tf_va >> 8);
1755 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1756 hs_offchip_param);
1757 }
1758 }
1759
1760 if (descriptor_bo) {
1761 uint64_t va = radv_buffer_get_va(descriptor_bo);
1762 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1763 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1764 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1765 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
1766 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
1767
1768 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1769 radeon_set_sh_reg_seq(cs, regs[i], 2);
1770 radeon_emit(cs, va);
1771 radeon_emit(cs, va >> 32);
1772 }
1773 } else {
1774 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1775 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1776 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1777 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1778 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1779 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1780
1781 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1782 radeon_set_sh_reg_seq(cs, regs[i], 2);
1783 radeon_emit(cs, va);
1784 radeon_emit(cs, va >> 32);
1785 }
1786 }
1787 }
1788
1789 if (compute_scratch_bo) {
1790 uint64_t scratch_va = radv_buffer_get_va(compute_scratch_bo);
1791 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1792 S_008F04_SWIZZLE_ENABLE(1);
1793
1794 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo, 8);
1795
1796 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1797 radeon_emit(cs, scratch_va);
1798 radeon_emit(cs, rsrc1);
1799 }
1800
1801 if (i == 0) {
1802 si_cs_emit_cache_flush(cs,
1803 queue->device->physical_device->rad_info.chip_class,
1804 NULL, 0,
1805 queue->queue_family_index == RING_COMPUTE &&
1806 queue->device->physical_device->rad_info.chip_class >= CIK,
1807 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
1808 RADV_CMD_FLAG_INV_ICACHE |
1809 RADV_CMD_FLAG_INV_SMEM_L1 |
1810 RADV_CMD_FLAG_INV_VMEM_L1 |
1811 RADV_CMD_FLAG_INV_GLOBAL_L2);
1812 } else if (i == 1) {
1813 si_cs_emit_cache_flush(cs,
1814 queue->device->physical_device->rad_info.chip_class,
1815 NULL, 0,
1816 queue->queue_family_index == RING_COMPUTE &&
1817 queue->device->physical_device->rad_info.chip_class >= CIK,
1818 RADV_CMD_FLAG_INV_ICACHE |
1819 RADV_CMD_FLAG_INV_SMEM_L1 |
1820 RADV_CMD_FLAG_INV_VMEM_L1 |
1821 RADV_CMD_FLAG_INV_GLOBAL_L2);
1822 }
1823
1824 if (!queue->device->ws->cs_finalize(cs))
1825 goto fail;
1826 }
1827
1828 if (queue->initial_full_flush_preamble_cs)
1829 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1830
1831 if (queue->initial_preamble_cs)
1832 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1833
1834 if (queue->continue_preamble_cs)
1835 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1836
1837 queue->initial_full_flush_preamble_cs = dest_cs[0];
1838 queue->initial_preamble_cs = dest_cs[1];
1839 queue->continue_preamble_cs = dest_cs[2];
1840
1841 if (scratch_bo != queue->scratch_bo) {
1842 if (queue->scratch_bo)
1843 queue->device->ws->buffer_destroy(queue->scratch_bo);
1844 queue->scratch_bo = scratch_bo;
1845 queue->scratch_size = scratch_size;
1846 }
1847
1848 if (compute_scratch_bo != queue->compute_scratch_bo) {
1849 if (queue->compute_scratch_bo)
1850 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1851 queue->compute_scratch_bo = compute_scratch_bo;
1852 queue->compute_scratch_size = compute_scratch_size;
1853 }
1854
1855 if (esgs_ring_bo != queue->esgs_ring_bo) {
1856 if (queue->esgs_ring_bo)
1857 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1858 queue->esgs_ring_bo = esgs_ring_bo;
1859 queue->esgs_ring_size = esgs_ring_size;
1860 }
1861
1862 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
1863 if (queue->gsvs_ring_bo)
1864 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1865 queue->gsvs_ring_bo = gsvs_ring_bo;
1866 queue->gsvs_ring_size = gsvs_ring_size;
1867 }
1868
1869 if (tess_factor_ring_bo != queue->tess_factor_ring_bo) {
1870 queue->tess_factor_ring_bo = tess_factor_ring_bo;
1871 }
1872
1873 if (tess_offchip_ring_bo != queue->tess_offchip_ring_bo) {
1874 queue->tess_offchip_ring_bo = tess_offchip_ring_bo;
1875 queue->has_tess_rings = true;
1876 }
1877
1878 if (descriptor_bo != queue->descriptor_bo) {
1879 if (queue->descriptor_bo)
1880 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1881
1882 queue->descriptor_bo = descriptor_bo;
1883 }
1884
1885 if (add_sample_positions)
1886 queue->has_sample_positions = true;
1887
1888 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1889 *initial_preamble_cs = queue->initial_preamble_cs;
1890 *continue_preamble_cs = queue->continue_preamble_cs;
1891 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1892 *continue_preamble_cs = NULL;
1893 return VK_SUCCESS;
1894 fail:
1895 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
1896 if (dest_cs[i])
1897 queue->device->ws->cs_destroy(dest_cs[i]);
1898 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
1899 queue->device->ws->buffer_destroy(descriptor_bo);
1900 if (scratch_bo && scratch_bo != queue->scratch_bo)
1901 queue->device->ws->buffer_destroy(scratch_bo);
1902 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
1903 queue->device->ws->buffer_destroy(compute_scratch_bo);
1904 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
1905 queue->device->ws->buffer_destroy(esgs_ring_bo);
1906 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
1907 queue->device->ws->buffer_destroy(gsvs_ring_bo);
1908 if (tess_factor_ring_bo && tess_factor_ring_bo != queue->tess_factor_ring_bo)
1909 queue->device->ws->buffer_destroy(tess_factor_ring_bo);
1910 if (tess_offchip_ring_bo && tess_offchip_ring_bo != queue->tess_offchip_ring_bo)
1911 queue->device->ws->buffer_destroy(tess_offchip_ring_bo);
1912 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
1913 }
1914
1915 static VkResult radv_alloc_sem_counts(struct radv_winsys_sem_counts *counts,
1916 int num_sems,
1917 const VkSemaphore *sems,
1918 VkFence _fence,
1919 bool reset_temp)
1920 {
1921 int syncobj_idx = 0, sem_idx = 0;
1922
1923 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
1924 return VK_SUCCESS;
1925
1926 for (uint32_t i = 0; i < num_sems; i++) {
1927 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1928
1929 if (sem->temp_syncobj || sem->syncobj)
1930 counts->syncobj_count++;
1931 else
1932 counts->sem_count++;
1933 }
1934
1935 if (_fence != VK_NULL_HANDLE) {
1936 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1937 if (fence->temp_syncobj || fence->syncobj)
1938 counts->syncobj_count++;
1939 }
1940
1941 if (counts->syncobj_count) {
1942 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
1943 if (!counts->syncobj)
1944 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1945 }
1946
1947 if (counts->sem_count) {
1948 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
1949 if (!counts->sem) {
1950 free(counts->syncobj);
1951 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1952 }
1953 }
1954
1955 for (uint32_t i = 0; i < num_sems; i++) {
1956 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1957
1958 if (sem->temp_syncobj) {
1959 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
1960 }
1961 else if (sem->syncobj)
1962 counts->syncobj[syncobj_idx++] = sem->syncobj;
1963 else {
1964 assert(sem->sem);
1965 counts->sem[sem_idx++] = sem->sem;
1966 }
1967 }
1968
1969 if (_fence != VK_NULL_HANDLE) {
1970 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1971 if (fence->temp_syncobj)
1972 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
1973 else if (fence->syncobj)
1974 counts->syncobj[syncobj_idx++] = fence->syncobj;
1975 }
1976
1977 return VK_SUCCESS;
1978 }
1979
1980 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
1981 {
1982 free(sem_info->wait.syncobj);
1983 free(sem_info->wait.sem);
1984 free(sem_info->signal.syncobj);
1985 free(sem_info->signal.sem);
1986 }
1987
1988
1989 static void radv_free_temp_syncobjs(struct radv_device *device,
1990 int num_sems,
1991 const VkSemaphore *sems)
1992 {
1993 for (uint32_t i = 0; i < num_sems; i++) {
1994 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1995
1996 if (sem->temp_syncobj) {
1997 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
1998 sem->temp_syncobj = 0;
1999 }
2000 }
2001 }
2002
2003 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
2004 int num_wait_sems,
2005 const VkSemaphore *wait_sems,
2006 int num_signal_sems,
2007 const VkSemaphore *signal_sems,
2008 VkFence fence)
2009 {
2010 VkResult ret;
2011 memset(sem_info, 0, sizeof(*sem_info));
2012
2013 ret = radv_alloc_sem_counts(&sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2014 if (ret)
2015 return ret;
2016 ret = radv_alloc_sem_counts(&sem_info->signal, num_signal_sems, signal_sems, fence, false);
2017 if (ret)
2018 radv_free_sem_info(sem_info);
2019
2020 /* caller can override these */
2021 sem_info->cs_emit_wait = true;
2022 sem_info->cs_emit_signal = true;
2023 return ret;
2024 }
2025
2026 /* Signals fence as soon as all the work currently put on queue is done. */
2027 static VkResult radv_signal_fence(struct radv_queue *queue,
2028 struct radv_fence *fence)
2029 {
2030 int ret;
2031 VkResult result;
2032 struct radv_winsys_sem_info sem_info;
2033
2034 result = radv_alloc_sem_info(&sem_info, 0, NULL, 0, NULL,
2035 radv_fence_to_handle(fence));
2036 if (result != VK_SUCCESS)
2037 return result;
2038
2039 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2040 &queue->device->empty_cs[queue->queue_family_index],
2041 1, NULL, NULL, &sem_info,
2042 false, fence->fence);
2043 radv_free_sem_info(&sem_info);
2044
2045 /* TODO: find a better error */
2046 if (ret)
2047 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2048
2049 return VK_SUCCESS;
2050 }
2051
2052 VkResult radv_QueueSubmit(
2053 VkQueue _queue,
2054 uint32_t submitCount,
2055 const VkSubmitInfo* pSubmits,
2056 VkFence _fence)
2057 {
2058 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2059 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2060 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2061 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2062 int ret;
2063 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2064 uint32_t scratch_size = 0;
2065 uint32_t compute_scratch_size = 0;
2066 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2067 struct radeon_winsys_cs *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2068 VkResult result;
2069 bool fence_emitted = false;
2070 bool tess_rings_needed = false;
2071 bool sample_positions_needed = false;
2072
2073 /* Do this first so failing to allocate scratch buffers can't result in
2074 * partially executed submissions. */
2075 for (uint32_t i = 0; i < submitCount; i++) {
2076 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2077 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2078 pSubmits[i].pCommandBuffers[j]);
2079
2080 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2081 compute_scratch_size = MAX2(compute_scratch_size,
2082 cmd_buffer->compute_scratch_size_needed);
2083 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2084 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2085 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2086 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2087 }
2088 }
2089
2090 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2091 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2092 sample_positions_needed, &initial_flush_preamble_cs,
2093 &initial_preamble_cs, &continue_preamble_cs);
2094 if (result != VK_SUCCESS)
2095 return result;
2096
2097 for (uint32_t i = 0; i < submitCount; i++) {
2098 struct radeon_winsys_cs **cs_array;
2099 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2100 bool can_patch = true;
2101 uint32_t advance;
2102 struct radv_winsys_sem_info sem_info;
2103
2104 result = radv_alloc_sem_info(&sem_info,
2105 pSubmits[i].waitSemaphoreCount,
2106 pSubmits[i].pWaitSemaphores,
2107 pSubmits[i].signalSemaphoreCount,
2108 pSubmits[i].pSignalSemaphores,
2109 _fence);
2110 if (result != VK_SUCCESS)
2111 return result;
2112
2113 if (!pSubmits[i].commandBufferCount) {
2114 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2115 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2116 &queue->device->empty_cs[queue->queue_family_index],
2117 1, NULL, NULL,
2118 &sem_info,
2119 false, base_fence);
2120 if (ret) {
2121 radv_loge("failed to submit CS %d\n", i);
2122 abort();
2123 }
2124 fence_emitted = true;
2125 }
2126 radv_free_sem_info(&sem_info);
2127 continue;
2128 }
2129
2130 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
2131 (pSubmits[i].commandBufferCount));
2132
2133 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2134 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2135 pSubmits[i].pCommandBuffers[j]);
2136 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2137
2138 cs_array[j] = cmd_buffer->cs;
2139 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2140 can_patch = false;
2141
2142 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2143 }
2144
2145 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2146 struct radeon_winsys_cs *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2147 advance = MIN2(max_cs_submission,
2148 pSubmits[i].commandBufferCount - j);
2149
2150 if (queue->device->trace_bo)
2151 *queue->device->trace_id_ptr = 0;
2152
2153 sem_info.cs_emit_wait = j == 0;
2154 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2155
2156 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2157 advance, initial_preamble, continue_preamble_cs,
2158 &sem_info,
2159 can_patch, base_fence);
2160
2161 if (ret) {
2162 radv_loge("failed to submit CS %d\n", i);
2163 abort();
2164 }
2165 fence_emitted = true;
2166 if (queue->device->trace_bo) {
2167 radv_check_gpu_hangs(queue, cs_array[j]);
2168 }
2169 }
2170
2171 radv_free_temp_syncobjs(queue->device,
2172 pSubmits[i].waitSemaphoreCount,
2173 pSubmits[i].pWaitSemaphores);
2174 radv_free_sem_info(&sem_info);
2175 free(cs_array);
2176 }
2177
2178 if (fence) {
2179 if (!fence_emitted) {
2180 radv_signal_fence(queue, fence);
2181 }
2182 fence->submitted = true;
2183 }
2184
2185 return VK_SUCCESS;
2186 }
2187
2188 VkResult radv_QueueWaitIdle(
2189 VkQueue _queue)
2190 {
2191 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2192
2193 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2194 radv_queue_family_to_ring(queue->queue_family_index),
2195 queue->queue_idx);
2196 return VK_SUCCESS;
2197 }
2198
2199 VkResult radv_DeviceWaitIdle(
2200 VkDevice _device)
2201 {
2202 RADV_FROM_HANDLE(radv_device, device, _device);
2203
2204 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2205 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2206 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2207 }
2208 }
2209 return VK_SUCCESS;
2210 }
2211
2212 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2213 VkInstance instance,
2214 const char* pName)
2215 {
2216 return radv_lookup_entrypoint(pName);
2217 }
2218
2219 /* The loader wants us to expose a second GetInstanceProcAddr function
2220 * to work around certain LD_PRELOAD issues seen in apps.
2221 */
2222 PUBLIC
2223 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2224 VkInstance instance,
2225 const char* pName);
2226
2227 PUBLIC
2228 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2229 VkInstance instance,
2230 const char* pName)
2231 {
2232 return radv_GetInstanceProcAddr(instance, pName);
2233 }
2234
2235 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2236 VkDevice device,
2237 const char* pName)
2238 {
2239 return radv_lookup_entrypoint(pName);
2240 }
2241
2242 bool radv_get_memory_fd(struct radv_device *device,
2243 struct radv_device_memory *memory,
2244 int *pFD)
2245 {
2246 struct radeon_bo_metadata metadata;
2247
2248 if (memory->image) {
2249 radv_init_metadata(device, memory->image, &metadata);
2250 device->ws->buffer_set_metadata(memory->bo, &metadata);
2251 }
2252
2253 return device->ws->buffer_get_fd(device->ws, memory->bo,
2254 pFD);
2255 }
2256
2257 static VkResult radv_alloc_memory(struct radv_device *device,
2258 const VkMemoryAllocateInfo* pAllocateInfo,
2259 const VkAllocationCallbacks* pAllocator,
2260 VkDeviceMemory* pMem)
2261 {
2262 struct radv_device_memory *mem;
2263 VkResult result;
2264 enum radeon_bo_domain domain;
2265 uint32_t flags = 0;
2266 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
2267
2268 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2269
2270 if (pAllocateInfo->allocationSize == 0) {
2271 /* Apparently, this is allowed */
2272 *pMem = VK_NULL_HANDLE;
2273 return VK_SUCCESS;
2274 }
2275
2276 const VkImportMemoryFdInfoKHR *import_info =
2277 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2278 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2279 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2280 const VkExportMemoryAllocateInfoKHR *export_info =
2281 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO_KHR);
2282 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
2283 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
2284
2285 const struct wsi_memory_allocate_info *wsi_info =
2286 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
2287
2288 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2289 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2290 if (mem == NULL)
2291 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2292
2293 if (wsi_info && wsi_info->implicit_sync)
2294 flags |= RADEON_FLAG_IMPLICIT_SYNC;
2295
2296 if (dedicate_info) {
2297 mem->image = radv_image_from_handle(dedicate_info->image);
2298 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2299 } else {
2300 mem->image = NULL;
2301 mem->buffer = NULL;
2302 }
2303
2304 mem->user_ptr = NULL;
2305
2306 if (import_info) {
2307 assert(import_info->handleType ==
2308 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
2309 import_info->handleType ==
2310 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
2311 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2312 NULL, NULL);
2313 if (!mem->bo) {
2314 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2315 goto fail;
2316 } else {
2317 close(import_info->fd);
2318 goto out_success;
2319 }
2320 }
2321
2322 if (host_ptr_info) {
2323 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
2324 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
2325 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
2326 pAllocateInfo->allocationSize);
2327 if (!mem->bo) {
2328 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2329 goto fail;
2330 } else {
2331 mem->user_ptr = host_ptr_info->pHostPointer;
2332 goto out_success;
2333 }
2334 }
2335
2336 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2337 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2338 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
2339 domain = RADEON_DOMAIN_GTT;
2340 else
2341 domain = RADEON_DOMAIN_VRAM;
2342
2343 if (mem_type_index == RADV_MEM_TYPE_VRAM)
2344 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2345 else
2346 flags |= RADEON_FLAG_CPU_ACCESS;
2347
2348 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2349 flags |= RADEON_FLAG_GTT_WC;
2350
2351 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
2352 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
2353
2354 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2355 domain, flags);
2356
2357 if (!mem->bo) {
2358 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2359 goto fail;
2360 }
2361 mem->type_index = mem_type_index;
2362 out_success:
2363 *pMem = radv_device_memory_to_handle(mem);
2364
2365 return VK_SUCCESS;
2366
2367 fail:
2368 vk_free2(&device->alloc, pAllocator, mem);
2369
2370 return result;
2371 }
2372
2373 VkResult radv_AllocateMemory(
2374 VkDevice _device,
2375 const VkMemoryAllocateInfo* pAllocateInfo,
2376 const VkAllocationCallbacks* pAllocator,
2377 VkDeviceMemory* pMem)
2378 {
2379 RADV_FROM_HANDLE(radv_device, device, _device);
2380 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
2381 }
2382
2383 void radv_FreeMemory(
2384 VkDevice _device,
2385 VkDeviceMemory _mem,
2386 const VkAllocationCallbacks* pAllocator)
2387 {
2388 RADV_FROM_HANDLE(radv_device, device, _device);
2389 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2390
2391 if (mem == NULL)
2392 return;
2393
2394 device->ws->buffer_destroy(mem->bo);
2395 mem->bo = NULL;
2396
2397 vk_free2(&device->alloc, pAllocator, mem);
2398 }
2399
2400 VkResult radv_MapMemory(
2401 VkDevice _device,
2402 VkDeviceMemory _memory,
2403 VkDeviceSize offset,
2404 VkDeviceSize size,
2405 VkMemoryMapFlags flags,
2406 void** ppData)
2407 {
2408 RADV_FROM_HANDLE(radv_device, device, _device);
2409 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2410
2411 if (mem == NULL) {
2412 *ppData = NULL;
2413 return VK_SUCCESS;
2414 }
2415
2416 if (mem->user_ptr)
2417 *ppData = mem->user_ptr;
2418 else
2419 *ppData = device->ws->buffer_map(mem->bo);
2420
2421 if (*ppData) {
2422 *ppData += offset;
2423 return VK_SUCCESS;
2424 }
2425
2426 return vk_error(VK_ERROR_MEMORY_MAP_FAILED);
2427 }
2428
2429 void radv_UnmapMemory(
2430 VkDevice _device,
2431 VkDeviceMemory _memory)
2432 {
2433 RADV_FROM_HANDLE(radv_device, device, _device);
2434 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2435
2436 if (mem == NULL)
2437 return;
2438
2439 if (mem->user_ptr == NULL)
2440 device->ws->buffer_unmap(mem->bo);
2441 }
2442
2443 VkResult radv_FlushMappedMemoryRanges(
2444 VkDevice _device,
2445 uint32_t memoryRangeCount,
2446 const VkMappedMemoryRange* pMemoryRanges)
2447 {
2448 return VK_SUCCESS;
2449 }
2450
2451 VkResult radv_InvalidateMappedMemoryRanges(
2452 VkDevice _device,
2453 uint32_t memoryRangeCount,
2454 const VkMappedMemoryRange* pMemoryRanges)
2455 {
2456 return VK_SUCCESS;
2457 }
2458
2459 void radv_GetBufferMemoryRequirements(
2460 VkDevice _device,
2461 VkBuffer _buffer,
2462 VkMemoryRequirements* pMemoryRequirements)
2463 {
2464 RADV_FROM_HANDLE(radv_device, device, _device);
2465 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2466
2467 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2468
2469 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2470 pMemoryRequirements->alignment = 4096;
2471 else
2472 pMemoryRequirements->alignment = 16;
2473
2474 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2475 }
2476
2477 void radv_GetBufferMemoryRequirements2KHR(
2478 VkDevice device,
2479 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2480 VkMemoryRequirements2KHR* pMemoryRequirements)
2481 {
2482 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2483 &pMemoryRequirements->memoryRequirements);
2484 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
2485 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2486 switch (ext->sType) {
2487 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2488 VkMemoryDedicatedRequirementsKHR *req =
2489 (VkMemoryDedicatedRequirementsKHR *) ext;
2490 req->requiresDedicatedAllocation = buffer->shareable;
2491 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2492 break;
2493 }
2494 default:
2495 break;
2496 }
2497 }
2498 }
2499
2500 void radv_GetImageMemoryRequirements(
2501 VkDevice _device,
2502 VkImage _image,
2503 VkMemoryRequirements* pMemoryRequirements)
2504 {
2505 RADV_FROM_HANDLE(radv_device, device, _device);
2506 RADV_FROM_HANDLE(radv_image, image, _image);
2507
2508 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2509
2510 pMemoryRequirements->size = image->size;
2511 pMemoryRequirements->alignment = image->alignment;
2512 }
2513
2514 void radv_GetImageMemoryRequirements2KHR(
2515 VkDevice device,
2516 const VkImageMemoryRequirementsInfo2KHR* pInfo,
2517 VkMemoryRequirements2KHR* pMemoryRequirements)
2518 {
2519 radv_GetImageMemoryRequirements(device, pInfo->image,
2520 &pMemoryRequirements->memoryRequirements);
2521
2522 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
2523
2524 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2525 switch (ext->sType) {
2526 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2527 VkMemoryDedicatedRequirementsKHR *req =
2528 (VkMemoryDedicatedRequirementsKHR *) ext;
2529 req->requiresDedicatedAllocation = image->shareable;
2530 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2531 break;
2532 }
2533 default:
2534 break;
2535 }
2536 }
2537 }
2538
2539 void radv_GetImageSparseMemoryRequirements(
2540 VkDevice device,
2541 VkImage image,
2542 uint32_t* pSparseMemoryRequirementCount,
2543 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2544 {
2545 stub();
2546 }
2547
2548 void radv_GetImageSparseMemoryRequirements2KHR(
2549 VkDevice device,
2550 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
2551 uint32_t* pSparseMemoryRequirementCount,
2552 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
2553 {
2554 stub();
2555 }
2556
2557 void radv_GetDeviceMemoryCommitment(
2558 VkDevice device,
2559 VkDeviceMemory memory,
2560 VkDeviceSize* pCommittedMemoryInBytes)
2561 {
2562 *pCommittedMemoryInBytes = 0;
2563 }
2564
2565 VkResult radv_BindBufferMemory2KHR(VkDevice device,
2566 uint32_t bindInfoCount,
2567 const VkBindBufferMemoryInfoKHR *pBindInfos)
2568 {
2569 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2570 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2571 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
2572
2573 if (mem) {
2574 buffer->bo = mem->bo;
2575 buffer->offset = pBindInfos[i].memoryOffset;
2576 } else {
2577 buffer->bo = NULL;
2578 }
2579 }
2580 return VK_SUCCESS;
2581 }
2582
2583 VkResult radv_BindBufferMemory(
2584 VkDevice device,
2585 VkBuffer buffer,
2586 VkDeviceMemory memory,
2587 VkDeviceSize memoryOffset)
2588 {
2589 const VkBindBufferMemoryInfoKHR info = {
2590 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2591 .buffer = buffer,
2592 .memory = memory,
2593 .memoryOffset = memoryOffset
2594 };
2595
2596 return radv_BindBufferMemory2KHR(device, 1, &info);
2597 }
2598
2599 VkResult radv_BindImageMemory2KHR(VkDevice device,
2600 uint32_t bindInfoCount,
2601 const VkBindImageMemoryInfoKHR *pBindInfos)
2602 {
2603 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2604 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2605 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
2606
2607 if (mem) {
2608 image->bo = mem->bo;
2609 image->offset = pBindInfos[i].memoryOffset;
2610 } else {
2611 image->bo = NULL;
2612 image->offset = 0;
2613 }
2614 }
2615 return VK_SUCCESS;
2616 }
2617
2618
2619 VkResult radv_BindImageMemory(
2620 VkDevice device,
2621 VkImage image,
2622 VkDeviceMemory memory,
2623 VkDeviceSize memoryOffset)
2624 {
2625 const VkBindImageMemoryInfoKHR info = {
2626 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2627 .image = image,
2628 .memory = memory,
2629 .memoryOffset = memoryOffset
2630 };
2631
2632 return radv_BindImageMemory2KHR(device, 1, &info);
2633 }
2634
2635
2636 static void
2637 radv_sparse_buffer_bind_memory(struct radv_device *device,
2638 const VkSparseBufferMemoryBindInfo *bind)
2639 {
2640 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
2641
2642 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2643 struct radv_device_memory *mem = NULL;
2644
2645 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2646 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2647
2648 device->ws->buffer_virtual_bind(buffer->bo,
2649 bind->pBinds[i].resourceOffset,
2650 bind->pBinds[i].size,
2651 mem ? mem->bo : NULL,
2652 bind->pBinds[i].memoryOffset);
2653 }
2654 }
2655
2656 static void
2657 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
2658 const VkSparseImageOpaqueMemoryBindInfo *bind)
2659 {
2660 RADV_FROM_HANDLE(radv_image, image, bind->image);
2661
2662 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2663 struct radv_device_memory *mem = NULL;
2664
2665 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2666 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2667
2668 device->ws->buffer_virtual_bind(image->bo,
2669 bind->pBinds[i].resourceOffset,
2670 bind->pBinds[i].size,
2671 mem ? mem->bo : NULL,
2672 bind->pBinds[i].memoryOffset);
2673 }
2674 }
2675
2676 VkResult radv_QueueBindSparse(
2677 VkQueue _queue,
2678 uint32_t bindInfoCount,
2679 const VkBindSparseInfo* pBindInfo,
2680 VkFence _fence)
2681 {
2682 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2683 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2684 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2685 bool fence_emitted = false;
2686
2687 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2688 struct radv_winsys_sem_info sem_info;
2689 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
2690 radv_sparse_buffer_bind_memory(queue->device,
2691 pBindInfo[i].pBufferBinds + j);
2692 }
2693
2694 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
2695 radv_sparse_image_opaque_bind_memory(queue->device,
2696 pBindInfo[i].pImageOpaqueBinds + j);
2697 }
2698
2699 VkResult result;
2700 result = radv_alloc_sem_info(&sem_info,
2701 pBindInfo[i].waitSemaphoreCount,
2702 pBindInfo[i].pWaitSemaphores,
2703 pBindInfo[i].signalSemaphoreCount,
2704 pBindInfo[i].pSignalSemaphores,
2705 _fence);
2706 if (result != VK_SUCCESS)
2707 return result;
2708
2709 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
2710 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2711 &queue->device->empty_cs[queue->queue_family_index],
2712 1, NULL, NULL,
2713 &sem_info,
2714 false, base_fence);
2715 fence_emitted = true;
2716 if (fence)
2717 fence->submitted = true;
2718 }
2719
2720 radv_free_sem_info(&sem_info);
2721
2722 }
2723
2724 if (fence) {
2725 if (!fence_emitted) {
2726 radv_signal_fence(queue, fence);
2727 }
2728 fence->submitted = true;
2729 }
2730
2731 return VK_SUCCESS;
2732 }
2733
2734 VkResult radv_CreateFence(
2735 VkDevice _device,
2736 const VkFenceCreateInfo* pCreateInfo,
2737 const VkAllocationCallbacks* pAllocator,
2738 VkFence* pFence)
2739 {
2740 RADV_FROM_HANDLE(radv_device, device, _device);
2741 const VkExportFenceCreateInfoKHR *export =
2742 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO_KHR);
2743 VkExternalFenceHandleTypeFlagsKHR handleTypes =
2744 export ? export->handleTypes : 0;
2745
2746 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
2747 sizeof(*fence), 8,
2748 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2749
2750 if (!fence)
2751 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2752
2753 fence->submitted = false;
2754 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
2755 fence->temp_syncobj = 0;
2756 if (device->always_use_syncobj || handleTypes) {
2757 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
2758 if (ret) {
2759 vk_free2(&device->alloc, pAllocator, fence);
2760 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2761 }
2762 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
2763 device->ws->signal_syncobj(device->ws, fence->syncobj);
2764 }
2765 fence->fence = NULL;
2766 } else {
2767 fence->fence = device->ws->create_fence();
2768 if (!fence->fence) {
2769 vk_free2(&device->alloc, pAllocator, fence);
2770 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2771 }
2772 fence->syncobj = 0;
2773 }
2774
2775 *pFence = radv_fence_to_handle(fence);
2776
2777 return VK_SUCCESS;
2778 }
2779
2780 void radv_DestroyFence(
2781 VkDevice _device,
2782 VkFence _fence,
2783 const VkAllocationCallbacks* pAllocator)
2784 {
2785 RADV_FROM_HANDLE(radv_device, device, _device);
2786 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2787
2788 if (!fence)
2789 return;
2790
2791 if (fence->temp_syncobj)
2792 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
2793 if (fence->syncobj)
2794 device->ws->destroy_syncobj(device->ws, fence->syncobj);
2795 if (fence->fence)
2796 device->ws->destroy_fence(fence->fence);
2797 vk_free2(&device->alloc, pAllocator, fence);
2798 }
2799
2800 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
2801 {
2802 uint64_t current_time;
2803 struct timespec tv;
2804
2805 clock_gettime(CLOCK_MONOTONIC, &tv);
2806 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
2807
2808 timeout = MIN2(UINT64_MAX - current_time, timeout);
2809
2810 return current_time + timeout;
2811 }
2812
2813 VkResult radv_WaitForFences(
2814 VkDevice _device,
2815 uint32_t fenceCount,
2816 const VkFence* pFences,
2817 VkBool32 waitAll,
2818 uint64_t timeout)
2819 {
2820 RADV_FROM_HANDLE(radv_device, device, _device);
2821 timeout = radv_get_absolute_timeout(timeout);
2822
2823 if (!waitAll && fenceCount > 1) {
2824 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
2825 }
2826
2827 for (uint32_t i = 0; i < fenceCount; ++i) {
2828 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2829 bool expired = false;
2830
2831 if (fence->temp_syncobj) {
2832 if (!device->ws->wait_syncobj(device->ws, fence->temp_syncobj, timeout))
2833 return VK_TIMEOUT;
2834 continue;
2835 }
2836
2837 if (fence->syncobj) {
2838 if (!device->ws->wait_syncobj(device->ws, fence->syncobj, timeout))
2839 return VK_TIMEOUT;
2840 continue;
2841 }
2842
2843 if (fence->signalled)
2844 continue;
2845
2846 if (!fence->submitted)
2847 return VK_TIMEOUT;
2848
2849 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
2850 if (!expired)
2851 return VK_TIMEOUT;
2852
2853 fence->signalled = true;
2854 }
2855
2856 return VK_SUCCESS;
2857 }
2858
2859 VkResult radv_ResetFences(VkDevice _device,
2860 uint32_t fenceCount,
2861 const VkFence *pFences)
2862 {
2863 RADV_FROM_HANDLE(radv_device, device, _device);
2864
2865 for (unsigned i = 0; i < fenceCount; ++i) {
2866 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2867 fence->submitted = fence->signalled = false;
2868
2869 /* Per spec, we first restore the permanent payload, and then reset, so
2870 * having a temp syncobj should not skip resetting the permanent syncobj. */
2871 if (fence->temp_syncobj) {
2872 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
2873 fence->temp_syncobj = 0;
2874 }
2875
2876 if (fence->syncobj) {
2877 device->ws->reset_syncobj(device->ws, fence->syncobj);
2878 }
2879 }
2880
2881 return VK_SUCCESS;
2882 }
2883
2884 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
2885 {
2886 RADV_FROM_HANDLE(radv_device, device, _device);
2887 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2888
2889 if (fence->temp_syncobj) {
2890 bool success = device->ws->wait_syncobj(device->ws, fence->temp_syncobj, 0);
2891 return success ? VK_SUCCESS : VK_NOT_READY;
2892 }
2893
2894 if (fence->syncobj) {
2895 bool success = device->ws->wait_syncobj(device->ws, fence->syncobj, 0);
2896 return success ? VK_SUCCESS : VK_NOT_READY;
2897 }
2898
2899 if (fence->signalled)
2900 return VK_SUCCESS;
2901 if (!fence->submitted)
2902 return VK_NOT_READY;
2903 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
2904 return VK_NOT_READY;
2905
2906 return VK_SUCCESS;
2907 }
2908
2909
2910 // Queue semaphore functions
2911
2912 VkResult radv_CreateSemaphore(
2913 VkDevice _device,
2914 const VkSemaphoreCreateInfo* pCreateInfo,
2915 const VkAllocationCallbacks* pAllocator,
2916 VkSemaphore* pSemaphore)
2917 {
2918 RADV_FROM_HANDLE(radv_device, device, _device);
2919 const VkExportSemaphoreCreateInfoKHR *export =
2920 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
2921 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
2922 export ? export->handleTypes : 0;
2923
2924 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
2925 sizeof(*sem), 8,
2926 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2927 if (!sem)
2928 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2929
2930 sem->temp_syncobj = 0;
2931 /* create a syncobject if we are going to export this semaphore */
2932 if (device->always_use_syncobj || handleTypes) {
2933 assert (device->physical_device->rad_info.has_syncobj);
2934 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
2935 if (ret) {
2936 vk_free2(&device->alloc, pAllocator, sem);
2937 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2938 }
2939 sem->sem = NULL;
2940 } else {
2941 sem->sem = device->ws->create_sem(device->ws);
2942 if (!sem->sem) {
2943 vk_free2(&device->alloc, pAllocator, sem);
2944 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2945 }
2946 sem->syncobj = 0;
2947 }
2948
2949 *pSemaphore = radv_semaphore_to_handle(sem);
2950 return VK_SUCCESS;
2951 }
2952
2953 void radv_DestroySemaphore(
2954 VkDevice _device,
2955 VkSemaphore _semaphore,
2956 const VkAllocationCallbacks* pAllocator)
2957 {
2958 RADV_FROM_HANDLE(radv_device, device, _device);
2959 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
2960 if (!_semaphore)
2961 return;
2962
2963 if (sem->syncobj)
2964 device->ws->destroy_syncobj(device->ws, sem->syncobj);
2965 else
2966 device->ws->destroy_sem(sem->sem);
2967 vk_free2(&device->alloc, pAllocator, sem);
2968 }
2969
2970 VkResult radv_CreateEvent(
2971 VkDevice _device,
2972 const VkEventCreateInfo* pCreateInfo,
2973 const VkAllocationCallbacks* pAllocator,
2974 VkEvent* pEvent)
2975 {
2976 RADV_FROM_HANDLE(radv_device, device, _device);
2977 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
2978 sizeof(*event), 8,
2979 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2980
2981 if (!event)
2982 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2983
2984 event->bo = device->ws->buffer_create(device->ws, 8, 8,
2985 RADEON_DOMAIN_GTT,
2986 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
2987 if (!event->bo) {
2988 vk_free2(&device->alloc, pAllocator, event);
2989 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2990 }
2991
2992 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
2993
2994 *pEvent = radv_event_to_handle(event);
2995
2996 return VK_SUCCESS;
2997 }
2998
2999 void radv_DestroyEvent(
3000 VkDevice _device,
3001 VkEvent _event,
3002 const VkAllocationCallbacks* pAllocator)
3003 {
3004 RADV_FROM_HANDLE(radv_device, device, _device);
3005 RADV_FROM_HANDLE(radv_event, event, _event);
3006
3007 if (!event)
3008 return;
3009 device->ws->buffer_destroy(event->bo);
3010 vk_free2(&device->alloc, pAllocator, event);
3011 }
3012
3013 VkResult radv_GetEventStatus(
3014 VkDevice _device,
3015 VkEvent _event)
3016 {
3017 RADV_FROM_HANDLE(radv_event, event, _event);
3018
3019 if (*event->map == 1)
3020 return VK_EVENT_SET;
3021 return VK_EVENT_RESET;
3022 }
3023
3024 VkResult radv_SetEvent(
3025 VkDevice _device,
3026 VkEvent _event)
3027 {
3028 RADV_FROM_HANDLE(radv_event, event, _event);
3029 *event->map = 1;
3030
3031 return VK_SUCCESS;
3032 }
3033
3034 VkResult radv_ResetEvent(
3035 VkDevice _device,
3036 VkEvent _event)
3037 {
3038 RADV_FROM_HANDLE(radv_event, event, _event);
3039 *event->map = 0;
3040
3041 return VK_SUCCESS;
3042 }
3043
3044 VkResult radv_CreateBuffer(
3045 VkDevice _device,
3046 const VkBufferCreateInfo* pCreateInfo,
3047 const VkAllocationCallbacks* pAllocator,
3048 VkBuffer* pBuffer)
3049 {
3050 RADV_FROM_HANDLE(radv_device, device, _device);
3051 struct radv_buffer *buffer;
3052
3053 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
3054
3055 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
3056 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3057 if (buffer == NULL)
3058 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3059
3060 buffer->size = pCreateInfo->size;
3061 buffer->usage = pCreateInfo->usage;
3062 buffer->bo = NULL;
3063 buffer->offset = 0;
3064 buffer->flags = pCreateInfo->flags;
3065
3066 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
3067 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR) != NULL;
3068
3069 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
3070 buffer->bo = device->ws->buffer_create(device->ws,
3071 align64(buffer->size, 4096),
3072 4096, 0, RADEON_FLAG_VIRTUAL);
3073 if (!buffer->bo) {
3074 vk_free2(&device->alloc, pAllocator, buffer);
3075 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
3076 }
3077 }
3078
3079 *pBuffer = radv_buffer_to_handle(buffer);
3080
3081 return VK_SUCCESS;
3082 }
3083
3084 void radv_DestroyBuffer(
3085 VkDevice _device,
3086 VkBuffer _buffer,
3087 const VkAllocationCallbacks* pAllocator)
3088 {
3089 RADV_FROM_HANDLE(radv_device, device, _device);
3090 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3091
3092 if (!buffer)
3093 return;
3094
3095 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3096 device->ws->buffer_destroy(buffer->bo);
3097
3098 vk_free2(&device->alloc, pAllocator, buffer);
3099 }
3100
3101 static inline unsigned
3102 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
3103 {
3104 if (stencil)
3105 return image->surface.u.legacy.stencil_tiling_index[level];
3106 else
3107 return image->surface.u.legacy.tiling_index[level];
3108 }
3109
3110 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
3111 {
3112 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
3113 }
3114
3115 static void
3116 radv_initialise_color_surface(struct radv_device *device,
3117 struct radv_color_buffer_info *cb,
3118 struct radv_image_view *iview)
3119 {
3120 const struct vk_format_description *desc;
3121 unsigned ntype, format, swap, endian;
3122 unsigned blend_clamp = 0, blend_bypass = 0;
3123 uint64_t va;
3124 const struct radeon_surf *surf = &iview->image->surface;
3125
3126 desc = vk_format_description(iview->vk_format);
3127
3128 memset(cb, 0, sizeof(*cb));
3129
3130 /* Intensity is implemented as Red, so treat it that way. */
3131 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
3132
3133 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3134
3135 cb->cb_color_base = va >> 8;
3136
3137 if (device->physical_device->rad_info.chip_class >= GFX9) {
3138 struct gfx9_surf_meta_flags meta;
3139 if (iview->image->dcc_offset)
3140 meta = iview->image->surface.u.gfx9.dcc;
3141 else
3142 meta = iview->image->surface.u.gfx9.cmask;
3143
3144 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3145 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
3146 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3147 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3148
3149 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
3150 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3151 } else {
3152 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
3153 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3154
3155 cb->cb_color_base += level_info->offset >> 8;
3156 if (level_info->mode == RADEON_SURF_MODE_2D)
3157 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3158
3159 pitch_tile_max = level_info->nblk_x / 8 - 1;
3160 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
3161 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
3162
3163 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3164 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3165 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
3166
3167 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3168
3169 if (iview->image->fmask.size) {
3170 if (device->physical_device->rad_info.chip_class >= CIK)
3171 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
3172 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
3173 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
3174 } else {
3175 /* This must be set for fast clear to work without FMASK. */
3176 if (device->physical_device->rad_info.chip_class >= CIK)
3177 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3178 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3179 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3180 }
3181 }
3182
3183 /* CMASK variables */
3184 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3185 va += iview->image->cmask.offset;
3186 cb->cb_color_cmask = va >> 8;
3187
3188 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3189 va += iview->image->dcc_offset;
3190 cb->cb_dcc_base = va >> 8;
3191 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
3192
3193 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3194 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3195 S_028C6C_SLICE_MAX(max_slice);
3196
3197 if (iview->image->info.samples > 1) {
3198 unsigned log_samples = util_logbase2(iview->image->info.samples);
3199
3200 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3201 S_028C74_NUM_FRAGMENTS(log_samples);
3202 }
3203
3204 if (iview->image->fmask.size) {
3205 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3206 cb->cb_color_fmask = va >> 8;
3207 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3208 } else {
3209 cb->cb_color_fmask = cb->cb_color_base;
3210 }
3211
3212 ntype = radv_translate_color_numformat(iview->vk_format,
3213 desc,
3214 vk_format_get_first_non_void_channel(iview->vk_format));
3215 format = radv_translate_colorformat(iview->vk_format);
3216 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3217 radv_finishme("Illegal color\n");
3218 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3219 endian = radv_colorformat_endian_swap(format);
3220
3221 /* blend clamp should be set for all NORM/SRGB types */
3222 if (ntype == V_028C70_NUMBER_UNORM ||
3223 ntype == V_028C70_NUMBER_SNORM ||
3224 ntype == V_028C70_NUMBER_SRGB)
3225 blend_clamp = 1;
3226
3227 /* set blend bypass according to docs if SINT/UINT or
3228 8/24 COLOR variants */
3229 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3230 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3231 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3232 blend_clamp = 0;
3233 blend_bypass = 1;
3234 }
3235 #if 0
3236 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3237 (format == V_028C70_COLOR_8 ||
3238 format == V_028C70_COLOR_8_8 ||
3239 format == V_028C70_COLOR_8_8_8_8))
3240 ->color_is_int8 = true;
3241 #endif
3242 cb->cb_color_info = S_028C70_FORMAT(format) |
3243 S_028C70_COMP_SWAP(swap) |
3244 S_028C70_BLEND_CLAMP(blend_clamp) |
3245 S_028C70_BLEND_BYPASS(blend_bypass) |
3246 S_028C70_SIMPLE_FLOAT(1) |
3247 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3248 ntype != V_028C70_NUMBER_SNORM &&
3249 ntype != V_028C70_NUMBER_SRGB &&
3250 format != V_028C70_COLOR_8_24 &&
3251 format != V_028C70_COLOR_24_8) |
3252 S_028C70_NUMBER_TYPE(ntype) |
3253 S_028C70_ENDIAN(endian);
3254 if ((iview->image->info.samples > 1) && iview->image->fmask.size) {
3255 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3256 if (device->physical_device->rad_info.chip_class == SI) {
3257 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3258 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3259 }
3260 }
3261
3262 if (iview->image->cmask.size &&
3263 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3264 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3265
3266 if (radv_vi_dcc_enabled(iview->image, iview->base_mip))
3267 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3268
3269 if (device->physical_device->rad_info.chip_class >= VI) {
3270 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
3271 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
3272 unsigned independent_64b_blocks = 0;
3273 unsigned max_compressed_block_size;
3274
3275 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
3276 64 for APU because all of our APUs to date use DIMMs which have
3277 a request granularity size of 64B while all other chips have a
3278 32B request size */
3279 if (!device->physical_device->rad_info.has_dedicated_vram)
3280 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
3281
3282 if (iview->image->info.samples > 1) {
3283 if (iview->image->surface.bpe == 1)
3284 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3285 else if (iview->image->surface.bpe == 2)
3286 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
3287 }
3288
3289 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT | VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
3290 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
3291 independent_64b_blocks = 1;
3292 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3293 } else
3294 max_compressed_block_size = max_uncompressed_block_size;
3295
3296 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3297 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
3298 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
3299 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
3300 }
3301
3302 /* This must be set for fast clear to work without FMASK. */
3303 if (!iview->image->fmask.size &&
3304 device->physical_device->rad_info.chip_class == SI) {
3305 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3306 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3307 }
3308
3309 if (device->physical_device->rad_info.chip_class >= GFX9) {
3310 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
3311 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
3312
3313 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3314 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3315 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3316 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
3317 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
3318 S_028C68_MAX_MIP(iview->image->info.levels - 1);
3319 }
3320 }
3321
3322 static void
3323 radv_initialise_ds_surface(struct radv_device *device,
3324 struct radv_ds_buffer_info *ds,
3325 struct radv_image_view *iview)
3326 {
3327 unsigned level = iview->base_mip;
3328 unsigned format, stencil_format;
3329 uint64_t va, s_offs, z_offs;
3330 bool stencil_only = false;
3331 memset(ds, 0, sizeof(*ds));
3332 switch (iview->image->vk_format) {
3333 case VK_FORMAT_D24_UNORM_S8_UINT:
3334 case VK_FORMAT_X8_D24_UNORM_PACK32:
3335 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3336 ds->offset_scale = 2.0f;
3337 break;
3338 case VK_FORMAT_D16_UNORM:
3339 case VK_FORMAT_D16_UNORM_S8_UINT:
3340 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3341 ds->offset_scale = 4.0f;
3342 break;
3343 case VK_FORMAT_D32_SFLOAT:
3344 case VK_FORMAT_D32_SFLOAT_S8_UINT:
3345 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3346 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3347 ds->offset_scale = 1.0f;
3348 break;
3349 case VK_FORMAT_S8_UINT:
3350 stencil_only = true;
3351 break;
3352 default:
3353 break;
3354 }
3355
3356 format = radv_translate_dbformat(iview->image->vk_format);
3357 stencil_format = iview->image->surface.has_stencil ?
3358 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
3359
3360 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3361 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
3362 S_028008_SLICE_MAX(max_slice);
3363
3364 ds->db_htile_data_base = 0;
3365 ds->db_htile_surface = 0;
3366
3367 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3368 s_offs = z_offs = va;
3369
3370 if (device->physical_device->rad_info.chip_class >= GFX9) {
3371 assert(iview->image->surface.u.gfx9.surf_offset == 0);
3372 s_offs += iview->image->surface.u.gfx9.stencil_offset;
3373
3374 ds->db_z_info = S_028038_FORMAT(format) |
3375 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
3376 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3377 S_028038_MAXMIP(iview->image->info.levels - 1);
3378 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
3379 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
3380
3381 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3382 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
3383 ds->db_depth_view |= S_028008_MIPID(level);
3384
3385 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
3386 S_02801C_Y_MAX(iview->image->info.height - 1);
3387
3388 if (radv_htile_enabled(iview->image, level)) {
3389 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
3390
3391 if (iview->image->tc_compatible_htile) {
3392 unsigned max_zplanes = 4;
3393
3394 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
3395 iview->image->info.samples > 1)
3396 max_zplanes = 2;
3397
3398 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
3399 S_028038_ITERATE_FLUSH(1);
3400 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
3401 }
3402
3403 if (!iview->image->surface.has_stencil)
3404 /* Use all of the htile_buffer for depth if there's no stencil. */
3405 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
3406 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3407 iview->image->htile_offset;
3408 ds->db_htile_data_base = va >> 8;
3409 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
3410 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
3411 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
3412 }
3413 } else {
3414 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
3415
3416 if (stencil_only)
3417 level_info = &iview->image->surface.u.legacy.stencil_level[level];
3418
3419 z_offs += iview->image->surface.u.legacy.level[level].offset;
3420 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
3421
3422 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!iview->image->tc_compatible_htile);
3423 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
3424 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
3425
3426 if (iview->image->info.samples > 1)
3427 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
3428
3429 if (device->physical_device->rad_info.chip_class >= CIK) {
3430 struct radeon_info *info = &device->physical_device->rad_info;
3431 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
3432 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
3433 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
3434 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
3435 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
3436 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
3437
3438 if (stencil_only)
3439 tile_mode = stencil_tile_mode;
3440
3441 ds->db_depth_info |=
3442 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
3443 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
3444 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
3445 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
3446 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
3447 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
3448 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
3449 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
3450 } else {
3451 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
3452 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3453 tile_mode_index = si_tile_mode_index(iview->image, level, true);
3454 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
3455 if (stencil_only)
3456 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3457 }
3458
3459 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
3460 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
3461 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
3462
3463 if (radv_htile_enabled(iview->image, level)) {
3464 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
3465
3466 if (!iview->image->surface.has_stencil &&
3467 !iview->image->tc_compatible_htile)
3468 /* Use all of the htile_buffer for depth if there's no stencil. */
3469 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
3470
3471 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3472 iview->image->htile_offset;
3473 ds->db_htile_data_base = va >> 8;
3474 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
3475
3476 if (iview->image->tc_compatible_htile) {
3477 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
3478
3479 if (iview->image->info.samples <= 1)
3480 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
3481 else if (iview->image->info.samples <= 4)
3482 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
3483 else
3484 ds->db_z_info|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
3485 }
3486 }
3487 }
3488
3489 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
3490 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
3491 }
3492
3493 VkResult radv_CreateFramebuffer(
3494 VkDevice _device,
3495 const VkFramebufferCreateInfo* pCreateInfo,
3496 const VkAllocationCallbacks* pAllocator,
3497 VkFramebuffer* pFramebuffer)
3498 {
3499 RADV_FROM_HANDLE(radv_device, device, _device);
3500 struct radv_framebuffer *framebuffer;
3501
3502 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
3503
3504 size_t size = sizeof(*framebuffer) +
3505 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
3506 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
3507 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3508 if (framebuffer == NULL)
3509 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3510
3511 framebuffer->attachment_count = pCreateInfo->attachmentCount;
3512 framebuffer->width = pCreateInfo->width;
3513 framebuffer->height = pCreateInfo->height;
3514 framebuffer->layers = pCreateInfo->layers;
3515 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
3516 VkImageView _iview = pCreateInfo->pAttachments[i];
3517 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
3518 framebuffer->attachments[i].attachment = iview;
3519 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
3520 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
3521 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3522 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
3523 }
3524 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
3525 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
3526 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
3527 }
3528
3529 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
3530 return VK_SUCCESS;
3531 }
3532
3533 void radv_DestroyFramebuffer(
3534 VkDevice _device,
3535 VkFramebuffer _fb,
3536 const VkAllocationCallbacks* pAllocator)
3537 {
3538 RADV_FROM_HANDLE(radv_device, device, _device);
3539 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
3540
3541 if (!fb)
3542 return;
3543 vk_free2(&device->alloc, pAllocator, fb);
3544 }
3545
3546 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
3547 {
3548 switch (address_mode) {
3549 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
3550 return V_008F30_SQ_TEX_WRAP;
3551 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
3552 return V_008F30_SQ_TEX_MIRROR;
3553 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
3554 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
3555 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
3556 return V_008F30_SQ_TEX_CLAMP_BORDER;
3557 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
3558 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
3559 default:
3560 unreachable("illegal tex wrap mode");
3561 break;
3562 }
3563 }
3564
3565 static unsigned
3566 radv_tex_compare(VkCompareOp op)
3567 {
3568 switch (op) {
3569 case VK_COMPARE_OP_NEVER:
3570 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
3571 case VK_COMPARE_OP_LESS:
3572 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
3573 case VK_COMPARE_OP_EQUAL:
3574 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
3575 case VK_COMPARE_OP_LESS_OR_EQUAL:
3576 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
3577 case VK_COMPARE_OP_GREATER:
3578 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
3579 case VK_COMPARE_OP_NOT_EQUAL:
3580 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
3581 case VK_COMPARE_OP_GREATER_OR_EQUAL:
3582 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
3583 case VK_COMPARE_OP_ALWAYS:
3584 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
3585 default:
3586 unreachable("illegal compare mode");
3587 break;
3588 }
3589 }
3590
3591 static unsigned
3592 radv_tex_filter(VkFilter filter, unsigned max_ansio)
3593 {
3594 switch (filter) {
3595 case VK_FILTER_NEAREST:
3596 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
3597 V_008F38_SQ_TEX_XY_FILTER_POINT);
3598 case VK_FILTER_LINEAR:
3599 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
3600 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
3601 case VK_FILTER_CUBIC_IMG:
3602 default:
3603 fprintf(stderr, "illegal texture filter");
3604 return 0;
3605 }
3606 }
3607
3608 static unsigned
3609 radv_tex_mipfilter(VkSamplerMipmapMode mode)
3610 {
3611 switch (mode) {
3612 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
3613 return V_008F38_SQ_TEX_Z_FILTER_POINT;
3614 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
3615 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
3616 default:
3617 return V_008F38_SQ_TEX_Z_FILTER_NONE;
3618 }
3619 }
3620
3621 static unsigned
3622 radv_tex_bordercolor(VkBorderColor bcolor)
3623 {
3624 switch (bcolor) {
3625 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
3626 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
3627 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3628 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
3629 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
3630 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3631 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
3632 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
3633 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3634 default:
3635 break;
3636 }
3637 return 0;
3638 }
3639
3640 static unsigned
3641 radv_tex_aniso_filter(unsigned filter)
3642 {
3643 if (filter < 2)
3644 return 0;
3645 if (filter < 4)
3646 return 1;
3647 if (filter < 8)
3648 return 2;
3649 if (filter < 16)
3650 return 3;
3651 return 4;
3652 }
3653
3654 static void
3655 radv_init_sampler(struct radv_device *device,
3656 struct radv_sampler *sampler,
3657 const VkSamplerCreateInfo *pCreateInfo)
3658 {
3659 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
3660 (uint32_t) pCreateInfo->maxAnisotropy : 0;
3661 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
3662 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
3663
3664 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
3665 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
3666 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
3667 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3668 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
3669 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
3670 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3671 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3672 S_008F30_DISABLE_CUBE_WRAP(0) |
3673 S_008F30_COMPAT_MODE(is_vi));
3674 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
3675 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
3676 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3677 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
3678 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
3679 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
3680 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
3681 S_008F38_MIP_POINT_PRECLAMP(0) |
3682 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
3683 S_008F38_FILTER_PREC_FIX(1) |
3684 S_008F38_ANISO_OVERRIDE(is_vi));
3685 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3686 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
3687 }
3688
3689 VkResult radv_CreateSampler(
3690 VkDevice _device,
3691 const VkSamplerCreateInfo* pCreateInfo,
3692 const VkAllocationCallbacks* pAllocator,
3693 VkSampler* pSampler)
3694 {
3695 RADV_FROM_HANDLE(radv_device, device, _device);
3696 struct radv_sampler *sampler;
3697
3698 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
3699
3700 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
3701 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3702 if (!sampler)
3703 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3704
3705 radv_init_sampler(device, sampler, pCreateInfo);
3706 *pSampler = radv_sampler_to_handle(sampler);
3707
3708 return VK_SUCCESS;
3709 }
3710
3711 void radv_DestroySampler(
3712 VkDevice _device,
3713 VkSampler _sampler,
3714 const VkAllocationCallbacks* pAllocator)
3715 {
3716 RADV_FROM_HANDLE(radv_device, device, _device);
3717 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
3718
3719 if (!sampler)
3720 return;
3721 vk_free2(&device->alloc, pAllocator, sampler);
3722 }
3723
3724 /* vk_icd.h does not declare this function, so we declare it here to
3725 * suppress Wmissing-prototypes.
3726 */
3727 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3728 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
3729
3730 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3731 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
3732 {
3733 /* For the full details on loader interface versioning, see
3734 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3735 * What follows is a condensed summary, to help you navigate the large and
3736 * confusing official doc.
3737 *
3738 * - Loader interface v0 is incompatible with later versions. We don't
3739 * support it.
3740 *
3741 * - In loader interface v1:
3742 * - The first ICD entrypoint called by the loader is
3743 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3744 * entrypoint.
3745 * - The ICD must statically expose no other Vulkan symbol unless it is
3746 * linked with -Bsymbolic.
3747 * - Each dispatchable Vulkan handle created by the ICD must be
3748 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3749 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3750 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3751 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3752 * such loader-managed surfaces.
3753 *
3754 * - Loader interface v2 differs from v1 in:
3755 * - The first ICD entrypoint called by the loader is
3756 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3757 * statically expose this entrypoint.
3758 *
3759 * - Loader interface v3 differs from v2 in:
3760 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3761 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3762 * because the loader no longer does so.
3763 */
3764 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
3765 return VK_SUCCESS;
3766 }
3767
3768 VkResult radv_GetMemoryFdKHR(VkDevice _device,
3769 const VkMemoryGetFdInfoKHR *pGetFdInfo,
3770 int *pFD)
3771 {
3772 RADV_FROM_HANDLE(radv_device, device, _device);
3773 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
3774
3775 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
3776
3777 /* At the moment, we support only the below handle types. */
3778 assert(pGetFdInfo->handleType ==
3779 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
3780 pGetFdInfo->handleType ==
3781 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3782
3783 bool ret = radv_get_memory_fd(device, memory, pFD);
3784 if (ret == false)
3785 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
3786 return VK_SUCCESS;
3787 }
3788
3789 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
3790 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
3791 int fd,
3792 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
3793 {
3794 switch (handleType) {
3795 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
3796 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
3797 return VK_SUCCESS;
3798
3799 default:
3800 /* The valid usage section for this function says:
3801 *
3802 * "handleType must not be one of the handle types defined as
3803 * opaque."
3804 *
3805 * So opaque handle types fall into the default "unsupported" case.
3806 */
3807 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3808 }
3809 }
3810
3811 static VkResult radv_import_opaque_fd(struct radv_device *device,
3812 int fd,
3813 uint32_t *syncobj)
3814 {
3815 uint32_t syncobj_handle = 0;
3816 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
3817 if (ret != 0)
3818 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3819
3820 if (*syncobj)
3821 device->ws->destroy_syncobj(device->ws, *syncobj);
3822
3823 *syncobj = syncobj_handle;
3824 close(fd);
3825
3826 return VK_SUCCESS;
3827 }
3828
3829 static VkResult radv_import_sync_fd(struct radv_device *device,
3830 int fd,
3831 uint32_t *syncobj)
3832 {
3833 /* If we create a syncobj we do it locally so that if we have an error, we don't
3834 * leave a syncobj in an undetermined state in the fence. */
3835 uint32_t syncobj_handle = *syncobj;
3836 if (!syncobj_handle) {
3837 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
3838 if (ret) {
3839 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3840 }
3841 }
3842
3843 if (fd == -1) {
3844 device->ws->signal_syncobj(device->ws, syncobj_handle);
3845 } else {
3846 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
3847 if (ret != 0)
3848 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3849 }
3850
3851 *syncobj = syncobj_handle;
3852 if (fd != -1)
3853 close(fd);
3854
3855 return VK_SUCCESS;
3856 }
3857
3858 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
3859 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
3860 {
3861 RADV_FROM_HANDLE(radv_device, device, _device);
3862 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
3863 uint32_t *syncobj_dst = NULL;
3864
3865 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
3866 syncobj_dst = &sem->temp_syncobj;
3867 } else {
3868 syncobj_dst = &sem->syncobj;
3869 }
3870
3871 switch(pImportSemaphoreFdInfo->handleType) {
3872 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
3873 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
3874 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
3875 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
3876 default:
3877 unreachable("Unhandled semaphore handle type");
3878 }
3879 }
3880
3881 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
3882 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
3883 int *pFd)
3884 {
3885 RADV_FROM_HANDLE(radv_device, device, _device);
3886 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
3887 int ret;
3888 uint32_t syncobj_handle;
3889
3890 if (sem->temp_syncobj)
3891 syncobj_handle = sem->temp_syncobj;
3892 else
3893 syncobj_handle = sem->syncobj;
3894
3895 switch(pGetFdInfo->handleType) {
3896 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
3897 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
3898 break;
3899 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
3900 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
3901 if (!ret) {
3902 if (sem->temp_syncobj) {
3903 close (sem->temp_syncobj);
3904 sem->temp_syncobj = 0;
3905 } else {
3906 device->ws->reset_syncobj(device->ws, syncobj_handle);
3907 }
3908 }
3909 break;
3910 default:
3911 unreachable("Unhandled semaphore handle type");
3912 }
3913
3914 if (ret)
3915 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3916 return VK_SUCCESS;
3917 }
3918
3919 void radv_GetPhysicalDeviceExternalSemaphorePropertiesKHR(
3920 VkPhysicalDevice physicalDevice,
3921 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
3922 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
3923 {
3924 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
3925
3926 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
3927 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
3928 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
3929 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
3930 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
3931 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
3932 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
3933 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
3934 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
3935 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3936 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3937 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
3938 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
3939 } else {
3940 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
3941 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
3942 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
3943 }
3944 }
3945
3946 VkResult radv_ImportFenceFdKHR(VkDevice _device,
3947 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
3948 {
3949 RADV_FROM_HANDLE(radv_device, device, _device);
3950 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
3951 uint32_t *syncobj_dst = NULL;
3952
3953
3954 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT_KHR) {
3955 syncobj_dst = &fence->temp_syncobj;
3956 } else {
3957 syncobj_dst = &fence->syncobj;
3958 }
3959
3960 switch(pImportFenceFdInfo->handleType) {
3961 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
3962 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
3963 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
3964 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
3965 default:
3966 unreachable("Unhandled fence handle type");
3967 }
3968 }
3969
3970 VkResult radv_GetFenceFdKHR(VkDevice _device,
3971 const VkFenceGetFdInfoKHR *pGetFdInfo,
3972 int *pFd)
3973 {
3974 RADV_FROM_HANDLE(radv_device, device, _device);
3975 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
3976 int ret;
3977 uint32_t syncobj_handle;
3978
3979 if (fence->temp_syncobj)
3980 syncobj_handle = fence->temp_syncobj;
3981 else
3982 syncobj_handle = fence->syncobj;
3983
3984 switch(pGetFdInfo->handleType) {
3985 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
3986 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
3987 break;
3988 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
3989 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
3990 if (!ret) {
3991 if (fence->temp_syncobj) {
3992 close (fence->temp_syncobj);
3993 fence->temp_syncobj = 0;
3994 } else {
3995 device->ws->reset_syncobj(device->ws, syncobj_handle);
3996 }
3997 }
3998 break;
3999 default:
4000 unreachable("Unhandled fence handle type");
4001 }
4002
4003 if (ret)
4004 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4005 return VK_SUCCESS;
4006 }
4007
4008 void radv_GetPhysicalDeviceExternalFencePropertiesKHR(
4009 VkPhysicalDevice physicalDevice,
4010 const VkPhysicalDeviceExternalFenceInfoKHR* pExternalFenceInfo,
4011 VkExternalFencePropertiesKHR* pExternalFenceProperties)
4012 {
4013 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4014
4015 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4016 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4017 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4018 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4019 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4020 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT_KHR |
4021 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4022 } else {
4023 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
4024 pExternalFenceProperties->compatibleHandleTypes = 0;
4025 pExternalFenceProperties->externalFenceFeatures = 0;
4026 }
4027 }
4028
4029 VkResult
4030 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
4031 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
4032 const VkAllocationCallbacks* pAllocator,
4033 VkDebugReportCallbackEXT* pCallback)
4034 {
4035 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4036 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
4037 pCreateInfo, pAllocator, &instance->alloc,
4038 pCallback);
4039 }
4040
4041 void
4042 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
4043 VkDebugReportCallbackEXT _callback,
4044 const VkAllocationCallbacks* pAllocator)
4045 {
4046 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4047 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
4048 _callback, pAllocator, &instance->alloc);
4049 }
4050
4051 void
4052 radv_DebugReportMessageEXT(VkInstance _instance,
4053 VkDebugReportFlagsEXT flags,
4054 VkDebugReportObjectTypeEXT objectType,
4055 uint64_t object,
4056 size_t location,
4057 int32_t messageCode,
4058 const char* pLayerPrefix,
4059 const char* pMessage)
4060 {
4061 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4062 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
4063 object, location, messageCode, pLayerPrefix, pMessage);
4064 }