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0ed3e27c7bcbf5c35bd2b33dd8e4a825b26234dd
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "gfx9d.h"
47 #include "util/debug.h"
48
49 static int
50 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
51 {
52 uint32_t mesa_timestamp, llvm_timestamp;
53 uint16_t f = family;
54 memset(uuid, 0, VK_UUID_SIZE);
55 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
56 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
57 return -1;
58
59 memcpy(uuid, &mesa_timestamp, 4);
60 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
61 memcpy((char*)uuid + 8, &f, 2);
62 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
63 return 0;
64 }
65
66 static void
67 radv_get_driver_uuid(void *uuid)
68 {
69 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
70 }
71
72 static void
73 radv_get_device_uuid(struct radeon_info *info, void *uuid)
74 {
75 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
76 }
77
78 static void
79 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
80 {
81 const char *chip_string;
82 char llvm_string[32] = {};
83
84 switch (family) {
85 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
86 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
87 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
88 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
89 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
90 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
91 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
92 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
93 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
94 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
95 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
96 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
97 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
98 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
99 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
100 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
101 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
102 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
103 case CHIP_VEGA10: chip_string = "AMD RADV VEGA"; break;
104 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
105 default: chip_string = "AMD RADV unknown"; break;
106 }
107
108 if (HAVE_LLVM > 0) {
109 snprintf(llvm_string, sizeof(llvm_string),
110 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
111 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
112 }
113
114 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
115 }
116
117 static void
118 radv_physical_device_init_mem_types(struct radv_physical_device *device)
119 {
120 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
121 uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
122 device->rad_info.vram_vis_size);
123
124 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
125 device->memory_properties.memoryHeapCount = 0;
126 if (device->rad_info.vram_size - visible_vram_size > 0) {
127 vram_index = device->memory_properties.memoryHeapCount++;
128 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
129 .size = device->rad_info.vram_size - visible_vram_size,
130 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
131 };
132 }
133 if (visible_vram_size) {
134 visible_vram_index = device->memory_properties.memoryHeapCount++;
135 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
136 .size = visible_vram_size,
137 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
138 };
139 }
140 if (device->rad_info.gart_size > 0) {
141 gart_index = device->memory_properties.memoryHeapCount++;
142 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
143 .size = device->rad_info.gart_size,
144 .flags = 0,
145 };
146 }
147
148 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
149 unsigned type_count = 0;
150 if (vram_index >= 0) {
151 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
152 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
153 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
154 .heapIndex = vram_index,
155 };
156 }
157 if (gart_index >= 0) {
158 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
159 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
160 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
161 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
162 .heapIndex = gart_index,
163 };
164 }
165 if (visible_vram_index >= 0) {
166 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
167 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
168 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
169 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
170 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
171 .heapIndex = visible_vram_index,
172 };
173 }
174 if (gart_index >= 0) {
175 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
176 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
177 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
178 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
179 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
180 .heapIndex = gart_index,
181 };
182 }
183 device->memory_properties.memoryTypeCount = type_count;
184 }
185
186 static void
187 radv_handle_env_var_force_family(struct radv_physical_device *device)
188 {
189 const char *family = getenv("RADV_FORCE_FAMILY");
190 unsigned i;
191
192 if (!family)
193 return;
194
195 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
196 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
197 /* Override family and chip_class. */
198 device->rad_info.family = i;
199
200 if (i >= CHIP_VEGA10)
201 device->rad_info.chip_class = GFX9;
202 else if (i >= CHIP_TONGA)
203 device->rad_info.chip_class = VI;
204 else if (i >= CHIP_BONAIRE)
205 device->rad_info.chip_class = CIK;
206 else
207 device->rad_info.chip_class = SI;
208
209 return;
210 }
211 }
212
213 fprintf(stderr, "radv: Unknown family: %s\n", family);
214 exit(1);
215 }
216
217 static VkResult
218 radv_physical_device_init(struct radv_physical_device *device,
219 struct radv_instance *instance,
220 drmDevicePtr drm_device)
221 {
222 const char *path = drm_device->nodes[DRM_NODE_RENDER];
223 VkResult result;
224 drmVersionPtr version;
225 int fd;
226
227 fd = open(path, O_RDWR | O_CLOEXEC);
228 if (fd < 0)
229 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
230
231 version = drmGetVersion(fd);
232 if (!version) {
233 close(fd);
234 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
235 "failed to get version %s: %m", path);
236 }
237
238 if (strcmp(version->name, "amdgpu")) {
239 drmFreeVersion(version);
240 close(fd);
241 return VK_ERROR_INCOMPATIBLE_DRIVER;
242 }
243 drmFreeVersion(version);
244
245 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
246 device->instance = instance;
247 assert(strlen(path) < ARRAY_SIZE(device->path));
248 strncpy(device->path, path, ARRAY_SIZE(device->path));
249
250 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
251 instance->perftest_flags);
252 if (!device->ws) {
253 result = VK_ERROR_INCOMPATIBLE_DRIVER;
254 goto fail;
255 }
256
257 device->local_fd = fd;
258 device->ws->query_info(device->ws, &device->rad_info);
259
260 radv_handle_env_var_force_family(device);
261
262 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
263
264 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
265 device->ws->destroy(device->ws);
266 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
267 "cannot generate UUID");
268 goto fail;
269 }
270
271 /* These flags affect shader compilation. */
272 uint64_t shader_env_flags =
273 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
274 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
275
276 /* The gpu id is already embeded in the uuid so we just pass "radv"
277 * when creating the cache.
278 */
279 char buf[VK_UUID_SIZE * 2 + 1];
280 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
281 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
282
283 if (device->rad_info.chip_class < VI ||
284 device->rad_info.chip_class > GFX9)
285 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
286
287 radv_get_driver_uuid(&device->device_uuid);
288 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
289
290 if (device->rad_info.family == CHIP_STONEY ||
291 device->rad_info.chip_class >= GFX9) {
292 device->has_rbplus = true;
293 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY;
294 }
295
296 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
297 * on SI.
298 */
299 device->has_clear_state = device->rad_info.chip_class >= CIK;
300
301 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
302
303 /* Vega10/Raven need a special workaround for a hardware bug. */
304 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
305 device->rad_info.family == CHIP_RAVEN;
306
307 radv_physical_device_init_mem_types(device);
308 radv_fill_device_extension_table(device, &device->supported_extensions);
309
310 result = radv_init_wsi(device);
311 if (result != VK_SUCCESS) {
312 device->ws->destroy(device->ws);
313 goto fail;
314 }
315
316 return VK_SUCCESS;
317
318 fail:
319 close(fd);
320 return result;
321 }
322
323 static void
324 radv_physical_device_finish(struct radv_physical_device *device)
325 {
326 radv_finish_wsi(device);
327 device->ws->destroy(device->ws);
328 disk_cache_destroy(device->disk_cache);
329 close(device->local_fd);
330 }
331
332 static void *
333 default_alloc_func(void *pUserData, size_t size, size_t align,
334 VkSystemAllocationScope allocationScope)
335 {
336 return malloc(size);
337 }
338
339 static void *
340 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
341 size_t align, VkSystemAllocationScope allocationScope)
342 {
343 return realloc(pOriginal, size);
344 }
345
346 static void
347 default_free_func(void *pUserData, void *pMemory)
348 {
349 free(pMemory);
350 }
351
352 static const VkAllocationCallbacks default_alloc = {
353 .pUserData = NULL,
354 .pfnAllocation = default_alloc_func,
355 .pfnReallocation = default_realloc_func,
356 .pfnFree = default_free_func,
357 };
358
359 static const struct debug_control radv_debug_options[] = {
360 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
361 {"nodcc", RADV_DEBUG_NO_DCC},
362 {"shaders", RADV_DEBUG_DUMP_SHADERS},
363 {"nocache", RADV_DEBUG_NO_CACHE},
364 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
365 {"nohiz", RADV_DEBUG_NO_HIZ},
366 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
367 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
368 {"allbos", RADV_DEBUG_ALL_BOS},
369 {"noibs", RADV_DEBUG_NO_IBS},
370 {"spirv", RADV_DEBUG_DUMP_SPIRV},
371 {"vmfaults", RADV_DEBUG_VM_FAULTS},
372 {"zerovram", RADV_DEBUG_ZERO_VRAM},
373 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
374 {"nosisched", RADV_DEBUG_NO_SISCHED},
375 {"preoptir", RADV_DEBUG_PREOPTIR},
376 {NULL, 0}
377 };
378
379 const char *
380 radv_get_debug_option_name(int id)
381 {
382 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
383 return radv_debug_options[id].string;
384 }
385
386 static const struct debug_control radv_perftest_options[] = {
387 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
388 {"sisched", RADV_PERFTEST_SISCHED},
389 {"localbos", RADV_PERFTEST_LOCAL_BOS},
390 {"binning", RADV_PERFTEST_BINNING},
391 {NULL, 0}
392 };
393
394 const char *
395 radv_get_perftest_option_name(int id)
396 {
397 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
398 return radv_perftest_options[id].string;
399 }
400
401 static void
402 radv_handle_per_app_options(struct radv_instance *instance,
403 const VkApplicationInfo *info)
404 {
405 const char *name = info ? info->pApplicationName : NULL;
406
407 if (!name)
408 return;
409
410 if (!strcmp(name, "Talos - Linux - 32bit") ||
411 !strcmp(name, "Talos - Linux - 64bit")) {
412 /* Force enable LLVM sisched for Talos because it looks safe
413 * and it gives few more FPS.
414 */
415 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
416 }
417 }
418
419 static int radv_get_instance_extension_index(const char *name)
420 {
421 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
422 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
423 return i;
424 }
425 return -1;
426 }
427
428
429 VkResult radv_CreateInstance(
430 const VkInstanceCreateInfo* pCreateInfo,
431 const VkAllocationCallbacks* pAllocator,
432 VkInstance* pInstance)
433 {
434 struct radv_instance *instance;
435 VkResult result;
436
437 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
438
439 uint32_t client_version;
440 if (pCreateInfo->pApplicationInfo &&
441 pCreateInfo->pApplicationInfo->apiVersion != 0) {
442 client_version = pCreateInfo->pApplicationInfo->apiVersion;
443 } else {
444 client_version = VK_MAKE_VERSION(1, 0, 0);
445 }
446
447 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
448 client_version > VK_MAKE_VERSION(1, 1, 0xfff)) {
449 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
450 "Client requested version %d.%d.%d",
451 VK_VERSION_MAJOR(client_version),
452 VK_VERSION_MINOR(client_version),
453 VK_VERSION_PATCH(client_version));
454 }
455
456 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
457 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
458 if (!instance)
459 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
460
461 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
462
463 if (pAllocator)
464 instance->alloc = *pAllocator;
465 else
466 instance->alloc = default_alloc;
467
468 instance->apiVersion = client_version;
469 instance->physicalDeviceCount = -1;
470
471 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
472 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
473 int index = radv_get_instance_extension_index(ext_name);
474
475 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
476 vk_free2(&default_alloc, pAllocator, instance);
477 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
478 }
479
480 instance->enabled_extensions.extensions[index] = true;
481 }
482
483 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
484 if (result != VK_SUCCESS) {
485 vk_free2(&default_alloc, pAllocator, instance);
486 return vk_error(result);
487 }
488
489 _mesa_locale_init();
490
491 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
492
493 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
494 radv_debug_options);
495
496 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
497 radv_perftest_options);
498
499 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
500
501 if (instance->debug_flags & RADV_DEBUG_NO_SISCHED) {
502 /* Disable sisched when the user requests it, this is mostly
503 * useful when the driver force-enable sisched for the given
504 * application.
505 */
506 instance->perftest_flags &= ~RADV_PERFTEST_SISCHED;
507 }
508
509 *pInstance = radv_instance_to_handle(instance);
510
511 return VK_SUCCESS;
512 }
513
514 void radv_DestroyInstance(
515 VkInstance _instance,
516 const VkAllocationCallbacks* pAllocator)
517 {
518 RADV_FROM_HANDLE(radv_instance, instance, _instance);
519
520 if (!instance)
521 return;
522
523 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
524 radv_physical_device_finish(instance->physicalDevices + i);
525 }
526
527 VG(VALGRIND_DESTROY_MEMPOOL(instance));
528
529 _mesa_locale_fini();
530
531 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
532
533 vk_free(&instance->alloc, instance);
534 }
535
536 static VkResult
537 radv_enumerate_devices(struct radv_instance *instance)
538 {
539 /* TODO: Check for more devices ? */
540 drmDevicePtr devices[8];
541 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
542 int max_devices;
543
544 instance->physicalDeviceCount = 0;
545
546 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
547 if (max_devices < 1)
548 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
549
550 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
551 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
552 devices[i]->bustype == DRM_BUS_PCI &&
553 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
554
555 result = radv_physical_device_init(instance->physicalDevices +
556 instance->physicalDeviceCount,
557 instance,
558 devices[i]);
559 if (result == VK_SUCCESS)
560 ++instance->physicalDeviceCount;
561 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
562 break;
563 }
564 }
565 drmFreeDevices(devices, max_devices);
566
567 return result;
568 }
569
570 VkResult radv_EnumeratePhysicalDevices(
571 VkInstance _instance,
572 uint32_t* pPhysicalDeviceCount,
573 VkPhysicalDevice* pPhysicalDevices)
574 {
575 RADV_FROM_HANDLE(radv_instance, instance, _instance);
576 VkResult result;
577
578 if (instance->physicalDeviceCount < 0) {
579 result = radv_enumerate_devices(instance);
580 if (result != VK_SUCCESS &&
581 result != VK_ERROR_INCOMPATIBLE_DRIVER)
582 return result;
583 }
584
585 if (!pPhysicalDevices) {
586 *pPhysicalDeviceCount = instance->physicalDeviceCount;
587 } else {
588 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
589 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
590 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
591 }
592
593 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
594 : VK_SUCCESS;
595 }
596
597 VkResult radv_EnumeratePhysicalDeviceGroups(
598 VkInstance _instance,
599 uint32_t* pPhysicalDeviceGroupCount,
600 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
601 {
602 RADV_FROM_HANDLE(radv_instance, instance, _instance);
603 VkResult result;
604
605 if (instance->physicalDeviceCount < 0) {
606 result = radv_enumerate_devices(instance);
607 if (result != VK_SUCCESS &&
608 result != VK_ERROR_INCOMPATIBLE_DRIVER)
609 return result;
610 }
611
612 if (!pPhysicalDeviceGroupProperties) {
613 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
614 } else {
615 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
616 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
617 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
618 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
619 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
620 }
621 }
622 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
623 : VK_SUCCESS;
624 }
625
626 void radv_GetPhysicalDeviceFeatures(
627 VkPhysicalDevice physicalDevice,
628 VkPhysicalDeviceFeatures* pFeatures)
629 {
630 memset(pFeatures, 0, sizeof(*pFeatures));
631
632 *pFeatures = (VkPhysicalDeviceFeatures) {
633 .robustBufferAccess = true,
634 .fullDrawIndexUint32 = true,
635 .imageCubeArray = true,
636 .independentBlend = true,
637 .geometryShader = true,
638 .tessellationShader = true,
639 .sampleRateShading = true,
640 .dualSrcBlend = true,
641 .logicOp = true,
642 .multiDrawIndirect = true,
643 .drawIndirectFirstInstance = true,
644 .depthClamp = true,
645 .depthBiasClamp = true,
646 .fillModeNonSolid = true,
647 .depthBounds = true,
648 .wideLines = true,
649 .largePoints = true,
650 .alphaToOne = true,
651 .multiViewport = true,
652 .samplerAnisotropy = true,
653 .textureCompressionETC2 = false,
654 .textureCompressionASTC_LDR = false,
655 .textureCompressionBC = true,
656 .occlusionQueryPrecise = true,
657 .pipelineStatisticsQuery = true,
658 .vertexPipelineStoresAndAtomics = true,
659 .fragmentStoresAndAtomics = true,
660 .shaderTessellationAndGeometryPointSize = true,
661 .shaderImageGatherExtended = true,
662 .shaderStorageImageExtendedFormats = true,
663 .shaderStorageImageMultisample = false,
664 .shaderUniformBufferArrayDynamicIndexing = true,
665 .shaderSampledImageArrayDynamicIndexing = true,
666 .shaderStorageBufferArrayDynamicIndexing = true,
667 .shaderStorageImageArrayDynamicIndexing = true,
668 .shaderStorageImageReadWithoutFormat = true,
669 .shaderStorageImageWriteWithoutFormat = true,
670 .shaderClipDistance = true,
671 .shaderCullDistance = true,
672 .shaderFloat64 = true,
673 .shaderInt64 = true,
674 .shaderInt16 = false,
675 .sparseBinding = true,
676 .variableMultisampleRate = true,
677 .inheritedQueries = true,
678 };
679 }
680
681 void radv_GetPhysicalDeviceFeatures2(
682 VkPhysicalDevice physicalDevice,
683 VkPhysicalDeviceFeatures2KHR *pFeatures)
684 {
685 vk_foreach_struct(ext, pFeatures->pNext) {
686 switch (ext->sType) {
687 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
688 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
689 features->variablePointersStorageBuffer = true;
690 features->variablePointers = false;
691 break;
692 }
693 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHR: {
694 VkPhysicalDeviceMultiviewFeaturesKHR *features = (VkPhysicalDeviceMultiviewFeaturesKHR*)ext;
695 features->multiview = true;
696 features->multiviewGeometryShader = true;
697 features->multiviewTessellationShader = true;
698 break;
699 }
700 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
701 VkPhysicalDeviceShaderDrawParameterFeatures *features =
702 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
703 features->shaderDrawParameters = true;
704 break;
705 }
706 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
707 VkPhysicalDeviceProtectedMemoryFeatures *features =
708 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
709 features->protectedMemory = false;
710 break;
711 }
712 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
713 VkPhysicalDevice16BitStorageFeatures *features =
714 (VkPhysicalDevice16BitStorageFeatures*)ext;
715 features->storageBuffer16BitAccess = false;
716 features->uniformAndStorageBuffer16BitAccess = false;
717 features->storagePushConstant16 = false;
718 features->storageInputOutput16 = false;
719 break;
720 }
721 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
722 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
723 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
724 features->samplerYcbcrConversion = false;
725 break;
726 }
727 default:
728 break;
729 }
730 }
731 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
732 }
733
734 void radv_GetPhysicalDeviceProperties(
735 VkPhysicalDevice physicalDevice,
736 VkPhysicalDeviceProperties* pProperties)
737 {
738 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
739 VkSampleCountFlags sample_counts = 0xf;
740
741 /* make sure that the entire descriptor set is addressable with a signed
742 * 32-bit int. So the sum of all limits scaled by descriptor size has to
743 * be at most 2 GiB. the combined image & samples object count as one of
744 * both. This limit is for the pipeline layout, not for the set layout, but
745 * there is no set limit, so we just set a pipeline limit. I don't think
746 * any app is going to hit this soon. */
747 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
748 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
749 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
750 32 /* sampler, largest when combined with image */ +
751 64 /* sampled image */ +
752 64 /* storage image */);
753
754 VkPhysicalDeviceLimits limits = {
755 .maxImageDimension1D = (1 << 14),
756 .maxImageDimension2D = (1 << 14),
757 .maxImageDimension3D = (1 << 11),
758 .maxImageDimensionCube = (1 << 14),
759 .maxImageArrayLayers = (1 << 11),
760 .maxTexelBufferElements = 128 * 1024 * 1024,
761 .maxUniformBufferRange = UINT32_MAX,
762 .maxStorageBufferRange = UINT32_MAX,
763 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
764 .maxMemoryAllocationCount = UINT32_MAX,
765 .maxSamplerAllocationCount = 64 * 1024,
766 .bufferImageGranularity = 64, /* A cache line */
767 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
768 .maxBoundDescriptorSets = MAX_SETS,
769 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
770 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
771 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
772 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
773 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
774 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
775 .maxPerStageResources = max_descriptor_set_size,
776 .maxDescriptorSetSamplers = max_descriptor_set_size,
777 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
778 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
779 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
780 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
781 .maxDescriptorSetSampledImages = max_descriptor_set_size,
782 .maxDescriptorSetStorageImages = max_descriptor_set_size,
783 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
784 .maxVertexInputAttributes = 32,
785 .maxVertexInputBindings = 32,
786 .maxVertexInputAttributeOffset = 2047,
787 .maxVertexInputBindingStride = 2048,
788 .maxVertexOutputComponents = 128,
789 .maxTessellationGenerationLevel = 64,
790 .maxTessellationPatchSize = 32,
791 .maxTessellationControlPerVertexInputComponents = 128,
792 .maxTessellationControlPerVertexOutputComponents = 128,
793 .maxTessellationControlPerPatchOutputComponents = 120,
794 .maxTessellationControlTotalOutputComponents = 4096,
795 .maxTessellationEvaluationInputComponents = 128,
796 .maxTessellationEvaluationOutputComponents = 128,
797 .maxGeometryShaderInvocations = 127,
798 .maxGeometryInputComponents = 64,
799 .maxGeometryOutputComponents = 128,
800 .maxGeometryOutputVertices = 256,
801 .maxGeometryTotalOutputComponents = 1024,
802 .maxFragmentInputComponents = 128,
803 .maxFragmentOutputAttachments = 8,
804 .maxFragmentDualSrcAttachments = 1,
805 .maxFragmentCombinedOutputResources = 8,
806 .maxComputeSharedMemorySize = 32768,
807 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
808 .maxComputeWorkGroupInvocations = 2048,
809 .maxComputeWorkGroupSize = {
810 2048,
811 2048,
812 2048
813 },
814 .subPixelPrecisionBits = 4 /* FIXME */,
815 .subTexelPrecisionBits = 4 /* FIXME */,
816 .mipmapPrecisionBits = 4 /* FIXME */,
817 .maxDrawIndexedIndexValue = UINT32_MAX,
818 .maxDrawIndirectCount = UINT32_MAX,
819 .maxSamplerLodBias = 16,
820 .maxSamplerAnisotropy = 16,
821 .maxViewports = MAX_VIEWPORTS,
822 .maxViewportDimensions = { (1 << 14), (1 << 14) },
823 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
824 .viewportSubPixelBits = 13, /* We take a float? */
825 .minMemoryMapAlignment = 4096, /* A page */
826 .minTexelBufferOffsetAlignment = 1,
827 .minUniformBufferOffsetAlignment = 4,
828 .minStorageBufferOffsetAlignment = 4,
829 .minTexelOffset = -32,
830 .maxTexelOffset = 31,
831 .minTexelGatherOffset = -32,
832 .maxTexelGatherOffset = 31,
833 .minInterpolationOffset = -2,
834 .maxInterpolationOffset = 2,
835 .subPixelInterpolationOffsetBits = 8,
836 .maxFramebufferWidth = (1 << 14),
837 .maxFramebufferHeight = (1 << 14),
838 .maxFramebufferLayers = (1 << 10),
839 .framebufferColorSampleCounts = sample_counts,
840 .framebufferDepthSampleCounts = sample_counts,
841 .framebufferStencilSampleCounts = sample_counts,
842 .framebufferNoAttachmentsSampleCounts = sample_counts,
843 .maxColorAttachments = MAX_RTS,
844 .sampledImageColorSampleCounts = sample_counts,
845 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
846 .sampledImageDepthSampleCounts = sample_counts,
847 .sampledImageStencilSampleCounts = sample_counts,
848 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
849 .maxSampleMaskWords = 1,
850 .timestampComputeAndGraphics = true,
851 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
852 .maxClipDistances = 8,
853 .maxCullDistances = 8,
854 .maxCombinedClipAndCullDistances = 8,
855 .discreteQueuePriorities = 1,
856 .pointSizeRange = { 0.125, 255.875 },
857 .lineWidthRange = { 0.0, 7.9921875 },
858 .pointSizeGranularity = (1.0 / 8.0),
859 .lineWidthGranularity = (1.0 / 128.0),
860 .strictLines = false, /* FINISHME */
861 .standardSampleLocations = true,
862 .optimalBufferCopyOffsetAlignment = 128,
863 .optimalBufferCopyRowPitchAlignment = 128,
864 .nonCoherentAtomSize = 64,
865 };
866
867 *pProperties = (VkPhysicalDeviceProperties) {
868 .apiVersion = radv_physical_device_api_version(pdevice),
869 .driverVersion = vk_get_driver_version(),
870 .vendorID = ATI_VENDOR_ID,
871 .deviceID = pdevice->rad_info.pci_id,
872 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
873 .limits = limits,
874 .sparseProperties = {0},
875 };
876
877 strcpy(pProperties->deviceName, pdevice->name);
878 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
879 }
880
881 void radv_GetPhysicalDeviceProperties2(
882 VkPhysicalDevice physicalDevice,
883 VkPhysicalDeviceProperties2KHR *pProperties)
884 {
885 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
886 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
887
888 vk_foreach_struct(ext, pProperties->pNext) {
889 switch (ext->sType) {
890 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
891 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
892 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
893 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
894 break;
895 }
896 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
897 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
898 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
899 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
900 properties->deviceLUIDValid = false;
901 break;
902 }
903 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHR: {
904 VkPhysicalDeviceMultiviewPropertiesKHR *properties = (VkPhysicalDeviceMultiviewPropertiesKHR*)ext;
905 properties->maxMultiviewViewCount = MAX_VIEWS;
906 properties->maxMultiviewInstanceIndex = INT_MAX;
907 break;
908 }
909 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
910 VkPhysicalDevicePointClippingPropertiesKHR *properties =
911 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
912 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
913 break;
914 }
915 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
916 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
917 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
918 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
919 break;
920 }
921 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
922 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
923 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
924 properties->minImportedHostPointerAlignment = 4096;
925 break;
926 }
927 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
928 VkPhysicalDeviceSubgroupProperties *properties =
929 (VkPhysicalDeviceSubgroupProperties*)ext;
930 properties->subgroupSize = 64;
931 properties->supportedStages = VK_SHADER_STAGE_ALL;
932 properties->supportedOperations = VK_SUBGROUP_FEATURE_BASIC_BIT;
933 properties->quadOperationsInAllStages = false;
934 break;
935 }
936 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
937 VkPhysicalDeviceMaintenance3Properties *properties =
938 (VkPhysicalDeviceMaintenance3Properties*)ext;
939 /* Make sure everything is addressable by a signed 32-bit int, and
940 * our largest descriptors are 96 bytes. */
941 properties->maxPerSetDescriptors = (1ull << 31) / 96;
942 /* Our buffer size fields allow only this much */
943 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
944 break;
945 }
946 default:
947 break;
948 }
949 }
950 }
951
952 static void radv_get_physical_device_queue_family_properties(
953 struct radv_physical_device* pdevice,
954 uint32_t* pCount,
955 VkQueueFamilyProperties** pQueueFamilyProperties)
956 {
957 int num_queue_families = 1;
958 int idx;
959 if (pdevice->rad_info.num_compute_rings > 0 &&
960 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
961 num_queue_families++;
962
963 if (pQueueFamilyProperties == NULL) {
964 *pCount = num_queue_families;
965 return;
966 }
967
968 if (!*pCount)
969 return;
970
971 idx = 0;
972 if (*pCount >= 1) {
973 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
974 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
975 VK_QUEUE_COMPUTE_BIT |
976 VK_QUEUE_TRANSFER_BIT |
977 VK_QUEUE_SPARSE_BINDING_BIT,
978 .queueCount = 1,
979 .timestampValidBits = 64,
980 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
981 };
982 idx++;
983 }
984
985 if (pdevice->rad_info.num_compute_rings > 0 &&
986 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
987 if (*pCount > idx) {
988 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
989 .queueFlags = VK_QUEUE_COMPUTE_BIT |
990 VK_QUEUE_TRANSFER_BIT |
991 VK_QUEUE_SPARSE_BINDING_BIT,
992 .queueCount = pdevice->rad_info.num_compute_rings,
993 .timestampValidBits = 64,
994 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
995 };
996 idx++;
997 }
998 }
999 *pCount = idx;
1000 }
1001
1002 void radv_GetPhysicalDeviceQueueFamilyProperties(
1003 VkPhysicalDevice physicalDevice,
1004 uint32_t* pCount,
1005 VkQueueFamilyProperties* pQueueFamilyProperties)
1006 {
1007 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1008 if (!pQueueFamilyProperties) {
1009 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1010 return;
1011 }
1012 VkQueueFamilyProperties *properties[] = {
1013 pQueueFamilyProperties + 0,
1014 pQueueFamilyProperties + 1,
1015 pQueueFamilyProperties + 2,
1016 };
1017 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1018 assert(*pCount <= 3);
1019 }
1020
1021 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1022 VkPhysicalDevice physicalDevice,
1023 uint32_t* pCount,
1024 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
1025 {
1026 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1027 if (!pQueueFamilyProperties) {
1028 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1029 return;
1030 }
1031 VkQueueFamilyProperties *properties[] = {
1032 &pQueueFamilyProperties[0].queueFamilyProperties,
1033 &pQueueFamilyProperties[1].queueFamilyProperties,
1034 &pQueueFamilyProperties[2].queueFamilyProperties,
1035 };
1036 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1037 assert(*pCount <= 3);
1038 }
1039
1040 void radv_GetPhysicalDeviceMemoryProperties(
1041 VkPhysicalDevice physicalDevice,
1042 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1043 {
1044 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1045
1046 *pMemoryProperties = physical_device->memory_properties;
1047 }
1048
1049 void radv_GetPhysicalDeviceMemoryProperties2(
1050 VkPhysicalDevice physicalDevice,
1051 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
1052 {
1053 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1054 &pMemoryProperties->memoryProperties);
1055 }
1056
1057 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1058 VkDevice _device,
1059 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
1060 const void *pHostPointer,
1061 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1062 {
1063 RADV_FROM_HANDLE(radv_device, device, _device);
1064
1065 switch (handleType)
1066 {
1067 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1068 const struct radv_physical_device *physical_device = device->physical_device;
1069 uint32_t memoryTypeBits = 0;
1070 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1071 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1072 memoryTypeBits = (1 << i);
1073 break;
1074 }
1075 }
1076 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1077 return VK_SUCCESS;
1078 }
1079 default:
1080 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
1081 }
1082 }
1083
1084 static enum radeon_ctx_priority
1085 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1086 {
1087 /* Default to MEDIUM when a specific global priority isn't requested */
1088 if (!pObj)
1089 return RADEON_CTX_PRIORITY_MEDIUM;
1090
1091 switch(pObj->globalPriority) {
1092 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1093 return RADEON_CTX_PRIORITY_REALTIME;
1094 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1095 return RADEON_CTX_PRIORITY_HIGH;
1096 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1097 return RADEON_CTX_PRIORITY_MEDIUM;
1098 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1099 return RADEON_CTX_PRIORITY_LOW;
1100 default:
1101 unreachable("Illegal global priority value");
1102 return RADEON_CTX_PRIORITY_INVALID;
1103 }
1104 }
1105
1106 static int
1107 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1108 uint32_t queue_family_index, int idx,
1109 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1110 {
1111 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1112 queue->device = device;
1113 queue->queue_family_index = queue_family_index;
1114 queue->queue_idx = idx;
1115 queue->priority = radv_get_queue_global_priority(global_priority);
1116
1117 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1118 if (!queue->hw_ctx)
1119 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1120
1121 return VK_SUCCESS;
1122 }
1123
1124 static void
1125 radv_queue_finish(struct radv_queue *queue)
1126 {
1127 if (queue->hw_ctx)
1128 queue->device->ws->ctx_destroy(queue->hw_ctx);
1129
1130 if (queue->initial_full_flush_preamble_cs)
1131 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1132 if (queue->initial_preamble_cs)
1133 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1134 if (queue->continue_preamble_cs)
1135 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1136 if (queue->descriptor_bo)
1137 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1138 if (queue->scratch_bo)
1139 queue->device->ws->buffer_destroy(queue->scratch_bo);
1140 if (queue->esgs_ring_bo)
1141 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1142 if (queue->gsvs_ring_bo)
1143 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1144 if (queue->tess_rings_bo)
1145 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1146 if (queue->compute_scratch_bo)
1147 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1148 }
1149
1150 static void
1151 radv_device_init_gs_info(struct radv_device *device)
1152 {
1153 switch (device->physical_device->rad_info.family) {
1154 case CHIP_OLAND:
1155 case CHIP_HAINAN:
1156 case CHIP_KAVERI:
1157 case CHIP_KABINI:
1158 case CHIP_MULLINS:
1159 case CHIP_ICELAND:
1160 case CHIP_CARRIZO:
1161 case CHIP_STONEY:
1162 device->gs_table_depth = 16;
1163 return;
1164 case CHIP_TAHITI:
1165 case CHIP_PITCAIRN:
1166 case CHIP_VERDE:
1167 case CHIP_BONAIRE:
1168 case CHIP_HAWAII:
1169 case CHIP_TONGA:
1170 case CHIP_FIJI:
1171 case CHIP_POLARIS10:
1172 case CHIP_POLARIS11:
1173 case CHIP_POLARIS12:
1174 case CHIP_VEGA10:
1175 case CHIP_RAVEN:
1176 device->gs_table_depth = 32;
1177 return;
1178 default:
1179 unreachable("unknown GPU");
1180 }
1181 }
1182
1183 static int radv_get_device_extension_index(const char *name)
1184 {
1185 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1186 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1187 return i;
1188 }
1189 return -1;
1190 }
1191
1192 VkResult radv_CreateDevice(
1193 VkPhysicalDevice physicalDevice,
1194 const VkDeviceCreateInfo* pCreateInfo,
1195 const VkAllocationCallbacks* pAllocator,
1196 VkDevice* pDevice)
1197 {
1198 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1199 VkResult result;
1200 struct radv_device *device;
1201
1202 bool keep_shader_info = false;
1203
1204 /* Check enabled features */
1205 if (pCreateInfo->pEnabledFeatures) {
1206 VkPhysicalDeviceFeatures supported_features;
1207 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1208 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1209 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1210 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1211 for (uint32_t i = 0; i < num_features; i++) {
1212 if (enabled_feature[i] && !supported_feature[i])
1213 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
1214 }
1215 }
1216
1217 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1218 sizeof(*device), 8,
1219 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1220 if (!device)
1221 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1222
1223 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1224 device->instance = physical_device->instance;
1225 device->physical_device = physical_device;
1226
1227 device->ws = physical_device->ws;
1228 if (pAllocator)
1229 device->alloc = *pAllocator;
1230 else
1231 device->alloc = physical_device->instance->alloc;
1232
1233 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1234 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1235 int index = radv_get_device_extension_index(ext_name);
1236 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1237 vk_free(&device->alloc, device);
1238 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
1239 }
1240
1241 device->enabled_extensions.extensions[index] = true;
1242 }
1243
1244 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1245
1246 mtx_init(&device->shader_slab_mutex, mtx_plain);
1247 list_inithead(&device->shader_slabs);
1248
1249 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1250 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1251 uint32_t qfi = queue_create->queueFamilyIndex;
1252 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1253 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1254
1255 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1256
1257 device->queues[qfi] = vk_alloc(&device->alloc,
1258 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1259 if (!device->queues[qfi]) {
1260 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1261 goto fail;
1262 }
1263
1264 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1265
1266 device->queue_count[qfi] = queue_create->queueCount;
1267
1268 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1269 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q, global_priority);
1270 if (result != VK_SUCCESS)
1271 goto fail;
1272 }
1273 }
1274
1275 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1276 (device->instance->perftest_flags & RADV_PERFTEST_BINNING);
1277
1278 /* Disabled and not implemented for now. */
1279 device->dfsm_allowed = device->pbb_allowed && false;
1280
1281 #ifdef ANDROID
1282 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1283 #endif
1284
1285 device->llvm_supports_spill = true;
1286
1287 /* The maximum number of scratch waves. Scratch space isn't divided
1288 * evenly between CUs. The number is only a function of the number of CUs.
1289 * We can decrease the constant to decrease the scratch buffer size.
1290 *
1291 * sctx->scratch_waves must be >= the maximum posible size of
1292 * 1 threadgroup, so that the hw doesn't hang from being unable
1293 * to start any.
1294 *
1295 * The recommended value is 4 per CU at most. Higher numbers don't
1296 * bring much benefit, but they still occupy chip resources (think
1297 * async compute). I've seen ~2% performance difference between 4 and 32.
1298 */
1299 uint32_t max_threads_per_block = 2048;
1300 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1301 max_threads_per_block / 64);
1302
1303 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1304
1305 if (device->physical_device->rad_info.chip_class >= CIK) {
1306 /* If the KMD allows it (there is a KMD hw register for it),
1307 * allow launching waves out-of-order.
1308 */
1309 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1310 }
1311
1312 radv_device_init_gs_info(device);
1313
1314 device->tess_offchip_block_dw_size =
1315 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1316 device->has_distributed_tess =
1317 device->physical_device->rad_info.chip_class >= VI &&
1318 device->physical_device->rad_info.max_se >= 2;
1319
1320 if (getenv("RADV_TRACE_FILE")) {
1321 keep_shader_info = true;
1322
1323 if (!radv_init_trace(device))
1324 goto fail;
1325 }
1326
1327 device->keep_shader_info = keep_shader_info;
1328
1329 result = radv_device_init_meta(device);
1330 if (result != VK_SUCCESS)
1331 goto fail;
1332
1333 radv_device_init_msaa(device);
1334
1335 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1336 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1337 switch (family) {
1338 case RADV_QUEUE_GENERAL:
1339 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1340 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1341 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1342 break;
1343 case RADV_QUEUE_COMPUTE:
1344 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1345 radeon_emit(device->empty_cs[family], 0);
1346 break;
1347 }
1348 device->ws->cs_finalize(device->empty_cs[family]);
1349 }
1350
1351 if (device->physical_device->rad_info.chip_class >= CIK)
1352 cik_create_gfx_config(device);
1353
1354 VkPipelineCacheCreateInfo ci;
1355 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1356 ci.pNext = NULL;
1357 ci.flags = 0;
1358 ci.pInitialData = NULL;
1359 ci.initialDataSize = 0;
1360 VkPipelineCache pc;
1361 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1362 &ci, NULL, &pc);
1363 if (result != VK_SUCCESS)
1364 goto fail_meta;
1365
1366 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1367
1368 *pDevice = radv_device_to_handle(device);
1369 return VK_SUCCESS;
1370
1371 fail_meta:
1372 radv_device_finish_meta(device);
1373 fail:
1374 if (device->trace_bo)
1375 device->ws->buffer_destroy(device->trace_bo);
1376
1377 if (device->gfx_init)
1378 device->ws->buffer_destroy(device->gfx_init);
1379
1380 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1381 for (unsigned q = 0; q < device->queue_count[i]; q++)
1382 radv_queue_finish(&device->queues[i][q]);
1383 if (device->queue_count[i])
1384 vk_free(&device->alloc, device->queues[i]);
1385 }
1386
1387 vk_free(&device->alloc, device);
1388 return result;
1389 }
1390
1391 void radv_DestroyDevice(
1392 VkDevice _device,
1393 const VkAllocationCallbacks* pAllocator)
1394 {
1395 RADV_FROM_HANDLE(radv_device, device, _device);
1396
1397 if (!device)
1398 return;
1399
1400 if (device->trace_bo)
1401 device->ws->buffer_destroy(device->trace_bo);
1402
1403 if (device->gfx_init)
1404 device->ws->buffer_destroy(device->gfx_init);
1405
1406 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1407 for (unsigned q = 0; q < device->queue_count[i]; q++)
1408 radv_queue_finish(&device->queues[i][q]);
1409 if (device->queue_count[i])
1410 vk_free(&device->alloc, device->queues[i]);
1411 if (device->empty_cs[i])
1412 device->ws->cs_destroy(device->empty_cs[i]);
1413 }
1414 radv_device_finish_meta(device);
1415
1416 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1417 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1418
1419 radv_destroy_shader_slabs(device);
1420
1421 vk_free(&device->alloc, device);
1422 }
1423
1424 VkResult radv_EnumerateInstanceLayerProperties(
1425 uint32_t* pPropertyCount,
1426 VkLayerProperties* pProperties)
1427 {
1428 if (pProperties == NULL) {
1429 *pPropertyCount = 0;
1430 return VK_SUCCESS;
1431 }
1432
1433 /* None supported at this time */
1434 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1435 }
1436
1437 VkResult radv_EnumerateDeviceLayerProperties(
1438 VkPhysicalDevice physicalDevice,
1439 uint32_t* pPropertyCount,
1440 VkLayerProperties* pProperties)
1441 {
1442 if (pProperties == NULL) {
1443 *pPropertyCount = 0;
1444 return VK_SUCCESS;
1445 }
1446
1447 /* None supported at this time */
1448 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1449 }
1450
1451 void radv_GetDeviceQueue2(
1452 VkDevice _device,
1453 const VkDeviceQueueInfo2* pQueueInfo,
1454 VkQueue* pQueue)
1455 {
1456 RADV_FROM_HANDLE(radv_device, device, _device);
1457
1458 *pQueue = radv_queue_to_handle(&device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex]);
1459 }
1460
1461 void radv_GetDeviceQueue(
1462 VkDevice _device,
1463 uint32_t queueFamilyIndex,
1464 uint32_t queueIndex,
1465 VkQueue* pQueue)
1466 {
1467 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
1468 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
1469 .queueFamilyIndex = queueFamilyIndex,
1470 .queueIndex = queueIndex
1471 };
1472
1473 radv_GetDeviceQueue2(_device, &info, pQueue);
1474 }
1475
1476 static void
1477 fill_geom_tess_rings(struct radv_queue *queue,
1478 uint32_t *map,
1479 bool add_sample_positions,
1480 uint32_t esgs_ring_size,
1481 struct radeon_winsys_bo *esgs_ring_bo,
1482 uint32_t gsvs_ring_size,
1483 struct radeon_winsys_bo *gsvs_ring_bo,
1484 uint32_t tess_factor_ring_size,
1485 uint32_t tess_offchip_ring_offset,
1486 uint32_t tess_offchip_ring_size,
1487 struct radeon_winsys_bo *tess_rings_bo)
1488 {
1489 uint64_t esgs_va = 0, gsvs_va = 0;
1490 uint64_t tess_va = 0, tess_offchip_va = 0;
1491 uint32_t *desc = &map[4];
1492
1493 if (esgs_ring_bo)
1494 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1495 if (gsvs_ring_bo)
1496 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1497 if (tess_rings_bo) {
1498 tess_va = radv_buffer_get_va(tess_rings_bo);
1499 tess_offchip_va = tess_va + tess_offchip_ring_offset;
1500 }
1501
1502 /* stride 0, num records - size, add tid, swizzle, elsize4,
1503 index stride 64 */
1504 desc[0] = esgs_va;
1505 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1506 S_008F04_STRIDE(0) |
1507 S_008F04_SWIZZLE_ENABLE(true);
1508 desc[2] = esgs_ring_size;
1509 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1510 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1511 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1512 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1513 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1514 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1515 S_008F0C_ELEMENT_SIZE(1) |
1516 S_008F0C_INDEX_STRIDE(3) |
1517 S_008F0C_ADD_TID_ENABLE(true);
1518
1519 desc += 4;
1520 /* GS entry for ES->GS ring */
1521 /* stride 0, num records - size, elsize0,
1522 index stride 0 */
1523 desc[0] = esgs_va;
1524 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1525 S_008F04_STRIDE(0) |
1526 S_008F04_SWIZZLE_ENABLE(false);
1527 desc[2] = esgs_ring_size;
1528 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1529 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1530 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1531 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1532 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1533 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1534 S_008F0C_ELEMENT_SIZE(0) |
1535 S_008F0C_INDEX_STRIDE(0) |
1536 S_008F0C_ADD_TID_ENABLE(false);
1537
1538 desc += 4;
1539 /* VS entry for GS->VS ring */
1540 /* stride 0, num records - size, elsize0,
1541 index stride 0 */
1542 desc[0] = gsvs_va;
1543 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1544 S_008F04_STRIDE(0) |
1545 S_008F04_SWIZZLE_ENABLE(false);
1546 desc[2] = gsvs_ring_size;
1547 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1548 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1549 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1550 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1551 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1552 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1553 S_008F0C_ELEMENT_SIZE(0) |
1554 S_008F0C_INDEX_STRIDE(0) |
1555 S_008F0C_ADD_TID_ENABLE(false);
1556 desc += 4;
1557
1558 /* stride gsvs_itemsize, num records 64
1559 elsize 4, index stride 16 */
1560 /* shader will patch stride and desc[2] */
1561 desc[0] = gsvs_va;
1562 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1563 S_008F04_STRIDE(0) |
1564 S_008F04_SWIZZLE_ENABLE(true);
1565 desc[2] = 0;
1566 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1567 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1568 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1569 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1570 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1571 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1572 S_008F0C_ELEMENT_SIZE(1) |
1573 S_008F0C_INDEX_STRIDE(1) |
1574 S_008F0C_ADD_TID_ENABLE(true);
1575 desc += 4;
1576
1577 desc[0] = tess_va;
1578 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
1579 S_008F04_STRIDE(0) |
1580 S_008F04_SWIZZLE_ENABLE(false);
1581 desc[2] = tess_factor_ring_size;
1582 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1583 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1584 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1585 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1586 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1587 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1588 S_008F0C_ELEMENT_SIZE(0) |
1589 S_008F0C_INDEX_STRIDE(0) |
1590 S_008F0C_ADD_TID_ENABLE(false);
1591 desc += 4;
1592
1593 desc[0] = tess_offchip_va;
1594 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1595 S_008F04_STRIDE(0) |
1596 S_008F04_SWIZZLE_ENABLE(false);
1597 desc[2] = tess_offchip_ring_size;
1598 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1599 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1600 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1601 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1602 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1603 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1604 S_008F0C_ELEMENT_SIZE(0) |
1605 S_008F0C_INDEX_STRIDE(0) |
1606 S_008F0C_ADD_TID_ENABLE(false);
1607 desc += 4;
1608
1609 /* add sample positions after all rings */
1610 memcpy(desc, queue->device->sample_locations_1x, 8);
1611 desc += 2;
1612 memcpy(desc, queue->device->sample_locations_2x, 16);
1613 desc += 4;
1614 memcpy(desc, queue->device->sample_locations_4x, 32);
1615 desc += 8;
1616 memcpy(desc, queue->device->sample_locations_8x, 64);
1617 desc += 16;
1618 memcpy(desc, queue->device->sample_locations_16x, 128);
1619 }
1620
1621 static unsigned
1622 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1623 {
1624 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1625 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1626 device->physical_device->rad_info.family != CHIP_STONEY;
1627 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1628 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1629 device->physical_device->rad_info.max_se;
1630 unsigned offchip_granularity;
1631 unsigned hs_offchip_param;
1632 switch (device->tess_offchip_block_dw_size) {
1633 default:
1634 assert(0);
1635 /* fall through */
1636 case 8192:
1637 offchip_granularity = V_03093C_X_8K_DWORDS;
1638 break;
1639 case 4096:
1640 offchip_granularity = V_03093C_X_4K_DWORDS;
1641 break;
1642 }
1643
1644 switch (device->physical_device->rad_info.chip_class) {
1645 case SI:
1646 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1647 break;
1648 case CIK:
1649 case VI:
1650 case GFX9:
1651 default:
1652 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1653 break;
1654 }
1655
1656 *max_offchip_buffers_p = max_offchip_buffers;
1657 if (device->physical_device->rad_info.chip_class >= CIK) {
1658 if (device->physical_device->rad_info.chip_class >= VI)
1659 --max_offchip_buffers;
1660 hs_offchip_param =
1661 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1662 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1663 } else {
1664 hs_offchip_param =
1665 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1666 }
1667 return hs_offchip_param;
1668 }
1669
1670 static VkResult
1671 radv_get_preamble_cs(struct radv_queue *queue,
1672 uint32_t scratch_size,
1673 uint32_t compute_scratch_size,
1674 uint32_t esgs_ring_size,
1675 uint32_t gsvs_ring_size,
1676 bool needs_tess_rings,
1677 bool needs_sample_positions,
1678 struct radeon_winsys_cs **initial_full_flush_preamble_cs,
1679 struct radeon_winsys_cs **initial_preamble_cs,
1680 struct radeon_winsys_cs **continue_preamble_cs)
1681 {
1682 struct radeon_winsys_bo *scratch_bo = NULL;
1683 struct radeon_winsys_bo *descriptor_bo = NULL;
1684 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1685 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1686 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1687 struct radeon_winsys_bo *tess_rings_bo = NULL;
1688 struct radeon_winsys_cs *dest_cs[3] = {0};
1689 bool add_tess_rings = false, add_sample_positions = false;
1690 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1691 unsigned max_offchip_buffers;
1692 unsigned hs_offchip_param = 0;
1693 unsigned tess_offchip_ring_offset;
1694 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
1695 if (!queue->has_tess_rings) {
1696 if (needs_tess_rings)
1697 add_tess_rings = true;
1698 }
1699 if (!queue->has_sample_positions) {
1700 if (needs_sample_positions)
1701 add_sample_positions = true;
1702 }
1703 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1704 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1705 &max_offchip_buffers);
1706 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
1707 tess_offchip_ring_size = max_offchip_buffers *
1708 queue->device->tess_offchip_block_dw_size * 4;
1709
1710 if (scratch_size <= queue->scratch_size &&
1711 compute_scratch_size <= queue->compute_scratch_size &&
1712 esgs_ring_size <= queue->esgs_ring_size &&
1713 gsvs_ring_size <= queue->gsvs_ring_size &&
1714 !add_tess_rings && !add_sample_positions &&
1715 queue->initial_preamble_cs) {
1716 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1717 *initial_preamble_cs = queue->initial_preamble_cs;
1718 *continue_preamble_cs = queue->continue_preamble_cs;
1719 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1720 *continue_preamble_cs = NULL;
1721 return VK_SUCCESS;
1722 }
1723
1724 if (scratch_size > queue->scratch_size) {
1725 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1726 scratch_size,
1727 4096,
1728 RADEON_DOMAIN_VRAM,
1729 ring_bo_flags);
1730 if (!scratch_bo)
1731 goto fail;
1732 } else
1733 scratch_bo = queue->scratch_bo;
1734
1735 if (compute_scratch_size > queue->compute_scratch_size) {
1736 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1737 compute_scratch_size,
1738 4096,
1739 RADEON_DOMAIN_VRAM,
1740 ring_bo_flags);
1741 if (!compute_scratch_bo)
1742 goto fail;
1743
1744 } else
1745 compute_scratch_bo = queue->compute_scratch_bo;
1746
1747 if (esgs_ring_size > queue->esgs_ring_size) {
1748 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1749 esgs_ring_size,
1750 4096,
1751 RADEON_DOMAIN_VRAM,
1752 ring_bo_flags);
1753 if (!esgs_ring_bo)
1754 goto fail;
1755 } else {
1756 esgs_ring_bo = queue->esgs_ring_bo;
1757 esgs_ring_size = queue->esgs_ring_size;
1758 }
1759
1760 if (gsvs_ring_size > queue->gsvs_ring_size) {
1761 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1762 gsvs_ring_size,
1763 4096,
1764 RADEON_DOMAIN_VRAM,
1765 ring_bo_flags);
1766 if (!gsvs_ring_bo)
1767 goto fail;
1768 } else {
1769 gsvs_ring_bo = queue->gsvs_ring_bo;
1770 gsvs_ring_size = queue->gsvs_ring_size;
1771 }
1772
1773 if (add_tess_rings) {
1774 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
1775 tess_offchip_ring_offset + tess_offchip_ring_size,
1776 256,
1777 RADEON_DOMAIN_VRAM,
1778 ring_bo_flags);
1779 if (!tess_rings_bo)
1780 goto fail;
1781 } else {
1782 tess_rings_bo = queue->tess_rings_bo;
1783 }
1784
1785 if (scratch_bo != queue->scratch_bo ||
1786 esgs_ring_bo != queue->esgs_ring_bo ||
1787 gsvs_ring_bo != queue->gsvs_ring_bo ||
1788 tess_rings_bo != queue->tess_rings_bo ||
1789 add_sample_positions) {
1790 uint32_t size = 0;
1791 if (gsvs_ring_bo || esgs_ring_bo ||
1792 tess_rings_bo || add_sample_positions) {
1793 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
1794 if (add_sample_positions)
1795 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1796 }
1797 else if (scratch_bo)
1798 size = 8; /* 2 dword */
1799
1800 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1801 size,
1802 4096,
1803 RADEON_DOMAIN_VRAM,
1804 RADEON_FLAG_CPU_ACCESS |
1805 RADEON_FLAG_NO_INTERPROCESS_SHARING |
1806 RADEON_FLAG_READ_ONLY);
1807 if (!descriptor_bo)
1808 goto fail;
1809 } else
1810 descriptor_bo = queue->descriptor_bo;
1811
1812 for(int i = 0; i < 3; ++i) {
1813 struct radeon_winsys_cs *cs = NULL;
1814 cs = queue->device->ws->cs_create(queue->device->ws,
1815 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1816 if (!cs)
1817 goto fail;
1818
1819 dest_cs[i] = cs;
1820
1821 if (scratch_bo)
1822 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo, 8);
1823
1824 if (esgs_ring_bo)
1825 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo, 8);
1826
1827 if (gsvs_ring_bo)
1828 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo, 8);
1829
1830 if (tess_rings_bo)
1831 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo, 8);
1832
1833 if (descriptor_bo)
1834 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo, 8);
1835
1836 if (descriptor_bo != queue->descriptor_bo) {
1837 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1838
1839 if (scratch_bo) {
1840 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
1841 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1842 S_008F04_SWIZZLE_ENABLE(1);
1843 map[0] = scratch_va;
1844 map[1] = rsrc1;
1845 }
1846
1847 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo ||
1848 add_sample_positions)
1849 fill_geom_tess_rings(queue, map, add_sample_positions,
1850 esgs_ring_size, esgs_ring_bo,
1851 gsvs_ring_size, gsvs_ring_bo,
1852 tess_factor_ring_size,
1853 tess_offchip_ring_offset,
1854 tess_offchip_ring_size,
1855 tess_rings_bo);
1856
1857 queue->device->ws->buffer_unmap(descriptor_bo);
1858 }
1859
1860 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
1861 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1862 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1863 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1864 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1865 }
1866
1867 if (esgs_ring_bo || gsvs_ring_bo) {
1868 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1869 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1870 radeon_emit(cs, esgs_ring_size >> 8);
1871 radeon_emit(cs, gsvs_ring_size >> 8);
1872 } else {
1873 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1874 radeon_emit(cs, esgs_ring_size >> 8);
1875 radeon_emit(cs, gsvs_ring_size >> 8);
1876 }
1877 }
1878
1879 if (tess_rings_bo) {
1880 uint64_t tf_va = radv_buffer_get_va(tess_rings_bo);
1881 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1882 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1883 S_030938_SIZE(tess_factor_ring_size / 4));
1884 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1885 tf_va >> 8);
1886 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1887 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1888 tf_va >> 40);
1889 }
1890 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
1891 } else {
1892 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1893 S_008988_SIZE(tess_factor_ring_size / 4));
1894 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1895 tf_va >> 8);
1896 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1897 hs_offchip_param);
1898 }
1899 }
1900
1901 if (descriptor_bo) {
1902 uint64_t va = radv_buffer_get_va(descriptor_bo);
1903 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1904 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1905 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1906 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
1907 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
1908
1909 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1910 radeon_set_sh_reg_seq(cs, regs[i], 2);
1911 radeon_emit(cs, va);
1912 radeon_emit(cs, va >> 32);
1913 }
1914 } else {
1915 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1916 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1917 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1918 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1919 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1920 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1921
1922 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1923 radeon_set_sh_reg_seq(cs, regs[i], 2);
1924 radeon_emit(cs, va);
1925 radeon_emit(cs, va >> 32);
1926 }
1927 }
1928 }
1929
1930 if (compute_scratch_bo) {
1931 uint64_t scratch_va = radv_buffer_get_va(compute_scratch_bo);
1932 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1933 S_008F04_SWIZZLE_ENABLE(1);
1934
1935 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo, 8);
1936
1937 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1938 radeon_emit(cs, scratch_va);
1939 radeon_emit(cs, rsrc1);
1940 }
1941
1942 if (i == 0) {
1943 si_cs_emit_cache_flush(cs,
1944 queue->device->physical_device->rad_info.chip_class,
1945 NULL, 0,
1946 queue->queue_family_index == RING_COMPUTE &&
1947 queue->device->physical_device->rad_info.chip_class >= CIK,
1948 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
1949 RADV_CMD_FLAG_INV_ICACHE |
1950 RADV_CMD_FLAG_INV_SMEM_L1 |
1951 RADV_CMD_FLAG_INV_VMEM_L1 |
1952 RADV_CMD_FLAG_INV_GLOBAL_L2);
1953 } else if (i == 1) {
1954 si_cs_emit_cache_flush(cs,
1955 queue->device->physical_device->rad_info.chip_class,
1956 NULL, 0,
1957 queue->queue_family_index == RING_COMPUTE &&
1958 queue->device->physical_device->rad_info.chip_class >= CIK,
1959 RADV_CMD_FLAG_INV_ICACHE |
1960 RADV_CMD_FLAG_INV_SMEM_L1 |
1961 RADV_CMD_FLAG_INV_VMEM_L1 |
1962 RADV_CMD_FLAG_INV_GLOBAL_L2);
1963 }
1964
1965 if (!queue->device->ws->cs_finalize(cs))
1966 goto fail;
1967 }
1968
1969 if (queue->initial_full_flush_preamble_cs)
1970 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1971
1972 if (queue->initial_preamble_cs)
1973 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1974
1975 if (queue->continue_preamble_cs)
1976 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1977
1978 queue->initial_full_flush_preamble_cs = dest_cs[0];
1979 queue->initial_preamble_cs = dest_cs[1];
1980 queue->continue_preamble_cs = dest_cs[2];
1981
1982 if (scratch_bo != queue->scratch_bo) {
1983 if (queue->scratch_bo)
1984 queue->device->ws->buffer_destroy(queue->scratch_bo);
1985 queue->scratch_bo = scratch_bo;
1986 queue->scratch_size = scratch_size;
1987 }
1988
1989 if (compute_scratch_bo != queue->compute_scratch_bo) {
1990 if (queue->compute_scratch_bo)
1991 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1992 queue->compute_scratch_bo = compute_scratch_bo;
1993 queue->compute_scratch_size = compute_scratch_size;
1994 }
1995
1996 if (esgs_ring_bo != queue->esgs_ring_bo) {
1997 if (queue->esgs_ring_bo)
1998 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1999 queue->esgs_ring_bo = esgs_ring_bo;
2000 queue->esgs_ring_size = esgs_ring_size;
2001 }
2002
2003 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2004 if (queue->gsvs_ring_bo)
2005 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2006 queue->gsvs_ring_bo = gsvs_ring_bo;
2007 queue->gsvs_ring_size = gsvs_ring_size;
2008 }
2009
2010 if (tess_rings_bo != queue->tess_rings_bo) {
2011 queue->tess_rings_bo = tess_rings_bo;
2012 queue->has_tess_rings = true;
2013 }
2014
2015 if (descriptor_bo != queue->descriptor_bo) {
2016 if (queue->descriptor_bo)
2017 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2018
2019 queue->descriptor_bo = descriptor_bo;
2020 }
2021
2022 if (add_sample_positions)
2023 queue->has_sample_positions = true;
2024
2025 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2026 *initial_preamble_cs = queue->initial_preamble_cs;
2027 *continue_preamble_cs = queue->continue_preamble_cs;
2028 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2029 *continue_preamble_cs = NULL;
2030 return VK_SUCCESS;
2031 fail:
2032 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2033 if (dest_cs[i])
2034 queue->device->ws->cs_destroy(dest_cs[i]);
2035 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2036 queue->device->ws->buffer_destroy(descriptor_bo);
2037 if (scratch_bo && scratch_bo != queue->scratch_bo)
2038 queue->device->ws->buffer_destroy(scratch_bo);
2039 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2040 queue->device->ws->buffer_destroy(compute_scratch_bo);
2041 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2042 queue->device->ws->buffer_destroy(esgs_ring_bo);
2043 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2044 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2045 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2046 queue->device->ws->buffer_destroy(tess_rings_bo);
2047 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2048 }
2049
2050 static VkResult radv_alloc_sem_counts(struct radv_winsys_sem_counts *counts,
2051 int num_sems,
2052 const VkSemaphore *sems,
2053 VkFence _fence,
2054 bool reset_temp)
2055 {
2056 int syncobj_idx = 0, sem_idx = 0;
2057
2058 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2059 return VK_SUCCESS;
2060
2061 for (uint32_t i = 0; i < num_sems; i++) {
2062 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2063
2064 if (sem->temp_syncobj || sem->syncobj)
2065 counts->syncobj_count++;
2066 else
2067 counts->sem_count++;
2068 }
2069
2070 if (_fence != VK_NULL_HANDLE) {
2071 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2072 if (fence->temp_syncobj || fence->syncobj)
2073 counts->syncobj_count++;
2074 }
2075
2076 if (counts->syncobj_count) {
2077 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2078 if (!counts->syncobj)
2079 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2080 }
2081
2082 if (counts->sem_count) {
2083 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2084 if (!counts->sem) {
2085 free(counts->syncobj);
2086 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2087 }
2088 }
2089
2090 for (uint32_t i = 0; i < num_sems; i++) {
2091 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2092
2093 if (sem->temp_syncobj) {
2094 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2095 }
2096 else if (sem->syncobj)
2097 counts->syncobj[syncobj_idx++] = sem->syncobj;
2098 else {
2099 assert(sem->sem);
2100 counts->sem[sem_idx++] = sem->sem;
2101 }
2102 }
2103
2104 if (_fence != VK_NULL_HANDLE) {
2105 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2106 if (fence->temp_syncobj)
2107 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2108 else if (fence->syncobj)
2109 counts->syncobj[syncobj_idx++] = fence->syncobj;
2110 }
2111
2112 return VK_SUCCESS;
2113 }
2114
2115 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2116 {
2117 free(sem_info->wait.syncobj);
2118 free(sem_info->wait.sem);
2119 free(sem_info->signal.syncobj);
2120 free(sem_info->signal.sem);
2121 }
2122
2123
2124 static void radv_free_temp_syncobjs(struct radv_device *device,
2125 int num_sems,
2126 const VkSemaphore *sems)
2127 {
2128 for (uint32_t i = 0; i < num_sems; i++) {
2129 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2130
2131 if (sem->temp_syncobj) {
2132 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2133 sem->temp_syncobj = 0;
2134 }
2135 }
2136 }
2137
2138 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
2139 int num_wait_sems,
2140 const VkSemaphore *wait_sems,
2141 int num_signal_sems,
2142 const VkSemaphore *signal_sems,
2143 VkFence fence)
2144 {
2145 VkResult ret;
2146 memset(sem_info, 0, sizeof(*sem_info));
2147
2148 ret = radv_alloc_sem_counts(&sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2149 if (ret)
2150 return ret;
2151 ret = radv_alloc_sem_counts(&sem_info->signal, num_signal_sems, signal_sems, fence, false);
2152 if (ret)
2153 radv_free_sem_info(sem_info);
2154
2155 /* caller can override these */
2156 sem_info->cs_emit_wait = true;
2157 sem_info->cs_emit_signal = true;
2158 return ret;
2159 }
2160
2161 /* Signals fence as soon as all the work currently put on queue is done. */
2162 static VkResult radv_signal_fence(struct radv_queue *queue,
2163 struct radv_fence *fence)
2164 {
2165 int ret;
2166 VkResult result;
2167 struct radv_winsys_sem_info sem_info;
2168
2169 result = radv_alloc_sem_info(&sem_info, 0, NULL, 0, NULL,
2170 radv_fence_to_handle(fence));
2171 if (result != VK_SUCCESS)
2172 return result;
2173
2174 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2175 &queue->device->empty_cs[queue->queue_family_index],
2176 1, NULL, NULL, &sem_info,
2177 false, fence->fence);
2178 radv_free_sem_info(&sem_info);
2179
2180 /* TODO: find a better error */
2181 if (ret)
2182 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2183
2184 return VK_SUCCESS;
2185 }
2186
2187 VkResult radv_QueueSubmit(
2188 VkQueue _queue,
2189 uint32_t submitCount,
2190 const VkSubmitInfo* pSubmits,
2191 VkFence _fence)
2192 {
2193 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2194 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2195 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2196 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2197 int ret;
2198 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2199 uint32_t scratch_size = 0;
2200 uint32_t compute_scratch_size = 0;
2201 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2202 struct radeon_winsys_cs *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2203 VkResult result;
2204 bool fence_emitted = false;
2205 bool tess_rings_needed = false;
2206 bool sample_positions_needed = false;
2207
2208 /* Do this first so failing to allocate scratch buffers can't result in
2209 * partially executed submissions. */
2210 for (uint32_t i = 0; i < submitCount; i++) {
2211 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2212 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2213 pSubmits[i].pCommandBuffers[j]);
2214
2215 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2216 compute_scratch_size = MAX2(compute_scratch_size,
2217 cmd_buffer->compute_scratch_size_needed);
2218 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2219 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2220 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2221 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2222 }
2223 }
2224
2225 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2226 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2227 sample_positions_needed, &initial_flush_preamble_cs,
2228 &initial_preamble_cs, &continue_preamble_cs);
2229 if (result != VK_SUCCESS)
2230 return result;
2231
2232 for (uint32_t i = 0; i < submitCount; i++) {
2233 struct radeon_winsys_cs **cs_array;
2234 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2235 bool can_patch = true;
2236 uint32_t advance;
2237 struct radv_winsys_sem_info sem_info;
2238
2239 result = radv_alloc_sem_info(&sem_info,
2240 pSubmits[i].waitSemaphoreCount,
2241 pSubmits[i].pWaitSemaphores,
2242 pSubmits[i].signalSemaphoreCount,
2243 pSubmits[i].pSignalSemaphores,
2244 _fence);
2245 if (result != VK_SUCCESS)
2246 return result;
2247
2248 if (!pSubmits[i].commandBufferCount) {
2249 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2250 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2251 &queue->device->empty_cs[queue->queue_family_index],
2252 1, NULL, NULL,
2253 &sem_info,
2254 false, base_fence);
2255 if (ret) {
2256 radv_loge("failed to submit CS %d\n", i);
2257 abort();
2258 }
2259 fence_emitted = true;
2260 }
2261 radv_free_sem_info(&sem_info);
2262 continue;
2263 }
2264
2265 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
2266 (pSubmits[i].commandBufferCount));
2267
2268 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2269 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2270 pSubmits[i].pCommandBuffers[j]);
2271 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2272
2273 cs_array[j] = cmd_buffer->cs;
2274 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2275 can_patch = false;
2276
2277 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2278 }
2279
2280 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2281 struct radeon_winsys_cs *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2282 advance = MIN2(max_cs_submission,
2283 pSubmits[i].commandBufferCount - j);
2284
2285 if (queue->device->trace_bo)
2286 *queue->device->trace_id_ptr = 0;
2287
2288 sem_info.cs_emit_wait = j == 0;
2289 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2290
2291 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2292 advance, initial_preamble, continue_preamble_cs,
2293 &sem_info,
2294 can_patch, base_fence);
2295
2296 if (ret) {
2297 radv_loge("failed to submit CS %d\n", i);
2298 abort();
2299 }
2300 fence_emitted = true;
2301 if (queue->device->trace_bo) {
2302 radv_check_gpu_hangs(queue, cs_array[j]);
2303 }
2304 }
2305
2306 radv_free_temp_syncobjs(queue->device,
2307 pSubmits[i].waitSemaphoreCount,
2308 pSubmits[i].pWaitSemaphores);
2309 radv_free_sem_info(&sem_info);
2310 free(cs_array);
2311 }
2312
2313 if (fence) {
2314 if (!fence_emitted) {
2315 radv_signal_fence(queue, fence);
2316 }
2317 fence->submitted = true;
2318 }
2319
2320 return VK_SUCCESS;
2321 }
2322
2323 VkResult radv_QueueWaitIdle(
2324 VkQueue _queue)
2325 {
2326 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2327
2328 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2329 radv_queue_family_to_ring(queue->queue_family_index),
2330 queue->queue_idx);
2331 return VK_SUCCESS;
2332 }
2333
2334 VkResult radv_DeviceWaitIdle(
2335 VkDevice _device)
2336 {
2337 RADV_FROM_HANDLE(radv_device, device, _device);
2338
2339 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2340 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2341 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2342 }
2343 }
2344 return VK_SUCCESS;
2345 }
2346
2347 VkResult radv_EnumerateInstanceExtensionProperties(
2348 const char* pLayerName,
2349 uint32_t* pPropertyCount,
2350 VkExtensionProperties* pProperties)
2351 {
2352 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2353
2354 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
2355 if (radv_supported_instance_extensions.extensions[i]) {
2356 vk_outarray_append(&out, prop) {
2357 *prop = radv_instance_extensions[i];
2358 }
2359 }
2360 }
2361
2362 return vk_outarray_status(&out);
2363 }
2364
2365 VkResult radv_EnumerateDeviceExtensionProperties(
2366 VkPhysicalDevice physicalDevice,
2367 const char* pLayerName,
2368 uint32_t* pPropertyCount,
2369 VkExtensionProperties* pProperties)
2370 {
2371 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2372 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2373
2374 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
2375 if (device->supported_extensions.extensions[i]) {
2376 vk_outarray_append(&out, prop) {
2377 *prop = radv_device_extensions[i];
2378 }
2379 }
2380 }
2381
2382 return vk_outarray_status(&out);
2383 }
2384
2385 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2386 VkInstance _instance,
2387 const char* pName)
2388 {
2389 RADV_FROM_HANDLE(radv_instance, instance, _instance);
2390
2391 return radv_lookup_entrypoint_checked(pName,
2392 instance ? instance->apiVersion : 0,
2393 instance ? &instance->enabled_extensions : NULL,
2394 NULL);
2395 }
2396
2397 /* The loader wants us to expose a second GetInstanceProcAddr function
2398 * to work around certain LD_PRELOAD issues seen in apps.
2399 */
2400 PUBLIC
2401 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2402 VkInstance instance,
2403 const char* pName);
2404
2405 PUBLIC
2406 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2407 VkInstance instance,
2408 const char* pName)
2409 {
2410 return radv_GetInstanceProcAddr(instance, pName);
2411 }
2412
2413 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2414 VkDevice _device,
2415 const char* pName)
2416 {
2417 RADV_FROM_HANDLE(radv_device, device, _device);
2418
2419 return radv_lookup_entrypoint_checked(pName,
2420 device->instance->apiVersion,
2421 &device->instance->enabled_extensions,
2422 &device->enabled_extensions);
2423 }
2424
2425 bool radv_get_memory_fd(struct radv_device *device,
2426 struct radv_device_memory *memory,
2427 int *pFD)
2428 {
2429 struct radeon_bo_metadata metadata;
2430
2431 if (memory->image) {
2432 radv_init_metadata(device, memory->image, &metadata);
2433 device->ws->buffer_set_metadata(memory->bo, &metadata);
2434 }
2435
2436 return device->ws->buffer_get_fd(device->ws, memory->bo,
2437 pFD);
2438 }
2439
2440 static VkResult radv_alloc_memory(struct radv_device *device,
2441 const VkMemoryAllocateInfo* pAllocateInfo,
2442 const VkAllocationCallbacks* pAllocator,
2443 VkDeviceMemory* pMem)
2444 {
2445 struct radv_device_memory *mem;
2446 VkResult result;
2447 enum radeon_bo_domain domain;
2448 uint32_t flags = 0;
2449 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
2450
2451 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2452
2453 if (pAllocateInfo->allocationSize == 0) {
2454 /* Apparently, this is allowed */
2455 *pMem = VK_NULL_HANDLE;
2456 return VK_SUCCESS;
2457 }
2458
2459 const VkImportMemoryFdInfoKHR *import_info =
2460 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2461 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2462 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2463 const VkExportMemoryAllocateInfoKHR *export_info =
2464 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO_KHR);
2465 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
2466 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
2467
2468 const struct wsi_memory_allocate_info *wsi_info =
2469 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
2470
2471 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2472 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2473 if (mem == NULL)
2474 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2475
2476 if (wsi_info && wsi_info->implicit_sync)
2477 flags |= RADEON_FLAG_IMPLICIT_SYNC;
2478
2479 if (dedicate_info) {
2480 mem->image = radv_image_from_handle(dedicate_info->image);
2481 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2482 } else {
2483 mem->image = NULL;
2484 mem->buffer = NULL;
2485 }
2486
2487 mem->user_ptr = NULL;
2488
2489 if (import_info) {
2490 assert(import_info->handleType ==
2491 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
2492 import_info->handleType ==
2493 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
2494 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2495 NULL, NULL);
2496 if (!mem->bo) {
2497 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2498 goto fail;
2499 } else {
2500 close(import_info->fd);
2501 goto out_success;
2502 }
2503 }
2504
2505 if (host_ptr_info) {
2506 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
2507 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
2508 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
2509 pAllocateInfo->allocationSize);
2510 if (!mem->bo) {
2511 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2512 goto fail;
2513 } else {
2514 mem->user_ptr = host_ptr_info->pHostPointer;
2515 goto out_success;
2516 }
2517 }
2518
2519 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2520 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2521 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
2522 domain = RADEON_DOMAIN_GTT;
2523 else
2524 domain = RADEON_DOMAIN_VRAM;
2525
2526 if (mem_type_index == RADV_MEM_TYPE_VRAM)
2527 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2528 else
2529 flags |= RADEON_FLAG_CPU_ACCESS;
2530
2531 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2532 flags |= RADEON_FLAG_GTT_WC;
2533
2534 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
2535 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
2536
2537 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2538 domain, flags);
2539
2540 if (!mem->bo) {
2541 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2542 goto fail;
2543 }
2544 mem->type_index = mem_type_index;
2545 out_success:
2546 *pMem = radv_device_memory_to_handle(mem);
2547
2548 return VK_SUCCESS;
2549
2550 fail:
2551 vk_free2(&device->alloc, pAllocator, mem);
2552
2553 return result;
2554 }
2555
2556 VkResult radv_AllocateMemory(
2557 VkDevice _device,
2558 const VkMemoryAllocateInfo* pAllocateInfo,
2559 const VkAllocationCallbacks* pAllocator,
2560 VkDeviceMemory* pMem)
2561 {
2562 RADV_FROM_HANDLE(radv_device, device, _device);
2563 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
2564 }
2565
2566 void radv_FreeMemory(
2567 VkDevice _device,
2568 VkDeviceMemory _mem,
2569 const VkAllocationCallbacks* pAllocator)
2570 {
2571 RADV_FROM_HANDLE(radv_device, device, _device);
2572 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2573
2574 if (mem == NULL)
2575 return;
2576
2577 device->ws->buffer_destroy(mem->bo);
2578 mem->bo = NULL;
2579
2580 vk_free2(&device->alloc, pAllocator, mem);
2581 }
2582
2583 VkResult radv_MapMemory(
2584 VkDevice _device,
2585 VkDeviceMemory _memory,
2586 VkDeviceSize offset,
2587 VkDeviceSize size,
2588 VkMemoryMapFlags flags,
2589 void** ppData)
2590 {
2591 RADV_FROM_HANDLE(radv_device, device, _device);
2592 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2593
2594 if (mem == NULL) {
2595 *ppData = NULL;
2596 return VK_SUCCESS;
2597 }
2598
2599 if (mem->user_ptr)
2600 *ppData = mem->user_ptr;
2601 else
2602 *ppData = device->ws->buffer_map(mem->bo);
2603
2604 if (*ppData) {
2605 *ppData += offset;
2606 return VK_SUCCESS;
2607 }
2608
2609 return vk_error(VK_ERROR_MEMORY_MAP_FAILED);
2610 }
2611
2612 void radv_UnmapMemory(
2613 VkDevice _device,
2614 VkDeviceMemory _memory)
2615 {
2616 RADV_FROM_HANDLE(radv_device, device, _device);
2617 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2618
2619 if (mem == NULL)
2620 return;
2621
2622 if (mem->user_ptr == NULL)
2623 device->ws->buffer_unmap(mem->bo);
2624 }
2625
2626 VkResult radv_FlushMappedMemoryRanges(
2627 VkDevice _device,
2628 uint32_t memoryRangeCount,
2629 const VkMappedMemoryRange* pMemoryRanges)
2630 {
2631 return VK_SUCCESS;
2632 }
2633
2634 VkResult radv_InvalidateMappedMemoryRanges(
2635 VkDevice _device,
2636 uint32_t memoryRangeCount,
2637 const VkMappedMemoryRange* pMemoryRanges)
2638 {
2639 return VK_SUCCESS;
2640 }
2641
2642 void radv_GetBufferMemoryRequirements(
2643 VkDevice _device,
2644 VkBuffer _buffer,
2645 VkMemoryRequirements* pMemoryRequirements)
2646 {
2647 RADV_FROM_HANDLE(radv_device, device, _device);
2648 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2649
2650 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2651
2652 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2653 pMemoryRequirements->alignment = 4096;
2654 else
2655 pMemoryRequirements->alignment = 16;
2656
2657 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2658 }
2659
2660 void radv_GetBufferMemoryRequirements2(
2661 VkDevice device,
2662 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2663 VkMemoryRequirements2KHR* pMemoryRequirements)
2664 {
2665 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2666 &pMemoryRequirements->memoryRequirements);
2667 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
2668 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2669 switch (ext->sType) {
2670 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2671 VkMemoryDedicatedRequirementsKHR *req =
2672 (VkMemoryDedicatedRequirementsKHR *) ext;
2673 req->requiresDedicatedAllocation = buffer->shareable;
2674 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2675 break;
2676 }
2677 default:
2678 break;
2679 }
2680 }
2681 }
2682
2683 void radv_GetImageMemoryRequirements(
2684 VkDevice _device,
2685 VkImage _image,
2686 VkMemoryRequirements* pMemoryRequirements)
2687 {
2688 RADV_FROM_HANDLE(radv_device, device, _device);
2689 RADV_FROM_HANDLE(radv_image, image, _image);
2690
2691 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2692
2693 pMemoryRequirements->size = image->size;
2694 pMemoryRequirements->alignment = image->alignment;
2695 }
2696
2697 void radv_GetImageMemoryRequirements2(
2698 VkDevice device,
2699 const VkImageMemoryRequirementsInfo2KHR* pInfo,
2700 VkMemoryRequirements2KHR* pMemoryRequirements)
2701 {
2702 radv_GetImageMemoryRequirements(device, pInfo->image,
2703 &pMemoryRequirements->memoryRequirements);
2704
2705 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
2706
2707 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2708 switch (ext->sType) {
2709 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2710 VkMemoryDedicatedRequirementsKHR *req =
2711 (VkMemoryDedicatedRequirementsKHR *) ext;
2712 req->requiresDedicatedAllocation = image->shareable;
2713 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2714 break;
2715 }
2716 default:
2717 break;
2718 }
2719 }
2720 }
2721
2722 void radv_GetImageSparseMemoryRequirements(
2723 VkDevice device,
2724 VkImage image,
2725 uint32_t* pSparseMemoryRequirementCount,
2726 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2727 {
2728 stub();
2729 }
2730
2731 void radv_GetImageSparseMemoryRequirements2(
2732 VkDevice device,
2733 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
2734 uint32_t* pSparseMemoryRequirementCount,
2735 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
2736 {
2737 stub();
2738 }
2739
2740 void radv_GetDeviceMemoryCommitment(
2741 VkDevice device,
2742 VkDeviceMemory memory,
2743 VkDeviceSize* pCommittedMemoryInBytes)
2744 {
2745 *pCommittedMemoryInBytes = 0;
2746 }
2747
2748 VkResult radv_BindBufferMemory2(VkDevice device,
2749 uint32_t bindInfoCount,
2750 const VkBindBufferMemoryInfoKHR *pBindInfos)
2751 {
2752 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2753 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2754 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
2755
2756 if (mem) {
2757 buffer->bo = mem->bo;
2758 buffer->offset = pBindInfos[i].memoryOffset;
2759 } else {
2760 buffer->bo = NULL;
2761 }
2762 }
2763 return VK_SUCCESS;
2764 }
2765
2766 VkResult radv_BindBufferMemory(
2767 VkDevice device,
2768 VkBuffer buffer,
2769 VkDeviceMemory memory,
2770 VkDeviceSize memoryOffset)
2771 {
2772 const VkBindBufferMemoryInfoKHR info = {
2773 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2774 .buffer = buffer,
2775 .memory = memory,
2776 .memoryOffset = memoryOffset
2777 };
2778
2779 return radv_BindBufferMemory2(device, 1, &info);
2780 }
2781
2782 VkResult radv_BindImageMemory2(VkDevice device,
2783 uint32_t bindInfoCount,
2784 const VkBindImageMemoryInfoKHR *pBindInfos)
2785 {
2786 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2787 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2788 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
2789
2790 if (mem) {
2791 image->bo = mem->bo;
2792 image->offset = pBindInfos[i].memoryOffset;
2793 } else {
2794 image->bo = NULL;
2795 image->offset = 0;
2796 }
2797 }
2798 return VK_SUCCESS;
2799 }
2800
2801
2802 VkResult radv_BindImageMemory(
2803 VkDevice device,
2804 VkImage image,
2805 VkDeviceMemory memory,
2806 VkDeviceSize memoryOffset)
2807 {
2808 const VkBindImageMemoryInfoKHR info = {
2809 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2810 .image = image,
2811 .memory = memory,
2812 .memoryOffset = memoryOffset
2813 };
2814
2815 return radv_BindImageMemory2(device, 1, &info);
2816 }
2817
2818
2819 static void
2820 radv_sparse_buffer_bind_memory(struct radv_device *device,
2821 const VkSparseBufferMemoryBindInfo *bind)
2822 {
2823 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
2824
2825 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2826 struct radv_device_memory *mem = NULL;
2827
2828 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2829 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2830
2831 device->ws->buffer_virtual_bind(buffer->bo,
2832 bind->pBinds[i].resourceOffset,
2833 bind->pBinds[i].size,
2834 mem ? mem->bo : NULL,
2835 bind->pBinds[i].memoryOffset);
2836 }
2837 }
2838
2839 static void
2840 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
2841 const VkSparseImageOpaqueMemoryBindInfo *bind)
2842 {
2843 RADV_FROM_HANDLE(radv_image, image, bind->image);
2844
2845 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2846 struct radv_device_memory *mem = NULL;
2847
2848 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2849 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2850
2851 device->ws->buffer_virtual_bind(image->bo,
2852 bind->pBinds[i].resourceOffset,
2853 bind->pBinds[i].size,
2854 mem ? mem->bo : NULL,
2855 bind->pBinds[i].memoryOffset);
2856 }
2857 }
2858
2859 VkResult radv_QueueBindSparse(
2860 VkQueue _queue,
2861 uint32_t bindInfoCount,
2862 const VkBindSparseInfo* pBindInfo,
2863 VkFence _fence)
2864 {
2865 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2866 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2867 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2868 bool fence_emitted = false;
2869
2870 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2871 struct radv_winsys_sem_info sem_info;
2872 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
2873 radv_sparse_buffer_bind_memory(queue->device,
2874 pBindInfo[i].pBufferBinds + j);
2875 }
2876
2877 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
2878 radv_sparse_image_opaque_bind_memory(queue->device,
2879 pBindInfo[i].pImageOpaqueBinds + j);
2880 }
2881
2882 VkResult result;
2883 result = radv_alloc_sem_info(&sem_info,
2884 pBindInfo[i].waitSemaphoreCount,
2885 pBindInfo[i].pWaitSemaphores,
2886 pBindInfo[i].signalSemaphoreCount,
2887 pBindInfo[i].pSignalSemaphores,
2888 _fence);
2889 if (result != VK_SUCCESS)
2890 return result;
2891
2892 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
2893 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2894 &queue->device->empty_cs[queue->queue_family_index],
2895 1, NULL, NULL,
2896 &sem_info,
2897 false, base_fence);
2898 fence_emitted = true;
2899 if (fence)
2900 fence->submitted = true;
2901 }
2902
2903 radv_free_sem_info(&sem_info);
2904
2905 }
2906
2907 if (fence) {
2908 if (!fence_emitted) {
2909 radv_signal_fence(queue, fence);
2910 }
2911 fence->submitted = true;
2912 }
2913
2914 return VK_SUCCESS;
2915 }
2916
2917 VkResult radv_CreateFence(
2918 VkDevice _device,
2919 const VkFenceCreateInfo* pCreateInfo,
2920 const VkAllocationCallbacks* pAllocator,
2921 VkFence* pFence)
2922 {
2923 RADV_FROM_HANDLE(radv_device, device, _device);
2924 const VkExportFenceCreateInfoKHR *export =
2925 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO_KHR);
2926 VkExternalFenceHandleTypeFlagsKHR handleTypes =
2927 export ? export->handleTypes : 0;
2928
2929 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
2930 sizeof(*fence), 8,
2931 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2932
2933 if (!fence)
2934 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2935
2936 fence->submitted = false;
2937 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
2938 fence->temp_syncobj = 0;
2939 if (device->always_use_syncobj || handleTypes) {
2940 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
2941 if (ret) {
2942 vk_free2(&device->alloc, pAllocator, fence);
2943 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2944 }
2945 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
2946 device->ws->signal_syncobj(device->ws, fence->syncobj);
2947 }
2948 fence->fence = NULL;
2949 } else {
2950 fence->fence = device->ws->create_fence();
2951 if (!fence->fence) {
2952 vk_free2(&device->alloc, pAllocator, fence);
2953 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2954 }
2955 fence->syncobj = 0;
2956 }
2957
2958 *pFence = radv_fence_to_handle(fence);
2959
2960 return VK_SUCCESS;
2961 }
2962
2963 void radv_DestroyFence(
2964 VkDevice _device,
2965 VkFence _fence,
2966 const VkAllocationCallbacks* pAllocator)
2967 {
2968 RADV_FROM_HANDLE(radv_device, device, _device);
2969 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2970
2971 if (!fence)
2972 return;
2973
2974 if (fence->temp_syncobj)
2975 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
2976 if (fence->syncobj)
2977 device->ws->destroy_syncobj(device->ws, fence->syncobj);
2978 if (fence->fence)
2979 device->ws->destroy_fence(fence->fence);
2980 vk_free2(&device->alloc, pAllocator, fence);
2981 }
2982
2983
2984 static uint64_t radv_get_current_time()
2985 {
2986 struct timespec tv;
2987 clock_gettime(CLOCK_MONOTONIC, &tv);
2988 return tv.tv_nsec + tv.tv_sec*1000000000ull;
2989 }
2990
2991 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
2992 {
2993 uint64_t current_time = radv_get_current_time();
2994
2995 timeout = MIN2(UINT64_MAX - current_time, timeout);
2996
2997 return current_time + timeout;
2998 }
2999
3000
3001 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3002 {
3003 for (uint32_t i = 0; i < fenceCount; ++i) {
3004 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3005 if (fence->syncobj || fence->temp_syncobj || (!fence->signalled && !fence->submitted))
3006 return false;
3007 }
3008 return true;
3009 }
3010
3011 VkResult radv_WaitForFences(
3012 VkDevice _device,
3013 uint32_t fenceCount,
3014 const VkFence* pFences,
3015 VkBool32 waitAll,
3016 uint64_t timeout)
3017 {
3018 RADV_FROM_HANDLE(radv_device, device, _device);
3019 timeout = radv_get_absolute_timeout(timeout);
3020
3021 if (device->always_use_syncobj) {
3022 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3023 if (!handles)
3024 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3025
3026 for (uint32_t i = 0; i < fenceCount; ++i) {
3027 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3028 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3029 }
3030
3031 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3032
3033 free(handles);
3034 return success ? VK_SUCCESS : VK_TIMEOUT;
3035 }
3036
3037 if (!waitAll && fenceCount > 1) {
3038 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3039 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3040 uint32_t wait_count = 0;
3041 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3042 if (!fences)
3043 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3044
3045 for (uint32_t i = 0; i < fenceCount; ++i) {
3046 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3047
3048 if (fence->signalled) {
3049 free(fences);
3050 return VK_SUCCESS;
3051 }
3052
3053 fences[wait_count++] = fence->fence;
3054 }
3055
3056 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3057 waitAll, timeout - radv_get_current_time());
3058
3059 free(fences);
3060 return success ? VK_SUCCESS : VK_TIMEOUT;
3061 }
3062
3063 while(radv_get_current_time() <= timeout) {
3064 for (uint32_t i = 0; i < fenceCount; ++i) {
3065 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3066 return VK_SUCCESS;
3067 }
3068 }
3069 return VK_TIMEOUT;
3070 }
3071
3072 for (uint32_t i = 0; i < fenceCount; ++i) {
3073 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3074 bool expired = false;
3075
3076 if (fence->temp_syncobj) {
3077 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3078 return VK_TIMEOUT;
3079 continue;
3080 }
3081
3082 if (fence->syncobj) {
3083 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3084 return VK_TIMEOUT;
3085 continue;
3086 }
3087
3088 if (fence->signalled)
3089 continue;
3090
3091 if (!fence->submitted) {
3092 while(radv_get_current_time() <= timeout && !fence->submitted)
3093 /* Do nothing */;
3094
3095 if (!fence->submitted)
3096 return VK_TIMEOUT;
3097
3098 /* Recheck as it may have been set by submitting operations. */
3099 if (fence->signalled)
3100 continue;
3101 }
3102
3103 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
3104 if (!expired)
3105 return VK_TIMEOUT;
3106
3107 fence->signalled = true;
3108 }
3109
3110 return VK_SUCCESS;
3111 }
3112
3113 VkResult radv_ResetFences(VkDevice _device,
3114 uint32_t fenceCount,
3115 const VkFence *pFences)
3116 {
3117 RADV_FROM_HANDLE(radv_device, device, _device);
3118
3119 for (unsigned i = 0; i < fenceCount; ++i) {
3120 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3121 fence->submitted = fence->signalled = false;
3122
3123 /* Per spec, we first restore the permanent payload, and then reset, so
3124 * having a temp syncobj should not skip resetting the permanent syncobj. */
3125 if (fence->temp_syncobj) {
3126 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3127 fence->temp_syncobj = 0;
3128 }
3129
3130 if (fence->syncobj) {
3131 device->ws->reset_syncobj(device->ws, fence->syncobj);
3132 }
3133 }
3134
3135 return VK_SUCCESS;
3136 }
3137
3138 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3139 {
3140 RADV_FROM_HANDLE(radv_device, device, _device);
3141 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3142
3143 if (fence->temp_syncobj) {
3144 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3145 return success ? VK_SUCCESS : VK_NOT_READY;
3146 }
3147
3148 if (fence->syncobj) {
3149 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3150 return success ? VK_SUCCESS : VK_NOT_READY;
3151 }
3152
3153 if (fence->signalled)
3154 return VK_SUCCESS;
3155 if (!fence->submitted)
3156 return VK_NOT_READY;
3157 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3158 return VK_NOT_READY;
3159
3160 return VK_SUCCESS;
3161 }
3162
3163
3164 // Queue semaphore functions
3165
3166 VkResult radv_CreateSemaphore(
3167 VkDevice _device,
3168 const VkSemaphoreCreateInfo* pCreateInfo,
3169 const VkAllocationCallbacks* pAllocator,
3170 VkSemaphore* pSemaphore)
3171 {
3172 RADV_FROM_HANDLE(radv_device, device, _device);
3173 const VkExportSemaphoreCreateInfoKHR *export =
3174 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
3175 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
3176 export ? export->handleTypes : 0;
3177
3178 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3179 sizeof(*sem), 8,
3180 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3181 if (!sem)
3182 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3183
3184 sem->temp_syncobj = 0;
3185 /* create a syncobject if we are going to export this semaphore */
3186 if (device->always_use_syncobj || handleTypes) {
3187 assert (device->physical_device->rad_info.has_syncobj);
3188 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3189 if (ret) {
3190 vk_free2(&device->alloc, pAllocator, sem);
3191 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3192 }
3193 sem->sem = NULL;
3194 } else {
3195 sem->sem = device->ws->create_sem(device->ws);
3196 if (!sem->sem) {
3197 vk_free2(&device->alloc, pAllocator, sem);
3198 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3199 }
3200 sem->syncobj = 0;
3201 }
3202
3203 *pSemaphore = radv_semaphore_to_handle(sem);
3204 return VK_SUCCESS;
3205 }
3206
3207 void radv_DestroySemaphore(
3208 VkDevice _device,
3209 VkSemaphore _semaphore,
3210 const VkAllocationCallbacks* pAllocator)
3211 {
3212 RADV_FROM_HANDLE(radv_device, device, _device);
3213 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3214 if (!_semaphore)
3215 return;
3216
3217 if (sem->syncobj)
3218 device->ws->destroy_syncobj(device->ws, sem->syncobj);
3219 else
3220 device->ws->destroy_sem(sem->sem);
3221 vk_free2(&device->alloc, pAllocator, sem);
3222 }
3223
3224 VkResult radv_CreateEvent(
3225 VkDevice _device,
3226 const VkEventCreateInfo* pCreateInfo,
3227 const VkAllocationCallbacks* pAllocator,
3228 VkEvent* pEvent)
3229 {
3230 RADV_FROM_HANDLE(radv_device, device, _device);
3231 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
3232 sizeof(*event), 8,
3233 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3234
3235 if (!event)
3236 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3237
3238 event->bo = device->ws->buffer_create(device->ws, 8, 8,
3239 RADEON_DOMAIN_GTT,
3240 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
3241 if (!event->bo) {
3242 vk_free2(&device->alloc, pAllocator, event);
3243 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
3244 }
3245
3246 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
3247
3248 *pEvent = radv_event_to_handle(event);
3249
3250 return VK_SUCCESS;
3251 }
3252
3253 void radv_DestroyEvent(
3254 VkDevice _device,
3255 VkEvent _event,
3256 const VkAllocationCallbacks* pAllocator)
3257 {
3258 RADV_FROM_HANDLE(radv_device, device, _device);
3259 RADV_FROM_HANDLE(radv_event, event, _event);
3260
3261 if (!event)
3262 return;
3263 device->ws->buffer_destroy(event->bo);
3264 vk_free2(&device->alloc, pAllocator, event);
3265 }
3266
3267 VkResult radv_GetEventStatus(
3268 VkDevice _device,
3269 VkEvent _event)
3270 {
3271 RADV_FROM_HANDLE(radv_event, event, _event);
3272
3273 if (*event->map == 1)
3274 return VK_EVENT_SET;
3275 return VK_EVENT_RESET;
3276 }
3277
3278 VkResult radv_SetEvent(
3279 VkDevice _device,
3280 VkEvent _event)
3281 {
3282 RADV_FROM_HANDLE(radv_event, event, _event);
3283 *event->map = 1;
3284
3285 return VK_SUCCESS;
3286 }
3287
3288 VkResult radv_ResetEvent(
3289 VkDevice _device,
3290 VkEvent _event)
3291 {
3292 RADV_FROM_HANDLE(radv_event, event, _event);
3293 *event->map = 0;
3294
3295 return VK_SUCCESS;
3296 }
3297
3298 VkResult radv_CreateBuffer(
3299 VkDevice _device,
3300 const VkBufferCreateInfo* pCreateInfo,
3301 const VkAllocationCallbacks* pAllocator,
3302 VkBuffer* pBuffer)
3303 {
3304 RADV_FROM_HANDLE(radv_device, device, _device);
3305 struct radv_buffer *buffer;
3306
3307 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
3308
3309 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
3310 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3311 if (buffer == NULL)
3312 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3313
3314 buffer->size = pCreateInfo->size;
3315 buffer->usage = pCreateInfo->usage;
3316 buffer->bo = NULL;
3317 buffer->offset = 0;
3318 buffer->flags = pCreateInfo->flags;
3319
3320 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
3321 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR) != NULL;
3322
3323 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
3324 buffer->bo = device->ws->buffer_create(device->ws,
3325 align64(buffer->size, 4096),
3326 4096, 0, RADEON_FLAG_VIRTUAL);
3327 if (!buffer->bo) {
3328 vk_free2(&device->alloc, pAllocator, buffer);
3329 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
3330 }
3331 }
3332
3333 *pBuffer = radv_buffer_to_handle(buffer);
3334
3335 return VK_SUCCESS;
3336 }
3337
3338 void radv_DestroyBuffer(
3339 VkDevice _device,
3340 VkBuffer _buffer,
3341 const VkAllocationCallbacks* pAllocator)
3342 {
3343 RADV_FROM_HANDLE(radv_device, device, _device);
3344 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3345
3346 if (!buffer)
3347 return;
3348
3349 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3350 device->ws->buffer_destroy(buffer->bo);
3351
3352 vk_free2(&device->alloc, pAllocator, buffer);
3353 }
3354
3355 static inline unsigned
3356 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
3357 {
3358 if (stencil)
3359 return image->surface.u.legacy.stencil_tiling_index[level];
3360 else
3361 return image->surface.u.legacy.tiling_index[level];
3362 }
3363
3364 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
3365 {
3366 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
3367 }
3368
3369 static void
3370 radv_initialise_color_surface(struct radv_device *device,
3371 struct radv_color_buffer_info *cb,
3372 struct radv_image_view *iview)
3373 {
3374 const struct vk_format_description *desc;
3375 unsigned ntype, format, swap, endian;
3376 unsigned blend_clamp = 0, blend_bypass = 0;
3377 uint64_t va;
3378 const struct radeon_surf *surf = &iview->image->surface;
3379
3380 desc = vk_format_description(iview->vk_format);
3381
3382 memset(cb, 0, sizeof(*cb));
3383
3384 /* Intensity is implemented as Red, so treat it that way. */
3385 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
3386
3387 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3388
3389 cb->cb_color_base = va >> 8;
3390
3391 if (device->physical_device->rad_info.chip_class >= GFX9) {
3392 struct gfx9_surf_meta_flags meta;
3393 if (iview->image->dcc_offset)
3394 meta = iview->image->surface.u.gfx9.dcc;
3395 else
3396 meta = iview->image->surface.u.gfx9.cmask;
3397
3398 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3399 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
3400 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3401 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3402
3403 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
3404 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3405 } else {
3406 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
3407 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3408
3409 cb->cb_color_base += level_info->offset >> 8;
3410 if (level_info->mode == RADEON_SURF_MODE_2D)
3411 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3412
3413 pitch_tile_max = level_info->nblk_x / 8 - 1;
3414 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
3415 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
3416
3417 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3418 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3419 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
3420
3421 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3422
3423 if (iview->image->fmask.size) {
3424 if (device->physical_device->rad_info.chip_class >= CIK)
3425 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
3426 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
3427 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
3428 } else {
3429 /* This must be set for fast clear to work without FMASK. */
3430 if (device->physical_device->rad_info.chip_class >= CIK)
3431 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3432 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3433 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3434 }
3435 }
3436
3437 /* CMASK variables */
3438 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3439 va += iview->image->cmask.offset;
3440 cb->cb_color_cmask = va >> 8;
3441
3442 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3443 va += iview->image->dcc_offset;
3444 cb->cb_dcc_base = va >> 8;
3445 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
3446
3447 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3448 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3449 S_028C6C_SLICE_MAX(max_slice);
3450
3451 if (iview->image->info.samples > 1) {
3452 unsigned log_samples = util_logbase2(iview->image->info.samples);
3453
3454 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3455 S_028C74_NUM_FRAGMENTS(log_samples);
3456 }
3457
3458 if (iview->image->fmask.size) {
3459 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3460 cb->cb_color_fmask = va >> 8;
3461 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3462 } else {
3463 cb->cb_color_fmask = cb->cb_color_base;
3464 }
3465
3466 ntype = radv_translate_color_numformat(iview->vk_format,
3467 desc,
3468 vk_format_get_first_non_void_channel(iview->vk_format));
3469 format = radv_translate_colorformat(iview->vk_format);
3470 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3471 radv_finishme("Illegal color\n");
3472 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3473 endian = radv_colorformat_endian_swap(format);
3474
3475 /* blend clamp should be set for all NORM/SRGB types */
3476 if (ntype == V_028C70_NUMBER_UNORM ||
3477 ntype == V_028C70_NUMBER_SNORM ||
3478 ntype == V_028C70_NUMBER_SRGB)
3479 blend_clamp = 1;
3480
3481 /* set blend bypass according to docs if SINT/UINT or
3482 8/24 COLOR variants */
3483 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3484 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3485 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3486 blend_clamp = 0;
3487 blend_bypass = 1;
3488 }
3489 #if 0
3490 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3491 (format == V_028C70_COLOR_8 ||
3492 format == V_028C70_COLOR_8_8 ||
3493 format == V_028C70_COLOR_8_8_8_8))
3494 ->color_is_int8 = true;
3495 #endif
3496 cb->cb_color_info = S_028C70_FORMAT(format) |
3497 S_028C70_COMP_SWAP(swap) |
3498 S_028C70_BLEND_CLAMP(blend_clamp) |
3499 S_028C70_BLEND_BYPASS(blend_bypass) |
3500 S_028C70_SIMPLE_FLOAT(1) |
3501 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3502 ntype != V_028C70_NUMBER_SNORM &&
3503 ntype != V_028C70_NUMBER_SRGB &&
3504 format != V_028C70_COLOR_8_24 &&
3505 format != V_028C70_COLOR_24_8) |
3506 S_028C70_NUMBER_TYPE(ntype) |
3507 S_028C70_ENDIAN(endian);
3508 if ((iview->image->info.samples > 1) && iview->image->fmask.size) {
3509 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3510 if (device->physical_device->rad_info.chip_class == SI) {
3511 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3512 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3513 }
3514 }
3515
3516 if (iview->image->cmask.size &&
3517 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3518 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3519
3520 if (radv_vi_dcc_enabled(iview->image, iview->base_mip))
3521 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3522
3523 if (device->physical_device->rad_info.chip_class >= VI) {
3524 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
3525 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
3526 unsigned independent_64b_blocks = 0;
3527 unsigned max_compressed_block_size;
3528
3529 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
3530 64 for APU because all of our APUs to date use DIMMs which have
3531 a request granularity size of 64B while all other chips have a
3532 32B request size */
3533 if (!device->physical_device->rad_info.has_dedicated_vram)
3534 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
3535
3536 if (iview->image->info.samples > 1) {
3537 if (iview->image->surface.bpe == 1)
3538 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3539 else if (iview->image->surface.bpe == 2)
3540 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
3541 }
3542
3543 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT | VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
3544 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
3545 independent_64b_blocks = 1;
3546 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3547 } else
3548 max_compressed_block_size = max_uncompressed_block_size;
3549
3550 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3551 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
3552 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
3553 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
3554 }
3555
3556 /* This must be set for fast clear to work without FMASK. */
3557 if (!iview->image->fmask.size &&
3558 device->physical_device->rad_info.chip_class == SI) {
3559 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3560 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3561 }
3562
3563 if (device->physical_device->rad_info.chip_class >= GFX9) {
3564 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
3565 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
3566
3567 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3568 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3569 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3570 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
3571 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
3572 S_028C68_MAX_MIP(iview->image->info.levels - 1);
3573 }
3574 }
3575
3576 static void
3577 radv_initialise_ds_surface(struct radv_device *device,
3578 struct radv_ds_buffer_info *ds,
3579 struct radv_image_view *iview)
3580 {
3581 unsigned level = iview->base_mip;
3582 unsigned format, stencil_format;
3583 uint64_t va, s_offs, z_offs;
3584 bool stencil_only = false;
3585 memset(ds, 0, sizeof(*ds));
3586 switch (iview->image->vk_format) {
3587 case VK_FORMAT_D24_UNORM_S8_UINT:
3588 case VK_FORMAT_X8_D24_UNORM_PACK32:
3589 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3590 ds->offset_scale = 2.0f;
3591 break;
3592 case VK_FORMAT_D16_UNORM:
3593 case VK_FORMAT_D16_UNORM_S8_UINT:
3594 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3595 ds->offset_scale = 4.0f;
3596 break;
3597 case VK_FORMAT_D32_SFLOAT:
3598 case VK_FORMAT_D32_SFLOAT_S8_UINT:
3599 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3600 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3601 ds->offset_scale = 1.0f;
3602 break;
3603 case VK_FORMAT_S8_UINT:
3604 stencil_only = true;
3605 break;
3606 default:
3607 break;
3608 }
3609
3610 format = radv_translate_dbformat(iview->image->vk_format);
3611 stencil_format = iview->image->surface.has_stencil ?
3612 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
3613
3614 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3615 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
3616 S_028008_SLICE_MAX(max_slice);
3617
3618 ds->db_htile_data_base = 0;
3619 ds->db_htile_surface = 0;
3620
3621 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3622 s_offs = z_offs = va;
3623
3624 if (device->physical_device->rad_info.chip_class >= GFX9) {
3625 assert(iview->image->surface.u.gfx9.surf_offset == 0);
3626 s_offs += iview->image->surface.u.gfx9.stencil_offset;
3627
3628 ds->db_z_info = S_028038_FORMAT(format) |
3629 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
3630 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3631 S_028038_MAXMIP(iview->image->info.levels - 1);
3632 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
3633 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
3634
3635 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3636 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
3637 ds->db_depth_view |= S_028008_MIPID(level);
3638
3639 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
3640 S_02801C_Y_MAX(iview->image->info.height - 1);
3641
3642 if (radv_htile_enabled(iview->image, level)) {
3643 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
3644
3645 if (iview->image->tc_compatible_htile) {
3646 unsigned max_zplanes = 4;
3647
3648 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
3649 iview->image->info.samples > 1)
3650 max_zplanes = 2;
3651
3652 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
3653 S_028038_ITERATE_FLUSH(1);
3654 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
3655 }
3656
3657 if (!iview->image->surface.has_stencil)
3658 /* Use all of the htile_buffer for depth if there's no stencil. */
3659 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
3660 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3661 iview->image->htile_offset;
3662 ds->db_htile_data_base = va >> 8;
3663 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
3664 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
3665 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
3666 }
3667 } else {
3668 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
3669
3670 if (stencil_only)
3671 level_info = &iview->image->surface.u.legacy.stencil_level[level];
3672
3673 z_offs += iview->image->surface.u.legacy.level[level].offset;
3674 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
3675
3676 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!iview->image->tc_compatible_htile);
3677 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
3678 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
3679
3680 if (iview->image->info.samples > 1)
3681 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
3682
3683 if (device->physical_device->rad_info.chip_class >= CIK) {
3684 struct radeon_info *info = &device->physical_device->rad_info;
3685 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
3686 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
3687 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
3688 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
3689 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
3690 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
3691
3692 if (stencil_only)
3693 tile_mode = stencil_tile_mode;
3694
3695 ds->db_depth_info |=
3696 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
3697 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
3698 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
3699 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
3700 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
3701 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
3702 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
3703 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
3704 } else {
3705 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
3706 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3707 tile_mode_index = si_tile_mode_index(iview->image, level, true);
3708 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
3709 if (stencil_only)
3710 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3711 }
3712
3713 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
3714 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
3715 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
3716
3717 if (radv_htile_enabled(iview->image, level)) {
3718 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
3719
3720 if (!iview->image->surface.has_stencil &&
3721 !iview->image->tc_compatible_htile)
3722 /* Use all of the htile_buffer for depth if there's no stencil. */
3723 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
3724
3725 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3726 iview->image->htile_offset;
3727 ds->db_htile_data_base = va >> 8;
3728 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
3729
3730 if (iview->image->tc_compatible_htile) {
3731 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
3732
3733 if (iview->image->info.samples <= 1)
3734 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
3735 else if (iview->image->info.samples <= 4)
3736 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
3737 else
3738 ds->db_z_info|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
3739 }
3740 }
3741 }
3742
3743 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
3744 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
3745 }
3746
3747 VkResult radv_CreateFramebuffer(
3748 VkDevice _device,
3749 const VkFramebufferCreateInfo* pCreateInfo,
3750 const VkAllocationCallbacks* pAllocator,
3751 VkFramebuffer* pFramebuffer)
3752 {
3753 RADV_FROM_HANDLE(radv_device, device, _device);
3754 struct radv_framebuffer *framebuffer;
3755
3756 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
3757
3758 size_t size = sizeof(*framebuffer) +
3759 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
3760 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
3761 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3762 if (framebuffer == NULL)
3763 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3764
3765 framebuffer->attachment_count = pCreateInfo->attachmentCount;
3766 framebuffer->width = pCreateInfo->width;
3767 framebuffer->height = pCreateInfo->height;
3768 framebuffer->layers = pCreateInfo->layers;
3769 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
3770 VkImageView _iview = pCreateInfo->pAttachments[i];
3771 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
3772 framebuffer->attachments[i].attachment = iview;
3773 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
3774 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
3775 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3776 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
3777 }
3778 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
3779 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
3780 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
3781 }
3782
3783 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
3784 return VK_SUCCESS;
3785 }
3786
3787 void radv_DestroyFramebuffer(
3788 VkDevice _device,
3789 VkFramebuffer _fb,
3790 const VkAllocationCallbacks* pAllocator)
3791 {
3792 RADV_FROM_HANDLE(radv_device, device, _device);
3793 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
3794
3795 if (!fb)
3796 return;
3797 vk_free2(&device->alloc, pAllocator, fb);
3798 }
3799
3800 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
3801 {
3802 switch (address_mode) {
3803 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
3804 return V_008F30_SQ_TEX_WRAP;
3805 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
3806 return V_008F30_SQ_TEX_MIRROR;
3807 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
3808 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
3809 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
3810 return V_008F30_SQ_TEX_CLAMP_BORDER;
3811 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
3812 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
3813 default:
3814 unreachable("illegal tex wrap mode");
3815 break;
3816 }
3817 }
3818
3819 static unsigned
3820 radv_tex_compare(VkCompareOp op)
3821 {
3822 switch (op) {
3823 case VK_COMPARE_OP_NEVER:
3824 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
3825 case VK_COMPARE_OP_LESS:
3826 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
3827 case VK_COMPARE_OP_EQUAL:
3828 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
3829 case VK_COMPARE_OP_LESS_OR_EQUAL:
3830 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
3831 case VK_COMPARE_OP_GREATER:
3832 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
3833 case VK_COMPARE_OP_NOT_EQUAL:
3834 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
3835 case VK_COMPARE_OP_GREATER_OR_EQUAL:
3836 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
3837 case VK_COMPARE_OP_ALWAYS:
3838 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
3839 default:
3840 unreachable("illegal compare mode");
3841 break;
3842 }
3843 }
3844
3845 static unsigned
3846 radv_tex_filter(VkFilter filter, unsigned max_ansio)
3847 {
3848 switch (filter) {
3849 case VK_FILTER_NEAREST:
3850 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
3851 V_008F38_SQ_TEX_XY_FILTER_POINT);
3852 case VK_FILTER_LINEAR:
3853 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
3854 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
3855 case VK_FILTER_CUBIC_IMG:
3856 default:
3857 fprintf(stderr, "illegal texture filter");
3858 return 0;
3859 }
3860 }
3861
3862 static unsigned
3863 radv_tex_mipfilter(VkSamplerMipmapMode mode)
3864 {
3865 switch (mode) {
3866 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
3867 return V_008F38_SQ_TEX_Z_FILTER_POINT;
3868 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
3869 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
3870 default:
3871 return V_008F38_SQ_TEX_Z_FILTER_NONE;
3872 }
3873 }
3874
3875 static unsigned
3876 radv_tex_bordercolor(VkBorderColor bcolor)
3877 {
3878 switch (bcolor) {
3879 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
3880 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
3881 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3882 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
3883 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
3884 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3885 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
3886 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
3887 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3888 default:
3889 break;
3890 }
3891 return 0;
3892 }
3893
3894 static unsigned
3895 radv_tex_aniso_filter(unsigned filter)
3896 {
3897 if (filter < 2)
3898 return 0;
3899 if (filter < 4)
3900 return 1;
3901 if (filter < 8)
3902 return 2;
3903 if (filter < 16)
3904 return 3;
3905 return 4;
3906 }
3907
3908 static void
3909 radv_init_sampler(struct radv_device *device,
3910 struct radv_sampler *sampler,
3911 const VkSamplerCreateInfo *pCreateInfo)
3912 {
3913 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
3914 (uint32_t) pCreateInfo->maxAnisotropy : 0;
3915 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
3916 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
3917
3918 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
3919 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
3920 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
3921 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3922 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
3923 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
3924 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3925 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3926 S_008F30_DISABLE_CUBE_WRAP(0) |
3927 S_008F30_COMPAT_MODE(is_vi));
3928 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
3929 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
3930 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3931 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
3932 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
3933 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
3934 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
3935 S_008F38_MIP_POINT_PRECLAMP(0) |
3936 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
3937 S_008F38_FILTER_PREC_FIX(1) |
3938 S_008F38_ANISO_OVERRIDE(is_vi));
3939 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3940 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
3941 }
3942
3943 VkResult radv_CreateSampler(
3944 VkDevice _device,
3945 const VkSamplerCreateInfo* pCreateInfo,
3946 const VkAllocationCallbacks* pAllocator,
3947 VkSampler* pSampler)
3948 {
3949 RADV_FROM_HANDLE(radv_device, device, _device);
3950 struct radv_sampler *sampler;
3951
3952 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
3953
3954 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
3955 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3956 if (!sampler)
3957 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3958
3959 radv_init_sampler(device, sampler, pCreateInfo);
3960 *pSampler = radv_sampler_to_handle(sampler);
3961
3962 return VK_SUCCESS;
3963 }
3964
3965 void radv_DestroySampler(
3966 VkDevice _device,
3967 VkSampler _sampler,
3968 const VkAllocationCallbacks* pAllocator)
3969 {
3970 RADV_FROM_HANDLE(radv_device, device, _device);
3971 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
3972
3973 if (!sampler)
3974 return;
3975 vk_free2(&device->alloc, pAllocator, sampler);
3976 }
3977
3978 /* vk_icd.h does not declare this function, so we declare it here to
3979 * suppress Wmissing-prototypes.
3980 */
3981 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3982 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
3983
3984 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3985 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
3986 {
3987 /* For the full details on loader interface versioning, see
3988 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3989 * What follows is a condensed summary, to help you navigate the large and
3990 * confusing official doc.
3991 *
3992 * - Loader interface v0 is incompatible with later versions. We don't
3993 * support it.
3994 *
3995 * - In loader interface v1:
3996 * - The first ICD entrypoint called by the loader is
3997 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3998 * entrypoint.
3999 * - The ICD must statically expose no other Vulkan symbol unless it is
4000 * linked with -Bsymbolic.
4001 * - Each dispatchable Vulkan handle created by the ICD must be
4002 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4003 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4004 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4005 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4006 * such loader-managed surfaces.
4007 *
4008 * - Loader interface v2 differs from v1 in:
4009 * - The first ICD entrypoint called by the loader is
4010 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4011 * statically expose this entrypoint.
4012 *
4013 * - Loader interface v3 differs from v2 in:
4014 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4015 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4016 * because the loader no longer does so.
4017 */
4018 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4019 return VK_SUCCESS;
4020 }
4021
4022 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4023 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4024 int *pFD)
4025 {
4026 RADV_FROM_HANDLE(radv_device, device, _device);
4027 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4028
4029 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4030
4031 /* At the moment, we support only the below handle types. */
4032 assert(pGetFdInfo->handleType ==
4033 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4034 pGetFdInfo->handleType ==
4035 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4036
4037 bool ret = radv_get_memory_fd(device, memory, pFD);
4038 if (ret == false)
4039 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
4040 return VK_SUCCESS;
4041 }
4042
4043 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4044 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
4045 int fd,
4046 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4047 {
4048 switch (handleType) {
4049 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4050 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4051 return VK_SUCCESS;
4052
4053 default:
4054 /* The valid usage section for this function says:
4055 *
4056 * "handleType must not be one of the handle types defined as
4057 * opaque."
4058 *
4059 * So opaque handle types fall into the default "unsupported" case.
4060 */
4061 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4062 }
4063 }
4064
4065 static VkResult radv_import_opaque_fd(struct radv_device *device,
4066 int fd,
4067 uint32_t *syncobj)
4068 {
4069 uint32_t syncobj_handle = 0;
4070 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4071 if (ret != 0)
4072 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4073
4074 if (*syncobj)
4075 device->ws->destroy_syncobj(device->ws, *syncobj);
4076
4077 *syncobj = syncobj_handle;
4078 close(fd);
4079
4080 return VK_SUCCESS;
4081 }
4082
4083 static VkResult radv_import_sync_fd(struct radv_device *device,
4084 int fd,
4085 uint32_t *syncobj)
4086 {
4087 /* If we create a syncobj we do it locally so that if we have an error, we don't
4088 * leave a syncobj in an undetermined state in the fence. */
4089 uint32_t syncobj_handle = *syncobj;
4090 if (!syncobj_handle) {
4091 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4092 if (ret) {
4093 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4094 }
4095 }
4096
4097 if (fd == -1) {
4098 device->ws->signal_syncobj(device->ws, syncobj_handle);
4099 } else {
4100 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
4101 if (ret != 0)
4102 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4103 }
4104
4105 *syncobj = syncobj_handle;
4106 if (fd != -1)
4107 close(fd);
4108
4109 return VK_SUCCESS;
4110 }
4111
4112 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
4113 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
4114 {
4115 RADV_FROM_HANDLE(radv_device, device, _device);
4116 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
4117 uint32_t *syncobj_dst = NULL;
4118
4119 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
4120 syncobj_dst = &sem->temp_syncobj;
4121 } else {
4122 syncobj_dst = &sem->syncobj;
4123 }
4124
4125 switch(pImportSemaphoreFdInfo->handleType) {
4126 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4127 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4128 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4129 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4130 default:
4131 unreachable("Unhandled semaphore handle type");
4132 }
4133 }
4134
4135 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
4136 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
4137 int *pFd)
4138 {
4139 RADV_FROM_HANDLE(radv_device, device, _device);
4140 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
4141 int ret;
4142 uint32_t syncobj_handle;
4143
4144 if (sem->temp_syncobj)
4145 syncobj_handle = sem->temp_syncobj;
4146 else
4147 syncobj_handle = sem->syncobj;
4148
4149 switch(pGetFdInfo->handleType) {
4150 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4151 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4152 break;
4153 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4154 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4155 if (!ret) {
4156 if (sem->temp_syncobj) {
4157 close (sem->temp_syncobj);
4158 sem->temp_syncobj = 0;
4159 } else {
4160 device->ws->reset_syncobj(device->ws, syncobj_handle);
4161 }
4162 }
4163 break;
4164 default:
4165 unreachable("Unhandled semaphore handle type");
4166 }
4167
4168 if (ret)
4169 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4170 return VK_SUCCESS;
4171 }
4172
4173 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
4174 VkPhysicalDevice physicalDevice,
4175 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
4176 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
4177 {
4178 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4179
4180 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
4181 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4182 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4183 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4184 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4185 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4186 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4187 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4188 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
4189 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4190 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4191 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4192 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4193 } else {
4194 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
4195 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
4196 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
4197 }
4198 }
4199
4200 VkResult radv_ImportFenceFdKHR(VkDevice _device,
4201 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
4202 {
4203 RADV_FROM_HANDLE(radv_device, device, _device);
4204 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
4205 uint32_t *syncobj_dst = NULL;
4206
4207
4208 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT_KHR) {
4209 syncobj_dst = &fence->temp_syncobj;
4210 } else {
4211 syncobj_dst = &fence->syncobj;
4212 }
4213
4214 switch(pImportFenceFdInfo->handleType) {
4215 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4216 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4217 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4218 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4219 default:
4220 unreachable("Unhandled fence handle type");
4221 }
4222 }
4223
4224 VkResult radv_GetFenceFdKHR(VkDevice _device,
4225 const VkFenceGetFdInfoKHR *pGetFdInfo,
4226 int *pFd)
4227 {
4228 RADV_FROM_HANDLE(radv_device, device, _device);
4229 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
4230 int ret;
4231 uint32_t syncobj_handle;
4232
4233 if (fence->temp_syncobj)
4234 syncobj_handle = fence->temp_syncobj;
4235 else
4236 syncobj_handle = fence->syncobj;
4237
4238 switch(pGetFdInfo->handleType) {
4239 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4240 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4241 break;
4242 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4243 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4244 if (!ret) {
4245 if (fence->temp_syncobj) {
4246 close (fence->temp_syncobj);
4247 fence->temp_syncobj = 0;
4248 } else {
4249 device->ws->reset_syncobj(device->ws, syncobj_handle);
4250 }
4251 }
4252 break;
4253 default:
4254 unreachable("Unhandled fence handle type");
4255 }
4256
4257 if (ret)
4258 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4259 return VK_SUCCESS;
4260 }
4261
4262 void radv_GetPhysicalDeviceExternalFenceProperties(
4263 VkPhysicalDevice physicalDevice,
4264 const VkPhysicalDeviceExternalFenceInfoKHR* pExternalFenceInfo,
4265 VkExternalFencePropertiesKHR* pExternalFenceProperties)
4266 {
4267 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4268
4269 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4270 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4271 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4272 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4273 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4274 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT_KHR |
4275 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4276 } else {
4277 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
4278 pExternalFenceProperties->compatibleHandleTypes = 0;
4279 pExternalFenceProperties->externalFenceFeatures = 0;
4280 }
4281 }
4282
4283 VkResult
4284 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
4285 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
4286 const VkAllocationCallbacks* pAllocator,
4287 VkDebugReportCallbackEXT* pCallback)
4288 {
4289 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4290 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
4291 pCreateInfo, pAllocator, &instance->alloc,
4292 pCallback);
4293 }
4294
4295 void
4296 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
4297 VkDebugReportCallbackEXT _callback,
4298 const VkAllocationCallbacks* pAllocator)
4299 {
4300 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4301 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
4302 _callback, pAllocator, &instance->alloc);
4303 }
4304
4305 void
4306 radv_DebugReportMessageEXT(VkInstance _instance,
4307 VkDebugReportFlagsEXT flags,
4308 VkDebugReportObjectTypeEXT objectType,
4309 uint64_t object,
4310 size_t location,
4311 int32_t messageCode,
4312 const char* pLayerPrefix,
4313 const char* pMessage)
4314 {
4315 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4316 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
4317 object, location, messageCode, pLayerPrefix, pMessage);
4318 }
4319
4320 void
4321 radv_GetDeviceGroupPeerMemoryFeatures(
4322 VkDevice device,
4323 uint32_t heapIndex,
4324 uint32_t localDeviceIndex,
4325 uint32_t remoteDeviceIndex,
4326 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
4327 {
4328 assert(localDeviceIndex == remoteDeviceIndex);
4329
4330 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
4331 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
4332 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
4333 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
4334 }