2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include <linux/audit.h>
32 #include <linux/bpf.h>
33 #include <linux/filter.h>
34 #include <linux/seccomp.h>
35 #include <linux/unistd.h>
36 #include <stdatomic.h>
41 #include <sys/prctl.h>
46 #include "radv_debug.h"
47 #include "radv_private.h"
48 #include "radv_shader.h"
50 #include "util/disk_cache.h"
54 #include "drm-uapi/amdgpu_drm.h"
55 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
56 #include "winsys/null/radv_null_winsys_public.h"
57 #include "ac_llvm_util.h"
58 #include "vk_format.h"
61 #include "util/build_id.h"
62 #include "util/debug.h"
63 #include "util/mesa-sha1.h"
64 #include "util/timespec.h"
65 #include "util/u_atomic.h"
66 #include "compiler/glsl_types.h"
67 #include "util/driconf.h"
69 static struct radv_timeline_point
*
70 radv_timeline_find_point_at_least_locked(struct radv_device
*device
,
71 struct radv_timeline
*timeline
,
74 static struct radv_timeline_point
*
75 radv_timeline_add_point_locked(struct radv_device
*device
,
76 struct radv_timeline
*timeline
,
80 radv_timeline_trigger_waiters_locked(struct radv_timeline
*timeline
,
81 struct list_head
*processing_list
);
84 void radv_destroy_semaphore_part(struct radv_device
*device
,
85 struct radv_semaphore_part
*part
);
88 radv_create_pthread_cond(pthread_cond_t
*cond
);
90 uint64_t radv_get_current_time(void)
93 clock_gettime(CLOCK_MONOTONIC
, &tv
);
94 return tv
.tv_nsec
+ tv
.tv_sec
*1000000000ull;
97 static uint64_t radv_get_absolute_timeout(uint64_t timeout
)
99 uint64_t current_time
= radv_get_current_time();
101 timeout
= MIN2(UINT64_MAX
- current_time
, timeout
);
103 return current_time
+ timeout
;
107 radv_device_get_cache_uuid(enum radeon_family family
, void *uuid
)
109 struct mesa_sha1 ctx
;
110 unsigned char sha1
[20];
111 unsigned ptr_size
= sizeof(void*);
113 memset(uuid
, 0, VK_UUID_SIZE
);
114 _mesa_sha1_init(&ctx
);
116 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid
, &ctx
) ||
117 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo
, &ctx
))
120 _mesa_sha1_update(&ctx
, &family
, sizeof(family
));
121 _mesa_sha1_update(&ctx
, &ptr_size
, sizeof(ptr_size
));
122 _mesa_sha1_final(&ctx
, sha1
);
124 memcpy(uuid
, sha1
, VK_UUID_SIZE
);
129 radv_get_driver_uuid(void *uuid
)
131 ac_compute_driver_uuid(uuid
, VK_UUID_SIZE
);
135 radv_get_device_uuid(struct radeon_info
*info
, void *uuid
)
137 ac_compute_device_uuid(info
, uuid
, VK_UUID_SIZE
);
141 radv_get_visible_vram_size(struct radv_physical_device
*device
)
143 return MIN2(device
->rad_info
.vram_size
, device
->rad_info
.vram_vis_size
);
147 radv_get_vram_size(struct radv_physical_device
*device
)
149 return device
->rad_info
.vram_size
- radv_get_visible_vram_size(device
);
153 radv_physical_device_init_mem_types(struct radv_physical_device
*device
)
155 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
156 uint64_t vram_size
= radv_get_vram_size(device
);
157 int vram_index
= -1, visible_vram_index
= -1, gart_index
= -1;
158 device
->memory_properties
.memoryHeapCount
= 0;
160 vram_index
= device
->memory_properties
.memoryHeapCount
++;
161 device
->memory_properties
.memoryHeaps
[vram_index
] = (VkMemoryHeap
) {
163 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
167 if (device
->rad_info
.gart_size
> 0) {
168 gart_index
= device
->memory_properties
.memoryHeapCount
++;
169 device
->memory_properties
.memoryHeaps
[gart_index
] = (VkMemoryHeap
) {
170 .size
= device
->rad_info
.gart_size
,
175 if (visible_vram_size
) {
176 visible_vram_index
= device
->memory_properties
.memoryHeapCount
++;
177 device
->memory_properties
.memoryHeaps
[visible_vram_index
] = (VkMemoryHeap
) {
178 .size
= visible_vram_size
,
179 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
183 unsigned type_count
= 0;
185 if (vram_index
>= 0 || visible_vram_index
>= 0) {
186 device
->memory_domains
[type_count
] = RADEON_DOMAIN_VRAM
;
187 device
->memory_flags
[type_count
] = RADEON_FLAG_NO_CPU_ACCESS
;
188 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
189 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
,
190 .heapIndex
= vram_index
>= 0 ? vram_index
: visible_vram_index
,
194 if (gart_index
>= 0) {
195 device
->memory_domains
[type_count
] = RADEON_DOMAIN_GTT
;
196 device
->memory_flags
[type_count
] = RADEON_FLAG_GTT_WC
| RADEON_FLAG_CPU_ACCESS
;
197 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
198 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
199 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
200 .heapIndex
= gart_index
,
203 if (visible_vram_index
>= 0) {
204 device
->memory_domains
[type_count
] = RADEON_DOMAIN_VRAM
;
205 device
->memory_flags
[type_count
] = RADEON_FLAG_CPU_ACCESS
;
206 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
207 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
208 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
209 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
210 .heapIndex
= visible_vram_index
,
214 if (gart_index
>= 0) {
215 device
->memory_domains
[type_count
] = RADEON_DOMAIN_GTT
;
216 device
->memory_flags
[type_count
] = RADEON_FLAG_CPU_ACCESS
;
217 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
218 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
219 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
220 VK_MEMORY_PROPERTY_HOST_CACHED_BIT
,
221 .heapIndex
= gart_index
,
224 device
->memory_properties
.memoryTypeCount
= type_count
;
226 if (device
->rad_info
.has_l2_uncached
) {
227 for (int i
= 0; i
< device
->memory_properties
.memoryTypeCount
; i
++) {
228 VkMemoryType mem_type
= device
->memory_properties
.memoryTypes
[i
];
230 if ((mem_type
.propertyFlags
& (VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
231 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
)) ||
232 mem_type
.propertyFlags
== VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
) {
234 VkMemoryPropertyFlags property_flags
= mem_type
.propertyFlags
|
235 VK_MEMORY_PROPERTY_DEVICE_COHERENT_BIT_AMD
|
236 VK_MEMORY_PROPERTY_DEVICE_UNCACHED_BIT_AMD
;
238 device
->memory_domains
[type_count
] = device
->memory_domains
[i
];
239 device
->memory_flags
[type_count
] = device
->memory_flags
[i
] | RADEON_FLAG_VA_UNCACHED
;
240 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
241 .propertyFlags
= property_flags
,
242 .heapIndex
= mem_type
.heapIndex
,
246 device
->memory_properties
.memoryTypeCount
= type_count
;
251 radv_get_compiler_string(struct radv_physical_device
*pdevice
)
253 if (!pdevice
->use_llvm
) {
254 /* Some games like SotTR apply shader workarounds if the LLVM
255 * version is too old or if the LLVM version string is
256 * missing. This gives 2-5% performance with SotTR and ACO.
258 if (driQueryOptionb(&pdevice
->instance
->dri_options
,
259 "radv_report_llvm9_version_string")) {
260 return "ACO/LLVM 9.0.1";
266 return "LLVM " MESA_LLVM_VERSION_STRING
;
270 radv_physical_device_try_create(struct radv_instance
*instance
,
271 drmDevicePtr drm_device
,
272 struct radv_physical_device
**device_out
)
279 const char *path
= drm_device
->nodes
[DRM_NODE_RENDER
];
280 drmVersionPtr version
;
282 fd
= open(path
, O_RDWR
| O_CLOEXEC
);
284 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
285 radv_logi("Could not open device '%s'", path
);
287 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
290 version
= drmGetVersion(fd
);
294 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
295 radv_logi("Could not get the kernel driver version for device '%s'", path
);
297 return vk_errorf(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
,
298 "failed to get version %s: %m", path
);
301 if (strcmp(version
->name
, "amdgpu")) {
302 drmFreeVersion(version
);
305 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
306 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path
);
308 return VK_ERROR_INCOMPATIBLE_DRIVER
;
310 drmFreeVersion(version
);
312 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
313 radv_logi("Found compatible device '%s'.", path
);
316 struct radv_physical_device
*device
=
317 vk_zalloc2(&instance
->alloc
, NULL
, sizeof(*device
), 8,
318 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
320 result
= vk_error(instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
324 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
325 device
->instance
= instance
;
328 device
->ws
= radv_amdgpu_winsys_create(fd
, instance
->debug_flags
,
329 instance
->perftest_flags
);
331 device
->ws
= radv_null_winsys_create();
335 result
= vk_errorf(instance
, VK_ERROR_INITIALIZATION_FAILED
,
336 "failed to initialize winsys");
340 if (drm_device
&& instance
->enabled_extensions
.KHR_display
) {
341 master_fd
= open(drm_device
->nodes
[DRM_NODE_PRIMARY
], O_RDWR
| O_CLOEXEC
);
342 if (master_fd
>= 0) {
343 uint32_t accel_working
= 0;
344 struct drm_amdgpu_info request
= {
345 .return_pointer
= (uintptr_t)&accel_working
,
346 .return_size
= sizeof(accel_working
),
347 .query
= AMDGPU_INFO_ACCEL_WORKING
350 if (drmCommandWrite(master_fd
, DRM_AMDGPU_INFO
, &request
, sizeof (struct drm_amdgpu_info
)) < 0 || !accel_working
) {
357 device
->master_fd
= master_fd
;
358 device
->local_fd
= fd
;
359 device
->ws
->query_info(device
->ws
, &device
->rad_info
);
361 device
->use_llvm
= instance
->debug_flags
& RADV_DEBUG_LLVM
;
363 snprintf(device
->name
, sizeof(device
->name
),
365 device
->rad_info
.name
, radv_get_compiler_string(device
));
367 if (radv_device_get_cache_uuid(device
->rad_info
.family
, device
->cache_uuid
)) {
368 result
= vk_errorf(instance
, VK_ERROR_INITIALIZATION_FAILED
,
369 "cannot generate UUID");
373 /* These flags affect shader compilation. */
374 uint64_t shader_env_flags
= (device
->use_llvm
? 0 : 0x2);
376 /* The gpu id is already embedded in the uuid so we just pass "radv"
377 * when creating the cache.
379 char buf
[VK_UUID_SIZE
* 2 + 1];
380 disk_cache_format_hex_id(buf
, device
->cache_uuid
, VK_UUID_SIZE
* 2);
381 device
->disk_cache
= disk_cache_create(device
->name
, buf
, shader_env_flags
);
383 if (device
->rad_info
.chip_class
< GFX8
|| !device
->use_llvm
)
384 fprintf(stderr
, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
386 radv_get_driver_uuid(&device
->driver_uuid
);
387 radv_get_device_uuid(&device
->rad_info
, &device
->device_uuid
);
389 device
->out_of_order_rast_allowed
= device
->rad_info
.has_out_of_order_rast
&&
390 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_OUT_OF_ORDER
);
392 device
->dcc_msaa_allowed
=
393 (device
->instance
->perftest_flags
& RADV_PERFTEST_DCC_MSAA
);
395 device
->use_ngg
= device
->rad_info
.chip_class
>= GFX10
&&
396 device
->rad_info
.family
!= CHIP_NAVI14
&&
397 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_NGG
);
399 /* TODO: Implement NGG GS with ACO. */
400 device
->use_ngg_gs
= device
->use_ngg
&& device
->use_llvm
;
401 device
->use_ngg_streamout
= false;
403 /* Determine the number of threads per wave for all stages. */
404 device
->cs_wave_size
= 64;
405 device
->ps_wave_size
= 64;
406 device
->ge_wave_size
= 64;
408 if (device
->rad_info
.chip_class
>= GFX10
) {
409 if (device
->instance
->perftest_flags
& RADV_PERFTEST_CS_WAVE_32
)
410 device
->cs_wave_size
= 32;
412 /* For pixel shaders, wave64 is recommanded. */
413 if (device
->instance
->perftest_flags
& RADV_PERFTEST_PS_WAVE_32
)
414 device
->ps_wave_size
= 32;
416 if (device
->instance
->perftest_flags
& RADV_PERFTEST_GE_WAVE_32
)
417 device
->ge_wave_size
= 32;
420 radv_physical_device_init_mem_types(device
);
422 radv_physical_device_get_supported_extensions(device
,
423 &device
->supported_extensions
);
426 device
->bus_info
= *drm_device
->businfo
.pci
;
428 if ((device
->instance
->debug_flags
& RADV_DEBUG_INFO
))
429 ac_print_gpu_info(&device
->rad_info
);
431 /* The WSI is structured as a layer on top of the driver, so this has
432 * to be the last part of initialization (at least until we get other
435 result
= radv_init_wsi(device
);
436 if (result
!= VK_SUCCESS
) {
437 vk_error(instance
, result
);
438 goto fail_disk_cache
;
441 *device_out
= device
;
446 disk_cache_destroy(device
->disk_cache
);
448 device
->ws
->destroy(device
->ws
);
450 vk_free(&instance
->alloc
, device
);
460 radv_physical_device_destroy(struct radv_physical_device
*device
)
462 radv_finish_wsi(device
);
463 device
->ws
->destroy(device
->ws
);
464 disk_cache_destroy(device
->disk_cache
);
465 close(device
->local_fd
);
466 if (device
->master_fd
!= -1)
467 close(device
->master_fd
);
468 vk_free(&device
->instance
->alloc
, device
);
472 default_alloc_func(void *pUserData
, size_t size
, size_t align
,
473 VkSystemAllocationScope allocationScope
)
479 default_realloc_func(void *pUserData
, void *pOriginal
, size_t size
,
480 size_t align
, VkSystemAllocationScope allocationScope
)
482 return realloc(pOriginal
, size
);
486 default_free_func(void *pUserData
, void *pMemory
)
491 static const VkAllocationCallbacks default_alloc
= {
493 .pfnAllocation
= default_alloc_func
,
494 .pfnReallocation
= default_realloc_func
,
495 .pfnFree
= default_free_func
,
498 static const struct debug_control radv_debug_options
[] = {
499 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS
},
500 {"nodcc", RADV_DEBUG_NO_DCC
},
501 {"shaders", RADV_DEBUG_DUMP_SHADERS
},
502 {"nocache", RADV_DEBUG_NO_CACHE
},
503 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS
},
504 {"nohiz", RADV_DEBUG_NO_HIZ
},
505 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE
},
506 {"allbos", RADV_DEBUG_ALL_BOS
},
507 {"noibs", RADV_DEBUG_NO_IBS
},
508 {"spirv", RADV_DEBUG_DUMP_SPIRV
},
509 {"vmfaults", RADV_DEBUG_VM_FAULTS
},
510 {"zerovram", RADV_DEBUG_ZERO_VRAM
},
511 {"syncshaders", RADV_DEBUG_SYNC_SHADERS
},
512 {"preoptir", RADV_DEBUG_PREOPTIR
},
513 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS
},
514 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER
},
515 {"info", RADV_DEBUG_INFO
},
516 {"errors", RADV_DEBUG_ERRORS
},
517 {"startup", RADV_DEBUG_STARTUP
},
518 {"checkir", RADV_DEBUG_CHECKIR
},
519 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM
},
520 {"nobinning", RADV_DEBUG_NOBINNING
},
521 {"nongg", RADV_DEBUG_NO_NGG
},
522 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS
},
523 {"metashaders", RADV_DEBUG_DUMP_META_SHADERS
},
524 {"nomemorycache", RADV_DEBUG_NO_MEMORY_CACHE
},
525 {"llvm", RADV_DEBUG_LLVM
},
526 {"forcecompress", RADV_DEBUG_FORCE_COMPRESS
},
531 radv_get_debug_option_name(int id
)
533 assert(id
< ARRAY_SIZE(radv_debug_options
) - 1);
534 return radv_debug_options
[id
].string
;
537 static const struct debug_control radv_perftest_options
[] = {
538 {"localbos", RADV_PERFTEST_LOCAL_BOS
},
539 {"dccmsaa", RADV_PERFTEST_DCC_MSAA
},
540 {"bolist", RADV_PERFTEST_BO_LIST
},
541 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK
},
542 {"cswave32", RADV_PERFTEST_CS_WAVE_32
},
543 {"pswave32", RADV_PERFTEST_PS_WAVE_32
},
544 {"gewave32", RADV_PERFTEST_GE_WAVE_32
},
545 {"dfsm", RADV_PERFTEST_DFSM
},
550 radv_get_perftest_option_name(int id
)
552 assert(id
< ARRAY_SIZE(radv_perftest_options
) - 1);
553 return radv_perftest_options
[id
].string
;
557 radv_handle_per_app_options(struct radv_instance
*instance
,
558 const VkApplicationInfo
*info
)
560 const char *name
= info
? info
->pApplicationName
: NULL
;
561 const char *engine_name
= info
? info
->pEngineName
: NULL
;
564 if (!strcmp(name
, "DOOM_VFR")) {
565 /* Work around a Doom VFR game bug */
566 instance
->debug_flags
|= RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
567 } else if (!strcmp(name
, "Fledge")) {
569 * Zero VRAM for "The Surge 2"
571 * This avoid a hang when when rendering any level. Likely
572 * uninitialized data in an indirect draw.
574 instance
->debug_flags
|= RADV_DEBUG_ZERO_VRAM
;
575 } else if (!strcmp(name
, "No Man's Sky")) {
576 /* Work around a NMS game bug */
577 instance
->debug_flags
|= RADV_DEBUG_DISCARD_TO_DEMOTE
;
578 } else if (!strcmp(name
, "DOOMEternal")) {
579 /* Zero VRAM for Doom Eternal to fix rendering issues. */
580 instance
->debug_flags
|= RADV_DEBUG_ZERO_VRAM
;
581 } else if (!strcmp(name
, "Red Dead Redemption 2")) {
582 /* Work around a RDR2 game bug */
583 instance
->debug_flags
|= RADV_DEBUG_DISCARD_TO_DEMOTE
;
588 if (!strcmp(engine_name
, "vkd3d")) {
589 /* Zero VRAM for all VKD3D (DX12->VK) games to fix
592 instance
->debug_flags
|= RADV_DEBUG_ZERO_VRAM
;
593 } else if (!strcmp(engine_name
, "Quantic Dream Engine")) {
594 /* Fix various artifacts in Detroit: Become Human */
595 instance
->debug_flags
|= RADV_DEBUG_ZERO_VRAM
|
596 RADV_DEBUG_DISCARD_TO_DEMOTE
;
600 instance
->enable_mrt_output_nan_fixup
=
601 driQueryOptionb(&instance
->dri_options
,
602 "radv_enable_mrt_output_nan_fixup");
604 if (driQueryOptionb(&instance
->dri_options
, "radv_no_dynamic_bounds"))
605 instance
->debug_flags
|= RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
608 static const char radv_dri_options_xml
[] =
610 DRI_CONF_SECTION_PERFORMANCE
611 DRI_CONF_ADAPTIVE_SYNC("true")
612 DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0)
613 DRI_CONF_VK_X11_STRICT_IMAGE_COUNT("false")
614 DRI_CONF_VK_X11_ENSURE_MIN_IMAGE_COUNT("false")
615 DRI_CONF_RADV_REPORT_LLVM9_VERSION_STRING("false")
616 DRI_CONF_RADV_ENABLE_MRT_OUTPUT_NAN_FIXUP("false")
617 DRI_CONF_RADV_NO_DYNAMIC_BOUNDS("false")
620 DRI_CONF_SECTION_DEBUG
621 DRI_CONF_VK_WSI_FORCE_BGRA8_UNORM_FIRST("false")
625 static void radv_init_dri_options(struct radv_instance
*instance
)
627 driParseOptionInfo(&instance
->available_dri_options
, radv_dri_options_xml
);
628 driParseConfigFiles(&instance
->dri_options
,
629 &instance
->available_dri_options
,
631 instance
->applicationName
,
632 instance
->applicationVersion
,
633 instance
->engineName
,
634 instance
->engineVersion
);
637 VkResult
radv_CreateInstance(
638 const VkInstanceCreateInfo
* pCreateInfo
,
639 const VkAllocationCallbacks
* pAllocator
,
640 VkInstance
* pInstance
)
642 struct radv_instance
*instance
;
645 instance
= vk_zalloc2(&default_alloc
, pAllocator
, sizeof(*instance
), 8,
646 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
648 return vk_error(NULL
, VK_ERROR_OUT_OF_HOST_MEMORY
);
650 vk_object_base_init(NULL
, &instance
->base
, VK_OBJECT_TYPE_INSTANCE
);
653 instance
->alloc
= *pAllocator
;
655 instance
->alloc
= default_alloc
;
657 if (pCreateInfo
->pApplicationInfo
) {
658 const VkApplicationInfo
*app
= pCreateInfo
->pApplicationInfo
;
660 instance
->applicationName
=
661 vk_strdup(&instance
->alloc
, app
->pApplicationName
,
662 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
663 instance
->applicationVersion
= app
->applicationVersion
;
665 instance
->engineName
=
666 vk_strdup(&instance
->alloc
, app
->pEngineName
,
667 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
668 instance
->engineVersion
= app
->engineVersion
;
669 instance
->apiVersion
= app
->apiVersion
;
672 if (instance
->apiVersion
== 0)
673 instance
->apiVersion
= VK_API_VERSION_1_0
;
675 instance
->debug_flags
= parse_debug_string(getenv("RADV_DEBUG"),
678 const char *radv_perftest_str
= getenv("RADV_PERFTEST");
679 instance
->perftest_flags
= parse_debug_string(radv_perftest_str
,
680 radv_perftest_options
);
682 if (radv_perftest_str
) {
683 /* Output warnings for famous RADV_PERFTEST options that no
684 * longer exist or are deprecated.
686 if (strstr(radv_perftest_str
, "aco")) {
687 fprintf(stderr
, "*******************************************************************************\n");
688 fprintf(stderr
, "* WARNING: Unknown option RADV_PERFTEST='aco'. ACO is enabled by default now. *\n");
689 fprintf(stderr
, "*******************************************************************************\n");
691 if (strstr(radv_perftest_str
, "llvm")) {
692 fprintf(stderr
, "*********************************************************************************\n");
693 fprintf(stderr
, "* WARNING: Unknown option 'RADV_PERFTEST=llvm'. Did you mean 'RADV_DEBUG=llvm'? *\n");
694 fprintf(stderr
, "*********************************************************************************\n");
699 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
700 radv_logi("Created an instance");
702 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
704 for (idx
= 0; idx
< RADV_INSTANCE_EXTENSION_COUNT
; idx
++) {
705 if (!strcmp(pCreateInfo
->ppEnabledExtensionNames
[i
],
706 radv_instance_extensions
[idx
].extensionName
))
710 if (idx
>= RADV_INSTANCE_EXTENSION_COUNT
||
711 !radv_instance_extensions_supported
.extensions
[idx
]) {
712 vk_object_base_finish(&instance
->base
);
713 vk_free2(&default_alloc
, pAllocator
, instance
);
714 return vk_error(instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
717 instance
->enabled_extensions
.extensions
[idx
] = true;
720 bool unchecked
= instance
->debug_flags
& RADV_DEBUG_ALL_ENTRYPOINTS
;
722 for (unsigned i
= 0; i
< ARRAY_SIZE(instance
->dispatch
.entrypoints
); i
++) {
723 /* Vulkan requires that entrypoints for extensions which have
724 * not been enabled must not be advertised.
727 !radv_instance_entrypoint_is_enabled(i
, instance
->apiVersion
,
728 &instance
->enabled_extensions
)) {
729 instance
->dispatch
.entrypoints
[i
] = NULL
;
731 instance
->dispatch
.entrypoints
[i
] =
732 radv_instance_dispatch_table
.entrypoints
[i
];
736 for (unsigned i
= 0; i
< ARRAY_SIZE(instance
->physical_device_dispatch
.entrypoints
); i
++) {
737 /* Vulkan requires that entrypoints for extensions which have
738 * not been enabled must not be advertised.
741 !radv_physical_device_entrypoint_is_enabled(i
, instance
->apiVersion
,
742 &instance
->enabled_extensions
)) {
743 instance
->physical_device_dispatch
.entrypoints
[i
] = NULL
;
745 instance
->physical_device_dispatch
.entrypoints
[i
] =
746 radv_physical_device_dispatch_table
.entrypoints
[i
];
750 for (unsigned i
= 0; i
< ARRAY_SIZE(instance
->device_dispatch
.entrypoints
); i
++) {
751 /* Vulkan requires that entrypoints for extensions which have
752 * not been enabled must not be advertised.
755 !radv_device_entrypoint_is_enabled(i
, instance
->apiVersion
,
756 &instance
->enabled_extensions
, NULL
)) {
757 instance
->device_dispatch
.entrypoints
[i
] = NULL
;
759 instance
->device_dispatch
.entrypoints
[i
] =
760 radv_device_dispatch_table
.entrypoints
[i
];
764 instance
->physical_devices_enumerated
= false;
765 list_inithead(&instance
->physical_devices
);
767 result
= vk_debug_report_instance_init(&instance
->debug_report_callbacks
);
768 if (result
!= VK_SUCCESS
) {
769 vk_object_base_finish(&instance
->base
);
770 vk_free2(&default_alloc
, pAllocator
, instance
);
771 return vk_error(instance
, result
);
774 glsl_type_singleton_init_or_ref();
776 VG(VALGRIND_CREATE_MEMPOOL(instance
, 0, false));
778 radv_init_dri_options(instance
);
779 radv_handle_per_app_options(instance
, pCreateInfo
->pApplicationInfo
);
781 *pInstance
= radv_instance_to_handle(instance
);
786 void radv_DestroyInstance(
787 VkInstance _instance
,
788 const VkAllocationCallbacks
* pAllocator
)
790 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
795 list_for_each_entry_safe(struct radv_physical_device
, pdevice
,
796 &instance
->physical_devices
, link
) {
797 radv_physical_device_destroy(pdevice
);
800 vk_free(&instance
->alloc
, instance
->engineName
);
801 vk_free(&instance
->alloc
, instance
->applicationName
);
803 VG(VALGRIND_DESTROY_MEMPOOL(instance
));
805 glsl_type_singleton_decref();
807 driDestroyOptionCache(&instance
->dri_options
);
808 driDestroyOptionInfo(&instance
->available_dri_options
);
810 vk_debug_report_instance_destroy(&instance
->debug_report_callbacks
);
812 vk_object_base_finish(&instance
->base
);
813 vk_free(&instance
->alloc
, instance
);
817 radv_enumerate_physical_devices(struct radv_instance
*instance
)
819 if (instance
->physical_devices_enumerated
)
822 instance
->physical_devices_enumerated
= true;
824 /* TODO: Check for more devices ? */
825 drmDevicePtr devices
[8];
826 VkResult result
= VK_SUCCESS
;
829 if (getenv("RADV_FORCE_FAMILY")) {
830 /* When RADV_FORCE_FAMILY is set, the driver creates a nul
831 * device that allows to test the compiler without having an
834 struct radv_physical_device
*pdevice
;
836 result
= radv_physical_device_try_create(instance
, NULL
, &pdevice
);
837 if (result
!= VK_SUCCESS
)
840 list_addtail(&pdevice
->link
, &instance
->physical_devices
);
844 max_devices
= drmGetDevices2(0, devices
, ARRAY_SIZE(devices
));
846 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
847 radv_logi("Found %d drm nodes", max_devices
);
850 return vk_error(instance
, VK_SUCCESS
);
852 for (unsigned i
= 0; i
< (unsigned)max_devices
; i
++) {
853 if (devices
[i
]->available_nodes
& 1 << DRM_NODE_RENDER
&&
854 devices
[i
]->bustype
== DRM_BUS_PCI
&&
855 devices
[i
]->deviceinfo
.pci
->vendor_id
== ATI_VENDOR_ID
) {
857 struct radv_physical_device
*pdevice
;
858 result
= radv_physical_device_try_create(instance
, devices
[i
],
860 /* Incompatible DRM device, skip. */
861 if (result
== VK_ERROR_INCOMPATIBLE_DRIVER
) {
866 /* Error creating the physical device, report the error. */
867 if (result
!= VK_SUCCESS
)
870 list_addtail(&pdevice
->link
, &instance
->physical_devices
);
873 drmFreeDevices(devices
, max_devices
);
875 /* If we successfully enumerated any devices, call it success */
879 VkResult
radv_EnumeratePhysicalDevices(
880 VkInstance _instance
,
881 uint32_t* pPhysicalDeviceCount
,
882 VkPhysicalDevice
* pPhysicalDevices
)
884 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
885 VK_OUTARRAY_MAKE(out
, pPhysicalDevices
, pPhysicalDeviceCount
);
887 VkResult result
= radv_enumerate_physical_devices(instance
);
888 if (result
!= VK_SUCCESS
)
891 list_for_each_entry(struct radv_physical_device
, pdevice
,
892 &instance
->physical_devices
, link
) {
893 vk_outarray_append(&out
, i
) {
894 *i
= radv_physical_device_to_handle(pdevice
);
898 return vk_outarray_status(&out
);
901 VkResult
radv_EnumeratePhysicalDeviceGroups(
902 VkInstance _instance
,
903 uint32_t* pPhysicalDeviceGroupCount
,
904 VkPhysicalDeviceGroupProperties
* pPhysicalDeviceGroupProperties
)
906 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
907 VK_OUTARRAY_MAKE(out
, pPhysicalDeviceGroupProperties
,
908 pPhysicalDeviceGroupCount
);
910 VkResult result
= radv_enumerate_physical_devices(instance
);
911 if (result
!= VK_SUCCESS
)
914 list_for_each_entry(struct radv_physical_device
, pdevice
,
915 &instance
->physical_devices
, link
) {
916 vk_outarray_append(&out
, p
) {
917 p
->physicalDeviceCount
= 1;
918 memset(p
->physicalDevices
, 0, sizeof(p
->physicalDevices
));
919 p
->physicalDevices
[0] = radv_physical_device_to_handle(pdevice
);
920 p
->subsetAllocation
= false;
924 return vk_outarray_status(&out
);
927 void radv_GetPhysicalDeviceFeatures(
928 VkPhysicalDevice physicalDevice
,
929 VkPhysicalDeviceFeatures
* pFeatures
)
931 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
932 memset(pFeatures
, 0, sizeof(*pFeatures
));
934 *pFeatures
= (VkPhysicalDeviceFeatures
) {
935 .robustBufferAccess
= true,
936 .fullDrawIndexUint32
= true,
937 .imageCubeArray
= true,
938 .independentBlend
= true,
939 .geometryShader
= true,
940 .tessellationShader
= true,
941 .sampleRateShading
= true,
942 .dualSrcBlend
= true,
944 .multiDrawIndirect
= true,
945 .drawIndirectFirstInstance
= true,
947 .depthBiasClamp
= true,
948 .fillModeNonSolid
= true,
953 .multiViewport
= true,
954 .samplerAnisotropy
= true,
955 .textureCompressionETC2
= radv_device_supports_etc(pdevice
),
956 .textureCompressionASTC_LDR
= false,
957 .textureCompressionBC
= true,
958 .occlusionQueryPrecise
= true,
959 .pipelineStatisticsQuery
= true,
960 .vertexPipelineStoresAndAtomics
= true,
961 .fragmentStoresAndAtomics
= true,
962 .shaderTessellationAndGeometryPointSize
= true,
963 .shaderImageGatherExtended
= true,
964 .shaderStorageImageExtendedFormats
= true,
965 .shaderStorageImageMultisample
= true,
966 .shaderUniformBufferArrayDynamicIndexing
= true,
967 .shaderSampledImageArrayDynamicIndexing
= true,
968 .shaderStorageBufferArrayDynamicIndexing
= true,
969 .shaderStorageImageArrayDynamicIndexing
= true,
970 .shaderStorageImageReadWithoutFormat
= true,
971 .shaderStorageImageWriteWithoutFormat
= true,
972 .shaderClipDistance
= true,
973 .shaderCullDistance
= true,
974 .shaderFloat64
= true,
977 .sparseBinding
= true,
978 .variableMultisampleRate
= true,
979 .shaderResourceMinLod
= true,
980 .inheritedQueries
= true,
985 radv_get_physical_device_features_1_1(struct radv_physical_device
*pdevice
,
986 VkPhysicalDeviceVulkan11Features
*f
)
988 assert(f
->sType
== VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES
);
990 f
->storageBuffer16BitAccess
= true;
991 f
->uniformAndStorageBuffer16BitAccess
= true;
992 f
->storagePushConstant16
= true;
993 f
->storageInputOutput16
= pdevice
->rad_info
.has_packed_math_16bit
&& (LLVM_VERSION_MAJOR
>= 9 || !pdevice
->use_llvm
);
995 f
->multiviewGeometryShader
= true;
996 f
->multiviewTessellationShader
= true;
997 f
->variablePointersStorageBuffer
= true;
998 f
->variablePointers
= true;
999 f
->protectedMemory
= false;
1000 f
->samplerYcbcrConversion
= true;
1001 f
->shaderDrawParameters
= true;
1005 radv_get_physical_device_features_1_2(struct radv_physical_device
*pdevice
,
1006 VkPhysicalDeviceVulkan12Features
*f
)
1008 assert(f
->sType
== VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES
);
1010 f
->samplerMirrorClampToEdge
= true;
1011 f
->drawIndirectCount
= true;
1012 f
->storageBuffer8BitAccess
= true;
1013 f
->uniformAndStorageBuffer8BitAccess
= true;
1014 f
->storagePushConstant8
= true;
1015 f
->shaderBufferInt64Atomics
= LLVM_VERSION_MAJOR
>= 9 || !pdevice
->use_llvm
;
1016 f
->shaderSharedInt64Atomics
= LLVM_VERSION_MAJOR
>= 9 || !pdevice
->use_llvm
;
1017 f
->shaderFloat16
= pdevice
->rad_info
.has_packed_math_16bit
;
1018 f
->shaderInt8
= true;
1020 f
->descriptorIndexing
= true;
1021 f
->shaderInputAttachmentArrayDynamicIndexing
= true;
1022 f
->shaderUniformTexelBufferArrayDynamicIndexing
= true;
1023 f
->shaderStorageTexelBufferArrayDynamicIndexing
= true;
1024 f
->shaderUniformBufferArrayNonUniformIndexing
= true;
1025 f
->shaderSampledImageArrayNonUniformIndexing
= true;
1026 f
->shaderStorageBufferArrayNonUniformIndexing
= true;
1027 f
->shaderStorageImageArrayNonUniformIndexing
= true;
1028 f
->shaderInputAttachmentArrayNonUniformIndexing
= true;
1029 f
->shaderUniformTexelBufferArrayNonUniformIndexing
= true;
1030 f
->shaderStorageTexelBufferArrayNonUniformIndexing
= true;
1031 f
->descriptorBindingUniformBufferUpdateAfterBind
= true;
1032 f
->descriptorBindingSampledImageUpdateAfterBind
= true;
1033 f
->descriptorBindingStorageImageUpdateAfterBind
= true;
1034 f
->descriptorBindingStorageBufferUpdateAfterBind
= true;
1035 f
->descriptorBindingUniformTexelBufferUpdateAfterBind
= true;
1036 f
->descriptorBindingStorageTexelBufferUpdateAfterBind
= true;
1037 f
->descriptorBindingUpdateUnusedWhilePending
= true;
1038 f
->descriptorBindingPartiallyBound
= true;
1039 f
->descriptorBindingVariableDescriptorCount
= true;
1040 f
->runtimeDescriptorArray
= true;
1042 f
->samplerFilterMinmax
= true;
1043 f
->scalarBlockLayout
= pdevice
->rad_info
.chip_class
>= GFX7
;
1044 f
->imagelessFramebuffer
= true;
1045 f
->uniformBufferStandardLayout
= true;
1046 f
->shaderSubgroupExtendedTypes
= true;
1047 f
->separateDepthStencilLayouts
= true;
1048 f
->hostQueryReset
= true;
1049 f
->timelineSemaphore
= pdevice
->rad_info
.has_syncobj_wait_for_submit
;
1050 f
->bufferDeviceAddress
= true;
1051 f
->bufferDeviceAddressCaptureReplay
= false;
1052 f
->bufferDeviceAddressMultiDevice
= false;
1053 f
->vulkanMemoryModel
= true;
1054 f
->vulkanMemoryModelDeviceScope
= true;
1055 f
->vulkanMemoryModelAvailabilityVisibilityChains
= false;
1056 f
->shaderOutputViewportIndex
= true;
1057 f
->shaderOutputLayer
= true;
1058 f
->subgroupBroadcastDynamicId
= true;
1061 void radv_GetPhysicalDeviceFeatures2(
1062 VkPhysicalDevice physicalDevice
,
1063 VkPhysicalDeviceFeatures2
*pFeatures
)
1065 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1066 radv_GetPhysicalDeviceFeatures(physicalDevice
, &pFeatures
->features
);
1068 VkPhysicalDeviceVulkan11Features core_1_1
= {
1069 .sType
= VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES
,
1071 radv_get_physical_device_features_1_1(pdevice
, &core_1_1
);
1073 VkPhysicalDeviceVulkan12Features core_1_2
= {
1074 .sType
= VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES
,
1076 radv_get_physical_device_features_1_2(pdevice
, &core_1_2
);
1078 #define CORE_FEATURE(major, minor, feature) \
1079 features->feature = core_##major##_##minor.feature
1081 vk_foreach_struct(ext
, pFeatures
->pNext
) {
1082 switch (ext
->sType
) {
1083 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES
: {
1084 VkPhysicalDeviceVariablePointersFeatures
*features
= (void *)ext
;
1085 CORE_FEATURE(1, 1, variablePointersStorageBuffer
);
1086 CORE_FEATURE(1, 1, variablePointers
);
1089 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES
: {
1090 VkPhysicalDeviceMultiviewFeatures
*features
= (VkPhysicalDeviceMultiviewFeatures
*)ext
;
1091 CORE_FEATURE(1, 1, multiview
);
1092 CORE_FEATURE(1, 1, multiviewGeometryShader
);
1093 CORE_FEATURE(1, 1, multiviewTessellationShader
);
1096 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES
: {
1097 VkPhysicalDeviceShaderDrawParametersFeatures
*features
=
1098 (VkPhysicalDeviceShaderDrawParametersFeatures
*)ext
;
1099 CORE_FEATURE(1, 1, shaderDrawParameters
);
1102 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES
: {
1103 VkPhysicalDeviceProtectedMemoryFeatures
*features
=
1104 (VkPhysicalDeviceProtectedMemoryFeatures
*)ext
;
1105 CORE_FEATURE(1, 1, protectedMemory
);
1108 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES
: {
1109 VkPhysicalDevice16BitStorageFeatures
*features
=
1110 (VkPhysicalDevice16BitStorageFeatures
*)ext
;
1111 CORE_FEATURE(1, 1, storageBuffer16BitAccess
);
1112 CORE_FEATURE(1, 1, uniformAndStorageBuffer16BitAccess
);
1113 CORE_FEATURE(1, 1, storagePushConstant16
);
1114 CORE_FEATURE(1, 1, storageInputOutput16
);
1117 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES
: {
1118 VkPhysicalDeviceSamplerYcbcrConversionFeatures
*features
=
1119 (VkPhysicalDeviceSamplerYcbcrConversionFeatures
*)ext
;
1120 CORE_FEATURE(1, 1, samplerYcbcrConversion
);
1123 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES
: {
1124 VkPhysicalDeviceDescriptorIndexingFeatures
*features
=
1125 (VkPhysicalDeviceDescriptorIndexingFeatures
*)ext
;
1126 CORE_FEATURE(1, 2, shaderInputAttachmentArrayDynamicIndexing
);
1127 CORE_FEATURE(1, 2, shaderUniformTexelBufferArrayDynamicIndexing
);
1128 CORE_FEATURE(1, 2, shaderStorageTexelBufferArrayDynamicIndexing
);
1129 CORE_FEATURE(1, 2, shaderUniformBufferArrayNonUniformIndexing
);
1130 CORE_FEATURE(1, 2, shaderSampledImageArrayNonUniformIndexing
);
1131 CORE_FEATURE(1, 2, shaderStorageBufferArrayNonUniformIndexing
);
1132 CORE_FEATURE(1, 2, shaderStorageImageArrayNonUniformIndexing
);
1133 CORE_FEATURE(1, 2, shaderInputAttachmentArrayNonUniformIndexing
);
1134 CORE_FEATURE(1, 2, shaderUniformTexelBufferArrayNonUniformIndexing
);
1135 CORE_FEATURE(1, 2, shaderStorageTexelBufferArrayNonUniformIndexing
);
1136 CORE_FEATURE(1, 2, descriptorBindingUniformBufferUpdateAfterBind
);
1137 CORE_FEATURE(1, 2, descriptorBindingSampledImageUpdateAfterBind
);
1138 CORE_FEATURE(1, 2, descriptorBindingStorageImageUpdateAfterBind
);
1139 CORE_FEATURE(1, 2, descriptorBindingStorageBufferUpdateAfterBind
);
1140 CORE_FEATURE(1, 2, descriptorBindingUniformTexelBufferUpdateAfterBind
);
1141 CORE_FEATURE(1, 2, descriptorBindingStorageTexelBufferUpdateAfterBind
);
1142 CORE_FEATURE(1, 2, descriptorBindingUpdateUnusedWhilePending
);
1143 CORE_FEATURE(1, 2, descriptorBindingPartiallyBound
);
1144 CORE_FEATURE(1, 2, descriptorBindingVariableDescriptorCount
);
1145 CORE_FEATURE(1, 2, runtimeDescriptorArray
);
1148 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT
: {
1149 VkPhysicalDeviceConditionalRenderingFeaturesEXT
*features
=
1150 (VkPhysicalDeviceConditionalRenderingFeaturesEXT
*)ext
;
1151 features
->conditionalRendering
= true;
1152 features
->inheritedConditionalRendering
= false;
1155 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT
: {
1156 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*features
=
1157 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*)ext
;
1158 features
->vertexAttributeInstanceRateDivisor
= true;
1159 features
->vertexAttributeInstanceRateZeroDivisor
= true;
1162 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT
: {
1163 VkPhysicalDeviceTransformFeedbackFeaturesEXT
*features
=
1164 (VkPhysicalDeviceTransformFeedbackFeaturesEXT
*)ext
;
1165 features
->transformFeedback
= true;
1166 features
->geometryStreams
= !pdevice
->use_ngg_streamout
;
1169 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES
: {
1170 VkPhysicalDeviceScalarBlockLayoutFeatures
*features
=
1171 (VkPhysicalDeviceScalarBlockLayoutFeatures
*)ext
;
1172 CORE_FEATURE(1, 2, scalarBlockLayout
);
1175 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT
: {
1176 VkPhysicalDeviceMemoryPriorityFeaturesEXT
*features
=
1177 (VkPhysicalDeviceMemoryPriorityFeaturesEXT
*)ext
;
1178 features
->memoryPriority
= true;
1181 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT
: {
1182 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*features
=
1183 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*)ext
;
1184 features
->bufferDeviceAddress
= true;
1185 features
->bufferDeviceAddressCaptureReplay
= false;
1186 features
->bufferDeviceAddressMultiDevice
= false;
1189 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES
: {
1190 VkPhysicalDeviceBufferDeviceAddressFeatures
*features
=
1191 (VkPhysicalDeviceBufferDeviceAddressFeatures
*)ext
;
1192 CORE_FEATURE(1, 2, bufferDeviceAddress
);
1193 CORE_FEATURE(1, 2, bufferDeviceAddressCaptureReplay
);
1194 CORE_FEATURE(1, 2, bufferDeviceAddressMultiDevice
);
1197 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT
: {
1198 VkPhysicalDeviceDepthClipEnableFeaturesEXT
*features
=
1199 (VkPhysicalDeviceDepthClipEnableFeaturesEXT
*)ext
;
1200 features
->depthClipEnable
= true;
1203 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES
: {
1204 VkPhysicalDeviceHostQueryResetFeatures
*features
=
1205 (VkPhysicalDeviceHostQueryResetFeatures
*)ext
;
1206 CORE_FEATURE(1, 2, hostQueryReset
);
1209 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES
: {
1210 VkPhysicalDevice8BitStorageFeatures
*features
=
1211 (VkPhysicalDevice8BitStorageFeatures
*)ext
;
1212 CORE_FEATURE(1, 2, storageBuffer8BitAccess
);
1213 CORE_FEATURE(1, 2, uniformAndStorageBuffer8BitAccess
);
1214 CORE_FEATURE(1, 2, storagePushConstant8
);
1217 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_FLOAT16_INT8_FEATURES
: {
1218 VkPhysicalDeviceShaderFloat16Int8Features
*features
=
1219 (VkPhysicalDeviceShaderFloat16Int8Features
*)ext
;
1220 CORE_FEATURE(1, 2, shaderFloat16
);
1221 CORE_FEATURE(1, 2, shaderInt8
);
1224 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES
: {
1225 VkPhysicalDeviceShaderAtomicInt64Features
*features
=
1226 (VkPhysicalDeviceShaderAtomicInt64Features
*)ext
;
1227 CORE_FEATURE(1, 2, shaderBufferInt64Atomics
);
1228 CORE_FEATURE(1, 2, shaderSharedInt64Atomics
);
1231 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DEMOTE_TO_HELPER_INVOCATION_FEATURES_EXT
: {
1232 VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT
*features
=
1233 (VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT
*)ext
;
1234 features
->shaderDemoteToHelperInvocation
= LLVM_VERSION_MAJOR
>= 9 || !pdevice
->use_llvm
;
1237 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT
: {
1238 VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*features
=
1239 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*)ext
;
1241 features
->inlineUniformBlock
= true;
1242 features
->descriptorBindingInlineUniformBlockUpdateAfterBind
= true;
1245 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV
: {
1246 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*features
=
1247 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*)ext
;
1248 features
->computeDerivativeGroupQuads
= false;
1249 features
->computeDerivativeGroupLinear
= true;
1252 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT
: {
1253 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*features
=
1254 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*)ext
;
1255 features
->ycbcrImageArrays
= true;
1258 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES
: {
1259 VkPhysicalDeviceUniformBufferStandardLayoutFeatures
*features
=
1260 (VkPhysicalDeviceUniformBufferStandardLayoutFeatures
*)ext
;
1261 CORE_FEATURE(1, 2, uniformBufferStandardLayout
);
1264 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT
: {
1265 VkPhysicalDeviceIndexTypeUint8FeaturesEXT
*features
=
1266 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT
*)ext
;
1267 features
->indexTypeUint8
= pdevice
->rad_info
.chip_class
>= GFX8
;
1270 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES
: {
1271 VkPhysicalDeviceImagelessFramebufferFeatures
*features
=
1272 (VkPhysicalDeviceImagelessFramebufferFeatures
*)ext
;
1273 CORE_FEATURE(1, 2, imagelessFramebuffer
);
1276 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR
: {
1277 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR
*features
=
1278 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR
*)ext
;
1279 features
->pipelineExecutableInfo
= true;
1282 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CLOCK_FEATURES_KHR
: {
1283 VkPhysicalDeviceShaderClockFeaturesKHR
*features
=
1284 (VkPhysicalDeviceShaderClockFeaturesKHR
*)ext
;
1285 features
->shaderSubgroupClock
= true;
1286 features
->shaderDeviceClock
= pdevice
->rad_info
.chip_class
>= GFX8
;
1289 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_FEATURES_EXT
: {
1290 VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT
*features
=
1291 (VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT
*)ext
;
1292 features
->texelBufferAlignment
= true;
1295 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_FEATURES
: {
1296 VkPhysicalDeviceTimelineSemaphoreFeatures
*features
=
1297 (VkPhysicalDeviceTimelineSemaphoreFeatures
*) ext
;
1298 CORE_FEATURE(1, 2, timelineSemaphore
);
1301 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_FEATURES_EXT
: {
1302 VkPhysicalDeviceSubgroupSizeControlFeaturesEXT
*features
=
1303 (VkPhysicalDeviceSubgroupSizeControlFeaturesEXT
*)ext
;
1304 features
->subgroupSizeControl
= true;
1305 features
->computeFullSubgroups
= true;
1308 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COHERENT_MEMORY_FEATURES_AMD
: {
1309 VkPhysicalDeviceCoherentMemoryFeaturesAMD
*features
=
1310 (VkPhysicalDeviceCoherentMemoryFeaturesAMD
*)ext
;
1311 features
->deviceCoherentMemory
= pdevice
->rad_info
.has_l2_uncached
;
1314 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_SUBGROUP_EXTENDED_TYPES_FEATURES
: {
1315 VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures
*features
=
1316 (VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures
*)ext
;
1317 CORE_FEATURE(1, 2, shaderSubgroupExtendedTypes
);
1320 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SEPARATE_DEPTH_STENCIL_LAYOUTS_FEATURES_KHR
: {
1321 VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR
*features
=
1322 (VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR
*)ext
;
1323 CORE_FEATURE(1, 2, separateDepthStencilLayouts
);
1326 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES
: {
1327 radv_get_physical_device_features_1_1(pdevice
, (void *)ext
);
1330 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES
: {
1331 radv_get_physical_device_features_1_2(pdevice
, (void *)ext
);
1334 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_FEATURES_EXT
: {
1335 VkPhysicalDeviceLineRasterizationFeaturesEXT
*features
=
1336 (VkPhysicalDeviceLineRasterizationFeaturesEXT
*)ext
;
1337 features
->rectangularLines
= false;
1338 features
->bresenhamLines
= true;
1339 features
->smoothLines
= false;
1340 features
->stippledRectangularLines
= false;
1341 features
->stippledBresenhamLines
= true;
1342 features
->stippledSmoothLines
= false;
1345 case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD
: {
1346 VkDeviceMemoryOverallocationCreateInfoAMD
*features
=
1347 (VkDeviceMemoryOverallocationCreateInfoAMD
*)ext
;
1348 features
->overallocationBehavior
= true;
1351 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ROBUSTNESS_2_FEATURES_EXT
: {
1352 VkPhysicalDeviceRobustness2FeaturesEXT
*features
=
1353 (VkPhysicalDeviceRobustness2FeaturesEXT
*)ext
;
1354 features
->robustBufferAccess2
= true;
1355 features
->robustImageAccess2
= true;
1356 features
->nullDescriptor
= true;
1359 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_FEATURES_EXT
: {
1360 VkPhysicalDeviceCustomBorderColorFeaturesEXT
*features
=
1361 (VkPhysicalDeviceCustomBorderColorFeaturesEXT
*)ext
;
1362 features
->customBorderColors
= true;
1363 features
->customBorderColorWithoutFormat
= true;
1366 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PRIVATE_DATA_FEATURES_EXT
: {
1367 VkPhysicalDevicePrivateDataFeaturesEXT
*features
=
1368 (VkPhysicalDevicePrivateDataFeaturesEXT
*)ext
;
1369 features
->privateData
= true;
1372 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_CREATION_CACHE_CONTROL_FEATURES_EXT
: {
1373 VkPhysicalDevicePipelineCreationCacheControlFeaturesEXT
*features
=
1374 (VkPhysicalDevicePipelineCreationCacheControlFeaturesEXT
*)ext
;
1375 features
-> pipelineCreationCacheControl
= true;
1378 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_MEMORY_MODEL_FEATURES_KHR
: {
1379 VkPhysicalDeviceVulkanMemoryModelFeaturesKHR
*features
=
1380 (VkPhysicalDeviceVulkanMemoryModelFeaturesKHR
*)ext
;
1381 CORE_FEATURE(1, 2, vulkanMemoryModel
);
1382 CORE_FEATURE(1, 2, vulkanMemoryModelDeviceScope
);
1383 CORE_FEATURE(1, 2, vulkanMemoryModelAvailabilityVisibilityChains
);
1386 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTENDED_DYNAMIC_STATE_FEATURES_EXT
: {
1387 VkPhysicalDeviceExtendedDynamicStateFeaturesEXT
*features
=
1388 (VkPhysicalDeviceExtendedDynamicStateFeaturesEXT
*) ext
;
1389 features
->extendedDynamicState
= true;
1392 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGE_ROBUSTNESS_FEATURES_EXT
: {
1393 VkPhysicalDeviceImageRobustnessFeaturesEXT
*features
=
1394 (VkPhysicalDeviceImageRobustnessFeaturesEXT
*)ext
;
1395 features
->robustImageAccess
= true;
1398 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_FLOAT_FEATURES_EXT
: {
1399 VkPhysicalDeviceShaderAtomicFloatFeaturesEXT
*features
=
1400 (VkPhysicalDeviceShaderAtomicFloatFeaturesEXT
*)ext
;
1401 features
->shaderBufferFloat32Atomics
= true;
1402 features
->shaderBufferFloat32AtomicAdd
= false;
1403 features
->shaderBufferFloat64Atomics
= true;
1404 features
->shaderBufferFloat64AtomicAdd
= false;
1405 features
->shaderSharedFloat32Atomics
= true;
1406 features
->shaderSharedFloat32AtomicAdd
= pdevice
->rad_info
.chip_class
>= GFX8
&&
1407 (!pdevice
->use_llvm
|| LLVM_VERSION_MAJOR
>= 10);
1408 features
->shaderSharedFloat64Atomics
= true;
1409 features
->shaderSharedFloat64AtomicAdd
= false;
1410 features
->shaderImageFloat32Atomics
= true;
1411 features
->shaderImageFloat32AtomicAdd
= false;
1412 features
->sparseImageFloat32Atomics
= false;
1413 features
->sparseImageFloat32AtomicAdd
= false;
1416 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_4444_FORMATS_FEATURES_EXT
: {
1417 VkPhysicalDevice4444FormatsFeaturesEXT
*features
=
1418 (VkPhysicalDevice4444FormatsFeaturesEXT
*)ext
;
1419 features
->formatA4R4G4B4
= true;
1420 features
->formatA4B4G4R4
= true;
1431 radv_max_descriptor_set_size()
1433 /* make sure that the entire descriptor set is addressable with a signed
1434 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1435 * be at most 2 GiB. the combined image & samples object count as one of
1436 * both. This limit is for the pipeline layout, not for the set layout, but
1437 * there is no set limit, so we just set a pipeline limit. I don't think
1438 * any app is going to hit this soon. */
1439 return ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
1440 - MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_INLINE_UNIFORM_BLOCK_COUNT
) /
1441 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1442 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1443 32 /* sampler, largest when combined with image */ +
1444 64 /* sampled image */ +
1445 64 /* storage image */);
1448 void radv_GetPhysicalDeviceProperties(
1449 VkPhysicalDevice physicalDevice
,
1450 VkPhysicalDeviceProperties
* pProperties
)
1452 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1453 VkSampleCountFlags sample_counts
= 0xf;
1455 size_t max_descriptor_set_size
= radv_max_descriptor_set_size();
1457 VkPhysicalDeviceLimits limits
= {
1458 .maxImageDimension1D
= (1 << 14),
1459 .maxImageDimension2D
= (1 << 14),
1460 .maxImageDimension3D
= (1 << 11),
1461 .maxImageDimensionCube
= (1 << 14),
1462 .maxImageArrayLayers
= (1 << 11),
1463 .maxTexelBufferElements
= UINT32_MAX
,
1464 .maxUniformBufferRange
= UINT32_MAX
,
1465 .maxStorageBufferRange
= UINT32_MAX
,
1466 .maxPushConstantsSize
= MAX_PUSH_CONSTANTS_SIZE
,
1467 .maxMemoryAllocationCount
= UINT32_MAX
,
1468 .maxSamplerAllocationCount
= 64 * 1024,
1469 .bufferImageGranularity
= 64, /* A cache line */
1470 .sparseAddressSpaceSize
= RADV_MAX_MEMORY_ALLOCATION_SIZE
, /* buffer max size */
1471 .maxBoundDescriptorSets
= MAX_SETS
,
1472 .maxPerStageDescriptorSamplers
= max_descriptor_set_size
,
1473 .maxPerStageDescriptorUniformBuffers
= max_descriptor_set_size
,
1474 .maxPerStageDescriptorStorageBuffers
= max_descriptor_set_size
,
1475 .maxPerStageDescriptorSampledImages
= max_descriptor_set_size
,
1476 .maxPerStageDescriptorStorageImages
= max_descriptor_set_size
,
1477 .maxPerStageDescriptorInputAttachments
= max_descriptor_set_size
,
1478 .maxPerStageResources
= max_descriptor_set_size
,
1479 .maxDescriptorSetSamplers
= max_descriptor_set_size
,
1480 .maxDescriptorSetUniformBuffers
= max_descriptor_set_size
,
1481 .maxDescriptorSetUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
,
1482 .maxDescriptorSetStorageBuffers
= max_descriptor_set_size
,
1483 .maxDescriptorSetStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
,
1484 .maxDescriptorSetSampledImages
= max_descriptor_set_size
,
1485 .maxDescriptorSetStorageImages
= max_descriptor_set_size
,
1486 .maxDescriptorSetInputAttachments
= max_descriptor_set_size
,
1487 .maxVertexInputAttributes
= MAX_VERTEX_ATTRIBS
,
1488 .maxVertexInputBindings
= MAX_VBS
,
1489 .maxVertexInputAttributeOffset
= 2047,
1490 .maxVertexInputBindingStride
= 2048,
1491 .maxVertexOutputComponents
= 128,
1492 .maxTessellationGenerationLevel
= 64,
1493 .maxTessellationPatchSize
= 32,
1494 .maxTessellationControlPerVertexInputComponents
= 128,
1495 .maxTessellationControlPerVertexOutputComponents
= 128,
1496 .maxTessellationControlPerPatchOutputComponents
= 120,
1497 .maxTessellationControlTotalOutputComponents
= 4096,
1498 .maxTessellationEvaluationInputComponents
= 128,
1499 .maxTessellationEvaluationOutputComponents
= 128,
1500 .maxGeometryShaderInvocations
= 127,
1501 .maxGeometryInputComponents
= 64,
1502 .maxGeometryOutputComponents
= 128,
1503 .maxGeometryOutputVertices
= 256,
1504 .maxGeometryTotalOutputComponents
= 1024,
1505 .maxFragmentInputComponents
= 128,
1506 .maxFragmentOutputAttachments
= 8,
1507 .maxFragmentDualSrcAttachments
= 1,
1508 .maxFragmentCombinedOutputResources
= 8,
1509 .maxComputeSharedMemorySize
= 32768,
1510 .maxComputeWorkGroupCount
= { 65535, 65535, 65535 },
1511 .maxComputeWorkGroupInvocations
= 1024,
1512 .maxComputeWorkGroupSize
= {
1517 .subPixelPrecisionBits
= 8,
1518 .subTexelPrecisionBits
= 8,
1519 .mipmapPrecisionBits
= 8,
1520 .maxDrawIndexedIndexValue
= UINT32_MAX
,
1521 .maxDrawIndirectCount
= UINT32_MAX
,
1522 .maxSamplerLodBias
= 16,
1523 .maxSamplerAnisotropy
= 16,
1524 .maxViewports
= MAX_VIEWPORTS
,
1525 .maxViewportDimensions
= { (1 << 14), (1 << 14) },
1526 .viewportBoundsRange
= { INT16_MIN
, INT16_MAX
},
1527 .viewportSubPixelBits
= 8,
1528 .minMemoryMapAlignment
= 4096, /* A page */
1529 .minTexelBufferOffsetAlignment
= 4,
1530 .minUniformBufferOffsetAlignment
= 4,
1531 .minStorageBufferOffsetAlignment
= 4,
1532 .minTexelOffset
= -32,
1533 .maxTexelOffset
= 31,
1534 .minTexelGatherOffset
= -32,
1535 .maxTexelGatherOffset
= 31,
1536 .minInterpolationOffset
= -2,
1537 .maxInterpolationOffset
= 2,
1538 .subPixelInterpolationOffsetBits
= 8,
1539 .maxFramebufferWidth
= (1 << 14),
1540 .maxFramebufferHeight
= (1 << 14),
1541 .maxFramebufferLayers
= (1 << 10),
1542 .framebufferColorSampleCounts
= sample_counts
,
1543 .framebufferDepthSampleCounts
= sample_counts
,
1544 .framebufferStencilSampleCounts
= sample_counts
,
1545 .framebufferNoAttachmentsSampleCounts
= sample_counts
,
1546 .maxColorAttachments
= MAX_RTS
,
1547 .sampledImageColorSampleCounts
= sample_counts
,
1548 .sampledImageIntegerSampleCounts
= sample_counts
,
1549 .sampledImageDepthSampleCounts
= sample_counts
,
1550 .sampledImageStencilSampleCounts
= sample_counts
,
1551 .storageImageSampleCounts
= sample_counts
,
1552 .maxSampleMaskWords
= 1,
1553 .timestampComputeAndGraphics
= true,
1554 .timestampPeriod
= 1000000.0 / pdevice
->rad_info
.clock_crystal_freq
,
1555 .maxClipDistances
= 8,
1556 .maxCullDistances
= 8,
1557 .maxCombinedClipAndCullDistances
= 8,
1558 .discreteQueuePriorities
= 2,
1559 .pointSizeRange
= { 0.0, 8191.875 },
1560 .lineWidthRange
= { 0.0, 8191.875 },
1561 .pointSizeGranularity
= (1.0 / 8.0),
1562 .lineWidthGranularity
= (1.0 / 8.0),
1563 .strictLines
= false, /* FINISHME */
1564 .standardSampleLocations
= true,
1565 .optimalBufferCopyOffsetAlignment
= 128,
1566 .optimalBufferCopyRowPitchAlignment
= 128,
1567 .nonCoherentAtomSize
= 64,
1570 *pProperties
= (VkPhysicalDeviceProperties
) {
1571 .apiVersion
= radv_physical_device_api_version(pdevice
),
1572 .driverVersion
= vk_get_driver_version(),
1573 .vendorID
= ATI_VENDOR_ID
,
1574 .deviceID
= pdevice
->rad_info
.pci_id
,
1575 .deviceType
= pdevice
->rad_info
.has_dedicated_vram
? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU
: VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU
,
1577 .sparseProperties
= {0},
1580 strcpy(pProperties
->deviceName
, pdevice
->name
);
1581 memcpy(pProperties
->pipelineCacheUUID
, pdevice
->cache_uuid
, VK_UUID_SIZE
);
1585 radv_get_physical_device_properties_1_1(struct radv_physical_device
*pdevice
,
1586 VkPhysicalDeviceVulkan11Properties
*p
)
1588 assert(p
->sType
== VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES
);
1590 memcpy(p
->deviceUUID
, pdevice
->device_uuid
, VK_UUID_SIZE
);
1591 memcpy(p
->driverUUID
, pdevice
->driver_uuid
, VK_UUID_SIZE
);
1592 memset(p
->deviceLUID
, 0, VK_LUID_SIZE
);
1593 /* The LUID is for Windows. */
1594 p
->deviceLUIDValid
= false;
1595 p
->deviceNodeMask
= 0;
1597 p
->subgroupSize
= RADV_SUBGROUP_SIZE
;
1598 p
->subgroupSupportedStages
= VK_SHADER_STAGE_ALL_GRAPHICS
|
1599 VK_SHADER_STAGE_COMPUTE_BIT
;
1600 p
->subgroupSupportedOperations
= VK_SUBGROUP_FEATURE_BASIC_BIT
|
1601 VK_SUBGROUP_FEATURE_VOTE_BIT
|
1602 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT
|
1603 VK_SUBGROUP_FEATURE_BALLOT_BIT
|
1604 VK_SUBGROUP_FEATURE_CLUSTERED_BIT
|
1605 VK_SUBGROUP_FEATURE_QUAD_BIT
|
1606 VK_SUBGROUP_FEATURE_SHUFFLE_BIT
|
1607 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT
;
1608 p
->subgroupQuadOperationsInAllStages
= true;
1610 p
->pointClippingBehavior
= VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES
;
1611 p
->maxMultiviewViewCount
= MAX_VIEWS
;
1612 p
->maxMultiviewInstanceIndex
= INT_MAX
;
1613 p
->protectedNoFault
= false;
1614 p
->maxPerSetDescriptors
= RADV_MAX_PER_SET_DESCRIPTORS
;
1615 p
->maxMemoryAllocationSize
= RADV_MAX_MEMORY_ALLOCATION_SIZE
;
1619 radv_get_physical_device_properties_1_2(struct radv_physical_device
*pdevice
,
1620 VkPhysicalDeviceVulkan12Properties
*p
)
1622 assert(p
->sType
== VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES
);
1624 p
->driverID
= VK_DRIVER_ID_MESA_RADV
;
1625 snprintf(p
->driverName
, VK_MAX_DRIVER_NAME_SIZE
, "radv");
1626 snprintf(p
->driverInfo
, VK_MAX_DRIVER_INFO_SIZE
,
1627 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
" (%s)",
1628 radv_get_compiler_string(pdevice
));
1629 p
->conformanceVersion
= (VkConformanceVersion
) {
1636 /* On AMD hardware, denormals and rounding modes for fp16/fp64 are
1637 * controlled by the same config register.
1639 if (pdevice
->rad_info
.has_packed_math_16bit
) {
1640 p
->denormBehaviorIndependence
= VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR
;
1641 p
->roundingModeIndependence
= VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR
;
1643 p
->denormBehaviorIndependence
= VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR
;
1644 p
->roundingModeIndependence
= VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR
;
1647 /* With LLVM, do not allow both preserving and flushing denorms because
1648 * different shaders in the same pipeline can have different settings and
1649 * this won't work for merged shaders. To make it work, this requires LLVM
1650 * support for changing the register. The same logic applies for the
1651 * rounding modes because they are configured with the same config
1654 p
->shaderDenormFlushToZeroFloat32
= true;
1655 p
->shaderDenormPreserveFloat32
= !pdevice
->use_llvm
;
1656 p
->shaderRoundingModeRTEFloat32
= true;
1657 p
->shaderRoundingModeRTZFloat32
= !pdevice
->use_llvm
;
1658 p
->shaderSignedZeroInfNanPreserveFloat32
= true;
1660 p
->shaderDenormFlushToZeroFloat16
= pdevice
->rad_info
.has_packed_math_16bit
&& !pdevice
->use_llvm
;
1661 p
->shaderDenormPreserveFloat16
= pdevice
->rad_info
.has_packed_math_16bit
;
1662 p
->shaderRoundingModeRTEFloat16
= pdevice
->rad_info
.has_packed_math_16bit
;
1663 p
->shaderRoundingModeRTZFloat16
= pdevice
->rad_info
.has_packed_math_16bit
&& !pdevice
->use_llvm
;
1664 p
->shaderSignedZeroInfNanPreserveFloat16
= pdevice
->rad_info
.has_packed_math_16bit
;
1666 p
->shaderDenormFlushToZeroFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_llvm
;
1667 p
->shaderDenormPreserveFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
;
1668 p
->shaderRoundingModeRTEFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
;
1669 p
->shaderRoundingModeRTZFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_llvm
;
1670 p
->shaderSignedZeroInfNanPreserveFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
;
1672 p
->maxUpdateAfterBindDescriptorsInAllPools
= UINT32_MAX
/ 64;
1673 p
->shaderUniformBufferArrayNonUniformIndexingNative
= false;
1674 p
->shaderSampledImageArrayNonUniformIndexingNative
= false;
1675 p
->shaderStorageBufferArrayNonUniformIndexingNative
= false;
1676 p
->shaderStorageImageArrayNonUniformIndexingNative
= false;
1677 p
->shaderInputAttachmentArrayNonUniformIndexingNative
= false;
1678 p
->robustBufferAccessUpdateAfterBind
= false;
1679 p
->quadDivergentImplicitLod
= false;
1681 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
-
1682 MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_INLINE_UNIFORM_BLOCK_COUNT
) /
1683 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1684 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1685 32 /* sampler, largest when combined with image */ +
1686 64 /* sampled image */ +
1687 64 /* storage image */);
1688 p
->maxPerStageDescriptorUpdateAfterBindSamplers
= max_descriptor_set_size
;
1689 p
->maxPerStageDescriptorUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1690 p
->maxPerStageDescriptorUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1691 p
->maxPerStageDescriptorUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1692 p
->maxPerStageDescriptorUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1693 p
->maxPerStageDescriptorUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1694 p
->maxPerStageUpdateAfterBindResources
= max_descriptor_set_size
;
1695 p
->maxDescriptorSetUpdateAfterBindSamplers
= max_descriptor_set_size
;
1696 p
->maxDescriptorSetUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1697 p
->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
;
1698 p
->maxDescriptorSetUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1699 p
->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
;
1700 p
->maxDescriptorSetUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1701 p
->maxDescriptorSetUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1702 p
->maxDescriptorSetUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1704 /* We support all of the depth resolve modes */
1705 p
->supportedDepthResolveModes
= VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
|
1706 VK_RESOLVE_MODE_AVERAGE_BIT_KHR
|
1707 VK_RESOLVE_MODE_MIN_BIT_KHR
|
1708 VK_RESOLVE_MODE_MAX_BIT_KHR
;
1710 /* Average doesn't make sense for stencil so we don't support that */
1711 p
->supportedStencilResolveModes
= VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
|
1712 VK_RESOLVE_MODE_MIN_BIT_KHR
|
1713 VK_RESOLVE_MODE_MAX_BIT_KHR
;
1715 p
->independentResolveNone
= true;
1716 p
->independentResolve
= true;
1718 /* GFX6-8 only support single channel min/max filter. */
1719 p
->filterMinmaxImageComponentMapping
= pdevice
->rad_info
.chip_class
>= GFX9
;
1720 p
->filterMinmaxSingleComponentFormats
= true;
1722 p
->maxTimelineSemaphoreValueDifference
= UINT64_MAX
;
1724 p
->framebufferIntegerColorSampleCounts
= VK_SAMPLE_COUNT_1_BIT
;
1727 void radv_GetPhysicalDeviceProperties2(
1728 VkPhysicalDevice physicalDevice
,
1729 VkPhysicalDeviceProperties2
*pProperties
)
1731 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1732 radv_GetPhysicalDeviceProperties(physicalDevice
, &pProperties
->properties
);
1734 VkPhysicalDeviceVulkan11Properties core_1_1
= {
1735 .sType
= VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES
,
1737 radv_get_physical_device_properties_1_1(pdevice
, &core_1_1
);
1739 VkPhysicalDeviceVulkan12Properties core_1_2
= {
1740 .sType
= VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES
,
1742 radv_get_physical_device_properties_1_2(pdevice
, &core_1_2
);
1744 #define CORE_RENAMED_PROPERTY(major, minor, ext_property, core_property) \
1745 memcpy(&properties->ext_property, &core_##major##_##minor.core_property, \
1746 sizeof(core_##major##_##minor.core_property))
1748 #define CORE_PROPERTY(major, minor, property) \
1749 CORE_RENAMED_PROPERTY(major, minor, property, property)
1751 vk_foreach_struct(ext
, pProperties
->pNext
) {
1752 switch (ext
->sType
) {
1753 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR
: {
1754 VkPhysicalDevicePushDescriptorPropertiesKHR
*properties
=
1755 (VkPhysicalDevicePushDescriptorPropertiesKHR
*) ext
;
1756 properties
->maxPushDescriptors
= MAX_PUSH_DESCRIPTORS
;
1759 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES
: {
1760 VkPhysicalDeviceIDProperties
*properties
= (VkPhysicalDeviceIDProperties
*)ext
;
1761 CORE_PROPERTY(1, 1, deviceUUID
);
1762 CORE_PROPERTY(1, 1, driverUUID
);
1763 CORE_PROPERTY(1, 1, deviceLUID
);
1764 CORE_PROPERTY(1, 1, deviceLUIDValid
);
1767 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES
: {
1768 VkPhysicalDeviceMultiviewProperties
*properties
= (VkPhysicalDeviceMultiviewProperties
*)ext
;
1769 CORE_PROPERTY(1, 1, maxMultiviewViewCount
);
1770 CORE_PROPERTY(1, 1, maxMultiviewInstanceIndex
);
1773 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES
: {
1774 VkPhysicalDevicePointClippingProperties
*properties
=
1775 (VkPhysicalDevicePointClippingProperties
*)ext
;
1776 CORE_PROPERTY(1, 1, pointClippingBehavior
);
1779 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT
: {
1780 VkPhysicalDeviceDiscardRectanglePropertiesEXT
*properties
=
1781 (VkPhysicalDeviceDiscardRectanglePropertiesEXT
*)ext
;
1782 properties
->maxDiscardRectangles
= MAX_DISCARD_RECTANGLES
;
1785 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT
: {
1786 VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*properties
=
1787 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*) ext
;
1788 properties
->minImportedHostPointerAlignment
= 4096;
1791 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES
: {
1792 VkPhysicalDeviceSubgroupProperties
*properties
=
1793 (VkPhysicalDeviceSubgroupProperties
*)ext
;
1794 CORE_PROPERTY(1, 1, subgroupSize
);
1795 CORE_RENAMED_PROPERTY(1, 1, supportedStages
,
1796 subgroupSupportedStages
);
1797 CORE_RENAMED_PROPERTY(1, 1, supportedOperations
,
1798 subgroupSupportedOperations
);
1799 CORE_RENAMED_PROPERTY(1, 1, quadOperationsInAllStages
,
1800 subgroupQuadOperationsInAllStages
);
1803 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES
: {
1804 VkPhysicalDeviceMaintenance3Properties
*properties
=
1805 (VkPhysicalDeviceMaintenance3Properties
*)ext
;
1806 CORE_PROPERTY(1, 1, maxPerSetDescriptors
);
1807 CORE_PROPERTY(1, 1, maxMemoryAllocationSize
);
1810 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES
: {
1811 VkPhysicalDeviceSamplerFilterMinmaxProperties
*properties
=
1812 (VkPhysicalDeviceSamplerFilterMinmaxProperties
*)ext
;
1813 CORE_PROPERTY(1, 2, filterMinmaxImageComponentMapping
);
1814 CORE_PROPERTY(1, 2, filterMinmaxSingleComponentFormats
);
1817 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD
: {
1818 VkPhysicalDeviceShaderCorePropertiesAMD
*properties
=
1819 (VkPhysicalDeviceShaderCorePropertiesAMD
*)ext
;
1821 /* Shader engines. */
1822 properties
->shaderEngineCount
=
1823 pdevice
->rad_info
.max_se
;
1824 properties
->shaderArraysPerEngineCount
=
1825 pdevice
->rad_info
.max_sh_per_se
;
1826 properties
->computeUnitsPerShaderArray
=
1827 pdevice
->rad_info
.min_good_cu_per_sa
;
1828 properties
->simdPerComputeUnit
=
1829 pdevice
->rad_info
.num_simd_per_compute_unit
;
1830 properties
->wavefrontsPerSimd
=
1831 pdevice
->rad_info
.max_wave64_per_simd
;
1832 properties
->wavefrontSize
= 64;
1835 properties
->sgprsPerSimd
=
1836 pdevice
->rad_info
.num_physical_sgprs_per_simd
;
1837 properties
->minSgprAllocation
=
1838 pdevice
->rad_info
.min_sgpr_alloc
;
1839 properties
->maxSgprAllocation
=
1840 pdevice
->rad_info
.max_sgpr_alloc
;
1841 properties
->sgprAllocationGranularity
=
1842 pdevice
->rad_info
.sgpr_alloc_granularity
;
1845 properties
->vgprsPerSimd
=
1846 pdevice
->rad_info
.num_physical_wave64_vgprs_per_simd
;
1847 properties
->minVgprAllocation
=
1848 pdevice
->rad_info
.min_wave64_vgpr_alloc
;
1849 properties
->maxVgprAllocation
=
1850 pdevice
->rad_info
.max_vgpr_alloc
;
1851 properties
->vgprAllocationGranularity
=
1852 pdevice
->rad_info
.wave64_vgpr_alloc_granularity
;
1855 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD
: {
1856 VkPhysicalDeviceShaderCoreProperties2AMD
*properties
=
1857 (VkPhysicalDeviceShaderCoreProperties2AMD
*)ext
;
1859 properties
->shaderCoreFeatures
= 0;
1860 properties
->activeComputeUnitCount
=
1861 pdevice
->rad_info
.num_good_compute_units
;
1864 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT
: {
1865 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*properties
=
1866 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*)ext
;
1867 properties
->maxVertexAttribDivisor
= UINT32_MAX
;
1870 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES
: {
1871 VkPhysicalDeviceDescriptorIndexingProperties
*properties
=
1872 (VkPhysicalDeviceDescriptorIndexingProperties
*)ext
;
1873 CORE_PROPERTY(1, 2, maxUpdateAfterBindDescriptorsInAllPools
);
1874 CORE_PROPERTY(1, 2, shaderUniformBufferArrayNonUniformIndexingNative
);
1875 CORE_PROPERTY(1, 2, shaderSampledImageArrayNonUniformIndexingNative
);
1876 CORE_PROPERTY(1, 2, shaderStorageBufferArrayNonUniformIndexingNative
);
1877 CORE_PROPERTY(1, 2, shaderStorageImageArrayNonUniformIndexingNative
);
1878 CORE_PROPERTY(1, 2, shaderInputAttachmentArrayNonUniformIndexingNative
);
1879 CORE_PROPERTY(1, 2, robustBufferAccessUpdateAfterBind
);
1880 CORE_PROPERTY(1, 2, quadDivergentImplicitLod
);
1881 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSamplers
);
1882 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindUniformBuffers
);
1883 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageBuffers
);
1884 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSampledImages
);
1885 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageImages
);
1886 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindInputAttachments
);
1887 CORE_PROPERTY(1, 2, maxPerStageUpdateAfterBindResources
);
1888 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSamplers
);
1889 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffers
);
1890 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffersDynamic
);
1891 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffers
);
1892 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffersDynamic
);
1893 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSampledImages
);
1894 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageImages
);
1895 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindInputAttachments
);
1898 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES
: {
1899 VkPhysicalDeviceProtectedMemoryProperties
*properties
=
1900 (VkPhysicalDeviceProtectedMemoryProperties
*)ext
;
1901 CORE_PROPERTY(1, 1, protectedNoFault
);
1904 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT
: {
1905 VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*properties
=
1906 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*)ext
;
1907 properties
->primitiveOverestimationSize
= 0;
1908 properties
->maxExtraPrimitiveOverestimationSize
= 0;
1909 properties
->extraPrimitiveOverestimationSizeGranularity
= 0;
1910 properties
->primitiveUnderestimation
= false;
1911 properties
->conservativePointAndLineRasterization
= false;
1912 properties
->degenerateTrianglesRasterized
= false;
1913 properties
->degenerateLinesRasterized
= false;
1914 properties
->fullyCoveredFragmentShaderInputVariable
= false;
1915 properties
->conservativeRasterizationPostDepthCoverage
= false;
1918 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT
: {
1919 VkPhysicalDevicePCIBusInfoPropertiesEXT
*properties
=
1920 (VkPhysicalDevicePCIBusInfoPropertiesEXT
*)ext
;
1921 properties
->pciDomain
= pdevice
->bus_info
.domain
;
1922 properties
->pciBus
= pdevice
->bus_info
.bus
;
1923 properties
->pciDevice
= pdevice
->bus_info
.dev
;
1924 properties
->pciFunction
= pdevice
->bus_info
.func
;
1927 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES
: {
1928 VkPhysicalDeviceDriverProperties
*properties
=
1929 (VkPhysicalDeviceDriverProperties
*) ext
;
1930 CORE_PROPERTY(1, 2, driverID
);
1931 CORE_PROPERTY(1, 2, driverName
);
1932 CORE_PROPERTY(1, 2, driverInfo
);
1933 CORE_PROPERTY(1, 2, conformanceVersion
);
1936 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT
: {
1937 VkPhysicalDeviceTransformFeedbackPropertiesEXT
*properties
=
1938 (VkPhysicalDeviceTransformFeedbackPropertiesEXT
*)ext
;
1939 properties
->maxTransformFeedbackStreams
= MAX_SO_STREAMS
;
1940 properties
->maxTransformFeedbackBuffers
= MAX_SO_BUFFERS
;
1941 properties
->maxTransformFeedbackBufferSize
= UINT32_MAX
;
1942 properties
->maxTransformFeedbackStreamDataSize
= 512;
1943 properties
->maxTransformFeedbackBufferDataSize
= UINT32_MAX
;
1944 properties
->maxTransformFeedbackBufferDataStride
= 512;
1945 properties
->transformFeedbackQueries
= !pdevice
->use_ngg_streamout
;
1946 properties
->transformFeedbackStreamsLinesTriangles
= !pdevice
->use_ngg_streamout
;
1947 properties
->transformFeedbackRasterizationStreamSelect
= false;
1948 properties
->transformFeedbackDraw
= true;
1951 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT
: {
1952 VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*props
=
1953 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*)ext
;
1955 props
->maxInlineUniformBlockSize
= MAX_INLINE_UNIFORM_BLOCK_SIZE
;
1956 props
->maxPerStageDescriptorInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1957 props
->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1958 props
->maxDescriptorSetInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1959 props
->maxDescriptorSetUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1962 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT
: {
1963 VkPhysicalDeviceSampleLocationsPropertiesEXT
*properties
=
1964 (VkPhysicalDeviceSampleLocationsPropertiesEXT
*)ext
;
1965 properties
->sampleLocationSampleCounts
= VK_SAMPLE_COUNT_2_BIT
|
1966 VK_SAMPLE_COUNT_4_BIT
|
1967 VK_SAMPLE_COUNT_8_BIT
;
1968 properties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2 , 2 };
1969 properties
->sampleLocationCoordinateRange
[0] = 0.0f
;
1970 properties
->sampleLocationCoordinateRange
[1] = 0.9375f
;
1971 properties
->sampleLocationSubPixelBits
= 4;
1972 properties
->variableSampleLocations
= false;
1975 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES
: {
1976 VkPhysicalDeviceDepthStencilResolveProperties
*properties
=
1977 (VkPhysicalDeviceDepthStencilResolveProperties
*)ext
;
1978 CORE_PROPERTY(1, 2, supportedDepthResolveModes
);
1979 CORE_PROPERTY(1, 2, supportedStencilResolveModes
);
1980 CORE_PROPERTY(1, 2, independentResolveNone
);
1981 CORE_PROPERTY(1, 2, independentResolve
);
1984 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_PROPERTIES_EXT
: {
1985 VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT
*properties
=
1986 (VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT
*)ext
;
1987 properties
->storageTexelBufferOffsetAlignmentBytes
= 4;
1988 properties
->storageTexelBufferOffsetSingleTexelAlignment
= true;
1989 properties
->uniformTexelBufferOffsetAlignmentBytes
= 4;
1990 properties
->uniformTexelBufferOffsetSingleTexelAlignment
= true;
1993 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT_CONTROLS_PROPERTIES
: {
1994 VkPhysicalDeviceFloatControlsProperties
*properties
=
1995 (VkPhysicalDeviceFloatControlsProperties
*)ext
;
1996 CORE_PROPERTY(1, 2, denormBehaviorIndependence
);
1997 CORE_PROPERTY(1, 2, roundingModeIndependence
);
1998 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat16
);
1999 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat16
);
2000 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat16
);
2001 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat16
);
2002 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat16
);
2003 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat32
);
2004 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat32
);
2005 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat32
);
2006 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat32
);
2007 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat32
);
2008 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat64
);
2009 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat64
);
2010 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat64
);
2011 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat64
);
2012 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat64
);
2015 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_PROPERTIES
: {
2016 VkPhysicalDeviceTimelineSemaphoreProperties
*properties
=
2017 (VkPhysicalDeviceTimelineSemaphoreProperties
*) ext
;
2018 CORE_PROPERTY(1, 2, maxTimelineSemaphoreValueDifference
);
2021 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_PROPERTIES_EXT
: {
2022 VkPhysicalDeviceSubgroupSizeControlPropertiesEXT
*props
=
2023 (VkPhysicalDeviceSubgroupSizeControlPropertiesEXT
*)ext
;
2024 props
->minSubgroupSize
= 64;
2025 props
->maxSubgroupSize
= 64;
2026 props
->maxComputeWorkgroupSubgroups
= UINT32_MAX
;
2027 props
->requiredSubgroupSizeStages
= 0;
2029 if (pdevice
->rad_info
.chip_class
>= GFX10
) {
2030 /* Only GFX10+ supports wave32. */
2031 props
->minSubgroupSize
= 32;
2032 props
->requiredSubgroupSizeStages
= VK_SHADER_STAGE_COMPUTE_BIT
;
2036 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES
:
2037 radv_get_physical_device_properties_1_1(pdevice
, (void *)ext
);
2039 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES
:
2040 radv_get_physical_device_properties_1_2(pdevice
, (void *)ext
);
2042 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_PROPERTIES_EXT
: {
2043 VkPhysicalDeviceLineRasterizationPropertiesEXT
*props
=
2044 (VkPhysicalDeviceLineRasterizationPropertiesEXT
*)ext
;
2045 props
->lineSubPixelPrecisionBits
= 4;
2048 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ROBUSTNESS_2_PROPERTIES_EXT
: {
2049 VkPhysicalDeviceRobustness2PropertiesEXT
*properties
=
2050 (VkPhysicalDeviceRobustness2PropertiesEXT
*)ext
;
2051 properties
->robustStorageBufferAccessSizeAlignment
= 4;
2052 properties
->robustUniformBufferAccessSizeAlignment
= 4;
2055 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_PROPERTIES_EXT
: {
2056 VkPhysicalDeviceCustomBorderColorPropertiesEXT
*props
=
2057 (VkPhysicalDeviceCustomBorderColorPropertiesEXT
*)ext
;
2058 props
->maxCustomBorderColorSamplers
= RADV_BORDER_COLOR_COUNT
;
2067 static void radv_get_physical_device_queue_family_properties(
2068 struct radv_physical_device
* pdevice
,
2070 VkQueueFamilyProperties
** pQueueFamilyProperties
)
2072 int num_queue_families
= 1;
2074 if (pdevice
->rad_info
.num_rings
[RING_COMPUTE
] > 0 &&
2075 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
))
2076 num_queue_families
++;
2078 if (pQueueFamilyProperties
== NULL
) {
2079 *pCount
= num_queue_families
;
2088 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
2089 .queueFlags
= VK_QUEUE_GRAPHICS_BIT
|
2090 VK_QUEUE_COMPUTE_BIT
|
2091 VK_QUEUE_TRANSFER_BIT
|
2092 VK_QUEUE_SPARSE_BINDING_BIT
,
2094 .timestampValidBits
= 64,
2095 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
2100 if (pdevice
->rad_info
.num_rings
[RING_COMPUTE
] > 0 &&
2101 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
)) {
2102 if (*pCount
> idx
) {
2103 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
2104 .queueFlags
= VK_QUEUE_COMPUTE_BIT
|
2105 VK_QUEUE_TRANSFER_BIT
|
2106 VK_QUEUE_SPARSE_BINDING_BIT
,
2107 .queueCount
= pdevice
->rad_info
.num_rings
[RING_COMPUTE
],
2108 .timestampValidBits
= 64,
2109 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
2117 void radv_GetPhysicalDeviceQueueFamilyProperties(
2118 VkPhysicalDevice physicalDevice
,
2120 VkQueueFamilyProperties
* pQueueFamilyProperties
)
2122 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
2123 if (!pQueueFamilyProperties
) {
2124 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
2127 VkQueueFamilyProperties
*properties
[] = {
2128 pQueueFamilyProperties
+ 0,
2129 pQueueFamilyProperties
+ 1,
2130 pQueueFamilyProperties
+ 2,
2132 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
2133 assert(*pCount
<= 3);
2136 void radv_GetPhysicalDeviceQueueFamilyProperties2(
2137 VkPhysicalDevice physicalDevice
,
2139 VkQueueFamilyProperties2
*pQueueFamilyProperties
)
2141 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
2142 if (!pQueueFamilyProperties
) {
2143 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
2146 VkQueueFamilyProperties
*properties
[] = {
2147 &pQueueFamilyProperties
[0].queueFamilyProperties
,
2148 &pQueueFamilyProperties
[1].queueFamilyProperties
,
2149 &pQueueFamilyProperties
[2].queueFamilyProperties
,
2151 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
2152 assert(*pCount
<= 3);
2155 void radv_GetPhysicalDeviceMemoryProperties(
2156 VkPhysicalDevice physicalDevice
,
2157 VkPhysicalDeviceMemoryProperties
*pMemoryProperties
)
2159 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
2161 *pMemoryProperties
= physical_device
->memory_properties
;
2165 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice
,
2166 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memoryBudget
)
2168 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
2169 VkPhysicalDeviceMemoryProperties
*memory_properties
= &device
->memory_properties
;
2170 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
2171 uint64_t vram_size
= radv_get_vram_size(device
);
2172 uint64_t gtt_size
= device
->rad_info
.gart_size
;
2173 uint64_t heap_budget
, heap_usage
;
2175 /* For all memory heaps, the computation of budget is as follow:
2176 * heap_budget = heap_size - global_heap_usage + app_heap_usage
2178 * The Vulkan spec 1.1.97 says that the budget should include any
2179 * currently allocated device memory.
2181 * Note that the application heap usages are not really accurate (eg.
2182 * in presence of shared buffers).
2184 for (int i
= 0; i
< device
->memory_properties
.memoryTypeCount
; i
++) {
2185 uint32_t heap_index
= device
->memory_properties
.memoryTypes
[i
].heapIndex
;
2187 if ((device
->memory_domains
[i
] & RADEON_DOMAIN_VRAM
) && (device
->memory_flags
[i
] & RADEON_FLAG_NO_CPU_ACCESS
)) {
2188 heap_usage
= device
->ws
->query_value(device
->ws
,
2189 RADEON_ALLOCATED_VRAM
);
2191 heap_budget
= vram_size
-
2192 device
->ws
->query_value(device
->ws
, RADEON_VRAM_USAGE
) +
2195 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
2196 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
2197 } else if (device
->memory_domains
[i
] & RADEON_DOMAIN_VRAM
) {
2198 heap_usage
= device
->ws
->query_value(device
->ws
,
2199 RADEON_ALLOCATED_VRAM_VIS
);
2201 heap_budget
= visible_vram_size
-
2202 device
->ws
->query_value(device
->ws
, RADEON_VRAM_VIS_USAGE
) +
2205 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
2206 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
2208 assert(device
->memory_domains
[i
] & RADEON_DOMAIN_GTT
);
2210 heap_usage
= device
->ws
->query_value(device
->ws
,
2211 RADEON_ALLOCATED_GTT
);
2213 heap_budget
= gtt_size
-
2214 device
->ws
->query_value(device
->ws
, RADEON_GTT_USAGE
) +
2217 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
2218 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
2222 /* The heapBudget and heapUsage values must be zero for array elements
2223 * greater than or equal to
2224 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
2226 for (uint32_t i
= memory_properties
->memoryHeapCount
; i
< VK_MAX_MEMORY_HEAPS
; i
++) {
2227 memoryBudget
->heapBudget
[i
] = 0;
2228 memoryBudget
->heapUsage
[i
] = 0;
2232 void radv_GetPhysicalDeviceMemoryProperties2(
2233 VkPhysicalDevice physicalDevice
,
2234 VkPhysicalDeviceMemoryProperties2
*pMemoryProperties
)
2236 radv_GetPhysicalDeviceMemoryProperties(physicalDevice
,
2237 &pMemoryProperties
->memoryProperties
);
2239 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memory_budget
=
2240 vk_find_struct(pMemoryProperties
->pNext
,
2241 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT
);
2243 radv_get_memory_budget_properties(physicalDevice
, memory_budget
);
2246 VkResult
radv_GetMemoryHostPointerPropertiesEXT(
2248 VkExternalMemoryHandleTypeFlagBits handleType
,
2249 const void *pHostPointer
,
2250 VkMemoryHostPointerPropertiesEXT
*pMemoryHostPointerProperties
)
2252 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2256 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
: {
2257 const struct radv_physical_device
*physical_device
= device
->physical_device
;
2258 uint32_t memoryTypeBits
= 0;
2259 for (int i
= 0; i
< physical_device
->memory_properties
.memoryTypeCount
; i
++) {
2260 if (physical_device
->memory_domains
[i
] == RADEON_DOMAIN_GTT
&&
2261 !(physical_device
->memory_flags
[i
] & RADEON_FLAG_GTT_WC
)) {
2262 memoryTypeBits
= (1 << i
);
2266 pMemoryHostPointerProperties
->memoryTypeBits
= memoryTypeBits
;
2270 return VK_ERROR_INVALID_EXTERNAL_HANDLE
;
2274 static enum radeon_ctx_priority
2275 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT
*pObj
)
2277 /* Default to MEDIUM when a specific global priority isn't requested */
2279 return RADEON_CTX_PRIORITY_MEDIUM
;
2281 switch(pObj
->globalPriority
) {
2282 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT
:
2283 return RADEON_CTX_PRIORITY_REALTIME
;
2284 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT
:
2285 return RADEON_CTX_PRIORITY_HIGH
;
2286 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT
:
2287 return RADEON_CTX_PRIORITY_MEDIUM
;
2288 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT
:
2289 return RADEON_CTX_PRIORITY_LOW
;
2291 unreachable("Illegal global priority value");
2292 return RADEON_CTX_PRIORITY_INVALID
;
2297 radv_queue_init(struct radv_device
*device
, struct radv_queue
*queue
,
2298 uint32_t queue_family_index
, int idx
,
2299 VkDeviceQueueCreateFlags flags
,
2300 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
)
2302 queue
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
2303 queue
->device
= device
;
2304 queue
->queue_family_index
= queue_family_index
;
2305 queue
->queue_idx
= idx
;
2306 queue
->priority
= radv_get_queue_global_priority(global_priority
);
2307 queue
->flags
= flags
;
2308 queue
->hw_ctx
= NULL
;
2310 VkResult result
= device
->ws
->ctx_create(device
->ws
, queue
->priority
, &queue
->hw_ctx
);
2311 if (result
!= VK_SUCCESS
)
2312 return vk_error(device
->instance
, result
);
2314 list_inithead(&queue
->pending_submissions
);
2315 pthread_mutex_init(&queue
->pending_mutex
, NULL
);
2317 pthread_mutex_init(&queue
->thread_mutex
, NULL
);
2318 queue
->thread_submission
= NULL
;
2319 queue
->thread_running
= queue
->thread_exit
= false;
2320 result
= radv_create_pthread_cond(&queue
->thread_cond
);
2321 if (result
!= VK_SUCCESS
)
2322 return vk_error(device
->instance
, result
);
2328 radv_queue_finish(struct radv_queue
*queue
)
2330 if (queue
->thread_running
) {
2331 p_atomic_set(&queue
->thread_exit
, true);
2332 pthread_cond_broadcast(&queue
->thread_cond
);
2333 pthread_join(queue
->submission_thread
, NULL
);
2335 pthread_cond_destroy(&queue
->thread_cond
);
2336 pthread_mutex_destroy(&queue
->pending_mutex
);
2337 pthread_mutex_destroy(&queue
->thread_mutex
);
2340 queue
->device
->ws
->ctx_destroy(queue
->hw_ctx
);
2342 if (queue
->initial_full_flush_preamble_cs
)
2343 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
2344 if (queue
->initial_preamble_cs
)
2345 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
2346 if (queue
->continue_preamble_cs
)
2347 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
2348 if (queue
->descriptor_bo
)
2349 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
2350 if (queue
->scratch_bo
)
2351 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
2352 if (queue
->esgs_ring_bo
)
2353 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
2354 if (queue
->gsvs_ring_bo
)
2355 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
2356 if (queue
->tess_rings_bo
)
2357 queue
->device
->ws
->buffer_destroy(queue
->tess_rings_bo
);
2359 queue
->device
->ws
->buffer_destroy(queue
->gds_bo
);
2360 if (queue
->gds_oa_bo
)
2361 queue
->device
->ws
->buffer_destroy(queue
->gds_oa_bo
);
2362 if (queue
->compute_scratch_bo
)
2363 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
2367 radv_bo_list_init(struct radv_bo_list
*bo_list
)
2369 pthread_mutex_init(&bo_list
->mutex
, NULL
);
2370 bo_list
->list
.count
= bo_list
->capacity
= 0;
2371 bo_list
->list
.bos
= NULL
;
2375 radv_bo_list_finish(struct radv_bo_list
*bo_list
)
2377 free(bo_list
->list
.bos
);
2378 pthread_mutex_destroy(&bo_list
->mutex
);
2381 VkResult
radv_bo_list_add(struct radv_device
*device
,
2382 struct radeon_winsys_bo
*bo
)
2384 struct radv_bo_list
*bo_list
= &device
->bo_list
;
2389 if (unlikely(!device
->use_global_bo_list
))
2392 pthread_mutex_lock(&bo_list
->mutex
);
2393 if (bo_list
->list
.count
== bo_list
->capacity
) {
2394 unsigned capacity
= MAX2(4, bo_list
->capacity
* 2);
2395 void *data
= realloc(bo_list
->list
.bos
, capacity
* sizeof(struct radeon_winsys_bo
*));
2398 pthread_mutex_unlock(&bo_list
->mutex
);
2399 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2402 bo_list
->list
.bos
= (struct radeon_winsys_bo
**)data
;
2403 bo_list
->capacity
= capacity
;
2406 bo_list
->list
.bos
[bo_list
->list
.count
++] = bo
;
2407 pthread_mutex_unlock(&bo_list
->mutex
);
2411 void radv_bo_list_remove(struct radv_device
*device
,
2412 struct radeon_winsys_bo
*bo
)
2414 struct radv_bo_list
*bo_list
= &device
->bo_list
;
2419 if (unlikely(!device
->use_global_bo_list
))
2422 pthread_mutex_lock(&bo_list
->mutex
);
2423 /* Loop the list backwards so we find the most recently added
2425 for(unsigned i
= bo_list
->list
.count
; i
-- > 0;) {
2426 if (bo_list
->list
.bos
[i
] == bo
) {
2427 bo_list
->list
.bos
[i
] = bo_list
->list
.bos
[bo_list
->list
.count
- 1];
2428 --bo_list
->list
.count
;
2432 pthread_mutex_unlock(&bo_list
->mutex
);
2436 radv_device_init_gs_info(struct radv_device
*device
)
2438 device
->gs_table_depth
= ac_get_gs_table_depth(device
->physical_device
->rad_info
.chip_class
,
2439 device
->physical_device
->rad_info
.family
);
2442 static int radv_get_device_extension_index(const char *name
)
2444 for (unsigned i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; ++i
) {
2445 if (strcmp(name
, radv_device_extensions
[i
].extensionName
) == 0)
2452 radv_get_int_debug_option(const char *name
, int default_value
)
2459 result
= default_value
;
2463 result
= strtol(str
, &endptr
, 0);
2464 if (str
== endptr
) {
2465 /* No digits founs. */
2466 result
= default_value
;
2474 radv_device_init_dispatch(struct radv_device
*device
)
2476 const struct radv_instance
*instance
= device
->physical_device
->instance
;
2477 const struct radv_device_dispatch_table
*dispatch_table_layer
= NULL
;
2478 bool unchecked
= instance
->debug_flags
& RADV_DEBUG_ALL_ENTRYPOINTS
;
2479 int radv_thread_trace
= radv_get_int_debug_option("RADV_THREAD_TRACE", -1);
2481 if (radv_thread_trace
>= 0) {
2482 /* Use device entrypoints from the SQTT layer if enabled. */
2483 dispatch_table_layer
= &sqtt_device_dispatch_table
;
2486 for (unsigned i
= 0; i
< ARRAY_SIZE(device
->dispatch
.entrypoints
); i
++) {
2487 /* Vulkan requires that entrypoints for extensions which have not been
2488 * enabled must not be advertised.
2491 !radv_device_entrypoint_is_enabled(i
, instance
->apiVersion
,
2492 &instance
->enabled_extensions
,
2493 &device
->enabled_extensions
)) {
2494 device
->dispatch
.entrypoints
[i
] = NULL
;
2495 } else if (dispatch_table_layer
&&
2496 dispatch_table_layer
->entrypoints
[i
]) {
2497 device
->dispatch
.entrypoints
[i
] =
2498 dispatch_table_layer
->entrypoints
[i
];
2500 device
->dispatch
.entrypoints
[i
] =
2501 radv_device_dispatch_table
.entrypoints
[i
];
2507 radv_create_pthread_cond(pthread_cond_t
*cond
)
2509 pthread_condattr_t condattr
;
2510 if (pthread_condattr_init(&condattr
)) {
2511 return VK_ERROR_INITIALIZATION_FAILED
;
2514 if (pthread_condattr_setclock(&condattr
, CLOCK_MONOTONIC
)) {
2515 pthread_condattr_destroy(&condattr
);
2516 return VK_ERROR_INITIALIZATION_FAILED
;
2518 if (pthread_cond_init(cond
, &condattr
)) {
2519 pthread_condattr_destroy(&condattr
);
2520 return VK_ERROR_INITIALIZATION_FAILED
;
2522 pthread_condattr_destroy(&condattr
);
2527 check_physical_device_features(VkPhysicalDevice physicalDevice
,
2528 const VkPhysicalDeviceFeatures
*features
)
2530 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
2531 VkPhysicalDeviceFeatures supported_features
;
2532 radv_GetPhysicalDeviceFeatures(physicalDevice
, &supported_features
);
2533 VkBool32
*supported_feature
= (VkBool32
*)&supported_features
;
2534 VkBool32
*enabled_feature
= (VkBool32
*)features
;
2535 unsigned num_features
= sizeof(VkPhysicalDeviceFeatures
) / sizeof(VkBool32
);
2536 for (uint32_t i
= 0; i
< num_features
; i
++) {
2537 if (enabled_feature
[i
] && !supported_feature
[i
])
2538 return vk_error(physical_device
->instance
, VK_ERROR_FEATURE_NOT_PRESENT
);
2544 static VkResult
radv_device_init_border_color(struct radv_device
*device
)
2546 device
->border_color_data
.bo
=
2547 device
->ws
->buffer_create(device
->ws
,
2548 RADV_BORDER_COLOR_BUFFER_SIZE
,
2551 RADEON_FLAG_CPU_ACCESS
|
2552 RADEON_FLAG_READ_ONLY
|
2553 RADEON_FLAG_NO_INTERPROCESS_SHARING
,
2554 RADV_BO_PRIORITY_SHADER
);
2556 if (device
->border_color_data
.bo
== NULL
)
2557 return vk_error(device
->physical_device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2559 device
->border_color_data
.colors_gpu_ptr
=
2560 device
->ws
->buffer_map(device
->border_color_data
.bo
);
2561 if (!device
->border_color_data
.colors_gpu_ptr
)
2562 return vk_error(device
->physical_device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2563 pthread_mutex_init(&device
->border_color_data
.mutex
, NULL
);
2568 static void radv_device_finish_border_color(struct radv_device
*device
)
2570 if (device
->border_color_data
.bo
) {
2571 device
->ws
->buffer_destroy(device
->border_color_data
.bo
);
2573 pthread_mutex_destroy(&device
->border_color_data
.mutex
);
2577 VkResult
radv_CreateDevice(
2578 VkPhysicalDevice physicalDevice
,
2579 const VkDeviceCreateInfo
* pCreateInfo
,
2580 const VkAllocationCallbacks
* pAllocator
,
2583 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
2585 struct radv_device
*device
;
2587 bool keep_shader_info
= false;
2588 bool robust_buffer_access
= false;
2589 bool overallocation_disallowed
= false;
2590 bool custom_border_colors
= false;
2592 /* Check enabled features */
2593 if (pCreateInfo
->pEnabledFeatures
) {
2594 result
= check_physical_device_features(physicalDevice
,
2595 pCreateInfo
->pEnabledFeatures
);
2596 if (result
!= VK_SUCCESS
)
2599 if (pCreateInfo
->pEnabledFeatures
->robustBufferAccess
)
2600 robust_buffer_access
= true;
2603 vk_foreach_struct_const(ext
, pCreateInfo
->pNext
) {
2604 switch (ext
->sType
) {
2605 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FEATURES_2
: {
2606 const VkPhysicalDeviceFeatures2
*features
= (const void *)ext
;
2607 result
= check_physical_device_features(physicalDevice
,
2608 &features
->features
);
2609 if (result
!= VK_SUCCESS
)
2612 if (features
->features
.robustBufferAccess
)
2613 robust_buffer_access
= true;
2616 case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD
: {
2617 const VkDeviceMemoryOverallocationCreateInfoAMD
*overallocation
= (const void *)ext
;
2618 if (overallocation
->overallocationBehavior
== VK_MEMORY_OVERALLOCATION_BEHAVIOR_DISALLOWED_AMD
)
2619 overallocation_disallowed
= true;
2622 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_FEATURES_EXT
: {
2623 const VkPhysicalDeviceCustomBorderColorFeaturesEXT
*border_color_features
= (const void *)ext
;
2624 custom_border_colors
= border_color_features
->customBorderColors
;
2632 device
= vk_zalloc2(&physical_device
->instance
->alloc
, pAllocator
,
2634 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2636 return vk_error(physical_device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2638 vk_device_init(&device
->vk
, pCreateInfo
,
2639 &physical_device
->instance
->alloc
, pAllocator
);
2641 device
->instance
= physical_device
->instance
;
2642 device
->physical_device
= physical_device
;
2644 device
->ws
= physical_device
->ws
;
2646 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
2647 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
2648 int index
= radv_get_device_extension_index(ext_name
);
2649 if (index
< 0 || !physical_device
->supported_extensions
.extensions
[index
]) {
2650 vk_free(&device
->vk
.alloc
, device
);
2651 return vk_error(physical_device
->instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
2654 device
->enabled_extensions
.extensions
[index
] = true;
2657 radv_device_init_dispatch(device
);
2659 keep_shader_info
= device
->enabled_extensions
.AMD_shader_info
;
2661 /* With update after bind we can't attach bo's to the command buffer
2662 * from the descriptor set anymore, so we have to use a global BO list.
2664 device
->use_global_bo_list
=
2665 (device
->instance
->perftest_flags
& RADV_PERFTEST_BO_LIST
) ||
2666 device
->enabled_extensions
.EXT_descriptor_indexing
||
2667 device
->enabled_extensions
.EXT_buffer_device_address
||
2668 device
->enabled_extensions
.KHR_buffer_device_address
;
2670 device
->robust_buffer_access
= robust_buffer_access
;
2672 mtx_init(&device
->shader_slab_mutex
, mtx_plain
);
2673 list_inithead(&device
->shader_slabs
);
2675 device
->overallocation_disallowed
= overallocation_disallowed
;
2676 mtx_init(&device
->overallocation_mutex
, mtx_plain
);
2678 radv_bo_list_init(&device
->bo_list
);
2680 for (unsigned i
= 0; i
< pCreateInfo
->queueCreateInfoCount
; i
++) {
2681 const VkDeviceQueueCreateInfo
*queue_create
= &pCreateInfo
->pQueueCreateInfos
[i
];
2682 uint32_t qfi
= queue_create
->queueFamilyIndex
;
2683 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
=
2684 vk_find_struct_const(queue_create
->pNext
, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT
);
2686 assert(!global_priority
|| device
->physical_device
->rad_info
.has_ctx_priority
);
2688 device
->queues
[qfi
] = vk_alloc(&device
->vk
.alloc
,
2689 queue_create
->queueCount
* sizeof(struct radv_queue
), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2690 if (!device
->queues
[qfi
]) {
2691 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2695 memset(device
->queues
[qfi
], 0, queue_create
->queueCount
* sizeof(struct radv_queue
));
2697 device
->queue_count
[qfi
] = queue_create
->queueCount
;
2699 for (unsigned q
= 0; q
< queue_create
->queueCount
; q
++) {
2700 result
= radv_queue_init(device
, &device
->queues
[qfi
][q
],
2701 qfi
, q
, queue_create
->flags
,
2703 if (result
!= VK_SUCCESS
)
2708 device
->pbb_allowed
= device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2709 !(device
->instance
->debug_flags
& RADV_DEBUG_NOBINNING
);
2711 /* Disable DFSM by default. As of 2019-09-15 Talos on Low is still 3% slower on Raven. */
2712 device
->dfsm_allowed
= device
->pbb_allowed
&&
2713 (device
->instance
->perftest_flags
& RADV_PERFTEST_DFSM
);
2715 device
->always_use_syncobj
= device
->physical_device
->rad_info
.has_syncobj_wait_for_submit
;
2717 /* The maximum number of scratch waves. Scratch space isn't divided
2718 * evenly between CUs. The number is only a function of the number of CUs.
2719 * We can decrease the constant to decrease the scratch buffer size.
2721 * sctx->scratch_waves must be >= the maximum possible size of
2722 * 1 threadgroup, so that the hw doesn't hang from being unable
2725 * The recommended value is 4 per CU at most. Higher numbers don't
2726 * bring much benefit, but they still occupy chip resources (think
2727 * async compute). I've seen ~2% performance difference between 4 and 32.
2729 uint32_t max_threads_per_block
= 2048;
2730 device
->scratch_waves
= MAX2(32 * physical_device
->rad_info
.num_good_compute_units
,
2731 max_threads_per_block
/ 64);
2733 device
->dispatch_initiator
= S_00B800_COMPUTE_SHADER_EN(1);
2735 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2736 /* If the KMD allows it (there is a KMD hw register for it),
2737 * allow launching waves out-of-order.
2739 device
->dispatch_initiator
|= S_00B800_ORDER_MODE(1);
2742 radv_device_init_gs_info(device
);
2744 device
->tess_offchip_block_dw_size
=
2745 device
->physical_device
->rad_info
.family
== CHIP_HAWAII
? 4096 : 8192;
2747 if (getenv("RADV_TRACE_FILE")) {
2748 const char *filename
= getenv("RADV_TRACE_FILE");
2750 keep_shader_info
= true;
2752 if (!radv_init_trace(device
))
2755 fprintf(stderr
, "*****************************************************************************\n");
2756 fprintf(stderr
, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
2757 fprintf(stderr
, "*****************************************************************************\n");
2759 fprintf(stderr
, "Trace file will be dumped to %s\n", filename
);
2760 radv_dump_enabled_options(device
, stderr
);
2763 int radv_thread_trace
= radv_get_int_debug_option("RADV_THREAD_TRACE", -1);
2764 if (radv_thread_trace
>= 0) {
2765 fprintf(stderr
, "*************************************************\n");
2766 fprintf(stderr
, "* WARNING: Thread trace support is experimental *\n");
2767 fprintf(stderr
, "*************************************************\n");
2769 if (device
->physical_device
->rad_info
.chip_class
< GFX8
) {
2770 fprintf(stderr
, "GPU hardware not supported: refer to "
2771 "the RGP documentation for the list of "
2772 "supported GPUs!\n");
2776 /* Default buffer size set to 1MB per SE. */
2777 device
->thread_trace_buffer_size
=
2778 radv_get_int_debug_option("RADV_THREAD_TRACE_BUFFER_SIZE", 1024 * 1024);
2779 device
->thread_trace_start_frame
= radv_thread_trace
;
2781 if (!radv_thread_trace_init(device
))
2785 device
->keep_shader_info
= keep_shader_info
;
2786 result
= radv_device_init_meta(device
);
2787 if (result
!= VK_SUCCESS
)
2790 radv_device_init_msaa(device
);
2792 /* If the border color extension is enabled, let's create the buffer we need. */
2793 if (custom_border_colors
) {
2794 result
= radv_device_init_border_color(device
);
2795 if (result
!= VK_SUCCESS
)
2799 for (int family
= 0; family
< RADV_MAX_QUEUE_FAMILIES
; ++family
) {
2800 device
->empty_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
2801 if (!device
->empty_cs
[family
])
2805 case RADV_QUEUE_GENERAL
:
2806 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2807 radeon_emit(device
->empty_cs
[family
], CC0_UPDATE_LOAD_ENABLES(1));
2808 radeon_emit(device
->empty_cs
[family
], CC1_UPDATE_SHADOW_ENABLES(1));
2810 case RADV_QUEUE_COMPUTE
:
2811 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_NOP
, 0, 0));
2812 radeon_emit(device
->empty_cs
[family
], 0);
2816 result
= device
->ws
->cs_finalize(device
->empty_cs
[family
]);
2817 if (result
!= VK_SUCCESS
)
2821 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
2822 cik_create_gfx_config(device
);
2824 VkPipelineCacheCreateInfo ci
;
2825 ci
.sType
= VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
;
2828 ci
.pInitialData
= NULL
;
2829 ci
.initialDataSize
= 0;
2831 result
= radv_CreatePipelineCache(radv_device_to_handle(device
),
2833 if (result
!= VK_SUCCESS
)
2836 device
->mem_cache
= radv_pipeline_cache_from_handle(pc
);
2838 result
= radv_create_pthread_cond(&device
->timeline_cond
);
2839 if (result
!= VK_SUCCESS
)
2840 goto fail_mem_cache
;
2842 device
->force_aniso
=
2843 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2844 if (device
->force_aniso
>= 0) {
2845 fprintf(stderr
, "radv: Forcing anisotropy filter to %ix\n",
2846 1 << util_logbase2(device
->force_aniso
));
2849 *pDevice
= radv_device_to_handle(device
);
2853 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
2855 radv_device_finish_meta(device
);
2857 radv_bo_list_finish(&device
->bo_list
);
2859 radv_thread_trace_finish(device
);
2861 if (device
->trace_bo
)
2862 device
->ws
->buffer_destroy(device
->trace_bo
);
2864 if (device
->gfx_init
)
2865 device
->ws
->buffer_destroy(device
->gfx_init
);
2867 radv_device_finish_border_color(device
);
2869 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
2870 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
2871 radv_queue_finish(&device
->queues
[i
][q
]);
2872 if (device
->queue_count
[i
])
2873 vk_free(&device
->vk
.alloc
, device
->queues
[i
]);
2876 vk_free(&device
->vk
.alloc
, device
);
2880 void radv_DestroyDevice(
2882 const VkAllocationCallbacks
* pAllocator
)
2884 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2889 if (device
->trace_bo
)
2890 device
->ws
->buffer_destroy(device
->trace_bo
);
2892 if (device
->gfx_init
)
2893 device
->ws
->buffer_destroy(device
->gfx_init
);
2895 radv_device_finish_border_color(device
);
2897 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
2898 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
2899 radv_queue_finish(&device
->queues
[i
][q
]);
2900 if (device
->queue_count
[i
])
2901 vk_free(&device
->vk
.alloc
, device
->queues
[i
]);
2902 if (device
->empty_cs
[i
])
2903 device
->ws
->cs_destroy(device
->empty_cs
[i
]);
2905 radv_device_finish_meta(device
);
2907 VkPipelineCache pc
= radv_pipeline_cache_to_handle(device
->mem_cache
);
2908 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
2910 radv_destroy_shader_slabs(device
);
2912 pthread_cond_destroy(&device
->timeline_cond
);
2913 radv_bo_list_finish(&device
->bo_list
);
2915 radv_thread_trace_finish(device
);
2917 vk_free(&device
->vk
.alloc
, device
);
2920 VkResult
radv_EnumerateInstanceLayerProperties(
2921 uint32_t* pPropertyCount
,
2922 VkLayerProperties
* pProperties
)
2924 if (pProperties
== NULL
) {
2925 *pPropertyCount
= 0;
2929 /* None supported at this time */
2930 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
2933 VkResult
radv_EnumerateDeviceLayerProperties(
2934 VkPhysicalDevice physicalDevice
,
2935 uint32_t* pPropertyCount
,
2936 VkLayerProperties
* pProperties
)
2938 if (pProperties
== NULL
) {
2939 *pPropertyCount
= 0;
2943 /* None supported at this time */
2944 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
2947 void radv_GetDeviceQueue2(
2949 const VkDeviceQueueInfo2
* pQueueInfo
,
2952 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2953 struct radv_queue
*queue
;
2955 queue
= &device
->queues
[pQueueInfo
->queueFamilyIndex
][pQueueInfo
->queueIndex
];
2956 if (pQueueInfo
->flags
!= queue
->flags
) {
2957 /* From the Vulkan 1.1.70 spec:
2959 * "The queue returned by vkGetDeviceQueue2 must have the same
2960 * flags value from this structure as that used at device
2961 * creation time in a VkDeviceQueueCreateInfo instance. If no
2962 * matching flags were specified at device creation time then
2963 * pQueue will return VK_NULL_HANDLE."
2965 *pQueue
= VK_NULL_HANDLE
;
2969 *pQueue
= radv_queue_to_handle(queue
);
2972 void radv_GetDeviceQueue(
2974 uint32_t queueFamilyIndex
,
2975 uint32_t queueIndex
,
2978 const VkDeviceQueueInfo2 info
= (VkDeviceQueueInfo2
) {
2979 .sType
= VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2
,
2980 .queueFamilyIndex
= queueFamilyIndex
,
2981 .queueIndex
= queueIndex
2984 radv_GetDeviceQueue2(_device
, &info
, pQueue
);
2988 fill_geom_tess_rings(struct radv_queue
*queue
,
2990 bool add_sample_positions
,
2991 uint32_t esgs_ring_size
,
2992 struct radeon_winsys_bo
*esgs_ring_bo
,
2993 uint32_t gsvs_ring_size
,
2994 struct radeon_winsys_bo
*gsvs_ring_bo
,
2995 uint32_t tess_factor_ring_size
,
2996 uint32_t tess_offchip_ring_offset
,
2997 uint32_t tess_offchip_ring_size
,
2998 struct radeon_winsys_bo
*tess_rings_bo
)
3000 uint32_t *desc
= &map
[4];
3003 uint64_t esgs_va
= radv_buffer_get_va(esgs_ring_bo
);
3005 /* stride 0, num records - size, add tid, swizzle, elsize4,
3008 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32) |
3009 S_008F04_SWIZZLE_ENABLE(true);
3010 desc
[2] = esgs_ring_size
;
3011 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3012 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3013 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3014 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
3015 S_008F0C_INDEX_STRIDE(3) |
3016 S_008F0C_ADD_TID_ENABLE(1);
3018 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3019 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3020 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3021 S_008F0C_RESOURCE_LEVEL(1);
3023 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3024 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
3025 S_008F0C_ELEMENT_SIZE(1);
3028 /* GS entry for ES->GS ring */
3029 /* stride 0, num records - size, elsize0,
3032 desc
[5] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32);
3033 desc
[6] = esgs_ring_size
;
3034 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3035 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3036 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3037 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3039 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3040 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3041 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3042 S_008F0C_RESOURCE_LEVEL(1);
3044 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3045 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3052 uint64_t gsvs_va
= radv_buffer_get_va(gsvs_ring_bo
);
3054 /* VS entry for GS->VS ring */
3055 /* stride 0, num records - size, elsize0,
3058 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32);
3059 desc
[2] = gsvs_ring_size
;
3060 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3061 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3062 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3063 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3065 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3066 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3067 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3068 S_008F0C_RESOURCE_LEVEL(1);
3070 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3071 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3074 /* stride gsvs_itemsize, num records 64
3075 elsize 4, index stride 16 */
3076 /* shader will patch stride and desc[2] */
3078 desc
[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32) |
3079 S_008F04_SWIZZLE_ENABLE(1);
3081 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3082 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3083 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3084 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
3085 S_008F0C_INDEX_STRIDE(1) |
3086 S_008F0C_ADD_TID_ENABLE(true);
3088 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3089 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3090 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3091 S_008F0C_RESOURCE_LEVEL(1);
3093 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3094 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
3095 S_008F0C_ELEMENT_SIZE(1);
3102 if (tess_rings_bo
) {
3103 uint64_t tess_va
= radv_buffer_get_va(tess_rings_bo
);
3104 uint64_t tess_offchip_va
= tess_va
+ tess_offchip_ring_offset
;
3107 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_va
>> 32);
3108 desc
[2] = tess_factor_ring_size
;
3109 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3110 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3111 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3112 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3114 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3115 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3116 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
3117 S_008F0C_RESOURCE_LEVEL(1);
3119 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3120 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3123 desc
[4] = tess_offchip_va
;
3124 desc
[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va
>> 32);
3125 desc
[6] = tess_offchip_ring_size
;
3126 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3127 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3128 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3129 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3131 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3132 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3133 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
3134 S_008F0C_RESOURCE_LEVEL(1);
3136 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3137 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3143 if (add_sample_positions
) {
3144 /* add sample positions after all rings */
3145 memcpy(desc
, queue
->device
->sample_locations_1x
, 8);
3147 memcpy(desc
, queue
->device
->sample_locations_2x
, 16);
3149 memcpy(desc
, queue
->device
->sample_locations_4x
, 32);
3151 memcpy(desc
, queue
->device
->sample_locations_8x
, 64);
3156 radv_get_hs_offchip_param(struct radv_device
*device
, uint32_t *max_offchip_buffers_p
)
3158 bool double_offchip_buffers
= device
->physical_device
->rad_info
.chip_class
>= GFX7
&&
3159 device
->physical_device
->rad_info
.family
!= CHIP_CARRIZO
&&
3160 device
->physical_device
->rad_info
.family
!= CHIP_STONEY
;
3161 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
3162 unsigned max_offchip_buffers
;
3163 unsigned offchip_granularity
;
3164 unsigned hs_offchip_param
;
3168 * This must be one less than the maximum number due to a hw limitation.
3169 * Various hardware bugs need thGFX7
3172 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
3173 * Gfx7 should limit max_offchip_buffers to 508
3174 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
3176 * Follow AMDVLK here.
3178 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3179 max_offchip_buffers_per_se
= 256;
3180 } else if (device
->physical_device
->rad_info
.family
== CHIP_VEGA10
||
3181 device
->physical_device
->rad_info
.chip_class
== GFX7
||
3182 device
->physical_device
->rad_info
.chip_class
== GFX6
)
3183 --max_offchip_buffers_per_se
;
3185 max_offchip_buffers
= max_offchip_buffers_per_se
*
3186 device
->physical_device
->rad_info
.max_se
;
3188 /* Hawaii has a bug with offchip buffers > 256 that can be worked
3189 * around by setting 4K granularity.
3191 if (device
->tess_offchip_block_dw_size
== 4096) {
3192 assert(device
->physical_device
->rad_info
.family
== CHIP_HAWAII
);
3193 offchip_granularity
= V_03093C_X_4K_DWORDS
;
3195 assert(device
->tess_offchip_block_dw_size
== 8192);
3196 offchip_granularity
= V_03093C_X_8K_DWORDS
;
3199 switch (device
->physical_device
->rad_info
.chip_class
) {
3201 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
3206 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
3214 *max_offchip_buffers_p
= max_offchip_buffers
;
3215 if (device
->physical_device
->rad_info
.chip_class
>= GFX10_3
) {
3216 hs_offchip_param
= S_03093C_OFFCHIP_BUFFERING_GFX103(max_offchip_buffers
- 1) |
3217 S_03093C_OFFCHIP_GRANULARITY_GFX103(offchip_granularity
);
3218 } else if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3219 if (device
->physical_device
->rad_info
.chip_class
>= GFX8
)
3220 --max_offchip_buffers
;
3222 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
3223 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
3226 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
3228 return hs_offchip_param
;
3232 radv_emit_gs_ring_sizes(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3233 struct radeon_winsys_bo
*esgs_ring_bo
,
3234 uint32_t esgs_ring_size
,
3235 struct radeon_winsys_bo
*gsvs_ring_bo
,
3236 uint32_t gsvs_ring_size
)
3238 if (!esgs_ring_bo
&& !gsvs_ring_bo
)
3242 radv_cs_add_buffer(queue
->device
->ws
, cs
, esgs_ring_bo
);
3245 radv_cs_add_buffer(queue
->device
->ws
, cs
, gsvs_ring_bo
);
3247 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3248 radeon_set_uconfig_reg_seq(cs
, R_030900_VGT_ESGS_RING_SIZE
, 2);
3249 radeon_emit(cs
, esgs_ring_size
>> 8);
3250 radeon_emit(cs
, gsvs_ring_size
>> 8);
3252 radeon_set_config_reg_seq(cs
, R_0088C8_VGT_ESGS_RING_SIZE
, 2);
3253 radeon_emit(cs
, esgs_ring_size
>> 8);
3254 radeon_emit(cs
, gsvs_ring_size
>> 8);
3259 radv_emit_tess_factor_ring(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3260 unsigned hs_offchip_param
, unsigned tf_ring_size
,
3261 struct radeon_winsys_bo
*tess_rings_bo
)
3268 tf_va
= radv_buffer_get_va(tess_rings_bo
);
3270 radv_cs_add_buffer(queue
->device
->ws
, cs
, tess_rings_bo
);
3272 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3273 radeon_set_uconfig_reg(cs
, R_030938_VGT_TF_RING_SIZE
,
3274 S_030938_SIZE(tf_ring_size
/ 4));
3275 radeon_set_uconfig_reg(cs
, R_030940_VGT_TF_MEMORY_BASE
,
3278 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3279 radeon_set_uconfig_reg(cs
, R_030984_VGT_TF_MEMORY_BASE_HI_UMD
,
3280 S_030984_BASE_HI(tf_va
>> 40));
3281 } else if (queue
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3282 radeon_set_uconfig_reg(cs
, R_030944_VGT_TF_MEMORY_BASE_HI
,
3283 S_030944_BASE_HI(tf_va
>> 40));
3285 radeon_set_uconfig_reg(cs
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
3288 radeon_set_config_reg(cs
, R_008988_VGT_TF_RING_SIZE
,
3289 S_008988_SIZE(tf_ring_size
/ 4));
3290 radeon_set_config_reg(cs
, R_0089B8_VGT_TF_MEMORY_BASE
,
3292 radeon_set_config_reg(cs
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
3298 radv_emit_graphics_scratch(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3299 uint32_t size_per_wave
, uint32_t waves
,
3300 struct radeon_winsys_bo
*scratch_bo
)
3302 if (queue
->queue_family_index
!= RADV_QUEUE_GENERAL
)
3308 radv_cs_add_buffer(queue
->device
->ws
, cs
, scratch_bo
);
3310 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
,
3311 S_0286E8_WAVES(waves
) |
3312 S_0286E8_WAVESIZE(round_up_u32(size_per_wave
, 1024)));
3316 radv_emit_compute_scratch(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3317 uint32_t size_per_wave
, uint32_t waves
,
3318 struct radeon_winsys_bo
*compute_scratch_bo
)
3320 uint64_t scratch_va
;
3322 if (!compute_scratch_bo
)
3325 scratch_va
= radv_buffer_get_va(compute_scratch_bo
);
3327 radv_cs_add_buffer(queue
->device
->ws
, cs
, compute_scratch_bo
);
3329 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, 2);
3330 radeon_emit(cs
, scratch_va
);
3331 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
3332 S_008F04_SWIZZLE_ENABLE(1));
3334 radeon_set_sh_reg(cs
, R_00B860_COMPUTE_TMPRING_SIZE
,
3335 S_00B860_WAVES(waves
) |
3336 S_00B860_WAVESIZE(round_up_u32(size_per_wave
, 1024)));
3340 radv_emit_global_shader_pointers(struct radv_queue
*queue
,
3341 struct radeon_cmdbuf
*cs
,
3342 struct radeon_winsys_bo
*descriptor_bo
)
3349 va
= radv_buffer_get_va(descriptor_bo
);
3351 radv_cs_add_buffer(queue
->device
->ws
, cs
, descriptor_bo
);
3353 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3354 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
3355 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
3356 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
3357 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
3359 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
3360 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
3363 } else if (queue
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3364 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
3365 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
3366 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
3367 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
3369 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
3370 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
3374 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
3375 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
3376 R_00B230_SPI_SHADER_USER_DATA_GS_0
,
3377 R_00B330_SPI_SHADER_USER_DATA_ES_0
,
3378 R_00B430_SPI_SHADER_USER_DATA_HS_0
,
3379 R_00B530_SPI_SHADER_USER_DATA_LS_0
};
3381 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
3382 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
3389 radv_init_graphics_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
3391 struct radv_device
*device
= queue
->device
;
3393 if (device
->gfx_init
) {
3394 uint64_t va
= radv_buffer_get_va(device
->gfx_init
);
3396 radeon_emit(cs
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
3397 radeon_emit(cs
, va
);
3398 radeon_emit(cs
, va
>> 32);
3399 radeon_emit(cs
, device
->gfx_init_size_dw
& 0xffff);
3401 radv_cs_add_buffer(device
->ws
, cs
, device
->gfx_init
);
3403 si_emit_graphics(device
, cs
);
3408 radv_init_compute_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
3410 si_emit_compute(queue
->device
, cs
);
3414 radv_get_preamble_cs(struct radv_queue
*queue
,
3415 uint32_t scratch_size_per_wave
,
3416 uint32_t scratch_waves
,
3417 uint32_t compute_scratch_size_per_wave
,
3418 uint32_t compute_scratch_waves
,
3419 uint32_t esgs_ring_size
,
3420 uint32_t gsvs_ring_size
,
3421 bool needs_tess_rings
,
3424 bool needs_sample_positions
,
3425 struct radeon_cmdbuf
**initial_full_flush_preamble_cs
,
3426 struct radeon_cmdbuf
**initial_preamble_cs
,
3427 struct radeon_cmdbuf
**continue_preamble_cs
)
3429 struct radeon_winsys_bo
*scratch_bo
= NULL
;
3430 struct radeon_winsys_bo
*descriptor_bo
= NULL
;
3431 struct radeon_winsys_bo
*compute_scratch_bo
= NULL
;
3432 struct radeon_winsys_bo
*esgs_ring_bo
= NULL
;
3433 struct radeon_winsys_bo
*gsvs_ring_bo
= NULL
;
3434 struct radeon_winsys_bo
*tess_rings_bo
= NULL
;
3435 struct radeon_winsys_bo
*gds_bo
= NULL
;
3436 struct radeon_winsys_bo
*gds_oa_bo
= NULL
;
3437 struct radeon_cmdbuf
*dest_cs
[3] = {0};
3438 bool add_tess_rings
= false, add_gds
= false, add_gds_oa
= false, add_sample_positions
= false;
3439 unsigned tess_factor_ring_size
= 0, tess_offchip_ring_size
= 0;
3440 unsigned max_offchip_buffers
;
3441 unsigned hs_offchip_param
= 0;
3442 unsigned tess_offchip_ring_offset
;
3443 uint32_t ring_bo_flags
= RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
;
3444 if (!queue
->has_tess_rings
) {
3445 if (needs_tess_rings
)
3446 add_tess_rings
= true;
3448 if (!queue
->has_gds
) {
3452 if (!queue
->has_gds_oa
) {
3456 if (!queue
->has_sample_positions
) {
3457 if (needs_sample_positions
)
3458 add_sample_positions
= true;
3460 tess_factor_ring_size
= 32768 * queue
->device
->physical_device
->rad_info
.max_se
;
3461 hs_offchip_param
= radv_get_hs_offchip_param(queue
->device
,
3462 &max_offchip_buffers
);
3463 tess_offchip_ring_offset
= align(tess_factor_ring_size
, 64 * 1024);
3464 tess_offchip_ring_size
= max_offchip_buffers
*
3465 queue
->device
->tess_offchip_block_dw_size
* 4;
3467 scratch_size_per_wave
= MAX2(scratch_size_per_wave
, queue
->scratch_size_per_wave
);
3468 if (scratch_size_per_wave
)
3469 scratch_waves
= MIN2(scratch_waves
, UINT32_MAX
/ scratch_size_per_wave
);
3473 compute_scratch_size_per_wave
= MAX2(compute_scratch_size_per_wave
, queue
->compute_scratch_size_per_wave
);
3474 if (compute_scratch_size_per_wave
)
3475 compute_scratch_waves
= MIN2(compute_scratch_waves
, UINT32_MAX
/ compute_scratch_size_per_wave
);
3477 compute_scratch_waves
= 0;
3479 if (scratch_size_per_wave
<= queue
->scratch_size_per_wave
&&
3480 scratch_waves
<= queue
->scratch_waves
&&
3481 compute_scratch_size_per_wave
<= queue
->compute_scratch_size_per_wave
&&
3482 compute_scratch_waves
<= queue
->compute_scratch_waves
&&
3483 esgs_ring_size
<= queue
->esgs_ring_size
&&
3484 gsvs_ring_size
<= queue
->gsvs_ring_size
&&
3485 !add_tess_rings
&& !add_gds
&& !add_gds_oa
&& !add_sample_positions
&&
3486 queue
->initial_preamble_cs
) {
3487 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
3488 *initial_preamble_cs
= queue
->initial_preamble_cs
;
3489 *continue_preamble_cs
= queue
->continue_preamble_cs
;
3490 if (!scratch_size_per_wave
&& !compute_scratch_size_per_wave
&&
3491 !esgs_ring_size
&& !gsvs_ring_size
&& !needs_tess_rings
&&
3492 !needs_gds
&& !needs_gds_oa
&& !needs_sample_positions
)
3493 *continue_preamble_cs
= NULL
;
3497 uint32_t scratch_size
= scratch_size_per_wave
* scratch_waves
;
3498 uint32_t queue_scratch_size
= queue
->scratch_size_per_wave
* queue
->scratch_waves
;
3499 if (scratch_size
> queue_scratch_size
) {
3500 scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3505 RADV_BO_PRIORITY_SCRATCH
);
3509 scratch_bo
= queue
->scratch_bo
;
3511 uint32_t compute_scratch_size
= compute_scratch_size_per_wave
* compute_scratch_waves
;
3512 uint32_t compute_queue_scratch_size
= queue
->compute_scratch_size_per_wave
* queue
->compute_scratch_waves
;
3513 if (compute_scratch_size
> compute_queue_scratch_size
) {
3514 compute_scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3515 compute_scratch_size
,
3519 RADV_BO_PRIORITY_SCRATCH
);
3520 if (!compute_scratch_bo
)
3524 compute_scratch_bo
= queue
->compute_scratch_bo
;
3526 if (esgs_ring_size
> queue
->esgs_ring_size
) {
3527 esgs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3532 RADV_BO_PRIORITY_SCRATCH
);
3536 esgs_ring_bo
= queue
->esgs_ring_bo
;
3537 esgs_ring_size
= queue
->esgs_ring_size
;
3540 if (gsvs_ring_size
> queue
->gsvs_ring_size
) {
3541 gsvs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3546 RADV_BO_PRIORITY_SCRATCH
);
3550 gsvs_ring_bo
= queue
->gsvs_ring_bo
;
3551 gsvs_ring_size
= queue
->gsvs_ring_size
;
3554 if (add_tess_rings
) {
3555 tess_rings_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3556 tess_offchip_ring_offset
+ tess_offchip_ring_size
,
3560 RADV_BO_PRIORITY_SCRATCH
);
3564 tess_rings_bo
= queue
->tess_rings_bo
;
3568 assert(queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
3570 /* 4 streamout GDS counters.
3571 * We need 256B (64 dw) of GDS, otherwise streamout hangs.
3573 gds_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3577 RADV_BO_PRIORITY_SCRATCH
);
3581 gds_bo
= queue
->gds_bo
;
3585 assert(queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
3587 gds_oa_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3591 RADV_BO_PRIORITY_SCRATCH
);
3595 gds_oa_bo
= queue
->gds_oa_bo
;
3598 if (scratch_bo
!= queue
->scratch_bo
||
3599 esgs_ring_bo
!= queue
->esgs_ring_bo
||
3600 gsvs_ring_bo
!= queue
->gsvs_ring_bo
||
3601 tess_rings_bo
!= queue
->tess_rings_bo
||
3602 add_sample_positions
) {
3604 if (gsvs_ring_bo
|| esgs_ring_bo
||
3605 tess_rings_bo
|| add_sample_positions
) {
3606 size
= 112; /* 2 dword + 2 padding + 4 dword * 6 */
3607 if (add_sample_positions
)
3608 size
+= 128; /* 64+32+16+8 = 120 bytes */
3610 else if (scratch_bo
)
3611 size
= 8; /* 2 dword */
3613 descriptor_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3617 RADEON_FLAG_CPU_ACCESS
|
3618 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
3619 RADEON_FLAG_READ_ONLY
,
3620 RADV_BO_PRIORITY_DESCRIPTOR
);
3624 descriptor_bo
= queue
->descriptor_bo
;
3626 if (descriptor_bo
!= queue
->descriptor_bo
) {
3627 uint32_t *map
= (uint32_t*)queue
->device
->ws
->buffer_map(descriptor_bo
);
3632 uint64_t scratch_va
= radv_buffer_get_va(scratch_bo
);
3633 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
3634 S_008F04_SWIZZLE_ENABLE(1);
3635 map
[0] = scratch_va
;
3639 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
|| add_sample_positions
)
3640 fill_geom_tess_rings(queue
, map
, add_sample_positions
,
3641 esgs_ring_size
, esgs_ring_bo
,
3642 gsvs_ring_size
, gsvs_ring_bo
,
3643 tess_factor_ring_size
,
3644 tess_offchip_ring_offset
,
3645 tess_offchip_ring_size
,
3648 queue
->device
->ws
->buffer_unmap(descriptor_bo
);
3651 for(int i
= 0; i
< 3; ++i
) {
3652 struct radeon_cmdbuf
*cs
= NULL
;
3653 cs
= queue
->device
->ws
->cs_create(queue
->device
->ws
,
3654 queue
->queue_family_index
? RING_COMPUTE
: RING_GFX
);
3661 radv_cs_add_buffer(queue
->device
->ws
, cs
, scratch_bo
);
3663 /* Emit initial configuration. */
3664 switch (queue
->queue_family_index
) {
3665 case RADV_QUEUE_GENERAL
:
3666 radv_init_graphics_state(cs
, queue
);
3668 case RADV_QUEUE_COMPUTE
:
3669 radv_init_compute_state(cs
, queue
);
3671 case RADV_QUEUE_TRANSFER
:
3675 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
) {
3676 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3677 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
3679 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3680 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
3683 radv_emit_gs_ring_sizes(queue
, cs
, esgs_ring_bo
, esgs_ring_size
,
3684 gsvs_ring_bo
, gsvs_ring_size
);
3685 radv_emit_tess_factor_ring(queue
, cs
, hs_offchip_param
,
3686 tess_factor_ring_size
, tess_rings_bo
);
3687 radv_emit_global_shader_pointers(queue
, cs
, descriptor_bo
);
3688 radv_emit_compute_scratch(queue
, cs
, compute_scratch_size_per_wave
,
3689 compute_scratch_waves
, compute_scratch_bo
);
3690 radv_emit_graphics_scratch(queue
, cs
, scratch_size_per_wave
,
3691 scratch_waves
, scratch_bo
);
3694 radv_cs_add_buffer(queue
->device
->ws
, cs
, gds_bo
);
3696 radv_cs_add_buffer(queue
->device
->ws
, cs
, gds_oa_bo
);
3698 if (queue
->device
->trace_bo
)
3699 radv_cs_add_buffer(queue
->device
->ws
, cs
, queue
->device
->trace_bo
);
3701 if (queue
->device
->border_color_data
.bo
)
3702 radv_cs_add_buffer(queue
->device
->ws
, cs
,
3703 queue
->device
->border_color_data
.bo
);
3706 si_cs_emit_cache_flush(cs
,
3707 queue
->device
->physical_device
->rad_info
.chip_class
,
3709 queue
->queue_family_index
== RING_COMPUTE
&&
3710 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
3711 (queue
->queue_family_index
== RADV_QUEUE_COMPUTE
? RADV_CMD_FLAG_CS_PARTIAL_FLUSH
: (RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
)) |
3712 RADV_CMD_FLAG_INV_ICACHE
|
3713 RADV_CMD_FLAG_INV_SCACHE
|
3714 RADV_CMD_FLAG_INV_VCACHE
|
3715 RADV_CMD_FLAG_INV_L2
|
3716 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
3717 } else if (i
== 1) {
3718 si_cs_emit_cache_flush(cs
,
3719 queue
->device
->physical_device
->rad_info
.chip_class
,
3721 queue
->queue_family_index
== RING_COMPUTE
&&
3722 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
3723 RADV_CMD_FLAG_INV_ICACHE
|
3724 RADV_CMD_FLAG_INV_SCACHE
|
3725 RADV_CMD_FLAG_INV_VCACHE
|
3726 RADV_CMD_FLAG_INV_L2
|
3727 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
3730 if (queue
->device
->ws
->cs_finalize(cs
) != VK_SUCCESS
)
3734 if (queue
->initial_full_flush_preamble_cs
)
3735 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
3737 if (queue
->initial_preamble_cs
)
3738 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
3740 if (queue
->continue_preamble_cs
)
3741 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
3743 queue
->initial_full_flush_preamble_cs
= dest_cs
[0];
3744 queue
->initial_preamble_cs
= dest_cs
[1];
3745 queue
->continue_preamble_cs
= dest_cs
[2];
3747 if (scratch_bo
!= queue
->scratch_bo
) {
3748 if (queue
->scratch_bo
)
3749 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
3750 queue
->scratch_bo
= scratch_bo
;
3752 queue
->scratch_size_per_wave
= scratch_size_per_wave
;
3753 queue
->scratch_waves
= scratch_waves
;
3755 if (compute_scratch_bo
!= queue
->compute_scratch_bo
) {
3756 if (queue
->compute_scratch_bo
)
3757 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
3758 queue
->compute_scratch_bo
= compute_scratch_bo
;
3760 queue
->compute_scratch_size_per_wave
= compute_scratch_size_per_wave
;
3761 queue
->compute_scratch_waves
= compute_scratch_waves
;
3763 if (esgs_ring_bo
!= queue
->esgs_ring_bo
) {
3764 if (queue
->esgs_ring_bo
)
3765 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
3766 queue
->esgs_ring_bo
= esgs_ring_bo
;
3767 queue
->esgs_ring_size
= esgs_ring_size
;
3770 if (gsvs_ring_bo
!= queue
->gsvs_ring_bo
) {
3771 if (queue
->gsvs_ring_bo
)
3772 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
3773 queue
->gsvs_ring_bo
= gsvs_ring_bo
;
3774 queue
->gsvs_ring_size
= gsvs_ring_size
;
3777 if (tess_rings_bo
!= queue
->tess_rings_bo
) {
3778 queue
->tess_rings_bo
= tess_rings_bo
;
3779 queue
->has_tess_rings
= true;
3782 if (gds_bo
!= queue
->gds_bo
) {
3783 queue
->gds_bo
= gds_bo
;
3784 queue
->has_gds
= true;
3787 if (gds_oa_bo
!= queue
->gds_oa_bo
) {
3788 queue
->gds_oa_bo
= gds_oa_bo
;
3789 queue
->has_gds_oa
= true;
3792 if (descriptor_bo
!= queue
->descriptor_bo
) {
3793 if (queue
->descriptor_bo
)
3794 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
3796 queue
->descriptor_bo
= descriptor_bo
;
3799 if (add_sample_positions
)
3800 queue
->has_sample_positions
= true;
3802 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
3803 *initial_preamble_cs
= queue
->initial_preamble_cs
;
3804 *continue_preamble_cs
= queue
->continue_preamble_cs
;
3805 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
3806 *continue_preamble_cs
= NULL
;
3809 for (int i
= 0; i
< ARRAY_SIZE(dest_cs
); ++i
)
3811 queue
->device
->ws
->cs_destroy(dest_cs
[i
]);
3812 if (descriptor_bo
&& descriptor_bo
!= queue
->descriptor_bo
)
3813 queue
->device
->ws
->buffer_destroy(descriptor_bo
);
3814 if (scratch_bo
&& scratch_bo
!= queue
->scratch_bo
)
3815 queue
->device
->ws
->buffer_destroy(scratch_bo
);
3816 if (compute_scratch_bo
&& compute_scratch_bo
!= queue
->compute_scratch_bo
)
3817 queue
->device
->ws
->buffer_destroy(compute_scratch_bo
);
3818 if (esgs_ring_bo
&& esgs_ring_bo
!= queue
->esgs_ring_bo
)
3819 queue
->device
->ws
->buffer_destroy(esgs_ring_bo
);
3820 if (gsvs_ring_bo
&& gsvs_ring_bo
!= queue
->gsvs_ring_bo
)
3821 queue
->device
->ws
->buffer_destroy(gsvs_ring_bo
);
3822 if (tess_rings_bo
&& tess_rings_bo
!= queue
->tess_rings_bo
)
3823 queue
->device
->ws
->buffer_destroy(tess_rings_bo
);
3824 if (gds_bo
&& gds_bo
!= queue
->gds_bo
)
3825 queue
->device
->ws
->buffer_destroy(gds_bo
);
3826 if (gds_oa_bo
&& gds_oa_bo
!= queue
->gds_oa_bo
)
3827 queue
->device
->ws
->buffer_destroy(gds_oa_bo
);
3829 return vk_error(queue
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3832 static VkResult
radv_alloc_sem_counts(struct radv_device
*device
,
3833 struct radv_winsys_sem_counts
*counts
,
3835 struct radv_semaphore_part
**sems
,
3836 const uint64_t *timeline_values
,
3840 int syncobj_idx
= 0, non_reset_idx
= 0, sem_idx
= 0, timeline_idx
= 0;
3842 if (num_sems
== 0 && _fence
== VK_NULL_HANDLE
)
3845 for (uint32_t i
= 0; i
< num_sems
; i
++) {
3846 switch(sems
[i
]->kind
) {
3847 case RADV_SEMAPHORE_SYNCOBJ
:
3848 counts
->syncobj_count
++;
3849 counts
->syncobj_reset_count
++;
3851 case RADV_SEMAPHORE_WINSYS
:
3852 counts
->sem_count
++;
3854 case RADV_SEMAPHORE_NONE
:
3856 case RADV_SEMAPHORE_TIMELINE
:
3857 counts
->syncobj_count
++;
3859 case RADV_SEMAPHORE_TIMELINE_SYNCOBJ
:
3860 counts
->timeline_syncobj_count
++;
3865 if (_fence
!= VK_NULL_HANDLE
) {
3866 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3868 struct radv_fence_part
*part
=
3869 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
3870 &fence
->temporary
: &fence
->permanent
;
3871 if (part
->kind
== RADV_FENCE_SYNCOBJ
)
3872 counts
->syncobj_count
++;
3875 if (counts
->syncobj_count
|| counts
->timeline_syncobj_count
) {
3876 counts
->points
= (uint64_t *)malloc(
3877 sizeof(*counts
->syncobj
) * counts
->syncobj_count
+
3878 (sizeof(*counts
->syncobj
) + sizeof(*counts
->points
)) * counts
->timeline_syncobj_count
);
3879 if (!counts
->points
)
3880 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3881 counts
->syncobj
= (uint32_t*)(counts
->points
+ counts
->timeline_syncobj_count
);
3884 if (counts
->sem_count
) {
3885 counts
->sem
= (struct radeon_winsys_sem
**)malloc(sizeof(struct radeon_winsys_sem
*) * counts
->sem_count
);
3887 free(counts
->syncobj
);
3888 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3892 non_reset_idx
= counts
->syncobj_reset_count
;
3894 for (uint32_t i
= 0; i
< num_sems
; i
++) {
3895 switch(sems
[i
]->kind
) {
3896 case RADV_SEMAPHORE_NONE
:
3897 unreachable("Empty semaphore");
3899 case RADV_SEMAPHORE_SYNCOBJ
:
3900 counts
->syncobj
[syncobj_idx
++] = sems
[i
]->syncobj
;
3902 case RADV_SEMAPHORE_WINSYS
:
3903 counts
->sem
[sem_idx
++] = sems
[i
]->ws_sem
;
3905 case RADV_SEMAPHORE_TIMELINE
: {
3906 pthread_mutex_lock(&sems
[i
]->timeline
.mutex
);
3907 struct radv_timeline_point
*point
= NULL
;
3909 point
= radv_timeline_add_point_locked(device
, &sems
[i
]->timeline
, timeline_values
[i
]);
3911 point
= radv_timeline_find_point_at_least_locked(device
, &sems
[i
]->timeline
, timeline_values
[i
]);
3914 pthread_mutex_unlock(&sems
[i
]->timeline
.mutex
);
3917 counts
->syncobj
[non_reset_idx
++] = point
->syncobj
;
3919 /* Explicitly remove the semaphore so we might not find
3920 * a point later post-submit. */
3925 case RADV_SEMAPHORE_TIMELINE_SYNCOBJ
:
3926 counts
->syncobj
[counts
->syncobj_count
+ timeline_idx
] = sems
[i
]->syncobj
;
3927 counts
->points
[timeline_idx
] = timeline_values
[i
];
3933 if (_fence
!= VK_NULL_HANDLE
) {
3934 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3936 struct radv_fence_part
*part
=
3937 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
3938 &fence
->temporary
: &fence
->permanent
;
3939 if (part
->kind
== RADV_FENCE_SYNCOBJ
)
3940 counts
->syncobj
[non_reset_idx
++] = part
->syncobj
;
3943 assert(MAX2(syncobj_idx
, non_reset_idx
) <= counts
->syncobj_count
);
3944 counts
->syncobj_count
= MAX2(syncobj_idx
, non_reset_idx
);
3950 radv_free_sem_info(struct radv_winsys_sem_info
*sem_info
)
3952 free(sem_info
->wait
.points
);
3953 free(sem_info
->wait
.sem
);
3954 free(sem_info
->signal
.points
);
3955 free(sem_info
->signal
.sem
);
3959 static void radv_free_temp_syncobjs(struct radv_device
*device
,
3961 struct radv_semaphore_part
*sems
)
3963 for (uint32_t i
= 0; i
< num_sems
; i
++) {
3964 radv_destroy_semaphore_part(device
, sems
+ i
);
3969 radv_alloc_sem_info(struct radv_device
*device
,
3970 struct radv_winsys_sem_info
*sem_info
,
3972 struct radv_semaphore_part
**wait_sems
,
3973 const uint64_t *wait_values
,
3974 int num_signal_sems
,
3975 struct radv_semaphore_part
**signal_sems
,
3976 const uint64_t *signal_values
,
3980 memset(sem_info
, 0, sizeof(*sem_info
));
3982 ret
= radv_alloc_sem_counts(device
, &sem_info
->wait
, num_wait_sems
, wait_sems
, wait_values
, VK_NULL_HANDLE
, false);
3985 ret
= radv_alloc_sem_counts(device
, &sem_info
->signal
, num_signal_sems
, signal_sems
, signal_values
, fence
, true);
3987 radv_free_sem_info(sem_info
);
3989 /* caller can override these */
3990 sem_info
->cs_emit_wait
= true;
3991 sem_info
->cs_emit_signal
= true;
3996 radv_finalize_timelines(struct radv_device
*device
,
3997 uint32_t num_wait_sems
,
3998 struct radv_semaphore_part
**wait_sems
,
3999 const uint64_t *wait_values
,
4000 uint32_t num_signal_sems
,
4001 struct radv_semaphore_part
**signal_sems
,
4002 const uint64_t *signal_values
,
4003 struct list_head
*processing_list
)
4005 for (uint32_t i
= 0; i
< num_wait_sems
; ++i
) {
4006 if (wait_sems
[i
] && wait_sems
[i
]->kind
== RADV_SEMAPHORE_TIMELINE
) {
4007 pthread_mutex_lock(&wait_sems
[i
]->timeline
.mutex
);
4008 struct radv_timeline_point
*point
=
4009 radv_timeline_find_point_at_least_locked(device
, &wait_sems
[i
]->timeline
, wait_values
[i
]);
4010 point
->wait_count
-= 2;
4011 pthread_mutex_unlock(&wait_sems
[i
]->timeline
.mutex
);
4014 for (uint32_t i
= 0; i
< num_signal_sems
; ++i
) {
4015 if (signal_sems
[i
] && signal_sems
[i
]->kind
== RADV_SEMAPHORE_TIMELINE
) {
4016 pthread_mutex_lock(&signal_sems
[i
]->timeline
.mutex
);
4017 struct radv_timeline_point
*point
=
4018 radv_timeline_find_point_at_least_locked(device
, &signal_sems
[i
]->timeline
, signal_values
[i
]);
4019 signal_sems
[i
]->timeline
.highest_submitted
=
4020 MAX2(signal_sems
[i
]->timeline
.highest_submitted
, point
->value
);
4021 point
->wait_count
-= 2;
4022 radv_timeline_trigger_waiters_locked(&signal_sems
[i
]->timeline
, processing_list
);
4023 pthread_mutex_unlock(&signal_sems
[i
]->timeline
.mutex
);
4024 } else if (signal_sems
[i
] && signal_sems
[i
]->kind
== RADV_SEMAPHORE_TIMELINE_SYNCOBJ
) {
4025 signal_sems
[i
]->timeline_syncobj
.max_point
=
4026 MAX2(signal_sems
[i
]->timeline_syncobj
.max_point
, signal_values
[i
]);
4032 radv_sparse_buffer_bind_memory(struct radv_device
*device
,
4033 const VkSparseBufferMemoryBindInfo
*bind
)
4035 RADV_FROM_HANDLE(radv_buffer
, buffer
, bind
->buffer
);
4038 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
4039 struct radv_device_memory
*mem
= NULL
;
4041 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
4042 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
4044 result
= device
->ws
->buffer_virtual_bind(buffer
->bo
,
4045 bind
->pBinds
[i
].resourceOffset
,
4046 bind
->pBinds
[i
].size
,
4047 mem
? mem
->bo
: NULL
,
4048 bind
->pBinds
[i
].memoryOffset
);
4049 if (result
!= VK_SUCCESS
)
4057 radv_sparse_image_opaque_bind_memory(struct radv_device
*device
,
4058 const VkSparseImageOpaqueMemoryBindInfo
*bind
)
4060 RADV_FROM_HANDLE(radv_image
, image
, bind
->image
);
4063 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
4064 struct radv_device_memory
*mem
= NULL
;
4066 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
4067 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
4069 result
= device
->ws
->buffer_virtual_bind(image
->bo
,
4070 bind
->pBinds
[i
].resourceOffset
,
4071 bind
->pBinds
[i
].size
,
4072 mem
? mem
->bo
: NULL
,
4073 bind
->pBinds
[i
].memoryOffset
);
4074 if (result
!= VK_SUCCESS
)
4082 radv_get_preambles(struct radv_queue
*queue
,
4083 const VkCommandBuffer
*cmd_buffers
,
4084 uint32_t cmd_buffer_count
,
4085 struct radeon_cmdbuf
**initial_full_flush_preamble_cs
,
4086 struct radeon_cmdbuf
**initial_preamble_cs
,
4087 struct radeon_cmdbuf
**continue_preamble_cs
)
4089 uint32_t scratch_size_per_wave
= 0, waves_wanted
= 0;
4090 uint32_t compute_scratch_size_per_wave
= 0, compute_waves_wanted
= 0;
4091 uint32_t esgs_ring_size
= 0, gsvs_ring_size
= 0;
4092 bool tess_rings_needed
= false;
4093 bool gds_needed
= false;
4094 bool gds_oa_needed
= false;
4095 bool sample_positions_needed
= false;
4097 for (uint32_t j
= 0; j
< cmd_buffer_count
; j
++) {
4098 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
4101 scratch_size_per_wave
= MAX2(scratch_size_per_wave
, cmd_buffer
->scratch_size_per_wave_needed
);
4102 waves_wanted
= MAX2(waves_wanted
, cmd_buffer
->scratch_waves_wanted
);
4103 compute_scratch_size_per_wave
= MAX2(compute_scratch_size_per_wave
,
4104 cmd_buffer
->compute_scratch_size_per_wave_needed
);
4105 compute_waves_wanted
= MAX2(compute_waves_wanted
,
4106 cmd_buffer
->compute_scratch_waves_wanted
);
4107 esgs_ring_size
= MAX2(esgs_ring_size
, cmd_buffer
->esgs_ring_size_needed
);
4108 gsvs_ring_size
= MAX2(gsvs_ring_size
, cmd_buffer
->gsvs_ring_size_needed
);
4109 tess_rings_needed
|= cmd_buffer
->tess_rings_needed
;
4110 gds_needed
|= cmd_buffer
->gds_needed
;
4111 gds_oa_needed
|= cmd_buffer
->gds_oa_needed
;
4112 sample_positions_needed
|= cmd_buffer
->sample_positions_needed
;
4115 return radv_get_preamble_cs(queue
, scratch_size_per_wave
, waves_wanted
,
4116 compute_scratch_size_per_wave
, compute_waves_wanted
,
4117 esgs_ring_size
, gsvs_ring_size
, tess_rings_needed
,
4118 gds_needed
, gds_oa_needed
, sample_positions_needed
,
4119 initial_full_flush_preamble_cs
,
4120 initial_preamble_cs
, continue_preamble_cs
);
4123 struct radv_deferred_queue_submission
{
4124 struct radv_queue
*queue
;
4125 VkCommandBuffer
*cmd_buffers
;
4126 uint32_t cmd_buffer_count
;
4128 /* Sparse bindings that happen on a queue. */
4129 VkSparseBufferMemoryBindInfo
*buffer_binds
;
4130 uint32_t buffer_bind_count
;
4131 VkSparseImageOpaqueMemoryBindInfo
*image_opaque_binds
;
4132 uint32_t image_opaque_bind_count
;
4135 VkShaderStageFlags wait_dst_stage_mask
;
4136 struct radv_semaphore_part
**wait_semaphores
;
4137 uint32_t wait_semaphore_count
;
4138 struct radv_semaphore_part
**signal_semaphores
;
4139 uint32_t signal_semaphore_count
;
4142 uint64_t *wait_values
;
4143 uint64_t *signal_values
;
4145 struct radv_semaphore_part
*temporary_semaphore_parts
;
4146 uint32_t temporary_semaphore_part_count
;
4148 struct list_head queue_pending_list
;
4149 uint32_t submission_wait_count
;
4150 struct radv_timeline_waiter
*wait_nodes
;
4152 struct list_head processing_list
;
4155 struct radv_queue_submission
{
4156 const VkCommandBuffer
*cmd_buffers
;
4157 uint32_t cmd_buffer_count
;
4159 /* Sparse bindings that happen on a queue. */
4160 const VkSparseBufferMemoryBindInfo
*buffer_binds
;
4161 uint32_t buffer_bind_count
;
4162 const VkSparseImageOpaqueMemoryBindInfo
*image_opaque_binds
;
4163 uint32_t image_opaque_bind_count
;
4166 VkPipelineStageFlags wait_dst_stage_mask
;
4167 const VkSemaphore
*wait_semaphores
;
4168 uint32_t wait_semaphore_count
;
4169 const VkSemaphore
*signal_semaphores
;
4170 uint32_t signal_semaphore_count
;
4173 const uint64_t *wait_values
;
4174 uint32_t wait_value_count
;
4175 const uint64_t *signal_values
;
4176 uint32_t signal_value_count
;
4180 radv_queue_trigger_submission(struct radv_deferred_queue_submission
*submission
,
4182 struct list_head
*processing_list
);
4185 radv_create_deferred_submission(struct radv_queue
*queue
,
4186 const struct radv_queue_submission
*submission
,
4187 struct radv_deferred_queue_submission
**out
)
4189 struct radv_deferred_queue_submission
*deferred
= NULL
;
4190 size_t size
= sizeof(struct radv_deferred_queue_submission
);
4192 uint32_t temporary_count
= 0;
4193 for (uint32_t i
= 0; i
< submission
->wait_semaphore_count
; ++i
) {
4194 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, submission
->wait_semaphores
[i
]);
4195 if (semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
)
4199 size
+= submission
->cmd_buffer_count
* sizeof(VkCommandBuffer
);
4200 size
+= submission
->buffer_bind_count
* sizeof(VkSparseBufferMemoryBindInfo
);
4201 size
+= submission
->image_opaque_bind_count
* sizeof(VkSparseImageOpaqueMemoryBindInfo
);
4202 size
+= submission
->wait_semaphore_count
* sizeof(struct radv_semaphore_part
*);
4203 size
+= temporary_count
* sizeof(struct radv_semaphore_part
);
4204 size
+= submission
->signal_semaphore_count
* sizeof(struct radv_semaphore_part
*);
4205 size
+= submission
->wait_value_count
* sizeof(uint64_t);
4206 size
+= submission
->signal_value_count
* sizeof(uint64_t);
4207 size
+= submission
->wait_semaphore_count
* sizeof(struct radv_timeline_waiter
);
4209 deferred
= calloc(1, size
);
4211 return VK_ERROR_OUT_OF_HOST_MEMORY
;
4213 deferred
->queue
= queue
;
4215 deferred
->cmd_buffers
= (void*)(deferred
+ 1);
4216 deferred
->cmd_buffer_count
= submission
->cmd_buffer_count
;
4217 memcpy(deferred
->cmd_buffers
, submission
->cmd_buffers
,
4218 submission
->cmd_buffer_count
* sizeof(*deferred
->cmd_buffers
));
4220 deferred
->buffer_binds
= (void*)(deferred
->cmd_buffers
+ submission
->cmd_buffer_count
);
4221 deferred
->buffer_bind_count
= submission
->buffer_bind_count
;
4222 memcpy(deferred
->buffer_binds
, submission
->buffer_binds
,
4223 submission
->buffer_bind_count
* sizeof(*deferred
->buffer_binds
));
4225 deferred
->image_opaque_binds
= (void*)(deferred
->buffer_binds
+ submission
->buffer_bind_count
);
4226 deferred
->image_opaque_bind_count
= submission
->image_opaque_bind_count
;
4227 memcpy(deferred
->image_opaque_binds
, submission
->image_opaque_binds
,
4228 submission
->image_opaque_bind_count
* sizeof(*deferred
->image_opaque_binds
));
4230 deferred
->flush_caches
= submission
->flush_caches
;
4231 deferred
->wait_dst_stage_mask
= submission
->wait_dst_stage_mask
;
4233 deferred
->wait_semaphores
= (void*)(deferred
->image_opaque_binds
+ deferred
->image_opaque_bind_count
);
4234 deferred
->wait_semaphore_count
= submission
->wait_semaphore_count
;
4236 deferred
->signal_semaphores
= (void*)(deferred
->wait_semaphores
+ deferred
->wait_semaphore_count
);
4237 deferred
->signal_semaphore_count
= submission
->signal_semaphore_count
;
4239 deferred
->fence
= submission
->fence
;
4241 deferred
->temporary_semaphore_parts
= (void*)(deferred
->signal_semaphores
+ deferred
->signal_semaphore_count
);
4242 deferred
->temporary_semaphore_part_count
= temporary_count
;
4244 uint32_t temporary_idx
= 0;
4245 for (uint32_t i
= 0; i
< submission
->wait_semaphore_count
; ++i
) {
4246 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, submission
->wait_semaphores
[i
]);
4247 if (semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
4248 deferred
->wait_semaphores
[i
] = &deferred
->temporary_semaphore_parts
[temporary_idx
];
4249 deferred
->temporary_semaphore_parts
[temporary_idx
] = semaphore
->temporary
;
4250 semaphore
->temporary
.kind
= RADV_SEMAPHORE_NONE
;
4253 deferred
->wait_semaphores
[i
] = &semaphore
->permanent
;
4256 for (uint32_t i
= 0; i
< submission
->signal_semaphore_count
; ++i
) {
4257 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, submission
->signal_semaphores
[i
]);
4258 if (semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
4259 deferred
->signal_semaphores
[i
] = &semaphore
->temporary
;
4261 deferred
->signal_semaphores
[i
] = &semaphore
->permanent
;
4265 deferred
->wait_values
= (void*)(deferred
->temporary_semaphore_parts
+ temporary_count
);
4266 memcpy(deferred
->wait_values
, submission
->wait_values
, submission
->wait_value_count
* sizeof(uint64_t));
4267 deferred
->signal_values
= deferred
->wait_values
+ submission
->wait_value_count
;
4268 memcpy(deferred
->signal_values
, submission
->signal_values
, submission
->signal_value_count
* sizeof(uint64_t));
4270 deferred
->wait_nodes
= (void*)(deferred
->signal_values
+ submission
->signal_value_count
);
4271 /* This is worst-case. radv_queue_enqueue_submission will fill in further, but this
4272 * ensure the submission is not accidentally triggered early when adding wait timelines. */
4273 deferred
->submission_wait_count
= 1 + submission
->wait_semaphore_count
;
4280 radv_queue_enqueue_submission(struct radv_deferred_queue_submission
*submission
,
4281 struct list_head
*processing_list
)
4283 uint32_t wait_cnt
= 0;
4284 struct radv_timeline_waiter
*waiter
= submission
->wait_nodes
;
4285 for (uint32_t i
= 0; i
< submission
->wait_semaphore_count
; ++i
) {
4286 if (submission
->wait_semaphores
[i
]->kind
== RADV_SEMAPHORE_TIMELINE
) {
4287 pthread_mutex_lock(&submission
->wait_semaphores
[i
]->timeline
.mutex
);
4288 if (submission
->wait_semaphores
[i
]->timeline
.highest_submitted
< submission
->wait_values
[i
]) {
4290 waiter
->value
= submission
->wait_values
[i
];
4291 waiter
->submission
= submission
;
4292 list_addtail(&waiter
->list
, &submission
->wait_semaphores
[i
]->timeline
.waiters
);
4295 pthread_mutex_unlock(&submission
->wait_semaphores
[i
]->timeline
.mutex
);
4299 pthread_mutex_lock(&submission
->queue
->pending_mutex
);
4301 bool is_first
= list_is_empty(&submission
->queue
->pending_submissions
);
4302 list_addtail(&submission
->queue_pending_list
, &submission
->queue
->pending_submissions
);
4304 pthread_mutex_unlock(&submission
->queue
->pending_mutex
);
4306 /* If there is already a submission in the queue, that will decrement the counter by 1 when
4307 * submitted, but if the queue was empty, we decrement ourselves as there is no previous
4309 uint32_t decrement
= submission
->wait_semaphore_count
- wait_cnt
+ (is_first
? 1 : 0);
4310 return radv_queue_trigger_submission(submission
, decrement
, processing_list
);
4314 radv_queue_submission_update_queue(struct radv_deferred_queue_submission
*submission
,
4315 struct list_head
*processing_list
)
4317 pthread_mutex_lock(&submission
->queue
->pending_mutex
);
4318 list_del(&submission
->queue_pending_list
);
4320 /* trigger the next submission in the queue. */
4321 if (!list_is_empty(&submission
->queue
->pending_submissions
)) {
4322 struct radv_deferred_queue_submission
*next_submission
=
4323 list_first_entry(&submission
->queue
->pending_submissions
,
4324 struct radv_deferred_queue_submission
,
4325 queue_pending_list
);
4326 radv_queue_trigger_submission(next_submission
, 1, processing_list
);
4328 pthread_mutex_unlock(&submission
->queue
->pending_mutex
);
4330 pthread_cond_broadcast(&submission
->queue
->device
->timeline_cond
);
4334 radv_queue_submit_deferred(struct radv_deferred_queue_submission
*submission
,
4335 struct list_head
*processing_list
)
4337 RADV_FROM_HANDLE(radv_fence
, fence
, submission
->fence
);
4338 struct radv_queue
*queue
= submission
->queue
;
4339 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
4340 uint32_t max_cs_submission
= queue
->device
->trace_bo
? 1 : RADV_MAX_IBS_PER_SUBMIT
;
4341 struct radeon_winsys_fence
*base_fence
= NULL
;
4342 bool do_flush
= submission
->flush_caches
|| submission
->wait_dst_stage_mask
;
4343 bool can_patch
= true;
4345 struct radv_winsys_sem_info sem_info
;
4347 struct radeon_cmdbuf
*initial_preamble_cs
= NULL
;
4348 struct radeon_cmdbuf
*initial_flush_preamble_cs
= NULL
;
4349 struct radeon_cmdbuf
*continue_preamble_cs
= NULL
;
4352 /* Under most circumstances, out fences won't be temporary.
4353 * However, the spec does allow it for opaque_fd.
4355 * From the Vulkan 1.0.53 spec:
4357 * "If the import is temporary, the implementation must
4358 * restore the semaphore to its prior permanent state after
4359 * submitting the next semaphore wait operation."
4361 struct radv_fence_part
*part
=
4362 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
4363 &fence
->temporary
: &fence
->permanent
;
4364 if (part
->kind
== RADV_FENCE_WINSYS
)
4365 base_fence
= part
->fence
;
4368 result
= radv_get_preambles(queue
, submission
->cmd_buffers
,
4369 submission
->cmd_buffer_count
,
4370 &initial_preamble_cs
,
4371 &initial_flush_preamble_cs
,
4372 &continue_preamble_cs
);
4373 if (result
!= VK_SUCCESS
)
4376 result
= radv_alloc_sem_info(queue
->device
,
4378 submission
->wait_semaphore_count
,
4379 submission
->wait_semaphores
,
4380 submission
->wait_values
,
4381 submission
->signal_semaphore_count
,
4382 submission
->signal_semaphores
,
4383 submission
->signal_values
,
4385 if (result
!= VK_SUCCESS
)
4388 for (uint32_t i
= 0; i
< submission
->buffer_bind_count
; ++i
) {
4389 result
= radv_sparse_buffer_bind_memory(queue
->device
,
4390 submission
->buffer_binds
+ i
);
4391 if (result
!= VK_SUCCESS
)
4395 for (uint32_t i
= 0; i
< submission
->image_opaque_bind_count
; ++i
) {
4396 result
= radv_sparse_image_opaque_bind_memory(queue
->device
,
4397 submission
->image_opaque_binds
+ i
);
4398 if (result
!= VK_SUCCESS
)
4402 if (!submission
->cmd_buffer_count
) {
4403 result
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
4404 &queue
->device
->empty_cs
[queue
->queue_family_index
],
4408 if (result
!= VK_SUCCESS
)
4411 struct radeon_cmdbuf
**cs_array
= malloc(sizeof(struct radeon_cmdbuf
*) *
4412 (submission
->cmd_buffer_count
));
4414 for (uint32_t j
= 0; j
< submission
->cmd_buffer_count
; j
++) {
4415 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, submission
->cmd_buffers
[j
]);
4416 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
4418 cs_array
[j
] = cmd_buffer
->cs
;
4419 if ((cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT
))
4422 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_PENDING
;
4425 for (uint32_t j
= 0; j
< submission
->cmd_buffer_count
; j
+= advance
) {
4426 struct radeon_cmdbuf
*initial_preamble
= (do_flush
&& !j
) ? initial_flush_preamble_cs
: initial_preamble_cs
;
4427 const struct radv_winsys_bo_list
*bo_list
= NULL
;
4429 advance
= MIN2(max_cs_submission
,
4430 submission
->cmd_buffer_count
- j
);
4432 if (queue
->device
->trace_bo
)
4433 *queue
->device
->trace_id_ptr
= 0;
4435 sem_info
.cs_emit_wait
= j
== 0;
4436 sem_info
.cs_emit_signal
= j
+ advance
== submission
->cmd_buffer_count
;
4438 if (unlikely(queue
->device
->use_global_bo_list
)) {
4439 pthread_mutex_lock(&queue
->device
->bo_list
.mutex
);
4440 bo_list
= &queue
->device
->bo_list
.list
;
4443 result
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, cs_array
+ j
,
4444 advance
, initial_preamble
, continue_preamble_cs
,
4446 can_patch
, base_fence
);
4448 if (unlikely(queue
->device
->use_global_bo_list
))
4449 pthread_mutex_unlock(&queue
->device
->bo_list
.mutex
);
4451 if (result
!= VK_SUCCESS
)
4454 if (queue
->device
->trace_bo
) {
4455 radv_check_gpu_hangs(queue
, cs_array
[j
]);
4462 radv_free_temp_syncobjs(queue
->device
,
4463 submission
->temporary_semaphore_part_count
,
4464 submission
->temporary_semaphore_parts
);
4465 radv_finalize_timelines(queue
->device
,
4466 submission
->wait_semaphore_count
,
4467 submission
->wait_semaphores
,
4468 submission
->wait_values
,
4469 submission
->signal_semaphore_count
,
4470 submission
->signal_semaphores
,
4471 submission
->signal_values
,
4473 /* Has to happen after timeline finalization to make sure the
4474 * condition variable is only triggered when timelines and queue have
4476 radv_queue_submission_update_queue(submission
, processing_list
);
4477 radv_free_sem_info(&sem_info
);
4482 if (result
!= VK_SUCCESS
&& result
!= VK_ERROR_DEVICE_LOST
) {
4483 /* When something bad happened during the submission, such as
4484 * an out of memory issue, it might be hard to recover from
4485 * this inconsistent state. To avoid this sort of problem, we
4486 * assume that we are in a really bad situation and return
4487 * VK_ERROR_DEVICE_LOST to ensure the clients do not attempt
4488 * to submit the same job again to this device.
4490 result
= VK_ERROR_DEVICE_LOST
;
4493 radv_free_temp_syncobjs(queue
->device
,
4494 submission
->temporary_semaphore_part_count
,
4495 submission
->temporary_semaphore_parts
);
4501 radv_process_submissions(struct list_head
*processing_list
)
4503 while(!list_is_empty(processing_list
)) {
4504 struct radv_deferred_queue_submission
*submission
=
4505 list_first_entry(processing_list
, struct radv_deferred_queue_submission
, processing_list
);
4506 list_del(&submission
->processing_list
);
4508 VkResult result
= radv_queue_submit_deferred(submission
, processing_list
);
4509 if (result
!= VK_SUCCESS
)
4516 wait_for_submission_timelines_available(struct radv_deferred_queue_submission
*submission
,
4519 struct radv_device
*device
= submission
->queue
->device
;
4520 uint32_t syncobj_count
= 0;
4521 uint32_t syncobj_idx
= 0;
4523 for (uint32_t i
= 0; i
< submission
->wait_semaphore_count
; ++i
) {
4524 if (submission
->wait_semaphores
[i
]->kind
!= RADV_SEMAPHORE_TIMELINE_SYNCOBJ
)
4527 if (submission
->wait_semaphores
[i
]->timeline_syncobj
.max_point
>= submission
->wait_values
[i
])
4535 uint64_t *points
= malloc((sizeof(uint64_t) + sizeof(uint32_t)) * syncobj_count
);
4537 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4539 uint32_t *syncobj
= (uint32_t*)(points
+ syncobj_count
);
4541 for (uint32_t i
= 0; i
< submission
->wait_semaphore_count
; ++i
) {
4542 if (submission
->wait_semaphores
[i
]->kind
!= RADV_SEMAPHORE_TIMELINE_SYNCOBJ
)
4545 if (submission
->wait_semaphores
[i
]->timeline_syncobj
.max_point
>= submission
->wait_values
[i
])
4548 syncobj
[syncobj_idx
] = submission
->wait_semaphores
[i
]->syncobj
;
4549 points
[syncobj_idx
] = submission
->wait_values
[i
];
4552 bool success
= device
->ws
->wait_timeline_syncobj(device
->ws
, syncobj
, points
, syncobj_idx
, true, true, timeout
);
4555 return success
? VK_SUCCESS
: VK_TIMEOUT
;
4558 static void* radv_queue_submission_thread_run(void *q
)
4560 struct radv_queue
*queue
= q
;
4562 pthread_mutex_lock(&queue
->thread_mutex
);
4563 while (!p_atomic_read(&queue
->thread_exit
)) {
4564 struct radv_deferred_queue_submission
*submission
= queue
->thread_submission
;
4565 struct list_head processing_list
;
4566 VkResult result
= VK_SUCCESS
;
4568 pthread_cond_wait(&queue
->thread_cond
, &queue
->thread_mutex
);
4571 pthread_mutex_unlock(&queue
->thread_mutex
);
4573 /* Wait at most 5 seconds so we have a chance to notice shutdown when
4574 * a semaphore never gets signaled. If it takes longer we just retry
4575 * the wait next iteration. */
4576 result
= wait_for_submission_timelines_available(submission
,
4577 radv_get_absolute_timeout(5000000000));
4578 if (result
!= VK_SUCCESS
) {
4579 pthread_mutex_lock(&queue
->thread_mutex
);
4583 /* The lock isn't held but nobody will add one until we finish
4584 * the current submission. */
4585 p_atomic_set(&queue
->thread_submission
, NULL
);
4587 list_inithead(&processing_list
);
4588 list_addtail(&submission
->processing_list
, &processing_list
);
4589 result
= radv_process_submissions(&processing_list
);
4591 pthread_mutex_lock(&queue
->thread_mutex
);
4593 pthread_mutex_unlock(&queue
->thread_mutex
);
4598 radv_queue_trigger_submission(struct radv_deferred_queue_submission
*submission
,
4600 struct list_head
*processing_list
)
4602 struct radv_queue
*queue
= submission
->queue
;
4604 if (p_atomic_add_return(&submission
->submission_wait_count
, -decrement
))
4607 if (wait_for_submission_timelines_available(submission
, radv_get_absolute_timeout(0)) == VK_SUCCESS
) {
4608 list_addtail(&submission
->processing_list
, processing_list
);
4612 pthread_mutex_lock(&queue
->thread_mutex
);
4614 /* A submission can only be ready for the thread if it doesn't have
4615 * any predecessors in the same queue, so there can only be one such
4616 * submission at a time. */
4617 assert(queue
->thread_submission
== NULL
);
4619 /* Only start the thread on demand to save resources for the many games
4620 * which only use binary semaphores. */
4621 if (!queue
->thread_running
) {
4622 ret
= pthread_create(&queue
->submission_thread
, NULL
,
4623 radv_queue_submission_thread_run
, queue
);
4625 pthread_mutex_unlock(&queue
->thread_mutex
);
4626 return vk_errorf(queue
->device
->instance
,
4627 VK_ERROR_DEVICE_LOST
,
4628 "Failed to start submission thread");
4630 queue
->thread_running
= true;
4633 queue
->thread_submission
= submission
;
4634 pthread_mutex_unlock(&queue
->thread_mutex
);
4636 pthread_cond_signal(&queue
->thread_cond
);
4640 static VkResult
radv_queue_submit(struct radv_queue
*queue
,
4641 const struct radv_queue_submission
*submission
)
4643 struct radv_deferred_queue_submission
*deferred
= NULL
;
4645 VkResult result
= radv_create_deferred_submission(queue
, submission
, &deferred
);
4646 if (result
!= VK_SUCCESS
)
4649 struct list_head processing_list
;
4650 list_inithead(&processing_list
);
4652 result
= radv_queue_enqueue_submission(deferred
, &processing_list
);
4653 if (result
!= VK_SUCCESS
) {
4654 /* If anything is in the list we leak. */
4655 assert(list_is_empty(&processing_list
));
4658 return radv_process_submissions(&processing_list
);
4662 radv_queue_internal_submit(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
)
4664 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
4665 struct radv_winsys_sem_info sem_info
;
4668 result
= radv_alloc_sem_info(queue
->device
, &sem_info
, 0, NULL
, 0, 0,
4669 0, NULL
, VK_NULL_HANDLE
);
4670 if (result
!= VK_SUCCESS
)
4673 result
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, &cs
, 1,
4674 NULL
, NULL
, &sem_info
, NULL
,
4676 radv_free_sem_info(&sem_info
);
4677 if (result
!= VK_SUCCESS
)
4684 /* Signals fence as soon as all the work currently put on queue is done. */
4685 static VkResult
radv_signal_fence(struct radv_queue
*queue
,
4688 return radv_queue_submit(queue
, &(struct radv_queue_submission
) {
4693 static bool radv_submit_has_effects(const VkSubmitInfo
*info
)
4695 return info
->commandBufferCount
||
4696 info
->waitSemaphoreCount
||
4697 info
->signalSemaphoreCount
;
4700 VkResult
radv_QueueSubmit(
4702 uint32_t submitCount
,
4703 const VkSubmitInfo
* pSubmits
,
4706 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
4708 uint32_t fence_idx
= 0;
4709 bool flushed_caches
= false;
4711 if (fence
!= VK_NULL_HANDLE
) {
4712 for (uint32_t i
= 0; i
< submitCount
; ++i
)
4713 if (radv_submit_has_effects(pSubmits
+ i
))
4716 fence_idx
= UINT32_MAX
;
4718 for (uint32_t i
= 0; i
< submitCount
; i
++) {
4719 if (!radv_submit_has_effects(pSubmits
+ i
) && fence_idx
!= i
)
4722 VkPipelineStageFlags wait_dst_stage_mask
= 0;
4723 for (unsigned j
= 0; j
< pSubmits
[i
].waitSemaphoreCount
; ++j
) {
4724 wait_dst_stage_mask
|= pSubmits
[i
].pWaitDstStageMask
[j
];
4727 const VkTimelineSemaphoreSubmitInfo
*timeline_info
=
4728 vk_find_struct_const(pSubmits
[i
].pNext
, TIMELINE_SEMAPHORE_SUBMIT_INFO
);
4730 result
= radv_queue_submit(queue
, &(struct radv_queue_submission
) {
4731 .cmd_buffers
= pSubmits
[i
].pCommandBuffers
,
4732 .cmd_buffer_count
= pSubmits
[i
].commandBufferCount
,
4733 .wait_dst_stage_mask
= wait_dst_stage_mask
,
4734 .flush_caches
= !flushed_caches
,
4735 .wait_semaphores
= pSubmits
[i
].pWaitSemaphores
,
4736 .wait_semaphore_count
= pSubmits
[i
].waitSemaphoreCount
,
4737 .signal_semaphores
= pSubmits
[i
].pSignalSemaphores
,
4738 .signal_semaphore_count
= pSubmits
[i
].signalSemaphoreCount
,
4739 .fence
= i
== fence_idx
? fence
: VK_NULL_HANDLE
,
4740 .wait_values
= timeline_info
? timeline_info
->pWaitSemaphoreValues
: NULL
,
4741 .wait_value_count
= timeline_info
&& timeline_info
->pWaitSemaphoreValues
? timeline_info
->waitSemaphoreValueCount
: 0,
4742 .signal_values
= timeline_info
? timeline_info
->pSignalSemaphoreValues
: NULL
,
4743 .signal_value_count
= timeline_info
&& timeline_info
->pSignalSemaphoreValues
? timeline_info
->signalSemaphoreValueCount
: 0,
4745 if (result
!= VK_SUCCESS
)
4748 flushed_caches
= true;
4751 if (fence
!= VK_NULL_HANDLE
&& !submitCount
) {
4752 result
= radv_signal_fence(queue
, fence
);
4753 if (result
!= VK_SUCCESS
)
4761 radv_get_queue_family_name(struct radv_queue
*queue
)
4763 switch (queue
->queue_family_index
) {
4764 case RADV_QUEUE_GENERAL
:
4766 case RADV_QUEUE_COMPUTE
:
4768 case RADV_QUEUE_TRANSFER
:
4771 unreachable("Unknown queue family");
4775 VkResult
radv_QueueWaitIdle(
4778 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
4780 pthread_mutex_lock(&queue
->pending_mutex
);
4781 while (!list_is_empty(&queue
->pending_submissions
)) {
4782 pthread_cond_wait(&queue
->device
->timeline_cond
, &queue
->pending_mutex
);
4784 pthread_mutex_unlock(&queue
->pending_mutex
);
4786 if (!queue
->device
->ws
->ctx_wait_idle(queue
->hw_ctx
,
4787 radv_queue_family_to_ring(queue
->queue_family_index
),
4788 queue
->queue_idx
)) {
4789 return vk_errorf(queue
->device
->instance
, VK_ERROR_DEVICE_LOST
,
4790 "Failed to wait for a '%s' queue to be idle. "
4791 "GPU hang ?", radv_get_queue_family_name(queue
));
4797 VkResult
radv_DeviceWaitIdle(
4800 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4802 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
4803 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++) {
4805 radv_QueueWaitIdle(radv_queue_to_handle(&device
->queues
[i
][q
]));
4807 if (result
!= VK_SUCCESS
)
4814 VkResult
radv_EnumerateInstanceExtensionProperties(
4815 const char* pLayerName
,
4816 uint32_t* pPropertyCount
,
4817 VkExtensionProperties
* pProperties
)
4819 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
4821 for (int i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; i
++) {
4822 if (radv_instance_extensions_supported
.extensions
[i
]) {
4823 vk_outarray_append(&out
, prop
) {
4824 *prop
= radv_instance_extensions
[i
];
4829 return vk_outarray_status(&out
);
4832 VkResult
radv_EnumerateDeviceExtensionProperties(
4833 VkPhysicalDevice physicalDevice
,
4834 const char* pLayerName
,
4835 uint32_t* pPropertyCount
,
4836 VkExtensionProperties
* pProperties
)
4838 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
4839 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
4841 for (int i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; i
++) {
4842 if (device
->supported_extensions
.extensions
[i
]) {
4843 vk_outarray_append(&out
, prop
) {
4844 *prop
= radv_device_extensions
[i
];
4849 return vk_outarray_status(&out
);
4852 PFN_vkVoidFunction
radv_GetInstanceProcAddr(
4853 VkInstance _instance
,
4856 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
4858 /* The Vulkan 1.0 spec for vkGetInstanceProcAddr has a table of exactly
4859 * when we have to return valid function pointers, NULL, or it's left
4860 * undefined. See the table for exact details.
4865 #define LOOKUP_RADV_ENTRYPOINT(entrypoint) \
4866 if (strcmp(pName, "vk" #entrypoint) == 0) \
4867 return (PFN_vkVoidFunction)radv_##entrypoint
4869 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceExtensionProperties
);
4870 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceLayerProperties
);
4871 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceVersion
);
4872 LOOKUP_RADV_ENTRYPOINT(CreateInstance
);
4874 /* GetInstanceProcAddr() can also be called with a NULL instance.
4875 * See https://gitlab.khronos.org/vulkan/vulkan/issues/2057
4877 LOOKUP_RADV_ENTRYPOINT(GetInstanceProcAddr
);
4879 #undef LOOKUP_RADV_ENTRYPOINT
4881 if (instance
== NULL
)
4884 int idx
= radv_get_instance_entrypoint_index(pName
);
4886 return instance
->dispatch
.entrypoints
[idx
];
4888 idx
= radv_get_physical_device_entrypoint_index(pName
);
4890 return instance
->physical_device_dispatch
.entrypoints
[idx
];
4892 idx
= radv_get_device_entrypoint_index(pName
);
4894 return instance
->device_dispatch
.entrypoints
[idx
];
4899 /* The loader wants us to expose a second GetInstanceProcAddr function
4900 * to work around certain LD_PRELOAD issues seen in apps.
4903 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
4904 VkInstance instance
,
4908 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
4909 VkInstance instance
,
4912 return radv_GetInstanceProcAddr(instance
, pName
);
4916 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
4917 VkInstance _instance
,
4921 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
4922 VkInstance _instance
,
4925 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
4927 if (!pName
|| !instance
)
4930 int idx
= radv_get_physical_device_entrypoint_index(pName
);
4934 return instance
->physical_device_dispatch
.entrypoints
[idx
];
4937 PFN_vkVoidFunction
radv_GetDeviceProcAddr(
4941 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4943 if (!device
|| !pName
)
4946 int idx
= radv_get_device_entrypoint_index(pName
);
4950 return device
->dispatch
.entrypoints
[idx
];
4953 bool radv_get_memory_fd(struct radv_device
*device
,
4954 struct radv_device_memory
*memory
,
4957 struct radeon_bo_metadata metadata
;
4959 if (memory
->image
) {
4960 if (memory
->image
->tiling
!= VK_IMAGE_TILING_LINEAR
)
4961 radv_init_metadata(device
, memory
->image
, &metadata
);
4962 device
->ws
->buffer_set_metadata(memory
->bo
, &metadata
);
4965 return device
->ws
->buffer_get_fd(device
->ws
, memory
->bo
,
4971 radv_free_memory(struct radv_device
*device
,
4972 const VkAllocationCallbacks
* pAllocator
,
4973 struct radv_device_memory
*mem
)
4978 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
4979 if (mem
->android_hardware_buffer
)
4980 AHardwareBuffer_release(mem
->android_hardware_buffer
);
4984 if (device
->overallocation_disallowed
) {
4985 mtx_lock(&device
->overallocation_mutex
);
4986 device
->allocated_memory_size
[mem
->heap_index
] -= mem
->alloc_size
;
4987 mtx_unlock(&device
->overallocation_mutex
);
4990 radv_bo_list_remove(device
, mem
->bo
);
4991 device
->ws
->buffer_destroy(mem
->bo
);
4995 vk_object_base_finish(&mem
->base
);
4996 vk_free2(&device
->vk
.alloc
, pAllocator
, mem
);
4999 static VkResult
radv_alloc_memory(struct radv_device
*device
,
5000 const VkMemoryAllocateInfo
* pAllocateInfo
,
5001 const VkAllocationCallbacks
* pAllocator
,
5002 VkDeviceMemory
* pMem
)
5004 struct radv_device_memory
*mem
;
5006 enum radeon_bo_domain domain
;
5009 assert(pAllocateInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO
);
5011 const VkImportMemoryFdInfoKHR
*import_info
=
5012 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_FD_INFO_KHR
);
5013 const VkMemoryDedicatedAllocateInfo
*dedicate_info
=
5014 vk_find_struct_const(pAllocateInfo
->pNext
, MEMORY_DEDICATED_ALLOCATE_INFO
);
5015 const VkExportMemoryAllocateInfo
*export_info
=
5016 vk_find_struct_const(pAllocateInfo
->pNext
, EXPORT_MEMORY_ALLOCATE_INFO
);
5017 const struct VkImportAndroidHardwareBufferInfoANDROID
*ahb_import_info
=
5018 vk_find_struct_const(pAllocateInfo
->pNext
,
5019 IMPORT_ANDROID_HARDWARE_BUFFER_INFO_ANDROID
);
5020 const VkImportMemoryHostPointerInfoEXT
*host_ptr_info
=
5021 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_HOST_POINTER_INFO_EXT
);
5023 const struct wsi_memory_allocate_info
*wsi_info
=
5024 vk_find_struct_const(pAllocateInfo
->pNext
, WSI_MEMORY_ALLOCATE_INFO_MESA
);
5026 if (pAllocateInfo
->allocationSize
== 0 && !ahb_import_info
&&
5027 !(export_info
&& (export_info
->handleTypes
& VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID
))) {
5028 /* Apparently, this is allowed */
5029 *pMem
= VK_NULL_HANDLE
;
5033 mem
= vk_zalloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*mem
), 8,
5034 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5036 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5038 vk_object_base_init(&device
->vk
, &mem
->base
,
5039 VK_OBJECT_TYPE_DEVICE_MEMORY
);
5041 if (wsi_info
&& wsi_info
->implicit_sync
)
5042 flags
|= RADEON_FLAG_IMPLICIT_SYNC
;
5044 if (dedicate_info
) {
5045 mem
->image
= radv_image_from_handle(dedicate_info
->image
);
5046 mem
->buffer
= radv_buffer_from_handle(dedicate_info
->buffer
);
5052 float priority_float
= 0.5;
5053 const struct VkMemoryPriorityAllocateInfoEXT
*priority_ext
=
5054 vk_find_struct_const(pAllocateInfo
->pNext
,
5055 MEMORY_PRIORITY_ALLOCATE_INFO_EXT
);
5057 priority_float
= priority_ext
->priority
;
5059 unsigned priority
= MIN2(RADV_BO_PRIORITY_APPLICATION_MAX
- 1,
5060 (int)(priority_float
* RADV_BO_PRIORITY_APPLICATION_MAX
));
5062 mem
->user_ptr
= NULL
;
5065 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
5066 mem
->android_hardware_buffer
= NULL
;
5069 if (ahb_import_info
) {
5070 result
= radv_import_ahb_memory(device
, mem
, priority
, ahb_import_info
);
5071 if (result
!= VK_SUCCESS
)
5073 } else if(export_info
&& (export_info
->handleTypes
& VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID
)) {
5074 result
= radv_create_ahb_memory(device
, mem
, priority
, pAllocateInfo
);
5075 if (result
!= VK_SUCCESS
)
5077 } else if (import_info
) {
5078 assert(import_info
->handleType
==
5079 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
5080 import_info
->handleType
==
5081 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
5082 mem
->bo
= device
->ws
->buffer_from_fd(device
->ws
, import_info
->fd
,
5085 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
5088 close(import_info
->fd
);
5091 if (mem
->image
&& mem
->image
->plane_count
== 1 &&
5092 !vk_format_is_depth_or_stencil(mem
->image
->vk_format
)) {
5093 struct radeon_bo_metadata metadata
;
5094 device
->ws
->buffer_get_metadata(mem
->bo
, &metadata
);
5096 struct radv_image_create_info create_info
= {
5097 .no_metadata_planes
= true,
5098 .bo_metadata
= &metadata
5101 /* This gives a basic ability to import radeonsi images
5102 * that don't have DCC. This is not guaranteed by any
5103 * spec and can be removed after we support modifiers. */
5104 result
= radv_image_create_layout(device
, create_info
, mem
->image
);
5105 if (result
!= VK_SUCCESS
) {
5106 device
->ws
->buffer_destroy(mem
->bo
);
5110 } else if (host_ptr_info
) {
5111 assert(host_ptr_info
->handleType
== VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
);
5112 mem
->bo
= device
->ws
->buffer_from_ptr(device
->ws
, host_ptr_info
->pHostPointer
,
5113 pAllocateInfo
->allocationSize
,
5116 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
5119 mem
->user_ptr
= host_ptr_info
->pHostPointer
;
5122 uint64_t alloc_size
= align_u64(pAllocateInfo
->allocationSize
, 4096);
5123 uint32_t heap_index
;
5125 heap_index
= device
->physical_device
->memory_properties
.memoryTypes
[pAllocateInfo
->memoryTypeIndex
].heapIndex
;
5126 domain
= device
->physical_device
->memory_domains
[pAllocateInfo
->memoryTypeIndex
];
5127 flags
|= device
->physical_device
->memory_flags
[pAllocateInfo
->memoryTypeIndex
];
5129 if (!dedicate_info
&& !import_info
&& (!export_info
|| !export_info
->handleTypes
)) {
5130 flags
|= RADEON_FLAG_NO_INTERPROCESS_SHARING
;
5131 if (device
->use_global_bo_list
) {
5132 flags
|= RADEON_FLAG_PREFER_LOCAL_BO
;
5136 if (device
->overallocation_disallowed
) {
5137 uint64_t total_size
=
5138 device
->physical_device
->memory_properties
.memoryHeaps
[heap_index
].size
;
5140 mtx_lock(&device
->overallocation_mutex
);
5141 if (device
->allocated_memory_size
[heap_index
] + alloc_size
> total_size
) {
5142 mtx_unlock(&device
->overallocation_mutex
);
5143 result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
5146 device
->allocated_memory_size
[heap_index
] += alloc_size
;
5147 mtx_unlock(&device
->overallocation_mutex
);
5150 mem
->bo
= device
->ws
->buffer_create(device
->ws
, alloc_size
, device
->physical_device
->rad_info
.max_alignment
,
5151 domain
, flags
, priority
);
5154 if (device
->overallocation_disallowed
) {
5155 mtx_lock(&device
->overallocation_mutex
);
5156 device
->allocated_memory_size
[heap_index
] -= alloc_size
;
5157 mtx_unlock(&device
->overallocation_mutex
);
5159 result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
5163 mem
->heap_index
= heap_index
;
5164 mem
->alloc_size
= alloc_size
;
5168 result
= radv_bo_list_add(device
, mem
->bo
);
5169 if (result
!= VK_SUCCESS
)
5173 *pMem
= radv_device_memory_to_handle(mem
);
5178 radv_free_memory(device
, pAllocator
,mem
);
5183 VkResult
radv_AllocateMemory(
5185 const VkMemoryAllocateInfo
* pAllocateInfo
,
5186 const VkAllocationCallbacks
* pAllocator
,
5187 VkDeviceMemory
* pMem
)
5189 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5190 return radv_alloc_memory(device
, pAllocateInfo
, pAllocator
, pMem
);
5193 void radv_FreeMemory(
5195 VkDeviceMemory _mem
,
5196 const VkAllocationCallbacks
* pAllocator
)
5198 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5199 RADV_FROM_HANDLE(radv_device_memory
, mem
, _mem
);
5201 radv_free_memory(device
, pAllocator
, mem
);
5204 VkResult
radv_MapMemory(
5206 VkDeviceMemory _memory
,
5207 VkDeviceSize offset
,
5209 VkMemoryMapFlags flags
,
5212 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5213 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
5221 *ppData
= mem
->user_ptr
;
5223 *ppData
= device
->ws
->buffer_map(mem
->bo
);
5230 return vk_error(device
->instance
, VK_ERROR_MEMORY_MAP_FAILED
);
5233 void radv_UnmapMemory(
5235 VkDeviceMemory _memory
)
5237 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5238 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
5243 if (mem
->user_ptr
== NULL
)
5244 device
->ws
->buffer_unmap(mem
->bo
);
5247 VkResult
radv_FlushMappedMemoryRanges(
5249 uint32_t memoryRangeCount
,
5250 const VkMappedMemoryRange
* pMemoryRanges
)
5255 VkResult
radv_InvalidateMappedMemoryRanges(
5257 uint32_t memoryRangeCount
,
5258 const VkMappedMemoryRange
* pMemoryRanges
)
5263 void radv_GetBufferMemoryRequirements(
5266 VkMemoryRequirements
* pMemoryRequirements
)
5268 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5269 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
5271 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
5273 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
5274 pMemoryRequirements
->alignment
= 4096;
5276 pMemoryRequirements
->alignment
= 16;
5278 pMemoryRequirements
->size
= align64(buffer
->size
, pMemoryRequirements
->alignment
);
5281 void radv_GetBufferMemoryRequirements2(
5283 const VkBufferMemoryRequirementsInfo2
*pInfo
,
5284 VkMemoryRequirements2
*pMemoryRequirements
)
5286 radv_GetBufferMemoryRequirements(device
, pInfo
->buffer
,
5287 &pMemoryRequirements
->memoryRequirements
);
5288 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
5289 switch (ext
->sType
) {
5290 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
5291 VkMemoryDedicatedRequirements
*req
=
5292 (VkMemoryDedicatedRequirements
*) ext
;
5293 req
->requiresDedicatedAllocation
= false;
5294 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
5303 void radv_GetImageMemoryRequirements(
5306 VkMemoryRequirements
* pMemoryRequirements
)
5308 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5309 RADV_FROM_HANDLE(radv_image
, image
, _image
);
5311 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
5313 pMemoryRequirements
->size
= image
->size
;
5314 pMemoryRequirements
->alignment
= image
->alignment
;
5317 void radv_GetImageMemoryRequirements2(
5319 const VkImageMemoryRequirementsInfo2
*pInfo
,
5320 VkMemoryRequirements2
*pMemoryRequirements
)
5322 radv_GetImageMemoryRequirements(device
, pInfo
->image
,
5323 &pMemoryRequirements
->memoryRequirements
);
5325 RADV_FROM_HANDLE(radv_image
, image
, pInfo
->image
);
5327 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
5328 switch (ext
->sType
) {
5329 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
5330 VkMemoryDedicatedRequirements
*req
=
5331 (VkMemoryDedicatedRequirements
*) ext
;
5332 req
->requiresDedicatedAllocation
= image
->shareable
&&
5333 image
->tiling
!= VK_IMAGE_TILING_LINEAR
;
5334 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
5343 void radv_GetImageSparseMemoryRequirements(
5346 uint32_t* pSparseMemoryRequirementCount
,
5347 VkSparseImageMemoryRequirements
* pSparseMemoryRequirements
)
5352 void radv_GetImageSparseMemoryRequirements2(
5354 const VkImageSparseMemoryRequirementsInfo2
*pInfo
,
5355 uint32_t* pSparseMemoryRequirementCount
,
5356 VkSparseImageMemoryRequirements2
*pSparseMemoryRequirements
)
5361 void radv_GetDeviceMemoryCommitment(
5363 VkDeviceMemory memory
,
5364 VkDeviceSize
* pCommittedMemoryInBytes
)
5366 *pCommittedMemoryInBytes
= 0;
5369 VkResult
radv_BindBufferMemory2(VkDevice device
,
5370 uint32_t bindInfoCount
,
5371 const VkBindBufferMemoryInfo
*pBindInfos
)
5373 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
5374 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
5375 RADV_FROM_HANDLE(radv_buffer
, buffer
, pBindInfos
[i
].buffer
);
5378 buffer
->bo
= mem
->bo
;
5379 buffer
->offset
= pBindInfos
[i
].memoryOffset
;
5387 VkResult
radv_BindBufferMemory(
5390 VkDeviceMemory memory
,
5391 VkDeviceSize memoryOffset
)
5393 const VkBindBufferMemoryInfo info
= {
5394 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
5397 .memoryOffset
= memoryOffset
5400 return radv_BindBufferMemory2(device
, 1, &info
);
5403 VkResult
radv_BindImageMemory2(VkDevice device
,
5404 uint32_t bindInfoCount
,
5405 const VkBindImageMemoryInfo
*pBindInfos
)
5407 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
5408 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
5409 RADV_FROM_HANDLE(radv_image
, image
, pBindInfos
[i
].image
);
5412 image
->bo
= mem
->bo
;
5413 image
->offset
= pBindInfos
[i
].memoryOffset
;
5423 VkResult
radv_BindImageMemory(
5426 VkDeviceMemory memory
,
5427 VkDeviceSize memoryOffset
)
5429 const VkBindImageMemoryInfo info
= {
5430 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
5433 .memoryOffset
= memoryOffset
5436 return radv_BindImageMemory2(device
, 1, &info
);
5439 static bool radv_sparse_bind_has_effects(const VkBindSparseInfo
*info
)
5441 return info
->bufferBindCount
||
5442 info
->imageOpaqueBindCount
||
5443 info
->imageBindCount
||
5444 info
->waitSemaphoreCount
||
5445 info
->signalSemaphoreCount
;
5448 VkResult
radv_QueueBindSparse(
5450 uint32_t bindInfoCount
,
5451 const VkBindSparseInfo
* pBindInfo
,
5454 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
5456 uint32_t fence_idx
= 0;
5458 if (fence
!= VK_NULL_HANDLE
) {
5459 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
)
5460 if (radv_sparse_bind_has_effects(pBindInfo
+ i
))
5463 fence_idx
= UINT32_MAX
;
5465 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
5466 if (i
!= fence_idx
&& !radv_sparse_bind_has_effects(pBindInfo
+ i
))
5469 const VkTimelineSemaphoreSubmitInfo
*timeline_info
=
5470 vk_find_struct_const(pBindInfo
[i
].pNext
, TIMELINE_SEMAPHORE_SUBMIT_INFO
);
5472 VkResult result
= radv_queue_submit(queue
, &(struct radv_queue_submission
) {
5473 .buffer_binds
= pBindInfo
[i
].pBufferBinds
,
5474 .buffer_bind_count
= pBindInfo
[i
].bufferBindCount
,
5475 .image_opaque_binds
= pBindInfo
[i
].pImageOpaqueBinds
,
5476 .image_opaque_bind_count
= pBindInfo
[i
].imageOpaqueBindCount
,
5477 .wait_semaphores
= pBindInfo
[i
].pWaitSemaphores
,
5478 .wait_semaphore_count
= pBindInfo
[i
].waitSemaphoreCount
,
5479 .signal_semaphores
= pBindInfo
[i
].pSignalSemaphores
,
5480 .signal_semaphore_count
= pBindInfo
[i
].signalSemaphoreCount
,
5481 .fence
= i
== fence_idx
? fence
: VK_NULL_HANDLE
,
5482 .wait_values
= timeline_info
? timeline_info
->pWaitSemaphoreValues
: NULL
,
5483 .wait_value_count
= timeline_info
&& timeline_info
->pWaitSemaphoreValues
? timeline_info
->waitSemaphoreValueCount
: 0,
5484 .signal_values
= timeline_info
? timeline_info
->pSignalSemaphoreValues
: NULL
,
5485 .signal_value_count
= timeline_info
&& timeline_info
->pSignalSemaphoreValues
? timeline_info
->signalSemaphoreValueCount
: 0,
5488 if (result
!= VK_SUCCESS
)
5492 if (fence
!= VK_NULL_HANDLE
&& !bindInfoCount
) {
5493 result
= radv_signal_fence(queue
, fence
);
5494 if (result
!= VK_SUCCESS
)
5502 radv_destroy_fence_part(struct radv_device
*device
,
5503 struct radv_fence_part
*part
)
5505 switch (part
->kind
) {
5506 case RADV_FENCE_NONE
:
5508 case RADV_FENCE_WINSYS
:
5509 device
->ws
->destroy_fence(part
->fence
);
5511 case RADV_FENCE_SYNCOBJ
:
5512 device
->ws
->destroy_syncobj(device
->ws
, part
->syncobj
);
5514 case RADV_FENCE_WSI
:
5515 part
->fence_wsi
->destroy(part
->fence_wsi
);
5518 unreachable("Invalid fence type");
5521 part
->kind
= RADV_FENCE_NONE
;
5525 radv_destroy_fence(struct radv_device
*device
,
5526 const VkAllocationCallbacks
*pAllocator
,
5527 struct radv_fence
*fence
)
5529 radv_destroy_fence_part(device
, &fence
->temporary
);
5530 radv_destroy_fence_part(device
, &fence
->permanent
);
5532 vk_object_base_finish(&fence
->base
);
5533 vk_free2(&device
->vk
.alloc
, pAllocator
, fence
);
5536 VkResult
radv_CreateFence(
5538 const VkFenceCreateInfo
* pCreateInfo
,
5539 const VkAllocationCallbacks
* pAllocator
,
5542 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5543 const VkExportFenceCreateInfo
*export
=
5544 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_FENCE_CREATE_INFO
);
5545 VkExternalFenceHandleTypeFlags handleTypes
=
5546 export
? export
->handleTypes
: 0;
5547 struct radv_fence
*fence
;
5549 fence
= vk_zalloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*fence
), 8,
5550 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5552 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5554 vk_object_base_init(&device
->vk
, &fence
->base
, VK_OBJECT_TYPE_FENCE
);
5556 if (device
->always_use_syncobj
|| handleTypes
) {
5557 fence
->permanent
.kind
= RADV_FENCE_SYNCOBJ
;
5559 bool create_signaled
= false;
5560 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
)
5561 create_signaled
= true;
5563 int ret
= device
->ws
->create_syncobj(device
->ws
, create_signaled
,
5564 &fence
->permanent
.syncobj
);
5566 radv_destroy_fence(device
, pAllocator
, fence
);
5567 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5570 fence
->permanent
.kind
= RADV_FENCE_WINSYS
;
5572 fence
->permanent
.fence
= device
->ws
->create_fence();
5573 if (!fence
->permanent
.fence
) {
5574 vk_free2(&device
->vk
.alloc
, pAllocator
, fence
);
5575 radv_destroy_fence(device
, pAllocator
, fence
);
5576 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5578 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
)
5579 device
->ws
->signal_fence(fence
->permanent
.fence
);
5582 *pFence
= radv_fence_to_handle(fence
);
5588 void radv_DestroyFence(
5591 const VkAllocationCallbacks
* pAllocator
)
5593 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5594 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
5599 radv_destroy_fence(device
, pAllocator
, fence
);
5602 static bool radv_all_fences_plain_and_submitted(struct radv_device
*device
,
5603 uint32_t fenceCount
, const VkFence
*pFences
)
5605 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5606 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5608 struct radv_fence_part
*part
=
5609 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
5610 &fence
->temporary
: &fence
->permanent
;
5611 if (part
->kind
!= RADV_FENCE_WINSYS
||
5612 !device
->ws
->is_fence_waitable(part
->fence
))
5618 static bool radv_all_fences_syncobj(uint32_t fenceCount
, const VkFence
*pFences
)
5620 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5621 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5623 struct radv_fence_part
*part
=
5624 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
5625 &fence
->temporary
: &fence
->permanent
;
5626 if (part
->kind
!= RADV_FENCE_SYNCOBJ
)
5632 VkResult
radv_WaitForFences(
5634 uint32_t fenceCount
,
5635 const VkFence
* pFences
,
5639 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5640 timeout
= radv_get_absolute_timeout(timeout
);
5642 if (device
->always_use_syncobj
&&
5643 radv_all_fences_syncobj(fenceCount
, pFences
))
5645 uint32_t *handles
= malloc(sizeof(uint32_t) * fenceCount
);
5647 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5649 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5650 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5652 struct radv_fence_part
*part
=
5653 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
5654 &fence
->temporary
: &fence
->permanent
;
5656 assert(part
->kind
== RADV_FENCE_SYNCOBJ
);
5657 handles
[i
] = part
->syncobj
;
5660 bool success
= device
->ws
->wait_syncobj(device
->ws
, handles
, fenceCount
, waitAll
, timeout
);
5663 return success
? VK_SUCCESS
: VK_TIMEOUT
;
5666 if (!waitAll
&& fenceCount
> 1) {
5667 /* Not doing this by default for waitAll, due to needing to allocate twice. */
5668 if (device
->physical_device
->rad_info
.drm_minor
>= 10 && radv_all_fences_plain_and_submitted(device
, fenceCount
, pFences
)) {
5669 uint32_t wait_count
= 0;
5670 struct radeon_winsys_fence
**fences
= malloc(sizeof(struct radeon_winsys_fence
*) * fenceCount
);
5672 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5674 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5675 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5677 struct radv_fence_part
*part
=
5678 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
5679 &fence
->temporary
: &fence
->permanent
;
5680 assert(part
->kind
== RADV_FENCE_WINSYS
);
5682 if (device
->ws
->fence_wait(device
->ws
, part
->fence
, false, 0)) {
5687 fences
[wait_count
++] = part
->fence
;
5690 bool success
= device
->ws
->fences_wait(device
->ws
, fences
, wait_count
,
5691 waitAll
, timeout
- radv_get_current_time());
5694 return success
? VK_SUCCESS
: VK_TIMEOUT
;
5697 while(radv_get_current_time() <= timeout
) {
5698 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5699 if (radv_GetFenceStatus(_device
, pFences
[i
]) == VK_SUCCESS
)
5706 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5707 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5708 bool expired
= false;
5710 struct radv_fence_part
*part
=
5711 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
5712 &fence
->temporary
: &fence
->permanent
;
5714 switch (part
->kind
) {
5715 case RADV_FENCE_NONE
:
5717 case RADV_FENCE_WINSYS
:
5718 if (!device
->ws
->is_fence_waitable(part
->fence
)) {
5719 while (!device
->ws
->is_fence_waitable(part
->fence
) &&
5720 radv_get_current_time() <= timeout
)
5724 expired
= device
->ws
->fence_wait(device
->ws
,
5730 case RADV_FENCE_SYNCOBJ
:
5731 if (!device
->ws
->wait_syncobj(device
->ws
,
5732 &part
->syncobj
, 1, true,
5736 case RADV_FENCE_WSI
: {
5737 VkResult result
= part
->fence_wsi
->wait(part
->fence_wsi
, timeout
);
5738 if (result
!= VK_SUCCESS
)
5743 unreachable("Invalid fence type");
5750 VkResult
radv_ResetFences(VkDevice _device
,
5751 uint32_t fenceCount
,
5752 const VkFence
*pFences
)
5754 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5756 for (unsigned i
= 0; i
< fenceCount
; ++i
) {
5757 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5759 /* From the Vulkan 1.0.53 spec:
5761 * "If any member of pFences currently has its payload
5762 * imported with temporary permanence, that fence’s prior
5763 * permanent payload is irst restored. The remaining
5764 * operations described therefore operate on the restored
5767 if (fence
->temporary
.kind
!= RADV_FENCE_NONE
)
5768 radv_destroy_fence_part(device
, &fence
->temporary
);
5770 struct radv_fence_part
*part
= &fence
->permanent
;
5772 switch (part
->kind
) {
5773 case RADV_FENCE_WSI
:
5774 device
->ws
->reset_fence(part
->fence
);
5776 case RADV_FENCE_SYNCOBJ
:
5777 device
->ws
->reset_syncobj(device
->ws
, part
->syncobj
);
5780 unreachable("Invalid fence type");
5787 VkResult
radv_GetFenceStatus(VkDevice _device
, VkFence _fence
)
5789 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5790 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
5792 struct radv_fence_part
*part
=
5793 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
5794 &fence
->temporary
: &fence
->permanent
;
5796 switch (part
->kind
) {
5797 case RADV_FENCE_NONE
:
5799 case RADV_FENCE_WINSYS
:
5800 if (!device
->ws
->fence_wait(device
->ws
, part
->fence
, false, 0))
5801 return VK_NOT_READY
;
5803 case RADV_FENCE_SYNCOBJ
: {
5804 bool success
= device
->ws
->wait_syncobj(device
->ws
,
5805 &part
->syncobj
, 1, true, 0);
5807 return VK_NOT_READY
;
5810 case RADV_FENCE_WSI
: {
5811 VkResult result
= part
->fence_wsi
->wait(part
->fence_wsi
, 0);
5812 if (result
!= VK_SUCCESS
) {
5813 if (result
== VK_TIMEOUT
)
5814 return VK_NOT_READY
;
5820 unreachable("Invalid fence type");
5827 // Queue semaphore functions
5830 radv_create_timeline(struct radv_timeline
*timeline
, uint64_t value
)
5832 timeline
->highest_signaled
= value
;
5833 timeline
->highest_submitted
= value
;
5834 list_inithead(&timeline
->points
);
5835 list_inithead(&timeline
->free_points
);
5836 list_inithead(&timeline
->waiters
);
5837 pthread_mutex_init(&timeline
->mutex
, NULL
);
5841 radv_destroy_timeline(struct radv_device
*device
,
5842 struct radv_timeline
*timeline
)
5844 list_for_each_entry_safe(struct radv_timeline_point
, point
,
5845 &timeline
->free_points
, list
) {
5846 list_del(&point
->list
);
5847 device
->ws
->destroy_syncobj(device
->ws
, point
->syncobj
);
5850 list_for_each_entry_safe(struct radv_timeline_point
, point
,
5851 &timeline
->points
, list
) {
5852 list_del(&point
->list
);
5853 device
->ws
->destroy_syncobj(device
->ws
, point
->syncobj
);
5856 pthread_mutex_destroy(&timeline
->mutex
);
5860 radv_timeline_gc_locked(struct radv_device
*device
,
5861 struct radv_timeline
*timeline
)
5863 list_for_each_entry_safe(struct radv_timeline_point
, point
,
5864 &timeline
->points
, list
) {
5865 if (point
->wait_count
|| point
->value
> timeline
->highest_submitted
)
5868 if (device
->ws
->wait_syncobj(device
->ws
, &point
->syncobj
, 1, true, 0)) {
5869 timeline
->highest_signaled
= point
->value
;
5870 list_del(&point
->list
);
5871 list_add(&point
->list
, &timeline
->free_points
);
5876 static struct radv_timeline_point
*
5877 radv_timeline_find_point_at_least_locked(struct radv_device
*device
,
5878 struct radv_timeline
*timeline
,
5881 radv_timeline_gc_locked(device
, timeline
);
5883 if (p
<= timeline
->highest_signaled
)
5886 list_for_each_entry(struct radv_timeline_point
, point
,
5887 &timeline
->points
, list
) {
5888 if (point
->value
>= p
) {
5889 ++point
->wait_count
;
5896 static struct radv_timeline_point
*
5897 radv_timeline_add_point_locked(struct radv_device
*device
,
5898 struct radv_timeline
*timeline
,
5901 radv_timeline_gc_locked(device
, timeline
);
5903 struct radv_timeline_point
*ret
= NULL
;
5904 struct radv_timeline_point
*prev
= NULL
;
5907 if (p
<= timeline
->highest_signaled
)
5910 list_for_each_entry(struct radv_timeline_point
, point
,
5911 &timeline
->points
, list
) {
5912 if (point
->value
== p
) {
5916 if (point
->value
< p
)
5920 if (list_is_empty(&timeline
->free_points
)) {
5921 ret
= malloc(sizeof(struct radv_timeline_point
));
5922 r
= device
->ws
->create_syncobj(device
->ws
, false, &ret
->syncobj
);
5928 ret
= list_first_entry(&timeline
->free_points
, struct radv_timeline_point
, list
);
5929 list_del(&ret
->list
);
5931 device
->ws
->reset_syncobj(device
->ws
, ret
->syncobj
);
5935 ret
->wait_count
= 1;
5938 list_add(&ret
->list
, &prev
->list
);
5940 list_addtail(&ret
->list
, &timeline
->points
);
5947 radv_timeline_wait(struct radv_device
*device
,
5948 struct radv_timeline
*timeline
,
5950 uint64_t abs_timeout
)
5952 pthread_mutex_lock(&timeline
->mutex
);
5954 while(timeline
->highest_submitted
< value
) {
5955 struct timespec abstime
;
5956 timespec_from_nsec(&abstime
, abs_timeout
);
5958 pthread_cond_timedwait(&device
->timeline_cond
, &timeline
->mutex
, &abstime
);
5960 if (radv_get_current_time() >= abs_timeout
&& timeline
->highest_submitted
< value
) {
5961 pthread_mutex_unlock(&timeline
->mutex
);
5966 struct radv_timeline_point
*point
= radv_timeline_find_point_at_least_locked(device
, timeline
, value
);
5967 pthread_mutex_unlock(&timeline
->mutex
);
5971 bool success
= device
->ws
->wait_syncobj(device
->ws
, &point
->syncobj
, 1, true, abs_timeout
);
5973 pthread_mutex_lock(&timeline
->mutex
);
5974 point
->wait_count
--;
5975 pthread_mutex_unlock(&timeline
->mutex
);
5976 return success
? VK_SUCCESS
: VK_TIMEOUT
;
5980 radv_timeline_trigger_waiters_locked(struct radv_timeline
*timeline
,
5981 struct list_head
*processing_list
)
5983 list_for_each_entry_safe(struct radv_timeline_waiter
, waiter
,
5984 &timeline
->waiters
, list
) {
5985 if (waiter
->value
> timeline
->highest_submitted
)
5988 radv_queue_trigger_submission(waiter
->submission
, 1, processing_list
);
5989 list_del(&waiter
->list
);
5994 void radv_destroy_semaphore_part(struct radv_device
*device
,
5995 struct radv_semaphore_part
*part
)
5997 switch(part
->kind
) {
5998 case RADV_SEMAPHORE_NONE
:
6000 case RADV_SEMAPHORE_WINSYS
:
6001 device
->ws
->destroy_sem(part
->ws_sem
);
6003 case RADV_SEMAPHORE_TIMELINE
:
6004 radv_destroy_timeline(device
, &part
->timeline
);
6006 case RADV_SEMAPHORE_SYNCOBJ
:
6007 case RADV_SEMAPHORE_TIMELINE_SYNCOBJ
:
6008 device
->ws
->destroy_syncobj(device
->ws
, part
->syncobj
);
6011 part
->kind
= RADV_SEMAPHORE_NONE
;
6014 static VkSemaphoreTypeKHR
6015 radv_get_semaphore_type(const void *pNext
, uint64_t *initial_value
)
6017 const VkSemaphoreTypeCreateInfo
*type_info
=
6018 vk_find_struct_const(pNext
, SEMAPHORE_TYPE_CREATE_INFO
);
6021 return VK_SEMAPHORE_TYPE_BINARY
;
6024 *initial_value
= type_info
->initialValue
;
6025 return type_info
->semaphoreType
;
6029 radv_destroy_semaphore(struct radv_device
*device
,
6030 const VkAllocationCallbacks
*pAllocator
,
6031 struct radv_semaphore
*sem
)
6033 radv_destroy_semaphore_part(device
, &sem
->temporary
);
6034 radv_destroy_semaphore_part(device
, &sem
->permanent
);
6035 vk_object_base_finish(&sem
->base
);
6036 vk_free2(&device
->vk
.alloc
, pAllocator
, sem
);
6039 VkResult
radv_CreateSemaphore(
6041 const VkSemaphoreCreateInfo
* pCreateInfo
,
6042 const VkAllocationCallbacks
* pAllocator
,
6043 VkSemaphore
* pSemaphore
)
6045 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6046 const VkExportSemaphoreCreateInfo
*export
=
6047 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_SEMAPHORE_CREATE_INFO
);
6048 VkExternalSemaphoreHandleTypeFlags handleTypes
=
6049 export
? export
->handleTypes
: 0;
6050 uint64_t initial_value
= 0;
6051 VkSemaphoreTypeKHR type
= radv_get_semaphore_type(pCreateInfo
->pNext
, &initial_value
);
6053 struct radv_semaphore
*sem
= vk_alloc2(&device
->vk
.alloc
, pAllocator
,
6055 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
6057 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6059 vk_object_base_init(&device
->vk
, &sem
->base
,
6060 VK_OBJECT_TYPE_SEMAPHORE
);
6062 sem
->temporary
.kind
= RADV_SEMAPHORE_NONE
;
6063 sem
->permanent
.kind
= RADV_SEMAPHORE_NONE
;
6065 if (type
== VK_SEMAPHORE_TYPE_TIMELINE
&&
6066 device
->physical_device
->rad_info
.has_timeline_syncobj
) {
6067 int ret
= device
->ws
->create_syncobj(device
->ws
, false, &sem
->permanent
.syncobj
);
6069 radv_destroy_semaphore(device
, pAllocator
, sem
);
6070 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6072 device
->ws
->signal_syncobj(device
->ws
, sem
->permanent
.syncobj
, initial_value
);
6073 sem
->permanent
.timeline_syncobj
.max_point
= initial_value
;
6074 sem
->permanent
.kind
= RADV_SEMAPHORE_TIMELINE_SYNCOBJ
;
6075 } else if (type
== VK_SEMAPHORE_TYPE_TIMELINE
) {
6076 radv_create_timeline(&sem
->permanent
.timeline
, initial_value
);
6077 sem
->permanent
.kind
= RADV_SEMAPHORE_TIMELINE
;
6078 } else if (device
->always_use_syncobj
|| handleTypes
) {
6079 assert (device
->physical_device
->rad_info
.has_syncobj
);
6080 int ret
= device
->ws
->create_syncobj(device
->ws
, false,
6081 &sem
->permanent
.syncobj
);
6083 radv_destroy_semaphore(device
, pAllocator
, sem
);
6084 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6086 sem
->permanent
.kind
= RADV_SEMAPHORE_SYNCOBJ
;
6088 sem
->permanent
.ws_sem
= device
->ws
->create_sem(device
->ws
);
6089 if (!sem
->permanent
.ws_sem
) {
6090 radv_destroy_semaphore(device
, pAllocator
, sem
);
6091 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6093 sem
->permanent
.kind
= RADV_SEMAPHORE_WINSYS
;
6096 *pSemaphore
= radv_semaphore_to_handle(sem
);
6100 void radv_DestroySemaphore(
6102 VkSemaphore _semaphore
,
6103 const VkAllocationCallbacks
* pAllocator
)
6105 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6106 RADV_FROM_HANDLE(radv_semaphore
, sem
, _semaphore
);
6110 radv_destroy_semaphore(device
, pAllocator
, sem
);
6114 radv_GetSemaphoreCounterValue(VkDevice _device
,
6115 VkSemaphore _semaphore
,
6118 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6119 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, _semaphore
);
6121 struct radv_semaphore_part
*part
=
6122 semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
? &semaphore
->temporary
: &semaphore
->permanent
;
6124 switch (part
->kind
) {
6125 case RADV_SEMAPHORE_TIMELINE
: {
6126 pthread_mutex_lock(&part
->timeline
.mutex
);
6127 radv_timeline_gc_locked(device
, &part
->timeline
);
6128 *pValue
= part
->timeline
.highest_signaled
;
6129 pthread_mutex_unlock(&part
->timeline
.mutex
);
6132 case RADV_SEMAPHORE_TIMELINE_SYNCOBJ
: {
6133 return device
->ws
->query_syncobj(device
->ws
, part
->syncobj
, pValue
);
6135 case RADV_SEMAPHORE_NONE
:
6136 case RADV_SEMAPHORE_SYNCOBJ
:
6137 case RADV_SEMAPHORE_WINSYS
:
6138 unreachable("Invalid semaphore type");
6140 unreachable("Unhandled semaphore type");
6145 radv_wait_timelines(struct radv_device
*device
,
6146 const VkSemaphoreWaitInfo
* pWaitInfo
,
6147 uint64_t abs_timeout
)
6149 if ((pWaitInfo
->flags
& VK_SEMAPHORE_WAIT_ANY_BIT_KHR
) && pWaitInfo
->semaphoreCount
> 1) {
6151 for(uint32_t i
= 0; i
< pWaitInfo
->semaphoreCount
; ++i
) {
6152 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, pWaitInfo
->pSemaphores
[i
]);
6153 VkResult result
= radv_timeline_wait(device
, &semaphore
->permanent
.timeline
, pWaitInfo
->pValues
[i
], 0);
6155 if (result
== VK_SUCCESS
)
6158 if (radv_get_current_time() > abs_timeout
)
6163 for(uint32_t i
= 0; i
< pWaitInfo
->semaphoreCount
; ++i
) {
6164 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, pWaitInfo
->pSemaphores
[i
]);
6165 VkResult result
= radv_timeline_wait(device
, &semaphore
->permanent
.timeline
, pWaitInfo
->pValues
[i
], abs_timeout
);
6167 if (result
!= VK_SUCCESS
)
6173 radv_WaitSemaphores(VkDevice _device
,
6174 const VkSemaphoreWaitInfo
* pWaitInfo
,
6177 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6178 uint64_t abs_timeout
= radv_get_absolute_timeout(timeout
);
6180 if (radv_semaphore_from_handle(pWaitInfo
->pSemaphores
[0])->permanent
.kind
== RADV_SEMAPHORE_TIMELINE
)
6181 return radv_wait_timelines(device
, pWaitInfo
, abs_timeout
);
6183 if (pWaitInfo
->semaphoreCount
> UINT32_MAX
/ sizeof(uint32_t))
6184 return vk_errorf(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
, "semaphoreCount integer overflow");
6186 bool wait_all
= !(pWaitInfo
->flags
& VK_SEMAPHORE_WAIT_ANY_BIT_KHR
);
6187 uint32_t *handles
= malloc(sizeof(*handles
) * pWaitInfo
->semaphoreCount
);
6189 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6191 for (uint32_t i
= 0; i
< pWaitInfo
->semaphoreCount
; ++i
) {
6192 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, pWaitInfo
->pSemaphores
[i
]);
6193 handles
[i
] = semaphore
->permanent
.syncobj
;
6196 bool success
= device
->ws
->wait_timeline_syncobj(device
->ws
, handles
, pWaitInfo
->pValues
,
6197 pWaitInfo
->semaphoreCount
, wait_all
, false,
6200 return success
? VK_SUCCESS
: VK_TIMEOUT
;
6204 radv_SignalSemaphore(VkDevice _device
,
6205 const VkSemaphoreSignalInfo
* pSignalInfo
)
6207 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6208 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, pSignalInfo
->semaphore
);
6210 struct radv_semaphore_part
*part
=
6211 semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
? &semaphore
->temporary
: &semaphore
->permanent
;
6213 switch(part
->kind
) {
6214 case RADV_SEMAPHORE_TIMELINE
: {
6215 pthread_mutex_lock(&part
->timeline
.mutex
);
6216 radv_timeline_gc_locked(device
, &part
->timeline
);
6217 part
->timeline
.highest_submitted
= MAX2(part
->timeline
.highest_submitted
, pSignalInfo
->value
);
6218 part
->timeline
.highest_signaled
= MAX2(part
->timeline
.highest_signaled
, pSignalInfo
->value
);
6220 struct list_head processing_list
;
6221 list_inithead(&processing_list
);
6222 radv_timeline_trigger_waiters_locked(&part
->timeline
, &processing_list
);
6223 pthread_mutex_unlock(&part
->timeline
.mutex
);
6225 VkResult result
= radv_process_submissions(&processing_list
);
6227 /* This needs to happen after radv_process_submissions, so
6228 * that any submitted submissions that are now unblocked get
6229 * processed before we wake the application. This way we
6230 * ensure that any binary semaphores that are now unblocked
6231 * are usable by the application. */
6232 pthread_cond_broadcast(&device
->timeline_cond
);
6236 case RADV_SEMAPHORE_TIMELINE_SYNCOBJ
: {
6237 part
->timeline_syncobj
.max_point
= MAX2(part
->timeline_syncobj
.max_point
, pSignalInfo
->value
);
6238 device
->ws
->signal_syncobj(device
->ws
, part
->syncobj
, pSignalInfo
->value
);
6241 case RADV_SEMAPHORE_NONE
:
6242 case RADV_SEMAPHORE_SYNCOBJ
:
6243 case RADV_SEMAPHORE_WINSYS
:
6244 unreachable("Invalid semaphore type");
6249 static void radv_destroy_event(struct radv_device
*device
,
6250 const VkAllocationCallbacks
* pAllocator
,
6251 struct radv_event
*event
)
6254 device
->ws
->buffer_destroy(event
->bo
);
6256 vk_object_base_finish(&event
->base
);
6257 vk_free2(&device
->vk
.alloc
, pAllocator
, event
);
6260 VkResult
radv_CreateEvent(
6262 const VkEventCreateInfo
* pCreateInfo
,
6263 const VkAllocationCallbacks
* pAllocator
,
6266 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6267 struct radv_event
*event
= vk_alloc2(&device
->vk
.alloc
, pAllocator
,
6269 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
6272 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6274 vk_object_base_init(&device
->vk
, &event
->base
, VK_OBJECT_TYPE_EVENT
);
6276 event
->bo
= device
->ws
->buffer_create(device
->ws
, 8, 8,
6278 RADEON_FLAG_VA_UNCACHED
| RADEON_FLAG_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
,
6279 RADV_BO_PRIORITY_FENCE
);
6281 radv_destroy_event(device
, pAllocator
, event
);
6282 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
6285 event
->map
= (uint64_t*)device
->ws
->buffer_map(event
->bo
);
6287 radv_destroy_event(device
, pAllocator
, event
);
6288 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
6291 *pEvent
= radv_event_to_handle(event
);
6296 void radv_DestroyEvent(
6299 const VkAllocationCallbacks
* pAllocator
)
6301 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6302 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6307 radv_destroy_event(device
, pAllocator
, event
);
6310 VkResult
radv_GetEventStatus(
6314 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6316 if (*event
->map
== 1)
6317 return VK_EVENT_SET
;
6318 return VK_EVENT_RESET
;
6321 VkResult
radv_SetEvent(
6325 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6331 VkResult
radv_ResetEvent(
6335 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6342 radv_destroy_buffer(struct radv_device
*device
,
6343 const VkAllocationCallbacks
*pAllocator
,
6344 struct radv_buffer
*buffer
)
6346 if ((buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
) && buffer
->bo
)
6347 device
->ws
->buffer_destroy(buffer
->bo
);
6349 vk_object_base_finish(&buffer
->base
);
6350 vk_free2(&device
->vk
.alloc
, pAllocator
, buffer
);
6353 VkResult
radv_CreateBuffer(
6355 const VkBufferCreateInfo
* pCreateInfo
,
6356 const VkAllocationCallbacks
* pAllocator
,
6359 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6360 struct radv_buffer
*buffer
;
6362 if (pCreateInfo
->size
> RADV_MAX_MEMORY_ALLOCATION_SIZE
)
6363 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
6365 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO
);
6367 buffer
= vk_alloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*buffer
), 8,
6368 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
6370 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6372 vk_object_base_init(&device
->vk
, &buffer
->base
, VK_OBJECT_TYPE_BUFFER
);
6374 buffer
->size
= pCreateInfo
->size
;
6375 buffer
->usage
= pCreateInfo
->usage
;
6378 buffer
->flags
= pCreateInfo
->flags
;
6380 buffer
->shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
6381 EXTERNAL_MEMORY_BUFFER_CREATE_INFO
) != NULL
;
6383 if (pCreateInfo
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
) {
6384 buffer
->bo
= device
->ws
->buffer_create(device
->ws
,
6385 align64(buffer
->size
, 4096),
6386 4096, 0, RADEON_FLAG_VIRTUAL
,
6387 RADV_BO_PRIORITY_VIRTUAL
);
6389 radv_destroy_buffer(device
, pAllocator
, buffer
);
6390 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
6394 *pBuffer
= radv_buffer_to_handle(buffer
);
6399 void radv_DestroyBuffer(
6402 const VkAllocationCallbacks
* pAllocator
)
6404 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6405 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
6410 radv_destroy_buffer(device
, pAllocator
, buffer
);
6413 VkDeviceAddress
radv_GetBufferDeviceAddress(
6415 const VkBufferDeviceAddressInfo
* pInfo
)
6417 RADV_FROM_HANDLE(radv_buffer
, buffer
, pInfo
->buffer
);
6418 return radv_buffer_get_va(buffer
->bo
) + buffer
->offset
;
6422 uint64_t radv_GetBufferOpaqueCaptureAddress(VkDevice device
,
6423 const VkBufferDeviceAddressInfo
* pInfo
)
6428 uint64_t radv_GetDeviceMemoryOpaqueCaptureAddress(VkDevice device
,
6429 const VkDeviceMemoryOpaqueCaptureAddressInfo
* pInfo
)
6434 static inline unsigned
6435 si_tile_mode_index(const struct radv_image_plane
*plane
, unsigned level
, bool stencil
)
6438 return plane
->surface
.u
.legacy
.stencil_tiling_index
[level
];
6440 return plane
->surface
.u
.legacy
.tiling_index
[level
];
6443 static uint32_t radv_surface_max_layer_count(struct radv_image_view
*iview
)
6445 return iview
->type
== VK_IMAGE_VIEW_TYPE_3D
? iview
->extent
.depth
: (iview
->base_layer
+ iview
->layer_count
);
6449 radv_init_dcc_control_reg(struct radv_device
*device
,
6450 struct radv_image_view
*iview
)
6452 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
6453 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
6454 unsigned max_compressed_block_size
;
6455 unsigned independent_128b_blocks
;
6456 unsigned independent_64b_blocks
;
6458 if (!radv_dcc_enabled(iview
->image
, iview
->base_mip
))
6461 if (!device
->physical_device
->rad_info
.has_dedicated_vram
) {
6462 /* amdvlk: [min-compressed-block-size] should be set to 32 for
6463 * dGPU and 64 for APU because all of our APUs to date use
6464 * DIMMs which have a request granularity size of 64B while all
6465 * other chips have a 32B request size.
6467 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
6470 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6471 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
6472 independent_64b_blocks
= 0;
6473 independent_128b_blocks
= 1;
6475 independent_128b_blocks
= 0;
6477 if (iview
->image
->info
.samples
> 1) {
6478 if (iview
->image
->planes
[0].surface
.bpe
== 1)
6479 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
6480 else if (iview
->image
->planes
[0].surface
.bpe
== 2)
6481 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
6484 if (iview
->image
->usage
& (VK_IMAGE_USAGE_SAMPLED_BIT
|
6485 VK_IMAGE_USAGE_TRANSFER_SRC_BIT
|
6486 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)) {
6487 /* If this DCC image is potentially going to be used in texture
6488 * fetches, we need some special settings.
6490 independent_64b_blocks
= 1;
6491 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
6493 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
6494 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
6495 * big as possible for better compression state.
6497 independent_64b_blocks
= 0;
6498 max_compressed_block_size
= max_uncompressed_block_size
;
6502 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
6503 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size
) |
6504 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
6505 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks
) |
6506 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks
);
6510 radv_initialise_color_surface(struct radv_device
*device
,
6511 struct radv_color_buffer_info
*cb
,
6512 struct radv_image_view
*iview
)
6514 const struct vk_format_description
*desc
;
6515 unsigned ntype
, format
, swap
, endian
;
6516 unsigned blend_clamp
= 0, blend_bypass
= 0;
6518 const struct radv_image_plane
*plane
= &iview
->image
->planes
[iview
->plane_id
];
6519 const struct radeon_surf
*surf
= &plane
->surface
;
6521 desc
= vk_format_description(iview
->vk_format
);
6523 memset(cb
, 0, sizeof(*cb
));
6525 /* Intensity is implemented as Red, so treat it that way. */
6526 cb
->cb_color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == VK_SWIZZLE_1
);
6528 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ plane
->offset
;
6530 cb
->cb_color_base
= va
>> 8;
6532 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6533 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6534 cb
->cb_color_attrib3
|= S_028EE0_COLOR_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
6535 S_028EE0_FMASK_SW_MODE(surf
->u
.gfx9
.fmask
.swizzle_mode
) |
6536 S_028EE0_CMASK_PIPE_ALIGNED(1) |
6537 S_028EE0_DCC_PIPE_ALIGNED(surf
->u
.gfx9
.dcc
.pipe_aligned
);
6539 struct gfx9_surf_meta_flags meta
= {
6544 if (surf
->dcc_offset
)
6545 meta
= surf
->u
.gfx9
.dcc
;
6547 cb
->cb_color_attrib
|= S_028C74_COLOR_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
6548 S_028C74_FMASK_SW_MODE(surf
->u
.gfx9
.fmask
.swizzle_mode
) |
6549 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
6550 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
6551 cb
->cb_mrt_epitch
= S_0287A0_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
6554 cb
->cb_color_base
+= surf
->u
.gfx9
.surf_offset
>> 8;
6555 cb
->cb_color_base
|= surf
->tile_swizzle
;
6557 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[iview
->base_mip
];
6558 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
6560 cb
->cb_color_base
+= level_info
->offset
>> 8;
6561 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
6562 cb
->cb_color_base
|= surf
->tile_swizzle
;
6564 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
6565 slice_tile_max
= (level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1;
6566 tile_mode_index
= si_tile_mode_index(plane
, iview
->base_mip
, false);
6568 cb
->cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
6569 cb
->cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
6570 cb
->cb_color_cmask_slice
= surf
->u
.legacy
.cmask_slice_tile_max
;
6572 cb
->cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
6574 if (radv_image_has_fmask(iview
->image
)) {
6575 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
6576 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(surf
->u
.legacy
.fmask
.pitch_in_pixels
/ 8 - 1);
6577 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(surf
->u
.legacy
.fmask
.tiling_index
);
6578 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(surf
->u
.legacy
.fmask
.slice_tile_max
);
6580 /* This must be set for fast clear to work without FMASK. */
6581 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
6582 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
6583 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
6584 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
6588 /* CMASK variables */
6589 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
6590 va
+= surf
->cmask_offset
;
6591 cb
->cb_color_cmask
= va
>> 8;
6593 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
6594 va
+= surf
->dcc_offset
;
6596 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
) &&
6597 device
->physical_device
->rad_info
.chip_class
<= GFX8
)
6598 va
+= plane
->surface
.u
.legacy
.level
[iview
->base_mip
].dcc_offset
;
6600 unsigned dcc_tile_swizzle
= surf
->tile_swizzle
;
6601 dcc_tile_swizzle
&= (surf
->dcc_alignment
- 1) >> 8;
6603 cb
->cb_dcc_base
= va
>> 8;
6604 cb
->cb_dcc_base
|= dcc_tile_swizzle
;
6606 /* GFX10 field has the same base shift as the GFX6 field. */
6607 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
6608 cb
->cb_color_view
= S_028C6C_SLICE_START(iview
->base_layer
) |
6609 S_028C6C_SLICE_MAX_GFX10(max_slice
);
6611 if (iview
->image
->info
.samples
> 1) {
6612 unsigned log_samples
= util_logbase2(iview
->image
->info
.samples
);
6614 cb
->cb_color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
6615 S_028C74_NUM_FRAGMENTS(log_samples
);
6618 if (radv_image_has_fmask(iview
->image
)) {
6619 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ surf
->fmask_offset
;
6620 cb
->cb_color_fmask
= va
>> 8;
6621 cb
->cb_color_fmask
|= surf
->fmask_tile_swizzle
;
6623 cb
->cb_color_fmask
= cb
->cb_color_base
;
6626 ntype
= radv_translate_color_numformat(iview
->vk_format
,
6628 vk_format_get_first_non_void_channel(iview
->vk_format
));
6629 format
= radv_translate_colorformat(iview
->vk_format
);
6630 if (format
== V_028C70_COLOR_INVALID
|| ntype
== ~0u)
6631 radv_finishme("Illegal color\n");
6632 swap
= radv_translate_colorswap(iview
->vk_format
, false);
6633 endian
= radv_colorformat_endian_swap(format
);
6635 /* blend clamp should be set for all NORM/SRGB types */
6636 if (ntype
== V_028C70_NUMBER_UNORM
||
6637 ntype
== V_028C70_NUMBER_SNORM
||
6638 ntype
== V_028C70_NUMBER_SRGB
)
6641 /* set blend bypass according to docs if SINT/UINT or
6642 8/24 COLOR variants */
6643 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
6644 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
6645 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
6650 if ((ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) &&
6651 (format
== V_028C70_COLOR_8
||
6652 format
== V_028C70_COLOR_8_8
||
6653 format
== V_028C70_COLOR_8_8_8_8
))
6654 ->color_is_int8
= true;
6656 cb
->cb_color_info
= S_028C70_FORMAT(format
) |
6657 S_028C70_COMP_SWAP(swap
) |
6658 S_028C70_BLEND_CLAMP(blend_clamp
) |
6659 S_028C70_BLEND_BYPASS(blend_bypass
) |
6660 S_028C70_SIMPLE_FLOAT(1) |
6661 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
6662 ntype
!= V_028C70_NUMBER_SNORM
&&
6663 ntype
!= V_028C70_NUMBER_SRGB
&&
6664 format
!= V_028C70_COLOR_8_24
&&
6665 format
!= V_028C70_COLOR_24_8
) |
6666 S_028C70_NUMBER_TYPE(ntype
) |
6667 S_028C70_ENDIAN(endian
);
6668 if (radv_image_has_fmask(iview
->image
)) {
6669 cb
->cb_color_info
|= S_028C70_COMPRESSION(1);
6670 if (device
->physical_device
->rad_info
.chip_class
== GFX6
) {
6671 unsigned fmask_bankh
= util_logbase2(surf
->u
.legacy
.fmask
.bankh
);
6672 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
6675 if (radv_image_is_tc_compat_cmask(iview
->image
)) {
6676 /* Allow the texture block to read FMASK directly
6677 * without decompressing it. This bit must be cleared
6678 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
6679 * otherwise the operation doesn't happen.
6681 cb
->cb_color_info
|= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
6683 /* Set CMASK into a tiling format that allows the
6684 * texture block to read it.
6686 cb
->cb_color_info
|= S_028C70_CMASK_ADDR_TYPE(2);
6690 if (radv_image_has_cmask(iview
->image
) &&
6691 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
))
6692 cb
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
6694 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
))
6695 cb
->cb_color_info
|= S_028C70_DCC_ENABLE(1);
6697 cb
->cb_dcc_control
= radv_init_dcc_control_reg(device
, iview
);
6699 /* This must be set for fast clear to work without FMASK. */
6700 if (!radv_image_has_fmask(iview
->image
) &&
6701 device
->physical_device
->rad_info
.chip_class
== GFX6
) {
6702 unsigned bankh
= util_logbase2(surf
->u
.legacy
.bankh
);
6703 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
6706 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6707 const struct vk_format_description
*format_desc
= vk_format_description(iview
->image
->vk_format
);
6709 unsigned mip0_depth
= iview
->image
->type
== VK_IMAGE_TYPE_3D
?
6710 (iview
->extent
.depth
- 1) : (iview
->image
->info
.array_size
- 1);
6711 unsigned width
= iview
->extent
.width
/ (iview
->plane_id
? format_desc
->width_divisor
: 1);
6712 unsigned height
= iview
->extent
.height
/ (iview
->plane_id
? format_desc
->height_divisor
: 1);
6714 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6715 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL_GFX10(iview
->base_mip
);
6717 cb
->cb_color_attrib3
|= S_028EE0_MIP0_DEPTH(mip0_depth
) |
6718 S_028EE0_RESOURCE_TYPE(surf
->u
.gfx9
.resource_type
) |
6719 S_028EE0_RESOURCE_LEVEL(1);
6721 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL_GFX9(iview
->base_mip
);
6722 cb
->cb_color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
6723 S_028C74_RESOURCE_TYPE(surf
->u
.gfx9
.resource_type
);
6726 cb
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(width
- 1) |
6727 S_028C68_MIP0_HEIGHT(height
- 1) |
6728 S_028C68_MAX_MIP(iview
->image
->info
.levels
- 1);
6733 radv_calc_decompress_on_z_planes(struct radv_device
*device
,
6734 struct radv_image_view
*iview
)
6736 unsigned max_zplanes
= 0;
6738 assert(radv_image_is_tc_compat_htile(iview
->image
));
6740 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6741 /* Default value for 32-bit depth surfaces. */
6744 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
&&
6745 iview
->image
->info
.samples
> 1)
6748 max_zplanes
= max_zplanes
+ 1;
6750 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
) {
6751 /* Do not enable Z plane compression for 16-bit depth
6752 * surfaces because isn't supported on GFX8. Only
6753 * 32-bit depth surfaces are supported by the hardware.
6754 * This allows to maintain shader compatibility and to
6755 * reduce the number of depth decompressions.
6759 if (iview
->image
->info
.samples
<= 1)
6761 else if (iview
->image
->info
.samples
<= 4)
6772 radv_initialise_ds_surface(struct radv_device
*device
,
6773 struct radv_ds_buffer_info
*ds
,
6774 struct radv_image_view
*iview
)
6776 unsigned level
= iview
->base_mip
;
6777 unsigned format
, stencil_format
;
6778 uint64_t va
, s_offs
, z_offs
;
6779 bool stencil_only
= false;
6780 const struct radv_image_plane
*plane
= &iview
->image
->planes
[0];
6781 const struct radeon_surf
*surf
= &plane
->surface
;
6783 assert(vk_format_get_plane_count(iview
->image
->vk_format
) == 1);
6785 memset(ds
, 0, sizeof(*ds
));
6786 switch (iview
->image
->vk_format
) {
6787 case VK_FORMAT_D24_UNORM_S8_UINT
:
6788 case VK_FORMAT_X8_D24_UNORM_PACK32
:
6789 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
6790 ds
->offset_scale
= 2.0f
;
6792 case VK_FORMAT_D16_UNORM
:
6793 case VK_FORMAT_D16_UNORM_S8_UINT
:
6794 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
6795 ds
->offset_scale
= 4.0f
;
6797 case VK_FORMAT_D32_SFLOAT
:
6798 case VK_FORMAT_D32_SFLOAT_S8_UINT
:
6799 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
6800 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
6801 ds
->offset_scale
= 1.0f
;
6803 case VK_FORMAT_S8_UINT
:
6804 stencil_only
= true;
6810 format
= radv_translate_dbformat(iview
->image
->vk_format
);
6811 stencil_format
= surf
->has_stencil
?
6812 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
6814 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
6815 ds
->db_depth_view
= S_028008_SLICE_START(iview
->base_layer
) |
6816 S_028008_SLICE_MAX(max_slice
);
6817 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6818 ds
->db_depth_view
|= S_028008_SLICE_START_HI(iview
->base_layer
>> 11) |
6819 S_028008_SLICE_MAX_HI(max_slice
>> 11);
6822 ds
->db_htile_data_base
= 0;
6823 ds
->db_htile_surface
= 0;
6825 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
6826 s_offs
= z_offs
= va
;
6828 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6829 assert(surf
->u
.gfx9
.surf_offset
== 0);
6830 s_offs
+= surf
->u
.gfx9
.stencil_offset
;
6832 ds
->db_z_info
= S_028038_FORMAT(format
) |
6833 S_028038_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
)) |
6834 S_028038_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
6835 S_028038_MAXMIP(iview
->image
->info
.levels
- 1) |
6836 S_028038_ZRANGE_PRECISION(1);
6837 ds
->db_stencil_info
= S_02803C_FORMAT(stencil_format
) |
6838 S_02803C_SW_MODE(surf
->u
.gfx9
.stencil
.swizzle_mode
);
6840 if (device
->physical_device
->rad_info
.chip_class
== GFX9
) {
6841 ds
->db_z_info2
= S_028068_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
6842 ds
->db_stencil_info2
= S_02806C_EPITCH(surf
->u
.gfx9
.stencil
.epitch
);
6845 ds
->db_depth_view
|= S_028008_MIPID(level
);
6846 ds
->db_depth_size
= S_02801C_X_MAX(iview
->image
->info
.width
- 1) |
6847 S_02801C_Y_MAX(iview
->image
->info
.height
- 1);
6849 if (radv_htile_enabled(iview
->image
, level
)) {
6850 ds
->db_z_info
|= S_028038_TILE_SURFACE_ENABLE(1);
6852 if (radv_image_is_tc_compat_htile(iview
->image
)) {
6853 unsigned max_zplanes
=
6854 radv_calc_decompress_on_z_planes(device
, iview
);
6856 ds
->db_z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
6858 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6859 ds
->db_z_info
|= S_028040_ITERATE_FLUSH(1);
6860 ds
->db_stencil_info
|= S_028044_ITERATE_FLUSH(1);
6862 ds
->db_z_info
|= S_028038_ITERATE_FLUSH(1);
6863 ds
->db_stencil_info
|= S_02803C_ITERATE_FLUSH(1);
6867 if (!surf
->has_stencil
)
6868 /* Use all of the htile_buffer for depth if there's no stencil. */
6869 ds
->db_stencil_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
6870 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
6872 ds
->db_htile_data_base
= va
>> 8;
6873 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
6874 S_028ABC_PIPE_ALIGNED(1);
6876 if (device
->physical_device
->rad_info
.chip_class
== GFX9
) {
6877 ds
->db_htile_surface
|= S_028ABC_RB_ALIGNED(1);
6881 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[level
];
6884 level_info
= &surf
->u
.legacy
.stencil_level
[level
];
6886 z_offs
+= surf
->u
.legacy
.level
[level
].offset
;
6887 s_offs
+= surf
->u
.legacy
.stencil_level
[level
].offset
;
6889 ds
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview
->image
));
6890 ds
->db_z_info
= S_028040_FORMAT(format
) | S_028040_ZRANGE_PRECISION(1);
6891 ds
->db_stencil_info
= S_028044_FORMAT(stencil_format
);
6893 if (iview
->image
->info
.samples
> 1)
6894 ds
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
));
6896 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
6897 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
6898 unsigned tiling_index
= surf
->u
.legacy
.tiling_index
[level
];
6899 unsigned stencil_index
= surf
->u
.legacy
.stencil_tiling_index
[level
];
6900 unsigned macro_index
= surf
->u
.legacy
.macro_tile_index
;
6901 unsigned tile_mode
= info
->si_tile_mode_array
[tiling_index
];
6902 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
6903 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
6906 tile_mode
= stencil_tile_mode
;
6908 ds
->db_depth_info
|=
6909 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
6910 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
6911 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
6912 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
6913 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
6914 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
6915 ds
->db_z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
6916 ds
->db_stencil_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
6918 unsigned tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, false);
6919 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
6920 tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, true);
6921 ds
->db_stencil_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
6923 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
6926 ds
->db_depth_size
= S_028058_PITCH_TILE_MAX((level_info
->nblk_x
/ 8) - 1) |
6927 S_028058_HEIGHT_TILE_MAX((level_info
->nblk_y
/ 8) - 1);
6928 ds
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1);
6930 if (radv_htile_enabled(iview
->image
, level
)) {
6931 ds
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
6933 if (!surf
->has_stencil
&&
6934 !radv_image_is_tc_compat_htile(iview
->image
))
6935 /* Use all of the htile_buffer for depth if there's no stencil. */
6936 ds
->db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
6938 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
6940 ds
->db_htile_data_base
= va
>> 8;
6941 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
6943 if (radv_image_is_tc_compat_htile(iview
->image
)) {
6944 unsigned max_zplanes
=
6945 radv_calc_decompress_on_z_planes(device
, iview
);
6947 ds
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
6948 ds
->db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
6953 ds
->db_z_read_base
= ds
->db_z_write_base
= z_offs
>> 8;
6954 ds
->db_stencil_read_base
= ds
->db_stencil_write_base
= s_offs
>> 8;
6957 VkResult
radv_CreateFramebuffer(
6959 const VkFramebufferCreateInfo
* pCreateInfo
,
6960 const VkAllocationCallbacks
* pAllocator
,
6961 VkFramebuffer
* pFramebuffer
)
6963 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6964 struct radv_framebuffer
*framebuffer
;
6965 const VkFramebufferAttachmentsCreateInfo
*imageless_create_info
=
6966 vk_find_struct_const(pCreateInfo
->pNext
,
6967 FRAMEBUFFER_ATTACHMENTS_CREATE_INFO
);
6969 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
);
6971 size_t size
= sizeof(*framebuffer
);
6972 if (!imageless_create_info
)
6973 size
+= sizeof(struct radv_image_view
*) * pCreateInfo
->attachmentCount
;
6974 framebuffer
= vk_alloc2(&device
->vk
.alloc
, pAllocator
, size
, 8,
6975 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
6976 if (framebuffer
== NULL
)
6977 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6979 vk_object_base_init(&device
->vk
, &framebuffer
->base
,
6980 VK_OBJECT_TYPE_FRAMEBUFFER
);
6982 framebuffer
->attachment_count
= pCreateInfo
->attachmentCount
;
6983 framebuffer
->width
= pCreateInfo
->width
;
6984 framebuffer
->height
= pCreateInfo
->height
;
6985 framebuffer
->layers
= pCreateInfo
->layers
;
6986 if (imageless_create_info
) {
6987 for (unsigned i
= 0; i
< imageless_create_info
->attachmentImageInfoCount
; ++i
) {
6988 const VkFramebufferAttachmentImageInfo
*attachment
=
6989 imageless_create_info
->pAttachmentImageInfos
+ i
;
6990 framebuffer
->width
= MIN2(framebuffer
->width
, attachment
->width
);
6991 framebuffer
->height
= MIN2(framebuffer
->height
, attachment
->height
);
6992 framebuffer
->layers
= MIN2(framebuffer
->layers
, attachment
->layerCount
);
6995 for (uint32_t i
= 0; i
< pCreateInfo
->attachmentCount
; i
++) {
6996 VkImageView _iview
= pCreateInfo
->pAttachments
[i
];
6997 struct radv_image_view
*iview
= radv_image_view_from_handle(_iview
);
6998 framebuffer
->attachments
[i
] = iview
;
6999 framebuffer
->width
= MIN2(framebuffer
->width
, iview
->extent
.width
);
7000 framebuffer
->height
= MIN2(framebuffer
->height
, iview
->extent
.height
);
7001 framebuffer
->layers
= MIN2(framebuffer
->layers
, radv_surface_max_layer_count(iview
));
7005 *pFramebuffer
= radv_framebuffer_to_handle(framebuffer
);
7009 void radv_DestroyFramebuffer(
7012 const VkAllocationCallbacks
* pAllocator
)
7014 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7015 RADV_FROM_HANDLE(radv_framebuffer
, fb
, _fb
);
7019 vk_object_base_finish(&fb
->base
);
7020 vk_free2(&device
->vk
.alloc
, pAllocator
, fb
);
7023 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode
)
7025 switch (address_mode
) {
7026 case VK_SAMPLER_ADDRESS_MODE_REPEAT
:
7027 return V_008F30_SQ_TEX_WRAP
;
7028 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT
:
7029 return V_008F30_SQ_TEX_MIRROR
;
7030 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
:
7031 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
7032 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
:
7033 return V_008F30_SQ_TEX_CLAMP_BORDER
;
7034 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE
:
7035 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
7037 unreachable("illegal tex wrap mode");
7043 radv_tex_compare(VkCompareOp op
)
7046 case VK_COMPARE_OP_NEVER
:
7047 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
7048 case VK_COMPARE_OP_LESS
:
7049 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
7050 case VK_COMPARE_OP_EQUAL
:
7051 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
7052 case VK_COMPARE_OP_LESS_OR_EQUAL
:
7053 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
7054 case VK_COMPARE_OP_GREATER
:
7055 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
7056 case VK_COMPARE_OP_NOT_EQUAL
:
7057 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
7058 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
7059 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
7060 case VK_COMPARE_OP_ALWAYS
:
7061 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
7063 unreachable("illegal compare mode");
7069 radv_tex_filter(VkFilter filter
, unsigned max_ansio
)
7072 case VK_FILTER_NEAREST
:
7073 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
:
7074 V_008F38_SQ_TEX_XY_FILTER_POINT
);
7075 case VK_FILTER_LINEAR
:
7076 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
:
7077 V_008F38_SQ_TEX_XY_FILTER_BILINEAR
);
7078 case VK_FILTER_CUBIC_IMG
:
7080 fprintf(stderr
, "illegal texture filter");
7086 radv_tex_mipfilter(VkSamplerMipmapMode mode
)
7089 case VK_SAMPLER_MIPMAP_MODE_NEAREST
:
7090 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
7091 case VK_SAMPLER_MIPMAP_MODE_LINEAR
:
7092 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
7094 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
7099 radv_tex_bordercolor(VkBorderColor bcolor
)
7102 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
:
7103 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK
:
7104 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
7105 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK
:
7106 case VK_BORDER_COLOR_INT_OPAQUE_BLACK
:
7107 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
7108 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE
:
7109 case VK_BORDER_COLOR_INT_OPAQUE_WHITE
:
7110 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
7111 case VK_BORDER_COLOR_FLOAT_CUSTOM_EXT
:
7112 case VK_BORDER_COLOR_INT_CUSTOM_EXT
:
7113 return V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
;
7121 radv_tex_aniso_filter(unsigned filter
)
7135 radv_tex_filter_mode(VkSamplerReductionMode mode
)
7138 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT
:
7139 return V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
7140 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT
:
7141 return V_008F30_SQ_IMG_FILTER_MODE_MIN
;
7142 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT
:
7143 return V_008F30_SQ_IMG_FILTER_MODE_MAX
;
7151 radv_get_max_anisotropy(struct radv_device
*device
,
7152 const VkSamplerCreateInfo
*pCreateInfo
)
7154 if (device
->force_aniso
>= 0)
7155 return device
->force_aniso
;
7157 if (pCreateInfo
->anisotropyEnable
&&
7158 pCreateInfo
->maxAnisotropy
> 1.0f
)
7159 return (uint32_t)pCreateInfo
->maxAnisotropy
;
7164 static inline int S_FIXED(float value
, unsigned frac_bits
)
7166 return value
* (1 << frac_bits
);
7169 static uint32_t radv_register_border_color(struct radv_device
*device
,
7170 VkClearColorValue value
)
7174 pthread_mutex_lock(&device
->border_color_data
.mutex
);
7176 for (slot
= 0; slot
< RADV_BORDER_COLOR_COUNT
; slot
++) {
7177 if (!device
->border_color_data
.used
[slot
]) {
7178 /* Copy to the GPU wrt endian-ness. */
7179 util_memcpy_cpu_to_le32(&device
->border_color_data
.colors_gpu_ptr
[slot
],
7181 sizeof(VkClearColorValue
));
7183 device
->border_color_data
.used
[slot
] = true;
7188 pthread_mutex_unlock(&device
->border_color_data
.mutex
);
7193 static void radv_unregister_border_color(struct radv_device
*device
,
7196 pthread_mutex_lock(&device
->border_color_data
.mutex
);
7198 device
->border_color_data
.used
[slot
] = false;
7200 pthread_mutex_unlock(&device
->border_color_data
.mutex
);
7204 radv_init_sampler(struct radv_device
*device
,
7205 struct radv_sampler
*sampler
,
7206 const VkSamplerCreateInfo
*pCreateInfo
)
7208 uint32_t max_aniso
= radv_get_max_anisotropy(device
, pCreateInfo
);
7209 uint32_t max_aniso_ratio
= radv_tex_aniso_filter(max_aniso
);
7210 bool compat_mode
= device
->physical_device
->rad_info
.chip_class
== GFX8
||
7211 device
->physical_device
->rad_info
.chip_class
== GFX9
;
7212 unsigned filter_mode
= V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
7213 unsigned depth_compare_func
= V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
7214 bool trunc_coord
= pCreateInfo
->minFilter
== VK_FILTER_NEAREST
&& pCreateInfo
->magFilter
== VK_FILTER_NEAREST
;
7215 bool uses_border_color
= pCreateInfo
->addressModeU
== VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
||
7216 pCreateInfo
->addressModeV
== VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
||
7217 pCreateInfo
->addressModeW
== VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
;
7218 VkBorderColor border_color
= uses_border_color
? pCreateInfo
->borderColor
: VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
;
7219 uint32_t border_color_ptr
;
7221 const struct VkSamplerReductionModeCreateInfo
*sampler_reduction
=
7222 vk_find_struct_const(pCreateInfo
->pNext
,
7223 SAMPLER_REDUCTION_MODE_CREATE_INFO
);
7224 if (sampler_reduction
)
7225 filter_mode
= radv_tex_filter_mode(sampler_reduction
->reductionMode
);
7227 if (pCreateInfo
->compareEnable
)
7228 depth_compare_func
= radv_tex_compare(pCreateInfo
->compareOp
);
7230 sampler
->border_color_slot
= RADV_BORDER_COLOR_COUNT
;
7232 if (border_color
== VK_BORDER_COLOR_FLOAT_CUSTOM_EXT
|| border_color
== VK_BORDER_COLOR_INT_CUSTOM_EXT
) {
7233 const VkSamplerCustomBorderColorCreateInfoEXT
*custom_border_color
=
7234 vk_find_struct_const(pCreateInfo
->pNext
,
7235 SAMPLER_CUSTOM_BORDER_COLOR_CREATE_INFO_EXT
);
7237 assert(custom_border_color
);
7239 sampler
->border_color_slot
=
7240 radv_register_border_color(device
, custom_border_color
->customBorderColor
);
7242 /* Did we fail to find a slot? */
7243 if (sampler
->border_color_slot
== RADV_BORDER_COLOR_COUNT
) {
7244 fprintf(stderr
, "WARNING: no free border color slots, defaulting to TRANS_BLACK.\n");
7245 border_color
= VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
;
7249 /* If we don't have a custom color, set the ptr to 0 */
7250 border_color_ptr
= sampler
->border_color_slot
!= RADV_BORDER_COLOR_COUNT
7251 ? sampler
->border_color_slot
7254 sampler
->state
[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo
->addressModeU
)) |
7255 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo
->addressModeV
)) |
7256 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo
->addressModeW
)) |
7257 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
7258 S_008F30_DEPTH_COMPARE_FUNC(depth_compare_func
) |
7259 S_008F30_FORCE_UNNORMALIZED(pCreateInfo
->unnormalizedCoordinates
? 1 : 0) |
7260 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
7261 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
7262 S_008F30_DISABLE_CUBE_WRAP(0) |
7263 S_008F30_COMPAT_MODE(compat_mode
) |
7264 S_008F30_FILTER_MODE(filter_mode
) |
7265 S_008F30_TRUNC_COORD(trunc_coord
));
7266 sampler
->state
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo
->minLod
, 0, 15), 8)) |
7267 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo
->maxLod
, 0, 15), 8)) |
7268 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
7269 sampler
->state
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo
->mipLodBias
, -16, 16), 8)) |
7270 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo
->magFilter
, max_aniso
)) |
7271 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo
->minFilter
, max_aniso
)) |
7272 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo
->mipmapMode
)) |
7273 S_008F38_MIP_POINT_PRECLAMP(0));
7274 sampler
->state
[3] = (S_008F3C_BORDER_COLOR_PTR(border_color_ptr
) |
7275 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(border_color
)));
7277 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
7278 sampler
->state
[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
7280 sampler
->state
[2] |=
7281 S_008F38_DISABLE_LSB_CEIL(device
->physical_device
->rad_info
.chip_class
<= GFX8
) |
7282 S_008F38_FILTER_PREC_FIX(1) |
7283 S_008F38_ANISO_OVERRIDE_GFX6(device
->physical_device
->rad_info
.chip_class
>= GFX8
);
7287 VkResult
radv_CreateSampler(
7289 const VkSamplerCreateInfo
* pCreateInfo
,
7290 const VkAllocationCallbacks
* pAllocator
,
7291 VkSampler
* pSampler
)
7293 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7294 struct radv_sampler
*sampler
;
7296 const struct VkSamplerYcbcrConversionInfo
*ycbcr_conversion
=
7297 vk_find_struct_const(pCreateInfo
->pNext
,
7298 SAMPLER_YCBCR_CONVERSION_INFO
);
7300 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO
);
7302 sampler
= vk_alloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*sampler
), 8,
7303 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
7305 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
7307 vk_object_base_init(&device
->vk
, &sampler
->base
,
7308 VK_OBJECT_TYPE_SAMPLER
);
7310 radv_init_sampler(device
, sampler
, pCreateInfo
);
7312 sampler
->ycbcr_sampler
= ycbcr_conversion
? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion
->conversion
): NULL
;
7313 *pSampler
= radv_sampler_to_handle(sampler
);
7318 void radv_DestroySampler(
7321 const VkAllocationCallbacks
* pAllocator
)
7323 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7324 RADV_FROM_HANDLE(radv_sampler
, sampler
, _sampler
);
7329 if (sampler
->border_color_slot
!= RADV_BORDER_COLOR_COUNT
)
7330 radv_unregister_border_color(device
, sampler
->border_color_slot
);
7332 vk_object_base_finish(&sampler
->base
);
7333 vk_free2(&device
->vk
.alloc
, pAllocator
, sampler
);
7336 /* vk_icd.h does not declare this function, so we declare it here to
7337 * suppress Wmissing-prototypes.
7339 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
7340 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
);
7342 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
7343 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
)
7345 /* For the full details on loader interface versioning, see
7346 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
7347 * What follows is a condensed summary, to help you navigate the large and
7348 * confusing official doc.
7350 * - Loader interface v0 is incompatible with later versions. We don't
7353 * - In loader interface v1:
7354 * - The first ICD entrypoint called by the loader is
7355 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
7357 * - The ICD must statically expose no other Vulkan symbol unless it is
7358 * linked with -Bsymbolic.
7359 * - Each dispatchable Vulkan handle created by the ICD must be
7360 * a pointer to a struct whose first member is VK_LOADER_DATA. The
7361 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
7362 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
7363 * vkDestroySurfaceKHR(). The ICD must be capable of working with
7364 * such loader-managed surfaces.
7366 * - Loader interface v2 differs from v1 in:
7367 * - The first ICD entrypoint called by the loader is
7368 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
7369 * statically expose this entrypoint.
7371 * - Loader interface v3 differs from v2 in:
7372 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
7373 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
7374 * because the loader no longer does so.
7376 *pSupportedVersion
= MIN2(*pSupportedVersion
, 4u);
7380 VkResult
radv_GetMemoryFdKHR(VkDevice _device
,
7381 const VkMemoryGetFdInfoKHR
*pGetFdInfo
,
7384 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7385 RADV_FROM_HANDLE(radv_device_memory
, memory
, pGetFdInfo
->memory
);
7387 assert(pGetFdInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR
);
7389 /* At the moment, we support only the below handle types. */
7390 assert(pGetFdInfo
->handleType
==
7391 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
7392 pGetFdInfo
->handleType
==
7393 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
7395 bool ret
= radv_get_memory_fd(device
, memory
, pFD
);
7397 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
7401 static uint32_t radv_compute_valid_memory_types_attempt(struct radv_physical_device
*dev
,
7402 enum radeon_bo_domain domains
,
7403 enum radeon_bo_flag flags
,
7404 enum radeon_bo_flag ignore_flags
)
7406 /* Don't count GTT/CPU as relevant:
7408 * - We're not fully consistent between the two.
7409 * - Sometimes VRAM gets VRAM|GTT.
7411 const enum radeon_bo_domain relevant_domains
= RADEON_DOMAIN_VRAM
|
7415 for (unsigned i
= 0; i
< dev
->memory_properties
.memoryTypeCount
; ++i
) {
7416 if ((domains
& relevant_domains
) != (dev
->memory_domains
[i
] & relevant_domains
))
7419 if ((flags
& ~ignore_flags
) != (dev
->memory_flags
[i
] & ~ignore_flags
))
7428 static uint32_t radv_compute_valid_memory_types(struct radv_physical_device
*dev
,
7429 enum radeon_bo_domain domains
,
7430 enum radeon_bo_flag flags
)
7432 enum radeon_bo_flag ignore_flags
= ~(RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_GTT_WC
);
7433 uint32_t bits
= radv_compute_valid_memory_types_attempt(dev
, domains
, flags
, ignore_flags
);
7436 ignore_flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
7437 bits
= radv_compute_valid_memory_types_attempt(dev
, domains
, flags
, ignore_flags
);
7442 VkResult
radv_GetMemoryFdPropertiesKHR(VkDevice _device
,
7443 VkExternalMemoryHandleTypeFlagBits handleType
,
7445 VkMemoryFdPropertiesKHR
*pMemoryFdProperties
)
7447 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7449 switch (handleType
) {
7450 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
: {
7451 enum radeon_bo_domain domains
;
7452 enum radeon_bo_flag flags
;
7453 if (!device
->ws
->buffer_get_flags_from_fd(device
->ws
, fd
, &domains
, &flags
))
7454 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7456 pMemoryFdProperties
->memoryTypeBits
= radv_compute_valid_memory_types(device
->physical_device
, domains
, flags
);
7460 /* The valid usage section for this function says:
7462 * "handleType must not be one of the handle types defined as
7465 * So opaque handle types fall into the default "unsupported" case.
7467 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7471 static VkResult
radv_import_opaque_fd(struct radv_device
*device
,
7475 uint32_t syncobj_handle
= 0;
7476 int ret
= device
->ws
->import_syncobj(device
->ws
, fd
, &syncobj_handle
);
7478 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7481 device
->ws
->destroy_syncobj(device
->ws
, *syncobj
);
7483 *syncobj
= syncobj_handle
;
7489 static VkResult
radv_import_sync_fd(struct radv_device
*device
,
7493 /* If we create a syncobj we do it locally so that if we have an error, we don't
7494 * leave a syncobj in an undetermined state in the fence. */
7495 uint32_t syncobj_handle
= *syncobj
;
7496 if (!syncobj_handle
) {
7497 bool create_signaled
= fd
== -1 ? true : false;
7499 int ret
= device
->ws
->create_syncobj(device
->ws
, create_signaled
,
7502 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
7506 device
->ws
->signal_syncobj(device
->ws
, syncobj_handle
, 0);
7510 int ret
= device
->ws
->import_syncobj_from_sync_file(device
->ws
, syncobj_handle
, fd
);
7512 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7516 *syncobj
= syncobj_handle
;
7521 VkResult
radv_ImportSemaphoreFdKHR(VkDevice _device
,
7522 const VkImportSemaphoreFdInfoKHR
*pImportSemaphoreFdInfo
)
7524 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7525 RADV_FROM_HANDLE(radv_semaphore
, sem
, pImportSemaphoreFdInfo
->semaphore
);
7527 struct radv_semaphore_part
*dst
= NULL
;
7528 bool timeline
= sem
->permanent
.kind
== RADV_SEMAPHORE_TIMELINE_SYNCOBJ
;
7530 if (pImportSemaphoreFdInfo
->flags
& VK_SEMAPHORE_IMPORT_TEMPORARY_BIT
) {
7532 dst
= &sem
->temporary
;
7534 dst
= &sem
->permanent
;
7537 uint32_t syncobj
= (dst
->kind
== RADV_SEMAPHORE_SYNCOBJ
||
7538 dst
->kind
== RADV_SEMAPHORE_TIMELINE_SYNCOBJ
) ? dst
->syncobj
: 0;
7540 switch(pImportSemaphoreFdInfo
->handleType
) {
7541 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7542 result
= radv_import_opaque_fd(device
, pImportSemaphoreFdInfo
->fd
, &syncobj
);
7544 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
7546 result
= radv_import_sync_fd(device
, pImportSemaphoreFdInfo
->fd
, &syncobj
);
7549 unreachable("Unhandled semaphore handle type");
7552 if (result
== VK_SUCCESS
) {
7553 dst
->syncobj
= syncobj
;
7554 dst
->kind
= RADV_SEMAPHORE_SYNCOBJ
;
7556 dst
->kind
= RADV_SEMAPHORE_TIMELINE_SYNCOBJ
;
7557 dst
->timeline_syncobj
.max_point
= 0;
7564 VkResult
radv_GetSemaphoreFdKHR(VkDevice _device
,
7565 const VkSemaphoreGetFdInfoKHR
*pGetFdInfo
,
7568 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7569 RADV_FROM_HANDLE(radv_semaphore
, sem
, pGetFdInfo
->semaphore
);
7571 uint32_t syncobj_handle
;
7573 if (sem
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
7574 assert(sem
->temporary
.kind
== RADV_SEMAPHORE_SYNCOBJ
||
7575 sem
->temporary
.kind
== RADV_SEMAPHORE_TIMELINE_SYNCOBJ
);
7576 syncobj_handle
= sem
->temporary
.syncobj
;
7578 assert(sem
->permanent
.kind
== RADV_SEMAPHORE_SYNCOBJ
||
7579 sem
->permanent
.kind
== RADV_SEMAPHORE_TIMELINE_SYNCOBJ
);
7580 syncobj_handle
= sem
->permanent
.syncobj
;
7583 switch(pGetFdInfo
->handleType
) {
7584 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7585 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
7587 return vk_error(device
->instance
, VK_ERROR_TOO_MANY_OBJECTS
);
7589 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
7590 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
7592 return vk_error(device
->instance
, VK_ERROR_TOO_MANY_OBJECTS
);
7594 if (sem
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
7595 radv_destroy_semaphore_part(device
, &sem
->temporary
);
7597 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
7601 unreachable("Unhandled semaphore handle type");
7607 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
7608 VkPhysicalDevice physicalDevice
,
7609 const VkPhysicalDeviceExternalSemaphoreInfo
*pExternalSemaphoreInfo
,
7610 VkExternalSemaphoreProperties
*pExternalSemaphoreProperties
)
7612 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
7613 VkSemaphoreTypeKHR type
= radv_get_semaphore_type(pExternalSemaphoreInfo
->pNext
, NULL
);
7615 if (type
== VK_SEMAPHORE_TYPE_TIMELINE
&& pdevice
->rad_info
.has_timeline_syncobj
&&
7616 pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
) {
7617 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
7618 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
7619 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
7620 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
7621 } else if (type
== VK_SEMAPHORE_TYPE_TIMELINE
) {
7622 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= 0;
7623 pExternalSemaphoreProperties
->compatibleHandleTypes
= 0;
7624 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= 0;
7626 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
7627 } else if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
7628 (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
||
7629 pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
)) {
7630 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
7631 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
7632 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
7633 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
7634 } else if (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
) {
7635 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
7636 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
7637 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
7638 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
7640 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= 0;
7641 pExternalSemaphoreProperties
->compatibleHandleTypes
= 0;
7642 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= 0;
7646 VkResult
radv_ImportFenceFdKHR(VkDevice _device
,
7647 const VkImportFenceFdInfoKHR
*pImportFenceFdInfo
)
7649 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7650 RADV_FROM_HANDLE(radv_fence
, fence
, pImportFenceFdInfo
->fence
);
7651 struct radv_fence_part
*dst
= NULL
;
7654 if (pImportFenceFdInfo
->flags
& VK_FENCE_IMPORT_TEMPORARY_BIT
) {
7655 dst
= &fence
->temporary
;
7657 dst
= &fence
->permanent
;
7660 uint32_t syncobj
= dst
->kind
== RADV_FENCE_SYNCOBJ
? dst
->syncobj
: 0;
7662 switch(pImportFenceFdInfo
->handleType
) {
7663 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7664 result
= radv_import_opaque_fd(device
, pImportFenceFdInfo
->fd
, &syncobj
);
7666 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
7667 result
= radv_import_sync_fd(device
, pImportFenceFdInfo
->fd
, &syncobj
);
7670 unreachable("Unhandled fence handle type");
7673 if (result
== VK_SUCCESS
) {
7674 dst
->syncobj
= syncobj
;
7675 dst
->kind
= RADV_FENCE_SYNCOBJ
;
7681 VkResult
radv_GetFenceFdKHR(VkDevice _device
,
7682 const VkFenceGetFdInfoKHR
*pGetFdInfo
,
7685 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7686 RADV_FROM_HANDLE(radv_fence
, fence
, pGetFdInfo
->fence
);
7689 struct radv_fence_part
*part
=
7690 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
7691 &fence
->temporary
: &fence
->permanent
;
7693 switch(pGetFdInfo
->handleType
) {
7694 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7695 ret
= device
->ws
->export_syncobj(device
->ws
, part
->syncobj
, pFd
);
7697 return vk_error(device
->instance
, VK_ERROR_TOO_MANY_OBJECTS
);
7699 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
7700 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
,
7701 part
->syncobj
, pFd
);
7703 return vk_error(device
->instance
, VK_ERROR_TOO_MANY_OBJECTS
);
7705 if (part
== &fence
->temporary
) {
7706 radv_destroy_fence_part(device
, part
);
7708 device
->ws
->reset_syncobj(device
->ws
, part
->syncobj
);
7712 unreachable("Unhandled fence handle type");
7718 void radv_GetPhysicalDeviceExternalFenceProperties(
7719 VkPhysicalDevice physicalDevice
,
7720 const VkPhysicalDeviceExternalFenceInfo
*pExternalFenceInfo
,
7721 VkExternalFenceProperties
*pExternalFenceProperties
)
7723 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
7725 if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
7726 (pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
||
7727 pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
)) {
7728 pExternalFenceProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
7729 pExternalFenceProperties
->compatibleHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
7730 pExternalFenceProperties
->externalFenceFeatures
= VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT
|
7731 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
7733 pExternalFenceProperties
->exportFromImportedHandleTypes
= 0;
7734 pExternalFenceProperties
->compatibleHandleTypes
= 0;
7735 pExternalFenceProperties
->externalFenceFeatures
= 0;
7740 radv_CreateDebugReportCallbackEXT(VkInstance _instance
,
7741 const VkDebugReportCallbackCreateInfoEXT
* pCreateInfo
,
7742 const VkAllocationCallbacks
* pAllocator
,
7743 VkDebugReportCallbackEXT
* pCallback
)
7745 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
7746 return vk_create_debug_report_callback(&instance
->debug_report_callbacks
,
7747 pCreateInfo
, pAllocator
, &instance
->alloc
,
7752 radv_DestroyDebugReportCallbackEXT(VkInstance _instance
,
7753 VkDebugReportCallbackEXT _callback
,
7754 const VkAllocationCallbacks
* pAllocator
)
7756 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
7757 vk_destroy_debug_report_callback(&instance
->debug_report_callbacks
,
7758 _callback
, pAllocator
, &instance
->alloc
);
7762 radv_DebugReportMessageEXT(VkInstance _instance
,
7763 VkDebugReportFlagsEXT flags
,
7764 VkDebugReportObjectTypeEXT objectType
,
7767 int32_t messageCode
,
7768 const char* pLayerPrefix
,
7769 const char* pMessage
)
7771 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
7772 vk_debug_report(&instance
->debug_report_callbacks
, flags
, objectType
,
7773 object
, location
, messageCode
, pLayerPrefix
, pMessage
);
7777 radv_GetDeviceGroupPeerMemoryFeatures(
7780 uint32_t localDeviceIndex
,
7781 uint32_t remoteDeviceIndex
,
7782 VkPeerMemoryFeatureFlags
* pPeerMemoryFeatures
)
7784 assert(localDeviceIndex
== remoteDeviceIndex
);
7786 *pPeerMemoryFeatures
= VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT
|
7787 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT
|
7788 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT
|
7789 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT
;
7792 static const VkTimeDomainEXT radv_time_domains
[] = {
7793 VK_TIME_DOMAIN_DEVICE_EXT
,
7794 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
,
7795 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
,
7798 VkResult
radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
7799 VkPhysicalDevice physicalDevice
,
7800 uint32_t *pTimeDomainCount
,
7801 VkTimeDomainEXT
*pTimeDomains
)
7804 VK_OUTARRAY_MAKE(out
, pTimeDomains
, pTimeDomainCount
);
7806 for (d
= 0; d
< ARRAY_SIZE(radv_time_domains
); d
++) {
7807 vk_outarray_append(&out
, i
) {
7808 *i
= radv_time_domains
[d
];
7812 return vk_outarray_status(&out
);
7816 radv_clock_gettime(clockid_t clock_id
)
7818 struct timespec current
;
7821 ret
= clock_gettime(clock_id
, ¤t
);
7822 if (ret
< 0 && clock_id
== CLOCK_MONOTONIC_RAW
)
7823 ret
= clock_gettime(CLOCK_MONOTONIC
, ¤t
);
7827 return (uint64_t) current
.tv_sec
* 1000000000ULL + current
.tv_nsec
;
7830 VkResult
radv_GetCalibratedTimestampsEXT(
7832 uint32_t timestampCount
,
7833 const VkCalibratedTimestampInfoEXT
*pTimestampInfos
,
7834 uint64_t *pTimestamps
,
7835 uint64_t *pMaxDeviation
)
7837 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7838 uint32_t clock_crystal_freq
= device
->physical_device
->rad_info
.clock_crystal_freq
;
7840 uint64_t begin
, end
;
7841 uint64_t max_clock_period
= 0;
7843 begin
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
7845 for (d
= 0; d
< timestampCount
; d
++) {
7846 switch (pTimestampInfos
[d
].timeDomain
) {
7847 case VK_TIME_DOMAIN_DEVICE_EXT
:
7848 pTimestamps
[d
] = device
->ws
->query_value(device
->ws
,
7850 uint64_t device_period
= DIV_ROUND_UP(1000000, clock_crystal_freq
);
7851 max_clock_period
= MAX2(max_clock_period
, device_period
);
7853 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
:
7854 pTimestamps
[d
] = radv_clock_gettime(CLOCK_MONOTONIC
);
7855 max_clock_period
= MAX2(max_clock_period
, 1);
7858 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
:
7859 pTimestamps
[d
] = begin
;
7867 end
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
7870 * The maximum deviation is the sum of the interval over which we
7871 * perform the sampling and the maximum period of any sampled
7872 * clock. That's because the maximum skew between any two sampled
7873 * clock edges is when the sampled clock with the largest period is
7874 * sampled at the end of that period but right at the beginning of the
7875 * sampling interval and some other clock is sampled right at the
7876 * begining of its sampling period and right at the end of the
7877 * sampling interval. Let's assume the GPU has the longest clock
7878 * period and that the application is sampling GPU and monotonic:
7881 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
7882 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7886 * GPU -----_____-----_____-----_____-----_____
7889 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
7890 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7892 * Interval <----------------->
7893 * Deviation <-------------------------->
7897 * m = read(monotonic) 2
7900 * We round the sample interval up by one tick to cover sampling error
7901 * in the interval clock
7904 uint64_t sample_interval
= end
- begin
+ 1;
7906 *pMaxDeviation
= sample_interval
+ max_clock_period
;
7911 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
7912 VkPhysicalDevice physicalDevice
,
7913 VkSampleCountFlagBits samples
,
7914 VkMultisamplePropertiesEXT
* pMultisampleProperties
)
7916 if (samples
& (VK_SAMPLE_COUNT_2_BIT
|
7917 VK_SAMPLE_COUNT_4_BIT
|
7918 VK_SAMPLE_COUNT_8_BIT
)) {
7919 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2, 2 };
7921 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 0, 0 };
7925 VkResult
radv_CreatePrivateDataSlotEXT(
7927 const VkPrivateDataSlotCreateInfoEXT
* pCreateInfo
,
7928 const VkAllocationCallbacks
* pAllocator
,
7929 VkPrivateDataSlotEXT
* pPrivateDataSlot
)
7931 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7932 return vk_private_data_slot_create(&device
->vk
, pCreateInfo
, pAllocator
,
7936 void radv_DestroyPrivateDataSlotEXT(
7938 VkPrivateDataSlotEXT privateDataSlot
,
7939 const VkAllocationCallbacks
* pAllocator
)
7941 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7942 vk_private_data_slot_destroy(&device
->vk
, privateDataSlot
, pAllocator
);
7945 VkResult
radv_SetPrivateDataEXT(
7947 VkObjectType objectType
,
7948 uint64_t objectHandle
,
7949 VkPrivateDataSlotEXT privateDataSlot
,
7952 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7953 return vk_object_base_set_private_data(&device
->vk
, objectType
,
7954 objectHandle
, privateDataSlot
,
7958 void radv_GetPrivateDataEXT(
7960 VkObjectType objectType
,
7961 uint64_t objectHandle
,
7962 VkPrivateDataSlotEXT privateDataSlot
,
7965 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7966 vk_object_base_get_private_data(&device
->vk
, objectType
, objectHandle
,
7967 privateDataSlot
, pData
);