2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
34 #include "radv_private.h"
36 #include "util/strtod.h"
40 #include <amdgpu_drm.h>
41 #include "amdgpu_id.h"
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
46 #include "util/debug.h"
47 struct radv_dispatch_table dtable
;
50 radv_get_function_timestamp(void *ptr
, uint32_t* timestamp
)
54 if (!dladdr(ptr
, &info
) || !info
.dli_fname
) {
57 if (stat(info
.dli_fname
, &st
)) {
60 *timestamp
= st
.st_mtim
.tv_sec
;
65 radv_device_get_cache_uuid(enum radeon_family family
, void *uuid
)
67 uint32_t mesa_timestamp
, llvm_timestamp
;
69 memset(uuid
, 0, VK_UUID_SIZE
);
70 if (radv_get_function_timestamp(radv_device_get_cache_uuid
, &mesa_timestamp
) ||
71 radv_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo
, &llvm_timestamp
))
74 memcpy(uuid
, &mesa_timestamp
, 4);
75 memcpy((char*)uuid
+ 4, &llvm_timestamp
, 4);
76 memcpy((char*)uuid
+ 8, &f
, 2);
77 snprintf((char*)uuid
+ 10, VK_UUID_SIZE
- 10, "radv");
81 static const VkExtensionProperties instance_extensions
[] = {
83 .extensionName
= VK_KHR_SURFACE_EXTENSION_NAME
,
86 #ifdef VK_USE_PLATFORM_XCB_KHR
88 .extensionName
= VK_KHR_XCB_SURFACE_EXTENSION_NAME
,
92 #ifdef VK_USE_PLATFORM_XLIB_KHR
94 .extensionName
= VK_KHR_XLIB_SURFACE_EXTENSION_NAME
,
98 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
100 .extensionName
= VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME
,
106 static const VkExtensionProperties common_device_extensions
[] = {
108 .extensionName
= VK_KHR_MAINTENANCE1_EXTENSION_NAME
,
112 .extensionName
= VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME
,
116 .extensionName
= VK_KHR_SWAPCHAIN_EXTENSION_NAME
,
120 .extensionName
= VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME
,
124 .extensionName
= VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2_EXTENSION_NAME
,
128 .extensionName
= VK_KHR_SHADER_DRAW_PARAMETERS_EXTENSION_NAME
,
134 radv_extensions_register(struct radv_instance
*instance
,
135 struct radv_extensions
*extensions
,
136 const VkExtensionProperties
*new_ext
,
140 VkExtensionProperties
*new_ptr
;
142 assert(new_ext
&& num_ext
> 0);
145 return VK_ERROR_INITIALIZATION_FAILED
;
147 new_size
= (extensions
->num_ext
+ num_ext
) * sizeof(VkExtensionProperties
);
148 new_ptr
= vk_realloc(&instance
->alloc
, extensions
->ext_array
,
149 new_size
, 8, VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
151 /* Old array continues to be valid, update nothing */
153 return VK_ERROR_OUT_OF_HOST_MEMORY
;
155 memcpy(&new_ptr
[extensions
->num_ext
], new_ext
,
156 num_ext
* sizeof(VkExtensionProperties
));
157 extensions
->ext_array
= new_ptr
;
158 extensions
->num_ext
+= num_ext
;
164 radv_extensions_finish(struct radv_instance
*instance
,
165 struct radv_extensions
*extensions
)
170 radv_loge("Attemted to free invalid extension struct\n");
172 if (extensions
->ext_array
)
173 vk_free(&instance
->alloc
, extensions
->ext_array
);
177 is_extension_enabled(const VkExtensionProperties
*extensions
,
181 assert(extensions
&& name
);
183 for (uint32_t i
= 0; i
< num_ext
; i
++) {
184 if (strcmp(name
, extensions
[i
].extensionName
) == 0)
192 radv_physical_device_init(struct radv_physical_device
*device
,
193 struct radv_instance
*instance
,
197 drmVersionPtr version
;
200 fd
= open(path
, O_RDWR
| O_CLOEXEC
);
202 return VK_ERROR_INCOMPATIBLE_DRIVER
;
204 version
= drmGetVersion(fd
);
207 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER
,
208 "failed to get version %s: %m", path
);
211 if (strcmp(version
->name
, "amdgpu")) {
212 drmFreeVersion(version
);
214 return VK_ERROR_INCOMPATIBLE_DRIVER
;
216 drmFreeVersion(version
);
218 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
219 device
->instance
= instance
;
220 assert(strlen(path
) < ARRAY_SIZE(device
->path
));
221 strncpy(device
->path
, path
, ARRAY_SIZE(device
->path
));
223 device
->ws
= radv_amdgpu_winsys_create(fd
);
225 result
= VK_ERROR_INCOMPATIBLE_DRIVER
;
228 device
->ws
->query_info(device
->ws
, &device
->rad_info
);
229 result
= radv_init_wsi(device
);
230 if (result
!= VK_SUCCESS
) {
231 device
->ws
->destroy(device
->ws
);
235 if (radv_device_get_cache_uuid(device
->rad_info
.family
, device
->uuid
)) {
236 radv_finish_wsi(device
);
237 device
->ws
->destroy(device
->ws
);
238 result
= vk_errorf(VK_ERROR_INITIALIZATION_FAILED
,
239 "cannot generate UUID");
243 result
= radv_extensions_register(instance
,
245 common_device_extensions
,
246 ARRAY_SIZE(common_device_extensions
));
247 if (result
!= VK_SUCCESS
)
250 fprintf(stderr
, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
251 device
->name
= device
->rad_info
.name
;
261 radv_physical_device_finish(struct radv_physical_device
*device
)
263 radv_extensions_finish(device
->instance
, &device
->extensions
);
264 radv_finish_wsi(device
);
265 device
->ws
->destroy(device
->ws
);
270 default_alloc_func(void *pUserData
, size_t size
, size_t align
,
271 VkSystemAllocationScope allocationScope
)
277 default_realloc_func(void *pUserData
, void *pOriginal
, size_t size
,
278 size_t align
, VkSystemAllocationScope allocationScope
)
280 return realloc(pOriginal
, size
);
284 default_free_func(void *pUserData
, void *pMemory
)
289 static const VkAllocationCallbacks default_alloc
= {
291 .pfnAllocation
= default_alloc_func
,
292 .pfnReallocation
= default_realloc_func
,
293 .pfnFree
= default_free_func
,
296 static const struct debug_control radv_debug_options
[] = {
297 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS
},
298 {"nodcc", RADV_DEBUG_NO_DCC
},
299 {"shaders", RADV_DEBUG_DUMP_SHADERS
},
300 {"nocache", RADV_DEBUG_NO_CACHE
},
301 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS
},
302 {"nohiz", RADV_DEBUG_NO_HIZ
},
303 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE
},
304 {"unsafemath", RADV_DEBUG_UNSAFE_MATH
},
308 VkResult
radv_CreateInstance(
309 const VkInstanceCreateInfo
* pCreateInfo
,
310 const VkAllocationCallbacks
* pAllocator
,
311 VkInstance
* pInstance
)
313 struct radv_instance
*instance
;
315 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO
);
317 uint32_t client_version
;
318 if (pCreateInfo
->pApplicationInfo
&&
319 pCreateInfo
->pApplicationInfo
->apiVersion
!= 0) {
320 client_version
= pCreateInfo
->pApplicationInfo
->apiVersion
;
322 client_version
= VK_MAKE_VERSION(1, 0, 0);
325 if (VK_MAKE_VERSION(1, 0, 0) > client_version
||
326 client_version
> VK_MAKE_VERSION(1, 0, 0xfff)) {
327 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER
,
328 "Client requested version %d.%d.%d",
329 VK_VERSION_MAJOR(client_version
),
330 VK_VERSION_MINOR(client_version
),
331 VK_VERSION_PATCH(client_version
));
334 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
335 if (!is_extension_enabled(instance_extensions
,
336 ARRAY_SIZE(instance_extensions
),
337 pCreateInfo
->ppEnabledExtensionNames
[i
]))
338 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT
);
341 instance
= vk_alloc2(&default_alloc
, pAllocator
, sizeof(*instance
), 8,
342 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
344 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
346 memset(instance
, 0, sizeof(*instance
));
348 instance
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
351 instance
->alloc
= *pAllocator
;
353 instance
->alloc
= default_alloc
;
355 instance
->apiVersion
= client_version
;
356 instance
->physicalDeviceCount
= -1;
360 VG(VALGRIND_CREATE_MEMPOOL(instance
, 0, false));
362 instance
->debug_flags
= parse_debug_string(getenv("RADV_DEBUG"),
365 *pInstance
= radv_instance_to_handle(instance
);
370 void radv_DestroyInstance(
371 VkInstance _instance
,
372 const VkAllocationCallbacks
* pAllocator
)
374 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
376 for (int i
= 0; i
< instance
->physicalDeviceCount
; ++i
) {
377 radv_physical_device_finish(instance
->physicalDevices
+ i
);
380 VG(VALGRIND_DESTROY_MEMPOOL(instance
));
384 vk_free(&instance
->alloc
, instance
);
387 VkResult
radv_EnumeratePhysicalDevices(
388 VkInstance _instance
,
389 uint32_t* pPhysicalDeviceCount
,
390 VkPhysicalDevice
* pPhysicalDevices
)
392 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
395 if (instance
->physicalDeviceCount
< 0) {
397 instance
->physicalDeviceCount
= 0;
398 for (unsigned i
= 0; i
< RADV_MAX_DRM_DEVICES
; i
++) {
399 snprintf(path
, sizeof(path
), "/dev/dri/renderD%d", 128 + i
);
400 result
= radv_physical_device_init(instance
->physicalDevices
+
401 instance
->physicalDeviceCount
,
403 if (result
== VK_SUCCESS
)
404 ++instance
->physicalDeviceCount
;
405 else if (result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
410 if (!pPhysicalDevices
) {
411 *pPhysicalDeviceCount
= instance
->physicalDeviceCount
;
413 *pPhysicalDeviceCount
= MIN2(*pPhysicalDeviceCount
, instance
->physicalDeviceCount
);
414 for (unsigned i
= 0; i
< *pPhysicalDeviceCount
; ++i
)
415 pPhysicalDevices
[i
] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
418 return *pPhysicalDeviceCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
422 void radv_GetPhysicalDeviceFeatures(
423 VkPhysicalDevice physicalDevice
,
424 VkPhysicalDeviceFeatures
* pFeatures
)
426 // RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
428 memset(pFeatures
, 0, sizeof(*pFeatures
));
430 *pFeatures
= (VkPhysicalDeviceFeatures
) {
431 .robustBufferAccess
= true,
432 .fullDrawIndexUint32
= true,
433 .imageCubeArray
= true,
434 .independentBlend
= true,
435 .geometryShader
= true,
436 .tessellationShader
= false,
437 .sampleRateShading
= false,
438 .dualSrcBlend
= true,
440 .multiDrawIndirect
= true,
441 .drawIndirectFirstInstance
= true,
443 .depthBiasClamp
= true,
444 .fillModeNonSolid
= true,
449 .multiViewport
= true,
450 .samplerAnisotropy
= true,
451 .textureCompressionETC2
= false,
452 .textureCompressionASTC_LDR
= false,
453 .textureCompressionBC
= true,
454 .occlusionQueryPrecise
= true,
455 .pipelineStatisticsQuery
= false,
456 .vertexPipelineStoresAndAtomics
= true,
457 .fragmentStoresAndAtomics
= true,
458 .shaderTessellationAndGeometryPointSize
= true,
459 .shaderImageGatherExtended
= true,
460 .shaderStorageImageExtendedFormats
= true,
461 .shaderStorageImageMultisample
= false,
462 .shaderUniformBufferArrayDynamicIndexing
= true,
463 .shaderSampledImageArrayDynamicIndexing
= true,
464 .shaderStorageBufferArrayDynamicIndexing
= true,
465 .shaderStorageImageArrayDynamicIndexing
= true,
466 .shaderStorageImageReadWithoutFormat
= false,
467 .shaderStorageImageWriteWithoutFormat
= false,
468 .shaderClipDistance
= true,
469 .shaderCullDistance
= true,
470 .shaderFloat64
= true,
471 .shaderInt64
= false,
472 .shaderInt16
= false,
474 .variableMultisampleRate
= false,
475 .inheritedQueries
= false,
479 void radv_GetPhysicalDeviceFeatures2KHR(
480 VkPhysicalDevice physicalDevice
,
481 VkPhysicalDeviceFeatures2KHR
*pFeatures
)
483 return radv_GetPhysicalDeviceFeatures(physicalDevice
, &pFeatures
->features
);
486 void radv_GetPhysicalDeviceProperties(
487 VkPhysicalDevice physicalDevice
,
488 VkPhysicalDeviceProperties
* pProperties
)
490 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
491 VkSampleCountFlags sample_counts
= 0xf;
492 VkPhysicalDeviceLimits limits
= {
493 .maxImageDimension1D
= (1 << 14),
494 .maxImageDimension2D
= (1 << 14),
495 .maxImageDimension3D
= (1 << 11),
496 .maxImageDimensionCube
= (1 << 14),
497 .maxImageArrayLayers
= (1 << 11),
498 .maxTexelBufferElements
= 128 * 1024 * 1024,
499 .maxUniformBufferRange
= UINT32_MAX
,
500 .maxStorageBufferRange
= UINT32_MAX
,
501 .maxPushConstantsSize
= MAX_PUSH_CONSTANTS_SIZE
,
502 .maxMemoryAllocationCount
= UINT32_MAX
,
503 .maxSamplerAllocationCount
= 64 * 1024,
504 .bufferImageGranularity
= 64, /* A cache line */
505 .sparseAddressSpaceSize
= 0,
506 .maxBoundDescriptorSets
= MAX_SETS
,
507 .maxPerStageDescriptorSamplers
= 64,
508 .maxPerStageDescriptorUniformBuffers
= 64,
509 .maxPerStageDescriptorStorageBuffers
= 64,
510 .maxPerStageDescriptorSampledImages
= 64,
511 .maxPerStageDescriptorStorageImages
= 64,
512 .maxPerStageDescriptorInputAttachments
= 64,
513 .maxPerStageResources
= 128,
514 .maxDescriptorSetSamplers
= 256,
515 .maxDescriptorSetUniformBuffers
= 256,
516 .maxDescriptorSetUniformBuffersDynamic
= 256,
517 .maxDescriptorSetStorageBuffers
= 256,
518 .maxDescriptorSetStorageBuffersDynamic
= 256,
519 .maxDescriptorSetSampledImages
= 256,
520 .maxDescriptorSetStorageImages
= 256,
521 .maxDescriptorSetInputAttachments
= 256,
522 .maxVertexInputAttributes
= 32,
523 .maxVertexInputBindings
= 32,
524 .maxVertexInputAttributeOffset
= 2047,
525 .maxVertexInputBindingStride
= 2048,
526 .maxVertexOutputComponents
= 128,
527 .maxTessellationGenerationLevel
= 0,
528 .maxTessellationPatchSize
= 0,
529 .maxTessellationControlPerVertexInputComponents
= 0,
530 .maxTessellationControlPerVertexOutputComponents
= 0,
531 .maxTessellationControlPerPatchOutputComponents
= 0,
532 .maxTessellationControlTotalOutputComponents
= 0,
533 .maxTessellationEvaluationInputComponents
= 0,
534 .maxTessellationEvaluationOutputComponents
= 0,
535 .maxGeometryShaderInvocations
= 32,
536 .maxGeometryInputComponents
= 64,
537 .maxGeometryOutputComponents
= 128,
538 .maxGeometryOutputVertices
= 256,
539 .maxGeometryTotalOutputComponents
= 1024,
540 .maxFragmentInputComponents
= 128,
541 .maxFragmentOutputAttachments
= 8,
542 .maxFragmentDualSrcAttachments
= 1,
543 .maxFragmentCombinedOutputResources
= 8,
544 .maxComputeSharedMemorySize
= 32768,
545 .maxComputeWorkGroupCount
= { 65535, 65535, 65535 },
546 .maxComputeWorkGroupInvocations
= 2048,
547 .maxComputeWorkGroupSize
= {
552 .subPixelPrecisionBits
= 4 /* FIXME */,
553 .subTexelPrecisionBits
= 4 /* FIXME */,
554 .mipmapPrecisionBits
= 4 /* FIXME */,
555 .maxDrawIndexedIndexValue
= UINT32_MAX
,
556 .maxDrawIndirectCount
= UINT32_MAX
,
557 .maxSamplerLodBias
= 16,
558 .maxSamplerAnisotropy
= 16,
559 .maxViewports
= MAX_VIEWPORTS
,
560 .maxViewportDimensions
= { (1 << 14), (1 << 14) },
561 .viewportBoundsRange
= { INT16_MIN
, INT16_MAX
},
562 .viewportSubPixelBits
= 13, /* We take a float? */
563 .minMemoryMapAlignment
= 4096, /* A page */
564 .minTexelBufferOffsetAlignment
= 1,
565 .minUniformBufferOffsetAlignment
= 4,
566 .minStorageBufferOffsetAlignment
= 4,
567 .minTexelOffset
= -32,
568 .maxTexelOffset
= 31,
569 .minTexelGatherOffset
= -32,
570 .maxTexelGatherOffset
= 31,
571 .minInterpolationOffset
= -2,
572 .maxInterpolationOffset
= 2,
573 .subPixelInterpolationOffsetBits
= 8,
574 .maxFramebufferWidth
= (1 << 14),
575 .maxFramebufferHeight
= (1 << 14),
576 .maxFramebufferLayers
= (1 << 10),
577 .framebufferColorSampleCounts
= sample_counts
,
578 .framebufferDepthSampleCounts
= sample_counts
,
579 .framebufferStencilSampleCounts
= sample_counts
,
580 .framebufferNoAttachmentsSampleCounts
= sample_counts
,
581 .maxColorAttachments
= MAX_RTS
,
582 .sampledImageColorSampleCounts
= sample_counts
,
583 .sampledImageIntegerSampleCounts
= VK_SAMPLE_COUNT_1_BIT
,
584 .sampledImageDepthSampleCounts
= sample_counts
,
585 .sampledImageStencilSampleCounts
= sample_counts
,
586 .storageImageSampleCounts
= VK_SAMPLE_COUNT_1_BIT
,
587 .maxSampleMaskWords
= 1,
588 .timestampComputeAndGraphics
= false,
589 .timestampPeriod
= 100000.0 / pdevice
->rad_info
.clock_crystal_freq
,
590 .maxClipDistances
= 8,
591 .maxCullDistances
= 8,
592 .maxCombinedClipAndCullDistances
= 8,
593 .discreteQueuePriorities
= 1,
594 .pointSizeRange
= { 0.125, 255.875 },
595 .lineWidthRange
= { 0.0, 7.9921875 },
596 .pointSizeGranularity
= (1.0 / 8.0),
597 .lineWidthGranularity
= (1.0 / 128.0),
598 .strictLines
= false, /* FINISHME */
599 .standardSampleLocations
= true,
600 .optimalBufferCopyOffsetAlignment
= 128,
601 .optimalBufferCopyRowPitchAlignment
= 128,
602 .nonCoherentAtomSize
= 64,
605 *pProperties
= (VkPhysicalDeviceProperties
) {
606 .apiVersion
= VK_MAKE_VERSION(1, 0, 5),
609 .deviceID
= pdevice
->rad_info
.pci_id
,
610 .deviceType
= VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU
,
612 .sparseProperties
= {0}, /* Broadwell doesn't do sparse. */
615 strcpy(pProperties
->deviceName
, pdevice
->name
);
616 memcpy(pProperties
->pipelineCacheUUID
, pdevice
->uuid
, VK_UUID_SIZE
);
619 void radv_GetPhysicalDeviceProperties2KHR(
620 VkPhysicalDevice physicalDevice
,
621 VkPhysicalDeviceProperties2KHR
*pProperties
)
623 return radv_GetPhysicalDeviceProperties(physicalDevice
, &pProperties
->properties
);
626 static void radv_get_physical_device_queue_family_properties(
627 struct radv_physical_device
* pdevice
,
629 VkQueueFamilyProperties
** pQueueFamilyProperties
)
631 int num_queue_families
= 1;
633 if (pdevice
->rad_info
.compute_rings
> 0 &&
634 pdevice
->rad_info
.chip_class
>= CIK
&&
635 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
))
636 num_queue_families
++;
638 if (pQueueFamilyProperties
== NULL
) {
639 *pCount
= num_queue_families
;
648 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
649 .queueFlags
= VK_QUEUE_GRAPHICS_BIT
|
650 VK_QUEUE_COMPUTE_BIT
|
651 VK_QUEUE_TRANSFER_BIT
,
653 .timestampValidBits
= 64,
654 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
659 if (pdevice
->rad_info
.compute_rings
> 0 &&
660 pdevice
->rad_info
.chip_class
>= CIK
&&
661 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
)) {
663 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
664 .queueFlags
= VK_QUEUE_COMPUTE_BIT
| VK_QUEUE_TRANSFER_BIT
,
665 .queueCount
= pdevice
->rad_info
.compute_rings
,
666 .timestampValidBits
= 64,
667 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
675 void radv_GetPhysicalDeviceQueueFamilyProperties(
676 VkPhysicalDevice physicalDevice
,
678 VkQueueFamilyProperties
* pQueueFamilyProperties
)
680 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
681 if (!pQueueFamilyProperties
) {
682 return radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
685 VkQueueFamilyProperties
*properties
[] = {
686 pQueueFamilyProperties
+ 0,
687 pQueueFamilyProperties
+ 1,
688 pQueueFamilyProperties
+ 2,
690 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
691 assert(*pCount
<= 3);
694 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
695 VkPhysicalDevice physicalDevice
,
697 VkQueueFamilyProperties2KHR
*pQueueFamilyProperties
)
699 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
700 if (!pQueueFamilyProperties
) {
701 return radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
704 VkQueueFamilyProperties
*properties
[] = {
705 &pQueueFamilyProperties
[0].queueFamilyProperties
,
706 &pQueueFamilyProperties
[1].queueFamilyProperties
,
707 &pQueueFamilyProperties
[2].queueFamilyProperties
,
709 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
710 assert(*pCount
<= 3);
713 void radv_GetPhysicalDeviceMemoryProperties(
714 VkPhysicalDevice physicalDevice
,
715 VkPhysicalDeviceMemoryProperties
*pMemoryProperties
)
717 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
719 STATIC_ASSERT(RADV_MEM_TYPE_COUNT
<= VK_MAX_MEMORY_TYPES
);
721 pMemoryProperties
->memoryTypeCount
= RADV_MEM_TYPE_COUNT
;
722 pMemoryProperties
->memoryTypes
[RADV_MEM_TYPE_VRAM
] = (VkMemoryType
) {
723 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
,
724 .heapIndex
= RADV_MEM_HEAP_VRAM
,
726 pMemoryProperties
->memoryTypes
[RADV_MEM_TYPE_GTT_WRITE_COMBINE
] = (VkMemoryType
) {
727 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
728 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
729 .heapIndex
= RADV_MEM_HEAP_GTT
,
731 pMemoryProperties
->memoryTypes
[RADV_MEM_TYPE_VRAM_CPU_ACCESS
] = (VkMemoryType
) {
732 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
733 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
734 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
735 .heapIndex
= RADV_MEM_HEAP_VRAM_CPU_ACCESS
,
737 pMemoryProperties
->memoryTypes
[RADV_MEM_TYPE_GTT_CACHED
] = (VkMemoryType
) {
738 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
739 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
740 VK_MEMORY_PROPERTY_HOST_CACHED_BIT
,
741 .heapIndex
= RADV_MEM_HEAP_GTT
,
744 STATIC_ASSERT(RADV_MEM_HEAP_COUNT
<= VK_MAX_MEMORY_HEAPS
);
746 pMemoryProperties
->memoryHeapCount
= RADV_MEM_HEAP_COUNT
;
747 pMemoryProperties
->memoryHeaps
[RADV_MEM_HEAP_VRAM
] = (VkMemoryHeap
) {
748 .size
= physical_device
->rad_info
.vram_size
-
749 physical_device
->rad_info
.visible_vram_size
,
750 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
752 pMemoryProperties
->memoryHeaps
[RADV_MEM_HEAP_VRAM_CPU_ACCESS
] = (VkMemoryHeap
) {
753 .size
= physical_device
->rad_info
.visible_vram_size
,
754 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
756 pMemoryProperties
->memoryHeaps
[RADV_MEM_HEAP_GTT
] = (VkMemoryHeap
) {
757 .size
= physical_device
->rad_info
.gart_size
,
762 void radv_GetPhysicalDeviceMemoryProperties2KHR(
763 VkPhysicalDevice physicalDevice
,
764 VkPhysicalDeviceMemoryProperties2KHR
*pMemoryProperties
)
766 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice
,
767 &pMemoryProperties
->memoryProperties
);
771 radv_queue_init(struct radv_device
*device
, struct radv_queue
*queue
,
772 int queue_family_index
, int idx
)
774 queue
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
775 queue
->device
= device
;
776 queue
->queue_family_index
= queue_family_index
;
777 queue
->queue_idx
= idx
;
779 queue
->hw_ctx
= device
->ws
->ctx_create(device
->ws
);
781 return VK_ERROR_OUT_OF_HOST_MEMORY
;
787 radv_queue_finish(struct radv_queue
*queue
)
790 queue
->device
->ws
->ctx_destroy(queue
->hw_ctx
);
792 if (queue
->preamble_cs
)
793 queue
->device
->ws
->cs_destroy(queue
->preamble_cs
);
794 if (queue
->descriptor_bo
)
795 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
796 if (queue
->scratch_bo
)
797 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
798 if (queue
->esgs_ring_bo
)
799 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
800 if (queue
->gsvs_ring_bo
)
801 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
802 if (queue
->compute_scratch_bo
)
803 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
807 radv_device_init_gs_info(struct radv_device
*device
)
809 switch (device
->physical_device
->rad_info
.family
) {
818 device
->gs_table_depth
= 16;
829 device
->gs_table_depth
= 32;
832 unreachable("unknown GPU");
836 VkResult
radv_CreateDevice(
837 VkPhysicalDevice physicalDevice
,
838 const VkDeviceCreateInfo
* pCreateInfo
,
839 const VkAllocationCallbacks
* pAllocator
,
842 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
844 struct radv_device
*device
;
846 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
847 if (!is_extension_enabled(physical_device
->extensions
.ext_array
,
848 physical_device
->extensions
.num_ext
,
849 pCreateInfo
->ppEnabledExtensionNames
[i
]))
850 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT
);
853 device
= vk_alloc2(&physical_device
->instance
->alloc
, pAllocator
,
855 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
857 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
859 memset(device
, 0, sizeof(*device
));
861 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
862 device
->instance
= physical_device
->instance
;
863 device
->physical_device
= physical_device
;
865 device
->debug_flags
= device
->instance
->debug_flags
;
867 device
->ws
= physical_device
->ws
;
869 device
->alloc
= *pAllocator
;
871 device
->alloc
= physical_device
->instance
->alloc
;
873 for (unsigned i
= 0; i
< pCreateInfo
->queueCreateInfoCount
; i
++) {
874 const VkDeviceQueueCreateInfo
*queue_create
= &pCreateInfo
->pQueueCreateInfos
[i
];
875 uint32_t qfi
= queue_create
->queueFamilyIndex
;
877 device
->queues
[qfi
] = vk_alloc(&device
->alloc
,
878 queue_create
->queueCount
* sizeof(struct radv_queue
), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
879 if (!device
->queues
[qfi
]) {
880 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
884 memset(device
->queues
[qfi
], 0, queue_create
->queueCount
* sizeof(struct radv_queue
));
886 device
->queue_count
[qfi
] = queue_create
->queueCount
;
888 for (unsigned q
= 0; q
< queue_create
->queueCount
; q
++) {
889 result
= radv_queue_init(device
, &device
->queues
[qfi
][q
], qfi
, q
);
890 if (result
!= VK_SUCCESS
)
895 #if HAVE_LLVM < 0x0400
896 device
->llvm_supports_spill
= false;
898 device
->llvm_supports_spill
= true;
901 /* The maximum number of scratch waves. Scratch space isn't divided
902 * evenly between CUs. The number is only a function of the number of CUs.
903 * We can decrease the constant to decrease the scratch buffer size.
905 * sctx->scratch_waves must be >= the maximum posible size of
906 * 1 threadgroup, so that the hw doesn't hang from being unable
909 * The recommended value is 4 per CU at most. Higher numbers don't
910 * bring much benefit, but they still occupy chip resources (think
911 * async compute). I've seen ~2% performance difference between 4 and 32.
913 uint32_t max_threads_per_block
= 2048;
914 device
->scratch_waves
= MAX2(32 * physical_device
->rad_info
.num_good_compute_units
,
915 max_threads_per_block
/ 64);
917 radv_device_init_gs_info(device
);
919 result
= radv_device_init_meta(device
);
920 if (result
!= VK_SUCCESS
)
923 radv_device_init_msaa(device
);
925 for (int family
= 0; family
< RADV_MAX_QUEUE_FAMILIES
; ++family
) {
926 device
->empty_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
928 case RADV_QUEUE_GENERAL
:
929 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
930 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_LOAD_ENABLE(1));
931 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_SHADOW_ENABLE(1));
933 case RADV_QUEUE_COMPUTE
:
934 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_NOP
, 0, 0));
935 radeon_emit(device
->empty_cs
[family
], 0);
938 device
->ws
->cs_finalize(device
->empty_cs
[family
]);
941 if (getenv("RADV_TRACE_FILE")) {
942 device
->trace_bo
= device
->ws
->buffer_create(device
->ws
, 4096, 8,
943 RADEON_DOMAIN_VRAM
, RADEON_FLAG_CPU_ACCESS
);
944 if (!device
->trace_bo
)
947 device
->trace_id_ptr
= device
->ws
->buffer_map(device
->trace_bo
);
948 if (!device
->trace_id_ptr
)
952 if (device
->physical_device
->rad_info
.chip_class
>= CIK
)
953 cik_create_gfx_config(device
);
955 *pDevice
= radv_device_to_handle(device
);
959 if (device
->trace_bo
)
960 device
->ws
->buffer_destroy(device
->trace_bo
);
962 if (device
->gfx_init
)
963 device
->ws
->buffer_destroy(device
->gfx_init
);
965 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
966 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
967 radv_queue_finish(&device
->queues
[i
][q
]);
968 if (device
->queue_count
[i
])
969 vk_free(&device
->alloc
, device
->queues
[i
]);
972 vk_free(&device
->alloc
, device
);
976 void radv_DestroyDevice(
978 const VkAllocationCallbacks
* pAllocator
)
980 RADV_FROM_HANDLE(radv_device
, device
, _device
);
982 if (device
->trace_bo
)
983 device
->ws
->buffer_destroy(device
->trace_bo
);
985 if (device
->gfx_init
)
986 device
->ws
->buffer_destroy(device
->gfx_init
);
988 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
989 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
990 radv_queue_finish(&device
->queues
[i
][q
]);
991 if (device
->queue_count
[i
])
992 vk_free(&device
->alloc
, device
->queues
[i
]);
994 radv_device_finish_meta(device
);
996 vk_free(&device
->alloc
, device
);
999 VkResult
radv_EnumerateInstanceExtensionProperties(
1000 const char* pLayerName
,
1001 uint32_t* pPropertyCount
,
1002 VkExtensionProperties
* pProperties
)
1004 if (pProperties
== NULL
) {
1005 *pPropertyCount
= ARRAY_SIZE(instance_extensions
);
1009 *pPropertyCount
= MIN2(*pPropertyCount
, ARRAY_SIZE(instance_extensions
));
1010 typed_memcpy(pProperties
, instance_extensions
, *pPropertyCount
);
1012 if (*pPropertyCount
< ARRAY_SIZE(instance_extensions
))
1013 return VK_INCOMPLETE
;
1018 VkResult
radv_EnumerateDeviceExtensionProperties(
1019 VkPhysicalDevice physicalDevice
,
1020 const char* pLayerName
,
1021 uint32_t* pPropertyCount
,
1022 VkExtensionProperties
* pProperties
)
1024 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1026 if (pProperties
== NULL
) {
1027 *pPropertyCount
= pdevice
->extensions
.num_ext
;
1031 *pPropertyCount
= MIN2(*pPropertyCount
, pdevice
->extensions
.num_ext
);
1032 typed_memcpy(pProperties
, pdevice
->extensions
.ext_array
, *pPropertyCount
);
1034 if (*pPropertyCount
< pdevice
->extensions
.num_ext
)
1035 return VK_INCOMPLETE
;
1040 VkResult
radv_EnumerateInstanceLayerProperties(
1041 uint32_t* pPropertyCount
,
1042 VkLayerProperties
* pProperties
)
1044 if (pProperties
== NULL
) {
1045 *pPropertyCount
= 0;
1049 /* None supported at this time */
1050 return vk_error(VK_ERROR_LAYER_NOT_PRESENT
);
1053 VkResult
radv_EnumerateDeviceLayerProperties(
1054 VkPhysicalDevice physicalDevice
,
1055 uint32_t* pPropertyCount
,
1056 VkLayerProperties
* pProperties
)
1058 if (pProperties
== NULL
) {
1059 *pPropertyCount
= 0;
1063 /* None supported at this time */
1064 return vk_error(VK_ERROR_LAYER_NOT_PRESENT
);
1067 void radv_GetDeviceQueue(
1069 uint32_t queueFamilyIndex
,
1070 uint32_t queueIndex
,
1073 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1075 *pQueue
= radv_queue_to_handle(&device
->queues
[queueFamilyIndex
][queueIndex
]);
1078 static void radv_dump_trace(struct radv_device
*device
,
1079 struct radeon_winsys_cs
*cs
)
1081 const char *filename
= getenv("RADV_TRACE_FILE");
1082 FILE *f
= fopen(filename
, "w");
1084 fprintf(stderr
, "Failed to write trace dump to %s\n", filename
);
1088 fprintf(f
, "Trace ID: %x\n", *device
->trace_id_ptr
);
1089 device
->ws
->cs_dump(cs
, f
, *device
->trace_id_ptr
);
1094 fill_geom_rings(struct radv_queue
*queue
,
1096 uint32_t esgs_ring_size
,
1097 struct radeon_winsys_bo
*esgs_ring_bo
,
1098 uint32_t gsvs_ring_size
,
1099 struct radeon_winsys_bo
*gsvs_ring_bo
)
1101 uint64_t esgs_va
= 0, gsvs_va
= 0;
1102 uint32_t *desc
= &map
[4];
1105 esgs_va
= queue
->device
->ws
->buffer_get_va(esgs_ring_bo
);
1107 gsvs_va
= queue
->device
->ws
->buffer_get_va(gsvs_ring_bo
);
1109 /* stride 0, num records - size, add tid, swizzle, elsize4,
1112 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32) |
1113 S_008F04_STRIDE(0) |
1114 S_008F04_SWIZZLE_ENABLE(true);
1115 desc
[2] = esgs_ring_size
;
1116 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1117 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1118 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1119 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1120 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1121 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1122 S_008F0C_ELEMENT_SIZE(1) |
1123 S_008F0C_INDEX_STRIDE(3) |
1124 S_008F0C_ADD_TID_ENABLE(true);
1127 /* GS entry for ES->GS ring */
1128 /* stride 0, num records - size, elsize0,
1131 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32)|
1132 S_008F04_STRIDE(0) |
1133 S_008F04_SWIZZLE_ENABLE(false);
1134 desc
[2] = esgs_ring_size
;
1135 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1136 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1137 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1138 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1139 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1140 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1141 S_008F0C_ELEMENT_SIZE(0) |
1142 S_008F0C_INDEX_STRIDE(0) |
1143 S_008F0C_ADD_TID_ENABLE(false);
1146 /* VS entry for GS->VS ring */
1147 /* stride 0, num records - size, elsize0,
1150 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32)|
1151 S_008F04_STRIDE(0) |
1152 S_008F04_SWIZZLE_ENABLE(false);
1153 desc
[2] = gsvs_ring_size
;
1154 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1155 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1156 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1157 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1158 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1159 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1160 S_008F0C_ELEMENT_SIZE(0) |
1161 S_008F0C_INDEX_STRIDE(0) |
1162 S_008F0C_ADD_TID_ENABLE(false);
1165 /* stride gsvs_itemsize, num records 64
1166 elsize 4, index stride 16 */
1167 /* shader will patch stride and desc[2] */
1169 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32)|
1170 S_008F04_STRIDE(0) |
1171 S_008F04_SWIZZLE_ENABLE(true);
1173 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1174 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1175 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1176 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1177 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1178 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1179 S_008F0C_ELEMENT_SIZE(1) |
1180 S_008F0C_INDEX_STRIDE(1) |
1181 S_008F0C_ADD_TID_ENABLE(true);
1185 radv_get_preamble_cs(struct radv_queue
*queue
,
1186 uint32_t scratch_size
,
1187 uint32_t compute_scratch_size
,
1188 uint32_t esgs_ring_size
,
1189 uint32_t gsvs_ring_size
,
1190 struct radeon_winsys_cs
**preamble_cs
)
1192 struct radeon_winsys_bo
*scratch_bo
= NULL
;
1193 struct radeon_winsys_bo
*descriptor_bo
= NULL
;
1194 struct radeon_winsys_bo
*compute_scratch_bo
= NULL
;
1195 struct radeon_winsys_bo
*esgs_ring_bo
= NULL
;
1196 struct radeon_winsys_bo
*gsvs_ring_bo
= NULL
;
1197 struct radeon_winsys_cs
*cs
= NULL
;
1199 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
) {
1200 *preamble_cs
= NULL
;
1204 if (scratch_size
<= queue
->scratch_size
&&
1205 compute_scratch_size
<= queue
->compute_scratch_size
&&
1206 esgs_ring_size
<= queue
->esgs_ring_size
&&
1207 gsvs_ring_size
<= queue
->gsvs_ring_size
) {
1208 *preamble_cs
= queue
->preamble_cs
;
1212 if (scratch_size
> queue
->scratch_size
) {
1213 scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1217 RADEON_FLAG_NO_CPU_ACCESS
);
1221 scratch_bo
= queue
->scratch_bo
;
1223 if (compute_scratch_size
> queue
->compute_scratch_size
) {
1224 compute_scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1225 compute_scratch_size
,
1228 RADEON_FLAG_NO_CPU_ACCESS
);
1229 if (!compute_scratch_bo
)
1233 compute_scratch_bo
= queue
->compute_scratch_bo
;
1235 if (esgs_ring_size
> queue
->esgs_ring_size
) {
1236 esgs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1240 RADEON_FLAG_NO_CPU_ACCESS
);
1244 esgs_ring_bo
= queue
->esgs_ring_bo
;
1245 esgs_ring_size
= queue
->esgs_ring_size
;
1248 if (gsvs_ring_size
> queue
->gsvs_ring_size
) {
1249 gsvs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1253 RADEON_FLAG_NO_CPU_ACCESS
);
1257 gsvs_ring_bo
= queue
->gsvs_ring_bo
;
1258 gsvs_ring_size
= queue
->gsvs_ring_size
;
1261 if (scratch_bo
!= queue
->scratch_bo
||
1262 esgs_ring_bo
!= queue
->esgs_ring_bo
||
1263 gsvs_ring_bo
!= queue
->gsvs_ring_bo
) {
1265 if (gsvs_ring_bo
|| esgs_ring_bo
)
1266 size
= 80; /* 2 dword + 2 padding + 4 dword * 4 */
1267 else if (scratch_bo
)
1268 size
= 8; /* 2 dword */
1270 descriptor_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1274 RADEON_FLAG_CPU_ACCESS
);
1278 descriptor_bo
= queue
->descriptor_bo
;
1280 cs
= queue
->device
->ws
->cs_create(queue
->device
->ws
,
1281 queue
->queue_family_index
? RING_COMPUTE
: RING_GFX
);
1287 queue
->device
->ws
->cs_add_buffer(cs
, scratch_bo
, 8);
1290 queue
->device
->ws
->cs_add_buffer(cs
, esgs_ring_bo
, 8);
1293 queue
->device
->ws
->cs_add_buffer(cs
, gsvs_ring_bo
, 8);
1296 queue
->device
->ws
->cs_add_buffer(cs
, descriptor_bo
, 8);
1298 if (descriptor_bo
!= queue
->descriptor_bo
) {
1299 uint32_t *map
= (uint32_t*)queue
->device
->ws
->buffer_map(descriptor_bo
);
1302 uint64_t scratch_va
= queue
->device
->ws
->buffer_get_va(scratch_bo
);
1303 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
1304 S_008F04_SWIZZLE_ENABLE(1);
1305 map
[0] = scratch_va
;
1309 if (esgs_ring_bo
|| gsvs_ring_bo
)
1310 fill_geom_rings(queue
, map
, esgs_ring_size
, esgs_ring_bo
, gsvs_ring_size
, gsvs_ring_bo
);
1312 queue
->device
->ws
->buffer_unmap(descriptor_bo
);
1315 if (esgs_ring_bo
|| gsvs_ring_bo
) {
1316 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1317 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
1318 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1319 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
1321 if (queue
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1322 radeon_set_uconfig_reg_seq(cs
, R_030900_VGT_ESGS_RING_SIZE
, 2);
1323 radeon_emit(cs
, esgs_ring_size
>> 8);
1324 radeon_emit(cs
, gsvs_ring_size
>> 8);
1326 radeon_set_config_reg_seq(cs
, R_0088C8_VGT_ESGS_RING_SIZE
, 2);
1327 radeon_emit(cs
, esgs_ring_size
>> 8);
1328 radeon_emit(cs
, gsvs_ring_size
>> 8);
1332 if (descriptor_bo
) {
1333 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
1334 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
1335 R_00B230_SPI_SHADER_USER_DATA_GS_0
,
1336 R_00B330_SPI_SHADER_USER_DATA_ES_0
,
1337 R_00B430_SPI_SHADER_USER_DATA_HS_0
,
1338 R_00B530_SPI_SHADER_USER_DATA_LS_0
};
1340 uint64_t va
= queue
->device
->ws
->buffer_get_va(descriptor_bo
);
1342 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
1343 radeon_set_sh_reg_seq(cs
, regs
[i
], 2);
1344 radeon_emit(cs
, va
);
1345 radeon_emit(cs
, va
>> 32);
1349 if (compute_scratch_bo
) {
1350 uint64_t scratch_va
= queue
->device
->ws
->buffer_get_va(compute_scratch_bo
);
1351 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
1352 S_008F04_SWIZZLE_ENABLE(1);
1354 queue
->device
->ws
->cs_add_buffer(cs
, compute_scratch_bo
, 8);
1356 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, 2);
1357 radeon_emit(cs
, scratch_va
);
1358 radeon_emit(cs
, rsrc1
);
1361 if (!queue
->device
->ws
->cs_finalize(cs
))
1364 if (queue
->preamble_cs
)
1365 queue
->device
->ws
->cs_destroy(queue
->preamble_cs
);
1367 queue
->preamble_cs
= cs
;
1369 if (scratch_bo
!= queue
->scratch_bo
) {
1370 if (queue
->scratch_bo
)
1371 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
1372 queue
->scratch_bo
= scratch_bo
;
1373 queue
->scratch_size
= scratch_size
;
1376 if (compute_scratch_bo
!= queue
->compute_scratch_bo
) {
1377 if (queue
->compute_scratch_bo
)
1378 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
1379 queue
->compute_scratch_bo
= compute_scratch_bo
;
1380 queue
->compute_scratch_size
= compute_scratch_size
;
1383 if (esgs_ring_bo
!= queue
->esgs_ring_bo
) {
1384 if (queue
->esgs_ring_bo
)
1385 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
1386 queue
->esgs_ring_bo
= esgs_ring_bo
;
1387 queue
->esgs_ring_size
= esgs_ring_size
;
1390 if (gsvs_ring_bo
!= queue
->gsvs_ring_bo
) {
1391 if (queue
->gsvs_ring_bo
)
1392 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
1393 queue
->gsvs_ring_bo
= gsvs_ring_bo
;
1394 queue
->gsvs_ring_size
= gsvs_ring_size
;
1397 if (descriptor_bo
!= queue
->descriptor_bo
) {
1398 if (queue
->descriptor_bo
)
1399 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
1401 queue
->descriptor_bo
= descriptor_bo
;
1408 queue
->device
->ws
->cs_destroy(cs
);
1409 if (descriptor_bo
&& descriptor_bo
!= queue
->descriptor_bo
)
1410 queue
->device
->ws
->buffer_destroy(descriptor_bo
);
1411 if (scratch_bo
&& scratch_bo
!= queue
->scratch_bo
)
1412 queue
->device
->ws
->buffer_destroy(scratch_bo
);
1413 if (compute_scratch_bo
&& compute_scratch_bo
!= queue
->compute_scratch_bo
)
1414 queue
->device
->ws
->buffer_destroy(compute_scratch_bo
);
1415 if (esgs_ring_bo
&& esgs_ring_bo
!= queue
->esgs_ring_bo
)
1416 queue
->device
->ws
->buffer_destroy(esgs_ring_bo
);
1417 if (gsvs_ring_bo
&& gsvs_ring_bo
!= queue
->gsvs_ring_bo
)
1418 queue
->device
->ws
->buffer_destroy(gsvs_ring_bo
);
1419 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1422 VkResult
radv_QueueSubmit(
1424 uint32_t submitCount
,
1425 const VkSubmitInfo
* pSubmits
,
1428 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
1429 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
1430 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
1431 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
1433 uint32_t max_cs_submission
= queue
->device
->trace_bo
? 1 : UINT32_MAX
;
1434 uint32_t scratch_size
= 0;
1435 uint32_t compute_scratch_size
= 0;
1436 uint32_t esgs_ring_size
= 0, gsvs_ring_size
= 0;
1437 struct radeon_winsys_cs
*preamble_cs
= NULL
;
1439 bool fence_emitted
= false;
1441 /* Do this first so failing to allocate scratch buffers can't result in
1442 * partially executed submissions. */
1443 for (uint32_t i
= 0; i
< submitCount
; i
++) {
1444 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
1445 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
1446 pSubmits
[i
].pCommandBuffers
[j
]);
1448 scratch_size
= MAX2(scratch_size
, cmd_buffer
->scratch_size_needed
);
1449 compute_scratch_size
= MAX2(compute_scratch_size
,
1450 cmd_buffer
->compute_scratch_size_needed
);
1451 esgs_ring_size
= MAX2(esgs_ring_size
, cmd_buffer
->esgs_ring_size_needed
);
1452 gsvs_ring_size
= MAX2(gsvs_ring_size
, cmd_buffer
->gsvs_ring_size_needed
);
1456 result
= radv_get_preamble_cs(queue
, scratch_size
, compute_scratch_size
, esgs_ring_size
, gsvs_ring_size
, &preamble_cs
);
1457 if (result
!= VK_SUCCESS
)
1460 for (uint32_t i
= 0; i
< submitCount
; i
++) {
1461 struct radeon_winsys_cs
**cs_array
;
1462 bool can_patch
= true;
1464 int draw_cmd_buffers_count
= 0;
1466 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
1467 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
1468 pSubmits
[i
].pCommandBuffers
[j
]);
1469 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1470 if (cmd_buffer
->no_draws
== true)
1472 draw_cmd_buffers_count
++;
1475 if (!draw_cmd_buffers_count
) {
1476 if (pSubmits
[i
].waitSemaphoreCount
|| pSubmits
[i
].signalSemaphoreCount
) {
1477 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
1478 &queue
->device
->empty_cs
[queue
->queue_family_index
],
1480 (struct radeon_winsys_sem
**)pSubmits
[i
].pWaitSemaphores
,
1481 pSubmits
[i
].waitSemaphoreCount
,
1482 (struct radeon_winsys_sem
**)pSubmits
[i
].pSignalSemaphores
,
1483 pSubmits
[i
].signalSemaphoreCount
,
1486 radv_loge("failed to submit CS %d\n", i
);
1489 fence_emitted
= true;
1494 cs_array
= malloc(sizeof(struct radeon_winsys_cs
*) * draw_cmd_buffers_count
);
1496 int draw_cmd_buffer_idx
= 0;
1497 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
1498 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
1499 pSubmits
[i
].pCommandBuffers
[j
]);
1500 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1501 if (cmd_buffer
->no_draws
== true)
1504 cs_array
[draw_cmd_buffer_idx
] = cmd_buffer
->cs
;
1505 draw_cmd_buffer_idx
++;
1506 if ((cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT
))
1510 for (uint32_t j
= 0; j
< draw_cmd_buffers_count
; j
+= advance
) {
1511 advance
= MIN2(max_cs_submission
,
1512 draw_cmd_buffers_count
- j
);
1514 bool e
= j
+ advance
== draw_cmd_buffers_count
;
1516 if (queue
->device
->trace_bo
)
1517 *queue
->device
->trace_id_ptr
= 0;
1519 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, cs_array
+ j
,
1520 advance
, preamble_cs
,
1521 (struct radeon_winsys_sem
**)pSubmits
[i
].pWaitSemaphores
,
1522 b
? pSubmits
[i
].waitSemaphoreCount
: 0,
1523 (struct radeon_winsys_sem
**)pSubmits
[i
].pSignalSemaphores
,
1524 e
? pSubmits
[i
].signalSemaphoreCount
: 0,
1525 can_patch
, base_fence
);
1528 radv_loge("failed to submit CS %d\n", i
);
1531 fence_emitted
= true;
1532 if (queue
->device
->trace_bo
) {
1533 bool success
= queue
->device
->ws
->ctx_wait_idle(
1535 radv_queue_family_to_ring(
1536 queue
->queue_family_index
),
1539 if (!success
) { /* Hang */
1540 radv_dump_trace(queue
->device
, cs_array
[j
]);
1550 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
1551 &queue
->device
->empty_cs
[queue
->queue_family_index
],
1552 1, NULL
, NULL
, 0, NULL
, 0,
1555 fence
->submitted
= true;
1561 VkResult
radv_QueueWaitIdle(
1564 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
1566 queue
->device
->ws
->ctx_wait_idle(queue
->hw_ctx
,
1567 radv_queue_family_to_ring(queue
->queue_family_index
),
1572 VkResult
radv_DeviceWaitIdle(
1575 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1577 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
1578 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++) {
1579 radv_QueueWaitIdle(radv_queue_to_handle(&device
->queues
[i
][q
]));
1585 PFN_vkVoidFunction
radv_GetInstanceProcAddr(
1586 VkInstance instance
,
1589 return radv_lookup_entrypoint(pName
);
1592 /* The loader wants us to expose a second GetInstanceProcAddr function
1593 * to work around certain LD_PRELOAD issues seen in apps.
1596 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
1597 VkInstance instance
,
1601 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
1602 VkInstance instance
,
1605 return radv_GetInstanceProcAddr(instance
, pName
);
1608 PFN_vkVoidFunction
radv_GetDeviceProcAddr(
1612 return radv_lookup_entrypoint(pName
);
1615 VkResult
radv_AllocateMemory(
1617 const VkMemoryAllocateInfo
* pAllocateInfo
,
1618 const VkAllocationCallbacks
* pAllocator
,
1619 VkDeviceMemory
* pMem
)
1621 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1622 struct radv_device_memory
*mem
;
1624 enum radeon_bo_domain domain
;
1626 assert(pAllocateInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO
);
1628 if (pAllocateInfo
->allocationSize
== 0) {
1629 /* Apparently, this is allowed */
1630 *pMem
= VK_NULL_HANDLE
;
1634 mem
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*mem
), 8,
1635 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1637 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1639 uint64_t alloc_size
= align_u64(pAllocateInfo
->allocationSize
, 4096);
1640 if (pAllocateInfo
->memoryTypeIndex
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
||
1641 pAllocateInfo
->memoryTypeIndex
== RADV_MEM_TYPE_GTT_CACHED
)
1642 domain
= RADEON_DOMAIN_GTT
;
1644 domain
= RADEON_DOMAIN_VRAM
;
1646 if (pAllocateInfo
->memoryTypeIndex
== RADV_MEM_TYPE_VRAM
)
1647 flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
1649 flags
|= RADEON_FLAG_CPU_ACCESS
;
1651 if (pAllocateInfo
->memoryTypeIndex
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
)
1652 flags
|= RADEON_FLAG_GTT_WC
;
1654 mem
->bo
= device
->ws
->buffer_create(device
->ws
, alloc_size
, 65536,
1658 result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1661 mem
->type_index
= pAllocateInfo
->memoryTypeIndex
;
1663 *pMem
= radv_device_memory_to_handle(mem
);
1668 vk_free2(&device
->alloc
, pAllocator
, mem
);
1673 void radv_FreeMemory(
1675 VkDeviceMemory _mem
,
1676 const VkAllocationCallbacks
* pAllocator
)
1678 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1679 RADV_FROM_HANDLE(radv_device_memory
, mem
, _mem
);
1684 device
->ws
->buffer_destroy(mem
->bo
);
1687 vk_free2(&device
->alloc
, pAllocator
, mem
);
1690 VkResult
radv_MapMemory(
1692 VkDeviceMemory _memory
,
1693 VkDeviceSize offset
,
1695 VkMemoryMapFlags flags
,
1698 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1699 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
1706 *ppData
= device
->ws
->buffer_map(mem
->bo
);
1712 return VK_ERROR_MEMORY_MAP_FAILED
;
1715 void radv_UnmapMemory(
1717 VkDeviceMemory _memory
)
1719 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1720 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
1725 device
->ws
->buffer_unmap(mem
->bo
);
1728 VkResult
radv_FlushMappedMemoryRanges(
1730 uint32_t memoryRangeCount
,
1731 const VkMappedMemoryRange
* pMemoryRanges
)
1736 VkResult
radv_InvalidateMappedMemoryRanges(
1738 uint32_t memoryRangeCount
,
1739 const VkMappedMemoryRange
* pMemoryRanges
)
1744 void radv_GetBufferMemoryRequirements(
1747 VkMemoryRequirements
* pMemoryRequirements
)
1749 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
1751 pMemoryRequirements
->memoryTypeBits
= (1u << RADV_MEM_TYPE_COUNT
) - 1;
1753 pMemoryRequirements
->size
= buffer
->size
;
1754 pMemoryRequirements
->alignment
= 16;
1757 void radv_GetImageMemoryRequirements(
1760 VkMemoryRequirements
* pMemoryRequirements
)
1762 RADV_FROM_HANDLE(radv_image
, image
, _image
);
1764 pMemoryRequirements
->memoryTypeBits
= (1u << RADV_MEM_TYPE_COUNT
) - 1;
1766 pMemoryRequirements
->size
= image
->size
;
1767 pMemoryRequirements
->alignment
= image
->alignment
;
1770 void radv_GetImageSparseMemoryRequirements(
1773 uint32_t* pSparseMemoryRequirementCount
,
1774 VkSparseImageMemoryRequirements
* pSparseMemoryRequirements
)
1779 void radv_GetDeviceMemoryCommitment(
1781 VkDeviceMemory memory
,
1782 VkDeviceSize
* pCommittedMemoryInBytes
)
1784 *pCommittedMemoryInBytes
= 0;
1787 VkResult
radv_BindBufferMemory(
1790 VkDeviceMemory _memory
,
1791 VkDeviceSize memoryOffset
)
1793 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
1794 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
1797 buffer
->bo
= mem
->bo
;
1798 buffer
->offset
= memoryOffset
;
1807 VkResult
radv_BindImageMemory(
1810 VkDeviceMemory _memory
,
1811 VkDeviceSize memoryOffset
)
1813 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
1814 RADV_FROM_HANDLE(radv_image
, image
, _image
);
1817 image
->bo
= mem
->bo
;
1818 image
->offset
= memoryOffset
;
1827 VkResult
radv_QueueBindSparse(
1829 uint32_t bindInfoCount
,
1830 const VkBindSparseInfo
* pBindInfo
,
1833 stub_return(VK_ERROR_INCOMPATIBLE_DRIVER
);
1836 VkResult
radv_CreateFence(
1838 const VkFenceCreateInfo
* pCreateInfo
,
1839 const VkAllocationCallbacks
* pAllocator
,
1842 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1843 struct radv_fence
*fence
= vk_alloc2(&device
->alloc
, pAllocator
,
1845 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1848 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1850 memset(fence
, 0, sizeof(*fence
));
1851 fence
->submitted
= false;
1852 fence
->signalled
= !!(pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
);
1853 fence
->fence
= device
->ws
->create_fence();
1854 if (!fence
->fence
) {
1855 vk_free2(&device
->alloc
, pAllocator
, fence
);
1856 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1859 *pFence
= radv_fence_to_handle(fence
);
1864 void radv_DestroyFence(
1867 const VkAllocationCallbacks
* pAllocator
)
1869 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1870 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
1874 device
->ws
->destroy_fence(fence
->fence
);
1875 vk_free2(&device
->alloc
, pAllocator
, fence
);
1878 static uint64_t radv_get_absolute_timeout(uint64_t timeout
)
1880 uint64_t current_time
;
1883 clock_gettime(CLOCK_MONOTONIC
, &tv
);
1884 current_time
= tv
.tv_nsec
+ tv
.tv_sec
*1000000000ull;
1886 timeout
= MIN2(UINT64_MAX
- current_time
, timeout
);
1888 return current_time
+ timeout
;
1891 VkResult
radv_WaitForFences(
1893 uint32_t fenceCount
,
1894 const VkFence
* pFences
,
1898 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1899 timeout
= radv_get_absolute_timeout(timeout
);
1901 if (!waitAll
&& fenceCount
> 1) {
1902 fprintf(stderr
, "radv: WaitForFences without waitAll not implemented yet\n");
1905 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
1906 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
1907 bool expired
= false;
1909 if (fence
->signalled
)
1912 if (!fence
->submitted
)
1915 expired
= device
->ws
->fence_wait(device
->ws
, fence
->fence
, true, timeout
);
1919 fence
->signalled
= true;
1925 VkResult
radv_ResetFences(VkDevice device
,
1926 uint32_t fenceCount
,
1927 const VkFence
*pFences
)
1929 for (unsigned i
= 0; i
< fenceCount
; ++i
) {
1930 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
1931 fence
->submitted
= fence
->signalled
= false;
1937 VkResult
radv_GetFenceStatus(VkDevice _device
, VkFence _fence
)
1939 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1940 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
1942 if (fence
->signalled
)
1944 if (!fence
->submitted
)
1945 return VK_NOT_READY
;
1947 if (!device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0))
1948 return VK_NOT_READY
;
1954 // Queue semaphore functions
1956 VkResult
radv_CreateSemaphore(
1958 const VkSemaphoreCreateInfo
* pCreateInfo
,
1959 const VkAllocationCallbacks
* pAllocator
,
1960 VkSemaphore
* pSemaphore
)
1962 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1963 struct radeon_winsys_sem
*sem
;
1965 sem
= device
->ws
->create_sem(device
->ws
);
1967 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1969 *pSemaphore
= (VkSemaphore
)sem
;
1973 void radv_DestroySemaphore(
1975 VkSemaphore _semaphore
,
1976 const VkAllocationCallbacks
* pAllocator
)
1978 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1979 struct radeon_winsys_sem
*sem
;
1983 sem
= (struct radeon_winsys_sem
*)_semaphore
;
1984 device
->ws
->destroy_sem(sem
);
1987 VkResult
radv_CreateEvent(
1989 const VkEventCreateInfo
* pCreateInfo
,
1990 const VkAllocationCallbacks
* pAllocator
,
1993 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1994 struct radv_event
*event
= vk_alloc2(&device
->alloc
, pAllocator
,
1996 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1999 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2001 event
->bo
= device
->ws
->buffer_create(device
->ws
, 8, 8,
2003 RADEON_FLAG_CPU_ACCESS
);
2005 vk_free2(&device
->alloc
, pAllocator
, event
);
2006 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2009 event
->map
= (uint64_t*)device
->ws
->buffer_map(event
->bo
);
2011 *pEvent
= radv_event_to_handle(event
);
2016 void radv_DestroyEvent(
2019 const VkAllocationCallbacks
* pAllocator
)
2021 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2022 RADV_FROM_HANDLE(radv_event
, event
, _event
);
2026 device
->ws
->buffer_destroy(event
->bo
);
2027 vk_free2(&device
->alloc
, pAllocator
, event
);
2030 VkResult
radv_GetEventStatus(
2034 RADV_FROM_HANDLE(radv_event
, event
, _event
);
2036 if (*event
->map
== 1)
2037 return VK_EVENT_SET
;
2038 return VK_EVENT_RESET
;
2041 VkResult
radv_SetEvent(
2045 RADV_FROM_HANDLE(radv_event
, event
, _event
);
2051 VkResult
radv_ResetEvent(
2055 RADV_FROM_HANDLE(radv_event
, event
, _event
);
2061 VkResult
radv_CreateBuffer(
2063 const VkBufferCreateInfo
* pCreateInfo
,
2064 const VkAllocationCallbacks
* pAllocator
,
2067 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2068 struct radv_buffer
*buffer
;
2070 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO
);
2072 buffer
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*buffer
), 8,
2073 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2075 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2077 buffer
->size
= pCreateInfo
->size
;
2078 buffer
->usage
= pCreateInfo
->usage
;
2082 *pBuffer
= radv_buffer_to_handle(buffer
);
2087 void radv_DestroyBuffer(
2090 const VkAllocationCallbacks
* pAllocator
)
2092 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2093 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
2098 vk_free2(&device
->alloc
, pAllocator
, buffer
);
2101 static inline unsigned
2102 si_tile_mode_index(const struct radv_image
*image
, unsigned level
, bool stencil
)
2105 return image
->surface
.stencil_tiling_index
[level
];
2107 return image
->surface
.tiling_index
[level
];
2111 radv_initialise_color_surface(struct radv_device
*device
,
2112 struct radv_color_buffer_info
*cb
,
2113 struct radv_image_view
*iview
)
2115 const struct vk_format_description
*desc
;
2116 unsigned ntype
, format
, swap
, endian
;
2117 unsigned blend_clamp
= 0, blend_bypass
= 0;
2118 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
2120 const struct radeon_surf
*surf
= &iview
->image
->surface
;
2121 const struct radeon_surf_level
*level_info
= &surf
->level
[iview
->base_mip
];
2123 desc
= vk_format_description(iview
->vk_format
);
2125 memset(cb
, 0, sizeof(*cb
));
2127 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
;
2128 va
+= level_info
->offset
;
2129 cb
->cb_color_base
= va
>> 8;
2131 /* CMASK variables */
2132 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
;
2133 va
+= iview
->image
->cmask
.offset
;
2134 cb
->cb_color_cmask
= va
>> 8;
2135 cb
->cb_color_cmask_slice
= iview
->image
->cmask
.slice_tile_max
;
2137 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
;
2138 va
+= iview
->image
->dcc_offset
;
2139 cb
->cb_dcc_base
= va
>> 8;
2141 uint32_t max_slice
= iview
->type
== VK_IMAGE_VIEW_TYPE_3D
? iview
->extent
.depth
: iview
->layer_count
;
2142 cb
->cb_color_view
= S_028C6C_SLICE_START(iview
->base_layer
) |
2143 S_028C6C_SLICE_MAX(iview
->base_layer
+ max_slice
- 1);
2145 cb
->micro_tile_mode
= iview
->image
->surface
.micro_tile_mode
;
2146 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
2147 slice_tile_max
= (level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1;
2148 tile_mode_index
= si_tile_mode_index(iview
->image
, iview
->base_mip
, false);
2150 cb
->cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
2151 cb
->cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
2153 /* Intensity is implemented as Red, so treat it that way. */
2154 cb
->cb_color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == VK_SWIZZLE_1
) |
2155 S_028C74_TILE_MODE_INDEX(tile_mode_index
);
2157 if (iview
->image
->samples
> 1) {
2158 unsigned log_samples
= util_logbase2(iview
->image
->samples
);
2160 cb
->cb_color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
2161 S_028C74_NUM_FRAGMENTS(log_samples
);
2164 if (iview
->image
->fmask
.size
) {
2165 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
+ iview
->image
->fmask
.offset
;
2166 if (device
->physical_device
->rad_info
.chip_class
>= CIK
)
2167 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(iview
->image
->fmask
.pitch_in_pixels
/ 8 - 1);
2168 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(iview
->image
->fmask
.tile_mode_index
);
2169 cb
->cb_color_fmask
= va
>> 8;
2170 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(iview
->image
->fmask
.slice_tile_max
);
2172 /* This must be set for fast clear to work without FMASK. */
2173 if (device
->physical_device
->rad_info
.chip_class
>= CIK
)
2174 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
2175 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
2176 cb
->cb_color_fmask
= cb
->cb_color_base
;
2177 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
2180 ntype
= radv_translate_color_numformat(iview
->vk_format
,
2182 vk_format_get_first_non_void_channel(iview
->vk_format
));
2183 format
= radv_translate_colorformat(iview
->vk_format
);
2184 if (format
== V_028C70_COLOR_INVALID
|| ntype
== ~0u)
2185 radv_finishme("Illegal color\n");
2186 swap
= radv_translate_colorswap(iview
->vk_format
, FALSE
);
2187 endian
= radv_colorformat_endian_swap(format
);
2189 /* blend clamp should be set for all NORM/SRGB types */
2190 if (ntype
== V_028C70_NUMBER_UNORM
||
2191 ntype
== V_028C70_NUMBER_SNORM
||
2192 ntype
== V_028C70_NUMBER_SRGB
)
2195 /* set blend bypass according to docs if SINT/UINT or
2196 8/24 COLOR variants */
2197 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
2198 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
2199 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
2204 if ((ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) &&
2205 (format
== V_028C70_COLOR_8
||
2206 format
== V_028C70_COLOR_8_8
||
2207 format
== V_028C70_COLOR_8_8_8_8
))
2208 ->color_is_int8
= true;
2210 cb
->cb_color_info
= S_028C70_FORMAT(format
) |
2211 S_028C70_COMP_SWAP(swap
) |
2212 S_028C70_BLEND_CLAMP(blend_clamp
) |
2213 S_028C70_BLEND_BYPASS(blend_bypass
) |
2214 S_028C70_SIMPLE_FLOAT(1) |
2215 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
2216 ntype
!= V_028C70_NUMBER_SNORM
&&
2217 ntype
!= V_028C70_NUMBER_SRGB
&&
2218 format
!= V_028C70_COLOR_8_24
&&
2219 format
!= V_028C70_COLOR_24_8
) |
2220 S_028C70_NUMBER_TYPE(ntype
) |
2221 S_028C70_ENDIAN(endian
);
2222 if (iview
->image
->samples
> 1)
2223 if (iview
->image
->fmask
.size
)
2224 cb
->cb_color_info
|= S_028C70_COMPRESSION(1);
2226 if (iview
->image
->cmask
.size
&&
2227 !(device
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
))
2228 cb
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
2230 if (iview
->image
->surface
.dcc_size
&& level_info
->dcc_enabled
)
2231 cb
->cb_color_info
|= S_028C70_DCC_ENABLE(1);
2233 if (device
->physical_device
->rad_info
.chip_class
>= VI
) {
2234 unsigned max_uncompressed_block_size
= 2;
2235 if (iview
->image
->samples
> 1) {
2236 if (iview
->image
->surface
.bpe
== 1)
2237 max_uncompressed_block_size
= 0;
2238 else if (iview
->image
->surface
.bpe
== 2)
2239 max_uncompressed_block_size
= 1;
2242 cb
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
2243 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2246 /* This must be set for fast clear to work without FMASK. */
2247 if (!iview
->image
->fmask
.size
&&
2248 device
->physical_device
->rad_info
.chip_class
== SI
) {
2249 unsigned bankh
= util_logbase2(iview
->image
->surface
.bankh
);
2250 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
2255 radv_initialise_ds_surface(struct radv_device
*device
,
2256 struct radv_ds_buffer_info
*ds
,
2257 struct radv_image_view
*iview
)
2259 unsigned level
= iview
->base_mip
;
2261 uint64_t va
, s_offs
, z_offs
;
2262 const struct radeon_surf_level
*level_info
= &iview
->image
->surface
.level
[level
];
2263 memset(ds
, 0, sizeof(*ds
));
2264 switch (iview
->vk_format
) {
2265 case VK_FORMAT_D24_UNORM_S8_UINT
:
2266 case VK_FORMAT_X8_D24_UNORM_PACK32
:
2267 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
2268 ds
->offset_scale
= 2.0f
;
2270 case VK_FORMAT_D16_UNORM
:
2271 case VK_FORMAT_D16_UNORM_S8_UINT
:
2272 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
2273 ds
->offset_scale
= 4.0f
;
2275 case VK_FORMAT_D32_SFLOAT
:
2276 case VK_FORMAT_D32_SFLOAT_S8_UINT
:
2277 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
2278 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2279 ds
->offset_scale
= 1.0f
;
2285 format
= radv_translate_dbformat(iview
->vk_format
);
2286 if (format
== V_028040_Z_INVALID
) {
2287 fprintf(stderr
, "Invalid DB format: %d, disabling DB.\n", iview
->vk_format
);
2290 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
;
2291 s_offs
= z_offs
= va
;
2292 z_offs
+= iview
->image
->surface
.level
[level
].offset
;
2293 s_offs
+= iview
->image
->surface
.stencil_level
[level
].offset
;
2295 uint32_t max_slice
= iview
->type
== VK_IMAGE_VIEW_TYPE_3D
? iview
->extent
.depth
: iview
->layer_count
;
2296 ds
->db_depth_view
= S_028008_SLICE_START(iview
->base_layer
) |
2297 S_028008_SLICE_MAX(iview
->base_layer
+ max_slice
- 1);
2298 ds
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(1);
2299 ds
->db_z_info
= S_028040_FORMAT(format
) | S_028040_ZRANGE_PRECISION(1);
2301 if (iview
->image
->samples
> 1)
2302 ds
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(iview
->image
->samples
));
2304 if (iview
->image
->surface
.flags
& RADEON_SURF_SBUFFER
)
2305 ds
->db_stencil_info
= S_028044_FORMAT(V_028044_STENCIL_8
);
2307 ds
->db_stencil_info
= S_028044_FORMAT(V_028044_STENCIL_INVALID
);
2309 if (device
->physical_device
->rad_info
.chip_class
>= CIK
) {
2310 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
2311 unsigned tiling_index
= iview
->image
->surface
.tiling_index
[level
];
2312 unsigned stencil_index
= iview
->image
->surface
.stencil_tiling_index
[level
];
2313 unsigned macro_index
= iview
->image
->surface
.macro_tile_index
;
2314 unsigned tile_mode
= info
->si_tile_mode_array
[tiling_index
];
2315 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
2316 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
2318 ds
->db_depth_info
|=
2319 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
2320 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
2321 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
2322 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
2323 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
2324 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
2325 ds
->db_z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
2326 ds
->db_stencil_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
2328 unsigned tile_mode_index
= si_tile_mode_index(iview
->image
, level
, false);
2329 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
2330 tile_mode_index
= si_tile_mode_index(iview
->image
, level
, true);
2331 ds
->db_stencil_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
2334 if (iview
->image
->htile
.size
&& !level
) {
2335 ds
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1) |
2336 S_028040_ALLOW_EXPCLEAR(1);
2338 if (iview
->image
->surface
.flags
& RADEON_SURF_SBUFFER
) {
2339 /* Workaround: For a not yet understood reason, the
2340 * combination of MSAA, fast stencil clear and stencil
2341 * decompress messes with subsequent stencil buffer
2342 * uses. Problem was reproduced on Verde, Bonaire,
2343 * Tonga, and Carrizo.
2345 * Disabling EXPCLEAR works around the problem.
2347 * Check piglit's arb_texture_multisample-stencil-clear
2348 * test if you want to try changing this.
2350 if (iview
->image
->samples
<= 1)
2351 ds
->db_stencil_info
|= S_028044_ALLOW_EXPCLEAR(1);
2353 /* Use all of the htile_buffer for depth if there's no stencil. */
2354 ds
->db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
2356 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
+
2357 iview
->image
->htile
.offset
;
2358 ds
->db_htile_data_base
= va
>> 8;
2359 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
2361 ds
->db_htile_data_base
= 0;
2362 ds
->db_htile_surface
= 0;
2365 ds
->db_z_read_base
= ds
->db_z_write_base
= z_offs
>> 8;
2366 ds
->db_stencil_read_base
= ds
->db_stencil_write_base
= s_offs
>> 8;
2368 ds
->db_depth_size
= S_028058_PITCH_TILE_MAX((level_info
->nblk_x
/ 8) - 1) |
2369 S_028058_HEIGHT_TILE_MAX((level_info
->nblk_y
/ 8) - 1);
2370 ds
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1);
2373 VkResult
radv_CreateFramebuffer(
2375 const VkFramebufferCreateInfo
* pCreateInfo
,
2376 const VkAllocationCallbacks
* pAllocator
,
2377 VkFramebuffer
* pFramebuffer
)
2379 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2380 struct radv_framebuffer
*framebuffer
;
2382 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
);
2384 size_t size
= sizeof(*framebuffer
) +
2385 sizeof(struct radv_attachment_info
) * pCreateInfo
->attachmentCount
;
2386 framebuffer
= vk_alloc2(&device
->alloc
, pAllocator
, size
, 8,
2387 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2388 if (framebuffer
== NULL
)
2389 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2391 framebuffer
->attachment_count
= pCreateInfo
->attachmentCount
;
2392 for (uint32_t i
= 0; i
< pCreateInfo
->attachmentCount
; i
++) {
2393 VkImageView _iview
= pCreateInfo
->pAttachments
[i
];
2394 struct radv_image_view
*iview
= radv_image_view_from_handle(_iview
);
2395 framebuffer
->attachments
[i
].attachment
= iview
;
2396 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
) {
2397 radv_initialise_color_surface(device
, &framebuffer
->attachments
[i
].cb
, iview
);
2398 } else if (iview
->aspect_mask
& (VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
)) {
2399 radv_initialise_ds_surface(device
, &framebuffer
->attachments
[i
].ds
, iview
);
2403 framebuffer
->width
= pCreateInfo
->width
;
2404 framebuffer
->height
= pCreateInfo
->height
;
2405 framebuffer
->layers
= pCreateInfo
->layers
;
2407 *pFramebuffer
= radv_framebuffer_to_handle(framebuffer
);
2411 void radv_DestroyFramebuffer(
2414 const VkAllocationCallbacks
* pAllocator
)
2416 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2417 RADV_FROM_HANDLE(radv_framebuffer
, fb
, _fb
);
2421 vk_free2(&device
->alloc
, pAllocator
, fb
);
2424 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode
)
2426 switch (address_mode
) {
2427 case VK_SAMPLER_ADDRESS_MODE_REPEAT
:
2428 return V_008F30_SQ_TEX_WRAP
;
2429 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT
:
2430 return V_008F30_SQ_TEX_MIRROR
;
2431 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
:
2432 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
2433 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
:
2434 return V_008F30_SQ_TEX_CLAMP_BORDER
;
2435 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE
:
2436 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
2438 unreachable("illegal tex wrap mode");
2444 radv_tex_compare(VkCompareOp op
)
2447 case VK_COMPARE_OP_NEVER
:
2448 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
2449 case VK_COMPARE_OP_LESS
:
2450 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
2451 case VK_COMPARE_OP_EQUAL
:
2452 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
2453 case VK_COMPARE_OP_LESS_OR_EQUAL
:
2454 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
2455 case VK_COMPARE_OP_GREATER
:
2456 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
2457 case VK_COMPARE_OP_NOT_EQUAL
:
2458 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
2459 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
2460 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
2461 case VK_COMPARE_OP_ALWAYS
:
2462 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
2464 unreachable("illegal compare mode");
2470 radv_tex_filter(VkFilter filter
, unsigned max_ansio
)
2473 case VK_FILTER_NEAREST
:
2474 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
:
2475 V_008F38_SQ_TEX_XY_FILTER_POINT
);
2476 case VK_FILTER_LINEAR
:
2477 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
:
2478 V_008F38_SQ_TEX_XY_FILTER_BILINEAR
);
2479 case VK_FILTER_CUBIC_IMG
:
2481 fprintf(stderr
, "illegal texture filter");
2487 radv_tex_mipfilter(VkSamplerMipmapMode mode
)
2490 case VK_SAMPLER_MIPMAP_MODE_NEAREST
:
2491 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
2492 case VK_SAMPLER_MIPMAP_MODE_LINEAR
:
2493 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
2495 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
2500 radv_tex_bordercolor(VkBorderColor bcolor
)
2503 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
:
2504 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK
:
2505 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
2506 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK
:
2507 case VK_BORDER_COLOR_INT_OPAQUE_BLACK
:
2508 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
2509 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE
:
2510 case VK_BORDER_COLOR_INT_OPAQUE_WHITE
:
2511 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
2519 radv_tex_aniso_filter(unsigned filter
)
2533 radv_init_sampler(struct radv_device
*device
,
2534 struct radv_sampler
*sampler
,
2535 const VkSamplerCreateInfo
*pCreateInfo
)
2537 uint32_t max_aniso
= pCreateInfo
->anisotropyEnable
&& pCreateInfo
->maxAnisotropy
> 1.0 ?
2538 (uint32_t) pCreateInfo
->maxAnisotropy
: 0;
2539 uint32_t max_aniso_ratio
= radv_tex_aniso_filter(max_aniso
);
2540 bool is_vi
= (device
->physical_device
->rad_info
.chip_class
>= VI
);
2542 sampler
->state
[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo
->addressModeU
)) |
2543 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo
->addressModeV
)) |
2544 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo
->addressModeW
)) |
2545 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
2546 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo
->compareOp
)) |
2547 S_008F30_FORCE_UNNORMALIZED(pCreateInfo
->unnormalizedCoordinates
? 1 : 0) |
2548 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
2549 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
2550 S_008F30_DISABLE_CUBE_WRAP(0) |
2551 S_008F30_COMPAT_MODE(is_vi
));
2552 sampler
->state
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo
->minLod
, 0, 15), 8)) |
2553 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo
->maxLod
, 0, 15), 8)) |
2554 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
2555 sampler
->state
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo
->mipLodBias
, -16, 16), 8)) |
2556 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo
->magFilter
, max_aniso
)) |
2557 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo
->minFilter
, max_aniso
)) |
2558 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo
->mipmapMode
)) |
2559 S_008F38_MIP_POINT_PRECLAMP(1) |
2560 S_008F38_DISABLE_LSB_CEIL(1) |
2561 S_008F38_FILTER_PREC_FIX(1) |
2562 S_008F38_ANISO_OVERRIDE(is_vi
));
2563 sampler
->state
[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
2564 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo
->borderColor
)));
2567 VkResult
radv_CreateSampler(
2569 const VkSamplerCreateInfo
* pCreateInfo
,
2570 const VkAllocationCallbacks
* pAllocator
,
2571 VkSampler
* pSampler
)
2573 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2574 struct radv_sampler
*sampler
;
2576 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO
);
2578 sampler
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*sampler
), 8,
2579 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2581 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2583 radv_init_sampler(device
, sampler
, pCreateInfo
);
2584 *pSampler
= radv_sampler_to_handle(sampler
);
2589 void radv_DestroySampler(
2592 const VkAllocationCallbacks
* pAllocator
)
2594 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2595 RADV_FROM_HANDLE(radv_sampler
, sampler
, _sampler
);
2599 vk_free2(&device
->alloc
, pAllocator
, sampler
);
2603 /* vk_icd.h does not declare this function, so we declare it here to
2604 * suppress Wmissing-prototypes.
2606 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
2607 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
);
2609 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
2610 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
)
2612 /* For the full details on loader interface versioning, see
2613 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
2614 * What follows is a condensed summary, to help you navigate the large and
2615 * confusing official doc.
2617 * - Loader interface v0 is incompatible with later versions. We don't
2620 * - In loader interface v1:
2621 * - The first ICD entrypoint called by the loader is
2622 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
2624 * - The ICD must statically expose no other Vulkan symbol unless it is
2625 * linked with -Bsymbolic.
2626 * - Each dispatchable Vulkan handle created by the ICD must be
2627 * a pointer to a struct whose first member is VK_LOADER_DATA. The
2628 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
2629 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
2630 * vkDestroySurfaceKHR(). The ICD must be capable of working with
2631 * such loader-managed surfaces.
2633 * - Loader interface v2 differs from v1 in:
2634 * - The first ICD entrypoint called by the loader is
2635 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
2636 * statically expose this entrypoint.
2638 * - Loader interface v3 differs from v2 in:
2639 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
2640 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
2641 * because the loader no longer does so.
2643 *pSupportedVersion
= MIN2(*pSupportedVersion
, 3u);