2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
47 #include "util/build_id.h"
48 #include "util/debug.h"
49 #include "util/mesa-sha1.h"
50 #include "compiler/glsl_types.h"
51 #include "util/xmlpool.h"
54 radv_device_get_cache_uuid(enum radeon_family family
, void *uuid
)
57 unsigned char sha1
[20];
58 unsigned ptr_size
= sizeof(void*);
60 memset(uuid
, 0, VK_UUID_SIZE
);
61 _mesa_sha1_init(&ctx
);
63 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid
, &ctx
) ||
64 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo
, &ctx
))
67 _mesa_sha1_update(&ctx
, &family
, sizeof(family
));
68 _mesa_sha1_update(&ctx
, &ptr_size
, sizeof(ptr_size
));
69 _mesa_sha1_final(&ctx
, sha1
);
71 memcpy(uuid
, sha1
, VK_UUID_SIZE
);
76 radv_get_driver_uuid(void *uuid
)
78 ac_compute_driver_uuid(uuid
, VK_UUID_SIZE
);
82 radv_get_device_uuid(struct radeon_info
*info
, void *uuid
)
84 ac_compute_device_uuid(info
, uuid
, VK_UUID_SIZE
);
88 radv_get_device_name(enum radeon_family family
, char *name
, size_t name_len
)
90 const char *chip_string
;
93 case CHIP_TAHITI
: chip_string
= "AMD RADV TAHITI"; break;
94 case CHIP_PITCAIRN
: chip_string
= "AMD RADV PITCAIRN"; break;
95 case CHIP_VERDE
: chip_string
= "AMD RADV CAPE VERDE"; break;
96 case CHIP_OLAND
: chip_string
= "AMD RADV OLAND"; break;
97 case CHIP_HAINAN
: chip_string
= "AMD RADV HAINAN"; break;
98 case CHIP_BONAIRE
: chip_string
= "AMD RADV BONAIRE"; break;
99 case CHIP_KAVERI
: chip_string
= "AMD RADV KAVERI"; break;
100 case CHIP_KABINI
: chip_string
= "AMD RADV KABINI"; break;
101 case CHIP_HAWAII
: chip_string
= "AMD RADV HAWAII"; break;
102 case CHIP_TONGA
: chip_string
= "AMD RADV TONGA"; break;
103 case CHIP_ICELAND
: chip_string
= "AMD RADV ICELAND"; break;
104 case CHIP_CARRIZO
: chip_string
= "AMD RADV CARRIZO"; break;
105 case CHIP_FIJI
: chip_string
= "AMD RADV FIJI"; break;
106 case CHIP_POLARIS10
: chip_string
= "AMD RADV POLARIS10"; break;
107 case CHIP_POLARIS11
: chip_string
= "AMD RADV POLARIS11"; break;
108 case CHIP_POLARIS12
: chip_string
= "AMD RADV POLARIS12"; break;
109 case CHIP_STONEY
: chip_string
= "AMD RADV STONEY"; break;
110 case CHIP_VEGAM
: chip_string
= "AMD RADV VEGA M"; break;
111 case CHIP_VEGA10
: chip_string
= "AMD RADV VEGA10"; break;
112 case CHIP_VEGA12
: chip_string
= "AMD RADV VEGA12"; break;
113 case CHIP_VEGA20
: chip_string
= "AMD RADV VEGA20"; break;
114 case CHIP_RAVEN
: chip_string
= "AMD RADV RAVEN"; break;
115 case CHIP_RAVEN2
: chip_string
= "AMD RADV RAVEN2"; break;
116 default: chip_string
= "AMD RADV unknown"; break;
119 snprintf(name
, name_len
, "%s (LLVM " MESA_LLVM_VERSION_STRING
")", chip_string
);
123 radv_get_visible_vram_size(struct radv_physical_device
*device
)
125 return MIN2(device
->rad_info
.vram_size
, device
->rad_info
.vram_vis_size
);
129 radv_get_vram_size(struct radv_physical_device
*device
)
131 return device
->rad_info
.vram_size
- radv_get_visible_vram_size(device
);
135 radv_physical_device_init_mem_types(struct radv_physical_device
*device
)
137 STATIC_ASSERT(RADV_MEM_HEAP_COUNT
<= VK_MAX_MEMORY_HEAPS
);
138 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
139 uint64_t vram_size
= radv_get_vram_size(device
);
140 int vram_index
= -1, visible_vram_index
= -1, gart_index
= -1;
141 device
->memory_properties
.memoryHeapCount
= 0;
143 vram_index
= device
->memory_properties
.memoryHeapCount
++;
144 device
->memory_properties
.memoryHeaps
[vram_index
] = (VkMemoryHeap
) {
146 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
149 if (visible_vram_size
) {
150 visible_vram_index
= device
->memory_properties
.memoryHeapCount
++;
151 device
->memory_properties
.memoryHeaps
[visible_vram_index
] = (VkMemoryHeap
) {
152 .size
= visible_vram_size
,
153 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
156 if (device
->rad_info
.gart_size
> 0) {
157 gart_index
= device
->memory_properties
.memoryHeapCount
++;
158 device
->memory_properties
.memoryHeaps
[gart_index
] = (VkMemoryHeap
) {
159 .size
= device
->rad_info
.gart_size
,
160 .flags
= device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
164 STATIC_ASSERT(RADV_MEM_TYPE_COUNT
<= VK_MAX_MEMORY_TYPES
);
165 unsigned type_count
= 0;
166 if (vram_index
>= 0) {
167 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM
;
168 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
169 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
,
170 .heapIndex
= vram_index
,
173 if (gart_index
>= 0) {
174 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_WRITE_COMBINE
;
175 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
176 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
177 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
178 (device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
),
179 .heapIndex
= gart_index
,
182 if (visible_vram_index
>= 0) {
183 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM_CPU_ACCESS
;
184 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
185 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
186 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
187 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
188 .heapIndex
= visible_vram_index
,
191 if (gart_index
>= 0) {
192 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_CACHED
;
193 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
194 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
195 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
196 VK_MEMORY_PROPERTY_HOST_CACHED_BIT
|
197 (device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
),
198 .heapIndex
= gart_index
,
201 device
->memory_properties
.memoryTypeCount
= type_count
;
205 radv_handle_env_var_force_family(struct radv_physical_device
*device
)
207 const char *family
= getenv("RADV_FORCE_FAMILY");
213 for (i
= CHIP_TAHITI
; i
< CHIP_LAST
; i
++) {
214 if (!strcmp(family
, ac_get_llvm_processor_name(i
))) {
215 /* Override family and chip_class. */
216 device
->rad_info
.family
= i
;
218 if (i
>= CHIP_VEGA10
)
219 device
->rad_info
.chip_class
= GFX9
;
220 else if (i
>= CHIP_TONGA
)
221 device
->rad_info
.chip_class
= GFX8
;
222 else if (i
>= CHIP_BONAIRE
)
223 device
->rad_info
.chip_class
= GFX7
;
225 device
->rad_info
.chip_class
= GFX6
;
231 fprintf(stderr
, "radv: Unknown family: %s\n", family
);
236 radv_physical_device_init(struct radv_physical_device
*device
,
237 struct radv_instance
*instance
,
238 drmDevicePtr drm_device
)
240 const char *path
= drm_device
->nodes
[DRM_NODE_RENDER
];
242 drmVersionPtr version
;
246 fd
= open(path
, O_RDWR
| O_CLOEXEC
);
248 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
249 radv_logi("Could not open device '%s'", path
);
251 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
254 version
= drmGetVersion(fd
);
258 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
259 radv_logi("Could not get the kernel driver version for device '%s'", path
);
261 return vk_errorf(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
,
262 "failed to get version %s: %m", path
);
265 if (strcmp(version
->name
, "amdgpu")) {
266 drmFreeVersion(version
);
269 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
270 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path
);
272 return VK_ERROR_INCOMPATIBLE_DRIVER
;
274 drmFreeVersion(version
);
276 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
277 radv_logi("Found compatible device '%s'.", path
);
279 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
280 device
->instance
= instance
;
282 device
->ws
= radv_amdgpu_winsys_create(fd
, instance
->debug_flags
,
283 instance
->perftest_flags
);
285 result
= vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
289 if (instance
->enabled_extensions
.KHR_display
) {
290 master_fd
= open(drm_device
->nodes
[DRM_NODE_PRIMARY
], O_RDWR
| O_CLOEXEC
);
291 if (master_fd
>= 0) {
292 uint32_t accel_working
= 0;
293 struct drm_amdgpu_info request
= {
294 .return_pointer
= (uintptr_t)&accel_working
,
295 .return_size
= sizeof(accel_working
),
296 .query
= AMDGPU_INFO_ACCEL_WORKING
299 if (drmCommandWrite(master_fd
, DRM_AMDGPU_INFO
, &request
, sizeof (struct drm_amdgpu_info
)) < 0 || !accel_working
) {
306 device
->master_fd
= master_fd
;
307 device
->local_fd
= fd
;
308 device
->ws
->query_info(device
->ws
, &device
->rad_info
);
310 radv_handle_env_var_force_family(device
);
312 radv_get_device_name(device
->rad_info
.family
, device
->name
, sizeof(device
->name
));
314 if (radv_device_get_cache_uuid(device
->rad_info
.family
, device
->cache_uuid
)) {
315 device
->ws
->destroy(device
->ws
);
316 result
= vk_errorf(instance
, VK_ERROR_INITIALIZATION_FAILED
,
317 "cannot generate UUID");
321 /* These flags affect shader compilation. */
322 uint64_t shader_env_flags
=
323 (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
? 0x1 : 0) |
324 (device
->instance
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
? 0x2 : 0);
326 /* The gpu id is already embedded in the uuid so we just pass "radv"
327 * when creating the cache.
329 char buf
[VK_UUID_SIZE
* 2 + 1];
330 disk_cache_format_hex_id(buf
, device
->cache_uuid
, VK_UUID_SIZE
* 2);
331 device
->disk_cache
= disk_cache_create(device
->name
, buf
, shader_env_flags
);
333 if (device
->rad_info
.chip_class
< GFX8
||
334 device
->rad_info
.chip_class
> GFX9
)
335 fprintf(stderr
, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
337 radv_get_driver_uuid(&device
->driver_uuid
);
338 radv_get_device_uuid(&device
->rad_info
, &device
->device_uuid
);
340 if (device
->rad_info
.family
== CHIP_STONEY
||
341 device
->rad_info
.chip_class
>= GFX9
) {
342 device
->has_rbplus
= true;
343 device
->rbplus_allowed
= device
->rad_info
.family
== CHIP_STONEY
||
344 device
->rad_info
.family
== CHIP_VEGA12
||
345 device
->rad_info
.family
== CHIP_RAVEN
||
346 device
->rad_info
.family
== CHIP_RAVEN2
;
349 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
352 device
->has_clear_state
= device
->rad_info
.chip_class
>= GFX7
;
354 device
->cpdma_prefetch_writes_memory
= device
->rad_info
.chip_class
<= GFX8
;
356 /* Vega10/Raven need a special workaround for a hardware bug. */
357 device
->has_scissor_bug
= device
->rad_info
.family
== CHIP_VEGA10
||
358 device
->rad_info
.family
== CHIP_RAVEN
;
360 /* Out-of-order primitive rasterization. */
361 device
->has_out_of_order_rast
= device
->rad_info
.chip_class
>= GFX8
&&
362 device
->rad_info
.max_se
>= 2;
363 device
->out_of_order_rast_allowed
= device
->has_out_of_order_rast
&&
364 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_OUT_OF_ORDER
);
366 device
->dcc_msaa_allowed
=
367 (device
->instance
->perftest_flags
& RADV_PERFTEST_DCC_MSAA
);
369 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
370 device
->has_load_ctx_reg_pkt
= device
->rad_info
.chip_class
>= GFX9
||
371 (device
->rad_info
.chip_class
>= GFX8
&&
372 device
->rad_info
.me_fw_feature
>= 41);
374 device
->has_dcc_constant_encode
= device
->rad_info
.family
== CHIP_RAVEN2
;
376 device
->use_shader_ballot
= device
->instance
->perftest_flags
& RADV_PERFTEST_SHADER_BALLOT
;
378 radv_physical_device_init_mem_types(device
);
379 radv_fill_device_extension_table(device
, &device
->supported_extensions
);
381 device
->bus_info
= *drm_device
->businfo
.pci
;
383 if ((device
->instance
->debug_flags
& RADV_DEBUG_INFO
))
384 ac_print_gpu_info(&device
->rad_info
);
386 /* The WSI is structured as a layer on top of the driver, so this has
387 * to be the last part of initialization (at least until we get other
390 result
= radv_init_wsi(device
);
391 if (result
!= VK_SUCCESS
) {
392 device
->ws
->destroy(device
->ws
);
393 vk_error(instance
, result
);
407 radv_physical_device_finish(struct radv_physical_device
*device
)
409 radv_finish_wsi(device
);
410 device
->ws
->destroy(device
->ws
);
411 disk_cache_destroy(device
->disk_cache
);
412 close(device
->local_fd
);
413 if (device
->master_fd
!= -1)
414 close(device
->master_fd
);
418 default_alloc_func(void *pUserData
, size_t size
, size_t align
,
419 VkSystemAllocationScope allocationScope
)
425 default_realloc_func(void *pUserData
, void *pOriginal
, size_t size
,
426 size_t align
, VkSystemAllocationScope allocationScope
)
428 return realloc(pOriginal
, size
);
432 default_free_func(void *pUserData
, void *pMemory
)
437 static const VkAllocationCallbacks default_alloc
= {
439 .pfnAllocation
= default_alloc_func
,
440 .pfnReallocation
= default_realloc_func
,
441 .pfnFree
= default_free_func
,
444 static const struct debug_control radv_debug_options
[] = {
445 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS
},
446 {"nodcc", RADV_DEBUG_NO_DCC
},
447 {"shaders", RADV_DEBUG_DUMP_SHADERS
},
448 {"nocache", RADV_DEBUG_NO_CACHE
},
449 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS
},
450 {"nohiz", RADV_DEBUG_NO_HIZ
},
451 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE
},
452 {"unsafemath", RADV_DEBUG_UNSAFE_MATH
},
453 {"allbos", RADV_DEBUG_ALL_BOS
},
454 {"noibs", RADV_DEBUG_NO_IBS
},
455 {"spirv", RADV_DEBUG_DUMP_SPIRV
},
456 {"vmfaults", RADV_DEBUG_VM_FAULTS
},
457 {"zerovram", RADV_DEBUG_ZERO_VRAM
},
458 {"syncshaders", RADV_DEBUG_SYNC_SHADERS
},
459 {"nosisched", RADV_DEBUG_NO_SISCHED
},
460 {"preoptir", RADV_DEBUG_PREOPTIR
},
461 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS
},
462 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER
},
463 {"info", RADV_DEBUG_INFO
},
464 {"errors", RADV_DEBUG_ERRORS
},
465 {"startup", RADV_DEBUG_STARTUP
},
466 {"checkir", RADV_DEBUG_CHECKIR
},
467 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM
},
468 {"nobinning", RADV_DEBUG_NOBINNING
},
469 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT
},
474 radv_get_debug_option_name(int id
)
476 assert(id
< ARRAY_SIZE(radv_debug_options
) - 1);
477 return radv_debug_options
[id
].string
;
480 static const struct debug_control radv_perftest_options
[] = {
481 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN
},
482 {"sisched", RADV_PERFTEST_SISCHED
},
483 {"localbos", RADV_PERFTEST_LOCAL_BOS
},
484 {"dccmsaa", RADV_PERFTEST_DCC_MSAA
},
485 {"bolist", RADV_PERFTEST_BO_LIST
},
486 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT
},
487 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK
},
492 radv_get_perftest_option_name(int id
)
494 assert(id
< ARRAY_SIZE(radv_perftest_options
) - 1);
495 return radv_perftest_options
[id
].string
;
499 radv_handle_per_app_options(struct radv_instance
*instance
,
500 const VkApplicationInfo
*info
)
502 const char *name
= info
? info
->pApplicationName
: NULL
;
507 if (!strcmp(name
, "Talos - Linux - 32bit") ||
508 !strcmp(name
, "Talos - Linux - 64bit")) {
509 if (!(instance
->debug_flags
& RADV_DEBUG_NO_SISCHED
)) {
510 /* Force enable LLVM sisched for Talos because it looks
511 * safe and it gives few more FPS.
513 instance
->perftest_flags
|= RADV_PERFTEST_SISCHED
;
515 } else if (!strcmp(name
, "DOOM_VFR")) {
516 /* Work around a Doom VFR game bug */
517 instance
->debug_flags
|= RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
518 } else if (!strcmp(name
, "MonsterHunterWorld.exe")) {
519 /* Workaround for a WaW hazard when LLVM moves/merges
520 * load/store memory operations.
521 * See https://reviews.llvm.org/D61313
523 if (HAVE_LLVM
< 0x900)
524 instance
->debug_flags
|= RADV_DEBUG_NO_LOAD_STORE_OPT
;
528 static int radv_get_instance_extension_index(const char *name
)
530 for (unsigned i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; ++i
) {
531 if (strcmp(name
, radv_instance_extensions
[i
].extensionName
) == 0)
537 static const char radv_dri_options_xml
[] =
539 DRI_CONF_SECTION_QUALITY
540 DRI_CONF_ADAPTIVE_SYNC("true")
544 static void radv_init_dri_options(struct radv_instance
*instance
)
546 driParseOptionInfo(&instance
->available_dri_options
, radv_dri_options_xml
);
547 driParseConfigFiles(&instance
->dri_options
,
548 &instance
->available_dri_options
,
552 VkResult
radv_CreateInstance(
553 const VkInstanceCreateInfo
* pCreateInfo
,
554 const VkAllocationCallbacks
* pAllocator
,
555 VkInstance
* pInstance
)
557 struct radv_instance
*instance
;
560 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO
);
562 uint32_t client_version
;
563 if (pCreateInfo
->pApplicationInfo
&&
564 pCreateInfo
->pApplicationInfo
->apiVersion
!= 0) {
565 client_version
= pCreateInfo
->pApplicationInfo
->apiVersion
;
567 client_version
= VK_API_VERSION_1_0
;
570 instance
= vk_zalloc2(&default_alloc
, pAllocator
, sizeof(*instance
), 8,
571 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
573 return vk_error(NULL
, VK_ERROR_OUT_OF_HOST_MEMORY
);
575 instance
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
578 instance
->alloc
= *pAllocator
;
580 instance
->alloc
= default_alloc
;
582 instance
->apiVersion
= client_version
;
583 instance
->physicalDeviceCount
= -1;
585 instance
->debug_flags
= parse_debug_string(getenv("RADV_DEBUG"),
588 instance
->perftest_flags
= parse_debug_string(getenv("RADV_PERFTEST"),
589 radv_perftest_options
);
592 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
593 radv_logi("Created an instance");
595 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
596 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
597 int index
= radv_get_instance_extension_index(ext_name
);
599 if (index
< 0 || !radv_supported_instance_extensions
.extensions
[index
]) {
600 vk_free2(&default_alloc
, pAllocator
, instance
);
601 return vk_error(instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
604 instance
->enabled_extensions
.extensions
[index
] = true;
607 result
= vk_debug_report_instance_init(&instance
->debug_report_callbacks
);
608 if (result
!= VK_SUCCESS
) {
609 vk_free2(&default_alloc
, pAllocator
, instance
);
610 return vk_error(instance
, result
);
614 glsl_type_singleton_init_or_ref();
616 VG(VALGRIND_CREATE_MEMPOOL(instance
, 0, false));
618 radv_init_dri_options(instance
);
619 radv_handle_per_app_options(instance
, pCreateInfo
->pApplicationInfo
);
621 *pInstance
= radv_instance_to_handle(instance
);
626 void radv_DestroyInstance(
627 VkInstance _instance
,
628 const VkAllocationCallbacks
* pAllocator
)
630 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
635 for (int i
= 0; i
< instance
->physicalDeviceCount
; ++i
) {
636 radv_physical_device_finish(instance
->physicalDevices
+ i
);
639 VG(VALGRIND_DESTROY_MEMPOOL(instance
));
641 glsl_type_singleton_decref();
644 driDestroyOptionCache(&instance
->dri_options
);
645 driDestroyOptionInfo(&instance
->available_dri_options
);
647 vk_debug_report_instance_destroy(&instance
->debug_report_callbacks
);
649 vk_free(&instance
->alloc
, instance
);
653 radv_enumerate_devices(struct radv_instance
*instance
)
655 /* TODO: Check for more devices ? */
656 drmDevicePtr devices
[8];
657 VkResult result
= VK_ERROR_INCOMPATIBLE_DRIVER
;
660 instance
->physicalDeviceCount
= 0;
662 max_devices
= drmGetDevices2(0, devices
, ARRAY_SIZE(devices
));
664 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
665 radv_logi("Found %d drm nodes", max_devices
);
668 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
670 for (unsigned i
= 0; i
< (unsigned)max_devices
; i
++) {
671 if (devices
[i
]->available_nodes
& 1 << DRM_NODE_RENDER
&&
672 devices
[i
]->bustype
== DRM_BUS_PCI
&&
673 devices
[i
]->deviceinfo
.pci
->vendor_id
== ATI_VENDOR_ID
) {
675 result
= radv_physical_device_init(instance
->physicalDevices
+
676 instance
->physicalDeviceCount
,
679 if (result
== VK_SUCCESS
)
680 ++instance
->physicalDeviceCount
;
681 else if (result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
685 drmFreeDevices(devices
, max_devices
);
690 VkResult
radv_EnumeratePhysicalDevices(
691 VkInstance _instance
,
692 uint32_t* pPhysicalDeviceCount
,
693 VkPhysicalDevice
* pPhysicalDevices
)
695 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
698 if (instance
->physicalDeviceCount
< 0) {
699 result
= radv_enumerate_devices(instance
);
700 if (result
!= VK_SUCCESS
&&
701 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
705 if (!pPhysicalDevices
) {
706 *pPhysicalDeviceCount
= instance
->physicalDeviceCount
;
708 *pPhysicalDeviceCount
= MIN2(*pPhysicalDeviceCount
, instance
->physicalDeviceCount
);
709 for (unsigned i
= 0; i
< *pPhysicalDeviceCount
; ++i
)
710 pPhysicalDevices
[i
] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
713 return *pPhysicalDeviceCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
717 VkResult
radv_EnumeratePhysicalDeviceGroups(
718 VkInstance _instance
,
719 uint32_t* pPhysicalDeviceGroupCount
,
720 VkPhysicalDeviceGroupProperties
* pPhysicalDeviceGroupProperties
)
722 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
725 if (instance
->physicalDeviceCount
< 0) {
726 result
= radv_enumerate_devices(instance
);
727 if (result
!= VK_SUCCESS
&&
728 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
732 if (!pPhysicalDeviceGroupProperties
) {
733 *pPhysicalDeviceGroupCount
= instance
->physicalDeviceCount
;
735 *pPhysicalDeviceGroupCount
= MIN2(*pPhysicalDeviceGroupCount
, instance
->physicalDeviceCount
);
736 for (unsigned i
= 0; i
< *pPhysicalDeviceGroupCount
; ++i
) {
737 pPhysicalDeviceGroupProperties
[i
].physicalDeviceCount
= 1;
738 pPhysicalDeviceGroupProperties
[i
].physicalDevices
[0] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
739 pPhysicalDeviceGroupProperties
[i
].subsetAllocation
= false;
742 return *pPhysicalDeviceGroupCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
746 void radv_GetPhysicalDeviceFeatures(
747 VkPhysicalDevice physicalDevice
,
748 VkPhysicalDeviceFeatures
* pFeatures
)
750 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
751 memset(pFeatures
, 0, sizeof(*pFeatures
));
753 *pFeatures
= (VkPhysicalDeviceFeatures
) {
754 .robustBufferAccess
= true,
755 .fullDrawIndexUint32
= true,
756 .imageCubeArray
= true,
757 .independentBlend
= true,
758 .geometryShader
= true,
759 .tessellationShader
= true,
760 .sampleRateShading
= true,
761 .dualSrcBlend
= true,
763 .multiDrawIndirect
= true,
764 .drawIndirectFirstInstance
= true,
766 .depthBiasClamp
= true,
767 .fillModeNonSolid
= true,
772 .multiViewport
= true,
773 .samplerAnisotropy
= true,
774 .textureCompressionETC2
= radv_device_supports_etc(pdevice
),
775 .textureCompressionASTC_LDR
= false,
776 .textureCompressionBC
= true,
777 .occlusionQueryPrecise
= true,
778 .pipelineStatisticsQuery
= true,
779 .vertexPipelineStoresAndAtomics
= true,
780 .fragmentStoresAndAtomics
= true,
781 .shaderTessellationAndGeometryPointSize
= true,
782 .shaderImageGatherExtended
= true,
783 .shaderStorageImageExtendedFormats
= true,
784 .shaderStorageImageMultisample
= pdevice
->rad_info
.chip_class
>= GFX8
,
785 .shaderUniformBufferArrayDynamicIndexing
= true,
786 .shaderSampledImageArrayDynamicIndexing
= true,
787 .shaderStorageBufferArrayDynamicIndexing
= true,
788 .shaderStorageImageArrayDynamicIndexing
= true,
789 .shaderStorageImageReadWithoutFormat
= true,
790 .shaderStorageImageWriteWithoutFormat
= true,
791 .shaderClipDistance
= true,
792 .shaderCullDistance
= true,
793 .shaderFloat64
= true,
795 .shaderInt16
= pdevice
->rad_info
.chip_class
>= GFX9
,
796 .sparseBinding
= true,
797 .variableMultisampleRate
= true,
798 .inheritedQueries
= true,
802 void radv_GetPhysicalDeviceFeatures2(
803 VkPhysicalDevice physicalDevice
,
804 VkPhysicalDeviceFeatures2
*pFeatures
)
806 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
807 vk_foreach_struct(ext
, pFeatures
->pNext
) {
808 switch (ext
->sType
) {
809 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES
: {
810 VkPhysicalDeviceVariablePointersFeatures
*features
= (void *)ext
;
811 features
->variablePointersStorageBuffer
= true;
812 features
->variablePointers
= true;
815 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES
: {
816 VkPhysicalDeviceMultiviewFeatures
*features
= (VkPhysicalDeviceMultiviewFeatures
*)ext
;
817 features
->multiview
= true;
818 features
->multiviewGeometryShader
= true;
819 features
->multiviewTessellationShader
= true;
822 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES
: {
823 VkPhysicalDeviceShaderDrawParametersFeatures
*features
=
824 (VkPhysicalDeviceShaderDrawParametersFeatures
*)ext
;
825 features
->shaderDrawParameters
= true;
828 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES
: {
829 VkPhysicalDeviceProtectedMemoryFeatures
*features
=
830 (VkPhysicalDeviceProtectedMemoryFeatures
*)ext
;
831 features
->protectedMemory
= false;
834 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES
: {
835 VkPhysicalDevice16BitStorageFeatures
*features
=
836 (VkPhysicalDevice16BitStorageFeatures
*)ext
;
837 bool enabled
= pdevice
->rad_info
.chip_class
>= GFX8
;
838 features
->storageBuffer16BitAccess
= enabled
;
839 features
->uniformAndStorageBuffer16BitAccess
= enabled
;
840 features
->storagePushConstant16
= enabled
;
841 features
->storageInputOutput16
= enabled
&& HAVE_LLVM
>= 0x900;
844 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES
: {
845 VkPhysicalDeviceSamplerYcbcrConversionFeatures
*features
=
846 (VkPhysicalDeviceSamplerYcbcrConversionFeatures
*)ext
;
847 features
->samplerYcbcrConversion
= true;
850 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT
: {
851 VkPhysicalDeviceDescriptorIndexingFeaturesEXT
*features
=
852 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT
*)ext
;
853 features
->shaderInputAttachmentArrayDynamicIndexing
= true;
854 features
->shaderUniformTexelBufferArrayDynamicIndexing
= true;
855 features
->shaderStorageTexelBufferArrayDynamicIndexing
= true;
856 features
->shaderUniformBufferArrayNonUniformIndexing
= true;
857 features
->shaderSampledImageArrayNonUniformIndexing
= true;
858 features
->shaderStorageBufferArrayNonUniformIndexing
= true;
859 features
->shaderStorageImageArrayNonUniformIndexing
= true;
860 features
->shaderInputAttachmentArrayNonUniformIndexing
= true;
861 features
->shaderUniformTexelBufferArrayNonUniformIndexing
= true;
862 features
->shaderStorageTexelBufferArrayNonUniformIndexing
= true;
863 features
->descriptorBindingUniformBufferUpdateAfterBind
= true;
864 features
->descriptorBindingSampledImageUpdateAfterBind
= true;
865 features
->descriptorBindingStorageImageUpdateAfterBind
= true;
866 features
->descriptorBindingStorageBufferUpdateAfterBind
= true;
867 features
->descriptorBindingUniformTexelBufferUpdateAfterBind
= true;
868 features
->descriptorBindingStorageTexelBufferUpdateAfterBind
= true;
869 features
->descriptorBindingUpdateUnusedWhilePending
= true;
870 features
->descriptorBindingPartiallyBound
= true;
871 features
->descriptorBindingVariableDescriptorCount
= true;
872 features
->runtimeDescriptorArray
= true;
875 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT
: {
876 VkPhysicalDeviceConditionalRenderingFeaturesEXT
*features
=
877 (VkPhysicalDeviceConditionalRenderingFeaturesEXT
*)ext
;
878 features
->conditionalRendering
= true;
879 features
->inheritedConditionalRendering
= false;
882 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT
: {
883 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*features
=
884 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*)ext
;
885 features
->vertexAttributeInstanceRateDivisor
= VK_TRUE
;
886 features
->vertexAttributeInstanceRateZeroDivisor
= VK_TRUE
;
889 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT
: {
890 VkPhysicalDeviceTransformFeedbackFeaturesEXT
*features
=
891 (VkPhysicalDeviceTransformFeedbackFeaturesEXT
*)ext
;
892 features
->transformFeedback
= true;
893 features
->geometryStreams
= true;
896 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT
: {
897 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT
*features
=
898 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT
*)ext
;
899 features
->scalarBlockLayout
= pdevice
->rad_info
.chip_class
>= GFX7
;
902 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT
: {
903 VkPhysicalDeviceMemoryPriorityFeaturesEXT
*features
=
904 (VkPhysicalDeviceMemoryPriorityFeaturesEXT
*)ext
;
905 features
->memoryPriority
= VK_TRUE
;
908 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT
: {
909 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*features
=
910 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*)ext
;
911 features
->bufferDeviceAddress
= true;
912 features
->bufferDeviceAddressCaptureReplay
= false;
913 features
->bufferDeviceAddressMultiDevice
= false;
916 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT
: {
917 VkPhysicalDeviceDepthClipEnableFeaturesEXT
*features
=
918 (VkPhysicalDeviceDepthClipEnableFeaturesEXT
*)ext
;
919 features
->depthClipEnable
= true;
922 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT
: {
923 VkPhysicalDeviceHostQueryResetFeaturesEXT
*features
=
924 (VkPhysicalDeviceHostQueryResetFeaturesEXT
*)ext
;
925 features
->hostQueryReset
= true;
928 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR
: {
929 VkPhysicalDevice8BitStorageFeaturesKHR
*features
=
930 (VkPhysicalDevice8BitStorageFeaturesKHR
*)ext
;
931 bool enabled
= pdevice
->rad_info
.chip_class
>= GFX8
;
932 features
->storageBuffer8BitAccess
= enabled
;
933 features
->uniformAndStorageBuffer8BitAccess
= enabled
;
934 features
->storagePushConstant8
= enabled
;
937 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR
: {
938 VkPhysicalDeviceFloat16Int8FeaturesKHR
*features
=
939 (VkPhysicalDeviceFloat16Int8FeaturesKHR
*)ext
;
940 features
->shaderFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
&& HAVE_LLVM
>= 0x0800;
941 features
->shaderInt8
= true;
944 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR
: {
945 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR
*features
=
946 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR
*)ext
;
947 /* TODO: Enable this once the driver supports 64-bit
948 * compare&swap atomic operations.
950 features
->shaderBufferInt64Atomics
= false;
951 features
->shaderSharedInt64Atomics
= false;
954 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT
: {
955 VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*features
=
956 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*)ext
;
958 features
->inlineUniformBlock
= true;
959 features
->descriptorBindingInlineUniformBlockUpdateAfterBind
= true;
962 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV
: {
963 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*features
=
964 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*)ext
;
965 features
->computeDerivativeGroupQuads
= false;
966 features
->computeDerivativeGroupLinear
= true;
969 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT
: {
970 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*features
=
971 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*)ext
;
972 features
->ycbcrImageArrays
= true;
975 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR
: {
976 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR
*features
=
977 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR
*)ext
;
978 features
->uniformBufferStandardLayout
= true;
985 return radv_GetPhysicalDeviceFeatures(physicalDevice
, &pFeatures
->features
);
988 void radv_GetPhysicalDeviceProperties(
989 VkPhysicalDevice physicalDevice
,
990 VkPhysicalDeviceProperties
* pProperties
)
992 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
993 VkSampleCountFlags sample_counts
= 0xf;
995 /* make sure that the entire descriptor set is addressable with a signed
996 * 32-bit int. So the sum of all limits scaled by descriptor size has to
997 * be at most 2 GiB. the combined image & samples object count as one of
998 * both. This limit is for the pipeline layout, not for the set layout, but
999 * there is no set limit, so we just set a pipeline limit. I don't think
1000 * any app is going to hit this soon. */
1001 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
) /
1002 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1003 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1004 32 /* sampler, largest when combined with image */ +
1005 64 /* sampled image */ +
1006 64 /* storage image */);
1008 VkPhysicalDeviceLimits limits
= {
1009 .maxImageDimension1D
= (1 << 14),
1010 .maxImageDimension2D
= (1 << 14),
1011 .maxImageDimension3D
= (1 << 11),
1012 .maxImageDimensionCube
= (1 << 14),
1013 .maxImageArrayLayers
= (1 << 11),
1014 .maxTexelBufferElements
= 128 * 1024 * 1024,
1015 .maxUniformBufferRange
= UINT32_MAX
,
1016 .maxStorageBufferRange
= UINT32_MAX
,
1017 .maxPushConstantsSize
= MAX_PUSH_CONSTANTS_SIZE
,
1018 .maxMemoryAllocationCount
= UINT32_MAX
,
1019 .maxSamplerAllocationCount
= 64 * 1024,
1020 .bufferImageGranularity
= 64, /* A cache line */
1021 .sparseAddressSpaceSize
= 0xffffffffu
, /* buffer max size */
1022 .maxBoundDescriptorSets
= MAX_SETS
,
1023 .maxPerStageDescriptorSamplers
= max_descriptor_set_size
,
1024 .maxPerStageDescriptorUniformBuffers
= max_descriptor_set_size
,
1025 .maxPerStageDescriptorStorageBuffers
= max_descriptor_set_size
,
1026 .maxPerStageDescriptorSampledImages
= max_descriptor_set_size
,
1027 .maxPerStageDescriptorStorageImages
= max_descriptor_set_size
,
1028 .maxPerStageDescriptorInputAttachments
= max_descriptor_set_size
,
1029 .maxPerStageResources
= max_descriptor_set_size
,
1030 .maxDescriptorSetSamplers
= max_descriptor_set_size
,
1031 .maxDescriptorSetUniformBuffers
= max_descriptor_set_size
,
1032 .maxDescriptorSetUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
,
1033 .maxDescriptorSetStorageBuffers
= max_descriptor_set_size
,
1034 .maxDescriptorSetStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
,
1035 .maxDescriptorSetSampledImages
= max_descriptor_set_size
,
1036 .maxDescriptorSetStorageImages
= max_descriptor_set_size
,
1037 .maxDescriptorSetInputAttachments
= max_descriptor_set_size
,
1038 .maxVertexInputAttributes
= MAX_VERTEX_ATTRIBS
,
1039 .maxVertexInputBindings
= MAX_VBS
,
1040 .maxVertexInputAttributeOffset
= 2047,
1041 .maxVertexInputBindingStride
= 2048,
1042 .maxVertexOutputComponents
= 128,
1043 .maxTessellationGenerationLevel
= 64,
1044 .maxTessellationPatchSize
= 32,
1045 .maxTessellationControlPerVertexInputComponents
= 128,
1046 .maxTessellationControlPerVertexOutputComponents
= 128,
1047 .maxTessellationControlPerPatchOutputComponents
= 120,
1048 .maxTessellationControlTotalOutputComponents
= 4096,
1049 .maxTessellationEvaluationInputComponents
= 128,
1050 .maxTessellationEvaluationOutputComponents
= 128,
1051 .maxGeometryShaderInvocations
= 127,
1052 .maxGeometryInputComponents
= 64,
1053 .maxGeometryOutputComponents
= 128,
1054 .maxGeometryOutputVertices
= 256,
1055 .maxGeometryTotalOutputComponents
= 1024,
1056 .maxFragmentInputComponents
= 128,
1057 .maxFragmentOutputAttachments
= 8,
1058 .maxFragmentDualSrcAttachments
= 1,
1059 .maxFragmentCombinedOutputResources
= 8,
1060 .maxComputeSharedMemorySize
= 32768,
1061 .maxComputeWorkGroupCount
= { 65535, 65535, 65535 },
1062 .maxComputeWorkGroupInvocations
= 2048,
1063 .maxComputeWorkGroupSize
= {
1068 .subPixelPrecisionBits
= 8,
1069 .subTexelPrecisionBits
= 8,
1070 .mipmapPrecisionBits
= 8,
1071 .maxDrawIndexedIndexValue
= UINT32_MAX
,
1072 .maxDrawIndirectCount
= UINT32_MAX
,
1073 .maxSamplerLodBias
= 16,
1074 .maxSamplerAnisotropy
= 16,
1075 .maxViewports
= MAX_VIEWPORTS
,
1076 .maxViewportDimensions
= { (1 << 14), (1 << 14) },
1077 .viewportBoundsRange
= { INT16_MIN
, INT16_MAX
},
1078 .viewportSubPixelBits
= 8,
1079 .minMemoryMapAlignment
= 4096, /* A page */
1080 .minTexelBufferOffsetAlignment
= 1,
1081 .minUniformBufferOffsetAlignment
= 4,
1082 .minStorageBufferOffsetAlignment
= 4,
1083 .minTexelOffset
= -32,
1084 .maxTexelOffset
= 31,
1085 .minTexelGatherOffset
= -32,
1086 .maxTexelGatherOffset
= 31,
1087 .minInterpolationOffset
= -2,
1088 .maxInterpolationOffset
= 2,
1089 .subPixelInterpolationOffsetBits
= 8,
1090 .maxFramebufferWidth
= (1 << 14),
1091 .maxFramebufferHeight
= (1 << 14),
1092 .maxFramebufferLayers
= (1 << 10),
1093 .framebufferColorSampleCounts
= sample_counts
,
1094 .framebufferDepthSampleCounts
= sample_counts
,
1095 .framebufferStencilSampleCounts
= sample_counts
,
1096 .framebufferNoAttachmentsSampleCounts
= sample_counts
,
1097 .maxColorAttachments
= MAX_RTS
,
1098 .sampledImageColorSampleCounts
= sample_counts
,
1099 .sampledImageIntegerSampleCounts
= VK_SAMPLE_COUNT_1_BIT
,
1100 .sampledImageDepthSampleCounts
= sample_counts
,
1101 .sampledImageStencilSampleCounts
= sample_counts
,
1102 .storageImageSampleCounts
= pdevice
->rad_info
.chip_class
>= GFX8
? sample_counts
: VK_SAMPLE_COUNT_1_BIT
,
1103 .maxSampleMaskWords
= 1,
1104 .timestampComputeAndGraphics
= true,
1105 .timestampPeriod
= 1000000.0 / pdevice
->rad_info
.clock_crystal_freq
,
1106 .maxClipDistances
= 8,
1107 .maxCullDistances
= 8,
1108 .maxCombinedClipAndCullDistances
= 8,
1109 .discreteQueuePriorities
= 2,
1110 .pointSizeRange
= { 0.0, 8192.0 },
1111 .lineWidthRange
= { 0.0, 7.9921875 },
1112 .pointSizeGranularity
= (1.0 / 8.0),
1113 .lineWidthGranularity
= (1.0 / 128.0),
1114 .strictLines
= false, /* FINISHME */
1115 .standardSampleLocations
= true,
1116 .optimalBufferCopyOffsetAlignment
= 128,
1117 .optimalBufferCopyRowPitchAlignment
= 128,
1118 .nonCoherentAtomSize
= 64,
1121 *pProperties
= (VkPhysicalDeviceProperties
) {
1122 .apiVersion
= radv_physical_device_api_version(pdevice
),
1123 .driverVersion
= vk_get_driver_version(),
1124 .vendorID
= ATI_VENDOR_ID
,
1125 .deviceID
= pdevice
->rad_info
.pci_id
,
1126 .deviceType
= pdevice
->rad_info
.has_dedicated_vram
? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU
: VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU
,
1128 .sparseProperties
= {0},
1131 strcpy(pProperties
->deviceName
, pdevice
->name
);
1132 memcpy(pProperties
->pipelineCacheUUID
, pdevice
->cache_uuid
, VK_UUID_SIZE
);
1135 void radv_GetPhysicalDeviceProperties2(
1136 VkPhysicalDevice physicalDevice
,
1137 VkPhysicalDeviceProperties2
*pProperties
)
1139 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1140 radv_GetPhysicalDeviceProperties(physicalDevice
, &pProperties
->properties
);
1142 vk_foreach_struct(ext
, pProperties
->pNext
) {
1143 switch (ext
->sType
) {
1144 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR
: {
1145 VkPhysicalDevicePushDescriptorPropertiesKHR
*properties
=
1146 (VkPhysicalDevicePushDescriptorPropertiesKHR
*) ext
;
1147 properties
->maxPushDescriptors
= MAX_PUSH_DESCRIPTORS
;
1150 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES
: {
1151 VkPhysicalDeviceIDProperties
*properties
= (VkPhysicalDeviceIDProperties
*)ext
;
1152 memcpy(properties
->driverUUID
, pdevice
->driver_uuid
, VK_UUID_SIZE
);
1153 memcpy(properties
->deviceUUID
, pdevice
->device_uuid
, VK_UUID_SIZE
);
1154 properties
->deviceLUIDValid
= false;
1157 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES
: {
1158 VkPhysicalDeviceMultiviewProperties
*properties
= (VkPhysicalDeviceMultiviewProperties
*)ext
;
1159 properties
->maxMultiviewViewCount
= MAX_VIEWS
;
1160 properties
->maxMultiviewInstanceIndex
= INT_MAX
;
1163 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES
: {
1164 VkPhysicalDevicePointClippingProperties
*properties
=
1165 (VkPhysicalDevicePointClippingProperties
*)ext
;
1166 properties
->pointClippingBehavior
= VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES
;
1169 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT
: {
1170 VkPhysicalDeviceDiscardRectanglePropertiesEXT
*properties
=
1171 (VkPhysicalDeviceDiscardRectanglePropertiesEXT
*)ext
;
1172 properties
->maxDiscardRectangles
= MAX_DISCARD_RECTANGLES
;
1175 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT
: {
1176 VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*properties
=
1177 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*) ext
;
1178 properties
->minImportedHostPointerAlignment
= 4096;
1181 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES
: {
1182 VkPhysicalDeviceSubgroupProperties
*properties
=
1183 (VkPhysicalDeviceSubgroupProperties
*)ext
;
1184 properties
->subgroupSize
= 64;
1185 properties
->supportedStages
= VK_SHADER_STAGE_ALL
;
1186 properties
->supportedOperations
=
1187 VK_SUBGROUP_FEATURE_BASIC_BIT
|
1188 VK_SUBGROUP_FEATURE_BALLOT_BIT
|
1189 VK_SUBGROUP_FEATURE_QUAD_BIT
|
1190 VK_SUBGROUP_FEATURE_VOTE_BIT
;
1191 if (pdevice
->rad_info
.chip_class
>= GFX8
) {
1192 properties
->supportedOperations
|=
1193 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT
|
1194 VK_SUBGROUP_FEATURE_SHUFFLE_BIT
|
1195 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT
;
1197 properties
->quadOperationsInAllStages
= true;
1200 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES
: {
1201 VkPhysicalDeviceMaintenance3Properties
*properties
=
1202 (VkPhysicalDeviceMaintenance3Properties
*)ext
;
1203 /* Make sure everything is addressable by a signed 32-bit int, and
1204 * our largest descriptors are 96 bytes. */
1205 properties
->maxPerSetDescriptors
= (1ull << 31) / 96;
1206 /* Our buffer size fields allow only this much */
1207 properties
->maxMemoryAllocationSize
= 0xFFFFFFFFull
;
1210 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT
: {
1211 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT
*properties
=
1212 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT
*)ext
;
1213 /* GFX6-8 only support single channel min/max filter. */
1214 properties
->filterMinmaxImageComponentMapping
= pdevice
->rad_info
.chip_class
>= GFX9
;
1215 properties
->filterMinmaxSingleComponentFormats
= true;
1218 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD
: {
1219 VkPhysicalDeviceShaderCorePropertiesAMD
*properties
=
1220 (VkPhysicalDeviceShaderCorePropertiesAMD
*)ext
;
1222 /* Shader engines. */
1223 properties
->shaderEngineCount
=
1224 pdevice
->rad_info
.max_se
;
1225 properties
->shaderArraysPerEngineCount
=
1226 pdevice
->rad_info
.max_sh_per_se
;
1227 properties
->computeUnitsPerShaderArray
=
1228 pdevice
->rad_info
.num_good_cu_per_sh
;
1229 properties
->simdPerComputeUnit
= 4;
1230 properties
->wavefrontsPerSimd
=
1231 pdevice
->rad_info
.family
== CHIP_TONGA
||
1232 pdevice
->rad_info
.family
== CHIP_ICELAND
||
1233 pdevice
->rad_info
.family
== CHIP_POLARIS10
||
1234 pdevice
->rad_info
.family
== CHIP_POLARIS11
||
1235 pdevice
->rad_info
.family
== CHIP_POLARIS12
||
1236 pdevice
->rad_info
.family
== CHIP_VEGAM
? 8 : 10;
1237 properties
->wavefrontSize
= 64;
1240 properties
->sgprsPerSimd
=
1241 ac_get_num_physical_sgprs(pdevice
->rad_info
.chip_class
);
1242 properties
->minSgprAllocation
=
1243 pdevice
->rad_info
.chip_class
>= GFX8
? 16 : 8;
1244 properties
->maxSgprAllocation
=
1245 pdevice
->rad_info
.family
== CHIP_TONGA
||
1246 pdevice
->rad_info
.family
== CHIP_ICELAND
? 96 : 104;
1247 properties
->sgprAllocationGranularity
=
1248 pdevice
->rad_info
.chip_class
>= GFX8
? 16 : 8;
1251 properties
->vgprsPerSimd
= RADV_NUM_PHYSICAL_VGPRS
;
1252 properties
->minVgprAllocation
= 4;
1253 properties
->maxVgprAllocation
= 256;
1254 properties
->vgprAllocationGranularity
= 4;
1257 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT
: {
1258 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*properties
=
1259 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*)ext
;
1260 properties
->maxVertexAttribDivisor
= UINT32_MAX
;
1263 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT
: {
1264 VkPhysicalDeviceDescriptorIndexingPropertiesEXT
*properties
=
1265 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT
*)ext
;
1266 properties
->maxUpdateAfterBindDescriptorsInAllPools
= UINT32_MAX
/ 64;
1267 properties
->shaderUniformBufferArrayNonUniformIndexingNative
= false;
1268 properties
->shaderSampledImageArrayNonUniformIndexingNative
= false;
1269 properties
->shaderStorageBufferArrayNonUniformIndexingNative
= false;
1270 properties
->shaderStorageImageArrayNonUniformIndexingNative
= false;
1271 properties
->shaderInputAttachmentArrayNonUniformIndexingNative
= false;
1272 properties
->robustBufferAccessUpdateAfterBind
= false;
1273 properties
->quadDivergentImplicitLod
= false;
1275 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
-
1276 MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_INLINE_UNIFORM_BLOCK_COUNT
) /
1277 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1278 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1279 32 /* sampler, largest when combined with image */ +
1280 64 /* sampled image */ +
1281 64 /* storage image */);
1282 properties
->maxPerStageDescriptorUpdateAfterBindSamplers
= max_descriptor_set_size
;
1283 properties
->maxPerStageDescriptorUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1284 properties
->maxPerStageDescriptorUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1285 properties
->maxPerStageDescriptorUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1286 properties
->maxPerStageDescriptorUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1287 properties
->maxPerStageDescriptorUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1288 properties
->maxPerStageUpdateAfterBindResources
= max_descriptor_set_size
;
1289 properties
->maxDescriptorSetUpdateAfterBindSamplers
= max_descriptor_set_size
;
1290 properties
->maxDescriptorSetUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1291 properties
->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
;
1292 properties
->maxDescriptorSetUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1293 properties
->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
;
1294 properties
->maxDescriptorSetUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1295 properties
->maxDescriptorSetUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1296 properties
->maxDescriptorSetUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1299 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES
: {
1300 VkPhysicalDeviceProtectedMemoryProperties
*properties
=
1301 (VkPhysicalDeviceProtectedMemoryProperties
*)ext
;
1302 properties
->protectedNoFault
= false;
1305 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT
: {
1306 VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*properties
=
1307 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*)ext
;
1308 properties
->primitiveOverestimationSize
= 0;
1309 properties
->maxExtraPrimitiveOverestimationSize
= 0;
1310 properties
->extraPrimitiveOverestimationSizeGranularity
= 0;
1311 properties
->primitiveUnderestimation
= VK_FALSE
;
1312 properties
->conservativePointAndLineRasterization
= VK_FALSE
;
1313 properties
->degenerateTrianglesRasterized
= VK_FALSE
;
1314 properties
->degenerateLinesRasterized
= VK_FALSE
;
1315 properties
->fullyCoveredFragmentShaderInputVariable
= VK_FALSE
;
1316 properties
->conservativeRasterizationPostDepthCoverage
= VK_FALSE
;
1319 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT
: {
1320 VkPhysicalDevicePCIBusInfoPropertiesEXT
*properties
=
1321 (VkPhysicalDevicePCIBusInfoPropertiesEXT
*)ext
;
1322 properties
->pciDomain
= pdevice
->bus_info
.domain
;
1323 properties
->pciBus
= pdevice
->bus_info
.bus
;
1324 properties
->pciDevice
= pdevice
->bus_info
.dev
;
1325 properties
->pciFunction
= pdevice
->bus_info
.func
;
1328 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR
: {
1329 VkPhysicalDeviceDriverPropertiesKHR
*driver_props
=
1330 (VkPhysicalDeviceDriverPropertiesKHR
*) ext
;
1332 driver_props
->driverID
= VK_DRIVER_ID_MESA_RADV_KHR
;
1333 memset(driver_props
->driverName
, 0, VK_MAX_DRIVER_NAME_SIZE_KHR
);
1334 strcpy(driver_props
->driverName
, "radv");
1336 memset(driver_props
->driverInfo
, 0, VK_MAX_DRIVER_INFO_SIZE_KHR
);
1337 snprintf(driver_props
->driverInfo
, VK_MAX_DRIVER_INFO_SIZE_KHR
,
1338 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1339 " (LLVM " MESA_LLVM_VERSION_STRING
")");
1341 driver_props
->conformanceVersion
= (VkConformanceVersionKHR
) {
1349 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT
: {
1350 VkPhysicalDeviceTransformFeedbackPropertiesEXT
*properties
=
1351 (VkPhysicalDeviceTransformFeedbackPropertiesEXT
*)ext
;
1352 properties
->maxTransformFeedbackStreams
= MAX_SO_STREAMS
;
1353 properties
->maxTransformFeedbackBuffers
= MAX_SO_BUFFERS
;
1354 properties
->maxTransformFeedbackBufferSize
= UINT32_MAX
;
1355 properties
->maxTransformFeedbackStreamDataSize
= 512;
1356 properties
->maxTransformFeedbackBufferDataSize
= UINT32_MAX
;
1357 properties
->maxTransformFeedbackBufferDataStride
= 512;
1358 properties
->transformFeedbackQueries
= true;
1359 properties
->transformFeedbackStreamsLinesTriangles
= true;
1360 properties
->transformFeedbackRasterizationStreamSelect
= false;
1361 properties
->transformFeedbackDraw
= true;
1364 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT
: {
1365 VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*props
=
1366 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*)ext
;
1368 props
->maxInlineUniformBlockSize
= MAX_INLINE_UNIFORM_BLOCK_SIZE
;
1369 props
->maxPerStageDescriptorInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1370 props
->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1371 props
->maxDescriptorSetInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1372 props
->maxDescriptorSetUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1375 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT
: {
1376 VkPhysicalDeviceSampleLocationsPropertiesEXT
*properties
=
1377 (VkPhysicalDeviceSampleLocationsPropertiesEXT
*)ext
;
1378 properties
->sampleLocationSampleCounts
= VK_SAMPLE_COUNT_2_BIT
|
1379 VK_SAMPLE_COUNT_4_BIT
|
1380 VK_SAMPLE_COUNT_8_BIT
;
1381 properties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2 , 2 };
1382 properties
->sampleLocationCoordinateRange
[0] = 0.0f
;
1383 properties
->sampleLocationCoordinateRange
[1] = 0.9375f
;
1384 properties
->sampleLocationSubPixelBits
= 4;
1385 properties
->variableSampleLocations
= VK_FALSE
;
1388 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES_KHR
: {
1389 VkPhysicalDeviceDepthStencilResolvePropertiesKHR
*properties
=
1390 (VkPhysicalDeviceDepthStencilResolvePropertiesKHR
*)ext
;
1392 /* We support all of the depth resolve modes */
1393 properties
->supportedDepthResolveModes
=
1394 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
|
1395 VK_RESOLVE_MODE_AVERAGE_BIT_KHR
|
1396 VK_RESOLVE_MODE_MIN_BIT_KHR
|
1397 VK_RESOLVE_MODE_MAX_BIT_KHR
;
1399 /* Average doesn't make sense for stencil so we don't support that */
1400 properties
->supportedStencilResolveModes
=
1401 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
|
1402 VK_RESOLVE_MODE_MIN_BIT_KHR
|
1403 VK_RESOLVE_MODE_MAX_BIT_KHR
;
1405 properties
->independentResolveNone
= VK_TRUE
;
1406 properties
->independentResolve
= VK_TRUE
;
1415 static void radv_get_physical_device_queue_family_properties(
1416 struct radv_physical_device
* pdevice
,
1418 VkQueueFamilyProperties
** pQueueFamilyProperties
)
1420 int num_queue_families
= 1;
1422 if (pdevice
->rad_info
.num_compute_rings
> 0 &&
1423 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
))
1424 num_queue_families
++;
1426 if (pQueueFamilyProperties
== NULL
) {
1427 *pCount
= num_queue_families
;
1436 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
1437 .queueFlags
= VK_QUEUE_GRAPHICS_BIT
|
1438 VK_QUEUE_COMPUTE_BIT
|
1439 VK_QUEUE_TRANSFER_BIT
|
1440 VK_QUEUE_SPARSE_BINDING_BIT
,
1442 .timestampValidBits
= 64,
1443 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
1448 if (pdevice
->rad_info
.num_compute_rings
> 0 &&
1449 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
)) {
1450 if (*pCount
> idx
) {
1451 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
1452 .queueFlags
= VK_QUEUE_COMPUTE_BIT
|
1453 VK_QUEUE_TRANSFER_BIT
|
1454 VK_QUEUE_SPARSE_BINDING_BIT
,
1455 .queueCount
= pdevice
->rad_info
.num_compute_rings
,
1456 .timestampValidBits
= 64,
1457 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
1465 void radv_GetPhysicalDeviceQueueFamilyProperties(
1466 VkPhysicalDevice physicalDevice
,
1468 VkQueueFamilyProperties
* pQueueFamilyProperties
)
1470 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1471 if (!pQueueFamilyProperties
) {
1472 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
1475 VkQueueFamilyProperties
*properties
[] = {
1476 pQueueFamilyProperties
+ 0,
1477 pQueueFamilyProperties
+ 1,
1478 pQueueFamilyProperties
+ 2,
1480 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
1481 assert(*pCount
<= 3);
1484 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1485 VkPhysicalDevice physicalDevice
,
1487 VkQueueFamilyProperties2
*pQueueFamilyProperties
)
1489 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1490 if (!pQueueFamilyProperties
) {
1491 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
1494 VkQueueFamilyProperties
*properties
[] = {
1495 &pQueueFamilyProperties
[0].queueFamilyProperties
,
1496 &pQueueFamilyProperties
[1].queueFamilyProperties
,
1497 &pQueueFamilyProperties
[2].queueFamilyProperties
,
1499 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
1500 assert(*pCount
<= 3);
1503 void radv_GetPhysicalDeviceMemoryProperties(
1504 VkPhysicalDevice physicalDevice
,
1505 VkPhysicalDeviceMemoryProperties
*pMemoryProperties
)
1507 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
1509 *pMemoryProperties
= physical_device
->memory_properties
;
1513 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice
,
1514 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memoryBudget
)
1516 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
1517 VkPhysicalDeviceMemoryProperties
*memory_properties
= &device
->memory_properties
;
1518 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
1519 uint64_t vram_size
= radv_get_vram_size(device
);
1520 uint64_t gtt_size
= device
->rad_info
.gart_size
;
1521 uint64_t heap_budget
, heap_usage
;
1523 /* For all memory heaps, the computation of budget is as follow:
1524 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1526 * The Vulkan spec 1.1.97 says that the budget should include any
1527 * currently allocated device memory.
1529 * Note that the application heap usages are not really accurate (eg.
1530 * in presence of shared buffers).
1532 for (int i
= 0; i
< device
->memory_properties
.memoryTypeCount
; i
++) {
1533 uint32_t heap_index
= device
->memory_properties
.memoryTypes
[i
].heapIndex
;
1535 switch (device
->mem_type_indices
[i
]) {
1536 case RADV_MEM_TYPE_VRAM
:
1537 heap_usage
= device
->ws
->query_value(device
->ws
,
1538 RADEON_ALLOCATED_VRAM
);
1540 heap_budget
= vram_size
-
1541 device
->ws
->query_value(device
->ws
, RADEON_VRAM_USAGE
) +
1544 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
1545 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
1547 case RADV_MEM_TYPE_VRAM_CPU_ACCESS
:
1548 heap_usage
= device
->ws
->query_value(device
->ws
,
1549 RADEON_ALLOCATED_VRAM_VIS
);
1551 heap_budget
= visible_vram_size
-
1552 device
->ws
->query_value(device
->ws
, RADEON_VRAM_VIS_USAGE
) +
1555 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
1556 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
1558 case RADV_MEM_TYPE_GTT_WRITE_COMBINE
:
1559 heap_usage
= device
->ws
->query_value(device
->ws
,
1560 RADEON_ALLOCATED_GTT
);
1562 heap_budget
= gtt_size
-
1563 device
->ws
->query_value(device
->ws
, RADEON_GTT_USAGE
) +
1566 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
1567 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
1574 /* The heapBudget and heapUsage values must be zero for array elements
1575 * greater than or equal to
1576 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1578 for (uint32_t i
= memory_properties
->memoryHeapCount
; i
< VK_MAX_MEMORY_HEAPS
; i
++) {
1579 memoryBudget
->heapBudget
[i
] = 0;
1580 memoryBudget
->heapUsage
[i
] = 0;
1584 void radv_GetPhysicalDeviceMemoryProperties2(
1585 VkPhysicalDevice physicalDevice
,
1586 VkPhysicalDeviceMemoryProperties2
*pMemoryProperties
)
1588 radv_GetPhysicalDeviceMemoryProperties(physicalDevice
,
1589 &pMemoryProperties
->memoryProperties
);
1591 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memory_budget
=
1592 vk_find_struct(pMemoryProperties
->pNext
,
1593 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT
);
1595 radv_get_memory_budget_properties(physicalDevice
, memory_budget
);
1598 VkResult
radv_GetMemoryHostPointerPropertiesEXT(
1600 VkExternalMemoryHandleTypeFlagBits handleType
,
1601 const void *pHostPointer
,
1602 VkMemoryHostPointerPropertiesEXT
*pMemoryHostPointerProperties
)
1604 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1608 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
: {
1609 const struct radv_physical_device
*physical_device
= device
->physical_device
;
1610 uint32_t memoryTypeBits
= 0;
1611 for (int i
= 0; i
< physical_device
->memory_properties
.memoryTypeCount
; i
++) {
1612 if (physical_device
->mem_type_indices
[i
] == RADV_MEM_TYPE_GTT_CACHED
) {
1613 memoryTypeBits
= (1 << i
);
1617 pMemoryHostPointerProperties
->memoryTypeBits
= memoryTypeBits
;
1621 return VK_ERROR_INVALID_EXTERNAL_HANDLE
;
1625 static enum radeon_ctx_priority
1626 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT
*pObj
)
1628 /* Default to MEDIUM when a specific global priority isn't requested */
1630 return RADEON_CTX_PRIORITY_MEDIUM
;
1632 switch(pObj
->globalPriority
) {
1633 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT
:
1634 return RADEON_CTX_PRIORITY_REALTIME
;
1635 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT
:
1636 return RADEON_CTX_PRIORITY_HIGH
;
1637 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT
:
1638 return RADEON_CTX_PRIORITY_MEDIUM
;
1639 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT
:
1640 return RADEON_CTX_PRIORITY_LOW
;
1642 unreachable("Illegal global priority value");
1643 return RADEON_CTX_PRIORITY_INVALID
;
1648 radv_queue_init(struct radv_device
*device
, struct radv_queue
*queue
,
1649 uint32_t queue_family_index
, int idx
,
1650 VkDeviceQueueCreateFlags flags
,
1651 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
)
1653 queue
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1654 queue
->device
= device
;
1655 queue
->queue_family_index
= queue_family_index
;
1656 queue
->queue_idx
= idx
;
1657 queue
->priority
= radv_get_queue_global_priority(global_priority
);
1658 queue
->flags
= flags
;
1660 queue
->hw_ctx
= device
->ws
->ctx_create(device
->ws
, queue
->priority
);
1662 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1668 radv_queue_finish(struct radv_queue
*queue
)
1671 queue
->device
->ws
->ctx_destroy(queue
->hw_ctx
);
1673 if (queue
->initial_full_flush_preamble_cs
)
1674 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
1675 if (queue
->initial_preamble_cs
)
1676 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
1677 if (queue
->continue_preamble_cs
)
1678 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
1679 if (queue
->descriptor_bo
)
1680 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
1681 if (queue
->scratch_bo
)
1682 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
1683 if (queue
->esgs_ring_bo
)
1684 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
1685 if (queue
->gsvs_ring_bo
)
1686 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
1687 if (queue
->tess_rings_bo
)
1688 queue
->device
->ws
->buffer_destroy(queue
->tess_rings_bo
);
1689 if (queue
->compute_scratch_bo
)
1690 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
1694 radv_bo_list_init(struct radv_bo_list
*bo_list
)
1696 pthread_mutex_init(&bo_list
->mutex
, NULL
);
1697 bo_list
->list
.count
= bo_list
->capacity
= 0;
1698 bo_list
->list
.bos
= NULL
;
1702 radv_bo_list_finish(struct radv_bo_list
*bo_list
)
1704 free(bo_list
->list
.bos
);
1705 pthread_mutex_destroy(&bo_list
->mutex
);
1708 static VkResult
radv_bo_list_add(struct radv_device
*device
,
1709 struct radeon_winsys_bo
*bo
)
1711 struct radv_bo_list
*bo_list
= &device
->bo_list
;
1716 if (unlikely(!device
->use_global_bo_list
))
1719 pthread_mutex_lock(&bo_list
->mutex
);
1720 if (bo_list
->list
.count
== bo_list
->capacity
) {
1721 unsigned capacity
= MAX2(4, bo_list
->capacity
* 2);
1722 void *data
= realloc(bo_list
->list
.bos
, capacity
* sizeof(struct radeon_winsys_bo
*));
1725 pthread_mutex_unlock(&bo_list
->mutex
);
1726 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1729 bo_list
->list
.bos
= (struct radeon_winsys_bo
**)data
;
1730 bo_list
->capacity
= capacity
;
1733 bo_list
->list
.bos
[bo_list
->list
.count
++] = bo
;
1734 pthread_mutex_unlock(&bo_list
->mutex
);
1738 static void radv_bo_list_remove(struct radv_device
*device
,
1739 struct radeon_winsys_bo
*bo
)
1741 struct radv_bo_list
*bo_list
= &device
->bo_list
;
1746 if (unlikely(!device
->use_global_bo_list
))
1749 pthread_mutex_lock(&bo_list
->mutex
);
1750 for(unsigned i
= 0; i
< bo_list
->list
.count
; ++i
) {
1751 if (bo_list
->list
.bos
[i
] == bo
) {
1752 bo_list
->list
.bos
[i
] = bo_list
->list
.bos
[bo_list
->list
.count
- 1];
1753 --bo_list
->list
.count
;
1757 pthread_mutex_unlock(&bo_list
->mutex
);
1761 radv_device_init_gs_info(struct radv_device
*device
)
1763 device
->gs_table_depth
= ac_get_gs_table_depth(device
->physical_device
->rad_info
.chip_class
,
1764 device
->physical_device
->rad_info
.family
);
1767 static int radv_get_device_extension_index(const char *name
)
1769 for (unsigned i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; ++i
) {
1770 if (strcmp(name
, radv_device_extensions
[i
].extensionName
) == 0)
1777 radv_get_int_debug_option(const char *name
, int default_value
)
1784 result
= default_value
;
1788 result
= strtol(str
, &endptr
, 0);
1789 if (str
== endptr
) {
1790 /* No digits founs. */
1791 result
= default_value
;
1798 VkResult
radv_CreateDevice(
1799 VkPhysicalDevice physicalDevice
,
1800 const VkDeviceCreateInfo
* pCreateInfo
,
1801 const VkAllocationCallbacks
* pAllocator
,
1804 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
1806 struct radv_device
*device
;
1808 bool keep_shader_info
= false;
1810 /* Check enabled features */
1811 if (pCreateInfo
->pEnabledFeatures
) {
1812 VkPhysicalDeviceFeatures supported_features
;
1813 radv_GetPhysicalDeviceFeatures(physicalDevice
, &supported_features
);
1814 VkBool32
*supported_feature
= (VkBool32
*)&supported_features
;
1815 VkBool32
*enabled_feature
= (VkBool32
*)pCreateInfo
->pEnabledFeatures
;
1816 unsigned num_features
= sizeof(VkPhysicalDeviceFeatures
) / sizeof(VkBool32
);
1817 for (uint32_t i
= 0; i
< num_features
; i
++) {
1818 if (enabled_feature
[i
] && !supported_feature
[i
])
1819 return vk_error(physical_device
->instance
, VK_ERROR_FEATURE_NOT_PRESENT
);
1823 device
= vk_zalloc2(&physical_device
->instance
->alloc
, pAllocator
,
1825 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
1827 return vk_error(physical_device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1829 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1830 device
->instance
= physical_device
->instance
;
1831 device
->physical_device
= physical_device
;
1833 device
->ws
= physical_device
->ws
;
1835 device
->alloc
= *pAllocator
;
1837 device
->alloc
= physical_device
->instance
->alloc
;
1839 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
1840 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
1841 int index
= radv_get_device_extension_index(ext_name
);
1842 if (index
< 0 || !physical_device
->supported_extensions
.extensions
[index
]) {
1843 vk_free(&device
->alloc
, device
);
1844 return vk_error(physical_device
->instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
1847 device
->enabled_extensions
.extensions
[index
] = true;
1850 keep_shader_info
= device
->enabled_extensions
.AMD_shader_info
;
1852 /* With update after bind we can't attach bo's to the command buffer
1853 * from the descriptor set anymore, so we have to use a global BO list.
1855 device
->use_global_bo_list
=
1856 (device
->instance
->perftest_flags
& RADV_PERFTEST_BO_LIST
) ||
1857 device
->enabled_extensions
.EXT_descriptor_indexing
||
1858 device
->enabled_extensions
.EXT_buffer_device_address
;
1860 mtx_init(&device
->shader_slab_mutex
, mtx_plain
);
1861 list_inithead(&device
->shader_slabs
);
1863 radv_bo_list_init(&device
->bo_list
);
1865 for (unsigned i
= 0; i
< pCreateInfo
->queueCreateInfoCount
; i
++) {
1866 const VkDeviceQueueCreateInfo
*queue_create
= &pCreateInfo
->pQueueCreateInfos
[i
];
1867 uint32_t qfi
= queue_create
->queueFamilyIndex
;
1868 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
=
1869 vk_find_struct_const(queue_create
->pNext
, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT
);
1871 assert(!global_priority
|| device
->physical_device
->rad_info
.has_ctx_priority
);
1873 device
->queues
[qfi
] = vk_alloc(&device
->alloc
,
1874 queue_create
->queueCount
* sizeof(struct radv_queue
), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
1875 if (!device
->queues
[qfi
]) {
1876 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
1880 memset(device
->queues
[qfi
], 0, queue_create
->queueCount
* sizeof(struct radv_queue
));
1882 device
->queue_count
[qfi
] = queue_create
->queueCount
;
1884 for (unsigned q
= 0; q
< queue_create
->queueCount
; q
++) {
1885 result
= radv_queue_init(device
, &device
->queues
[qfi
][q
],
1886 qfi
, q
, queue_create
->flags
,
1888 if (result
!= VK_SUCCESS
)
1893 device
->pbb_allowed
= device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
1894 !(device
->instance
->debug_flags
& RADV_DEBUG_NOBINNING
);
1896 /* Disabled and not implemented for now. */
1897 device
->dfsm_allowed
= device
->pbb_allowed
&&
1898 (device
->physical_device
->rad_info
.family
== CHIP_RAVEN
||
1899 device
->physical_device
->rad_info
.family
== CHIP_RAVEN2
);
1902 device
->always_use_syncobj
= device
->physical_device
->rad_info
.has_syncobj_wait_for_submit
;
1905 /* The maximum number of scratch waves. Scratch space isn't divided
1906 * evenly between CUs. The number is only a function of the number of CUs.
1907 * We can decrease the constant to decrease the scratch buffer size.
1909 * sctx->scratch_waves must be >= the maximum possible size of
1910 * 1 threadgroup, so that the hw doesn't hang from being unable
1913 * The recommended value is 4 per CU at most. Higher numbers don't
1914 * bring much benefit, but they still occupy chip resources (think
1915 * async compute). I've seen ~2% performance difference between 4 and 32.
1917 uint32_t max_threads_per_block
= 2048;
1918 device
->scratch_waves
= MAX2(32 * physical_device
->rad_info
.num_good_compute_units
,
1919 max_threads_per_block
/ 64);
1921 device
->dispatch_initiator
= S_00B800_COMPUTE_SHADER_EN(1);
1923 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
1924 /* If the KMD allows it (there is a KMD hw register for it),
1925 * allow launching waves out-of-order.
1927 device
->dispatch_initiator
|= S_00B800_ORDER_MODE(1);
1930 radv_device_init_gs_info(device
);
1932 device
->tess_offchip_block_dw_size
=
1933 device
->physical_device
->rad_info
.family
== CHIP_HAWAII
? 4096 : 8192;
1934 device
->has_distributed_tess
=
1935 device
->physical_device
->rad_info
.chip_class
>= GFX8
&&
1936 device
->physical_device
->rad_info
.max_se
>= 2;
1938 if (getenv("RADV_TRACE_FILE")) {
1939 const char *filename
= getenv("RADV_TRACE_FILE");
1941 keep_shader_info
= true;
1943 if (!radv_init_trace(device
))
1946 fprintf(stderr
, "*****************************************************************************\n");
1947 fprintf(stderr
, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1948 fprintf(stderr
, "*****************************************************************************\n");
1950 fprintf(stderr
, "Trace file will be dumped to %s\n", filename
);
1951 radv_dump_enabled_options(device
, stderr
);
1954 device
->keep_shader_info
= keep_shader_info
;
1956 result
= radv_device_init_meta(device
);
1957 if (result
!= VK_SUCCESS
)
1960 radv_device_init_msaa(device
);
1962 for (int family
= 0; family
< RADV_MAX_QUEUE_FAMILIES
; ++family
) {
1963 device
->empty_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
1965 case RADV_QUEUE_GENERAL
:
1966 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
1967 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_LOAD_ENABLE(1));
1968 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1970 case RADV_QUEUE_COMPUTE
:
1971 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_NOP
, 0, 0));
1972 radeon_emit(device
->empty_cs
[family
], 0);
1975 device
->ws
->cs_finalize(device
->empty_cs
[family
]);
1978 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
1979 cik_create_gfx_config(device
);
1981 VkPipelineCacheCreateInfo ci
;
1982 ci
.sType
= VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
;
1985 ci
.pInitialData
= NULL
;
1986 ci
.initialDataSize
= 0;
1988 result
= radv_CreatePipelineCache(radv_device_to_handle(device
),
1990 if (result
!= VK_SUCCESS
)
1993 device
->mem_cache
= radv_pipeline_cache_from_handle(pc
);
1995 device
->force_aniso
=
1996 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
1997 if (device
->force_aniso
>= 0) {
1998 fprintf(stderr
, "radv: Forcing anisotropy filter to %ix\n",
1999 1 << util_logbase2(device
->force_aniso
));
2002 *pDevice
= radv_device_to_handle(device
);
2006 radv_device_finish_meta(device
);
2008 radv_bo_list_finish(&device
->bo_list
);
2010 if (device
->trace_bo
)
2011 device
->ws
->buffer_destroy(device
->trace_bo
);
2013 if (device
->gfx_init
)
2014 device
->ws
->buffer_destroy(device
->gfx_init
);
2016 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
2017 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
2018 radv_queue_finish(&device
->queues
[i
][q
]);
2019 if (device
->queue_count
[i
])
2020 vk_free(&device
->alloc
, device
->queues
[i
]);
2023 vk_free(&device
->alloc
, device
);
2027 void radv_DestroyDevice(
2029 const VkAllocationCallbacks
* pAllocator
)
2031 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2036 if (device
->trace_bo
)
2037 device
->ws
->buffer_destroy(device
->trace_bo
);
2039 if (device
->gfx_init
)
2040 device
->ws
->buffer_destroy(device
->gfx_init
);
2042 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
2043 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
2044 radv_queue_finish(&device
->queues
[i
][q
]);
2045 if (device
->queue_count
[i
])
2046 vk_free(&device
->alloc
, device
->queues
[i
]);
2047 if (device
->empty_cs
[i
])
2048 device
->ws
->cs_destroy(device
->empty_cs
[i
]);
2050 radv_device_finish_meta(device
);
2052 VkPipelineCache pc
= radv_pipeline_cache_to_handle(device
->mem_cache
);
2053 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
2055 radv_destroy_shader_slabs(device
);
2057 radv_bo_list_finish(&device
->bo_list
);
2058 vk_free(&device
->alloc
, device
);
2061 VkResult
radv_EnumerateInstanceLayerProperties(
2062 uint32_t* pPropertyCount
,
2063 VkLayerProperties
* pProperties
)
2065 if (pProperties
== NULL
) {
2066 *pPropertyCount
= 0;
2070 /* None supported at this time */
2071 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
2074 VkResult
radv_EnumerateDeviceLayerProperties(
2075 VkPhysicalDevice physicalDevice
,
2076 uint32_t* pPropertyCount
,
2077 VkLayerProperties
* pProperties
)
2079 if (pProperties
== NULL
) {
2080 *pPropertyCount
= 0;
2084 /* None supported at this time */
2085 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
2088 void radv_GetDeviceQueue2(
2090 const VkDeviceQueueInfo2
* pQueueInfo
,
2093 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2094 struct radv_queue
*queue
;
2096 queue
= &device
->queues
[pQueueInfo
->queueFamilyIndex
][pQueueInfo
->queueIndex
];
2097 if (pQueueInfo
->flags
!= queue
->flags
) {
2098 /* From the Vulkan 1.1.70 spec:
2100 * "The queue returned by vkGetDeviceQueue2 must have the same
2101 * flags value from this structure as that used at device
2102 * creation time in a VkDeviceQueueCreateInfo instance. If no
2103 * matching flags were specified at device creation time then
2104 * pQueue will return VK_NULL_HANDLE."
2106 *pQueue
= VK_NULL_HANDLE
;
2110 *pQueue
= radv_queue_to_handle(queue
);
2113 void radv_GetDeviceQueue(
2115 uint32_t queueFamilyIndex
,
2116 uint32_t queueIndex
,
2119 const VkDeviceQueueInfo2 info
= (VkDeviceQueueInfo2
) {
2120 .sType
= VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2
,
2121 .queueFamilyIndex
= queueFamilyIndex
,
2122 .queueIndex
= queueIndex
2125 radv_GetDeviceQueue2(_device
, &info
, pQueue
);
2129 fill_geom_tess_rings(struct radv_queue
*queue
,
2131 bool add_sample_positions
,
2132 uint32_t esgs_ring_size
,
2133 struct radeon_winsys_bo
*esgs_ring_bo
,
2134 uint32_t gsvs_ring_size
,
2135 struct radeon_winsys_bo
*gsvs_ring_bo
,
2136 uint32_t tess_factor_ring_size
,
2137 uint32_t tess_offchip_ring_offset
,
2138 uint32_t tess_offchip_ring_size
,
2139 struct radeon_winsys_bo
*tess_rings_bo
)
2141 uint32_t *desc
= &map
[4];
2144 uint64_t esgs_va
= radv_buffer_get_va(esgs_ring_bo
);
2146 /* stride 0, num records - size, add tid, swizzle, elsize4,
2149 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32) |
2150 S_008F04_STRIDE(0) |
2151 S_008F04_SWIZZLE_ENABLE(true);
2152 desc
[2] = esgs_ring_size
;
2153 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2154 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2155 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2156 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2157 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2158 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2159 S_008F0C_ELEMENT_SIZE(1) |
2160 S_008F0C_INDEX_STRIDE(3) |
2161 S_008F0C_ADD_TID_ENABLE(true);
2163 /* GS entry for ES->GS ring */
2164 /* stride 0, num records - size, elsize0,
2167 desc
[5] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32)|
2168 S_008F04_STRIDE(0) |
2169 S_008F04_SWIZZLE_ENABLE(false);
2170 desc
[6] = esgs_ring_size
;
2171 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2172 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2173 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2174 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2175 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2176 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2177 S_008F0C_ELEMENT_SIZE(0) |
2178 S_008F0C_INDEX_STRIDE(0) |
2179 S_008F0C_ADD_TID_ENABLE(false);
2185 uint64_t gsvs_va
= radv_buffer_get_va(gsvs_ring_bo
);
2187 /* VS entry for GS->VS ring */
2188 /* stride 0, num records - size, elsize0,
2191 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32)|
2192 S_008F04_STRIDE(0) |
2193 S_008F04_SWIZZLE_ENABLE(false);
2194 desc
[2] = gsvs_ring_size
;
2195 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2196 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2197 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2198 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2199 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2200 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2201 S_008F0C_ELEMENT_SIZE(0) |
2202 S_008F0C_INDEX_STRIDE(0) |
2203 S_008F0C_ADD_TID_ENABLE(false);
2205 /* stride gsvs_itemsize, num records 64
2206 elsize 4, index stride 16 */
2207 /* shader will patch stride and desc[2] */
2209 desc
[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32)|
2210 S_008F04_STRIDE(0) |
2211 S_008F04_SWIZZLE_ENABLE(true);
2213 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2214 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2215 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2216 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2217 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2218 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2219 S_008F0C_ELEMENT_SIZE(1) |
2220 S_008F0C_INDEX_STRIDE(1) |
2221 S_008F0C_ADD_TID_ENABLE(true);
2226 if (tess_rings_bo
) {
2227 uint64_t tess_va
= radv_buffer_get_va(tess_rings_bo
);
2228 uint64_t tess_offchip_va
= tess_va
+ tess_offchip_ring_offset
;
2231 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_va
>> 32) |
2232 S_008F04_STRIDE(0) |
2233 S_008F04_SWIZZLE_ENABLE(false);
2234 desc
[2] = tess_factor_ring_size
;
2235 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2236 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2237 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2238 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2239 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2240 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2241 S_008F0C_ELEMENT_SIZE(0) |
2242 S_008F0C_INDEX_STRIDE(0) |
2243 S_008F0C_ADD_TID_ENABLE(false);
2245 desc
[4] = tess_offchip_va
;
2246 desc
[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va
>> 32) |
2247 S_008F04_STRIDE(0) |
2248 S_008F04_SWIZZLE_ENABLE(false);
2249 desc
[6] = tess_offchip_ring_size
;
2250 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2251 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2252 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2253 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2254 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2255 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2256 S_008F0C_ELEMENT_SIZE(0) |
2257 S_008F0C_INDEX_STRIDE(0) |
2258 S_008F0C_ADD_TID_ENABLE(false);
2263 if (add_sample_positions
) {
2264 /* add sample positions after all rings */
2265 memcpy(desc
, queue
->device
->sample_locations_1x
, 8);
2267 memcpy(desc
, queue
->device
->sample_locations_2x
, 16);
2269 memcpy(desc
, queue
->device
->sample_locations_4x
, 32);
2271 memcpy(desc
, queue
->device
->sample_locations_8x
, 64);
2276 radv_get_hs_offchip_param(struct radv_device
*device
, uint32_t *max_offchip_buffers_p
)
2278 bool double_offchip_buffers
= device
->physical_device
->rad_info
.chip_class
>= GFX7
&&
2279 device
->physical_device
->rad_info
.family
!= CHIP_CARRIZO
&&
2280 device
->physical_device
->rad_info
.family
!= CHIP_STONEY
;
2281 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
2282 unsigned max_offchip_buffers
;
2283 unsigned offchip_granularity
;
2284 unsigned hs_offchip_param
;
2288 * This must be one less than the maximum number due to a hw limitation.
2289 * Various hardware bugs need thGFX7
2292 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2293 * Gfx7 should limit max_offchip_buffers to 508
2294 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2296 * Follow AMDVLK here.
2298 if (device
->physical_device
->rad_info
.family
== CHIP_VEGA10
||
2299 device
->physical_device
->rad_info
.chip_class
== GFX7
||
2300 device
->physical_device
->rad_info
.chip_class
== GFX6
)
2301 --max_offchip_buffers_per_se
;
2303 max_offchip_buffers
= max_offchip_buffers_per_se
*
2304 device
->physical_device
->rad_info
.max_se
;
2306 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2307 * around by setting 4K granularity.
2309 if (device
->tess_offchip_block_dw_size
== 4096) {
2310 assert(device
->physical_device
->rad_info
.family
== CHIP_HAWAII
);
2311 offchip_granularity
= V_03093C_X_4K_DWORDS
;
2313 assert(device
->tess_offchip_block_dw_size
== 8192);
2314 offchip_granularity
= V_03093C_X_8K_DWORDS
;
2317 switch (device
->physical_device
->rad_info
.chip_class
) {
2319 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
2325 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
2329 *max_offchip_buffers_p
= max_offchip_buffers
;
2330 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2331 if (device
->physical_device
->rad_info
.chip_class
>= GFX8
)
2332 --max_offchip_buffers
;
2334 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
2335 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
2338 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
2340 return hs_offchip_param
;
2344 radv_emit_gs_ring_sizes(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
2345 struct radeon_winsys_bo
*esgs_ring_bo
,
2346 uint32_t esgs_ring_size
,
2347 struct radeon_winsys_bo
*gsvs_ring_bo
,
2348 uint32_t gsvs_ring_size
)
2350 if (!esgs_ring_bo
&& !gsvs_ring_bo
)
2354 radv_cs_add_buffer(queue
->device
->ws
, cs
, esgs_ring_bo
);
2357 radv_cs_add_buffer(queue
->device
->ws
, cs
, gsvs_ring_bo
);
2359 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2360 radeon_set_uconfig_reg_seq(cs
, R_030900_VGT_ESGS_RING_SIZE
, 2);
2361 radeon_emit(cs
, esgs_ring_size
>> 8);
2362 radeon_emit(cs
, gsvs_ring_size
>> 8);
2364 radeon_set_config_reg_seq(cs
, R_0088C8_VGT_ESGS_RING_SIZE
, 2);
2365 radeon_emit(cs
, esgs_ring_size
>> 8);
2366 radeon_emit(cs
, gsvs_ring_size
>> 8);
2371 radv_emit_tess_factor_ring(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
2372 unsigned hs_offchip_param
, unsigned tf_ring_size
,
2373 struct radeon_winsys_bo
*tess_rings_bo
)
2380 tf_va
= radv_buffer_get_va(tess_rings_bo
);
2382 radv_cs_add_buffer(queue
->device
->ws
, cs
, tess_rings_bo
);
2384 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2385 radeon_set_uconfig_reg(cs
, R_030938_VGT_TF_RING_SIZE
,
2386 S_030938_SIZE(tf_ring_size
/ 4));
2387 radeon_set_uconfig_reg(cs
, R_030940_VGT_TF_MEMORY_BASE
,
2389 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2390 radeon_set_uconfig_reg(cs
, R_030944_VGT_TF_MEMORY_BASE_HI
,
2391 S_030944_BASE_HI(tf_va
>> 40));
2393 radeon_set_uconfig_reg(cs
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
2396 radeon_set_config_reg(cs
, R_008988_VGT_TF_RING_SIZE
,
2397 S_008988_SIZE(tf_ring_size
/ 4));
2398 radeon_set_config_reg(cs
, R_0089B8_VGT_TF_MEMORY_BASE
,
2400 radeon_set_config_reg(cs
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
2406 radv_emit_compute_scratch(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
2407 struct radeon_winsys_bo
*compute_scratch_bo
)
2409 uint64_t scratch_va
;
2411 if (!compute_scratch_bo
)
2414 scratch_va
= radv_buffer_get_va(compute_scratch_bo
);
2416 radv_cs_add_buffer(queue
->device
->ws
, cs
, compute_scratch_bo
);
2418 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, 2);
2419 radeon_emit(cs
, scratch_va
);
2420 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
2421 S_008F04_SWIZZLE_ENABLE(1));
2425 radv_emit_global_shader_pointers(struct radv_queue
*queue
,
2426 struct radeon_cmdbuf
*cs
,
2427 struct radeon_winsys_bo
*descriptor_bo
)
2434 va
= radv_buffer_get_va(descriptor_bo
);
2436 radv_cs_add_buffer(queue
->device
->ws
, cs
, descriptor_bo
);
2438 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2439 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
2440 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
2441 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
2442 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
2444 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
2445 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
2449 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
2450 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
2451 R_00B230_SPI_SHADER_USER_DATA_GS_0
,
2452 R_00B330_SPI_SHADER_USER_DATA_ES_0
,
2453 R_00B430_SPI_SHADER_USER_DATA_HS_0
,
2454 R_00B530_SPI_SHADER_USER_DATA_LS_0
};
2456 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
2457 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
2464 radv_init_graphics_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
2466 struct radv_device
*device
= queue
->device
;
2468 if (device
->gfx_init
) {
2469 uint64_t va
= radv_buffer_get_va(device
->gfx_init
);
2471 radeon_emit(cs
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
2472 radeon_emit(cs
, va
);
2473 radeon_emit(cs
, va
>> 32);
2474 radeon_emit(cs
, device
->gfx_init_size_dw
& 0xffff);
2476 radv_cs_add_buffer(device
->ws
, cs
, device
->gfx_init
);
2478 struct radv_physical_device
*physical_device
= device
->physical_device
;
2479 si_emit_graphics(physical_device
, cs
);
2484 radv_init_compute_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
2486 struct radv_physical_device
*physical_device
= queue
->device
->physical_device
;
2487 si_emit_compute(physical_device
, cs
);
2491 radv_get_preamble_cs(struct radv_queue
*queue
,
2492 uint32_t scratch_size
,
2493 uint32_t compute_scratch_size
,
2494 uint32_t esgs_ring_size
,
2495 uint32_t gsvs_ring_size
,
2496 bool needs_tess_rings
,
2497 bool needs_sample_positions
,
2498 struct radeon_cmdbuf
**initial_full_flush_preamble_cs
,
2499 struct radeon_cmdbuf
**initial_preamble_cs
,
2500 struct radeon_cmdbuf
**continue_preamble_cs
)
2502 struct radeon_winsys_bo
*scratch_bo
= NULL
;
2503 struct radeon_winsys_bo
*descriptor_bo
= NULL
;
2504 struct radeon_winsys_bo
*compute_scratch_bo
= NULL
;
2505 struct radeon_winsys_bo
*esgs_ring_bo
= NULL
;
2506 struct radeon_winsys_bo
*gsvs_ring_bo
= NULL
;
2507 struct radeon_winsys_bo
*tess_rings_bo
= NULL
;
2508 struct radeon_cmdbuf
*dest_cs
[3] = {0};
2509 bool add_tess_rings
= false, add_sample_positions
= false;
2510 unsigned tess_factor_ring_size
= 0, tess_offchip_ring_size
= 0;
2511 unsigned max_offchip_buffers
;
2512 unsigned hs_offchip_param
= 0;
2513 unsigned tess_offchip_ring_offset
;
2514 uint32_t ring_bo_flags
= RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
;
2515 if (!queue
->has_tess_rings
) {
2516 if (needs_tess_rings
)
2517 add_tess_rings
= true;
2519 if (!queue
->has_sample_positions
) {
2520 if (needs_sample_positions
)
2521 add_sample_positions
= true;
2523 tess_factor_ring_size
= 32768 * queue
->device
->physical_device
->rad_info
.max_se
;
2524 hs_offchip_param
= radv_get_hs_offchip_param(queue
->device
,
2525 &max_offchip_buffers
);
2526 tess_offchip_ring_offset
= align(tess_factor_ring_size
, 64 * 1024);
2527 tess_offchip_ring_size
= max_offchip_buffers
*
2528 queue
->device
->tess_offchip_block_dw_size
* 4;
2530 if (scratch_size
<= queue
->scratch_size
&&
2531 compute_scratch_size
<= queue
->compute_scratch_size
&&
2532 esgs_ring_size
<= queue
->esgs_ring_size
&&
2533 gsvs_ring_size
<= queue
->gsvs_ring_size
&&
2534 !add_tess_rings
&& !add_sample_positions
&&
2535 queue
->initial_preamble_cs
) {
2536 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
2537 *initial_preamble_cs
= queue
->initial_preamble_cs
;
2538 *continue_preamble_cs
= queue
->continue_preamble_cs
;
2539 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
2540 *continue_preamble_cs
= NULL
;
2544 if (scratch_size
> queue
->scratch_size
) {
2545 scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2550 RADV_BO_PRIORITY_SCRATCH
);
2554 scratch_bo
= queue
->scratch_bo
;
2556 if (compute_scratch_size
> queue
->compute_scratch_size
) {
2557 compute_scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2558 compute_scratch_size
,
2562 RADV_BO_PRIORITY_SCRATCH
);
2563 if (!compute_scratch_bo
)
2567 compute_scratch_bo
= queue
->compute_scratch_bo
;
2569 if (esgs_ring_size
> queue
->esgs_ring_size
) {
2570 esgs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2575 RADV_BO_PRIORITY_SCRATCH
);
2579 esgs_ring_bo
= queue
->esgs_ring_bo
;
2580 esgs_ring_size
= queue
->esgs_ring_size
;
2583 if (gsvs_ring_size
> queue
->gsvs_ring_size
) {
2584 gsvs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2589 RADV_BO_PRIORITY_SCRATCH
);
2593 gsvs_ring_bo
= queue
->gsvs_ring_bo
;
2594 gsvs_ring_size
= queue
->gsvs_ring_size
;
2597 if (add_tess_rings
) {
2598 tess_rings_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2599 tess_offchip_ring_offset
+ tess_offchip_ring_size
,
2603 RADV_BO_PRIORITY_SCRATCH
);
2607 tess_rings_bo
= queue
->tess_rings_bo
;
2610 if (scratch_bo
!= queue
->scratch_bo
||
2611 esgs_ring_bo
!= queue
->esgs_ring_bo
||
2612 gsvs_ring_bo
!= queue
->gsvs_ring_bo
||
2613 tess_rings_bo
!= queue
->tess_rings_bo
||
2614 add_sample_positions
) {
2616 if (gsvs_ring_bo
|| esgs_ring_bo
||
2617 tess_rings_bo
|| add_sample_positions
) {
2618 size
= 112; /* 2 dword + 2 padding + 4 dword * 6 */
2619 if (add_sample_positions
)
2620 size
+= 128; /* 64+32+16+8 = 120 bytes */
2622 else if (scratch_bo
)
2623 size
= 8; /* 2 dword */
2625 descriptor_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2629 RADEON_FLAG_CPU_ACCESS
|
2630 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
2631 RADEON_FLAG_READ_ONLY
,
2632 RADV_BO_PRIORITY_DESCRIPTOR
);
2636 descriptor_bo
= queue
->descriptor_bo
;
2638 if (descriptor_bo
!= queue
->descriptor_bo
) {
2639 uint32_t *map
= (uint32_t*)queue
->device
->ws
->buffer_map(descriptor_bo
);
2642 uint64_t scratch_va
= radv_buffer_get_va(scratch_bo
);
2643 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
2644 S_008F04_SWIZZLE_ENABLE(1);
2645 map
[0] = scratch_va
;
2649 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
|| add_sample_positions
)
2650 fill_geom_tess_rings(queue
, map
, add_sample_positions
,
2651 esgs_ring_size
, esgs_ring_bo
,
2652 gsvs_ring_size
, gsvs_ring_bo
,
2653 tess_factor_ring_size
,
2654 tess_offchip_ring_offset
,
2655 tess_offchip_ring_size
,
2658 queue
->device
->ws
->buffer_unmap(descriptor_bo
);
2661 for(int i
= 0; i
< 3; ++i
) {
2662 struct radeon_cmdbuf
*cs
= NULL
;
2663 cs
= queue
->device
->ws
->cs_create(queue
->device
->ws
,
2664 queue
->queue_family_index
? RING_COMPUTE
: RING_GFX
);
2671 radv_cs_add_buffer(queue
->device
->ws
, cs
, scratch_bo
);
2673 /* Emit initial configuration. */
2674 switch (queue
->queue_family_index
) {
2675 case RADV_QUEUE_GENERAL
:
2676 radv_init_graphics_state(cs
, queue
);
2678 case RADV_QUEUE_COMPUTE
:
2679 radv_init_compute_state(cs
, queue
);
2681 case RADV_QUEUE_TRANSFER
:
2685 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
) {
2686 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2687 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2688 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2689 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
2692 radv_emit_gs_ring_sizes(queue
, cs
, esgs_ring_bo
, esgs_ring_size
,
2693 gsvs_ring_bo
, gsvs_ring_size
);
2694 radv_emit_tess_factor_ring(queue
, cs
, hs_offchip_param
,
2695 tess_factor_ring_size
, tess_rings_bo
);
2696 radv_emit_global_shader_pointers(queue
, cs
, descriptor_bo
);
2697 radv_emit_compute_scratch(queue
, cs
, compute_scratch_bo
);
2700 si_cs_emit_cache_flush(cs
,
2701 queue
->device
->physical_device
->rad_info
.chip_class
,
2703 queue
->queue_family_index
== RING_COMPUTE
&&
2704 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
2705 (queue
->queue_family_index
== RADV_QUEUE_COMPUTE
? RADV_CMD_FLAG_CS_PARTIAL_FLUSH
: (RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
)) |
2706 RADV_CMD_FLAG_INV_ICACHE
|
2707 RADV_CMD_FLAG_INV_SCACHE
|
2708 RADV_CMD_FLAG_INV_VCACHE
|
2709 RADV_CMD_FLAG_INV_L2
|
2710 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
2711 } else if (i
== 1) {
2712 si_cs_emit_cache_flush(cs
,
2713 queue
->device
->physical_device
->rad_info
.chip_class
,
2715 queue
->queue_family_index
== RING_COMPUTE
&&
2716 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
2717 RADV_CMD_FLAG_INV_ICACHE
|
2718 RADV_CMD_FLAG_INV_SCACHE
|
2719 RADV_CMD_FLAG_INV_VCACHE
|
2720 RADV_CMD_FLAG_INV_L2
|
2721 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
2724 if (!queue
->device
->ws
->cs_finalize(cs
))
2728 if (queue
->initial_full_flush_preamble_cs
)
2729 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
2731 if (queue
->initial_preamble_cs
)
2732 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
2734 if (queue
->continue_preamble_cs
)
2735 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
2737 queue
->initial_full_flush_preamble_cs
= dest_cs
[0];
2738 queue
->initial_preamble_cs
= dest_cs
[1];
2739 queue
->continue_preamble_cs
= dest_cs
[2];
2741 if (scratch_bo
!= queue
->scratch_bo
) {
2742 if (queue
->scratch_bo
)
2743 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
2744 queue
->scratch_bo
= scratch_bo
;
2745 queue
->scratch_size
= scratch_size
;
2748 if (compute_scratch_bo
!= queue
->compute_scratch_bo
) {
2749 if (queue
->compute_scratch_bo
)
2750 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
2751 queue
->compute_scratch_bo
= compute_scratch_bo
;
2752 queue
->compute_scratch_size
= compute_scratch_size
;
2755 if (esgs_ring_bo
!= queue
->esgs_ring_bo
) {
2756 if (queue
->esgs_ring_bo
)
2757 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
2758 queue
->esgs_ring_bo
= esgs_ring_bo
;
2759 queue
->esgs_ring_size
= esgs_ring_size
;
2762 if (gsvs_ring_bo
!= queue
->gsvs_ring_bo
) {
2763 if (queue
->gsvs_ring_bo
)
2764 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
2765 queue
->gsvs_ring_bo
= gsvs_ring_bo
;
2766 queue
->gsvs_ring_size
= gsvs_ring_size
;
2769 if (tess_rings_bo
!= queue
->tess_rings_bo
) {
2770 queue
->tess_rings_bo
= tess_rings_bo
;
2771 queue
->has_tess_rings
= true;
2774 if (descriptor_bo
!= queue
->descriptor_bo
) {
2775 if (queue
->descriptor_bo
)
2776 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
2778 queue
->descriptor_bo
= descriptor_bo
;
2781 if (add_sample_positions
)
2782 queue
->has_sample_positions
= true;
2784 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
2785 *initial_preamble_cs
= queue
->initial_preamble_cs
;
2786 *continue_preamble_cs
= queue
->continue_preamble_cs
;
2787 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
2788 *continue_preamble_cs
= NULL
;
2791 for (int i
= 0; i
< ARRAY_SIZE(dest_cs
); ++i
)
2793 queue
->device
->ws
->cs_destroy(dest_cs
[i
]);
2794 if (descriptor_bo
&& descriptor_bo
!= queue
->descriptor_bo
)
2795 queue
->device
->ws
->buffer_destroy(descriptor_bo
);
2796 if (scratch_bo
&& scratch_bo
!= queue
->scratch_bo
)
2797 queue
->device
->ws
->buffer_destroy(scratch_bo
);
2798 if (compute_scratch_bo
&& compute_scratch_bo
!= queue
->compute_scratch_bo
)
2799 queue
->device
->ws
->buffer_destroy(compute_scratch_bo
);
2800 if (esgs_ring_bo
&& esgs_ring_bo
!= queue
->esgs_ring_bo
)
2801 queue
->device
->ws
->buffer_destroy(esgs_ring_bo
);
2802 if (gsvs_ring_bo
&& gsvs_ring_bo
!= queue
->gsvs_ring_bo
)
2803 queue
->device
->ws
->buffer_destroy(gsvs_ring_bo
);
2804 if (tess_rings_bo
&& tess_rings_bo
!= queue
->tess_rings_bo
)
2805 queue
->device
->ws
->buffer_destroy(tess_rings_bo
);
2806 return vk_error(queue
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2809 static VkResult
radv_alloc_sem_counts(struct radv_instance
*instance
,
2810 struct radv_winsys_sem_counts
*counts
,
2812 const VkSemaphore
*sems
,
2816 int syncobj_idx
= 0, sem_idx
= 0;
2818 if (num_sems
== 0 && _fence
== VK_NULL_HANDLE
)
2821 for (uint32_t i
= 0; i
< num_sems
; i
++) {
2822 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
2824 if (sem
->temp_syncobj
|| sem
->syncobj
)
2825 counts
->syncobj_count
++;
2827 counts
->sem_count
++;
2830 if (_fence
!= VK_NULL_HANDLE
) {
2831 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2832 if (fence
->temp_syncobj
|| fence
->syncobj
)
2833 counts
->syncobj_count
++;
2836 if (counts
->syncobj_count
) {
2837 counts
->syncobj
= (uint32_t *)malloc(sizeof(uint32_t) * counts
->syncobj_count
);
2838 if (!counts
->syncobj
)
2839 return vk_error(instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2842 if (counts
->sem_count
) {
2843 counts
->sem
= (struct radeon_winsys_sem
**)malloc(sizeof(struct radeon_winsys_sem
*) * counts
->sem_count
);
2845 free(counts
->syncobj
);
2846 return vk_error(instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2850 for (uint32_t i
= 0; i
< num_sems
; i
++) {
2851 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
2853 if (sem
->temp_syncobj
) {
2854 counts
->syncobj
[syncobj_idx
++] = sem
->temp_syncobj
;
2856 else if (sem
->syncobj
)
2857 counts
->syncobj
[syncobj_idx
++] = sem
->syncobj
;
2860 counts
->sem
[sem_idx
++] = sem
->sem
;
2864 if (_fence
!= VK_NULL_HANDLE
) {
2865 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2866 if (fence
->temp_syncobj
)
2867 counts
->syncobj
[syncobj_idx
++] = fence
->temp_syncobj
;
2868 else if (fence
->syncobj
)
2869 counts
->syncobj
[syncobj_idx
++] = fence
->syncobj
;
2876 radv_free_sem_info(struct radv_winsys_sem_info
*sem_info
)
2878 free(sem_info
->wait
.syncobj
);
2879 free(sem_info
->wait
.sem
);
2880 free(sem_info
->signal
.syncobj
);
2881 free(sem_info
->signal
.sem
);
2885 static void radv_free_temp_syncobjs(struct radv_device
*device
,
2887 const VkSemaphore
*sems
)
2889 for (uint32_t i
= 0; i
< num_sems
; i
++) {
2890 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
2892 if (sem
->temp_syncobj
) {
2893 device
->ws
->destroy_syncobj(device
->ws
, sem
->temp_syncobj
);
2894 sem
->temp_syncobj
= 0;
2900 radv_alloc_sem_info(struct radv_instance
*instance
,
2901 struct radv_winsys_sem_info
*sem_info
,
2903 const VkSemaphore
*wait_sems
,
2904 int num_signal_sems
,
2905 const VkSemaphore
*signal_sems
,
2909 memset(sem_info
, 0, sizeof(*sem_info
));
2911 ret
= radv_alloc_sem_counts(instance
, &sem_info
->wait
, num_wait_sems
, wait_sems
, VK_NULL_HANDLE
, true);
2914 ret
= radv_alloc_sem_counts(instance
, &sem_info
->signal
, num_signal_sems
, signal_sems
, fence
, false);
2916 radv_free_sem_info(sem_info
);
2918 /* caller can override these */
2919 sem_info
->cs_emit_wait
= true;
2920 sem_info
->cs_emit_signal
= true;
2924 /* Signals fence as soon as all the work currently put on queue is done. */
2925 static VkResult
radv_signal_fence(struct radv_queue
*queue
,
2926 struct radv_fence
*fence
)
2930 struct radv_winsys_sem_info sem_info
;
2932 result
= radv_alloc_sem_info(queue
->device
->instance
, &sem_info
, 0, NULL
, 0, NULL
,
2933 radv_fence_to_handle(fence
));
2934 if (result
!= VK_SUCCESS
)
2937 ret
= queue
->device
->ws
->cs_submit(queue
->hw_ctx
, queue
->queue_idx
,
2938 &queue
->device
->empty_cs
[queue
->queue_family_index
],
2939 1, NULL
, NULL
, &sem_info
, NULL
,
2940 false, fence
->fence
);
2941 radv_free_sem_info(&sem_info
);
2944 return vk_error(queue
->device
->instance
, VK_ERROR_DEVICE_LOST
);
2949 VkResult
radv_QueueSubmit(
2951 uint32_t submitCount
,
2952 const VkSubmitInfo
* pSubmits
,
2955 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
2956 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2957 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
2958 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
2960 uint32_t max_cs_submission
= queue
->device
->trace_bo
? 1 : RADV_MAX_IBS_PER_SUBMIT
;
2961 uint32_t scratch_size
= 0;
2962 uint32_t compute_scratch_size
= 0;
2963 uint32_t esgs_ring_size
= 0, gsvs_ring_size
= 0;
2964 struct radeon_cmdbuf
*initial_preamble_cs
= NULL
, *initial_flush_preamble_cs
= NULL
, *continue_preamble_cs
= NULL
;
2966 bool fence_emitted
= false;
2967 bool tess_rings_needed
= false;
2968 bool sample_positions_needed
= false;
2970 /* Do this first so failing to allocate scratch buffers can't result in
2971 * partially executed submissions. */
2972 for (uint32_t i
= 0; i
< submitCount
; i
++) {
2973 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
2974 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
2975 pSubmits
[i
].pCommandBuffers
[j
]);
2977 scratch_size
= MAX2(scratch_size
, cmd_buffer
->scratch_size_needed
);
2978 compute_scratch_size
= MAX2(compute_scratch_size
,
2979 cmd_buffer
->compute_scratch_size_needed
);
2980 esgs_ring_size
= MAX2(esgs_ring_size
, cmd_buffer
->esgs_ring_size_needed
);
2981 gsvs_ring_size
= MAX2(gsvs_ring_size
, cmd_buffer
->gsvs_ring_size_needed
);
2982 tess_rings_needed
|= cmd_buffer
->tess_rings_needed
;
2983 sample_positions_needed
|= cmd_buffer
->sample_positions_needed
;
2987 result
= radv_get_preamble_cs(queue
, scratch_size
, compute_scratch_size
,
2988 esgs_ring_size
, gsvs_ring_size
, tess_rings_needed
,
2989 sample_positions_needed
, &initial_flush_preamble_cs
,
2990 &initial_preamble_cs
, &continue_preamble_cs
);
2991 if (result
!= VK_SUCCESS
)
2994 for (uint32_t i
= 0; i
< submitCount
; i
++) {
2995 struct radeon_cmdbuf
**cs_array
;
2996 bool do_flush
= !i
|| pSubmits
[i
].pWaitDstStageMask
;
2997 bool can_patch
= true;
2999 struct radv_winsys_sem_info sem_info
;
3001 result
= radv_alloc_sem_info(queue
->device
->instance
,
3003 pSubmits
[i
].waitSemaphoreCount
,
3004 pSubmits
[i
].pWaitSemaphores
,
3005 pSubmits
[i
].signalSemaphoreCount
,
3006 pSubmits
[i
].pSignalSemaphores
,
3008 if (result
!= VK_SUCCESS
)
3011 if (!pSubmits
[i
].commandBufferCount
) {
3012 if (pSubmits
[i
].waitSemaphoreCount
|| pSubmits
[i
].signalSemaphoreCount
) {
3013 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
3014 &queue
->device
->empty_cs
[queue
->queue_family_index
],
3019 radv_loge("failed to submit CS %d\n", i
);
3022 fence_emitted
= true;
3024 radv_free_sem_info(&sem_info
);
3028 cs_array
= malloc(sizeof(struct radeon_cmdbuf
*) *
3029 (pSubmits
[i
].commandBufferCount
));
3031 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
3032 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
3033 pSubmits
[i
].pCommandBuffers
[j
]);
3034 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
3036 cs_array
[j
] = cmd_buffer
->cs
;
3037 if ((cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT
))
3040 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_PENDING
;
3043 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
+= advance
) {
3044 struct radeon_cmdbuf
*initial_preamble
= (do_flush
&& !j
) ? initial_flush_preamble_cs
: initial_preamble_cs
;
3045 const struct radv_winsys_bo_list
*bo_list
= NULL
;
3047 advance
= MIN2(max_cs_submission
,
3048 pSubmits
[i
].commandBufferCount
- j
);
3050 if (queue
->device
->trace_bo
)
3051 *queue
->device
->trace_id_ptr
= 0;
3053 sem_info
.cs_emit_wait
= j
== 0;
3054 sem_info
.cs_emit_signal
= j
+ advance
== pSubmits
[i
].commandBufferCount
;
3056 if (unlikely(queue
->device
->use_global_bo_list
)) {
3057 pthread_mutex_lock(&queue
->device
->bo_list
.mutex
);
3058 bo_list
= &queue
->device
->bo_list
.list
;
3061 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, cs_array
+ j
,
3062 advance
, initial_preamble
, continue_preamble_cs
,
3064 can_patch
, base_fence
);
3066 if (unlikely(queue
->device
->use_global_bo_list
))
3067 pthread_mutex_unlock(&queue
->device
->bo_list
.mutex
);
3070 radv_loge("failed to submit CS %d\n", i
);
3073 fence_emitted
= true;
3074 if (queue
->device
->trace_bo
) {
3075 radv_check_gpu_hangs(queue
, cs_array
[j
]);
3079 radv_free_temp_syncobjs(queue
->device
,
3080 pSubmits
[i
].waitSemaphoreCount
,
3081 pSubmits
[i
].pWaitSemaphores
);
3082 radv_free_sem_info(&sem_info
);
3087 if (!fence_emitted
) {
3088 result
= radv_signal_fence(queue
, fence
);
3089 if (result
!= VK_SUCCESS
)
3097 VkResult
radv_QueueWaitIdle(
3100 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
3102 queue
->device
->ws
->ctx_wait_idle(queue
->hw_ctx
,
3103 radv_queue_family_to_ring(queue
->queue_family_index
),
3108 VkResult
radv_DeviceWaitIdle(
3111 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3113 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
3114 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++) {
3115 radv_QueueWaitIdle(radv_queue_to_handle(&device
->queues
[i
][q
]));
3121 VkResult
radv_EnumerateInstanceExtensionProperties(
3122 const char* pLayerName
,
3123 uint32_t* pPropertyCount
,
3124 VkExtensionProperties
* pProperties
)
3126 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
3128 for (int i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; i
++) {
3129 if (radv_supported_instance_extensions
.extensions
[i
]) {
3130 vk_outarray_append(&out
, prop
) {
3131 *prop
= radv_instance_extensions
[i
];
3136 return vk_outarray_status(&out
);
3139 VkResult
radv_EnumerateDeviceExtensionProperties(
3140 VkPhysicalDevice physicalDevice
,
3141 const char* pLayerName
,
3142 uint32_t* pPropertyCount
,
3143 VkExtensionProperties
* pProperties
)
3145 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
3146 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
3148 for (int i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; i
++) {
3149 if (device
->supported_extensions
.extensions
[i
]) {
3150 vk_outarray_append(&out
, prop
) {
3151 *prop
= radv_device_extensions
[i
];
3156 return vk_outarray_status(&out
);
3159 PFN_vkVoidFunction
radv_GetInstanceProcAddr(
3160 VkInstance _instance
,
3163 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
3165 return radv_lookup_entrypoint_checked(pName
,
3166 instance
? instance
->apiVersion
: 0,
3167 instance
? &instance
->enabled_extensions
: NULL
,
3171 /* The loader wants us to expose a second GetInstanceProcAddr function
3172 * to work around certain LD_PRELOAD issues seen in apps.
3175 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
3176 VkInstance instance
,
3180 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
3181 VkInstance instance
,
3184 return radv_GetInstanceProcAddr(instance
, pName
);
3188 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
3189 VkInstance _instance
,
3193 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
3194 VkInstance _instance
,
3197 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
3199 return radv_lookup_physical_device_entrypoint_checked(pName
,
3200 instance
? instance
->apiVersion
: 0,
3201 instance
? &instance
->enabled_extensions
: NULL
);
3204 PFN_vkVoidFunction
radv_GetDeviceProcAddr(
3208 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3210 return radv_lookup_entrypoint_checked(pName
,
3211 device
->instance
->apiVersion
,
3212 &device
->instance
->enabled_extensions
,
3213 &device
->enabled_extensions
);
3216 bool radv_get_memory_fd(struct radv_device
*device
,
3217 struct radv_device_memory
*memory
,
3220 struct radeon_bo_metadata metadata
;
3222 if (memory
->image
) {
3223 radv_init_metadata(device
, memory
->image
, &metadata
);
3224 device
->ws
->buffer_set_metadata(memory
->bo
, &metadata
);
3227 return device
->ws
->buffer_get_fd(device
->ws
, memory
->bo
,
3231 static VkResult
radv_alloc_memory(struct radv_device
*device
,
3232 const VkMemoryAllocateInfo
* pAllocateInfo
,
3233 const VkAllocationCallbacks
* pAllocator
,
3234 VkDeviceMemory
* pMem
)
3236 struct radv_device_memory
*mem
;
3238 enum radeon_bo_domain domain
;
3240 enum radv_mem_type mem_type_index
= device
->physical_device
->mem_type_indices
[pAllocateInfo
->memoryTypeIndex
];
3242 assert(pAllocateInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO
);
3244 if (pAllocateInfo
->allocationSize
== 0) {
3245 /* Apparently, this is allowed */
3246 *pMem
= VK_NULL_HANDLE
;
3250 const VkImportMemoryFdInfoKHR
*import_info
=
3251 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_FD_INFO_KHR
);
3252 const VkMemoryDedicatedAllocateInfo
*dedicate_info
=
3253 vk_find_struct_const(pAllocateInfo
->pNext
, MEMORY_DEDICATED_ALLOCATE_INFO
);
3254 const VkExportMemoryAllocateInfo
*export_info
=
3255 vk_find_struct_const(pAllocateInfo
->pNext
, EXPORT_MEMORY_ALLOCATE_INFO
);
3256 const VkImportMemoryHostPointerInfoEXT
*host_ptr_info
=
3257 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_HOST_POINTER_INFO_EXT
);
3259 const struct wsi_memory_allocate_info
*wsi_info
=
3260 vk_find_struct_const(pAllocateInfo
->pNext
, WSI_MEMORY_ALLOCATE_INFO_MESA
);
3262 mem
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*mem
), 8,
3263 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3265 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3267 if (wsi_info
&& wsi_info
->implicit_sync
)
3268 flags
|= RADEON_FLAG_IMPLICIT_SYNC
;
3270 if (dedicate_info
) {
3271 mem
->image
= radv_image_from_handle(dedicate_info
->image
);
3272 mem
->buffer
= radv_buffer_from_handle(dedicate_info
->buffer
);
3278 float priority_float
= 0.5;
3279 const struct VkMemoryPriorityAllocateInfoEXT
*priority_ext
=
3280 vk_find_struct_const(pAllocateInfo
->pNext
,
3281 MEMORY_PRIORITY_ALLOCATE_INFO_EXT
);
3283 priority_float
= priority_ext
->priority
;
3285 unsigned priority
= MIN2(RADV_BO_PRIORITY_APPLICATION_MAX
- 1,
3286 (int)(priority_float
* RADV_BO_PRIORITY_APPLICATION_MAX
));
3288 mem
->user_ptr
= NULL
;
3291 assert(import_info
->handleType
==
3292 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
3293 import_info
->handleType
==
3294 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
3295 mem
->bo
= device
->ws
->buffer_from_fd(device
->ws
, import_info
->fd
,
3296 priority
, NULL
, NULL
);
3298 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
3301 close(import_info
->fd
);
3303 } else if (host_ptr_info
) {
3304 assert(host_ptr_info
->handleType
== VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
);
3305 assert(mem_type_index
== RADV_MEM_TYPE_GTT_CACHED
);
3306 mem
->bo
= device
->ws
->buffer_from_ptr(device
->ws
, host_ptr_info
->pHostPointer
,
3307 pAllocateInfo
->allocationSize
,
3310 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
3313 mem
->user_ptr
= host_ptr_info
->pHostPointer
;
3316 uint64_t alloc_size
= align_u64(pAllocateInfo
->allocationSize
, 4096);
3317 if (mem_type_index
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
||
3318 mem_type_index
== RADV_MEM_TYPE_GTT_CACHED
)
3319 domain
= RADEON_DOMAIN_GTT
;
3321 domain
= RADEON_DOMAIN_VRAM
;
3323 if (mem_type_index
== RADV_MEM_TYPE_VRAM
)
3324 flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
3326 flags
|= RADEON_FLAG_CPU_ACCESS
;
3328 if (mem_type_index
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
)
3329 flags
|= RADEON_FLAG_GTT_WC
;
3331 if (!dedicate_info
&& !import_info
&& (!export_info
|| !export_info
->handleTypes
)) {
3332 flags
|= RADEON_FLAG_NO_INTERPROCESS_SHARING
;
3333 if (device
->use_global_bo_list
) {
3334 flags
|= RADEON_FLAG_PREFER_LOCAL_BO
;
3338 mem
->bo
= device
->ws
->buffer_create(device
->ws
, alloc_size
, device
->physical_device
->rad_info
.max_alignment
,
3339 domain
, flags
, priority
);
3342 result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
3345 mem
->type_index
= mem_type_index
;
3348 result
= radv_bo_list_add(device
, mem
->bo
);
3349 if (result
!= VK_SUCCESS
)
3352 *pMem
= radv_device_memory_to_handle(mem
);
3357 device
->ws
->buffer_destroy(mem
->bo
);
3359 vk_free2(&device
->alloc
, pAllocator
, mem
);
3364 VkResult
radv_AllocateMemory(
3366 const VkMemoryAllocateInfo
* pAllocateInfo
,
3367 const VkAllocationCallbacks
* pAllocator
,
3368 VkDeviceMemory
* pMem
)
3370 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3371 return radv_alloc_memory(device
, pAllocateInfo
, pAllocator
, pMem
);
3374 void radv_FreeMemory(
3376 VkDeviceMemory _mem
,
3377 const VkAllocationCallbacks
* pAllocator
)
3379 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3380 RADV_FROM_HANDLE(radv_device_memory
, mem
, _mem
);
3385 radv_bo_list_remove(device
, mem
->bo
);
3386 device
->ws
->buffer_destroy(mem
->bo
);
3389 vk_free2(&device
->alloc
, pAllocator
, mem
);
3392 VkResult
radv_MapMemory(
3394 VkDeviceMemory _memory
,
3395 VkDeviceSize offset
,
3397 VkMemoryMapFlags flags
,
3400 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3401 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
3409 *ppData
= mem
->user_ptr
;
3411 *ppData
= device
->ws
->buffer_map(mem
->bo
);
3418 return vk_error(device
->instance
, VK_ERROR_MEMORY_MAP_FAILED
);
3421 void radv_UnmapMemory(
3423 VkDeviceMemory _memory
)
3425 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3426 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
3431 if (mem
->user_ptr
== NULL
)
3432 device
->ws
->buffer_unmap(mem
->bo
);
3435 VkResult
radv_FlushMappedMemoryRanges(
3437 uint32_t memoryRangeCount
,
3438 const VkMappedMemoryRange
* pMemoryRanges
)
3443 VkResult
radv_InvalidateMappedMemoryRanges(
3445 uint32_t memoryRangeCount
,
3446 const VkMappedMemoryRange
* pMemoryRanges
)
3451 void radv_GetBufferMemoryRequirements(
3454 VkMemoryRequirements
* pMemoryRequirements
)
3456 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3457 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3459 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
3461 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
3462 pMemoryRequirements
->alignment
= 4096;
3464 pMemoryRequirements
->alignment
= 16;
3466 pMemoryRequirements
->size
= align64(buffer
->size
, pMemoryRequirements
->alignment
);
3469 void radv_GetBufferMemoryRequirements2(
3471 const VkBufferMemoryRequirementsInfo2
*pInfo
,
3472 VkMemoryRequirements2
*pMemoryRequirements
)
3474 radv_GetBufferMemoryRequirements(device
, pInfo
->buffer
,
3475 &pMemoryRequirements
->memoryRequirements
);
3476 RADV_FROM_HANDLE(radv_buffer
, buffer
, pInfo
->buffer
);
3477 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
3478 switch (ext
->sType
) {
3479 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
3480 VkMemoryDedicatedRequirements
*req
=
3481 (VkMemoryDedicatedRequirements
*) ext
;
3482 req
->requiresDedicatedAllocation
= buffer
->shareable
;
3483 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
3492 void radv_GetImageMemoryRequirements(
3495 VkMemoryRequirements
* pMemoryRequirements
)
3497 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3498 RADV_FROM_HANDLE(radv_image
, image
, _image
);
3500 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
3502 pMemoryRequirements
->size
= image
->size
;
3503 pMemoryRequirements
->alignment
= image
->alignment
;
3506 void radv_GetImageMemoryRequirements2(
3508 const VkImageMemoryRequirementsInfo2
*pInfo
,
3509 VkMemoryRequirements2
*pMemoryRequirements
)
3511 radv_GetImageMemoryRequirements(device
, pInfo
->image
,
3512 &pMemoryRequirements
->memoryRequirements
);
3514 RADV_FROM_HANDLE(radv_image
, image
, pInfo
->image
);
3516 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
3517 switch (ext
->sType
) {
3518 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
3519 VkMemoryDedicatedRequirements
*req
=
3520 (VkMemoryDedicatedRequirements
*) ext
;
3521 req
->requiresDedicatedAllocation
= image
->shareable
;
3522 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
3531 void radv_GetImageSparseMemoryRequirements(
3534 uint32_t* pSparseMemoryRequirementCount
,
3535 VkSparseImageMemoryRequirements
* pSparseMemoryRequirements
)
3540 void radv_GetImageSparseMemoryRequirements2(
3542 const VkImageSparseMemoryRequirementsInfo2
*pInfo
,
3543 uint32_t* pSparseMemoryRequirementCount
,
3544 VkSparseImageMemoryRequirements2
*pSparseMemoryRequirements
)
3549 void radv_GetDeviceMemoryCommitment(
3551 VkDeviceMemory memory
,
3552 VkDeviceSize
* pCommittedMemoryInBytes
)
3554 *pCommittedMemoryInBytes
= 0;
3557 VkResult
radv_BindBufferMemory2(VkDevice device
,
3558 uint32_t bindInfoCount
,
3559 const VkBindBufferMemoryInfo
*pBindInfos
)
3561 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
3562 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
3563 RADV_FROM_HANDLE(radv_buffer
, buffer
, pBindInfos
[i
].buffer
);
3566 buffer
->bo
= mem
->bo
;
3567 buffer
->offset
= pBindInfos
[i
].memoryOffset
;
3575 VkResult
radv_BindBufferMemory(
3578 VkDeviceMemory memory
,
3579 VkDeviceSize memoryOffset
)
3581 const VkBindBufferMemoryInfo info
= {
3582 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
3585 .memoryOffset
= memoryOffset
3588 return radv_BindBufferMemory2(device
, 1, &info
);
3591 VkResult
radv_BindImageMemory2(VkDevice device
,
3592 uint32_t bindInfoCount
,
3593 const VkBindImageMemoryInfo
*pBindInfos
)
3595 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
3596 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
3597 RADV_FROM_HANDLE(radv_image
, image
, pBindInfos
[i
].image
);
3600 image
->bo
= mem
->bo
;
3601 image
->offset
= pBindInfos
[i
].memoryOffset
;
3611 VkResult
radv_BindImageMemory(
3614 VkDeviceMemory memory
,
3615 VkDeviceSize memoryOffset
)
3617 const VkBindImageMemoryInfo info
= {
3618 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
3621 .memoryOffset
= memoryOffset
3624 return radv_BindImageMemory2(device
, 1, &info
);
3629 radv_sparse_buffer_bind_memory(struct radv_device
*device
,
3630 const VkSparseBufferMemoryBindInfo
*bind
)
3632 RADV_FROM_HANDLE(radv_buffer
, buffer
, bind
->buffer
);
3634 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
3635 struct radv_device_memory
*mem
= NULL
;
3637 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
3638 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
3640 device
->ws
->buffer_virtual_bind(buffer
->bo
,
3641 bind
->pBinds
[i
].resourceOffset
,
3642 bind
->pBinds
[i
].size
,
3643 mem
? mem
->bo
: NULL
,
3644 bind
->pBinds
[i
].memoryOffset
);
3649 radv_sparse_image_opaque_bind_memory(struct radv_device
*device
,
3650 const VkSparseImageOpaqueMemoryBindInfo
*bind
)
3652 RADV_FROM_HANDLE(radv_image
, image
, bind
->image
);
3654 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
3655 struct radv_device_memory
*mem
= NULL
;
3657 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
3658 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
3660 device
->ws
->buffer_virtual_bind(image
->bo
,
3661 bind
->pBinds
[i
].resourceOffset
,
3662 bind
->pBinds
[i
].size
,
3663 mem
? mem
->bo
: NULL
,
3664 bind
->pBinds
[i
].memoryOffset
);
3668 VkResult
radv_QueueBindSparse(
3670 uint32_t bindInfoCount
,
3671 const VkBindSparseInfo
* pBindInfo
,
3674 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3675 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
3676 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
3677 bool fence_emitted
= false;
3681 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
3682 struct radv_winsys_sem_info sem_info
;
3683 for (uint32_t j
= 0; j
< pBindInfo
[i
].bufferBindCount
; ++j
) {
3684 radv_sparse_buffer_bind_memory(queue
->device
,
3685 pBindInfo
[i
].pBufferBinds
+ j
);
3688 for (uint32_t j
= 0; j
< pBindInfo
[i
].imageOpaqueBindCount
; ++j
) {
3689 radv_sparse_image_opaque_bind_memory(queue
->device
,
3690 pBindInfo
[i
].pImageOpaqueBinds
+ j
);
3694 result
= radv_alloc_sem_info(queue
->device
->instance
,
3696 pBindInfo
[i
].waitSemaphoreCount
,
3697 pBindInfo
[i
].pWaitSemaphores
,
3698 pBindInfo
[i
].signalSemaphoreCount
,
3699 pBindInfo
[i
].pSignalSemaphores
,
3701 if (result
!= VK_SUCCESS
)
3704 if (pBindInfo
[i
].waitSemaphoreCount
|| pBindInfo
[i
].signalSemaphoreCount
) {
3705 ret
= queue
->device
->ws
->cs_submit(queue
->hw_ctx
, queue
->queue_idx
,
3706 &queue
->device
->empty_cs
[queue
->queue_family_index
],
3711 radv_loge("failed to submit CS %d\n", i
);
3715 fence_emitted
= true;
3718 radv_free_sem_info(&sem_info
);
3723 if (!fence_emitted
) {
3724 result
= radv_signal_fence(queue
, fence
);
3725 if (result
!= VK_SUCCESS
)
3733 VkResult
radv_CreateFence(
3735 const VkFenceCreateInfo
* pCreateInfo
,
3736 const VkAllocationCallbacks
* pAllocator
,
3739 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3740 const VkExportFenceCreateInfo
*export
=
3741 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_FENCE_CREATE_INFO
);
3742 VkExternalFenceHandleTypeFlags handleTypes
=
3743 export
? export
->handleTypes
: 0;
3745 struct radv_fence
*fence
= vk_alloc2(&device
->alloc
, pAllocator
,
3747 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3750 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3752 fence
->fence_wsi
= NULL
;
3753 fence
->temp_syncobj
= 0;
3754 if (device
->always_use_syncobj
|| handleTypes
) {
3755 int ret
= device
->ws
->create_syncobj(device
->ws
, &fence
->syncobj
);
3757 vk_free2(&device
->alloc
, pAllocator
, fence
);
3758 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3760 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
) {
3761 device
->ws
->signal_syncobj(device
->ws
, fence
->syncobj
);
3763 fence
->fence
= NULL
;
3765 fence
->fence
= device
->ws
->create_fence();
3766 if (!fence
->fence
) {
3767 vk_free2(&device
->alloc
, pAllocator
, fence
);
3768 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3771 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
)
3772 device
->ws
->signal_fence(fence
->fence
);
3775 *pFence
= radv_fence_to_handle(fence
);
3780 void radv_DestroyFence(
3783 const VkAllocationCallbacks
* pAllocator
)
3785 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3786 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3791 if (fence
->temp_syncobj
)
3792 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
3794 device
->ws
->destroy_syncobj(device
->ws
, fence
->syncobj
);
3796 device
->ws
->destroy_fence(fence
->fence
);
3797 if (fence
->fence_wsi
)
3798 fence
->fence_wsi
->destroy(fence
->fence_wsi
);
3799 vk_free2(&device
->alloc
, pAllocator
, fence
);
3803 uint64_t radv_get_current_time(void)
3806 clock_gettime(CLOCK_MONOTONIC
, &tv
);
3807 return tv
.tv_nsec
+ tv
.tv_sec
*1000000000ull;
3810 static uint64_t radv_get_absolute_timeout(uint64_t timeout
)
3812 uint64_t current_time
= radv_get_current_time();
3814 timeout
= MIN2(UINT64_MAX
- current_time
, timeout
);
3816 return current_time
+ timeout
;
3820 static bool radv_all_fences_plain_and_submitted(struct radv_device
*device
,
3821 uint32_t fenceCount
, const VkFence
*pFences
)
3823 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3824 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3825 if (fence
->fence
== NULL
|| fence
->syncobj
||
3826 fence
->temp_syncobj
|| fence
->fence_wsi
||
3827 (!device
->ws
->is_fence_waitable(fence
->fence
)))
3833 static bool radv_all_fences_syncobj(uint32_t fenceCount
, const VkFence
*pFences
)
3835 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3836 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3837 if (fence
->syncobj
== 0 && fence
->temp_syncobj
== 0)
3843 VkResult
radv_WaitForFences(
3845 uint32_t fenceCount
,
3846 const VkFence
* pFences
,
3850 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3851 timeout
= radv_get_absolute_timeout(timeout
);
3853 if (device
->always_use_syncobj
&&
3854 radv_all_fences_syncobj(fenceCount
, pFences
))
3856 uint32_t *handles
= malloc(sizeof(uint32_t) * fenceCount
);
3858 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3860 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3861 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3862 handles
[i
] = fence
->temp_syncobj
? fence
->temp_syncobj
: fence
->syncobj
;
3865 bool success
= device
->ws
->wait_syncobj(device
->ws
, handles
, fenceCount
, waitAll
, timeout
);
3868 return success
? VK_SUCCESS
: VK_TIMEOUT
;
3871 if (!waitAll
&& fenceCount
> 1) {
3872 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3873 if (device
->physical_device
->rad_info
.drm_minor
>= 10 && radv_all_fences_plain_and_submitted(device
, fenceCount
, pFences
)) {
3874 uint32_t wait_count
= 0;
3875 struct radeon_winsys_fence
**fences
= malloc(sizeof(struct radeon_winsys_fence
*) * fenceCount
);
3877 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3879 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3880 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3882 if (device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0)) {
3887 fences
[wait_count
++] = fence
->fence
;
3890 bool success
= device
->ws
->fences_wait(device
->ws
, fences
, wait_count
,
3891 waitAll
, timeout
- radv_get_current_time());
3894 return success
? VK_SUCCESS
: VK_TIMEOUT
;
3897 while(radv_get_current_time() <= timeout
) {
3898 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3899 if (radv_GetFenceStatus(_device
, pFences
[i
]) == VK_SUCCESS
)
3906 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3907 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3908 bool expired
= false;
3910 if (fence
->temp_syncobj
) {
3911 if (!device
->ws
->wait_syncobj(device
->ws
, &fence
->temp_syncobj
, 1, true, timeout
))
3916 if (fence
->syncobj
) {
3917 if (!device
->ws
->wait_syncobj(device
->ws
, &fence
->syncobj
, 1, true, timeout
))
3923 if (!device
->ws
->is_fence_waitable(fence
->fence
)) {
3924 while(!device
->ws
->is_fence_waitable(fence
->fence
) &&
3925 radv_get_current_time() <= timeout
)
3929 expired
= device
->ws
->fence_wait(device
->ws
,
3936 if (fence
->fence_wsi
) {
3937 VkResult result
= fence
->fence_wsi
->wait(fence
->fence_wsi
, timeout
);
3938 if (result
!= VK_SUCCESS
)
3946 VkResult
radv_ResetFences(VkDevice _device
,
3947 uint32_t fenceCount
,
3948 const VkFence
*pFences
)
3950 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3952 for (unsigned i
= 0; i
< fenceCount
; ++i
) {
3953 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3955 device
->ws
->reset_fence(fence
->fence
);
3957 /* Per spec, we first restore the permanent payload, and then reset, so
3958 * having a temp syncobj should not skip resetting the permanent syncobj. */
3959 if (fence
->temp_syncobj
) {
3960 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
3961 fence
->temp_syncobj
= 0;
3964 if (fence
->syncobj
) {
3965 device
->ws
->reset_syncobj(device
->ws
, fence
->syncobj
);
3972 VkResult
radv_GetFenceStatus(VkDevice _device
, VkFence _fence
)
3974 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3975 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3977 if (fence
->temp_syncobj
) {
3978 bool success
= device
->ws
->wait_syncobj(device
->ws
, &fence
->temp_syncobj
, 1, true, 0);
3979 return success
? VK_SUCCESS
: VK_NOT_READY
;
3982 if (fence
->syncobj
) {
3983 bool success
= device
->ws
->wait_syncobj(device
->ws
, &fence
->syncobj
, 1, true, 0);
3984 return success
? VK_SUCCESS
: VK_NOT_READY
;
3988 if (!device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0))
3989 return VK_NOT_READY
;
3991 if (fence
->fence_wsi
) {
3992 VkResult result
= fence
->fence_wsi
->wait(fence
->fence_wsi
, 0);
3994 if (result
!= VK_SUCCESS
) {
3995 if (result
== VK_TIMEOUT
)
3996 return VK_NOT_READY
;
4004 // Queue semaphore functions
4006 VkResult
radv_CreateSemaphore(
4008 const VkSemaphoreCreateInfo
* pCreateInfo
,
4009 const VkAllocationCallbacks
* pAllocator
,
4010 VkSemaphore
* pSemaphore
)
4012 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4013 const VkExportSemaphoreCreateInfo
*export
=
4014 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_SEMAPHORE_CREATE_INFO
);
4015 VkExternalSemaphoreHandleTypeFlags handleTypes
=
4016 export
? export
->handleTypes
: 0;
4018 struct radv_semaphore
*sem
= vk_alloc2(&device
->alloc
, pAllocator
,
4020 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4022 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4024 sem
->temp_syncobj
= 0;
4025 /* create a syncobject if we are going to export this semaphore */
4026 if (device
->always_use_syncobj
|| handleTypes
) {
4027 assert (device
->physical_device
->rad_info
.has_syncobj
);
4028 int ret
= device
->ws
->create_syncobj(device
->ws
, &sem
->syncobj
);
4030 vk_free2(&device
->alloc
, pAllocator
, sem
);
4031 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4035 sem
->sem
= device
->ws
->create_sem(device
->ws
);
4037 vk_free2(&device
->alloc
, pAllocator
, sem
);
4038 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4043 *pSemaphore
= radv_semaphore_to_handle(sem
);
4047 void radv_DestroySemaphore(
4049 VkSemaphore _semaphore
,
4050 const VkAllocationCallbacks
* pAllocator
)
4052 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4053 RADV_FROM_HANDLE(radv_semaphore
, sem
, _semaphore
);
4058 device
->ws
->destroy_syncobj(device
->ws
, sem
->syncobj
);
4060 device
->ws
->destroy_sem(sem
->sem
);
4061 vk_free2(&device
->alloc
, pAllocator
, sem
);
4064 VkResult
radv_CreateEvent(
4066 const VkEventCreateInfo
* pCreateInfo
,
4067 const VkAllocationCallbacks
* pAllocator
,
4070 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4071 struct radv_event
*event
= vk_alloc2(&device
->alloc
, pAllocator
,
4073 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4076 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4078 event
->bo
= device
->ws
->buffer_create(device
->ws
, 8, 8,
4080 RADEON_FLAG_VA_UNCACHED
| RADEON_FLAG_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
,
4081 RADV_BO_PRIORITY_FENCE
);
4083 vk_free2(&device
->alloc
, pAllocator
, event
);
4084 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
4087 event
->map
= (uint64_t*)device
->ws
->buffer_map(event
->bo
);
4089 *pEvent
= radv_event_to_handle(event
);
4094 void radv_DestroyEvent(
4097 const VkAllocationCallbacks
* pAllocator
)
4099 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4100 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4104 device
->ws
->buffer_destroy(event
->bo
);
4105 vk_free2(&device
->alloc
, pAllocator
, event
);
4108 VkResult
radv_GetEventStatus(
4112 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4114 if (*event
->map
== 1)
4115 return VK_EVENT_SET
;
4116 return VK_EVENT_RESET
;
4119 VkResult
radv_SetEvent(
4123 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4129 VkResult
radv_ResetEvent(
4133 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4139 VkResult
radv_CreateBuffer(
4141 const VkBufferCreateInfo
* pCreateInfo
,
4142 const VkAllocationCallbacks
* pAllocator
,
4145 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4146 struct radv_buffer
*buffer
;
4148 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO
);
4150 buffer
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*buffer
), 8,
4151 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4153 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4155 buffer
->size
= pCreateInfo
->size
;
4156 buffer
->usage
= pCreateInfo
->usage
;
4159 buffer
->flags
= pCreateInfo
->flags
;
4161 buffer
->shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
4162 EXTERNAL_MEMORY_BUFFER_CREATE_INFO
) != NULL
;
4164 if (pCreateInfo
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
) {
4165 buffer
->bo
= device
->ws
->buffer_create(device
->ws
,
4166 align64(buffer
->size
, 4096),
4167 4096, 0, RADEON_FLAG_VIRTUAL
,
4168 RADV_BO_PRIORITY_VIRTUAL
);
4170 vk_free2(&device
->alloc
, pAllocator
, buffer
);
4171 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
4175 *pBuffer
= radv_buffer_to_handle(buffer
);
4180 void radv_DestroyBuffer(
4183 const VkAllocationCallbacks
* pAllocator
)
4185 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4186 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4191 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
4192 device
->ws
->buffer_destroy(buffer
->bo
);
4194 vk_free2(&device
->alloc
, pAllocator
, buffer
);
4197 VkDeviceAddress
radv_GetBufferDeviceAddressEXT(
4199 const VkBufferDeviceAddressInfoEXT
* pInfo
)
4201 RADV_FROM_HANDLE(radv_buffer
, buffer
, pInfo
->buffer
);
4202 return radv_buffer_get_va(buffer
->bo
) + buffer
->offset
;
4206 static inline unsigned
4207 si_tile_mode_index(const struct radv_image_plane
*plane
, unsigned level
, bool stencil
)
4210 return plane
->surface
.u
.legacy
.stencil_tiling_index
[level
];
4212 return plane
->surface
.u
.legacy
.tiling_index
[level
];
4215 static uint32_t radv_surface_max_layer_count(struct radv_image_view
*iview
)
4217 return iview
->type
== VK_IMAGE_VIEW_TYPE_3D
? iview
->extent
.depth
: (iview
->base_layer
+ iview
->layer_count
);
4221 radv_init_dcc_control_reg(struct radv_device
*device
,
4222 struct radv_image_view
*iview
)
4224 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
4225 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
4226 unsigned max_compressed_block_size
;
4227 unsigned independent_64b_blocks
;
4229 if (!radv_dcc_enabled(iview
->image
, iview
->base_mip
))
4232 if (iview
->image
->info
.samples
> 1) {
4233 if (iview
->image
->planes
[0].surface
.bpe
== 1)
4234 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
4235 else if (iview
->image
->planes
[0].surface
.bpe
== 2)
4236 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
4239 if (!device
->physical_device
->rad_info
.has_dedicated_vram
) {
4240 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4241 * dGPU and 64 for APU because all of our APUs to date use
4242 * DIMMs which have a request granularity size of 64B while all
4243 * other chips have a 32B request size.
4245 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
4248 if (iview
->image
->usage
& (VK_IMAGE_USAGE_SAMPLED_BIT
|
4249 VK_IMAGE_USAGE_TRANSFER_SRC_BIT
|
4250 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)) {
4251 /* If this DCC image is potentially going to be used in texture
4252 * fetches, we need some special settings.
4254 independent_64b_blocks
= 1;
4255 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
4257 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4258 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4259 * big as possible for better compression state.
4261 independent_64b_blocks
= 0;
4262 max_compressed_block_size
= max_uncompressed_block_size
;
4265 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
4266 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size
) |
4267 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
4268 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks
);
4272 radv_initialise_color_surface(struct radv_device
*device
,
4273 struct radv_color_buffer_info
*cb
,
4274 struct radv_image_view
*iview
)
4276 const struct vk_format_description
*desc
;
4277 unsigned ntype
, format
, swap
, endian
;
4278 unsigned blend_clamp
= 0, blend_bypass
= 0;
4280 const struct radv_image_plane
*plane
= &iview
->image
->planes
[iview
->plane_id
];
4281 const struct radeon_surf
*surf
= &plane
->surface
;
4283 desc
= vk_format_description(iview
->vk_format
);
4285 memset(cb
, 0, sizeof(*cb
));
4287 /* Intensity is implemented as Red, so treat it that way. */
4288 cb
->cb_color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == VK_SWIZZLE_1
);
4290 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ plane
->offset
;
4292 cb
->cb_color_base
= va
>> 8;
4294 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4295 struct gfx9_surf_meta_flags meta
;
4296 if (iview
->image
->dcc_offset
)
4297 meta
= surf
->u
.gfx9
.dcc
;
4299 meta
= surf
->u
.gfx9
.cmask
;
4301 cb
->cb_color_attrib
|= S_028C74_COLOR_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
4302 S_028C74_FMASK_SW_MODE(surf
->u
.gfx9
.fmask
.swizzle_mode
) |
4303 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
4304 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
4306 cb
->cb_color_base
+= surf
->u
.gfx9
.surf_offset
>> 8;
4307 cb
->cb_color_base
|= surf
->tile_swizzle
;
4309 cb
->cb_mrt_epitch
= S_0287A0_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
4311 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[iview
->base_mip
];
4312 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
4314 cb
->cb_color_base
+= level_info
->offset
>> 8;
4315 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
4316 cb
->cb_color_base
|= surf
->tile_swizzle
;
4318 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
4319 slice_tile_max
= (level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1;
4320 tile_mode_index
= si_tile_mode_index(plane
, iview
->base_mip
, false);
4322 cb
->cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
4323 cb
->cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
4324 cb
->cb_color_cmask_slice
= iview
->image
->cmask
.slice_tile_max
;
4326 cb
->cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
4328 if (radv_image_has_fmask(iview
->image
)) {
4329 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
4330 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(iview
->image
->fmask
.pitch_in_pixels
/ 8 - 1);
4331 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(iview
->image
->fmask
.tile_mode_index
);
4332 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(iview
->image
->fmask
.slice_tile_max
);
4334 /* This must be set for fast clear to work without FMASK. */
4335 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
4336 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
4337 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
4338 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
4342 /* CMASK variables */
4343 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
4344 va
+= iview
->image
->cmask
.offset
;
4345 cb
->cb_color_cmask
= va
>> 8;
4347 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
4348 va
+= iview
->image
->dcc_offset
;
4350 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
) &&
4351 device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4352 va
+= plane
->surface
.u
.legacy
.level
[iview
->base_mip
].dcc_offset
;
4354 cb
->cb_dcc_base
= va
>> 8;
4355 cb
->cb_dcc_base
|= surf
->tile_swizzle
;
4357 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
4358 cb
->cb_color_view
= S_028C6C_SLICE_START(iview
->base_layer
) |
4359 S_028C6C_SLICE_MAX_GFX6(max_slice
);
4361 if (iview
->image
->info
.samples
> 1) {
4362 unsigned log_samples
= util_logbase2(iview
->image
->info
.samples
);
4364 cb
->cb_color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
4365 S_028C74_NUM_FRAGMENTS(log_samples
);
4368 if (radv_image_has_fmask(iview
->image
)) {
4369 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ iview
->image
->fmask
.offset
;
4370 cb
->cb_color_fmask
= va
>> 8;
4371 cb
->cb_color_fmask
|= iview
->image
->fmask
.tile_swizzle
;
4373 cb
->cb_color_fmask
= cb
->cb_color_base
;
4376 ntype
= radv_translate_color_numformat(iview
->vk_format
,
4378 vk_format_get_first_non_void_channel(iview
->vk_format
));
4379 format
= radv_translate_colorformat(iview
->vk_format
);
4380 if (format
== V_028C70_COLOR_INVALID
|| ntype
== ~0u)
4381 radv_finishme("Illegal color\n");
4382 swap
= radv_translate_colorswap(iview
->vk_format
, FALSE
);
4383 endian
= radv_colorformat_endian_swap(format
);
4385 /* blend clamp should be set for all NORM/SRGB types */
4386 if (ntype
== V_028C70_NUMBER_UNORM
||
4387 ntype
== V_028C70_NUMBER_SNORM
||
4388 ntype
== V_028C70_NUMBER_SRGB
)
4391 /* set blend bypass according to docs if SINT/UINT or
4392 8/24 COLOR variants */
4393 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
4394 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
4395 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
4400 if ((ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) &&
4401 (format
== V_028C70_COLOR_8
||
4402 format
== V_028C70_COLOR_8_8
||
4403 format
== V_028C70_COLOR_8_8_8_8
))
4404 ->color_is_int8
= true;
4406 cb
->cb_color_info
= S_028C70_FORMAT(format
) |
4407 S_028C70_COMP_SWAP(swap
) |
4408 S_028C70_BLEND_CLAMP(blend_clamp
) |
4409 S_028C70_BLEND_BYPASS(blend_bypass
) |
4410 S_028C70_SIMPLE_FLOAT(1) |
4411 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
4412 ntype
!= V_028C70_NUMBER_SNORM
&&
4413 ntype
!= V_028C70_NUMBER_SRGB
&&
4414 format
!= V_028C70_COLOR_8_24
&&
4415 format
!= V_028C70_COLOR_24_8
) |
4416 S_028C70_NUMBER_TYPE(ntype
) |
4417 S_028C70_ENDIAN(endian
);
4418 if (radv_image_has_fmask(iview
->image
)) {
4419 cb
->cb_color_info
|= S_028C70_COMPRESSION(1);
4420 if (device
->physical_device
->rad_info
.chip_class
== GFX6
) {
4421 unsigned fmask_bankh
= util_logbase2(iview
->image
->fmask
.bank_height
);
4422 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
4425 if (radv_image_is_tc_compat_cmask(iview
->image
)) {
4426 /* Allow the texture block to read FMASK directly
4427 * without decompressing it. This bit must be cleared
4428 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
4429 * otherwise the operation doesn't happen.
4431 cb
->cb_color_info
|= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
4433 /* Set CMASK into a tiling format that allows the
4434 * texture block to read it.
4436 cb
->cb_color_info
|= S_028C70_CMASK_ADDR_TYPE(2);
4440 if (radv_image_has_cmask(iview
->image
) &&
4441 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
))
4442 cb
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
4444 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
))
4445 cb
->cb_color_info
|= S_028C70_DCC_ENABLE(1);
4447 cb
->cb_dcc_control
= radv_init_dcc_control_reg(device
, iview
);
4449 /* This must be set for fast clear to work without FMASK. */
4450 if (!radv_image_has_fmask(iview
->image
) &&
4451 device
->physical_device
->rad_info
.chip_class
== GFX6
) {
4452 unsigned bankh
= util_logbase2(surf
->u
.legacy
.bankh
);
4453 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
4456 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4457 const struct vk_format_description
*format_desc
= vk_format_description(iview
->image
->vk_format
);
4459 unsigned mip0_depth
= iview
->image
->type
== VK_IMAGE_TYPE_3D
?
4460 (iview
->extent
.depth
- 1) : (iview
->image
->info
.array_size
- 1);
4461 unsigned width
= iview
->extent
.width
/ (iview
->plane_id
? format_desc
->width_divisor
: 1);
4462 unsigned height
= iview
->extent
.height
/ (iview
->plane_id
? format_desc
->height_divisor
: 1);
4464 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL_GFX9(iview
->base_mip
);
4465 cb
->cb_color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
4466 S_028C74_RESOURCE_TYPE(surf
->u
.gfx9
.resource_type
);
4467 cb
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(width
- 1) |
4468 S_028C68_MIP0_HEIGHT(height
- 1) |
4469 S_028C68_MAX_MIP(iview
->image
->info
.levels
- 1);
4474 radv_calc_decompress_on_z_planes(struct radv_device
*device
,
4475 struct radv_image_view
*iview
)
4477 unsigned max_zplanes
= 0;
4479 assert(radv_image_is_tc_compat_htile(iview
->image
));
4481 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4482 /* Default value for 32-bit depth surfaces. */
4485 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
&&
4486 iview
->image
->info
.samples
> 1)
4489 max_zplanes
= max_zplanes
+ 1;
4491 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
) {
4492 /* Do not enable Z plane compression for 16-bit depth
4493 * surfaces because isn't supported on GFX8. Only
4494 * 32-bit depth surfaces are supported by the hardware.
4495 * This allows to maintain shader compatibility and to
4496 * reduce the number of depth decompressions.
4500 if (iview
->image
->info
.samples
<= 1)
4502 else if (iview
->image
->info
.samples
<= 4)
4513 radv_initialise_ds_surface(struct radv_device
*device
,
4514 struct radv_ds_buffer_info
*ds
,
4515 struct radv_image_view
*iview
)
4517 unsigned level
= iview
->base_mip
;
4518 unsigned format
, stencil_format
;
4519 uint64_t va
, s_offs
, z_offs
;
4520 bool stencil_only
= false;
4521 const struct radv_image_plane
*plane
= &iview
->image
->planes
[0];
4522 const struct radeon_surf
*surf
= &plane
->surface
;
4524 assert(vk_format_get_plane_count(iview
->image
->vk_format
) == 1);
4526 memset(ds
, 0, sizeof(*ds
));
4527 switch (iview
->image
->vk_format
) {
4528 case VK_FORMAT_D24_UNORM_S8_UINT
:
4529 case VK_FORMAT_X8_D24_UNORM_PACK32
:
4530 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4531 ds
->offset_scale
= 2.0f
;
4533 case VK_FORMAT_D16_UNORM
:
4534 case VK_FORMAT_D16_UNORM_S8_UINT
:
4535 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4536 ds
->offset_scale
= 4.0f
;
4538 case VK_FORMAT_D32_SFLOAT
:
4539 case VK_FORMAT_D32_SFLOAT_S8_UINT
:
4540 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4541 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4542 ds
->offset_scale
= 1.0f
;
4544 case VK_FORMAT_S8_UINT
:
4545 stencil_only
= true;
4551 format
= radv_translate_dbformat(iview
->image
->vk_format
);
4552 stencil_format
= surf
->has_stencil
?
4553 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
4555 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
4556 ds
->db_depth_view
= S_028008_SLICE_START(iview
->base_layer
) |
4557 S_028008_SLICE_MAX(max_slice
);
4559 ds
->db_htile_data_base
= 0;
4560 ds
->db_htile_surface
= 0;
4562 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
4563 s_offs
= z_offs
= va
;
4565 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4566 assert(surf
->u
.gfx9
.surf_offset
== 0);
4567 s_offs
+= surf
->u
.gfx9
.stencil_offset
;
4569 ds
->db_z_info
= S_028038_FORMAT(format
) |
4570 S_028038_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
)) |
4571 S_028038_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
4572 S_028038_MAXMIP(iview
->image
->info
.levels
- 1) |
4573 S_028038_ZRANGE_PRECISION(1);
4574 ds
->db_stencil_info
= S_02803C_FORMAT(stencil_format
) |
4575 S_02803C_SW_MODE(surf
->u
.gfx9
.stencil
.swizzle_mode
);
4577 ds
->db_z_info2
= S_028068_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
4578 ds
->db_stencil_info2
= S_02806C_EPITCH(surf
->u
.gfx9
.stencil
.epitch
);
4579 ds
->db_depth_view
|= S_028008_MIPID(level
);
4581 ds
->db_depth_size
= S_02801C_X_MAX(iview
->image
->info
.width
- 1) |
4582 S_02801C_Y_MAX(iview
->image
->info
.height
- 1);
4584 if (radv_htile_enabled(iview
->image
, level
)) {
4585 ds
->db_z_info
|= S_028038_TILE_SURFACE_ENABLE(1);
4587 if (radv_image_is_tc_compat_htile(iview
->image
)) {
4588 unsigned max_zplanes
=
4589 radv_calc_decompress_on_z_planes(device
, iview
);
4591 ds
->db_z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
) |
4592 S_028038_ITERATE_FLUSH(1);
4593 ds
->db_stencil_info
|= S_02803C_ITERATE_FLUSH(1);
4596 if (!surf
->has_stencil
)
4597 /* Use all of the htile_buffer for depth if there's no stencil. */
4598 ds
->db_stencil_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
4599 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
4600 iview
->image
->htile_offset
;
4601 ds
->db_htile_data_base
= va
>> 8;
4602 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
4603 S_028ABC_PIPE_ALIGNED(surf
->u
.gfx9
.htile
.pipe_aligned
) |
4604 S_028ABC_RB_ALIGNED(surf
->u
.gfx9
.htile
.rb_aligned
);
4607 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[level
];
4610 level_info
= &surf
->u
.legacy
.stencil_level
[level
];
4612 z_offs
+= surf
->u
.legacy
.level
[level
].offset
;
4613 s_offs
+= surf
->u
.legacy
.stencil_level
[level
].offset
;
4615 ds
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview
->image
));
4616 ds
->db_z_info
= S_028040_FORMAT(format
) | S_028040_ZRANGE_PRECISION(1);
4617 ds
->db_stencil_info
= S_028044_FORMAT(stencil_format
);
4619 if (iview
->image
->info
.samples
> 1)
4620 ds
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
));
4622 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4623 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
4624 unsigned tiling_index
= surf
->u
.legacy
.tiling_index
[level
];
4625 unsigned stencil_index
= surf
->u
.legacy
.stencil_tiling_index
[level
];
4626 unsigned macro_index
= surf
->u
.legacy
.macro_tile_index
;
4627 unsigned tile_mode
= info
->si_tile_mode_array
[tiling_index
];
4628 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
4629 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
4632 tile_mode
= stencil_tile_mode
;
4634 ds
->db_depth_info
|=
4635 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
4636 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
4637 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
4638 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
4639 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
4640 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
4641 ds
->db_z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
4642 ds
->db_stencil_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
4644 unsigned tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, false);
4645 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
4646 tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, true);
4647 ds
->db_stencil_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
4649 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
4652 ds
->db_depth_size
= S_028058_PITCH_TILE_MAX((level_info
->nblk_x
/ 8) - 1) |
4653 S_028058_HEIGHT_TILE_MAX((level_info
->nblk_y
/ 8) - 1);
4654 ds
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1);
4656 if (radv_htile_enabled(iview
->image
, level
)) {
4657 ds
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
4659 if (!surf
->has_stencil
&&
4660 !radv_image_is_tc_compat_htile(iview
->image
))
4661 /* Use all of the htile_buffer for depth if there's no stencil. */
4662 ds
->db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
4664 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
4665 iview
->image
->htile_offset
;
4666 ds
->db_htile_data_base
= va
>> 8;
4667 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
4669 if (radv_image_is_tc_compat_htile(iview
->image
)) {
4670 unsigned max_zplanes
=
4671 radv_calc_decompress_on_z_planes(device
, iview
);
4673 ds
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
4674 ds
->db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
4679 ds
->db_z_read_base
= ds
->db_z_write_base
= z_offs
>> 8;
4680 ds
->db_stencil_read_base
= ds
->db_stencil_write_base
= s_offs
>> 8;
4683 VkResult
radv_CreateFramebuffer(
4685 const VkFramebufferCreateInfo
* pCreateInfo
,
4686 const VkAllocationCallbacks
* pAllocator
,
4687 VkFramebuffer
* pFramebuffer
)
4689 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4690 struct radv_framebuffer
*framebuffer
;
4692 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
);
4694 size_t size
= sizeof(*framebuffer
) +
4695 sizeof(struct radv_attachment_info
) * pCreateInfo
->attachmentCount
;
4696 framebuffer
= vk_alloc2(&device
->alloc
, pAllocator
, size
, 8,
4697 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4698 if (framebuffer
== NULL
)
4699 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4701 framebuffer
->attachment_count
= pCreateInfo
->attachmentCount
;
4702 framebuffer
->width
= pCreateInfo
->width
;
4703 framebuffer
->height
= pCreateInfo
->height
;
4704 framebuffer
->layers
= pCreateInfo
->layers
;
4705 for (uint32_t i
= 0; i
< pCreateInfo
->attachmentCount
; i
++) {
4706 VkImageView _iview
= pCreateInfo
->pAttachments
[i
];
4707 struct radv_image_view
*iview
= radv_image_view_from_handle(_iview
);
4708 framebuffer
->attachments
[i
].attachment
= iview
;
4709 if (iview
->aspect_mask
& (VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4710 radv_initialise_ds_surface(device
, &framebuffer
->attachments
[i
].ds
, iview
);
4712 radv_initialise_color_surface(device
, &framebuffer
->attachments
[i
].cb
, iview
);
4714 framebuffer
->width
= MIN2(framebuffer
->width
, iview
->extent
.width
);
4715 framebuffer
->height
= MIN2(framebuffer
->height
, iview
->extent
.height
);
4716 framebuffer
->layers
= MIN2(framebuffer
->layers
, radv_surface_max_layer_count(iview
));
4719 *pFramebuffer
= radv_framebuffer_to_handle(framebuffer
);
4723 void radv_DestroyFramebuffer(
4726 const VkAllocationCallbacks
* pAllocator
)
4728 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4729 RADV_FROM_HANDLE(radv_framebuffer
, fb
, _fb
);
4733 vk_free2(&device
->alloc
, pAllocator
, fb
);
4736 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode
)
4738 switch (address_mode
) {
4739 case VK_SAMPLER_ADDRESS_MODE_REPEAT
:
4740 return V_008F30_SQ_TEX_WRAP
;
4741 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT
:
4742 return V_008F30_SQ_TEX_MIRROR
;
4743 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
:
4744 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
4745 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
:
4746 return V_008F30_SQ_TEX_CLAMP_BORDER
;
4747 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE
:
4748 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
4750 unreachable("illegal tex wrap mode");
4756 radv_tex_compare(VkCompareOp op
)
4759 case VK_COMPARE_OP_NEVER
:
4760 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
4761 case VK_COMPARE_OP_LESS
:
4762 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
4763 case VK_COMPARE_OP_EQUAL
:
4764 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
4765 case VK_COMPARE_OP_LESS_OR_EQUAL
:
4766 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
4767 case VK_COMPARE_OP_GREATER
:
4768 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
4769 case VK_COMPARE_OP_NOT_EQUAL
:
4770 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
4771 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
4772 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
4773 case VK_COMPARE_OP_ALWAYS
:
4774 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
4776 unreachable("illegal compare mode");
4782 radv_tex_filter(VkFilter filter
, unsigned max_ansio
)
4785 case VK_FILTER_NEAREST
:
4786 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
:
4787 V_008F38_SQ_TEX_XY_FILTER_POINT
);
4788 case VK_FILTER_LINEAR
:
4789 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
:
4790 V_008F38_SQ_TEX_XY_FILTER_BILINEAR
);
4791 case VK_FILTER_CUBIC_IMG
:
4793 fprintf(stderr
, "illegal texture filter");
4799 radv_tex_mipfilter(VkSamplerMipmapMode mode
)
4802 case VK_SAMPLER_MIPMAP_MODE_NEAREST
:
4803 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
4804 case VK_SAMPLER_MIPMAP_MODE_LINEAR
:
4805 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
4807 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
4812 radv_tex_bordercolor(VkBorderColor bcolor
)
4815 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
:
4816 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK
:
4817 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
4818 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK
:
4819 case VK_BORDER_COLOR_INT_OPAQUE_BLACK
:
4820 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
4821 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE
:
4822 case VK_BORDER_COLOR_INT_OPAQUE_WHITE
:
4823 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
4831 radv_tex_aniso_filter(unsigned filter
)
4845 radv_tex_filter_mode(VkSamplerReductionModeEXT mode
)
4848 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT
:
4849 return V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
4850 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT
:
4851 return V_008F30_SQ_IMG_FILTER_MODE_MIN
;
4852 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT
:
4853 return V_008F30_SQ_IMG_FILTER_MODE_MAX
;
4861 radv_get_max_anisotropy(struct radv_device
*device
,
4862 const VkSamplerCreateInfo
*pCreateInfo
)
4864 if (device
->force_aniso
>= 0)
4865 return device
->force_aniso
;
4867 if (pCreateInfo
->anisotropyEnable
&&
4868 pCreateInfo
->maxAnisotropy
> 1.0f
)
4869 return (uint32_t)pCreateInfo
->maxAnisotropy
;
4875 radv_init_sampler(struct radv_device
*device
,
4876 struct radv_sampler
*sampler
,
4877 const VkSamplerCreateInfo
*pCreateInfo
)
4879 uint32_t max_aniso
= radv_get_max_anisotropy(device
, pCreateInfo
);
4880 uint32_t max_aniso_ratio
= radv_tex_aniso_filter(max_aniso
);
4881 bool is_vi
= (device
->physical_device
->rad_info
.chip_class
>= GFX8
);
4882 unsigned filter_mode
= V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
4884 const struct VkSamplerReductionModeCreateInfoEXT
*sampler_reduction
=
4885 vk_find_struct_const(pCreateInfo
->pNext
,
4886 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT
);
4887 if (sampler_reduction
)
4888 filter_mode
= radv_tex_filter_mode(sampler_reduction
->reductionMode
);
4890 sampler
->state
[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo
->addressModeU
)) |
4891 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo
->addressModeV
)) |
4892 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo
->addressModeW
)) |
4893 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
4894 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo
->compareOp
)) |
4895 S_008F30_FORCE_UNNORMALIZED(pCreateInfo
->unnormalizedCoordinates
? 1 : 0) |
4896 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
4897 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
4898 S_008F30_DISABLE_CUBE_WRAP(0) |
4899 S_008F30_COMPAT_MODE(is_vi
) |
4900 S_008F30_FILTER_MODE(filter_mode
));
4901 sampler
->state
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo
->minLod
, 0, 15), 8)) |
4902 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo
->maxLod
, 0, 15), 8)) |
4903 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
4904 sampler
->state
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo
->mipLodBias
, -16, 16), 8)) |
4905 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo
->magFilter
, max_aniso
)) |
4906 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo
->minFilter
, max_aniso
)) |
4907 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo
->mipmapMode
)) |
4908 S_008F38_MIP_POINT_PRECLAMP(0) |
4909 S_008F38_DISABLE_LSB_CEIL(device
->physical_device
->rad_info
.chip_class
<= GFX8
) |
4910 S_008F38_FILTER_PREC_FIX(1) |
4911 S_008F38_ANISO_OVERRIDE_GFX6(is_vi
));
4912 sampler
->state
[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4913 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo
->borderColor
)));
4916 VkResult
radv_CreateSampler(
4918 const VkSamplerCreateInfo
* pCreateInfo
,
4919 const VkAllocationCallbacks
* pAllocator
,
4920 VkSampler
* pSampler
)
4922 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4923 struct radv_sampler
*sampler
;
4925 const struct VkSamplerYcbcrConversionInfo
*ycbcr_conversion
=
4926 vk_find_struct_const(pCreateInfo
->pNext
,
4927 SAMPLER_YCBCR_CONVERSION_INFO
);
4929 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO
);
4931 sampler
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*sampler
), 8,
4932 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4934 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4936 radv_init_sampler(device
, sampler
, pCreateInfo
);
4938 sampler
->ycbcr_sampler
= ycbcr_conversion
? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion
->conversion
): NULL
;
4939 *pSampler
= radv_sampler_to_handle(sampler
);
4944 void radv_DestroySampler(
4947 const VkAllocationCallbacks
* pAllocator
)
4949 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4950 RADV_FROM_HANDLE(radv_sampler
, sampler
, _sampler
);
4954 vk_free2(&device
->alloc
, pAllocator
, sampler
);
4957 /* vk_icd.h does not declare this function, so we declare it here to
4958 * suppress Wmissing-prototypes.
4960 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4961 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
);
4963 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4964 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
)
4966 /* For the full details on loader interface versioning, see
4967 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4968 * What follows is a condensed summary, to help you navigate the large and
4969 * confusing official doc.
4971 * - Loader interface v0 is incompatible with later versions. We don't
4974 * - In loader interface v1:
4975 * - The first ICD entrypoint called by the loader is
4976 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4978 * - The ICD must statically expose no other Vulkan symbol unless it is
4979 * linked with -Bsymbolic.
4980 * - Each dispatchable Vulkan handle created by the ICD must be
4981 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4982 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4983 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4984 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4985 * such loader-managed surfaces.
4987 * - Loader interface v2 differs from v1 in:
4988 * - The first ICD entrypoint called by the loader is
4989 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4990 * statically expose this entrypoint.
4992 * - Loader interface v3 differs from v2 in:
4993 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4994 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4995 * because the loader no longer does so.
4997 *pSupportedVersion
= MIN2(*pSupportedVersion
, 4u);
5001 VkResult
radv_GetMemoryFdKHR(VkDevice _device
,
5002 const VkMemoryGetFdInfoKHR
*pGetFdInfo
,
5005 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5006 RADV_FROM_HANDLE(radv_device_memory
, memory
, pGetFdInfo
->memory
);
5008 assert(pGetFdInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR
);
5010 /* At the moment, we support only the below handle types. */
5011 assert(pGetFdInfo
->handleType
==
5012 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
5013 pGetFdInfo
->handleType
==
5014 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
5016 bool ret
= radv_get_memory_fd(device
, memory
, pFD
);
5018 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
5022 VkResult
radv_GetMemoryFdPropertiesKHR(VkDevice _device
,
5023 VkExternalMemoryHandleTypeFlagBits handleType
,
5025 VkMemoryFdPropertiesKHR
*pMemoryFdProperties
)
5027 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5029 switch (handleType
) {
5030 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
:
5031 pMemoryFdProperties
->memoryTypeBits
= (1 << RADV_MEM_TYPE_COUNT
) - 1;
5035 /* The valid usage section for this function says:
5037 * "handleType must not be one of the handle types defined as
5040 * So opaque handle types fall into the default "unsupported" case.
5042 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5046 static VkResult
radv_import_opaque_fd(struct radv_device
*device
,
5050 uint32_t syncobj_handle
= 0;
5051 int ret
= device
->ws
->import_syncobj(device
->ws
, fd
, &syncobj_handle
);
5053 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5056 device
->ws
->destroy_syncobj(device
->ws
, *syncobj
);
5058 *syncobj
= syncobj_handle
;
5064 static VkResult
radv_import_sync_fd(struct radv_device
*device
,
5068 /* If we create a syncobj we do it locally so that if we have an error, we don't
5069 * leave a syncobj in an undetermined state in the fence. */
5070 uint32_t syncobj_handle
= *syncobj
;
5071 if (!syncobj_handle
) {
5072 int ret
= device
->ws
->create_syncobj(device
->ws
, &syncobj_handle
);
5074 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5079 device
->ws
->signal_syncobj(device
->ws
, syncobj_handle
);
5081 int ret
= device
->ws
->import_syncobj_from_sync_file(device
->ws
, syncobj_handle
, fd
);
5083 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5086 *syncobj
= syncobj_handle
;
5093 VkResult
radv_ImportSemaphoreFdKHR(VkDevice _device
,
5094 const VkImportSemaphoreFdInfoKHR
*pImportSemaphoreFdInfo
)
5096 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5097 RADV_FROM_HANDLE(radv_semaphore
, sem
, pImportSemaphoreFdInfo
->semaphore
);
5098 uint32_t *syncobj_dst
= NULL
;
5100 if (pImportSemaphoreFdInfo
->flags
& VK_SEMAPHORE_IMPORT_TEMPORARY_BIT
) {
5101 syncobj_dst
= &sem
->temp_syncobj
;
5103 syncobj_dst
= &sem
->syncobj
;
5106 switch(pImportSemaphoreFdInfo
->handleType
) {
5107 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5108 return radv_import_opaque_fd(device
, pImportSemaphoreFdInfo
->fd
, syncobj_dst
);
5109 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
5110 return radv_import_sync_fd(device
, pImportSemaphoreFdInfo
->fd
, syncobj_dst
);
5112 unreachable("Unhandled semaphore handle type");
5116 VkResult
radv_GetSemaphoreFdKHR(VkDevice _device
,
5117 const VkSemaphoreGetFdInfoKHR
*pGetFdInfo
,
5120 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5121 RADV_FROM_HANDLE(radv_semaphore
, sem
, pGetFdInfo
->semaphore
);
5123 uint32_t syncobj_handle
;
5125 if (sem
->temp_syncobj
)
5126 syncobj_handle
= sem
->temp_syncobj
;
5128 syncobj_handle
= sem
->syncobj
;
5130 switch(pGetFdInfo
->handleType
) {
5131 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5132 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
5134 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
5135 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
5137 if (sem
->temp_syncobj
) {
5138 close (sem
->temp_syncobj
);
5139 sem
->temp_syncobj
= 0;
5141 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
5146 unreachable("Unhandled semaphore handle type");
5150 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5154 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5155 VkPhysicalDevice physicalDevice
,
5156 const VkPhysicalDeviceExternalSemaphoreInfo
*pExternalSemaphoreInfo
,
5157 VkExternalSemaphoreProperties
*pExternalSemaphoreProperties
)
5159 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
5161 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5162 if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
5163 (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
||
5164 pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
)) {
5165 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
5166 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
5167 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
5168 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
5169 } else if (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
) {
5170 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
5171 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
5172 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
5173 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
5175 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= 0;
5176 pExternalSemaphoreProperties
->compatibleHandleTypes
= 0;
5177 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= 0;
5181 VkResult
radv_ImportFenceFdKHR(VkDevice _device
,
5182 const VkImportFenceFdInfoKHR
*pImportFenceFdInfo
)
5184 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5185 RADV_FROM_HANDLE(radv_fence
, fence
, pImportFenceFdInfo
->fence
);
5186 uint32_t *syncobj_dst
= NULL
;
5189 if (pImportFenceFdInfo
->flags
& VK_FENCE_IMPORT_TEMPORARY_BIT
) {
5190 syncobj_dst
= &fence
->temp_syncobj
;
5192 syncobj_dst
= &fence
->syncobj
;
5195 switch(pImportFenceFdInfo
->handleType
) {
5196 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5197 return radv_import_opaque_fd(device
, pImportFenceFdInfo
->fd
, syncobj_dst
);
5198 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
5199 return radv_import_sync_fd(device
, pImportFenceFdInfo
->fd
, syncobj_dst
);
5201 unreachable("Unhandled fence handle type");
5205 VkResult
radv_GetFenceFdKHR(VkDevice _device
,
5206 const VkFenceGetFdInfoKHR
*pGetFdInfo
,
5209 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5210 RADV_FROM_HANDLE(radv_fence
, fence
, pGetFdInfo
->fence
);
5212 uint32_t syncobj_handle
;
5214 if (fence
->temp_syncobj
)
5215 syncobj_handle
= fence
->temp_syncobj
;
5217 syncobj_handle
= fence
->syncobj
;
5219 switch(pGetFdInfo
->handleType
) {
5220 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5221 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
5223 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
5224 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
5226 if (fence
->temp_syncobj
) {
5227 close (fence
->temp_syncobj
);
5228 fence
->temp_syncobj
= 0;
5230 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
5235 unreachable("Unhandled fence handle type");
5239 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5243 void radv_GetPhysicalDeviceExternalFenceProperties(
5244 VkPhysicalDevice physicalDevice
,
5245 const VkPhysicalDeviceExternalFenceInfo
*pExternalFenceInfo
,
5246 VkExternalFenceProperties
*pExternalFenceProperties
)
5248 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
5250 if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
5251 (pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
||
5252 pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
)) {
5253 pExternalFenceProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
5254 pExternalFenceProperties
->compatibleHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
5255 pExternalFenceProperties
->externalFenceFeatures
= VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT
|
5256 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
5258 pExternalFenceProperties
->exportFromImportedHandleTypes
= 0;
5259 pExternalFenceProperties
->compatibleHandleTypes
= 0;
5260 pExternalFenceProperties
->externalFenceFeatures
= 0;
5265 radv_CreateDebugReportCallbackEXT(VkInstance _instance
,
5266 const VkDebugReportCallbackCreateInfoEXT
* pCreateInfo
,
5267 const VkAllocationCallbacks
* pAllocator
,
5268 VkDebugReportCallbackEXT
* pCallback
)
5270 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
5271 return vk_create_debug_report_callback(&instance
->debug_report_callbacks
,
5272 pCreateInfo
, pAllocator
, &instance
->alloc
,
5277 radv_DestroyDebugReportCallbackEXT(VkInstance _instance
,
5278 VkDebugReportCallbackEXT _callback
,
5279 const VkAllocationCallbacks
* pAllocator
)
5281 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
5282 vk_destroy_debug_report_callback(&instance
->debug_report_callbacks
,
5283 _callback
, pAllocator
, &instance
->alloc
);
5287 radv_DebugReportMessageEXT(VkInstance _instance
,
5288 VkDebugReportFlagsEXT flags
,
5289 VkDebugReportObjectTypeEXT objectType
,
5292 int32_t messageCode
,
5293 const char* pLayerPrefix
,
5294 const char* pMessage
)
5296 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
5297 vk_debug_report(&instance
->debug_report_callbacks
, flags
, objectType
,
5298 object
, location
, messageCode
, pLayerPrefix
, pMessage
);
5302 radv_GetDeviceGroupPeerMemoryFeatures(
5305 uint32_t localDeviceIndex
,
5306 uint32_t remoteDeviceIndex
,
5307 VkPeerMemoryFeatureFlags
* pPeerMemoryFeatures
)
5309 assert(localDeviceIndex
== remoteDeviceIndex
);
5311 *pPeerMemoryFeatures
= VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT
|
5312 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT
|
5313 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT
|
5314 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT
;
5317 static const VkTimeDomainEXT radv_time_domains
[] = {
5318 VK_TIME_DOMAIN_DEVICE_EXT
,
5319 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
,
5320 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
,
5323 VkResult
radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5324 VkPhysicalDevice physicalDevice
,
5325 uint32_t *pTimeDomainCount
,
5326 VkTimeDomainEXT
*pTimeDomains
)
5329 VK_OUTARRAY_MAKE(out
, pTimeDomains
, pTimeDomainCount
);
5331 for (d
= 0; d
< ARRAY_SIZE(radv_time_domains
); d
++) {
5332 vk_outarray_append(&out
, i
) {
5333 *i
= radv_time_domains
[d
];
5337 return vk_outarray_status(&out
);
5341 radv_clock_gettime(clockid_t clock_id
)
5343 struct timespec current
;
5346 ret
= clock_gettime(clock_id
, ¤t
);
5347 if (ret
< 0 && clock_id
== CLOCK_MONOTONIC_RAW
)
5348 ret
= clock_gettime(CLOCK_MONOTONIC
, ¤t
);
5352 return (uint64_t) current
.tv_sec
* 1000000000ULL + current
.tv_nsec
;
5355 VkResult
radv_GetCalibratedTimestampsEXT(
5357 uint32_t timestampCount
,
5358 const VkCalibratedTimestampInfoEXT
*pTimestampInfos
,
5359 uint64_t *pTimestamps
,
5360 uint64_t *pMaxDeviation
)
5362 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5363 uint32_t clock_crystal_freq
= device
->physical_device
->rad_info
.clock_crystal_freq
;
5365 uint64_t begin
, end
;
5366 uint64_t max_clock_period
= 0;
5368 begin
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
5370 for (d
= 0; d
< timestampCount
; d
++) {
5371 switch (pTimestampInfos
[d
].timeDomain
) {
5372 case VK_TIME_DOMAIN_DEVICE_EXT
:
5373 pTimestamps
[d
] = device
->ws
->query_value(device
->ws
,
5375 uint64_t device_period
= DIV_ROUND_UP(1000000, clock_crystal_freq
);
5376 max_clock_period
= MAX2(max_clock_period
, device_period
);
5378 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
:
5379 pTimestamps
[d
] = radv_clock_gettime(CLOCK_MONOTONIC
);
5380 max_clock_period
= MAX2(max_clock_period
, 1);
5383 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
:
5384 pTimestamps
[d
] = begin
;
5392 end
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
5395 * The maximum deviation is the sum of the interval over which we
5396 * perform the sampling and the maximum period of any sampled
5397 * clock. That's because the maximum skew between any two sampled
5398 * clock edges is when the sampled clock with the largest period is
5399 * sampled at the end of that period but right at the beginning of the
5400 * sampling interval and some other clock is sampled right at the
5401 * begining of its sampling period and right at the end of the
5402 * sampling interval. Let's assume the GPU has the longest clock
5403 * period and that the application is sampling GPU and monotonic:
5406 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5407 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5411 * GPU -----_____-----_____-----_____-----_____
5414 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5415 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5417 * Interval <----------------->
5418 * Deviation <-------------------------->
5422 * m = read(monotonic) 2
5425 * We round the sample interval up by one tick to cover sampling error
5426 * in the interval clock
5429 uint64_t sample_interval
= end
- begin
+ 1;
5431 *pMaxDeviation
= sample_interval
+ max_clock_period
;
5436 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
5437 VkPhysicalDevice physicalDevice
,
5438 VkSampleCountFlagBits samples
,
5439 VkMultisamplePropertiesEXT
* pMultisampleProperties
)
5441 if (samples
& (VK_SAMPLE_COUNT_2_BIT
|
5442 VK_SAMPLE_COUNT_4_BIT
|
5443 VK_SAMPLE_COUNT_8_BIT
)) {
5444 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2, 2 };
5446 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 0, 0 };