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118f8f2b32ad26ebd7cf871081cf082450b75735
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "dirent.h"
29 #include <errno.h>
30 #include <fcntl.h>
31 #include <linux/audit.h>
32 #include <linux/bpf.h>
33 #include <linux/filter.h>
34 #include <linux/seccomp.h>
35 #include <linux/unistd.h>
36 #include <stdbool.h>
37 #include <stddef.h>
38 #include <stdio.h>
39 #include <string.h>
40 #include <sys/prctl.h>
41 #include <sys/wait.h>
42 #include <unistd.h>
43 #include <fcntl.h>
44
45 #include "radv_debug.h"
46 #include "radv_private.h"
47 #include "radv_shader.h"
48 #include "radv_cs.h"
49 #include "util/disk_cache.h"
50 #include "vk_util.h"
51 #include <xf86drm.h>
52 #include <amdgpu.h>
53 #include "drm-uapi/amdgpu_drm.h"
54 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
55 #include "winsys/null/radv_null_winsys_public.h"
56 #include "ac_llvm_util.h"
57 #include "vk_format.h"
58 #include "sid.h"
59 #include "git_sha1.h"
60 #include "util/build_id.h"
61 #include "util/debug.h"
62 #include "util/mesa-sha1.h"
63 #include "util/timespec.h"
64 #include "util/u_atomic.h"
65 #include "compiler/glsl_types.h"
66 #include "util/xmlpool.h"
67
68 static struct radv_timeline_point *
69 radv_timeline_find_point_at_least_locked(struct radv_device *device,
70 struct radv_timeline *timeline,
71 uint64_t p);
72
73 static struct radv_timeline_point *
74 radv_timeline_add_point_locked(struct radv_device *device,
75 struct radv_timeline *timeline,
76 uint64_t p);
77
78 static void
79 radv_timeline_trigger_waiters_locked(struct radv_timeline *timeline,
80 struct list_head *processing_list);
81
82 static
83 void radv_destroy_semaphore_part(struct radv_device *device,
84 struct radv_semaphore_part *part);
85
86 static int
87 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
88 {
89 struct mesa_sha1 ctx;
90 unsigned char sha1[20];
91 unsigned ptr_size = sizeof(void*);
92
93 memset(uuid, 0, VK_UUID_SIZE);
94 _mesa_sha1_init(&ctx);
95
96 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
97 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
98 return -1;
99
100 _mesa_sha1_update(&ctx, &family, sizeof(family));
101 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
102 _mesa_sha1_final(&ctx, sha1);
103
104 memcpy(uuid, sha1, VK_UUID_SIZE);
105 return 0;
106 }
107
108 static void
109 radv_get_driver_uuid(void *uuid)
110 {
111 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
112 }
113
114 static void
115 radv_get_device_uuid(struct radeon_info *info, void *uuid)
116 {
117 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
118 }
119
120 static uint64_t
121 radv_get_visible_vram_size(struct radv_physical_device *device)
122 {
123 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
124 }
125
126 static uint64_t
127 radv_get_vram_size(struct radv_physical_device *device)
128 {
129 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
130 }
131
132 static void
133 radv_physical_device_init_mem_types(struct radv_physical_device *device)
134 {
135 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
136 uint64_t vram_size = radv_get_vram_size(device);
137 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
138 device->memory_properties.memoryHeapCount = 0;
139 if (vram_size > 0) {
140 vram_index = device->memory_properties.memoryHeapCount++;
141 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
142 .size = vram_size,
143 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
144 };
145 }
146
147 if (device->rad_info.gart_size > 0) {
148 gart_index = device->memory_properties.memoryHeapCount++;
149 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
150 .size = device->rad_info.gart_size,
151 .flags = 0,
152 };
153 }
154
155 if (visible_vram_size) {
156 visible_vram_index = device->memory_properties.memoryHeapCount++;
157 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
158 .size = visible_vram_size,
159 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
160 };
161 }
162
163 unsigned type_count = 0;
164
165 if (device->rad_info.has_dedicated_vram) {
166 if (vram_index >= 0) {
167 device->memory_domains[type_count] = RADEON_DOMAIN_VRAM;
168 device->memory_flags[type_count] = RADEON_FLAG_NO_CPU_ACCESS;
169 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
170 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
171 .heapIndex = vram_index,
172 };
173 }
174 } else {
175 if (visible_vram_index >= 0) {
176 device->memory_domains[type_count] = RADEON_DOMAIN_VRAM;
177 device->memory_flags[type_count] = RADEON_FLAG_NO_CPU_ACCESS;
178 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
179 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
180 .heapIndex = visible_vram_index,
181 };
182 }
183 }
184
185 if (gart_index >= 0) {
186 device->memory_domains[type_count] = RADEON_DOMAIN_GTT;
187 device->memory_flags[type_count] = RADEON_FLAG_GTT_WC | RADEON_FLAG_CPU_ACCESS;
188 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
189 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
190 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
191 .heapIndex = gart_index,
192 };
193 }
194 if (visible_vram_index >= 0) {
195 device->memory_domains[type_count] = RADEON_DOMAIN_VRAM;
196 device->memory_flags[type_count] = RADEON_FLAG_CPU_ACCESS;
197 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
198 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
199 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
200 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
201 .heapIndex = visible_vram_index,
202 };
203 }
204
205 if (gart_index >= 0) {
206 device->memory_domains[type_count] = RADEON_DOMAIN_GTT;
207 device->memory_flags[type_count] = RADEON_FLAG_CPU_ACCESS;
208 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
209 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
210 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
211 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
212 .heapIndex = gart_index,
213 };
214 }
215 device->memory_properties.memoryTypeCount = type_count;
216
217 if (device->rad_info.has_l2_uncached) {
218 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
219 VkMemoryType mem_type = device->memory_properties.memoryTypes[i];
220
221 if ((mem_type.propertyFlags & (VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
222 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT)) ||
223 mem_type.propertyFlags == VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT) {
224
225 VkMemoryPropertyFlags property_flags = mem_type.propertyFlags |
226 VK_MEMORY_PROPERTY_DEVICE_COHERENT_BIT_AMD |
227 VK_MEMORY_PROPERTY_DEVICE_UNCACHED_BIT_AMD;
228
229 device->memory_domains[type_count] = device->memory_domains[i];
230 device->memory_flags[type_count] = device->memory_flags[i] | RADEON_FLAG_VA_UNCACHED;
231 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
232 .propertyFlags = property_flags,
233 .heapIndex = mem_type.heapIndex,
234 };
235 }
236 }
237 device->memory_properties.memoryTypeCount = type_count;
238 }
239 }
240
241 static VkResult
242 radv_physical_device_init(struct radv_physical_device *device,
243 struct radv_instance *instance,
244 drmDevicePtr drm_device)
245 {
246 VkResult result;
247 int fd = -1;
248 int master_fd = -1;
249
250 if (drm_device) {
251 const char *path = drm_device->nodes[DRM_NODE_RENDER];
252 drmVersionPtr version;
253
254 fd = open(path, O_RDWR | O_CLOEXEC);
255 if (fd < 0) {
256 if (instance->debug_flags & RADV_DEBUG_STARTUP)
257 radv_logi("Could not open device '%s'", path);
258
259 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
260 }
261
262 version = drmGetVersion(fd);
263 if (!version) {
264 close(fd);
265
266 if (instance->debug_flags & RADV_DEBUG_STARTUP)
267 radv_logi("Could not get the kernel driver version for device '%s'", path);
268
269 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
270 "failed to get version %s: %m", path);
271 }
272
273 if (strcmp(version->name, "amdgpu")) {
274 drmFreeVersion(version);
275 close(fd);
276
277 if (instance->debug_flags & RADV_DEBUG_STARTUP)
278 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
279
280 return VK_ERROR_INCOMPATIBLE_DRIVER;
281 }
282 drmFreeVersion(version);
283
284 if (instance->debug_flags & RADV_DEBUG_STARTUP)
285 radv_logi("Found compatible device '%s'.", path);
286 }
287
288 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
289 device->instance = instance;
290
291 if (drm_device) {
292 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
293 instance->perftest_flags);
294 } else {
295 device->ws = radv_null_winsys_create();
296 }
297
298 if (!device->ws) {
299 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
300 goto fail;
301 }
302
303 if (drm_device && instance->enabled_extensions.KHR_display) {
304 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
305 if (master_fd >= 0) {
306 uint32_t accel_working = 0;
307 struct drm_amdgpu_info request = {
308 .return_pointer = (uintptr_t)&accel_working,
309 .return_size = sizeof(accel_working),
310 .query = AMDGPU_INFO_ACCEL_WORKING
311 };
312
313 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
314 close(master_fd);
315 master_fd = -1;
316 }
317 }
318 }
319
320 device->master_fd = master_fd;
321 device->local_fd = fd;
322 device->ws->query_info(device->ws, &device->rad_info);
323
324 device->use_aco = instance->perftest_flags & RADV_PERFTEST_ACO;
325
326 snprintf(device->name, sizeof(device->name),
327 "AMD RADV%s %s (LLVM " MESA_LLVM_VERSION_STRING ")", device->use_aco ? "/ACO" : "",
328 device->rad_info.name);
329
330 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
331 device->ws->destroy(device->ws);
332 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
333 "cannot generate UUID");
334 goto fail;
335 }
336
337 /* These flags affect shader compilation. */
338 uint64_t shader_env_flags = (device->use_aco ? 0x2 : 0);
339
340 /* The gpu id is already embedded in the uuid so we just pass "radv"
341 * when creating the cache.
342 */
343 char buf[VK_UUID_SIZE * 2 + 1];
344 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
345 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
346
347 if (device->rad_info.chip_class < GFX8)
348 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
349
350 radv_get_driver_uuid(&device->driver_uuid);
351 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
352
353 device->out_of_order_rast_allowed = device->rad_info.has_out_of_order_rast &&
354 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
355
356 device->dcc_msaa_allowed =
357 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
358
359 device->use_shader_ballot = (device->use_aco && device->rad_info.chip_class >= GFX8) ||
360 (device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT);
361
362 device->use_ngg = device->rad_info.chip_class >= GFX10 &&
363 device->rad_info.family != CHIP_NAVI14 &&
364 !(device->instance->debug_flags & RADV_DEBUG_NO_NGG);
365
366 /* TODO: Implement NGG GS with ACO. */
367 device->use_ngg_gs = device->use_ngg && !device->use_aco;
368 device->use_ngg_streamout = false;
369
370 /* Determine the number of threads per wave for all stages. */
371 device->cs_wave_size = 64;
372 device->ps_wave_size = 64;
373 device->ge_wave_size = 64;
374
375 if (device->rad_info.chip_class >= GFX10) {
376 if (device->instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32)
377 device->cs_wave_size = 32;
378
379 /* For pixel shaders, wave64 is recommanded. */
380 if (device->instance->perftest_flags & RADV_PERFTEST_PS_WAVE_32)
381 device->ps_wave_size = 32;
382
383 if (device->instance->perftest_flags & RADV_PERFTEST_GE_WAVE_32)
384 device->ge_wave_size = 32;
385 }
386
387 radv_physical_device_init_mem_types(device);
388 radv_fill_device_extension_table(device, &device->supported_extensions);
389
390 if (drm_device)
391 device->bus_info = *drm_device->businfo.pci;
392
393 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
394 ac_print_gpu_info(&device->rad_info);
395
396 /* The WSI is structured as a layer on top of the driver, so this has
397 * to be the last part of initialization (at least until we get other
398 * semi-layers).
399 */
400 result = radv_init_wsi(device);
401 if (result != VK_SUCCESS) {
402 device->ws->destroy(device->ws);
403 vk_error(instance, result);
404 goto fail;
405 }
406
407 return VK_SUCCESS;
408
409 fail:
410 close(fd);
411 if (master_fd != -1)
412 close(master_fd);
413 return result;
414 }
415
416 static void
417 radv_physical_device_finish(struct radv_physical_device *device)
418 {
419 radv_finish_wsi(device);
420 device->ws->destroy(device->ws);
421 disk_cache_destroy(device->disk_cache);
422 close(device->local_fd);
423 if (device->master_fd != -1)
424 close(device->master_fd);
425 }
426
427 static void *
428 default_alloc_func(void *pUserData, size_t size, size_t align,
429 VkSystemAllocationScope allocationScope)
430 {
431 return malloc(size);
432 }
433
434 static void *
435 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
436 size_t align, VkSystemAllocationScope allocationScope)
437 {
438 return realloc(pOriginal, size);
439 }
440
441 static void
442 default_free_func(void *pUserData, void *pMemory)
443 {
444 free(pMemory);
445 }
446
447 static const VkAllocationCallbacks default_alloc = {
448 .pUserData = NULL,
449 .pfnAllocation = default_alloc_func,
450 .pfnReallocation = default_realloc_func,
451 .pfnFree = default_free_func,
452 };
453
454 static const struct debug_control radv_debug_options[] = {
455 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
456 {"nodcc", RADV_DEBUG_NO_DCC},
457 {"shaders", RADV_DEBUG_DUMP_SHADERS},
458 {"nocache", RADV_DEBUG_NO_CACHE},
459 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
460 {"nohiz", RADV_DEBUG_NO_HIZ},
461 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
462 {"allbos", RADV_DEBUG_ALL_BOS},
463 {"noibs", RADV_DEBUG_NO_IBS},
464 {"spirv", RADV_DEBUG_DUMP_SPIRV},
465 {"vmfaults", RADV_DEBUG_VM_FAULTS},
466 {"zerovram", RADV_DEBUG_ZERO_VRAM},
467 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
468 {"preoptir", RADV_DEBUG_PREOPTIR},
469 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
470 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
471 {"info", RADV_DEBUG_INFO},
472 {"errors", RADV_DEBUG_ERRORS},
473 {"startup", RADV_DEBUG_STARTUP},
474 {"checkir", RADV_DEBUG_CHECKIR},
475 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
476 {"nobinning", RADV_DEBUG_NOBINNING},
477 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT},
478 {"nongg", RADV_DEBUG_NO_NGG},
479 {"noshaderballot", RADV_DEBUG_NO_SHADER_BALLOT},
480 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS},
481 {"metashaders", RADV_DEBUG_DUMP_META_SHADERS},
482 {"nomemorycache", RADV_DEBUG_NO_MEMORY_CACHE},
483 {NULL, 0}
484 };
485
486 const char *
487 radv_get_debug_option_name(int id)
488 {
489 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
490 return radv_debug_options[id].string;
491 }
492
493 static const struct debug_control radv_perftest_options[] = {
494 {"localbos", RADV_PERFTEST_LOCAL_BOS},
495 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
496 {"bolist", RADV_PERFTEST_BO_LIST},
497 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT},
498 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
499 {"cswave32", RADV_PERFTEST_CS_WAVE_32},
500 {"pswave32", RADV_PERFTEST_PS_WAVE_32},
501 {"gewave32", RADV_PERFTEST_GE_WAVE_32},
502 {"dfsm", RADV_PERFTEST_DFSM},
503 {"aco", RADV_PERFTEST_ACO},
504 {NULL, 0}
505 };
506
507 const char *
508 radv_get_perftest_option_name(int id)
509 {
510 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
511 return radv_perftest_options[id].string;
512 }
513
514 static void
515 radv_handle_per_app_options(struct radv_instance *instance,
516 const VkApplicationInfo *info)
517 {
518 const char *name = info ? info->pApplicationName : NULL;
519
520 if (!name)
521 return;
522
523 if (!strcmp(name, "DOOM_VFR")) {
524 /* Work around a Doom VFR game bug */
525 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
526 } else if (!strcmp(name, "MonsterHunterWorld.exe")) {
527 /* Workaround for a WaW hazard when LLVM moves/merges
528 * load/store memory operations.
529 * See https://reviews.llvm.org/D61313
530 */
531 if (LLVM_VERSION_MAJOR < 9)
532 instance->debug_flags |= RADV_DEBUG_NO_LOAD_STORE_OPT;
533 } else if (!strcmp(name, "Wolfenstein: Youngblood")) {
534 if (!(instance->debug_flags & RADV_DEBUG_NO_SHADER_BALLOT) &&
535 !(instance->perftest_flags & RADV_PERFTEST_ACO)) {
536 /* Force enable VK_AMD_shader_ballot because it looks
537 * safe and it gives a nice boost (+20% on Vega 56 at
538 * this time). It also prevents corruption on LLVM.
539 */
540 instance->perftest_flags |= RADV_PERFTEST_SHADER_BALLOT;
541 }
542 } else if (!strcmp(name, "Fledge")) {
543 /*
544 * Zero VRAM for "The Surge 2"
545 *
546 * This avoid a hang when when rendering any level. Likely
547 * uninitialized data in an indirect draw.
548 */
549 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
550 } else if (!strcmp(name, "No Man's Sky")) {
551 /* Work around a NMS game bug */
552 instance->debug_flags |= RADV_DEBUG_DISCARD_TO_DEMOTE;
553 }
554 }
555
556 static const char radv_dri_options_xml[] =
557 DRI_CONF_BEGIN
558 DRI_CONF_SECTION_PERFORMANCE
559 DRI_CONF_ADAPTIVE_SYNC("true")
560 DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0)
561 DRI_CONF_VK_X11_STRICT_IMAGE_COUNT("false")
562 DRI_CONF_SECTION_END
563
564 DRI_CONF_SECTION_DEBUG
565 DRI_CONF_VK_WSI_FORCE_BGRA8_UNORM_FIRST("false")
566 DRI_CONF_SECTION_END
567 DRI_CONF_END;
568
569 static void radv_init_dri_options(struct radv_instance *instance)
570 {
571 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
572 driParseConfigFiles(&instance->dri_options,
573 &instance->available_dri_options,
574 0, "radv", NULL,
575 instance->engineName,
576 instance->engineVersion);
577 }
578
579 VkResult radv_CreateInstance(
580 const VkInstanceCreateInfo* pCreateInfo,
581 const VkAllocationCallbacks* pAllocator,
582 VkInstance* pInstance)
583 {
584 struct radv_instance *instance;
585 VkResult result;
586
587 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
588 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
589 if (!instance)
590 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
591
592 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
593
594 if (pAllocator)
595 instance->alloc = *pAllocator;
596 else
597 instance->alloc = default_alloc;
598
599 if (pCreateInfo->pApplicationInfo) {
600 const VkApplicationInfo *app = pCreateInfo->pApplicationInfo;
601
602 instance->engineName =
603 vk_strdup(&instance->alloc, app->pEngineName,
604 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
605 instance->engineVersion = app->engineVersion;
606 instance->apiVersion = app->apiVersion;
607 }
608
609 if (instance->apiVersion == 0)
610 instance->apiVersion = VK_API_VERSION_1_0;
611
612 instance->physicalDeviceCount = -1;
613
614 /* Get secure compile thread count. NOTE: We cap this at 32 */
615 #define MAX_SC_PROCS 32
616 char *num_sc_threads = getenv("RADV_SECURE_COMPILE_THREADS");
617 if (num_sc_threads)
618 instance->num_sc_threads = MIN2(strtoul(num_sc_threads, NULL, 10), MAX_SC_PROCS);
619
620 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
621 radv_debug_options);
622
623 /* Disable memory cache when secure compile is set */
624 if (radv_device_use_secure_compile(instance))
625 instance->debug_flags |= RADV_DEBUG_NO_MEMORY_CACHE;
626
627 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
628 radv_perftest_options);
629
630 if (instance->perftest_flags & RADV_PERFTEST_ACO)
631 fprintf(stderr, "WARNING: Experimental compiler backend enabled. Here be dragons! Incorrect rendering, GPU hangs and/or resets are likely\n");
632
633 if (instance->debug_flags & RADV_DEBUG_STARTUP)
634 radv_logi("Created an instance");
635
636 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
637 int idx;
638 for (idx = 0; idx < RADV_INSTANCE_EXTENSION_COUNT; idx++) {
639 if (!strcmp(pCreateInfo->ppEnabledExtensionNames[i],
640 radv_instance_extensions[idx].extensionName))
641 break;
642 }
643
644 if (idx >= RADV_INSTANCE_EXTENSION_COUNT ||
645 !radv_supported_instance_extensions.extensions[idx]) {
646 vk_free2(&default_alloc, pAllocator, instance);
647 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
648 }
649
650 instance->enabled_extensions.extensions[idx] = true;
651 }
652
653 bool unchecked = instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS;
654
655 for (unsigned i = 0; i < ARRAY_SIZE(instance->dispatch.entrypoints); i++) {
656 /* Vulkan requires that entrypoints for extensions which have
657 * not been enabled must not be advertised.
658 */
659 if (!unchecked &&
660 !radv_instance_entrypoint_is_enabled(i, instance->apiVersion,
661 &instance->enabled_extensions)) {
662 instance->dispatch.entrypoints[i] = NULL;
663 } else {
664 instance->dispatch.entrypoints[i] =
665 radv_instance_dispatch_table.entrypoints[i];
666 }
667 }
668
669 for (unsigned i = 0; i < ARRAY_SIZE(instance->physical_device_dispatch.entrypoints); i++) {
670 /* Vulkan requires that entrypoints for extensions which have
671 * not been enabled must not be advertised.
672 */
673 if (!unchecked &&
674 !radv_physical_device_entrypoint_is_enabled(i, instance->apiVersion,
675 &instance->enabled_extensions)) {
676 instance->physical_device_dispatch.entrypoints[i] = NULL;
677 } else {
678 instance->physical_device_dispatch.entrypoints[i] =
679 radv_physical_device_dispatch_table.entrypoints[i];
680 }
681 }
682
683 for (unsigned i = 0; i < ARRAY_SIZE(instance->device_dispatch.entrypoints); i++) {
684 /* Vulkan requires that entrypoints for extensions which have
685 * not been enabled must not be advertised.
686 */
687 if (!unchecked &&
688 !radv_device_entrypoint_is_enabled(i, instance->apiVersion,
689 &instance->enabled_extensions, NULL)) {
690 instance->device_dispatch.entrypoints[i] = NULL;
691 } else {
692 instance->device_dispatch.entrypoints[i] =
693 radv_device_dispatch_table.entrypoints[i];
694 }
695 }
696
697 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
698 if (result != VK_SUCCESS) {
699 vk_free2(&default_alloc, pAllocator, instance);
700 return vk_error(instance, result);
701 }
702
703 glsl_type_singleton_init_or_ref();
704
705 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
706
707 radv_init_dri_options(instance);
708 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
709
710 *pInstance = radv_instance_to_handle(instance);
711
712 return VK_SUCCESS;
713 }
714
715 void radv_DestroyInstance(
716 VkInstance _instance,
717 const VkAllocationCallbacks* pAllocator)
718 {
719 RADV_FROM_HANDLE(radv_instance, instance, _instance);
720
721 if (!instance)
722 return;
723
724 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
725 radv_physical_device_finish(instance->physicalDevices + i);
726 }
727
728 vk_free(&instance->alloc, instance->engineName);
729
730 VG(VALGRIND_DESTROY_MEMPOOL(instance));
731
732 glsl_type_singleton_decref();
733
734 driDestroyOptionCache(&instance->dri_options);
735 driDestroyOptionInfo(&instance->available_dri_options);
736
737 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
738
739 vk_free(&instance->alloc, instance);
740 }
741
742 static VkResult
743 radv_enumerate_physical_devices(struct radv_instance *instance)
744 {
745 /* TODO: Check for more devices ? */
746 drmDevicePtr devices[8];
747 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
748 int max_devices;
749
750 instance->physicalDeviceCount = 0;
751
752 if (getenv("RADV_FORCE_FAMILY")) {
753 /* When RADV_FORCE_FAMILY is set, the driver creates a nul
754 * device that allows to test the compiler without having an
755 * AMDGPU instance.
756 */
757 result = radv_physical_device_init(instance->physicalDevices +
758 instance->physicalDeviceCount,
759 instance, NULL);
760
761 ++instance->physicalDeviceCount;
762 return VK_SUCCESS;
763 }
764
765 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
766
767 if (instance->debug_flags & RADV_DEBUG_STARTUP)
768 radv_logi("Found %d drm nodes", max_devices);
769
770 if (max_devices < 1)
771 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
772
773 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
774 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
775 devices[i]->bustype == DRM_BUS_PCI &&
776 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
777
778 result = radv_physical_device_init(instance->physicalDevices +
779 instance->physicalDeviceCount,
780 instance,
781 devices[i]);
782 if (result == VK_SUCCESS)
783 ++instance->physicalDeviceCount;
784 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
785 break;
786 }
787 }
788 drmFreeDevices(devices, max_devices);
789
790 return result;
791 }
792
793 VkResult radv_EnumeratePhysicalDevices(
794 VkInstance _instance,
795 uint32_t* pPhysicalDeviceCount,
796 VkPhysicalDevice* pPhysicalDevices)
797 {
798 RADV_FROM_HANDLE(radv_instance, instance, _instance);
799 VkResult result;
800
801 if (instance->physicalDeviceCount < 0) {
802 result = radv_enumerate_physical_devices(instance);
803 if (result != VK_SUCCESS &&
804 result != VK_ERROR_INCOMPATIBLE_DRIVER)
805 return result;
806 }
807
808 if (!pPhysicalDevices) {
809 *pPhysicalDeviceCount = instance->physicalDeviceCount;
810 } else {
811 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
812 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
813 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
814 }
815
816 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
817 : VK_SUCCESS;
818 }
819
820 VkResult radv_EnumeratePhysicalDeviceGroups(
821 VkInstance _instance,
822 uint32_t* pPhysicalDeviceGroupCount,
823 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
824 {
825 RADV_FROM_HANDLE(radv_instance, instance, _instance);
826 VkResult result;
827
828 if (instance->physicalDeviceCount < 0) {
829 result = radv_enumerate_physical_devices(instance);
830 if (result != VK_SUCCESS &&
831 result != VK_ERROR_INCOMPATIBLE_DRIVER)
832 return result;
833 }
834
835 if (!pPhysicalDeviceGroupProperties) {
836 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
837 } else {
838 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
839 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
840 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
841 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
842 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
843 }
844 }
845 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
846 : VK_SUCCESS;
847 }
848
849 void radv_GetPhysicalDeviceFeatures(
850 VkPhysicalDevice physicalDevice,
851 VkPhysicalDeviceFeatures* pFeatures)
852 {
853 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
854 memset(pFeatures, 0, sizeof(*pFeatures));
855
856 *pFeatures = (VkPhysicalDeviceFeatures) {
857 .robustBufferAccess = true,
858 .fullDrawIndexUint32 = true,
859 .imageCubeArray = true,
860 .independentBlend = true,
861 .geometryShader = true,
862 .tessellationShader = true,
863 .sampleRateShading = true,
864 .dualSrcBlend = true,
865 .logicOp = true,
866 .multiDrawIndirect = true,
867 .drawIndirectFirstInstance = true,
868 .depthClamp = true,
869 .depthBiasClamp = true,
870 .fillModeNonSolid = true,
871 .depthBounds = true,
872 .wideLines = true,
873 .largePoints = true,
874 .alphaToOne = true,
875 .multiViewport = true,
876 .samplerAnisotropy = true,
877 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
878 .textureCompressionASTC_LDR = false,
879 .textureCompressionBC = true,
880 .occlusionQueryPrecise = true,
881 .pipelineStatisticsQuery = true,
882 .vertexPipelineStoresAndAtomics = true,
883 .fragmentStoresAndAtomics = true,
884 .shaderTessellationAndGeometryPointSize = true,
885 .shaderImageGatherExtended = true,
886 .shaderStorageImageExtendedFormats = true,
887 .shaderStorageImageMultisample = true,
888 .shaderUniformBufferArrayDynamicIndexing = true,
889 .shaderSampledImageArrayDynamicIndexing = true,
890 .shaderStorageBufferArrayDynamicIndexing = true,
891 .shaderStorageImageArrayDynamicIndexing = true,
892 .shaderStorageImageReadWithoutFormat = true,
893 .shaderStorageImageWriteWithoutFormat = true,
894 .shaderClipDistance = true,
895 .shaderCullDistance = true,
896 .shaderFloat64 = true,
897 .shaderInt64 = true,
898 .shaderInt16 = !pdevice->use_aco || pdevice->rad_info.chip_class >= GFX8,
899 .sparseBinding = true,
900 .variableMultisampleRate = true,
901 .inheritedQueries = true,
902 };
903 }
904
905 void radv_GetPhysicalDeviceFeatures2(
906 VkPhysicalDevice physicalDevice,
907 VkPhysicalDeviceFeatures2 *pFeatures)
908 {
909 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
910 vk_foreach_struct(ext, pFeatures->pNext) {
911 switch (ext->sType) {
912 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
913 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
914 features->variablePointersStorageBuffer = true;
915 features->variablePointers = true;
916 break;
917 }
918 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
919 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
920 features->multiview = true;
921 features->multiviewGeometryShader = true;
922 features->multiviewTessellationShader = true;
923 break;
924 }
925 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
926 VkPhysicalDeviceShaderDrawParametersFeatures *features =
927 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
928 features->shaderDrawParameters = true;
929 break;
930 }
931 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
932 VkPhysicalDeviceProtectedMemoryFeatures *features =
933 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
934 features->protectedMemory = false;
935 break;
936 }
937 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
938 VkPhysicalDevice16BitStorageFeatures *features =
939 (VkPhysicalDevice16BitStorageFeatures*)ext;
940 bool enable = !pdevice->use_aco || pdevice->rad_info.chip_class >= GFX8;
941 features->storageBuffer16BitAccess = enable;
942 features->uniformAndStorageBuffer16BitAccess = enable;
943 features->storagePushConstant16 = enable;
944 features->storageInputOutput16 = pdevice->rad_info.has_double_rate_fp16 && !pdevice->use_aco && LLVM_VERSION_MAJOR >= 9;
945 break;
946 }
947 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
948 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
949 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
950 features->samplerYcbcrConversion = true;
951 break;
952 }
953 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES: {
954 VkPhysicalDeviceDescriptorIndexingFeatures *features =
955 (VkPhysicalDeviceDescriptorIndexingFeatures*)ext;
956 features->shaderInputAttachmentArrayDynamicIndexing = true;
957 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
958 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
959 features->shaderUniformBufferArrayNonUniformIndexing = true;
960 features->shaderSampledImageArrayNonUniformIndexing = true;
961 features->shaderStorageBufferArrayNonUniformIndexing = true;
962 features->shaderStorageImageArrayNonUniformIndexing = true;
963 features->shaderInputAttachmentArrayNonUniformIndexing = true;
964 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
965 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
966 features->descriptorBindingUniformBufferUpdateAfterBind = true;
967 features->descriptorBindingSampledImageUpdateAfterBind = true;
968 features->descriptorBindingStorageImageUpdateAfterBind = true;
969 features->descriptorBindingStorageBufferUpdateAfterBind = true;
970 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
971 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
972 features->descriptorBindingUpdateUnusedWhilePending = true;
973 features->descriptorBindingPartiallyBound = true;
974 features->descriptorBindingVariableDescriptorCount = true;
975 features->runtimeDescriptorArray = true;
976 break;
977 }
978 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
979 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
980 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
981 features->conditionalRendering = true;
982 features->inheritedConditionalRendering = false;
983 break;
984 }
985 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
986 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
987 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
988 features->vertexAttributeInstanceRateDivisor = true;
989 features->vertexAttributeInstanceRateZeroDivisor = true;
990 break;
991 }
992 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
993 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
994 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
995 features->transformFeedback = true;
996 features->geometryStreams = !pdevice->use_ngg_streamout;
997 break;
998 }
999 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES: {
1000 VkPhysicalDeviceScalarBlockLayoutFeatures *features =
1001 (VkPhysicalDeviceScalarBlockLayoutFeatures *)ext;
1002 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
1003 break;
1004 }
1005 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
1006 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
1007 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
1008 features->memoryPriority = true;
1009 break;
1010 }
1011 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
1012 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
1013 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
1014 features->bufferDeviceAddress = true;
1015 features->bufferDeviceAddressCaptureReplay = false;
1016 features->bufferDeviceAddressMultiDevice = false;
1017 break;
1018 }
1019 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES: {
1020 VkPhysicalDeviceBufferDeviceAddressFeatures *features =
1021 (VkPhysicalDeviceBufferDeviceAddressFeatures *)ext;
1022 features->bufferDeviceAddress = true;
1023 features->bufferDeviceAddressCaptureReplay = false;
1024 features->bufferDeviceAddressMultiDevice = false;
1025 break;
1026 }
1027 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
1028 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
1029 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
1030 features->depthClipEnable = true;
1031 break;
1032 }
1033 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES: {
1034 VkPhysicalDeviceHostQueryResetFeatures *features =
1035 (VkPhysicalDeviceHostQueryResetFeatures *)ext;
1036 features->hostQueryReset = true;
1037 break;
1038 }
1039 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES: {
1040 VkPhysicalDevice8BitStorageFeatures *features =
1041 (VkPhysicalDevice8BitStorageFeatures *)ext;
1042 bool enable = !pdevice->use_aco || pdevice->rad_info.chip_class >= GFX8;
1043 features->storageBuffer8BitAccess = enable;
1044 features->uniformAndStorageBuffer8BitAccess = enable;
1045 features->storagePushConstant8 = enable;
1046 break;
1047 }
1048 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_FLOAT16_INT8_FEATURES: {
1049 VkPhysicalDeviceShaderFloat16Int8Features *features =
1050 (VkPhysicalDeviceShaderFloat16Int8Features*)ext;
1051 features->shaderFloat16 = pdevice->rad_info.has_double_rate_fp16 && !pdevice->use_aco;
1052 features->shaderInt8 = !pdevice->use_aco || pdevice->rad_info.chip_class >= GFX8;
1053 break;
1054 }
1055 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES: {
1056 VkPhysicalDeviceShaderAtomicInt64Features *features =
1057 (VkPhysicalDeviceShaderAtomicInt64Features *)ext;
1058 features->shaderBufferInt64Atomics = LLVM_VERSION_MAJOR >= 9;
1059 features->shaderSharedInt64Atomics = LLVM_VERSION_MAJOR >= 9;
1060 break;
1061 }
1062 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DEMOTE_TO_HELPER_INVOCATION_FEATURES_EXT: {
1063 VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *features =
1064 (VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *)ext;
1065 features->shaderDemoteToHelperInvocation = pdevice->use_aco;
1066 break;
1067 }
1068 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
1069 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
1070 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
1071
1072 features->inlineUniformBlock = true;
1073 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
1074 break;
1075 }
1076 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
1077 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
1078 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
1079 features->computeDerivativeGroupQuads = false;
1080 features->computeDerivativeGroupLinear = true;
1081 break;
1082 }
1083 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
1084 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
1085 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
1086 features->ycbcrImageArrays = true;
1087 break;
1088 }
1089 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES: {
1090 VkPhysicalDeviceUniformBufferStandardLayoutFeatures *features =
1091 (VkPhysicalDeviceUniformBufferStandardLayoutFeatures *)ext;
1092 features->uniformBufferStandardLayout = true;
1093 break;
1094 }
1095 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT: {
1096 VkPhysicalDeviceIndexTypeUint8FeaturesEXT *features =
1097 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT *)ext;
1098 features->indexTypeUint8 = pdevice->rad_info.chip_class >= GFX8;
1099 break;
1100 }
1101 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES: {
1102 VkPhysicalDeviceImagelessFramebufferFeatures *features =
1103 (VkPhysicalDeviceImagelessFramebufferFeatures *)ext;
1104 features->imagelessFramebuffer = true;
1105 break;
1106 }
1107 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR: {
1108 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *features =
1109 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *)ext;
1110 features->pipelineExecutableInfo = true;
1111 break;
1112 }
1113 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CLOCK_FEATURES_KHR: {
1114 VkPhysicalDeviceShaderClockFeaturesKHR *features =
1115 (VkPhysicalDeviceShaderClockFeaturesKHR *)ext;
1116 features->shaderSubgroupClock = true;
1117 features->shaderDeviceClock = false;
1118 break;
1119 }
1120 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_FEATURES_EXT: {
1121 VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *features =
1122 (VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *)ext;
1123 features->texelBufferAlignment = true;
1124 break;
1125 }
1126 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_FEATURES: {
1127 VkPhysicalDeviceTimelineSemaphoreFeatures *features =
1128 (VkPhysicalDeviceTimelineSemaphoreFeatures *) ext;
1129 features->timelineSemaphore = true;
1130 break;
1131 }
1132 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_FEATURES_EXT: {
1133 VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *features =
1134 (VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *)ext;
1135 features->subgroupSizeControl = true;
1136 features->computeFullSubgroups = true;
1137 break;
1138 }
1139 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COHERENT_MEMORY_FEATURES_AMD: {
1140 VkPhysicalDeviceCoherentMemoryFeaturesAMD *features =
1141 (VkPhysicalDeviceCoherentMemoryFeaturesAMD *)ext;
1142 features->deviceCoherentMemory = pdevice->rad_info.has_l2_uncached;
1143 break;
1144 }
1145 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_SUBGROUP_EXTENDED_TYPES_FEATURES: {
1146 VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures *features =
1147 (VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures *)ext;
1148 features->shaderSubgroupExtendedTypes = !pdevice->use_aco;
1149 break;
1150 }
1151 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SEPARATE_DEPTH_STENCIL_LAYOUTS_FEATURES_KHR: {
1152 VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR *features =
1153 (VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR *)ext;
1154 features->separateDepthStencilLayouts = true;
1155 break;
1156 }
1157 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES: {
1158 VkPhysicalDeviceVulkan11Features *features =
1159 (VkPhysicalDeviceVulkan11Features *)ext;
1160 bool storage16_enable = !pdevice->use_aco || pdevice->rad_info.chip_class >= GFX8;
1161 features->storageBuffer16BitAccess = storage16_enable;
1162 features->uniformAndStorageBuffer16BitAccess = storage16_enable;
1163 features->storagePushConstant16 = storage16_enable;
1164 features->storageInputOutput16 = pdevice->rad_info.has_double_rate_fp16 && !pdevice->use_aco && LLVM_VERSION_MAJOR >= 9;
1165 features->multiview = true;
1166 features->multiviewGeometryShader = true;
1167 features->multiviewTessellationShader = true;
1168 features->variablePointersStorageBuffer = true;
1169 features->variablePointers = true;
1170 features->protectedMemory = false;
1171 features->samplerYcbcrConversion = true;
1172 features->shaderDrawParameters = true;
1173 break;
1174 }
1175 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES: {
1176 VkPhysicalDeviceVulkan12Features *features =
1177 (VkPhysicalDeviceVulkan12Features *)ext;
1178 bool int8_enable = !pdevice->use_aco || pdevice->rad_info.chip_class >= GFX8;
1179 features->samplerMirrorClampToEdge = true;
1180 features->drawIndirectCount = true;
1181 features->storageBuffer8BitAccess = int8_enable;
1182 features->uniformAndStorageBuffer8BitAccess = int8_enable;
1183 features->storagePushConstant8 = int8_enable;
1184 features->shaderBufferInt64Atomics = LLVM_VERSION_MAJOR >= 9;
1185 features->shaderSharedInt64Atomics = LLVM_VERSION_MAJOR >= 9;
1186 features->shaderFloat16 = pdevice->rad_info.has_double_rate_fp16 && !pdevice->use_aco;
1187 features->shaderInt8 = int8_enable;
1188 features->descriptorIndexing = true;
1189 features->shaderInputAttachmentArrayDynamicIndexing = true;
1190 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
1191 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
1192 features->shaderUniformBufferArrayNonUniformIndexing = true;
1193 features->shaderSampledImageArrayNonUniformIndexing = true;
1194 features->shaderStorageBufferArrayNonUniformIndexing = true;
1195 features->shaderStorageImageArrayNonUniformIndexing = true;
1196 features->shaderInputAttachmentArrayNonUniformIndexing = true;
1197 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
1198 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
1199 features->descriptorBindingUniformBufferUpdateAfterBind = true;
1200 features->descriptorBindingSampledImageUpdateAfterBind = true;
1201 features->descriptorBindingStorageImageUpdateAfterBind = true;
1202 features->descriptorBindingStorageBufferUpdateAfterBind = true;
1203 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
1204 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
1205 features->descriptorBindingUpdateUnusedWhilePending = true;
1206 features->descriptorBindingPartiallyBound = true;
1207 features->descriptorBindingVariableDescriptorCount = true;
1208 features->runtimeDescriptorArray = true;
1209 features->samplerFilterMinmax = true;
1210 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
1211 features->imagelessFramebuffer = true;
1212 features->uniformBufferStandardLayout = true;
1213 features->shaderSubgroupExtendedTypes = !pdevice->use_aco;
1214 features->separateDepthStencilLayouts = true;
1215 features->hostQueryReset = true;
1216 features->timelineSemaphore = pdevice->rad_info.has_syncobj_wait_for_submit;
1217 features->bufferDeviceAddress = true;
1218 features->bufferDeviceAddressCaptureReplay = false;
1219 features->bufferDeviceAddressMultiDevice = false;
1220 features->vulkanMemoryModel = false;
1221 features->vulkanMemoryModelDeviceScope = false;
1222 features->vulkanMemoryModelAvailabilityVisibilityChains = false;
1223 features->shaderOutputViewportIndex = true;
1224 features->shaderOutputLayer = true;
1225 features->subgroupBroadcastDynamicId = true;
1226 break;
1227 }
1228 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_FEATURES_EXT: {
1229 VkPhysicalDeviceLineRasterizationFeaturesEXT *features =
1230 (VkPhysicalDeviceLineRasterizationFeaturesEXT *)ext;
1231 features->rectangularLines = false;
1232 features->bresenhamLines = true;
1233 features->smoothLines = false;
1234 features->stippledRectangularLines = false;
1235 features->stippledBresenhamLines = true;
1236 features->stippledSmoothLines = false;
1237 break;
1238 }
1239 case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD: {
1240 VkDeviceMemoryOverallocationCreateInfoAMD *features =
1241 (VkDeviceMemoryOverallocationCreateInfoAMD *)ext;
1242 features->overallocationBehavior = true;
1243 break;
1244 }
1245 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ROBUSTNESS_2_FEATURES_EXT: {
1246 VkPhysicalDeviceRobustness2FeaturesEXT *features =
1247 (VkPhysicalDeviceRobustness2FeaturesEXT *)ext;
1248 features->robustBufferAccess2 = true;
1249 features->robustImageAccess2 = true;
1250 features->nullDescriptor = true;
1251 break;
1252 }
1253 default:
1254 break;
1255 }
1256 }
1257 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
1258 }
1259
1260 static size_t
1261 radv_max_descriptor_set_size()
1262 {
1263 /* make sure that the entire descriptor set is addressable with a signed
1264 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1265 * be at most 2 GiB. the combined image & samples object count as one of
1266 * both. This limit is for the pipeline layout, not for the set layout, but
1267 * there is no set limit, so we just set a pipeline limit. I don't think
1268 * any app is going to hit this soon. */
1269 return ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
1270 - MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1271 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1272 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1273 32 /* sampler, largest when combined with image */ +
1274 64 /* sampled image */ +
1275 64 /* storage image */);
1276 }
1277
1278 void radv_GetPhysicalDeviceProperties(
1279 VkPhysicalDevice physicalDevice,
1280 VkPhysicalDeviceProperties* pProperties)
1281 {
1282 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1283 VkSampleCountFlags sample_counts = 0xf;
1284
1285 size_t max_descriptor_set_size = radv_max_descriptor_set_size();
1286
1287 VkPhysicalDeviceLimits limits = {
1288 .maxImageDimension1D = (1 << 14),
1289 .maxImageDimension2D = (1 << 14),
1290 .maxImageDimension3D = (1 << 11),
1291 .maxImageDimensionCube = (1 << 14),
1292 .maxImageArrayLayers = (1 << 11),
1293 .maxTexelBufferElements = UINT32_MAX,
1294 .maxUniformBufferRange = UINT32_MAX,
1295 .maxStorageBufferRange = UINT32_MAX,
1296 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1297 .maxMemoryAllocationCount = UINT32_MAX,
1298 .maxSamplerAllocationCount = 64 * 1024,
1299 .bufferImageGranularity = 64, /* A cache line */
1300 .sparseAddressSpaceSize = RADV_MAX_MEMORY_ALLOCATION_SIZE, /* buffer max size */
1301 .maxBoundDescriptorSets = MAX_SETS,
1302 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1303 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1304 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1305 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1306 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1307 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1308 .maxPerStageResources = max_descriptor_set_size,
1309 .maxDescriptorSetSamplers = max_descriptor_set_size,
1310 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1311 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1312 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1313 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1314 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1315 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1316 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1317 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1318 .maxVertexInputBindings = MAX_VBS,
1319 .maxVertexInputAttributeOffset = 2047,
1320 .maxVertexInputBindingStride = 2048,
1321 .maxVertexOutputComponents = 128,
1322 .maxTessellationGenerationLevel = 64,
1323 .maxTessellationPatchSize = 32,
1324 .maxTessellationControlPerVertexInputComponents = 128,
1325 .maxTessellationControlPerVertexOutputComponents = 128,
1326 .maxTessellationControlPerPatchOutputComponents = 120,
1327 .maxTessellationControlTotalOutputComponents = 4096,
1328 .maxTessellationEvaluationInputComponents = 128,
1329 .maxTessellationEvaluationOutputComponents = 128,
1330 .maxGeometryShaderInvocations = 127,
1331 .maxGeometryInputComponents = 64,
1332 .maxGeometryOutputComponents = 128,
1333 .maxGeometryOutputVertices = 256,
1334 .maxGeometryTotalOutputComponents = 1024,
1335 .maxFragmentInputComponents = 128,
1336 .maxFragmentOutputAttachments = 8,
1337 .maxFragmentDualSrcAttachments = 1,
1338 .maxFragmentCombinedOutputResources = 8,
1339 .maxComputeSharedMemorySize = 32768,
1340 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1341 .maxComputeWorkGroupInvocations = 1024,
1342 .maxComputeWorkGroupSize = {
1343 1024,
1344 1024,
1345 1024
1346 },
1347 .subPixelPrecisionBits = 8,
1348 .subTexelPrecisionBits = 8,
1349 .mipmapPrecisionBits = 8,
1350 .maxDrawIndexedIndexValue = UINT32_MAX,
1351 .maxDrawIndirectCount = UINT32_MAX,
1352 .maxSamplerLodBias = 16,
1353 .maxSamplerAnisotropy = 16,
1354 .maxViewports = MAX_VIEWPORTS,
1355 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1356 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1357 .viewportSubPixelBits = 8,
1358 .minMemoryMapAlignment = 4096, /* A page */
1359 .minTexelBufferOffsetAlignment = 4,
1360 .minUniformBufferOffsetAlignment = 4,
1361 .minStorageBufferOffsetAlignment = 4,
1362 .minTexelOffset = -32,
1363 .maxTexelOffset = 31,
1364 .minTexelGatherOffset = -32,
1365 .maxTexelGatherOffset = 31,
1366 .minInterpolationOffset = -2,
1367 .maxInterpolationOffset = 2,
1368 .subPixelInterpolationOffsetBits = 8,
1369 .maxFramebufferWidth = (1 << 14),
1370 .maxFramebufferHeight = (1 << 14),
1371 .maxFramebufferLayers = (1 << 10),
1372 .framebufferColorSampleCounts = sample_counts,
1373 .framebufferDepthSampleCounts = sample_counts,
1374 .framebufferStencilSampleCounts = sample_counts,
1375 .framebufferNoAttachmentsSampleCounts = sample_counts,
1376 .maxColorAttachments = MAX_RTS,
1377 .sampledImageColorSampleCounts = sample_counts,
1378 .sampledImageIntegerSampleCounts = sample_counts,
1379 .sampledImageDepthSampleCounts = sample_counts,
1380 .sampledImageStencilSampleCounts = sample_counts,
1381 .storageImageSampleCounts = sample_counts,
1382 .maxSampleMaskWords = 1,
1383 .timestampComputeAndGraphics = true,
1384 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1385 .maxClipDistances = 8,
1386 .maxCullDistances = 8,
1387 .maxCombinedClipAndCullDistances = 8,
1388 .discreteQueuePriorities = 2,
1389 .pointSizeRange = { 0.0, 8192.0 },
1390 .lineWidthRange = { 0.0, 8192.0 },
1391 .pointSizeGranularity = (1.0 / 8.0),
1392 .lineWidthGranularity = (1.0 / 8.0),
1393 .strictLines = false, /* FINISHME */
1394 .standardSampleLocations = true,
1395 .optimalBufferCopyOffsetAlignment = 128,
1396 .optimalBufferCopyRowPitchAlignment = 128,
1397 .nonCoherentAtomSize = 64,
1398 };
1399
1400 *pProperties = (VkPhysicalDeviceProperties) {
1401 .apiVersion = radv_physical_device_api_version(pdevice),
1402 .driverVersion = vk_get_driver_version(),
1403 .vendorID = ATI_VENDOR_ID,
1404 .deviceID = pdevice->rad_info.pci_id,
1405 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1406 .limits = limits,
1407 .sparseProperties = {0},
1408 };
1409
1410 strcpy(pProperties->deviceName, pdevice->name);
1411 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1412 }
1413
1414 static void
1415 radv_get_physical_device_properties_1_1(struct radv_physical_device *pdevice,
1416 VkPhysicalDeviceVulkan11Properties *p)
1417 {
1418 assert(p->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES);
1419
1420 memcpy(p->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1421 memcpy(p->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1422 memset(p->deviceLUID, 0, VK_LUID_SIZE);
1423 /* The LUID is for Windows. */
1424 p->deviceLUIDValid = false;
1425 p->deviceNodeMask = 0;
1426
1427 p->subgroupSize = RADV_SUBGROUP_SIZE;
1428 p->subgroupSupportedStages = VK_SHADER_STAGE_ALL_GRAPHICS |
1429 VK_SHADER_STAGE_COMPUTE_BIT;
1430 p->subgroupSupportedOperations = VK_SUBGROUP_FEATURE_BASIC_BIT |
1431 VK_SUBGROUP_FEATURE_VOTE_BIT |
1432 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1433 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1434 VK_SUBGROUP_FEATURE_CLUSTERED_BIT |
1435 VK_SUBGROUP_FEATURE_QUAD_BIT;
1436
1437 if (((pdevice->rad_info.chip_class == GFX6 ||
1438 pdevice->rad_info.chip_class == GFX7) && !pdevice->use_aco) ||
1439 pdevice->rad_info.chip_class >= GFX8) {
1440 p->subgroupSupportedOperations |= VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1441 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1442 }
1443 p->subgroupQuadOperationsInAllStages = true;
1444
1445 p->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1446 p->maxMultiviewViewCount = MAX_VIEWS;
1447 p->maxMultiviewInstanceIndex = INT_MAX;
1448 p->protectedNoFault = false;
1449 p->maxPerSetDescriptors = RADV_MAX_PER_SET_DESCRIPTORS;
1450 p->maxMemoryAllocationSize = RADV_MAX_MEMORY_ALLOCATION_SIZE;
1451 }
1452
1453 static void
1454 radv_get_physical_device_properties_1_2(struct radv_physical_device *pdevice,
1455 VkPhysicalDeviceVulkan12Properties *p)
1456 {
1457 assert(p->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES);
1458
1459 p->driverID = VK_DRIVER_ID_MESA_RADV;
1460 snprintf(p->driverName, VK_MAX_DRIVER_NAME_SIZE, "radv");
1461 snprintf(p->driverInfo, VK_MAX_DRIVER_INFO_SIZE,
1462 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1463 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1464 p->conformanceVersion = (VkConformanceVersion) {
1465 .major = 1,
1466 .minor = 2,
1467 .subminor = 0,
1468 .patch = 0,
1469 };
1470
1471 /* On AMD hardware, denormals and rounding modes for fp16/fp64 are
1472 * controlled by the same config register.
1473 */
1474 if (pdevice->rad_info.has_double_rate_fp16) {
1475 p->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1476 p->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1477 } else {
1478 p->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR;
1479 p->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR;
1480 }
1481
1482 /* Do not allow both preserving and flushing denorms because different
1483 * shaders in the same pipeline can have different settings and this
1484 * won't work for merged shaders. To make it work, this requires LLVM
1485 * support for changing the register. The same logic applies for the
1486 * rounding modes because they are configured with the same config
1487 * register. TODO: we can enable a lot of these for ACO when it
1488 * supports all stages.
1489 */
1490 p->shaderDenormFlushToZeroFloat32 = true;
1491 p->shaderDenormPreserveFloat32 = false;
1492 p->shaderRoundingModeRTEFloat32 = true;
1493 p->shaderRoundingModeRTZFloat32 = false;
1494 p->shaderSignedZeroInfNanPreserveFloat32 = true;
1495
1496 p->shaderDenormFlushToZeroFloat16 = false;
1497 p->shaderDenormPreserveFloat16 = pdevice->rad_info.has_double_rate_fp16;
1498 p->shaderRoundingModeRTEFloat16 = pdevice->rad_info.has_double_rate_fp16;
1499 p->shaderRoundingModeRTZFloat16 = false;
1500 p->shaderSignedZeroInfNanPreserveFloat16 = pdevice->rad_info.has_double_rate_fp16;
1501
1502 p->shaderDenormFlushToZeroFloat64 = false;
1503 p->shaderDenormPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1504 p->shaderRoundingModeRTEFloat64 = pdevice->rad_info.chip_class >= GFX8;
1505 p->shaderRoundingModeRTZFloat64 = false;
1506 p->shaderSignedZeroInfNanPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1507
1508 p->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1509 p->shaderUniformBufferArrayNonUniformIndexingNative = false;
1510 p->shaderSampledImageArrayNonUniformIndexingNative = false;
1511 p->shaderStorageBufferArrayNonUniformIndexingNative = false;
1512 p->shaderStorageImageArrayNonUniformIndexingNative = false;
1513 p->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1514 p->robustBufferAccessUpdateAfterBind = false;
1515 p->quadDivergentImplicitLod = false;
1516
1517 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1518 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1519 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1520 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1521 32 /* sampler, largest when combined with image */ +
1522 64 /* sampled image */ +
1523 64 /* storage image */);
1524 p->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1525 p->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1526 p->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1527 p->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1528 p->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1529 p->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1530 p->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1531 p->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1532 p->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1533 p->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1534 p->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1535 p->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1536 p->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1537 p->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1538 p->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1539
1540 /* We support all of the depth resolve modes */
1541 p->supportedDepthResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1542 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1543 VK_RESOLVE_MODE_MIN_BIT_KHR |
1544 VK_RESOLVE_MODE_MAX_BIT_KHR;
1545
1546 /* Average doesn't make sense for stencil so we don't support that */
1547 p->supportedStencilResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1548 VK_RESOLVE_MODE_MIN_BIT_KHR |
1549 VK_RESOLVE_MODE_MAX_BIT_KHR;
1550
1551 p->independentResolveNone = true;
1552 p->independentResolve = true;
1553
1554 /* GFX6-8 only support single channel min/max filter. */
1555 p->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1556 p->filterMinmaxSingleComponentFormats = true;
1557
1558 p->maxTimelineSemaphoreValueDifference = UINT64_MAX;
1559
1560 p->framebufferIntegerColorSampleCounts = VK_SAMPLE_COUNT_1_BIT;
1561 }
1562
1563 void radv_GetPhysicalDeviceProperties2(
1564 VkPhysicalDevice physicalDevice,
1565 VkPhysicalDeviceProperties2 *pProperties)
1566 {
1567 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1568 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1569
1570 VkPhysicalDeviceVulkan11Properties core_1_1 = {
1571 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES,
1572 };
1573 radv_get_physical_device_properties_1_1(pdevice, &core_1_1);
1574
1575 VkPhysicalDeviceVulkan12Properties core_1_2 = {
1576 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES,
1577 };
1578 radv_get_physical_device_properties_1_2(pdevice, &core_1_2);
1579
1580 #define CORE_RENAMED_PROPERTY(major, minor, ext_property, core_property) \
1581 memcpy(&properties->ext_property, &core_##major##_##minor.core_property, \
1582 sizeof(core_##major##_##minor.core_property))
1583
1584 #define CORE_PROPERTY(major, minor, property) \
1585 CORE_RENAMED_PROPERTY(major, minor, property, property)
1586
1587 vk_foreach_struct(ext, pProperties->pNext) {
1588 switch (ext->sType) {
1589 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1590 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1591 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1592 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1593 break;
1594 }
1595 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1596 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1597 CORE_PROPERTY(1, 1, deviceUUID);
1598 CORE_PROPERTY(1, 1, driverUUID);
1599 CORE_PROPERTY(1, 1, deviceLUID);
1600 CORE_PROPERTY(1, 1, deviceLUIDValid);
1601 break;
1602 }
1603 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1604 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1605 CORE_PROPERTY(1, 1, maxMultiviewViewCount);
1606 CORE_PROPERTY(1, 1, maxMultiviewInstanceIndex);
1607 break;
1608 }
1609 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1610 VkPhysicalDevicePointClippingProperties *properties =
1611 (VkPhysicalDevicePointClippingProperties*)ext;
1612 CORE_PROPERTY(1, 1, pointClippingBehavior);
1613 break;
1614 }
1615 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1616 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1617 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1618 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1619 break;
1620 }
1621 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1622 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1623 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1624 properties->minImportedHostPointerAlignment = 4096;
1625 break;
1626 }
1627 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1628 VkPhysicalDeviceSubgroupProperties *properties =
1629 (VkPhysicalDeviceSubgroupProperties*)ext;
1630 CORE_PROPERTY(1, 1, subgroupSize);
1631 CORE_RENAMED_PROPERTY(1, 1, supportedStages,
1632 subgroupSupportedStages);
1633 CORE_RENAMED_PROPERTY(1, 1, supportedOperations,
1634 subgroupSupportedOperations);
1635 CORE_RENAMED_PROPERTY(1, 1, quadOperationsInAllStages,
1636 subgroupQuadOperationsInAllStages);
1637 break;
1638 }
1639 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1640 VkPhysicalDeviceMaintenance3Properties *properties =
1641 (VkPhysicalDeviceMaintenance3Properties*)ext;
1642 CORE_PROPERTY(1, 1, maxPerSetDescriptors);
1643 CORE_PROPERTY(1, 1, maxMemoryAllocationSize);
1644 break;
1645 }
1646 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES: {
1647 VkPhysicalDeviceSamplerFilterMinmaxProperties *properties =
1648 (VkPhysicalDeviceSamplerFilterMinmaxProperties *)ext;
1649 CORE_PROPERTY(1, 2, filterMinmaxImageComponentMapping);
1650 CORE_PROPERTY(1, 2, filterMinmaxSingleComponentFormats);
1651 break;
1652 }
1653 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1654 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1655 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1656
1657 /* Shader engines. */
1658 properties->shaderEngineCount =
1659 pdevice->rad_info.max_se;
1660 properties->shaderArraysPerEngineCount =
1661 pdevice->rad_info.max_sh_per_se;
1662 properties->computeUnitsPerShaderArray =
1663 pdevice->rad_info.num_good_cu_per_sh;
1664 properties->simdPerComputeUnit =
1665 pdevice->rad_info.num_simd_per_compute_unit;
1666 properties->wavefrontsPerSimd =
1667 pdevice->rad_info.max_wave64_per_simd;
1668 properties->wavefrontSize = 64;
1669
1670 /* SGPR. */
1671 properties->sgprsPerSimd =
1672 pdevice->rad_info.num_physical_sgprs_per_simd;
1673 properties->minSgprAllocation =
1674 pdevice->rad_info.min_sgpr_alloc;
1675 properties->maxSgprAllocation =
1676 pdevice->rad_info.max_sgpr_alloc;
1677 properties->sgprAllocationGranularity =
1678 pdevice->rad_info.sgpr_alloc_granularity;
1679
1680 /* VGPR. */
1681 properties->vgprsPerSimd =
1682 pdevice->rad_info.num_physical_wave64_vgprs_per_simd;
1683 properties->minVgprAllocation =
1684 pdevice->rad_info.min_wave64_vgpr_alloc;
1685 properties->maxVgprAllocation =
1686 pdevice->rad_info.max_vgpr_alloc;
1687 properties->vgprAllocationGranularity =
1688 pdevice->rad_info.wave64_vgpr_alloc_granularity;
1689 break;
1690 }
1691 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD: {
1692 VkPhysicalDeviceShaderCoreProperties2AMD *properties =
1693 (VkPhysicalDeviceShaderCoreProperties2AMD *)ext;
1694
1695 properties->shaderCoreFeatures = 0;
1696 properties->activeComputeUnitCount =
1697 pdevice->rad_info.num_good_compute_units;
1698 break;
1699 }
1700 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1701 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1702 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1703 properties->maxVertexAttribDivisor = UINT32_MAX;
1704 break;
1705 }
1706 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES: {
1707 VkPhysicalDeviceDescriptorIndexingProperties *properties =
1708 (VkPhysicalDeviceDescriptorIndexingProperties*)ext;
1709 CORE_PROPERTY(1, 2, maxUpdateAfterBindDescriptorsInAllPools);
1710 CORE_PROPERTY(1, 2, shaderUniformBufferArrayNonUniformIndexingNative);
1711 CORE_PROPERTY(1, 2, shaderSampledImageArrayNonUniformIndexingNative);
1712 CORE_PROPERTY(1, 2, shaderStorageBufferArrayNonUniformIndexingNative);
1713 CORE_PROPERTY(1, 2, shaderStorageImageArrayNonUniformIndexingNative);
1714 CORE_PROPERTY(1, 2, shaderInputAttachmentArrayNonUniformIndexingNative);
1715 CORE_PROPERTY(1, 2, robustBufferAccessUpdateAfterBind);
1716 CORE_PROPERTY(1, 2, quadDivergentImplicitLod);
1717 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSamplers);
1718 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindUniformBuffers);
1719 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageBuffers);
1720 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSampledImages);
1721 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageImages);
1722 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindInputAttachments);
1723 CORE_PROPERTY(1, 2, maxPerStageUpdateAfterBindResources);
1724 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSamplers);
1725 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffers);
1726 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffersDynamic);
1727 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffers);
1728 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffersDynamic);
1729 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSampledImages);
1730 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageImages);
1731 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindInputAttachments);
1732 break;
1733 }
1734 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1735 VkPhysicalDeviceProtectedMemoryProperties *properties =
1736 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1737 CORE_PROPERTY(1, 1, protectedNoFault);
1738 break;
1739 }
1740 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1741 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1742 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1743 properties->primitiveOverestimationSize = 0;
1744 properties->maxExtraPrimitiveOverestimationSize = 0;
1745 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1746 properties->primitiveUnderestimation = false;
1747 properties->conservativePointAndLineRasterization = false;
1748 properties->degenerateTrianglesRasterized = false;
1749 properties->degenerateLinesRasterized = false;
1750 properties->fullyCoveredFragmentShaderInputVariable = false;
1751 properties->conservativeRasterizationPostDepthCoverage = false;
1752 break;
1753 }
1754 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1755 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1756 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1757 properties->pciDomain = pdevice->bus_info.domain;
1758 properties->pciBus = pdevice->bus_info.bus;
1759 properties->pciDevice = pdevice->bus_info.dev;
1760 properties->pciFunction = pdevice->bus_info.func;
1761 break;
1762 }
1763 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES: {
1764 VkPhysicalDeviceDriverProperties *properties =
1765 (VkPhysicalDeviceDriverProperties *) ext;
1766 CORE_PROPERTY(1, 2, driverID);
1767 CORE_PROPERTY(1, 2, driverName);
1768 CORE_PROPERTY(1, 2, driverInfo);
1769 CORE_PROPERTY(1, 2, conformanceVersion);
1770 break;
1771 }
1772 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1773 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1774 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1775 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1776 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1777 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1778 properties->maxTransformFeedbackStreamDataSize = 512;
1779 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1780 properties->maxTransformFeedbackBufferDataStride = 512;
1781 properties->transformFeedbackQueries = !pdevice->use_ngg_streamout;
1782 properties->transformFeedbackStreamsLinesTriangles = !pdevice->use_ngg_streamout;
1783 properties->transformFeedbackRasterizationStreamSelect = false;
1784 properties->transformFeedbackDraw = true;
1785 break;
1786 }
1787 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1788 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1789 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1790
1791 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1792 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1793 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1794 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1795 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1796 break;
1797 }
1798 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1799 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1800 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1801 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1802 VK_SAMPLE_COUNT_4_BIT |
1803 VK_SAMPLE_COUNT_8_BIT;
1804 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1805 properties->sampleLocationCoordinateRange[0] = 0.0f;
1806 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1807 properties->sampleLocationSubPixelBits = 4;
1808 properties->variableSampleLocations = false;
1809 break;
1810 }
1811 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES: {
1812 VkPhysicalDeviceDepthStencilResolveProperties *properties =
1813 (VkPhysicalDeviceDepthStencilResolveProperties *)ext;
1814 CORE_PROPERTY(1, 2, supportedDepthResolveModes);
1815 CORE_PROPERTY(1, 2, supportedStencilResolveModes);
1816 CORE_PROPERTY(1, 2, independentResolveNone);
1817 CORE_PROPERTY(1, 2, independentResolve);
1818 break;
1819 }
1820 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_PROPERTIES_EXT: {
1821 VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *properties =
1822 (VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *)ext;
1823 properties->storageTexelBufferOffsetAlignmentBytes = 4;
1824 properties->storageTexelBufferOffsetSingleTexelAlignment = true;
1825 properties->uniformTexelBufferOffsetAlignmentBytes = 4;
1826 properties->uniformTexelBufferOffsetSingleTexelAlignment = true;
1827 break;
1828 }
1829 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT_CONTROLS_PROPERTIES : {
1830 VkPhysicalDeviceFloatControlsProperties *properties =
1831 (VkPhysicalDeviceFloatControlsProperties *)ext;
1832 CORE_PROPERTY(1, 2, denormBehaviorIndependence);
1833 CORE_PROPERTY(1, 2, roundingModeIndependence);
1834 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat16);
1835 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat16);
1836 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat16);
1837 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat16);
1838 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat16);
1839 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat32);
1840 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat32);
1841 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat32);
1842 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat32);
1843 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat32);
1844 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat64);
1845 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat64);
1846 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat64);
1847 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat64);
1848 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat64);
1849 break;
1850 }
1851 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_PROPERTIES: {
1852 VkPhysicalDeviceTimelineSemaphoreProperties *properties =
1853 (VkPhysicalDeviceTimelineSemaphoreProperties *) ext;
1854 CORE_PROPERTY(1, 2, maxTimelineSemaphoreValueDifference);
1855 break;
1856 }
1857 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_PROPERTIES_EXT: {
1858 VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *props =
1859 (VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *)ext;
1860 props->minSubgroupSize = 64;
1861 props->maxSubgroupSize = 64;
1862 props->maxComputeWorkgroupSubgroups = UINT32_MAX;
1863 props->requiredSubgroupSizeStages = 0;
1864
1865 if (pdevice->rad_info.chip_class >= GFX10) {
1866 /* Only GFX10+ supports wave32. */
1867 props->minSubgroupSize = 32;
1868 props->requiredSubgroupSizeStages = VK_SHADER_STAGE_COMPUTE_BIT;
1869 }
1870 break;
1871 }
1872 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES:
1873 radv_get_physical_device_properties_1_1(pdevice, (void *)ext);
1874 break;
1875 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES:
1876 radv_get_physical_device_properties_1_2(pdevice, (void *)ext);
1877 break;
1878 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_PROPERTIES_EXT: {
1879 VkPhysicalDeviceLineRasterizationPropertiesEXT *props =
1880 (VkPhysicalDeviceLineRasterizationPropertiesEXT *)ext;
1881 props->lineSubPixelPrecisionBits = 4;
1882 break;
1883 }
1884 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ROBUSTNESS_2_PROPERTIES_EXT: {
1885 VkPhysicalDeviceRobustness2PropertiesEXT *properties =
1886 (VkPhysicalDeviceRobustness2PropertiesEXT *)ext;
1887 properties->robustStorageBufferAccessSizeAlignment = 4;
1888 properties->robustUniformBufferAccessSizeAlignment = 4;
1889 break;
1890 }
1891 default:
1892 break;
1893 }
1894 }
1895 }
1896
1897 static void radv_get_physical_device_queue_family_properties(
1898 struct radv_physical_device* pdevice,
1899 uint32_t* pCount,
1900 VkQueueFamilyProperties** pQueueFamilyProperties)
1901 {
1902 int num_queue_families = 1;
1903 int idx;
1904 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
1905 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1906 num_queue_families++;
1907
1908 if (pQueueFamilyProperties == NULL) {
1909 *pCount = num_queue_families;
1910 return;
1911 }
1912
1913 if (!*pCount)
1914 return;
1915
1916 idx = 0;
1917 if (*pCount >= 1) {
1918 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1919 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1920 VK_QUEUE_COMPUTE_BIT |
1921 VK_QUEUE_TRANSFER_BIT |
1922 VK_QUEUE_SPARSE_BINDING_BIT,
1923 .queueCount = 1,
1924 .timestampValidBits = 64,
1925 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1926 };
1927 idx++;
1928 }
1929
1930 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
1931 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1932 if (*pCount > idx) {
1933 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1934 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1935 VK_QUEUE_TRANSFER_BIT |
1936 VK_QUEUE_SPARSE_BINDING_BIT,
1937 .queueCount = pdevice->rad_info.num_rings[RING_COMPUTE],
1938 .timestampValidBits = 64,
1939 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1940 };
1941 idx++;
1942 }
1943 }
1944 *pCount = idx;
1945 }
1946
1947 void radv_GetPhysicalDeviceQueueFamilyProperties(
1948 VkPhysicalDevice physicalDevice,
1949 uint32_t* pCount,
1950 VkQueueFamilyProperties* pQueueFamilyProperties)
1951 {
1952 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1953 if (!pQueueFamilyProperties) {
1954 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1955 return;
1956 }
1957 VkQueueFamilyProperties *properties[] = {
1958 pQueueFamilyProperties + 0,
1959 pQueueFamilyProperties + 1,
1960 pQueueFamilyProperties + 2,
1961 };
1962 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1963 assert(*pCount <= 3);
1964 }
1965
1966 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1967 VkPhysicalDevice physicalDevice,
1968 uint32_t* pCount,
1969 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1970 {
1971 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1972 if (!pQueueFamilyProperties) {
1973 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1974 return;
1975 }
1976 VkQueueFamilyProperties *properties[] = {
1977 &pQueueFamilyProperties[0].queueFamilyProperties,
1978 &pQueueFamilyProperties[1].queueFamilyProperties,
1979 &pQueueFamilyProperties[2].queueFamilyProperties,
1980 };
1981 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1982 assert(*pCount <= 3);
1983 }
1984
1985 void radv_GetPhysicalDeviceMemoryProperties(
1986 VkPhysicalDevice physicalDevice,
1987 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1988 {
1989 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1990
1991 *pMemoryProperties = physical_device->memory_properties;
1992 }
1993
1994 static void
1995 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1996 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1997 {
1998 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1999 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
2000 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
2001 uint64_t vram_size = radv_get_vram_size(device);
2002 uint64_t gtt_size = device->rad_info.gart_size;
2003 uint64_t heap_budget, heap_usage;
2004
2005 /* For all memory heaps, the computation of budget is as follow:
2006 * heap_budget = heap_size - global_heap_usage + app_heap_usage
2007 *
2008 * The Vulkan spec 1.1.97 says that the budget should include any
2009 * currently allocated device memory.
2010 *
2011 * Note that the application heap usages are not really accurate (eg.
2012 * in presence of shared buffers).
2013 */
2014 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
2015 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
2016
2017 if ((device->memory_domains[i] & RADEON_DOMAIN_VRAM) && (device->memory_flags[i] & RADEON_FLAG_NO_CPU_ACCESS)) {
2018 heap_usage = device->ws->query_value(device->ws,
2019 RADEON_ALLOCATED_VRAM);
2020
2021 heap_budget = vram_size -
2022 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
2023 heap_usage;
2024
2025 memoryBudget->heapBudget[heap_index] = heap_budget;
2026 memoryBudget->heapUsage[heap_index] = heap_usage;
2027 } else if (device->memory_domains[i] & RADEON_DOMAIN_VRAM) {
2028 heap_usage = device->ws->query_value(device->ws,
2029 RADEON_ALLOCATED_VRAM_VIS);
2030
2031 heap_budget = visible_vram_size -
2032 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
2033 heap_usage;
2034
2035 memoryBudget->heapBudget[heap_index] = heap_budget;
2036 memoryBudget->heapUsage[heap_index] = heap_usage;
2037 } else {
2038 assert(device->memory_domains[i] & RADEON_DOMAIN_GTT);
2039
2040 heap_usage = device->ws->query_value(device->ws,
2041 RADEON_ALLOCATED_GTT);
2042
2043 heap_budget = gtt_size -
2044 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
2045 heap_usage;
2046
2047 memoryBudget->heapBudget[heap_index] = heap_budget;
2048 memoryBudget->heapUsage[heap_index] = heap_usage;
2049 }
2050 }
2051
2052 /* The heapBudget and heapUsage values must be zero for array elements
2053 * greater than or equal to
2054 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
2055 */
2056 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
2057 memoryBudget->heapBudget[i] = 0;
2058 memoryBudget->heapUsage[i] = 0;
2059 }
2060 }
2061
2062 void radv_GetPhysicalDeviceMemoryProperties2(
2063 VkPhysicalDevice physicalDevice,
2064 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
2065 {
2066 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
2067 &pMemoryProperties->memoryProperties);
2068
2069 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
2070 vk_find_struct(pMemoryProperties->pNext,
2071 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
2072 if (memory_budget)
2073 radv_get_memory_budget_properties(physicalDevice, memory_budget);
2074 }
2075
2076 VkResult radv_GetMemoryHostPointerPropertiesEXT(
2077 VkDevice _device,
2078 VkExternalMemoryHandleTypeFlagBits handleType,
2079 const void *pHostPointer,
2080 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
2081 {
2082 RADV_FROM_HANDLE(radv_device, device, _device);
2083
2084 switch (handleType)
2085 {
2086 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
2087 const struct radv_physical_device *physical_device = device->physical_device;
2088 uint32_t memoryTypeBits = 0;
2089 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
2090 if (physical_device->memory_domains[i] == RADEON_DOMAIN_GTT &&
2091 !(physical_device->memory_flags[i] & RADEON_FLAG_GTT_WC)) {
2092 memoryTypeBits = (1 << i);
2093 break;
2094 }
2095 }
2096 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
2097 return VK_SUCCESS;
2098 }
2099 default:
2100 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
2101 }
2102 }
2103
2104 static enum radeon_ctx_priority
2105 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
2106 {
2107 /* Default to MEDIUM when a specific global priority isn't requested */
2108 if (!pObj)
2109 return RADEON_CTX_PRIORITY_MEDIUM;
2110
2111 switch(pObj->globalPriority) {
2112 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
2113 return RADEON_CTX_PRIORITY_REALTIME;
2114 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
2115 return RADEON_CTX_PRIORITY_HIGH;
2116 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
2117 return RADEON_CTX_PRIORITY_MEDIUM;
2118 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
2119 return RADEON_CTX_PRIORITY_LOW;
2120 default:
2121 unreachable("Illegal global priority value");
2122 return RADEON_CTX_PRIORITY_INVALID;
2123 }
2124 }
2125
2126 static int
2127 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
2128 uint32_t queue_family_index, int idx,
2129 VkDeviceQueueCreateFlags flags,
2130 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
2131 {
2132 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2133 queue->device = device;
2134 queue->queue_family_index = queue_family_index;
2135 queue->queue_idx = idx;
2136 queue->priority = radv_get_queue_global_priority(global_priority);
2137 queue->flags = flags;
2138
2139 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
2140 if (!queue->hw_ctx)
2141 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2142
2143 list_inithead(&queue->pending_submissions);
2144 pthread_mutex_init(&queue->pending_mutex, NULL);
2145
2146 return VK_SUCCESS;
2147 }
2148
2149 static void
2150 radv_queue_finish(struct radv_queue *queue)
2151 {
2152 pthread_mutex_destroy(&queue->pending_mutex);
2153
2154 if (queue->hw_ctx)
2155 queue->device->ws->ctx_destroy(queue->hw_ctx);
2156
2157 if (queue->initial_full_flush_preamble_cs)
2158 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2159 if (queue->initial_preamble_cs)
2160 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2161 if (queue->continue_preamble_cs)
2162 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2163 if (queue->descriptor_bo)
2164 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2165 if (queue->scratch_bo)
2166 queue->device->ws->buffer_destroy(queue->scratch_bo);
2167 if (queue->esgs_ring_bo)
2168 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2169 if (queue->gsvs_ring_bo)
2170 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2171 if (queue->tess_rings_bo)
2172 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
2173 if (queue->gds_bo)
2174 queue->device->ws->buffer_destroy(queue->gds_bo);
2175 if (queue->gds_oa_bo)
2176 queue->device->ws->buffer_destroy(queue->gds_oa_bo);
2177 if (queue->compute_scratch_bo)
2178 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2179 }
2180
2181 static void
2182 radv_bo_list_init(struct radv_bo_list *bo_list)
2183 {
2184 pthread_mutex_init(&bo_list->mutex, NULL);
2185 bo_list->list.count = bo_list->capacity = 0;
2186 bo_list->list.bos = NULL;
2187 }
2188
2189 static void
2190 radv_bo_list_finish(struct radv_bo_list *bo_list)
2191 {
2192 free(bo_list->list.bos);
2193 pthread_mutex_destroy(&bo_list->mutex);
2194 }
2195
2196 VkResult radv_bo_list_add(struct radv_device *device,
2197 struct radeon_winsys_bo *bo)
2198 {
2199 struct radv_bo_list *bo_list = &device->bo_list;
2200
2201 if (bo->is_local)
2202 return VK_SUCCESS;
2203
2204 if (unlikely(!device->use_global_bo_list))
2205 return VK_SUCCESS;
2206
2207 pthread_mutex_lock(&bo_list->mutex);
2208 if (bo_list->list.count == bo_list->capacity) {
2209 unsigned capacity = MAX2(4, bo_list->capacity * 2);
2210 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
2211
2212 if (!data) {
2213 pthread_mutex_unlock(&bo_list->mutex);
2214 return VK_ERROR_OUT_OF_HOST_MEMORY;
2215 }
2216
2217 bo_list->list.bos = (struct radeon_winsys_bo**)data;
2218 bo_list->capacity = capacity;
2219 }
2220
2221 bo_list->list.bos[bo_list->list.count++] = bo;
2222 pthread_mutex_unlock(&bo_list->mutex);
2223 return VK_SUCCESS;
2224 }
2225
2226 void radv_bo_list_remove(struct radv_device *device,
2227 struct radeon_winsys_bo *bo)
2228 {
2229 struct radv_bo_list *bo_list = &device->bo_list;
2230
2231 if (bo->is_local)
2232 return;
2233
2234 if (unlikely(!device->use_global_bo_list))
2235 return;
2236
2237 pthread_mutex_lock(&bo_list->mutex);
2238 /* Loop the list backwards so we find the most recently added
2239 * memory first. */
2240 for(unsigned i = bo_list->list.count; i-- > 0;) {
2241 if (bo_list->list.bos[i] == bo) {
2242 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
2243 --bo_list->list.count;
2244 break;
2245 }
2246 }
2247 pthread_mutex_unlock(&bo_list->mutex);
2248 }
2249
2250 static void
2251 radv_device_init_gs_info(struct radv_device *device)
2252 {
2253 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
2254 device->physical_device->rad_info.family);
2255 }
2256
2257 static int radv_get_device_extension_index(const char *name)
2258 {
2259 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
2260 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
2261 return i;
2262 }
2263 return -1;
2264 }
2265
2266 static int
2267 radv_get_int_debug_option(const char *name, int default_value)
2268 {
2269 const char *str;
2270 int result;
2271
2272 str = getenv(name);
2273 if (!str) {
2274 result = default_value;
2275 } else {
2276 char *endptr;
2277
2278 result = strtol(str, &endptr, 0);
2279 if (str == endptr) {
2280 /* No digits founs. */
2281 result = default_value;
2282 }
2283 }
2284
2285 return result;
2286 }
2287
2288 static int install_seccomp_filter() {
2289
2290 struct sock_filter filter[] = {
2291 /* Check arch is 64bit x86 */
2292 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, arch))),
2293 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, AUDIT_ARCH_X86_64, 0, 12),
2294
2295 /* Futex is required for mutex locks */
2296 #if defined __NR__newselect
2297 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2298 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR__newselect, 11, 0),
2299 #elif defined __NR_select
2300 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2301 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_select, 11, 0),
2302 #else
2303 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2304 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_pselect6, 11, 0),
2305 #endif
2306
2307 /* Allow system exit calls for the forked process */
2308 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2309 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_exit_group, 9, 0),
2310
2311 /* Allow system read calls */
2312 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2313 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_read, 7, 0),
2314
2315 /* Allow system write calls */
2316 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2317 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_write, 5, 0),
2318
2319 /* Allow system brk calls (we need this for malloc) */
2320 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2321 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_brk, 3, 0),
2322
2323 /* Futex is required for mutex locks */
2324 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2325 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_futex, 1, 0),
2326
2327 /* Return error if we hit a system call not on the whitelist */
2328 BPF_STMT(BPF_RET + BPF_K, SECCOMP_RET_ERRNO | (EPERM & SECCOMP_RET_DATA)),
2329
2330 /* Allow whitelisted system calls */
2331 BPF_STMT(BPF_RET + BPF_K, SECCOMP_RET_ALLOW),
2332 };
2333
2334 struct sock_fprog prog = {
2335 .len = (unsigned short)(sizeof(filter) / sizeof(filter[0])),
2336 .filter = filter,
2337 };
2338
2339 if (prctl(PR_SET_NO_NEW_PRIVS, 1, 0, 0, 0))
2340 return -1;
2341
2342 if (prctl(PR_SET_SECCOMP, SECCOMP_MODE_FILTER, &prog))
2343 return -1;
2344
2345 return 0;
2346 }
2347
2348 /* Helper function with timeout support for reading from the pipe between
2349 * processes used for secure compile.
2350 */
2351 bool radv_sc_read(int fd, void *buf, size_t size, bool timeout)
2352 {
2353 fd_set fds;
2354 struct timeval tv;
2355
2356 FD_ZERO(&fds);
2357 FD_SET(fd, &fds);
2358
2359 while (true) {
2360 /* We can't rely on the value of tv after calling select() so
2361 * we must reset it on each iteration of the loop.
2362 */
2363 tv.tv_sec = 5;
2364 tv.tv_usec = 0;
2365
2366 int rval = select(fd + 1, &fds, NULL, NULL, timeout ? &tv : NULL);
2367
2368 if (rval == -1) {
2369 /* select error */
2370 return false;
2371 } else if (rval) {
2372 ssize_t bytes_read = read(fd, buf, size);
2373 if (bytes_read < 0)
2374 return false;
2375
2376 buf += bytes_read;
2377 size -= bytes_read;
2378 if (size == 0)
2379 return true;
2380 } else {
2381 /* select timeout */
2382 return false;
2383 }
2384 }
2385 }
2386
2387 static bool radv_close_all_fds(const int *keep_fds, int keep_fd_count)
2388 {
2389 DIR *d;
2390 struct dirent *dir;
2391 d = opendir("/proc/self/fd");
2392 if (!d)
2393 return false;
2394 int dir_fd = dirfd(d);
2395
2396 while ((dir = readdir(d)) != NULL) {
2397 if (dir->d_name[0] == '.')
2398 continue;
2399
2400 int fd = atoi(dir->d_name);
2401 if (fd == dir_fd)
2402 continue;
2403
2404 bool keep = false;
2405 for (int i = 0; !keep && i < keep_fd_count; ++i)
2406 if (keep_fds[i] == fd)
2407 keep = true;
2408
2409 if (keep)
2410 continue;
2411
2412 close(fd);
2413 }
2414 closedir(d);
2415 return true;
2416 }
2417
2418 static bool secure_compile_open_fifo_fds(struct radv_secure_compile_state *sc,
2419 int *fd_server, int *fd_client,
2420 unsigned process, bool make_fifo)
2421 {
2422 bool result = false;
2423 char *fifo_server_path = NULL;
2424 char *fifo_client_path = NULL;
2425
2426 if (asprintf(&fifo_server_path, "/tmp/radv_server_%s_%u", sc->uid, process) == -1)
2427 goto open_fifo_exit;
2428
2429 if (asprintf(&fifo_client_path, "/tmp/radv_client_%s_%u", sc->uid, process) == -1)
2430 goto open_fifo_exit;
2431
2432 if (make_fifo) {
2433 int file1 = mkfifo(fifo_server_path, 0666);
2434 if(file1 < 0)
2435 goto open_fifo_exit;
2436
2437 int file2 = mkfifo(fifo_client_path, 0666);
2438 if(file2 < 0)
2439 goto open_fifo_exit;
2440 }
2441
2442 *fd_server = open(fifo_server_path, O_RDWR);
2443 if(*fd_server < 1)
2444 goto open_fifo_exit;
2445
2446 *fd_client = open(fifo_client_path, O_RDWR);
2447 if(*fd_client < 1) {
2448 close(*fd_server);
2449 goto open_fifo_exit;
2450 }
2451
2452 result = true;
2453
2454 open_fifo_exit:
2455 free(fifo_server_path);
2456 free(fifo_client_path);
2457
2458 return result;
2459 }
2460
2461 static void run_secure_compile_device(struct radv_device *device, unsigned process,
2462 int fd_idle_device_output)
2463 {
2464 int fd_secure_input;
2465 int fd_secure_output;
2466 bool fifo_result = secure_compile_open_fifo_fds(device->sc_state,
2467 &fd_secure_input,
2468 &fd_secure_output,
2469 process, false);
2470
2471 enum radv_secure_compile_type sc_type;
2472
2473 const int needed_fds[] = {
2474 fd_secure_input,
2475 fd_secure_output,
2476 fd_idle_device_output,
2477 };
2478
2479 if (!fifo_result || !radv_close_all_fds(needed_fds, ARRAY_SIZE(needed_fds)) ||
2480 install_seccomp_filter() == -1) {
2481 sc_type = RADV_SC_TYPE_INIT_FAILURE;
2482 } else {
2483 sc_type = RADV_SC_TYPE_INIT_SUCCESS;
2484 device->sc_state->secure_compile_processes[process].fd_secure_input = fd_secure_input;
2485 device->sc_state->secure_compile_processes[process].fd_secure_output = fd_secure_output;
2486 }
2487
2488 write(fd_idle_device_output, &sc_type, sizeof(sc_type));
2489
2490 if (sc_type == RADV_SC_TYPE_INIT_FAILURE)
2491 goto secure_compile_exit;
2492
2493 while (true) {
2494 radv_sc_read(fd_secure_input, &sc_type, sizeof(sc_type), false);
2495
2496 if (sc_type == RADV_SC_TYPE_COMPILE_PIPELINE) {
2497 struct radv_pipeline *pipeline;
2498 bool sc_read = true;
2499
2500 pipeline = vk_zalloc2(&device->alloc, NULL, sizeof(*pipeline), 8,
2501 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2502
2503 pipeline->device = device;
2504
2505 /* Read pipeline layout */
2506 struct radv_pipeline_layout layout;
2507 sc_read = radv_sc_read(fd_secure_input, &layout, sizeof(struct radv_pipeline_layout), true);
2508 sc_read &= radv_sc_read(fd_secure_input, &layout.num_sets, sizeof(uint32_t), true);
2509 if (!sc_read)
2510 goto secure_compile_exit;
2511
2512 for (uint32_t set = 0; set < layout.num_sets; set++) {
2513 uint32_t layout_size;
2514 sc_read &= radv_sc_read(fd_secure_input, &layout_size, sizeof(uint32_t), true);
2515 if (!sc_read)
2516 goto secure_compile_exit;
2517
2518 layout.set[set].layout = malloc(layout_size);
2519 layout.set[set].layout->layout_size = layout_size;
2520 sc_read &= radv_sc_read(fd_secure_input, layout.set[set].layout,
2521 layout.set[set].layout->layout_size, true);
2522 }
2523
2524 pipeline->layout = &layout;
2525
2526 /* Read pipeline key */
2527 struct radv_pipeline_key key;
2528 sc_read &= radv_sc_read(fd_secure_input, &key, sizeof(struct radv_pipeline_key), true);
2529
2530 /* Read pipeline create flags */
2531 VkPipelineCreateFlags flags;
2532 sc_read &= radv_sc_read(fd_secure_input, &flags, sizeof(VkPipelineCreateFlags), true);
2533
2534 /* Read stage and shader information */
2535 uint32_t num_stages;
2536 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
2537 sc_read &= radv_sc_read(fd_secure_input, &num_stages, sizeof(uint32_t), true);
2538 if (!sc_read)
2539 goto secure_compile_exit;
2540
2541 for (uint32_t i = 0; i < num_stages; i++) {
2542
2543 /* Read stage */
2544 gl_shader_stage stage;
2545 sc_read &= radv_sc_read(fd_secure_input, &stage, sizeof(gl_shader_stage), true);
2546
2547 VkPipelineShaderStageCreateInfo *pStage = calloc(1, sizeof(VkPipelineShaderStageCreateInfo));
2548
2549 /* Read entry point name */
2550 size_t name_size;
2551 sc_read &= radv_sc_read(fd_secure_input, &name_size, sizeof(size_t), true);
2552 if (!sc_read)
2553 goto secure_compile_exit;
2554
2555 char *ep_name = malloc(name_size);
2556 sc_read &= radv_sc_read(fd_secure_input, ep_name, name_size, true);
2557 pStage->pName = ep_name;
2558
2559 /* Read shader module */
2560 size_t module_size;
2561 sc_read &= radv_sc_read(fd_secure_input, &module_size, sizeof(size_t), true);
2562 if (!sc_read)
2563 goto secure_compile_exit;
2564
2565 struct radv_shader_module *module = malloc(module_size);
2566 sc_read &= radv_sc_read(fd_secure_input, module, module_size, true);
2567 pStage->module = radv_shader_module_to_handle(module);
2568
2569 /* Read specialization info */
2570 bool has_spec_info;
2571 sc_read &= radv_sc_read(fd_secure_input, &has_spec_info, sizeof(bool), true);
2572 if (!sc_read)
2573 goto secure_compile_exit;
2574
2575 if (has_spec_info) {
2576 VkSpecializationInfo *specInfo = malloc(sizeof(VkSpecializationInfo));
2577 pStage->pSpecializationInfo = specInfo;
2578
2579 sc_read &= radv_sc_read(fd_secure_input, &specInfo->dataSize, sizeof(size_t), true);
2580 if (!sc_read)
2581 goto secure_compile_exit;
2582
2583 void *si_data = malloc(specInfo->dataSize);
2584 sc_read &= radv_sc_read(fd_secure_input, si_data, specInfo->dataSize, true);
2585 specInfo->pData = si_data;
2586
2587 sc_read &= radv_sc_read(fd_secure_input, &specInfo->mapEntryCount, sizeof(uint32_t), true);
2588 if (!sc_read)
2589 goto secure_compile_exit;
2590
2591 VkSpecializationMapEntry *mapEntries = malloc(sizeof(VkSpecializationMapEntry) * specInfo->mapEntryCount);
2592 for (uint32_t j = 0; j < specInfo->mapEntryCount; j++) {
2593 sc_read &= radv_sc_read(fd_secure_input, &mapEntries[j], sizeof(VkSpecializationMapEntry), true);
2594 if (!sc_read)
2595 goto secure_compile_exit;
2596 }
2597
2598 specInfo->pMapEntries = mapEntries;
2599 }
2600
2601 pStages[stage] = pStage;
2602 }
2603
2604 /* Compile the shaders */
2605 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
2606 radv_create_shaders(pipeline, device, NULL, &key, pStages, flags, NULL, stage_feedbacks);
2607
2608 /* free memory allocated above */
2609 for (uint32_t set = 0; set < layout.num_sets; set++)
2610 free(layout.set[set].layout);
2611
2612 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
2613 if (!pStages[i])
2614 continue;
2615
2616 free((void *) pStages[i]->pName);
2617 free(radv_shader_module_from_handle(pStages[i]->module));
2618 if (pStages[i]->pSpecializationInfo) {
2619 free((void *) pStages[i]->pSpecializationInfo->pData);
2620 free((void *) pStages[i]->pSpecializationInfo->pMapEntries);
2621 free((void *) pStages[i]->pSpecializationInfo);
2622 }
2623 free((void *) pStages[i]);
2624 }
2625
2626 vk_free(&device->alloc, pipeline);
2627
2628 sc_type = RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED;
2629 write(fd_secure_output, &sc_type, sizeof(sc_type));
2630
2631 } else if (sc_type == RADV_SC_TYPE_DESTROY_DEVICE) {
2632 goto secure_compile_exit;
2633 }
2634 }
2635
2636 secure_compile_exit:
2637 close(fd_secure_input);
2638 close(fd_secure_output);
2639 close(fd_idle_device_output);
2640 _exit(0);
2641 }
2642
2643 static enum radv_secure_compile_type fork_secure_compile_device(struct radv_device *device, unsigned process)
2644 {
2645 int fd_secure_input[2];
2646 int fd_secure_output[2];
2647
2648 /* create pipe descriptors (used to communicate between processes) */
2649 if (pipe(fd_secure_input) == -1 || pipe(fd_secure_output) == -1)
2650 return RADV_SC_TYPE_INIT_FAILURE;
2651
2652
2653 int sc_pid;
2654 if ((sc_pid = fork()) == 0) {
2655 device->sc_state->secure_compile_thread_counter = process;
2656 run_secure_compile_device(device, process, fd_secure_output[1]);
2657 } else {
2658 if (sc_pid == -1)
2659 return RADV_SC_TYPE_INIT_FAILURE;
2660
2661 /* Read the init result returned from the secure process */
2662 enum radv_secure_compile_type sc_type;
2663 bool sc_read = radv_sc_read(fd_secure_output[0], &sc_type, sizeof(sc_type), true);
2664
2665 if (sc_type == RADV_SC_TYPE_INIT_FAILURE || !sc_read) {
2666 close(fd_secure_input[0]);
2667 close(fd_secure_input[1]);
2668 close(fd_secure_output[1]);
2669 close(fd_secure_output[0]);
2670 int status;
2671 waitpid(sc_pid, &status, 0);
2672
2673 return RADV_SC_TYPE_INIT_FAILURE;
2674 } else {
2675 assert(sc_type == RADV_SC_TYPE_INIT_SUCCESS);
2676 write(device->sc_state->secure_compile_processes[process].fd_secure_output, &sc_type, sizeof(sc_type));
2677
2678 close(fd_secure_input[0]);
2679 close(fd_secure_input[1]);
2680 close(fd_secure_output[1]);
2681 close(fd_secure_output[0]);
2682
2683 int status;
2684 waitpid(sc_pid, &status, 0);
2685 }
2686 }
2687
2688 return RADV_SC_TYPE_INIT_SUCCESS;
2689 }
2690
2691 /* Run a bare bones fork of a device that was forked right after its creation.
2692 * This device will have low overhead when it is forked again before each
2693 * pipeline compilation. This device sits idle and its only job is to fork
2694 * itself.
2695 */
2696 static void run_secure_compile_idle_device(struct radv_device *device, unsigned process,
2697 int fd_secure_input, int fd_secure_output)
2698 {
2699 enum radv_secure_compile_type sc_type = RADV_SC_TYPE_INIT_SUCCESS;
2700 device->sc_state->secure_compile_processes[process].fd_secure_input = fd_secure_input;
2701 device->sc_state->secure_compile_processes[process].fd_secure_output = fd_secure_output;
2702
2703 write(fd_secure_output, &sc_type, sizeof(sc_type));
2704
2705 while (true) {
2706 radv_sc_read(fd_secure_input, &sc_type, sizeof(sc_type), false);
2707
2708 if (sc_type == RADV_SC_TYPE_FORK_DEVICE) {
2709 sc_type = fork_secure_compile_device(device, process);
2710
2711 if (sc_type == RADV_SC_TYPE_INIT_FAILURE)
2712 goto secure_compile_exit;
2713
2714 } else if (sc_type == RADV_SC_TYPE_DESTROY_DEVICE) {
2715 goto secure_compile_exit;
2716 }
2717 }
2718
2719 secure_compile_exit:
2720 close(fd_secure_input);
2721 close(fd_secure_output);
2722 _exit(0);
2723 }
2724
2725 static void destroy_secure_compile_device(struct radv_device *device, unsigned process)
2726 {
2727 int fd_secure_input = device->sc_state->secure_compile_processes[process].fd_secure_input;
2728
2729 enum radv_secure_compile_type sc_type = RADV_SC_TYPE_DESTROY_DEVICE;
2730 write(fd_secure_input, &sc_type, sizeof(sc_type));
2731
2732 close(device->sc_state->secure_compile_processes[process].fd_secure_input);
2733 close(device->sc_state->secure_compile_processes[process].fd_secure_output);
2734
2735 int status;
2736 waitpid(device->sc_state->secure_compile_processes[process].sc_pid, &status, 0);
2737 }
2738
2739 static VkResult fork_secure_compile_idle_device(struct radv_device *device)
2740 {
2741 device->sc_state = vk_zalloc(&device->alloc,
2742 sizeof(struct radv_secure_compile_state),
2743 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2744
2745 mtx_init(&device->sc_state->secure_compile_mutex, mtx_plain);
2746
2747 pid_t upid = getpid();
2748 time_t seconds = time(NULL);
2749
2750 char *uid;
2751 if (asprintf(&uid, "%ld_%ld", (long) upid, (long) seconds) == -1)
2752 return VK_ERROR_INITIALIZATION_FAILED;
2753
2754 device->sc_state->uid = uid;
2755
2756 uint8_t sc_threads = device->instance->num_sc_threads;
2757 int fd_secure_input[MAX_SC_PROCS][2];
2758 int fd_secure_output[MAX_SC_PROCS][2];
2759
2760 /* create pipe descriptors (used to communicate between processes) */
2761 for (unsigned i = 0; i < sc_threads; i++) {
2762 if (pipe(fd_secure_input[i]) == -1 ||
2763 pipe(fd_secure_output[i]) == -1) {
2764 return VK_ERROR_INITIALIZATION_FAILED;
2765 }
2766 }
2767
2768 device->sc_state->secure_compile_processes = vk_zalloc(&device->alloc,
2769 sizeof(struct radv_secure_compile_process) * sc_threads, 8,
2770 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2771
2772 for (unsigned process = 0; process < sc_threads; process++) {
2773 if ((device->sc_state->secure_compile_processes[process].sc_pid = fork()) == 0) {
2774 device->sc_state->secure_compile_thread_counter = process;
2775 run_secure_compile_idle_device(device, process, fd_secure_input[process][0], fd_secure_output[process][1]);
2776 } else {
2777 if (device->sc_state->secure_compile_processes[process].sc_pid == -1)
2778 return VK_ERROR_INITIALIZATION_FAILED;
2779
2780 /* Read the init result returned from the secure process */
2781 enum radv_secure_compile_type sc_type;
2782 bool sc_read = radv_sc_read(fd_secure_output[process][0], &sc_type, sizeof(sc_type), true);
2783
2784 bool fifo_result;
2785 if (sc_read && sc_type == RADV_SC_TYPE_INIT_SUCCESS) {
2786 fifo_result = secure_compile_open_fifo_fds(device->sc_state,
2787 &device->sc_state->secure_compile_processes[process].fd_server,
2788 &device->sc_state->secure_compile_processes[process].fd_client,
2789 process, true);
2790
2791 device->sc_state->secure_compile_processes[process].fd_secure_input = fd_secure_input[process][1];
2792 device->sc_state->secure_compile_processes[process].fd_secure_output = fd_secure_output[process][0];
2793 }
2794
2795 if (sc_type == RADV_SC_TYPE_INIT_FAILURE || !sc_read || !fifo_result) {
2796 close(fd_secure_input[process][0]);
2797 close(fd_secure_input[process][1]);
2798 close(fd_secure_output[process][1]);
2799 close(fd_secure_output[process][0]);
2800 int status;
2801 waitpid(device->sc_state->secure_compile_processes[process].sc_pid, &status, 0);
2802
2803 /* Destroy any forks that were created sucessfully */
2804 for (unsigned i = 0; i < process; i++) {
2805 destroy_secure_compile_device(device, i);
2806 }
2807
2808 return VK_ERROR_INITIALIZATION_FAILED;
2809 }
2810 }
2811 }
2812 return VK_SUCCESS;
2813 }
2814
2815 static void
2816 radv_device_init_dispatch(struct radv_device *device)
2817 {
2818 const struct radv_instance *instance = device->physical_device->instance;
2819 const struct radv_device_dispatch_table *dispatch_table_layer = NULL;
2820 bool unchecked = instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS;
2821 int radv_thread_trace = radv_get_int_debug_option("RADV_THREAD_TRACE", -1);
2822
2823 if (radv_thread_trace >= 0) {
2824 /* Use device entrypoints from the SQTT layer if enabled. */
2825 dispatch_table_layer = &sqtt_device_dispatch_table;
2826 }
2827
2828 for (unsigned i = 0; i < ARRAY_SIZE(device->dispatch.entrypoints); i++) {
2829 /* Vulkan requires that entrypoints for extensions which have not been
2830 * enabled must not be advertised.
2831 */
2832 if (!unchecked &&
2833 !radv_device_entrypoint_is_enabled(i, instance->apiVersion,
2834 &instance->enabled_extensions,
2835 &device->enabled_extensions)) {
2836 device->dispatch.entrypoints[i] = NULL;
2837 } else if (dispatch_table_layer &&
2838 dispatch_table_layer->entrypoints[i]) {
2839 device->dispatch.entrypoints[i] =
2840 dispatch_table_layer->entrypoints[i];
2841 } else {
2842 device->dispatch.entrypoints[i] =
2843 radv_device_dispatch_table.entrypoints[i];
2844 }
2845 }
2846 }
2847
2848 static VkResult
2849 radv_create_pthread_cond(pthread_cond_t *cond)
2850 {
2851 pthread_condattr_t condattr;
2852 if (pthread_condattr_init(&condattr)) {
2853 return VK_ERROR_INITIALIZATION_FAILED;
2854 }
2855
2856 if (pthread_condattr_setclock(&condattr, CLOCK_MONOTONIC)) {
2857 pthread_condattr_destroy(&condattr);
2858 return VK_ERROR_INITIALIZATION_FAILED;
2859 }
2860 if (pthread_cond_init(cond, &condattr)) {
2861 pthread_condattr_destroy(&condattr);
2862 return VK_ERROR_INITIALIZATION_FAILED;
2863 }
2864 pthread_condattr_destroy(&condattr);
2865 return VK_SUCCESS;
2866 }
2867
2868 static VkResult
2869 check_physical_device_features(VkPhysicalDevice physicalDevice,
2870 const VkPhysicalDeviceFeatures *features)
2871 {
2872 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2873 VkPhysicalDeviceFeatures supported_features;
2874 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
2875 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
2876 VkBool32 *enabled_feature = (VkBool32 *)features;
2877 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
2878 for (uint32_t i = 0; i < num_features; i++) {
2879 if (enabled_feature[i] && !supported_feature[i])
2880 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
2881 }
2882
2883 return VK_SUCCESS;
2884 }
2885
2886 VkResult radv_CreateDevice(
2887 VkPhysicalDevice physicalDevice,
2888 const VkDeviceCreateInfo* pCreateInfo,
2889 const VkAllocationCallbacks* pAllocator,
2890 VkDevice* pDevice)
2891 {
2892 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2893 VkResult result;
2894 struct radv_device *device;
2895
2896 bool keep_shader_info = false;
2897 bool robust_buffer_access = false;
2898 bool overallocation_disallowed = false;
2899
2900 /* Check enabled features */
2901 if (pCreateInfo->pEnabledFeatures) {
2902 result = check_physical_device_features(physicalDevice,
2903 pCreateInfo->pEnabledFeatures);
2904 if (result != VK_SUCCESS)
2905 return result;
2906
2907 if (pCreateInfo->pEnabledFeatures->robustBufferAccess)
2908 robust_buffer_access = true;
2909 }
2910
2911 vk_foreach_struct_const(ext, pCreateInfo->pNext) {
2912 switch (ext->sType) {
2913 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FEATURES_2: {
2914 const VkPhysicalDeviceFeatures2 *features = (const void *)ext;
2915 result = check_physical_device_features(physicalDevice,
2916 &features->features);
2917 if (result != VK_SUCCESS)
2918 return result;
2919
2920 if (features->features.robustBufferAccess)
2921 robust_buffer_access = true;
2922 break;
2923 }
2924 case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD: {
2925 const VkDeviceMemoryOverallocationCreateInfoAMD *overallocation = (const void *)ext;
2926 if (overallocation->overallocationBehavior == VK_MEMORY_OVERALLOCATION_BEHAVIOR_DISALLOWED_AMD)
2927 overallocation_disallowed = true;
2928 break;
2929 }
2930 default:
2931 break;
2932 }
2933 }
2934
2935 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
2936 sizeof(*device), 8,
2937 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2938 if (!device)
2939 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2940
2941 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2942 device->instance = physical_device->instance;
2943 device->physical_device = physical_device;
2944
2945 device->ws = physical_device->ws;
2946 if (pAllocator)
2947 device->alloc = *pAllocator;
2948 else
2949 device->alloc = physical_device->instance->alloc;
2950
2951 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
2952 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
2953 int index = radv_get_device_extension_index(ext_name);
2954 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
2955 vk_free(&device->alloc, device);
2956 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
2957 }
2958
2959 device->enabled_extensions.extensions[index] = true;
2960 }
2961
2962 radv_device_init_dispatch(device);
2963
2964 keep_shader_info = device->enabled_extensions.AMD_shader_info;
2965
2966 /* With update after bind we can't attach bo's to the command buffer
2967 * from the descriptor set anymore, so we have to use a global BO list.
2968 */
2969 device->use_global_bo_list =
2970 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
2971 device->enabled_extensions.EXT_descriptor_indexing ||
2972 device->enabled_extensions.EXT_buffer_device_address ||
2973 device->enabled_extensions.KHR_buffer_device_address;
2974
2975 device->robust_buffer_access = robust_buffer_access;
2976
2977 mtx_init(&device->shader_slab_mutex, mtx_plain);
2978 list_inithead(&device->shader_slabs);
2979
2980 device->overallocation_disallowed = overallocation_disallowed;
2981 mtx_init(&device->overallocation_mutex, mtx_plain);
2982
2983 radv_bo_list_init(&device->bo_list);
2984
2985 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
2986 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
2987 uint32_t qfi = queue_create->queueFamilyIndex;
2988 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
2989 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
2990
2991 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
2992
2993 device->queues[qfi] = vk_alloc(&device->alloc,
2994 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2995 if (!device->queues[qfi]) {
2996 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2997 goto fail;
2998 }
2999
3000 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
3001
3002 device->queue_count[qfi] = queue_create->queueCount;
3003
3004 for (unsigned q = 0; q < queue_create->queueCount; q++) {
3005 result = radv_queue_init(device, &device->queues[qfi][q],
3006 qfi, q, queue_create->flags,
3007 global_priority);
3008 if (result != VK_SUCCESS)
3009 goto fail;
3010 }
3011 }
3012
3013 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
3014 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
3015
3016 /* Disable DFSM by default. As of 2019-09-15 Talos on Low is still 3% slower on Raven. */
3017 device->dfsm_allowed = device->pbb_allowed &&
3018 (device->instance->perftest_flags & RADV_PERFTEST_DFSM);
3019
3020 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
3021
3022 /* The maximum number of scratch waves. Scratch space isn't divided
3023 * evenly between CUs. The number is only a function of the number of CUs.
3024 * We can decrease the constant to decrease the scratch buffer size.
3025 *
3026 * sctx->scratch_waves must be >= the maximum possible size of
3027 * 1 threadgroup, so that the hw doesn't hang from being unable
3028 * to start any.
3029 *
3030 * The recommended value is 4 per CU at most. Higher numbers don't
3031 * bring much benefit, but they still occupy chip resources (think
3032 * async compute). I've seen ~2% performance difference between 4 and 32.
3033 */
3034 uint32_t max_threads_per_block = 2048;
3035 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
3036 max_threads_per_block / 64);
3037
3038 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
3039
3040 if (device->physical_device->rad_info.chip_class >= GFX7) {
3041 /* If the KMD allows it (there is a KMD hw register for it),
3042 * allow launching waves out-of-order.
3043 */
3044 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
3045 }
3046
3047 radv_device_init_gs_info(device);
3048
3049 device->tess_offchip_block_dw_size =
3050 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
3051
3052 if (getenv("RADV_TRACE_FILE")) {
3053 const char *filename = getenv("RADV_TRACE_FILE");
3054
3055 keep_shader_info = true;
3056
3057 if (!radv_init_trace(device))
3058 goto fail;
3059
3060 fprintf(stderr, "*****************************************************************************\n");
3061 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
3062 fprintf(stderr, "*****************************************************************************\n");
3063
3064 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
3065 radv_dump_enabled_options(device, stderr);
3066 }
3067
3068 int radv_thread_trace = radv_get_int_debug_option("RADV_THREAD_TRACE", -1);
3069 if (radv_thread_trace >= 0) {
3070 fprintf(stderr, "*************************************************\n");
3071 fprintf(stderr, "* WARNING: Thread trace support is experimental *\n");
3072 fprintf(stderr, "*************************************************\n");
3073
3074 if (device->physical_device->rad_info.chip_class < GFX8) {
3075 fprintf(stderr, "GPU hardware not supported: refer to "
3076 "the RGP documentation for the list of "
3077 "supported GPUs!\n");
3078 abort();
3079 }
3080
3081 /* Default buffer size set to 1MB per SE. */
3082 device->thread_trace_buffer_size =
3083 radv_get_int_debug_option("RADV_THREAD_TRACE_BUFFER_SIZE", 1024 * 1024);
3084 device->thread_trace_start_frame = radv_thread_trace;
3085
3086 if (!radv_thread_trace_init(device))
3087 goto fail;
3088 }
3089
3090 /* Temporarily disable secure compile while we create meta shaders, etc */
3091 uint8_t sc_threads = device->instance->num_sc_threads;
3092 if (sc_threads)
3093 device->instance->num_sc_threads = 0;
3094
3095 device->keep_shader_info = keep_shader_info;
3096 result = radv_device_init_meta(device);
3097 if (result != VK_SUCCESS)
3098 goto fail;
3099
3100 radv_device_init_msaa(device);
3101
3102 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
3103 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
3104 switch (family) {
3105 case RADV_QUEUE_GENERAL:
3106 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
3107 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
3108 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
3109 break;
3110 case RADV_QUEUE_COMPUTE:
3111 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
3112 radeon_emit(device->empty_cs[family], 0);
3113 break;
3114 }
3115 device->ws->cs_finalize(device->empty_cs[family]);
3116 }
3117
3118 if (device->physical_device->rad_info.chip_class >= GFX7)
3119 cik_create_gfx_config(device);
3120
3121 VkPipelineCacheCreateInfo ci;
3122 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
3123 ci.pNext = NULL;
3124 ci.flags = 0;
3125 ci.pInitialData = NULL;
3126 ci.initialDataSize = 0;
3127 VkPipelineCache pc;
3128 result = radv_CreatePipelineCache(radv_device_to_handle(device),
3129 &ci, NULL, &pc);
3130 if (result != VK_SUCCESS)
3131 goto fail_meta;
3132
3133 device->mem_cache = radv_pipeline_cache_from_handle(pc);
3134
3135 result = radv_create_pthread_cond(&device->timeline_cond);
3136 if (result != VK_SUCCESS)
3137 goto fail_mem_cache;
3138
3139 device->force_aniso =
3140 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
3141 if (device->force_aniso >= 0) {
3142 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
3143 1 << util_logbase2(device->force_aniso));
3144 }
3145
3146 /* Fork device for secure compile as required */
3147 device->instance->num_sc_threads = sc_threads;
3148 if (radv_device_use_secure_compile(device->instance)) {
3149
3150 result = fork_secure_compile_idle_device(device);
3151 if (result != VK_SUCCESS)
3152 goto fail_meta;
3153 }
3154
3155 *pDevice = radv_device_to_handle(device);
3156 return VK_SUCCESS;
3157
3158 fail_mem_cache:
3159 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
3160 fail_meta:
3161 radv_device_finish_meta(device);
3162 fail:
3163 radv_bo_list_finish(&device->bo_list);
3164
3165 radv_thread_trace_finish(device);
3166
3167 if (device->trace_bo)
3168 device->ws->buffer_destroy(device->trace_bo);
3169
3170 if (device->gfx_init)
3171 device->ws->buffer_destroy(device->gfx_init);
3172
3173 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
3174 for (unsigned q = 0; q < device->queue_count[i]; q++)
3175 radv_queue_finish(&device->queues[i][q]);
3176 if (device->queue_count[i])
3177 vk_free(&device->alloc, device->queues[i]);
3178 }
3179
3180 vk_free(&device->alloc, device);
3181 return result;
3182 }
3183
3184 void radv_DestroyDevice(
3185 VkDevice _device,
3186 const VkAllocationCallbacks* pAllocator)
3187 {
3188 RADV_FROM_HANDLE(radv_device, device, _device);
3189
3190 if (!device)
3191 return;
3192
3193 if (device->trace_bo)
3194 device->ws->buffer_destroy(device->trace_bo);
3195
3196 if (device->gfx_init)
3197 device->ws->buffer_destroy(device->gfx_init);
3198
3199 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
3200 for (unsigned q = 0; q < device->queue_count[i]; q++)
3201 radv_queue_finish(&device->queues[i][q]);
3202 if (device->queue_count[i])
3203 vk_free(&device->alloc, device->queues[i]);
3204 if (device->empty_cs[i])
3205 device->ws->cs_destroy(device->empty_cs[i]);
3206 }
3207 radv_device_finish_meta(device);
3208
3209 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
3210 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
3211
3212 radv_destroy_shader_slabs(device);
3213
3214 pthread_cond_destroy(&device->timeline_cond);
3215 radv_bo_list_finish(&device->bo_list);
3216
3217 radv_thread_trace_finish(device);
3218
3219 if (radv_device_use_secure_compile(device->instance)) {
3220 for (unsigned i = 0; i < device->instance->num_sc_threads; i++ ) {
3221 destroy_secure_compile_device(device, i);
3222 }
3223 }
3224
3225 if (device->sc_state) {
3226 free(device->sc_state->uid);
3227 vk_free(&device->alloc, device->sc_state->secure_compile_processes);
3228 }
3229 vk_free(&device->alloc, device->sc_state);
3230 vk_free(&device->alloc, device);
3231 }
3232
3233 VkResult radv_EnumerateInstanceLayerProperties(
3234 uint32_t* pPropertyCount,
3235 VkLayerProperties* pProperties)
3236 {
3237 if (pProperties == NULL) {
3238 *pPropertyCount = 0;
3239 return VK_SUCCESS;
3240 }
3241
3242 /* None supported at this time */
3243 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
3244 }
3245
3246 VkResult radv_EnumerateDeviceLayerProperties(
3247 VkPhysicalDevice physicalDevice,
3248 uint32_t* pPropertyCount,
3249 VkLayerProperties* pProperties)
3250 {
3251 if (pProperties == NULL) {
3252 *pPropertyCount = 0;
3253 return VK_SUCCESS;
3254 }
3255
3256 /* None supported at this time */
3257 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
3258 }
3259
3260 void radv_GetDeviceQueue2(
3261 VkDevice _device,
3262 const VkDeviceQueueInfo2* pQueueInfo,
3263 VkQueue* pQueue)
3264 {
3265 RADV_FROM_HANDLE(radv_device, device, _device);
3266 struct radv_queue *queue;
3267
3268 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
3269 if (pQueueInfo->flags != queue->flags) {
3270 /* From the Vulkan 1.1.70 spec:
3271 *
3272 * "The queue returned by vkGetDeviceQueue2 must have the same
3273 * flags value from this structure as that used at device
3274 * creation time in a VkDeviceQueueCreateInfo instance. If no
3275 * matching flags were specified at device creation time then
3276 * pQueue will return VK_NULL_HANDLE."
3277 */
3278 *pQueue = VK_NULL_HANDLE;
3279 return;
3280 }
3281
3282 *pQueue = radv_queue_to_handle(queue);
3283 }
3284
3285 void radv_GetDeviceQueue(
3286 VkDevice _device,
3287 uint32_t queueFamilyIndex,
3288 uint32_t queueIndex,
3289 VkQueue* pQueue)
3290 {
3291 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
3292 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
3293 .queueFamilyIndex = queueFamilyIndex,
3294 .queueIndex = queueIndex
3295 };
3296
3297 radv_GetDeviceQueue2(_device, &info, pQueue);
3298 }
3299
3300 static void
3301 fill_geom_tess_rings(struct radv_queue *queue,
3302 uint32_t *map,
3303 bool add_sample_positions,
3304 uint32_t esgs_ring_size,
3305 struct radeon_winsys_bo *esgs_ring_bo,
3306 uint32_t gsvs_ring_size,
3307 struct radeon_winsys_bo *gsvs_ring_bo,
3308 uint32_t tess_factor_ring_size,
3309 uint32_t tess_offchip_ring_offset,
3310 uint32_t tess_offchip_ring_size,
3311 struct radeon_winsys_bo *tess_rings_bo)
3312 {
3313 uint32_t *desc = &map[4];
3314
3315 if (esgs_ring_bo) {
3316 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
3317
3318 /* stride 0, num records - size, add tid, swizzle, elsize4,
3319 index stride 64 */
3320 desc[0] = esgs_va;
3321 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
3322 S_008F04_SWIZZLE_ENABLE(true);
3323 desc[2] = esgs_ring_size;
3324 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3325 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3326 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3327 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3328 S_008F0C_INDEX_STRIDE(3) |
3329 S_008F0C_ADD_TID_ENABLE(1);
3330
3331 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3332 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3333 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3334 S_008F0C_RESOURCE_LEVEL(1);
3335 } else {
3336 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3337 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
3338 S_008F0C_ELEMENT_SIZE(1);
3339 }
3340
3341 /* GS entry for ES->GS ring */
3342 /* stride 0, num records - size, elsize0,
3343 index stride 0 */
3344 desc[4] = esgs_va;
3345 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32);
3346 desc[6] = esgs_ring_size;
3347 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3348 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3349 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3350 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3351
3352 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3353 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3354 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3355 S_008F0C_RESOURCE_LEVEL(1);
3356 } else {
3357 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3358 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3359 }
3360 }
3361
3362 desc += 8;
3363
3364 if (gsvs_ring_bo) {
3365 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
3366
3367 /* VS entry for GS->VS ring */
3368 /* stride 0, num records - size, elsize0,
3369 index stride 0 */
3370 desc[0] = gsvs_va;
3371 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32);
3372 desc[2] = gsvs_ring_size;
3373 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3374 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3375 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3376 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3377
3378 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3379 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3380 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3381 S_008F0C_RESOURCE_LEVEL(1);
3382 } else {
3383 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3384 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3385 }
3386
3387 /* stride gsvs_itemsize, num records 64
3388 elsize 4, index stride 16 */
3389 /* shader will patch stride and desc[2] */
3390 desc[4] = gsvs_va;
3391 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32) |
3392 S_008F04_SWIZZLE_ENABLE(1);
3393 desc[6] = 0;
3394 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3395 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3396 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3397 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3398 S_008F0C_INDEX_STRIDE(1) |
3399 S_008F0C_ADD_TID_ENABLE(true);
3400
3401 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3402 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3403 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3404 S_008F0C_RESOURCE_LEVEL(1);
3405 } else {
3406 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3407 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
3408 S_008F0C_ELEMENT_SIZE(1);
3409 }
3410
3411 }
3412
3413 desc += 8;
3414
3415 if (tess_rings_bo) {
3416 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
3417 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
3418
3419 desc[0] = tess_va;
3420 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32);
3421 desc[2] = tess_factor_ring_size;
3422 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3423 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3424 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3425 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3426
3427 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3428 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3429 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3430 S_008F0C_RESOURCE_LEVEL(1);
3431 } else {
3432 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3433 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3434 }
3435
3436 desc[4] = tess_offchip_va;
3437 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32);
3438 desc[6] = tess_offchip_ring_size;
3439 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3440 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3441 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3442 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3443
3444 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3445 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3446 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3447 S_008F0C_RESOURCE_LEVEL(1);
3448 } else {
3449 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3450 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3451 }
3452 }
3453
3454 desc += 8;
3455
3456 if (add_sample_positions) {
3457 /* add sample positions after all rings */
3458 memcpy(desc, queue->device->sample_locations_1x, 8);
3459 desc += 2;
3460 memcpy(desc, queue->device->sample_locations_2x, 16);
3461 desc += 4;
3462 memcpy(desc, queue->device->sample_locations_4x, 32);
3463 desc += 8;
3464 memcpy(desc, queue->device->sample_locations_8x, 64);
3465 }
3466 }
3467
3468 static unsigned
3469 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
3470 {
3471 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
3472 device->physical_device->rad_info.family != CHIP_CARRIZO &&
3473 device->physical_device->rad_info.family != CHIP_STONEY;
3474 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
3475 unsigned max_offchip_buffers;
3476 unsigned offchip_granularity;
3477 unsigned hs_offchip_param;
3478
3479 /*
3480 * Per RadeonSI:
3481 * This must be one less than the maximum number due to a hw limitation.
3482 * Various hardware bugs need thGFX7
3483 *
3484 * Per AMDVLK:
3485 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
3486 * Gfx7 should limit max_offchip_buffers to 508
3487 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
3488 *
3489 * Follow AMDVLK here.
3490 */
3491 if (device->physical_device->rad_info.chip_class >= GFX10) {
3492 max_offchip_buffers_per_se = 256;
3493 } else if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
3494 device->physical_device->rad_info.chip_class == GFX7 ||
3495 device->physical_device->rad_info.chip_class == GFX6)
3496 --max_offchip_buffers_per_se;
3497
3498 max_offchip_buffers = max_offchip_buffers_per_se *
3499 device->physical_device->rad_info.max_se;
3500
3501 /* Hawaii has a bug with offchip buffers > 256 that can be worked
3502 * around by setting 4K granularity.
3503 */
3504 if (device->tess_offchip_block_dw_size == 4096) {
3505 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
3506 offchip_granularity = V_03093C_X_4K_DWORDS;
3507 } else {
3508 assert(device->tess_offchip_block_dw_size == 8192);
3509 offchip_granularity = V_03093C_X_8K_DWORDS;
3510 }
3511
3512 switch (device->physical_device->rad_info.chip_class) {
3513 case GFX6:
3514 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
3515 break;
3516 case GFX7:
3517 case GFX8:
3518 case GFX9:
3519 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
3520 break;
3521 case GFX10:
3522 break;
3523 default:
3524 break;
3525 }
3526
3527 *max_offchip_buffers_p = max_offchip_buffers;
3528 if (device->physical_device->rad_info.chip_class >= GFX7) {
3529 if (device->physical_device->rad_info.chip_class >= GFX8)
3530 --max_offchip_buffers;
3531 hs_offchip_param =
3532 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
3533 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
3534 } else {
3535 hs_offchip_param =
3536 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
3537 }
3538 return hs_offchip_param;
3539 }
3540
3541 static void
3542 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3543 struct radeon_winsys_bo *esgs_ring_bo,
3544 uint32_t esgs_ring_size,
3545 struct radeon_winsys_bo *gsvs_ring_bo,
3546 uint32_t gsvs_ring_size)
3547 {
3548 if (!esgs_ring_bo && !gsvs_ring_bo)
3549 return;
3550
3551 if (esgs_ring_bo)
3552 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
3553
3554 if (gsvs_ring_bo)
3555 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
3556
3557 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
3558 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
3559 radeon_emit(cs, esgs_ring_size >> 8);
3560 radeon_emit(cs, gsvs_ring_size >> 8);
3561 } else {
3562 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
3563 radeon_emit(cs, esgs_ring_size >> 8);
3564 radeon_emit(cs, gsvs_ring_size >> 8);
3565 }
3566 }
3567
3568 static void
3569 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3570 unsigned hs_offchip_param, unsigned tf_ring_size,
3571 struct radeon_winsys_bo *tess_rings_bo)
3572 {
3573 uint64_t tf_va;
3574
3575 if (!tess_rings_bo)
3576 return;
3577
3578 tf_va = radv_buffer_get_va(tess_rings_bo);
3579
3580 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
3581
3582 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
3583 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
3584 S_030938_SIZE(tf_ring_size / 4));
3585 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
3586 tf_va >> 8);
3587
3588 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3589 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3590 S_030984_BASE_HI(tf_va >> 40));
3591 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
3592 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
3593 S_030944_BASE_HI(tf_va >> 40));
3594 }
3595 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
3596 hs_offchip_param);
3597 } else {
3598 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
3599 S_008988_SIZE(tf_ring_size / 4));
3600 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
3601 tf_va >> 8);
3602 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3603 hs_offchip_param);
3604 }
3605 }
3606
3607 static void
3608 radv_emit_graphics_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3609 uint32_t size_per_wave, uint32_t waves,
3610 struct radeon_winsys_bo *scratch_bo)
3611 {
3612 if (queue->queue_family_index != RADV_QUEUE_GENERAL)
3613 return;
3614
3615 if (!scratch_bo)
3616 return;
3617
3618 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
3619
3620 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3621 S_0286E8_WAVES(waves) |
3622 S_0286E8_WAVESIZE(round_up_u32(size_per_wave, 1024)));
3623 }
3624
3625 static void
3626 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3627 uint32_t size_per_wave, uint32_t waves,
3628 struct radeon_winsys_bo *compute_scratch_bo)
3629 {
3630 uint64_t scratch_va;
3631
3632 if (!compute_scratch_bo)
3633 return;
3634
3635 scratch_va = radv_buffer_get_va(compute_scratch_bo);
3636
3637 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
3638
3639 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
3640 radeon_emit(cs, scratch_va);
3641 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
3642 S_008F04_SWIZZLE_ENABLE(1));
3643
3644 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
3645 S_00B860_WAVES(waves) |
3646 S_00B860_WAVESIZE(round_up_u32(size_per_wave, 1024)));
3647 }
3648
3649 static void
3650 radv_emit_global_shader_pointers(struct radv_queue *queue,
3651 struct radeon_cmdbuf *cs,
3652 struct radeon_winsys_bo *descriptor_bo)
3653 {
3654 uint64_t va;
3655
3656 if (!descriptor_bo)
3657 return;
3658
3659 va = radv_buffer_get_va(descriptor_bo);
3660
3661 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
3662
3663 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3664 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3665 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3666 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
3667 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
3668
3669 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3670 radv_emit_shader_pointer(queue->device, cs, regs[i],
3671 va, true);
3672 }
3673 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
3674 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3675 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3676 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
3677 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
3678
3679 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3680 radv_emit_shader_pointer(queue->device, cs, regs[i],
3681 va, true);
3682 }
3683 } else {
3684 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3685 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3686 R_00B230_SPI_SHADER_USER_DATA_GS_0,
3687 R_00B330_SPI_SHADER_USER_DATA_ES_0,
3688 R_00B430_SPI_SHADER_USER_DATA_HS_0,
3689 R_00B530_SPI_SHADER_USER_DATA_LS_0};
3690
3691 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3692 radv_emit_shader_pointer(queue->device, cs, regs[i],
3693 va, true);
3694 }
3695 }
3696 }
3697
3698 static void
3699 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
3700 {
3701 struct radv_device *device = queue->device;
3702
3703 if (device->gfx_init) {
3704 uint64_t va = radv_buffer_get_va(device->gfx_init);
3705
3706 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
3707 radeon_emit(cs, va);
3708 radeon_emit(cs, va >> 32);
3709 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
3710
3711 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
3712 } else {
3713 si_emit_graphics(device, cs);
3714 }
3715 }
3716
3717 static void
3718 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
3719 {
3720 struct radv_physical_device *physical_device = queue->device->physical_device;
3721 si_emit_compute(physical_device, cs);
3722 }
3723
3724 static VkResult
3725 radv_get_preamble_cs(struct radv_queue *queue,
3726 uint32_t scratch_size_per_wave,
3727 uint32_t scratch_waves,
3728 uint32_t compute_scratch_size_per_wave,
3729 uint32_t compute_scratch_waves,
3730 uint32_t esgs_ring_size,
3731 uint32_t gsvs_ring_size,
3732 bool needs_tess_rings,
3733 bool needs_gds,
3734 bool needs_gds_oa,
3735 bool needs_sample_positions,
3736 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
3737 struct radeon_cmdbuf **initial_preamble_cs,
3738 struct radeon_cmdbuf **continue_preamble_cs)
3739 {
3740 struct radeon_winsys_bo *scratch_bo = NULL;
3741 struct radeon_winsys_bo *descriptor_bo = NULL;
3742 struct radeon_winsys_bo *compute_scratch_bo = NULL;
3743 struct radeon_winsys_bo *esgs_ring_bo = NULL;
3744 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
3745 struct radeon_winsys_bo *tess_rings_bo = NULL;
3746 struct radeon_winsys_bo *gds_bo = NULL;
3747 struct radeon_winsys_bo *gds_oa_bo = NULL;
3748 struct radeon_cmdbuf *dest_cs[3] = {0};
3749 bool add_tess_rings = false, add_gds = false, add_gds_oa = false, add_sample_positions = false;
3750 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
3751 unsigned max_offchip_buffers;
3752 unsigned hs_offchip_param = 0;
3753 unsigned tess_offchip_ring_offset;
3754 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
3755 if (!queue->has_tess_rings) {
3756 if (needs_tess_rings)
3757 add_tess_rings = true;
3758 }
3759 if (!queue->has_gds) {
3760 if (needs_gds)
3761 add_gds = true;
3762 }
3763 if (!queue->has_gds_oa) {
3764 if (needs_gds_oa)
3765 add_gds_oa = true;
3766 }
3767 if (!queue->has_sample_positions) {
3768 if (needs_sample_positions)
3769 add_sample_positions = true;
3770 }
3771 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
3772 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
3773 &max_offchip_buffers);
3774 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
3775 tess_offchip_ring_size = max_offchip_buffers *
3776 queue->device->tess_offchip_block_dw_size * 4;
3777
3778 scratch_size_per_wave = MAX2(scratch_size_per_wave, queue->scratch_size_per_wave);
3779 if (scratch_size_per_wave)
3780 scratch_waves = MIN2(scratch_waves, UINT32_MAX / scratch_size_per_wave);
3781 else
3782 scratch_waves = 0;
3783
3784 compute_scratch_size_per_wave = MAX2(compute_scratch_size_per_wave, queue->compute_scratch_size_per_wave);
3785 if (compute_scratch_size_per_wave)
3786 compute_scratch_waves = MIN2(compute_scratch_waves, UINT32_MAX / compute_scratch_size_per_wave);
3787 else
3788 compute_scratch_waves = 0;
3789
3790 if (scratch_size_per_wave <= queue->scratch_size_per_wave &&
3791 scratch_waves <= queue->scratch_waves &&
3792 compute_scratch_size_per_wave <= queue->compute_scratch_size_per_wave &&
3793 compute_scratch_waves <= queue->compute_scratch_waves &&
3794 esgs_ring_size <= queue->esgs_ring_size &&
3795 gsvs_ring_size <= queue->gsvs_ring_size &&
3796 !add_tess_rings && !add_gds && !add_gds_oa && !add_sample_positions &&
3797 queue->initial_preamble_cs) {
3798 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
3799 *initial_preamble_cs = queue->initial_preamble_cs;
3800 *continue_preamble_cs = queue->continue_preamble_cs;
3801 if (!scratch_size_per_wave && !compute_scratch_size_per_wave &&
3802 !esgs_ring_size && !gsvs_ring_size && !needs_tess_rings &&
3803 !needs_gds && !needs_gds_oa && !needs_sample_positions)
3804 *continue_preamble_cs = NULL;
3805 return VK_SUCCESS;
3806 }
3807
3808 uint32_t scratch_size = scratch_size_per_wave * scratch_waves;
3809 uint32_t queue_scratch_size = queue->scratch_size_per_wave * queue->scratch_waves;
3810 if (scratch_size > queue_scratch_size) {
3811 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
3812 scratch_size,
3813 4096,
3814 RADEON_DOMAIN_VRAM,
3815 ring_bo_flags,
3816 RADV_BO_PRIORITY_SCRATCH);
3817 if (!scratch_bo)
3818 goto fail;
3819 } else
3820 scratch_bo = queue->scratch_bo;
3821
3822 uint32_t compute_scratch_size = compute_scratch_size_per_wave * compute_scratch_waves;
3823 uint32_t compute_queue_scratch_size = queue->compute_scratch_size_per_wave * queue->compute_scratch_waves;
3824 if (compute_scratch_size > compute_queue_scratch_size) {
3825 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
3826 compute_scratch_size,
3827 4096,
3828 RADEON_DOMAIN_VRAM,
3829 ring_bo_flags,
3830 RADV_BO_PRIORITY_SCRATCH);
3831 if (!compute_scratch_bo)
3832 goto fail;
3833
3834 } else
3835 compute_scratch_bo = queue->compute_scratch_bo;
3836
3837 if (esgs_ring_size > queue->esgs_ring_size) {
3838 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
3839 esgs_ring_size,
3840 4096,
3841 RADEON_DOMAIN_VRAM,
3842 ring_bo_flags,
3843 RADV_BO_PRIORITY_SCRATCH);
3844 if (!esgs_ring_bo)
3845 goto fail;
3846 } else {
3847 esgs_ring_bo = queue->esgs_ring_bo;
3848 esgs_ring_size = queue->esgs_ring_size;
3849 }
3850
3851 if (gsvs_ring_size > queue->gsvs_ring_size) {
3852 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
3853 gsvs_ring_size,
3854 4096,
3855 RADEON_DOMAIN_VRAM,
3856 ring_bo_flags,
3857 RADV_BO_PRIORITY_SCRATCH);
3858 if (!gsvs_ring_bo)
3859 goto fail;
3860 } else {
3861 gsvs_ring_bo = queue->gsvs_ring_bo;
3862 gsvs_ring_size = queue->gsvs_ring_size;
3863 }
3864
3865 if (add_tess_rings) {
3866 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
3867 tess_offchip_ring_offset + tess_offchip_ring_size,
3868 256,
3869 RADEON_DOMAIN_VRAM,
3870 ring_bo_flags,
3871 RADV_BO_PRIORITY_SCRATCH);
3872 if (!tess_rings_bo)
3873 goto fail;
3874 } else {
3875 tess_rings_bo = queue->tess_rings_bo;
3876 }
3877
3878 if (add_gds) {
3879 assert(queue->device->physical_device->rad_info.chip_class >= GFX10);
3880
3881 /* 4 streamout GDS counters.
3882 * We need 256B (64 dw) of GDS, otherwise streamout hangs.
3883 */
3884 gds_bo = queue->device->ws->buffer_create(queue->device->ws,
3885 256, 4,
3886 RADEON_DOMAIN_GDS,
3887 ring_bo_flags,
3888 RADV_BO_PRIORITY_SCRATCH);
3889 if (!gds_bo)
3890 goto fail;
3891 } else {
3892 gds_bo = queue->gds_bo;
3893 }
3894
3895 if (add_gds_oa) {
3896 assert(queue->device->physical_device->rad_info.chip_class >= GFX10);
3897
3898 gds_oa_bo = queue->device->ws->buffer_create(queue->device->ws,
3899 4, 1,
3900 RADEON_DOMAIN_OA,
3901 ring_bo_flags,
3902 RADV_BO_PRIORITY_SCRATCH);
3903 if (!gds_oa_bo)
3904 goto fail;
3905 } else {
3906 gds_oa_bo = queue->gds_oa_bo;
3907 }
3908
3909 if (scratch_bo != queue->scratch_bo ||
3910 esgs_ring_bo != queue->esgs_ring_bo ||
3911 gsvs_ring_bo != queue->gsvs_ring_bo ||
3912 tess_rings_bo != queue->tess_rings_bo ||
3913 add_sample_positions) {
3914 uint32_t size = 0;
3915 if (gsvs_ring_bo || esgs_ring_bo ||
3916 tess_rings_bo || add_sample_positions) {
3917 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
3918 if (add_sample_positions)
3919 size += 128; /* 64+32+16+8 = 120 bytes */
3920 }
3921 else if (scratch_bo)
3922 size = 8; /* 2 dword */
3923
3924 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
3925 size,
3926 4096,
3927 RADEON_DOMAIN_VRAM,
3928 RADEON_FLAG_CPU_ACCESS |
3929 RADEON_FLAG_NO_INTERPROCESS_SHARING |
3930 RADEON_FLAG_READ_ONLY,
3931 RADV_BO_PRIORITY_DESCRIPTOR);
3932 if (!descriptor_bo)
3933 goto fail;
3934 } else
3935 descriptor_bo = queue->descriptor_bo;
3936
3937 if (descriptor_bo != queue->descriptor_bo) {
3938 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
3939
3940 if (scratch_bo) {
3941 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
3942 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
3943 S_008F04_SWIZZLE_ENABLE(1);
3944 map[0] = scratch_va;
3945 map[1] = rsrc1;
3946 }
3947
3948 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
3949 fill_geom_tess_rings(queue, map, add_sample_positions,
3950 esgs_ring_size, esgs_ring_bo,
3951 gsvs_ring_size, gsvs_ring_bo,
3952 tess_factor_ring_size,
3953 tess_offchip_ring_offset,
3954 tess_offchip_ring_size,
3955 tess_rings_bo);
3956
3957 queue->device->ws->buffer_unmap(descriptor_bo);
3958 }
3959
3960 for(int i = 0; i < 3; ++i) {
3961 struct radeon_cmdbuf *cs = NULL;
3962 cs = queue->device->ws->cs_create(queue->device->ws,
3963 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
3964 if (!cs)
3965 goto fail;
3966
3967 dest_cs[i] = cs;
3968
3969 if (scratch_bo)
3970 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
3971
3972 /* Emit initial configuration. */
3973 switch (queue->queue_family_index) {
3974 case RADV_QUEUE_GENERAL:
3975 radv_init_graphics_state(cs, queue);
3976 break;
3977 case RADV_QUEUE_COMPUTE:
3978 radv_init_compute_state(cs, queue);
3979 break;
3980 case RADV_QUEUE_TRANSFER:
3981 break;
3982 }
3983
3984 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
3985 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3986 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3987
3988 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3989 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3990 }
3991
3992 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
3993 gsvs_ring_bo, gsvs_ring_size);
3994 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
3995 tess_factor_ring_size, tess_rings_bo);
3996 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
3997 radv_emit_compute_scratch(queue, cs, compute_scratch_size_per_wave,
3998 compute_scratch_waves, compute_scratch_bo);
3999 radv_emit_graphics_scratch(queue, cs, scratch_size_per_wave,
4000 scratch_waves, scratch_bo);
4001
4002 if (gds_bo)
4003 radv_cs_add_buffer(queue->device->ws, cs, gds_bo);
4004 if (gds_oa_bo)
4005 radv_cs_add_buffer(queue->device->ws, cs, gds_oa_bo);
4006
4007 if (queue->device->trace_bo)
4008 radv_cs_add_buffer(queue->device->ws, cs, queue->device->trace_bo);
4009
4010 if (i == 0) {
4011 si_cs_emit_cache_flush(cs,
4012 queue->device->physical_device->rad_info.chip_class,
4013 NULL, 0,
4014 queue->queue_family_index == RING_COMPUTE &&
4015 queue->device->physical_device->rad_info.chip_class >= GFX7,
4016 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
4017 RADV_CMD_FLAG_INV_ICACHE |
4018 RADV_CMD_FLAG_INV_SCACHE |
4019 RADV_CMD_FLAG_INV_VCACHE |
4020 RADV_CMD_FLAG_INV_L2 |
4021 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
4022 } else if (i == 1) {
4023 si_cs_emit_cache_flush(cs,
4024 queue->device->physical_device->rad_info.chip_class,
4025 NULL, 0,
4026 queue->queue_family_index == RING_COMPUTE &&
4027 queue->device->physical_device->rad_info.chip_class >= GFX7,
4028 RADV_CMD_FLAG_INV_ICACHE |
4029 RADV_CMD_FLAG_INV_SCACHE |
4030 RADV_CMD_FLAG_INV_VCACHE |
4031 RADV_CMD_FLAG_INV_L2 |
4032 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
4033 }
4034
4035 if (!queue->device->ws->cs_finalize(cs))
4036 goto fail;
4037 }
4038
4039 if (queue->initial_full_flush_preamble_cs)
4040 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
4041
4042 if (queue->initial_preamble_cs)
4043 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
4044
4045 if (queue->continue_preamble_cs)
4046 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
4047
4048 queue->initial_full_flush_preamble_cs = dest_cs[0];
4049 queue->initial_preamble_cs = dest_cs[1];
4050 queue->continue_preamble_cs = dest_cs[2];
4051
4052 if (scratch_bo != queue->scratch_bo) {
4053 if (queue->scratch_bo)
4054 queue->device->ws->buffer_destroy(queue->scratch_bo);
4055 queue->scratch_bo = scratch_bo;
4056 }
4057 queue->scratch_size_per_wave = scratch_size_per_wave;
4058 queue->scratch_waves = scratch_waves;
4059
4060 if (compute_scratch_bo != queue->compute_scratch_bo) {
4061 if (queue->compute_scratch_bo)
4062 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
4063 queue->compute_scratch_bo = compute_scratch_bo;
4064 }
4065 queue->compute_scratch_size_per_wave = compute_scratch_size_per_wave;
4066 queue->compute_scratch_waves = compute_scratch_waves;
4067
4068 if (esgs_ring_bo != queue->esgs_ring_bo) {
4069 if (queue->esgs_ring_bo)
4070 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
4071 queue->esgs_ring_bo = esgs_ring_bo;
4072 queue->esgs_ring_size = esgs_ring_size;
4073 }
4074
4075 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
4076 if (queue->gsvs_ring_bo)
4077 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
4078 queue->gsvs_ring_bo = gsvs_ring_bo;
4079 queue->gsvs_ring_size = gsvs_ring_size;
4080 }
4081
4082 if (tess_rings_bo != queue->tess_rings_bo) {
4083 queue->tess_rings_bo = tess_rings_bo;
4084 queue->has_tess_rings = true;
4085 }
4086
4087 if (gds_bo != queue->gds_bo) {
4088 queue->gds_bo = gds_bo;
4089 queue->has_gds = true;
4090 }
4091
4092 if (gds_oa_bo != queue->gds_oa_bo) {
4093 queue->gds_oa_bo = gds_oa_bo;
4094 queue->has_gds_oa = true;
4095 }
4096
4097 if (descriptor_bo != queue->descriptor_bo) {
4098 if (queue->descriptor_bo)
4099 queue->device->ws->buffer_destroy(queue->descriptor_bo);
4100
4101 queue->descriptor_bo = descriptor_bo;
4102 }
4103
4104 if (add_sample_positions)
4105 queue->has_sample_positions = true;
4106
4107 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
4108 *initial_preamble_cs = queue->initial_preamble_cs;
4109 *continue_preamble_cs = queue->continue_preamble_cs;
4110 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
4111 *continue_preamble_cs = NULL;
4112 return VK_SUCCESS;
4113 fail:
4114 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
4115 if (dest_cs[i])
4116 queue->device->ws->cs_destroy(dest_cs[i]);
4117 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
4118 queue->device->ws->buffer_destroy(descriptor_bo);
4119 if (scratch_bo && scratch_bo != queue->scratch_bo)
4120 queue->device->ws->buffer_destroy(scratch_bo);
4121 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
4122 queue->device->ws->buffer_destroy(compute_scratch_bo);
4123 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
4124 queue->device->ws->buffer_destroy(esgs_ring_bo);
4125 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
4126 queue->device->ws->buffer_destroy(gsvs_ring_bo);
4127 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
4128 queue->device->ws->buffer_destroy(tess_rings_bo);
4129 if (gds_bo && gds_bo != queue->gds_bo)
4130 queue->device->ws->buffer_destroy(gds_bo);
4131 if (gds_oa_bo && gds_oa_bo != queue->gds_oa_bo)
4132 queue->device->ws->buffer_destroy(gds_oa_bo);
4133
4134 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4135 }
4136
4137 static VkResult radv_alloc_sem_counts(struct radv_device *device,
4138 struct radv_winsys_sem_counts *counts,
4139 int num_sems,
4140 struct radv_semaphore_part **sems,
4141 const uint64_t *timeline_values,
4142 VkFence _fence,
4143 bool is_signal)
4144 {
4145 int syncobj_idx = 0, sem_idx = 0;
4146
4147 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
4148 return VK_SUCCESS;
4149
4150 for (uint32_t i = 0; i < num_sems; i++) {
4151 switch(sems[i]->kind) {
4152 case RADV_SEMAPHORE_SYNCOBJ:
4153 counts->syncobj_count++;
4154 break;
4155 case RADV_SEMAPHORE_WINSYS:
4156 counts->sem_count++;
4157 break;
4158 case RADV_SEMAPHORE_NONE:
4159 break;
4160 case RADV_SEMAPHORE_TIMELINE:
4161 counts->syncobj_count++;
4162 break;
4163 }
4164 }
4165
4166 if (_fence != VK_NULL_HANDLE) {
4167 RADV_FROM_HANDLE(radv_fence, fence, _fence);
4168 if (fence->temp_syncobj || fence->syncobj)
4169 counts->syncobj_count++;
4170 }
4171
4172 if (counts->syncobj_count) {
4173 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
4174 if (!counts->syncobj)
4175 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4176 }
4177
4178 if (counts->sem_count) {
4179 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
4180 if (!counts->sem) {
4181 free(counts->syncobj);
4182 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4183 }
4184 }
4185
4186 for (uint32_t i = 0; i < num_sems; i++) {
4187 switch(sems[i]->kind) {
4188 case RADV_SEMAPHORE_NONE:
4189 unreachable("Empty semaphore");
4190 break;
4191 case RADV_SEMAPHORE_SYNCOBJ:
4192 counts->syncobj[syncobj_idx++] = sems[i]->syncobj;
4193 break;
4194 case RADV_SEMAPHORE_WINSYS:
4195 counts->sem[sem_idx++] = sems[i]->ws_sem;
4196 break;
4197 case RADV_SEMAPHORE_TIMELINE: {
4198 pthread_mutex_lock(&sems[i]->timeline.mutex);
4199 struct radv_timeline_point *point = NULL;
4200 if (is_signal) {
4201 point = radv_timeline_add_point_locked(device, &sems[i]->timeline, timeline_values[i]);
4202 } else {
4203 point = radv_timeline_find_point_at_least_locked(device, &sems[i]->timeline, timeline_values[i]);
4204 }
4205
4206 pthread_mutex_unlock(&sems[i]->timeline.mutex);
4207
4208 if (point) {
4209 counts->syncobj[syncobj_idx++] = point->syncobj;
4210 } else {
4211 /* Explicitly remove the semaphore so we might not find
4212 * a point later post-submit. */
4213 sems[i] = NULL;
4214 }
4215 break;
4216 }
4217 }
4218 }
4219
4220 if (_fence != VK_NULL_HANDLE) {
4221 RADV_FROM_HANDLE(radv_fence, fence, _fence);
4222 if (fence->temp_syncobj)
4223 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
4224 else if (fence->syncobj)
4225 counts->syncobj[syncobj_idx++] = fence->syncobj;
4226 }
4227
4228 assert(syncobj_idx <= counts->syncobj_count);
4229 counts->syncobj_count = syncobj_idx;
4230
4231 return VK_SUCCESS;
4232 }
4233
4234 static void
4235 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
4236 {
4237 free(sem_info->wait.syncobj);
4238 free(sem_info->wait.sem);
4239 free(sem_info->signal.syncobj);
4240 free(sem_info->signal.sem);
4241 }
4242
4243
4244 static void radv_free_temp_syncobjs(struct radv_device *device,
4245 int num_sems,
4246 struct radv_semaphore_part *sems)
4247 {
4248 for (uint32_t i = 0; i < num_sems; i++) {
4249 radv_destroy_semaphore_part(device, sems + i);
4250 }
4251 }
4252
4253 static VkResult
4254 radv_alloc_sem_info(struct radv_device *device,
4255 struct radv_winsys_sem_info *sem_info,
4256 int num_wait_sems,
4257 struct radv_semaphore_part **wait_sems,
4258 const uint64_t *wait_values,
4259 int num_signal_sems,
4260 struct radv_semaphore_part **signal_sems,
4261 const uint64_t *signal_values,
4262 VkFence fence)
4263 {
4264 VkResult ret;
4265 memset(sem_info, 0, sizeof(*sem_info));
4266
4267 ret = radv_alloc_sem_counts(device, &sem_info->wait, num_wait_sems, wait_sems, wait_values, VK_NULL_HANDLE, false);
4268 if (ret)
4269 return ret;
4270 ret = radv_alloc_sem_counts(device, &sem_info->signal, num_signal_sems, signal_sems, signal_values, fence, true);
4271 if (ret)
4272 radv_free_sem_info(sem_info);
4273
4274 /* caller can override these */
4275 sem_info->cs_emit_wait = true;
4276 sem_info->cs_emit_signal = true;
4277 return ret;
4278 }
4279
4280 static void
4281 radv_finalize_timelines(struct radv_device *device,
4282 uint32_t num_wait_sems,
4283 struct radv_semaphore_part **wait_sems,
4284 const uint64_t *wait_values,
4285 uint32_t num_signal_sems,
4286 struct radv_semaphore_part **signal_sems,
4287 const uint64_t *signal_values,
4288 struct list_head *processing_list)
4289 {
4290 for (uint32_t i = 0; i < num_wait_sems; ++i) {
4291 if (wait_sems[i] && wait_sems[i]->kind == RADV_SEMAPHORE_TIMELINE) {
4292 pthread_mutex_lock(&wait_sems[i]->timeline.mutex);
4293 struct radv_timeline_point *point =
4294 radv_timeline_find_point_at_least_locked(device, &wait_sems[i]->timeline, wait_values[i]);
4295 point->wait_count -= 2;
4296 pthread_mutex_unlock(&wait_sems[i]->timeline.mutex);
4297 }
4298 }
4299 for (uint32_t i = 0; i < num_signal_sems; ++i) {
4300 if (signal_sems[i] && signal_sems[i]->kind == RADV_SEMAPHORE_TIMELINE) {
4301 pthread_mutex_lock(&signal_sems[i]->timeline.mutex);
4302 struct radv_timeline_point *point =
4303 radv_timeline_find_point_at_least_locked(device, &signal_sems[i]->timeline, signal_values[i]);
4304 signal_sems[i]->timeline.highest_submitted =
4305 MAX2(signal_sems[i]->timeline.highest_submitted, point->value);
4306 point->wait_count -= 2;
4307 radv_timeline_trigger_waiters_locked(&signal_sems[i]->timeline, processing_list);
4308 pthread_mutex_unlock(&signal_sems[i]->timeline.mutex);
4309 }
4310 }
4311 }
4312
4313 static void
4314 radv_sparse_buffer_bind_memory(struct radv_device *device,
4315 const VkSparseBufferMemoryBindInfo *bind)
4316 {
4317 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
4318
4319 for (uint32_t i = 0; i < bind->bindCount; ++i) {
4320 struct radv_device_memory *mem = NULL;
4321
4322 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
4323 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
4324
4325 device->ws->buffer_virtual_bind(buffer->bo,
4326 bind->pBinds[i].resourceOffset,
4327 bind->pBinds[i].size,
4328 mem ? mem->bo : NULL,
4329 bind->pBinds[i].memoryOffset);
4330 }
4331 }
4332
4333 static void
4334 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
4335 const VkSparseImageOpaqueMemoryBindInfo *bind)
4336 {
4337 RADV_FROM_HANDLE(radv_image, image, bind->image);
4338
4339 for (uint32_t i = 0; i < bind->bindCount; ++i) {
4340 struct radv_device_memory *mem = NULL;
4341
4342 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
4343 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
4344
4345 device->ws->buffer_virtual_bind(image->bo,
4346 bind->pBinds[i].resourceOffset,
4347 bind->pBinds[i].size,
4348 mem ? mem->bo : NULL,
4349 bind->pBinds[i].memoryOffset);
4350 }
4351 }
4352
4353 static VkResult
4354 radv_get_preambles(struct radv_queue *queue,
4355 const VkCommandBuffer *cmd_buffers,
4356 uint32_t cmd_buffer_count,
4357 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
4358 struct radeon_cmdbuf **initial_preamble_cs,
4359 struct radeon_cmdbuf **continue_preamble_cs)
4360 {
4361 uint32_t scratch_size_per_wave = 0, waves_wanted = 0;
4362 uint32_t compute_scratch_size_per_wave = 0, compute_waves_wanted = 0;
4363 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
4364 bool tess_rings_needed = false;
4365 bool gds_needed = false;
4366 bool gds_oa_needed = false;
4367 bool sample_positions_needed = false;
4368
4369 for (uint32_t j = 0; j < cmd_buffer_count; j++) {
4370 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
4371 cmd_buffers[j]);
4372
4373 scratch_size_per_wave = MAX2(scratch_size_per_wave, cmd_buffer->scratch_size_per_wave_needed);
4374 waves_wanted = MAX2(waves_wanted, cmd_buffer->scratch_waves_wanted);
4375 compute_scratch_size_per_wave = MAX2(compute_scratch_size_per_wave,
4376 cmd_buffer->compute_scratch_size_per_wave_needed);
4377 compute_waves_wanted = MAX2(compute_waves_wanted,
4378 cmd_buffer->compute_scratch_waves_wanted);
4379 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
4380 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
4381 tess_rings_needed |= cmd_buffer->tess_rings_needed;
4382 gds_needed |= cmd_buffer->gds_needed;
4383 gds_oa_needed |= cmd_buffer->gds_oa_needed;
4384 sample_positions_needed |= cmd_buffer->sample_positions_needed;
4385 }
4386
4387 return radv_get_preamble_cs(queue, scratch_size_per_wave, waves_wanted,
4388 compute_scratch_size_per_wave, compute_waves_wanted,
4389 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
4390 gds_needed, gds_oa_needed, sample_positions_needed,
4391 initial_full_flush_preamble_cs,
4392 initial_preamble_cs, continue_preamble_cs);
4393 }
4394
4395 struct radv_deferred_queue_submission {
4396 struct radv_queue *queue;
4397 VkCommandBuffer *cmd_buffers;
4398 uint32_t cmd_buffer_count;
4399
4400 /* Sparse bindings that happen on a queue. */
4401 VkSparseBufferMemoryBindInfo *buffer_binds;
4402 uint32_t buffer_bind_count;
4403 VkSparseImageOpaqueMemoryBindInfo *image_opaque_binds;
4404 uint32_t image_opaque_bind_count;
4405
4406 bool flush_caches;
4407 VkShaderStageFlags wait_dst_stage_mask;
4408 struct radv_semaphore_part **wait_semaphores;
4409 uint32_t wait_semaphore_count;
4410 struct radv_semaphore_part **signal_semaphores;
4411 uint32_t signal_semaphore_count;
4412 VkFence fence;
4413
4414 uint64_t *wait_values;
4415 uint64_t *signal_values;
4416
4417 struct radv_semaphore_part *temporary_semaphore_parts;
4418 uint32_t temporary_semaphore_part_count;
4419
4420 struct list_head queue_pending_list;
4421 uint32_t submission_wait_count;
4422 struct radv_timeline_waiter *wait_nodes;
4423
4424 struct list_head processing_list;
4425 };
4426
4427 struct radv_queue_submission {
4428 const VkCommandBuffer *cmd_buffers;
4429 uint32_t cmd_buffer_count;
4430
4431 /* Sparse bindings that happen on a queue. */
4432 const VkSparseBufferMemoryBindInfo *buffer_binds;
4433 uint32_t buffer_bind_count;
4434 const VkSparseImageOpaqueMemoryBindInfo *image_opaque_binds;
4435 uint32_t image_opaque_bind_count;
4436
4437 bool flush_caches;
4438 VkPipelineStageFlags wait_dst_stage_mask;
4439 const VkSemaphore *wait_semaphores;
4440 uint32_t wait_semaphore_count;
4441 const VkSemaphore *signal_semaphores;
4442 uint32_t signal_semaphore_count;
4443 VkFence fence;
4444
4445 const uint64_t *wait_values;
4446 uint32_t wait_value_count;
4447 const uint64_t *signal_values;
4448 uint32_t signal_value_count;
4449 };
4450
4451 static VkResult
4452 radv_create_deferred_submission(struct radv_queue *queue,
4453 const struct radv_queue_submission *submission,
4454 struct radv_deferred_queue_submission **out)
4455 {
4456 struct radv_deferred_queue_submission *deferred = NULL;
4457 size_t size = sizeof(struct radv_deferred_queue_submission);
4458
4459 uint32_t temporary_count = 0;
4460 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4461 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->wait_semaphores[i]);
4462 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE)
4463 ++temporary_count;
4464 }
4465
4466 size += submission->cmd_buffer_count * sizeof(VkCommandBuffer);
4467 size += submission->buffer_bind_count * sizeof(VkSparseBufferMemoryBindInfo);
4468 size += submission->image_opaque_bind_count * sizeof(VkSparseImageOpaqueMemoryBindInfo);
4469 size += submission->wait_semaphore_count * sizeof(struct radv_semaphore_part *);
4470 size += temporary_count * sizeof(struct radv_semaphore_part);
4471 size += submission->signal_semaphore_count * sizeof(struct radv_semaphore_part *);
4472 size += submission->wait_value_count * sizeof(uint64_t);
4473 size += submission->signal_value_count * sizeof(uint64_t);
4474 size += submission->wait_semaphore_count * sizeof(struct radv_timeline_waiter);
4475
4476 deferred = calloc(1, size);
4477 if (!deferred)
4478 return VK_ERROR_OUT_OF_HOST_MEMORY;
4479
4480 deferred->queue = queue;
4481
4482 deferred->cmd_buffers = (void*)(deferred + 1);
4483 deferred->cmd_buffer_count = submission->cmd_buffer_count;
4484 memcpy(deferred->cmd_buffers, submission->cmd_buffers,
4485 submission->cmd_buffer_count * sizeof(*deferred->cmd_buffers));
4486
4487 deferred->buffer_binds = (void*)(deferred->cmd_buffers + submission->cmd_buffer_count);
4488 deferred->buffer_bind_count = submission->buffer_bind_count;
4489 memcpy(deferred->buffer_binds, submission->buffer_binds,
4490 submission->buffer_bind_count * sizeof(*deferred->buffer_binds));
4491
4492 deferred->image_opaque_binds = (void*)(deferred->buffer_binds + submission->buffer_bind_count);
4493 deferred->image_opaque_bind_count = submission->image_opaque_bind_count;
4494 memcpy(deferred->image_opaque_binds, submission->image_opaque_binds,
4495 submission->image_opaque_bind_count * sizeof(*deferred->image_opaque_binds));
4496
4497 deferred->flush_caches = submission->flush_caches;
4498 deferred->wait_dst_stage_mask = submission->wait_dst_stage_mask;
4499
4500 deferred->wait_semaphores = (void*)(deferred->image_opaque_binds + deferred->image_opaque_bind_count);
4501 deferred->wait_semaphore_count = submission->wait_semaphore_count;
4502
4503 deferred->signal_semaphores = (void*)(deferred->wait_semaphores + deferred->wait_semaphore_count);
4504 deferred->signal_semaphore_count = submission->signal_semaphore_count;
4505
4506 deferred->fence = submission->fence;
4507
4508 deferred->temporary_semaphore_parts = (void*)(deferred->signal_semaphores + deferred->signal_semaphore_count);
4509 deferred->temporary_semaphore_part_count = temporary_count;
4510
4511 uint32_t temporary_idx = 0;
4512 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4513 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->wait_semaphores[i]);
4514 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE) {
4515 deferred->wait_semaphores[i] = &deferred->temporary_semaphore_parts[temporary_idx];
4516 deferred->temporary_semaphore_parts[temporary_idx] = semaphore->temporary;
4517 semaphore->temporary.kind = RADV_SEMAPHORE_NONE;
4518 ++temporary_idx;
4519 } else
4520 deferred->wait_semaphores[i] = &semaphore->permanent;
4521 }
4522
4523 for (uint32_t i = 0; i < submission->signal_semaphore_count; ++i) {
4524 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->signal_semaphores[i]);
4525 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE) {
4526 deferred->signal_semaphores[i] = &semaphore->temporary;
4527 } else {
4528 deferred->signal_semaphores[i] = &semaphore->permanent;
4529 }
4530 }
4531
4532 deferred->wait_values = (void*)(deferred->temporary_semaphore_parts + temporary_count);
4533 memcpy(deferred->wait_values, submission->wait_values, submission->wait_value_count * sizeof(uint64_t));
4534 deferred->signal_values = deferred->wait_values + submission->wait_value_count;
4535 memcpy(deferred->signal_values, submission->signal_values, submission->signal_value_count * sizeof(uint64_t));
4536
4537 deferred->wait_nodes = (void*)(deferred->signal_values + submission->signal_value_count);
4538 /* This is worst-case. radv_queue_enqueue_submission will fill in further, but this
4539 * ensure the submission is not accidentally triggered early when adding wait timelines. */
4540 deferred->submission_wait_count = 1 + submission->wait_semaphore_count;
4541
4542 *out = deferred;
4543 return VK_SUCCESS;
4544 }
4545
4546 static void
4547 radv_queue_enqueue_submission(struct radv_deferred_queue_submission *submission,
4548 struct list_head *processing_list)
4549 {
4550 uint32_t wait_cnt = 0;
4551 struct radv_timeline_waiter *waiter = submission->wait_nodes;
4552 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4553 if (submission->wait_semaphores[i]->kind == RADV_SEMAPHORE_TIMELINE) {
4554 pthread_mutex_lock(&submission->wait_semaphores[i]->timeline.mutex);
4555 if (submission->wait_semaphores[i]->timeline.highest_submitted < submission->wait_values[i]) {
4556 ++wait_cnt;
4557 waiter->value = submission->wait_values[i];
4558 waiter->submission = submission;
4559 list_addtail(&waiter->list, &submission->wait_semaphores[i]->timeline.waiters);
4560 ++waiter;
4561 }
4562 pthread_mutex_unlock(&submission->wait_semaphores[i]->timeline.mutex);
4563 }
4564 }
4565
4566 pthread_mutex_lock(&submission->queue->pending_mutex);
4567
4568 bool is_first = list_is_empty(&submission->queue->pending_submissions);
4569 list_addtail(&submission->queue_pending_list, &submission->queue->pending_submissions);
4570
4571 pthread_mutex_unlock(&submission->queue->pending_mutex);
4572
4573 /* If there is already a submission in the queue, that will decrement the counter by 1 when
4574 * submitted, but if the queue was empty, we decrement ourselves as there is no previous
4575 * submission. */
4576 uint32_t decrement = submission->wait_semaphore_count - wait_cnt + (is_first ? 1 : 0);
4577 if (__atomic_sub_fetch(&submission->submission_wait_count, decrement, __ATOMIC_ACQ_REL) == 0) {
4578 list_addtail(&submission->processing_list, processing_list);
4579 }
4580 }
4581
4582 static void
4583 radv_queue_submission_update_queue(struct radv_deferred_queue_submission *submission,
4584 struct list_head *processing_list)
4585 {
4586 pthread_mutex_lock(&submission->queue->pending_mutex);
4587 list_del(&submission->queue_pending_list);
4588
4589 /* trigger the next submission in the queue. */
4590 if (!list_is_empty(&submission->queue->pending_submissions)) {
4591 struct radv_deferred_queue_submission *next_submission =
4592 list_first_entry(&submission->queue->pending_submissions,
4593 struct radv_deferred_queue_submission,
4594 queue_pending_list);
4595 if (p_atomic_dec_zero(&next_submission->submission_wait_count)) {
4596 list_addtail(&next_submission->processing_list, processing_list);
4597 }
4598 }
4599 pthread_mutex_unlock(&submission->queue->pending_mutex);
4600
4601 pthread_cond_broadcast(&submission->queue->device->timeline_cond);
4602 }
4603
4604 static VkResult
4605 radv_queue_submit_deferred(struct radv_deferred_queue_submission *submission,
4606 struct list_head *processing_list)
4607 {
4608 RADV_FROM_HANDLE(radv_fence, fence, submission->fence);
4609 struct radv_queue *queue = submission->queue;
4610 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
4611 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
4612 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
4613 bool do_flush = submission->flush_caches || submission->wait_dst_stage_mask;
4614 bool can_patch = true;
4615 uint32_t advance;
4616 struct radv_winsys_sem_info sem_info;
4617 VkResult result;
4618 int ret;
4619 struct radeon_cmdbuf *initial_preamble_cs = NULL;
4620 struct radeon_cmdbuf *initial_flush_preamble_cs = NULL;
4621 struct radeon_cmdbuf *continue_preamble_cs = NULL;
4622
4623 result = radv_get_preambles(queue, submission->cmd_buffers,
4624 submission->cmd_buffer_count,
4625 &initial_preamble_cs,
4626 &initial_flush_preamble_cs,
4627 &continue_preamble_cs);
4628 if (result != VK_SUCCESS)
4629 goto fail;
4630
4631 result = radv_alloc_sem_info(queue->device,
4632 &sem_info,
4633 submission->wait_semaphore_count,
4634 submission->wait_semaphores,
4635 submission->wait_values,
4636 submission->signal_semaphore_count,
4637 submission->signal_semaphores,
4638 submission->signal_values,
4639 submission->fence);
4640 if (result != VK_SUCCESS)
4641 goto fail;
4642
4643 for (uint32_t i = 0; i < submission->buffer_bind_count; ++i) {
4644 radv_sparse_buffer_bind_memory(queue->device,
4645 submission->buffer_binds + i);
4646 }
4647
4648 for (uint32_t i = 0; i < submission->image_opaque_bind_count; ++i) {
4649 radv_sparse_image_opaque_bind_memory(queue->device,
4650 submission->image_opaque_binds + i);
4651 }
4652
4653 if (!submission->cmd_buffer_count) {
4654 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
4655 &queue->device->empty_cs[queue->queue_family_index],
4656 1, NULL, NULL,
4657 &sem_info, NULL,
4658 false, base_fence);
4659 if (ret) {
4660 radv_loge("failed to submit CS\n");
4661 abort();
4662 }
4663
4664 goto success;
4665 } else {
4666 struct radeon_cmdbuf **cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
4667 (submission->cmd_buffer_count));
4668
4669 for (uint32_t j = 0; j < submission->cmd_buffer_count; j++) {
4670 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, submission->cmd_buffers[j]);
4671 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
4672
4673 cs_array[j] = cmd_buffer->cs;
4674 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
4675 can_patch = false;
4676
4677 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
4678 }
4679
4680 for (uint32_t j = 0; j < submission->cmd_buffer_count; j += advance) {
4681 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
4682 const struct radv_winsys_bo_list *bo_list = NULL;
4683
4684 advance = MIN2(max_cs_submission,
4685 submission->cmd_buffer_count - j);
4686
4687 if (queue->device->trace_bo)
4688 *queue->device->trace_id_ptr = 0;
4689
4690 sem_info.cs_emit_wait = j == 0;
4691 sem_info.cs_emit_signal = j + advance == submission->cmd_buffer_count;
4692
4693 if (unlikely(queue->device->use_global_bo_list)) {
4694 pthread_mutex_lock(&queue->device->bo_list.mutex);
4695 bo_list = &queue->device->bo_list.list;
4696 }
4697
4698 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
4699 advance, initial_preamble, continue_preamble_cs,
4700 &sem_info, bo_list,
4701 can_patch, base_fence);
4702
4703 if (unlikely(queue->device->use_global_bo_list))
4704 pthread_mutex_unlock(&queue->device->bo_list.mutex);
4705
4706 if (ret) {
4707 radv_loge("failed to submit CS\n");
4708 abort();
4709 }
4710 if (queue->device->trace_bo) {
4711 radv_check_gpu_hangs(queue, cs_array[j]);
4712 }
4713 }
4714
4715 free(cs_array);
4716 }
4717
4718 success:
4719 radv_free_temp_syncobjs(queue->device,
4720 submission->temporary_semaphore_part_count,
4721 submission->temporary_semaphore_parts);
4722 radv_finalize_timelines(queue->device,
4723 submission->wait_semaphore_count,
4724 submission->wait_semaphores,
4725 submission->wait_values,
4726 submission->signal_semaphore_count,
4727 submission->signal_semaphores,
4728 submission->signal_values,
4729 processing_list);
4730 /* Has to happen after timeline finalization to make sure the
4731 * condition variable is only triggered when timelines and queue have
4732 * been updated. */
4733 radv_queue_submission_update_queue(submission, processing_list);
4734 radv_free_sem_info(&sem_info);
4735 free(submission);
4736 return VK_SUCCESS;
4737
4738 fail:
4739 radv_free_temp_syncobjs(queue->device,
4740 submission->temporary_semaphore_part_count,
4741 submission->temporary_semaphore_parts);
4742 free(submission);
4743 return VK_ERROR_DEVICE_LOST;
4744 }
4745
4746 static VkResult
4747 radv_process_submissions(struct list_head *processing_list)
4748 {
4749 while(!list_is_empty(processing_list)) {
4750 struct radv_deferred_queue_submission *submission =
4751 list_first_entry(processing_list, struct radv_deferred_queue_submission, processing_list);
4752 list_del(&submission->processing_list);
4753
4754 VkResult result = radv_queue_submit_deferred(submission, processing_list);
4755 if (result != VK_SUCCESS)
4756 return result;
4757 }
4758 return VK_SUCCESS;
4759 }
4760
4761 static VkResult radv_queue_submit(struct radv_queue *queue,
4762 const struct radv_queue_submission *submission)
4763 {
4764 struct radv_deferred_queue_submission *deferred = NULL;
4765
4766 VkResult result = radv_create_deferred_submission(queue, submission, &deferred);
4767 if (result != VK_SUCCESS)
4768 return result;
4769
4770 struct list_head processing_list;
4771 list_inithead(&processing_list);
4772
4773 radv_queue_enqueue_submission(deferred, &processing_list);
4774 return radv_process_submissions(&processing_list);
4775 }
4776
4777 bool
4778 radv_queue_internal_submit(struct radv_queue *queue, struct radeon_cmdbuf *cs)
4779 {
4780 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
4781 struct radv_winsys_sem_info sem_info;
4782 VkResult result;
4783 int ret;
4784
4785 result = radv_alloc_sem_info(queue->device, &sem_info, 0, NULL, 0, 0,
4786 0, NULL, VK_NULL_HANDLE);
4787 if (result != VK_SUCCESS)
4788 return false;
4789
4790 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, &cs, 1, NULL,
4791 NULL, &sem_info, NULL, false, NULL);
4792 radv_free_sem_info(&sem_info);
4793 return !ret;
4794 }
4795
4796 /* Signals fence as soon as all the work currently put on queue is done. */
4797 static VkResult radv_signal_fence(struct radv_queue *queue,
4798 VkFence fence)
4799 {
4800 return radv_queue_submit(queue, &(struct radv_queue_submission) {
4801 .fence = fence
4802 });
4803 }
4804
4805 static bool radv_submit_has_effects(const VkSubmitInfo *info)
4806 {
4807 return info->commandBufferCount ||
4808 info->waitSemaphoreCount ||
4809 info->signalSemaphoreCount;
4810 }
4811
4812 VkResult radv_QueueSubmit(
4813 VkQueue _queue,
4814 uint32_t submitCount,
4815 const VkSubmitInfo* pSubmits,
4816 VkFence fence)
4817 {
4818 RADV_FROM_HANDLE(radv_queue, queue, _queue);
4819 VkResult result;
4820 uint32_t fence_idx = 0;
4821 bool flushed_caches = false;
4822
4823 if (fence != VK_NULL_HANDLE) {
4824 for (uint32_t i = 0; i < submitCount; ++i)
4825 if (radv_submit_has_effects(pSubmits + i))
4826 fence_idx = i;
4827 } else
4828 fence_idx = UINT32_MAX;
4829
4830 for (uint32_t i = 0; i < submitCount; i++) {
4831 if (!radv_submit_has_effects(pSubmits + i) && fence_idx != i)
4832 continue;
4833
4834 VkPipelineStageFlags wait_dst_stage_mask = 0;
4835 for (unsigned j = 0; j < pSubmits[i].waitSemaphoreCount; ++j) {
4836 wait_dst_stage_mask |= pSubmits[i].pWaitDstStageMask[j];
4837 }
4838
4839 const VkTimelineSemaphoreSubmitInfo *timeline_info =
4840 vk_find_struct_const(pSubmits[i].pNext, TIMELINE_SEMAPHORE_SUBMIT_INFO);
4841
4842 result = radv_queue_submit(queue, &(struct radv_queue_submission) {
4843 .cmd_buffers = pSubmits[i].pCommandBuffers,
4844 .cmd_buffer_count = pSubmits[i].commandBufferCount,
4845 .wait_dst_stage_mask = wait_dst_stage_mask,
4846 .flush_caches = !flushed_caches,
4847 .wait_semaphores = pSubmits[i].pWaitSemaphores,
4848 .wait_semaphore_count = pSubmits[i].waitSemaphoreCount,
4849 .signal_semaphores = pSubmits[i].pSignalSemaphores,
4850 .signal_semaphore_count = pSubmits[i].signalSemaphoreCount,
4851 .fence = i == fence_idx ? fence : VK_NULL_HANDLE,
4852 .wait_values = timeline_info ? timeline_info->pWaitSemaphoreValues : NULL,
4853 .wait_value_count = timeline_info && timeline_info->pWaitSemaphoreValues ? timeline_info->waitSemaphoreValueCount : 0,
4854 .signal_values = timeline_info ? timeline_info->pSignalSemaphoreValues : NULL,
4855 .signal_value_count = timeline_info && timeline_info->pSignalSemaphoreValues ? timeline_info->signalSemaphoreValueCount : 0,
4856 });
4857 if (result != VK_SUCCESS)
4858 return result;
4859
4860 flushed_caches = true;
4861 }
4862
4863 if (fence != VK_NULL_HANDLE && !submitCount) {
4864 result = radv_signal_fence(queue, fence);
4865 if (result != VK_SUCCESS)
4866 return result;
4867 }
4868
4869 return VK_SUCCESS;
4870 }
4871
4872 VkResult radv_QueueWaitIdle(
4873 VkQueue _queue)
4874 {
4875 RADV_FROM_HANDLE(radv_queue, queue, _queue);
4876
4877 pthread_mutex_lock(&queue->pending_mutex);
4878 while (!list_is_empty(&queue->pending_submissions)) {
4879 pthread_cond_wait(&queue->device->timeline_cond, &queue->pending_mutex);
4880 }
4881 pthread_mutex_unlock(&queue->pending_mutex);
4882
4883 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
4884 radv_queue_family_to_ring(queue->queue_family_index),
4885 queue->queue_idx);
4886 return VK_SUCCESS;
4887 }
4888
4889 VkResult radv_DeviceWaitIdle(
4890 VkDevice _device)
4891 {
4892 RADV_FROM_HANDLE(radv_device, device, _device);
4893
4894 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
4895 for (unsigned q = 0; q < device->queue_count[i]; q++) {
4896 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
4897 }
4898 }
4899 return VK_SUCCESS;
4900 }
4901
4902 VkResult radv_EnumerateInstanceExtensionProperties(
4903 const char* pLayerName,
4904 uint32_t* pPropertyCount,
4905 VkExtensionProperties* pProperties)
4906 {
4907 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
4908
4909 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
4910 if (radv_supported_instance_extensions.extensions[i]) {
4911 vk_outarray_append(&out, prop) {
4912 *prop = radv_instance_extensions[i];
4913 }
4914 }
4915 }
4916
4917 return vk_outarray_status(&out);
4918 }
4919
4920 VkResult radv_EnumerateDeviceExtensionProperties(
4921 VkPhysicalDevice physicalDevice,
4922 const char* pLayerName,
4923 uint32_t* pPropertyCount,
4924 VkExtensionProperties* pProperties)
4925 {
4926 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
4927 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
4928
4929 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
4930 if (device->supported_extensions.extensions[i]) {
4931 vk_outarray_append(&out, prop) {
4932 *prop = radv_device_extensions[i];
4933 }
4934 }
4935 }
4936
4937 return vk_outarray_status(&out);
4938 }
4939
4940 PFN_vkVoidFunction radv_GetInstanceProcAddr(
4941 VkInstance _instance,
4942 const char* pName)
4943 {
4944 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4945
4946 /* The Vulkan 1.0 spec for vkGetInstanceProcAddr has a table of exactly
4947 * when we have to return valid function pointers, NULL, or it's left
4948 * undefined. See the table for exact details.
4949 */
4950 if (pName == NULL)
4951 return NULL;
4952
4953 #define LOOKUP_RADV_ENTRYPOINT(entrypoint) \
4954 if (strcmp(pName, "vk" #entrypoint) == 0) \
4955 return (PFN_vkVoidFunction)radv_##entrypoint
4956
4957 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceExtensionProperties);
4958 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceLayerProperties);
4959 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceVersion);
4960 LOOKUP_RADV_ENTRYPOINT(CreateInstance);
4961
4962 /* GetInstanceProcAddr() can also be called with a NULL instance.
4963 * See https://gitlab.khronos.org/vulkan/vulkan/issues/2057
4964 */
4965 LOOKUP_RADV_ENTRYPOINT(GetInstanceProcAddr);
4966
4967 #undef LOOKUP_RADV_ENTRYPOINT
4968
4969 if (instance == NULL)
4970 return NULL;
4971
4972 int idx = radv_get_instance_entrypoint_index(pName);
4973 if (idx >= 0)
4974 return instance->dispatch.entrypoints[idx];
4975
4976 idx = radv_get_physical_device_entrypoint_index(pName);
4977 if (idx >= 0)
4978 return instance->physical_device_dispatch.entrypoints[idx];
4979
4980 idx = radv_get_device_entrypoint_index(pName);
4981 if (idx >= 0)
4982 return instance->device_dispatch.entrypoints[idx];
4983
4984 return NULL;
4985 }
4986
4987 /* The loader wants us to expose a second GetInstanceProcAddr function
4988 * to work around certain LD_PRELOAD issues seen in apps.
4989 */
4990 PUBLIC
4991 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
4992 VkInstance instance,
4993 const char* pName);
4994
4995 PUBLIC
4996 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
4997 VkInstance instance,
4998 const char* pName)
4999 {
5000 return radv_GetInstanceProcAddr(instance, pName);
5001 }
5002
5003 PUBLIC
5004 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
5005 VkInstance _instance,
5006 const char* pName);
5007
5008 PUBLIC
5009 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
5010 VkInstance _instance,
5011 const char* pName)
5012 {
5013 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5014
5015 if (!pName || !instance)
5016 return NULL;
5017
5018 int idx = radv_get_physical_device_entrypoint_index(pName);
5019 if (idx < 0)
5020 return NULL;
5021
5022 return instance->physical_device_dispatch.entrypoints[idx];
5023 }
5024
5025 PFN_vkVoidFunction radv_GetDeviceProcAddr(
5026 VkDevice _device,
5027 const char* pName)
5028 {
5029 RADV_FROM_HANDLE(radv_device, device, _device);
5030
5031 if (!device || !pName)
5032 return NULL;
5033
5034 int idx = radv_get_device_entrypoint_index(pName);
5035 if (idx < 0)
5036 return NULL;
5037
5038 return device->dispatch.entrypoints[idx];
5039 }
5040
5041 bool radv_get_memory_fd(struct radv_device *device,
5042 struct radv_device_memory *memory,
5043 int *pFD)
5044 {
5045 struct radeon_bo_metadata metadata;
5046
5047 if (memory->image) {
5048 if (memory->image->tiling != VK_IMAGE_TILING_LINEAR)
5049 radv_init_metadata(device, memory->image, &metadata);
5050 device->ws->buffer_set_metadata(memory->bo, &metadata);
5051 }
5052
5053 return device->ws->buffer_get_fd(device->ws, memory->bo,
5054 pFD);
5055 }
5056
5057
5058 static void radv_free_memory(struct radv_device *device,
5059 const VkAllocationCallbacks* pAllocator,
5060 struct radv_device_memory *mem)
5061 {
5062 if (mem == NULL)
5063 return;
5064
5065 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
5066 if (mem->android_hardware_buffer)
5067 AHardwareBuffer_release(mem->android_hardware_buffer);
5068 #endif
5069
5070 if (mem->bo) {
5071 if (device->overallocation_disallowed) {
5072 mtx_lock(&device->overallocation_mutex);
5073 device->allocated_memory_size[mem->heap_index] -= mem->alloc_size;
5074 mtx_unlock(&device->overallocation_mutex);
5075 }
5076
5077 radv_bo_list_remove(device, mem->bo);
5078 device->ws->buffer_destroy(mem->bo);
5079 mem->bo = NULL;
5080 }
5081
5082 vk_free2(&device->alloc, pAllocator, mem);
5083 }
5084
5085 static VkResult radv_alloc_memory(struct radv_device *device,
5086 const VkMemoryAllocateInfo* pAllocateInfo,
5087 const VkAllocationCallbacks* pAllocator,
5088 VkDeviceMemory* pMem)
5089 {
5090 struct radv_device_memory *mem;
5091 VkResult result;
5092 enum radeon_bo_domain domain;
5093 uint32_t flags = 0;
5094
5095 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
5096
5097 const VkImportMemoryFdInfoKHR *import_info =
5098 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
5099 const VkMemoryDedicatedAllocateInfo *dedicate_info =
5100 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
5101 const VkExportMemoryAllocateInfo *export_info =
5102 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
5103 const struct VkImportAndroidHardwareBufferInfoANDROID *ahb_import_info =
5104 vk_find_struct_const(pAllocateInfo->pNext,
5105 IMPORT_ANDROID_HARDWARE_BUFFER_INFO_ANDROID);
5106 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
5107 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
5108
5109 const struct wsi_memory_allocate_info *wsi_info =
5110 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
5111
5112 if (pAllocateInfo->allocationSize == 0 && !ahb_import_info &&
5113 !(export_info && (export_info->handleTypes & VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID))) {
5114 /* Apparently, this is allowed */
5115 *pMem = VK_NULL_HANDLE;
5116 return VK_SUCCESS;
5117 }
5118
5119 mem = vk_zalloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
5120 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5121 if (mem == NULL)
5122 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5123
5124 if (wsi_info && wsi_info->implicit_sync)
5125 flags |= RADEON_FLAG_IMPLICIT_SYNC;
5126
5127 if (dedicate_info) {
5128 mem->image = radv_image_from_handle(dedicate_info->image);
5129 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
5130 } else {
5131 mem->image = NULL;
5132 mem->buffer = NULL;
5133 }
5134
5135 float priority_float = 0.5;
5136 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
5137 vk_find_struct_const(pAllocateInfo->pNext,
5138 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
5139 if (priority_ext)
5140 priority_float = priority_ext->priority;
5141
5142 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
5143 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
5144
5145 mem->user_ptr = NULL;
5146 mem->bo = NULL;
5147
5148 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
5149 mem->android_hardware_buffer = NULL;
5150 #endif
5151
5152 if (ahb_import_info) {
5153 result = radv_import_ahb_memory(device, mem, priority, ahb_import_info);
5154 if (result != VK_SUCCESS)
5155 goto fail;
5156 } else if(export_info && (export_info->handleTypes & VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID)) {
5157 result = radv_create_ahb_memory(device, mem, priority, pAllocateInfo);
5158 if (result != VK_SUCCESS)
5159 goto fail;
5160 } else if (import_info) {
5161 assert(import_info->handleType ==
5162 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
5163 import_info->handleType ==
5164 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
5165 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
5166 priority, NULL);
5167 if (!mem->bo) {
5168 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
5169 goto fail;
5170 } else {
5171 close(import_info->fd);
5172 }
5173 } else if (host_ptr_info) {
5174 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
5175 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
5176 pAllocateInfo->allocationSize,
5177 priority);
5178 if (!mem->bo) {
5179 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
5180 goto fail;
5181 } else {
5182 mem->user_ptr = host_ptr_info->pHostPointer;
5183 }
5184 } else {
5185 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
5186 uint32_t heap_index;
5187
5188 heap_index = device->physical_device->memory_properties.memoryTypes[pAllocateInfo->memoryTypeIndex].heapIndex;
5189 domain = device->physical_device->memory_domains[pAllocateInfo->memoryTypeIndex];
5190 flags |= device->physical_device->memory_flags[pAllocateInfo->memoryTypeIndex];
5191
5192 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
5193 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
5194 if (device->use_global_bo_list) {
5195 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
5196 }
5197 }
5198
5199 if (device->overallocation_disallowed) {
5200 uint64_t total_size =
5201 device->physical_device->memory_properties.memoryHeaps[heap_index].size;
5202
5203 mtx_lock(&device->overallocation_mutex);
5204 if (device->allocated_memory_size[heap_index] + alloc_size > total_size) {
5205 mtx_unlock(&device->overallocation_mutex);
5206 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
5207 goto fail;
5208 }
5209 device->allocated_memory_size[heap_index] += alloc_size;
5210 mtx_unlock(&device->overallocation_mutex);
5211 }
5212
5213 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
5214 domain, flags, priority);
5215
5216 if (!mem->bo) {
5217 if (device->overallocation_disallowed) {
5218 mtx_lock(&device->overallocation_mutex);
5219 device->allocated_memory_size[heap_index] -= alloc_size;
5220 mtx_unlock(&device->overallocation_mutex);
5221 }
5222 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
5223 goto fail;
5224 }
5225
5226 mem->heap_index = heap_index;
5227 mem->alloc_size = alloc_size;
5228 }
5229
5230 if (!wsi_info) {
5231 result = radv_bo_list_add(device, mem->bo);
5232 if (result != VK_SUCCESS)
5233 goto fail;
5234 }
5235
5236 *pMem = radv_device_memory_to_handle(mem);
5237
5238 return VK_SUCCESS;
5239
5240 fail:
5241 radv_free_memory(device, pAllocator,mem);
5242
5243 return result;
5244 }
5245
5246 VkResult radv_AllocateMemory(
5247 VkDevice _device,
5248 const VkMemoryAllocateInfo* pAllocateInfo,
5249 const VkAllocationCallbacks* pAllocator,
5250 VkDeviceMemory* pMem)
5251 {
5252 RADV_FROM_HANDLE(radv_device, device, _device);
5253 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
5254 }
5255
5256 void radv_FreeMemory(
5257 VkDevice _device,
5258 VkDeviceMemory _mem,
5259 const VkAllocationCallbacks* pAllocator)
5260 {
5261 RADV_FROM_HANDLE(radv_device, device, _device);
5262 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
5263
5264 radv_free_memory(device, pAllocator, mem);
5265 }
5266
5267 VkResult radv_MapMemory(
5268 VkDevice _device,
5269 VkDeviceMemory _memory,
5270 VkDeviceSize offset,
5271 VkDeviceSize size,
5272 VkMemoryMapFlags flags,
5273 void** ppData)
5274 {
5275 RADV_FROM_HANDLE(radv_device, device, _device);
5276 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
5277
5278 if (mem == NULL) {
5279 *ppData = NULL;
5280 return VK_SUCCESS;
5281 }
5282
5283 if (mem->user_ptr)
5284 *ppData = mem->user_ptr;
5285 else
5286 *ppData = device->ws->buffer_map(mem->bo);
5287
5288 if (*ppData) {
5289 *ppData += offset;
5290 return VK_SUCCESS;
5291 }
5292
5293 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
5294 }
5295
5296 void radv_UnmapMemory(
5297 VkDevice _device,
5298 VkDeviceMemory _memory)
5299 {
5300 RADV_FROM_HANDLE(radv_device, device, _device);
5301 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
5302
5303 if (mem == NULL)
5304 return;
5305
5306 if (mem->user_ptr == NULL)
5307 device->ws->buffer_unmap(mem->bo);
5308 }
5309
5310 VkResult radv_FlushMappedMemoryRanges(
5311 VkDevice _device,
5312 uint32_t memoryRangeCount,
5313 const VkMappedMemoryRange* pMemoryRanges)
5314 {
5315 return VK_SUCCESS;
5316 }
5317
5318 VkResult radv_InvalidateMappedMemoryRanges(
5319 VkDevice _device,
5320 uint32_t memoryRangeCount,
5321 const VkMappedMemoryRange* pMemoryRanges)
5322 {
5323 return VK_SUCCESS;
5324 }
5325
5326 void radv_GetBufferMemoryRequirements(
5327 VkDevice _device,
5328 VkBuffer _buffer,
5329 VkMemoryRequirements* pMemoryRequirements)
5330 {
5331 RADV_FROM_HANDLE(radv_device, device, _device);
5332 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5333
5334 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
5335
5336 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
5337 pMemoryRequirements->alignment = 4096;
5338 else
5339 pMemoryRequirements->alignment = 16;
5340
5341 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
5342 }
5343
5344 void radv_GetBufferMemoryRequirements2(
5345 VkDevice device,
5346 const VkBufferMemoryRequirementsInfo2 *pInfo,
5347 VkMemoryRequirements2 *pMemoryRequirements)
5348 {
5349 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
5350 &pMemoryRequirements->memoryRequirements);
5351 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
5352 switch (ext->sType) {
5353 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
5354 VkMemoryDedicatedRequirements *req =
5355 (VkMemoryDedicatedRequirements *) ext;
5356 req->requiresDedicatedAllocation = false;
5357 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
5358 break;
5359 }
5360 default:
5361 break;
5362 }
5363 }
5364 }
5365
5366 void radv_GetImageMemoryRequirements(
5367 VkDevice _device,
5368 VkImage _image,
5369 VkMemoryRequirements* pMemoryRequirements)
5370 {
5371 RADV_FROM_HANDLE(radv_device, device, _device);
5372 RADV_FROM_HANDLE(radv_image, image, _image);
5373
5374 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
5375
5376 pMemoryRequirements->size = image->size;
5377 pMemoryRequirements->alignment = image->alignment;
5378 }
5379
5380 void radv_GetImageMemoryRequirements2(
5381 VkDevice device,
5382 const VkImageMemoryRequirementsInfo2 *pInfo,
5383 VkMemoryRequirements2 *pMemoryRequirements)
5384 {
5385 radv_GetImageMemoryRequirements(device, pInfo->image,
5386 &pMemoryRequirements->memoryRequirements);
5387
5388 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
5389
5390 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
5391 switch (ext->sType) {
5392 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
5393 VkMemoryDedicatedRequirements *req =
5394 (VkMemoryDedicatedRequirements *) ext;
5395 req->requiresDedicatedAllocation = image->shareable &&
5396 image->tiling != VK_IMAGE_TILING_LINEAR;
5397 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
5398 break;
5399 }
5400 default:
5401 break;
5402 }
5403 }
5404 }
5405
5406 void radv_GetImageSparseMemoryRequirements(
5407 VkDevice device,
5408 VkImage image,
5409 uint32_t* pSparseMemoryRequirementCount,
5410 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
5411 {
5412 stub();
5413 }
5414
5415 void radv_GetImageSparseMemoryRequirements2(
5416 VkDevice device,
5417 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
5418 uint32_t* pSparseMemoryRequirementCount,
5419 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
5420 {
5421 stub();
5422 }
5423
5424 void radv_GetDeviceMemoryCommitment(
5425 VkDevice device,
5426 VkDeviceMemory memory,
5427 VkDeviceSize* pCommittedMemoryInBytes)
5428 {
5429 *pCommittedMemoryInBytes = 0;
5430 }
5431
5432 VkResult radv_BindBufferMemory2(VkDevice device,
5433 uint32_t bindInfoCount,
5434 const VkBindBufferMemoryInfo *pBindInfos)
5435 {
5436 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5437 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
5438 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
5439
5440 if (mem) {
5441 buffer->bo = mem->bo;
5442 buffer->offset = pBindInfos[i].memoryOffset;
5443 } else {
5444 buffer->bo = NULL;
5445 }
5446 }
5447 return VK_SUCCESS;
5448 }
5449
5450 VkResult radv_BindBufferMemory(
5451 VkDevice device,
5452 VkBuffer buffer,
5453 VkDeviceMemory memory,
5454 VkDeviceSize memoryOffset)
5455 {
5456 const VkBindBufferMemoryInfo info = {
5457 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
5458 .buffer = buffer,
5459 .memory = memory,
5460 .memoryOffset = memoryOffset
5461 };
5462
5463 return radv_BindBufferMemory2(device, 1, &info);
5464 }
5465
5466 VkResult radv_BindImageMemory2(VkDevice device,
5467 uint32_t bindInfoCount,
5468 const VkBindImageMemoryInfo *pBindInfos)
5469 {
5470 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5471 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
5472 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
5473
5474 if (mem) {
5475 image->bo = mem->bo;
5476 image->offset = pBindInfos[i].memoryOffset;
5477 } else {
5478 image->bo = NULL;
5479 image->offset = 0;
5480 }
5481 }
5482 return VK_SUCCESS;
5483 }
5484
5485
5486 VkResult radv_BindImageMemory(
5487 VkDevice device,
5488 VkImage image,
5489 VkDeviceMemory memory,
5490 VkDeviceSize memoryOffset)
5491 {
5492 const VkBindImageMemoryInfo info = {
5493 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
5494 .image = image,
5495 .memory = memory,
5496 .memoryOffset = memoryOffset
5497 };
5498
5499 return radv_BindImageMemory2(device, 1, &info);
5500 }
5501
5502 static bool radv_sparse_bind_has_effects(const VkBindSparseInfo *info)
5503 {
5504 return info->bufferBindCount ||
5505 info->imageOpaqueBindCount ||
5506 info->imageBindCount ||
5507 info->waitSemaphoreCount ||
5508 info->signalSemaphoreCount;
5509 }
5510
5511 VkResult radv_QueueBindSparse(
5512 VkQueue _queue,
5513 uint32_t bindInfoCount,
5514 const VkBindSparseInfo* pBindInfo,
5515 VkFence fence)
5516 {
5517 RADV_FROM_HANDLE(radv_queue, queue, _queue);
5518 VkResult result;
5519 uint32_t fence_idx = 0;
5520
5521 if (fence != VK_NULL_HANDLE) {
5522 for (uint32_t i = 0; i < bindInfoCount; ++i)
5523 if (radv_sparse_bind_has_effects(pBindInfo + i))
5524 fence_idx = i;
5525 } else
5526 fence_idx = UINT32_MAX;
5527
5528 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5529 if (i != fence_idx && !radv_sparse_bind_has_effects(pBindInfo + i))
5530 continue;
5531
5532 const VkTimelineSemaphoreSubmitInfo *timeline_info =
5533 vk_find_struct_const(pBindInfo[i].pNext, TIMELINE_SEMAPHORE_SUBMIT_INFO);
5534
5535 VkResult result = radv_queue_submit(queue, &(struct radv_queue_submission) {
5536 .buffer_binds = pBindInfo[i].pBufferBinds,
5537 .buffer_bind_count = pBindInfo[i].bufferBindCount,
5538 .image_opaque_binds = pBindInfo[i].pImageOpaqueBinds,
5539 .image_opaque_bind_count = pBindInfo[i].imageOpaqueBindCount,
5540 .wait_semaphores = pBindInfo[i].pWaitSemaphores,
5541 .wait_semaphore_count = pBindInfo[i].waitSemaphoreCount,
5542 .signal_semaphores = pBindInfo[i].pSignalSemaphores,
5543 .signal_semaphore_count = pBindInfo[i].signalSemaphoreCount,
5544 .fence = i == fence_idx ? fence : VK_NULL_HANDLE,
5545 .wait_values = timeline_info ? timeline_info->pWaitSemaphoreValues : NULL,
5546 .wait_value_count = timeline_info && timeline_info->pWaitSemaphoreValues ? timeline_info->waitSemaphoreValueCount : 0,
5547 .signal_values = timeline_info ? timeline_info->pSignalSemaphoreValues : NULL,
5548 .signal_value_count = timeline_info && timeline_info->pSignalSemaphoreValues ? timeline_info->signalSemaphoreValueCount : 0,
5549 });
5550
5551 if (result != VK_SUCCESS)
5552 return result;
5553 }
5554
5555 if (fence != VK_NULL_HANDLE && !bindInfoCount) {
5556 result = radv_signal_fence(queue, fence);
5557 if (result != VK_SUCCESS)
5558 return result;
5559 }
5560
5561 return VK_SUCCESS;
5562 }
5563
5564 VkResult radv_CreateFence(
5565 VkDevice _device,
5566 const VkFenceCreateInfo* pCreateInfo,
5567 const VkAllocationCallbacks* pAllocator,
5568 VkFence* pFence)
5569 {
5570 RADV_FROM_HANDLE(radv_device, device, _device);
5571 const VkExportFenceCreateInfo *export =
5572 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
5573 VkExternalFenceHandleTypeFlags handleTypes =
5574 export ? export->handleTypes : 0;
5575
5576 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
5577 sizeof(*fence), 8,
5578 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5579
5580 if (!fence)
5581 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5582
5583 fence->fence_wsi = NULL;
5584 fence->temp_syncobj = 0;
5585 if (device->always_use_syncobj || handleTypes) {
5586 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
5587 if (ret) {
5588 vk_free2(&device->alloc, pAllocator, fence);
5589 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5590 }
5591 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
5592 device->ws->signal_syncobj(device->ws, fence->syncobj);
5593 }
5594 fence->fence = NULL;
5595 } else {
5596 fence->fence = device->ws->create_fence();
5597 if (!fence->fence) {
5598 vk_free2(&device->alloc, pAllocator, fence);
5599 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5600 }
5601 fence->syncobj = 0;
5602 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
5603 device->ws->signal_fence(fence->fence);
5604 }
5605
5606 *pFence = radv_fence_to_handle(fence);
5607
5608 return VK_SUCCESS;
5609 }
5610
5611 void radv_DestroyFence(
5612 VkDevice _device,
5613 VkFence _fence,
5614 const VkAllocationCallbacks* pAllocator)
5615 {
5616 RADV_FROM_HANDLE(radv_device, device, _device);
5617 RADV_FROM_HANDLE(radv_fence, fence, _fence);
5618
5619 if (!fence)
5620 return;
5621
5622 if (fence->temp_syncobj)
5623 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
5624 if (fence->syncobj)
5625 device->ws->destroy_syncobj(device->ws, fence->syncobj);
5626 if (fence->fence)
5627 device->ws->destroy_fence(fence->fence);
5628 if (fence->fence_wsi)
5629 fence->fence_wsi->destroy(fence->fence_wsi);
5630 vk_free2(&device->alloc, pAllocator, fence);
5631 }
5632
5633
5634 uint64_t radv_get_current_time(void)
5635 {
5636 struct timespec tv;
5637 clock_gettime(CLOCK_MONOTONIC, &tv);
5638 return tv.tv_nsec + tv.tv_sec*1000000000ull;
5639 }
5640
5641 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
5642 {
5643 uint64_t current_time = radv_get_current_time();
5644
5645 timeout = MIN2(UINT64_MAX - current_time, timeout);
5646
5647 return current_time + timeout;
5648 }
5649
5650
5651 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
5652 uint32_t fenceCount, const VkFence *pFences)
5653 {
5654 for (uint32_t i = 0; i < fenceCount; ++i) {
5655 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5656 if (fence->fence == NULL || fence->syncobj ||
5657 fence->temp_syncobj || fence->fence_wsi ||
5658 (!device->ws->is_fence_waitable(fence->fence)))
5659 return false;
5660 }
5661 return true;
5662 }
5663
5664 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
5665 {
5666 for (uint32_t i = 0; i < fenceCount; ++i) {
5667 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5668 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
5669 return false;
5670 }
5671 return true;
5672 }
5673
5674 VkResult radv_WaitForFences(
5675 VkDevice _device,
5676 uint32_t fenceCount,
5677 const VkFence* pFences,
5678 VkBool32 waitAll,
5679 uint64_t timeout)
5680 {
5681 RADV_FROM_HANDLE(radv_device, device, _device);
5682 timeout = radv_get_absolute_timeout(timeout);
5683
5684 if (device->always_use_syncobj &&
5685 radv_all_fences_syncobj(fenceCount, pFences))
5686 {
5687 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
5688 if (!handles)
5689 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5690
5691 for (uint32_t i = 0; i < fenceCount; ++i) {
5692 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5693 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
5694 }
5695
5696 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
5697
5698 free(handles);
5699 return success ? VK_SUCCESS : VK_TIMEOUT;
5700 }
5701
5702 if (!waitAll && fenceCount > 1) {
5703 /* Not doing this by default for waitAll, due to needing to allocate twice. */
5704 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
5705 uint32_t wait_count = 0;
5706 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
5707 if (!fences)
5708 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5709
5710 for (uint32_t i = 0; i < fenceCount; ++i) {
5711 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5712
5713 if (device->ws->fence_wait(device->ws, fence->fence, false, 0)) {
5714 free(fences);
5715 return VK_SUCCESS;
5716 }
5717
5718 fences[wait_count++] = fence->fence;
5719 }
5720
5721 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
5722 waitAll, timeout - radv_get_current_time());
5723
5724 free(fences);
5725 return success ? VK_SUCCESS : VK_TIMEOUT;
5726 }
5727
5728 while(radv_get_current_time() <= timeout) {
5729 for (uint32_t i = 0; i < fenceCount; ++i) {
5730 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
5731 return VK_SUCCESS;
5732 }
5733 }
5734 return VK_TIMEOUT;
5735 }
5736
5737 for (uint32_t i = 0; i < fenceCount; ++i) {
5738 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5739 bool expired = false;
5740
5741 if (fence->temp_syncobj) {
5742 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
5743 return VK_TIMEOUT;
5744 continue;
5745 }
5746
5747 if (fence->syncobj) {
5748 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
5749 return VK_TIMEOUT;
5750 continue;
5751 }
5752
5753 if (fence->fence) {
5754 if (!device->ws->is_fence_waitable(fence->fence)) {
5755 while(!device->ws->is_fence_waitable(fence->fence) &&
5756 radv_get_current_time() <= timeout)
5757 /* Do nothing */;
5758 }
5759
5760 expired = device->ws->fence_wait(device->ws,
5761 fence->fence,
5762 true, timeout);
5763 if (!expired)
5764 return VK_TIMEOUT;
5765 }
5766
5767 if (fence->fence_wsi) {
5768 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
5769 if (result != VK_SUCCESS)
5770 return result;
5771 }
5772 }
5773
5774 return VK_SUCCESS;
5775 }
5776
5777 VkResult radv_ResetFences(VkDevice _device,
5778 uint32_t fenceCount,
5779 const VkFence *pFences)
5780 {
5781 RADV_FROM_HANDLE(radv_device, device, _device);
5782
5783 for (unsigned i = 0; i < fenceCount; ++i) {
5784 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5785 if (fence->fence)
5786 device->ws->reset_fence(fence->fence);
5787
5788 /* Per spec, we first restore the permanent payload, and then reset, so
5789 * having a temp syncobj should not skip resetting the permanent syncobj. */
5790 if (fence->temp_syncobj) {
5791 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
5792 fence->temp_syncobj = 0;
5793 }
5794
5795 if (fence->syncobj) {
5796 device->ws->reset_syncobj(device->ws, fence->syncobj);
5797 }
5798 }
5799
5800 return VK_SUCCESS;
5801 }
5802
5803 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
5804 {
5805 RADV_FROM_HANDLE(radv_device, device, _device);
5806 RADV_FROM_HANDLE(radv_fence, fence, _fence);
5807
5808 if (fence->temp_syncobj) {
5809 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
5810 return success ? VK_SUCCESS : VK_NOT_READY;
5811 }
5812
5813 if (fence->syncobj) {
5814 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
5815 return success ? VK_SUCCESS : VK_NOT_READY;
5816 }
5817
5818 if (fence->fence) {
5819 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
5820 return VK_NOT_READY;
5821 }
5822 if (fence->fence_wsi) {
5823 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
5824
5825 if (result != VK_SUCCESS) {
5826 if (result == VK_TIMEOUT)
5827 return VK_NOT_READY;
5828 return result;
5829 }
5830 }
5831 return VK_SUCCESS;
5832 }
5833
5834
5835 // Queue semaphore functions
5836
5837 static void
5838 radv_create_timeline(struct radv_timeline *timeline, uint64_t value)
5839 {
5840 timeline->highest_signaled = value;
5841 timeline->highest_submitted = value;
5842 list_inithead(&timeline->points);
5843 list_inithead(&timeline->free_points);
5844 list_inithead(&timeline->waiters);
5845 pthread_mutex_init(&timeline->mutex, NULL);
5846 }
5847
5848 static void
5849 radv_destroy_timeline(struct radv_device *device,
5850 struct radv_timeline *timeline)
5851 {
5852 list_for_each_entry_safe(struct radv_timeline_point, point,
5853 &timeline->free_points, list) {
5854 list_del(&point->list);
5855 device->ws->destroy_syncobj(device->ws, point->syncobj);
5856 free(point);
5857 }
5858 list_for_each_entry_safe(struct radv_timeline_point, point,
5859 &timeline->points, list) {
5860 list_del(&point->list);
5861 device->ws->destroy_syncobj(device->ws, point->syncobj);
5862 free(point);
5863 }
5864 pthread_mutex_destroy(&timeline->mutex);
5865 }
5866
5867 static void
5868 radv_timeline_gc_locked(struct radv_device *device,
5869 struct radv_timeline *timeline)
5870 {
5871 list_for_each_entry_safe(struct radv_timeline_point, point,
5872 &timeline->points, list) {
5873 if (point->wait_count || point->value > timeline->highest_submitted)
5874 return;
5875
5876 if (device->ws->wait_syncobj(device->ws, &point->syncobj, 1, true, 0)) {
5877 timeline->highest_signaled = point->value;
5878 list_del(&point->list);
5879 list_add(&point->list, &timeline->free_points);
5880 }
5881 }
5882 }
5883
5884 static struct radv_timeline_point *
5885 radv_timeline_find_point_at_least_locked(struct radv_device *device,
5886 struct radv_timeline *timeline,
5887 uint64_t p)
5888 {
5889 radv_timeline_gc_locked(device, timeline);
5890
5891 if (p <= timeline->highest_signaled)
5892 return NULL;
5893
5894 list_for_each_entry(struct radv_timeline_point, point,
5895 &timeline->points, list) {
5896 if (point->value >= p) {
5897 ++point->wait_count;
5898 return point;
5899 }
5900 }
5901 return NULL;
5902 }
5903
5904 static struct radv_timeline_point *
5905 radv_timeline_add_point_locked(struct radv_device *device,
5906 struct radv_timeline *timeline,
5907 uint64_t p)
5908 {
5909 radv_timeline_gc_locked(device, timeline);
5910
5911 struct radv_timeline_point *ret = NULL;
5912 struct radv_timeline_point *prev = NULL;
5913
5914 if (p <= timeline->highest_signaled)
5915 return NULL;
5916
5917 list_for_each_entry(struct radv_timeline_point, point,
5918 &timeline->points, list) {
5919 if (point->value == p) {
5920 return NULL;
5921 }
5922
5923 if (point->value < p)
5924 prev = point;
5925 }
5926
5927 if (list_is_empty(&timeline->free_points)) {
5928 ret = malloc(sizeof(struct radv_timeline_point));
5929 device->ws->create_syncobj(device->ws, &ret->syncobj);
5930 } else {
5931 ret = list_first_entry(&timeline->free_points, struct radv_timeline_point, list);
5932 list_del(&ret->list);
5933
5934 device->ws->reset_syncobj(device->ws, ret->syncobj);
5935 }
5936
5937 ret->value = p;
5938 ret->wait_count = 1;
5939
5940 if (prev) {
5941 list_add(&ret->list, &prev->list);
5942 } else {
5943 list_addtail(&ret->list, &timeline->points);
5944 }
5945 return ret;
5946 }
5947
5948
5949 static VkResult
5950 radv_timeline_wait_locked(struct radv_device *device,
5951 struct radv_timeline *timeline,
5952 uint64_t value,
5953 uint64_t abs_timeout)
5954 {
5955 while(timeline->highest_submitted < value) {
5956 struct timespec abstime;
5957 timespec_from_nsec(&abstime, abs_timeout);
5958
5959 pthread_cond_timedwait(&device->timeline_cond, &timeline->mutex, &abstime);
5960
5961 if (radv_get_current_time() >= abs_timeout && timeline->highest_submitted < value)
5962 return VK_TIMEOUT;
5963 }
5964
5965 struct radv_timeline_point *point = radv_timeline_find_point_at_least_locked(device, timeline, value);
5966 if (!point)
5967 return VK_SUCCESS;
5968
5969 pthread_mutex_unlock(&timeline->mutex);
5970
5971 bool success = device->ws->wait_syncobj(device->ws, &point->syncobj, 1, true, abs_timeout);
5972
5973 pthread_mutex_lock(&timeline->mutex);
5974 point->wait_count--;
5975 return success ? VK_SUCCESS : VK_TIMEOUT;
5976 }
5977
5978 static void
5979 radv_timeline_trigger_waiters_locked(struct radv_timeline *timeline,
5980 struct list_head *processing_list)
5981 {
5982 list_for_each_entry_safe(struct radv_timeline_waiter, waiter,
5983 &timeline->waiters, list) {
5984 if (waiter->value > timeline->highest_submitted)
5985 continue;
5986
5987 if (p_atomic_dec_zero(&waiter->submission->submission_wait_count)) {
5988 list_addtail(&waiter->submission->processing_list, processing_list);
5989 }
5990 list_del(&waiter->list);
5991 }
5992 }
5993
5994 static
5995 void radv_destroy_semaphore_part(struct radv_device *device,
5996 struct radv_semaphore_part *part)
5997 {
5998 switch(part->kind) {
5999 case RADV_SEMAPHORE_NONE:
6000 break;
6001 case RADV_SEMAPHORE_WINSYS:
6002 device->ws->destroy_sem(part->ws_sem);
6003 break;
6004 case RADV_SEMAPHORE_TIMELINE:
6005 radv_destroy_timeline(device, &part->timeline);
6006 break;
6007 case RADV_SEMAPHORE_SYNCOBJ:
6008 device->ws->destroy_syncobj(device->ws, part->syncobj);
6009 break;
6010 }
6011 part->kind = RADV_SEMAPHORE_NONE;
6012 }
6013
6014 static VkSemaphoreTypeKHR
6015 radv_get_semaphore_type(const void *pNext, uint64_t *initial_value)
6016 {
6017 const VkSemaphoreTypeCreateInfo *type_info =
6018 vk_find_struct_const(pNext, SEMAPHORE_TYPE_CREATE_INFO);
6019
6020 if (!type_info)
6021 return VK_SEMAPHORE_TYPE_BINARY;
6022
6023 if (initial_value)
6024 *initial_value = type_info->initialValue;
6025 return type_info->semaphoreType;
6026 }
6027
6028 VkResult radv_CreateSemaphore(
6029 VkDevice _device,
6030 const VkSemaphoreCreateInfo* pCreateInfo,
6031 const VkAllocationCallbacks* pAllocator,
6032 VkSemaphore* pSemaphore)
6033 {
6034 RADV_FROM_HANDLE(radv_device, device, _device);
6035 const VkExportSemaphoreCreateInfo *export =
6036 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
6037 VkExternalSemaphoreHandleTypeFlags handleTypes =
6038 export ? export->handleTypes : 0;
6039 uint64_t initial_value = 0;
6040 VkSemaphoreTypeKHR type = radv_get_semaphore_type(pCreateInfo->pNext, &initial_value);
6041
6042 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
6043 sizeof(*sem), 8,
6044 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6045 if (!sem)
6046 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6047
6048 sem->temporary.kind = RADV_SEMAPHORE_NONE;
6049 sem->permanent.kind = RADV_SEMAPHORE_NONE;
6050
6051 if (type == VK_SEMAPHORE_TYPE_TIMELINE) {
6052 radv_create_timeline(&sem->permanent.timeline, initial_value);
6053 sem->permanent.kind = RADV_SEMAPHORE_TIMELINE;
6054 } else if (device->always_use_syncobj || handleTypes) {
6055 assert (device->physical_device->rad_info.has_syncobj);
6056 int ret = device->ws->create_syncobj(device->ws, &sem->permanent.syncobj);
6057 if (ret) {
6058 vk_free2(&device->alloc, pAllocator, sem);
6059 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6060 }
6061 sem->permanent.kind = RADV_SEMAPHORE_SYNCOBJ;
6062 } else {
6063 sem->permanent.ws_sem = device->ws->create_sem(device->ws);
6064 if (!sem->permanent.ws_sem) {
6065 vk_free2(&device->alloc, pAllocator, sem);
6066 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6067 }
6068 sem->permanent.kind = RADV_SEMAPHORE_WINSYS;
6069 }
6070
6071 *pSemaphore = radv_semaphore_to_handle(sem);
6072 return VK_SUCCESS;
6073 }
6074
6075 void radv_DestroySemaphore(
6076 VkDevice _device,
6077 VkSemaphore _semaphore,
6078 const VkAllocationCallbacks* pAllocator)
6079 {
6080 RADV_FROM_HANDLE(radv_device, device, _device);
6081 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
6082 if (!_semaphore)
6083 return;
6084
6085 radv_destroy_semaphore_part(device, &sem->temporary);
6086 radv_destroy_semaphore_part(device, &sem->permanent);
6087 vk_free2(&device->alloc, pAllocator, sem);
6088 }
6089
6090 VkResult
6091 radv_GetSemaphoreCounterValue(VkDevice _device,
6092 VkSemaphore _semaphore,
6093 uint64_t* pValue)
6094 {
6095 RADV_FROM_HANDLE(radv_device, device, _device);
6096 RADV_FROM_HANDLE(radv_semaphore, semaphore, _semaphore);
6097
6098 struct radv_semaphore_part *part =
6099 semaphore->temporary.kind != RADV_SEMAPHORE_NONE ? &semaphore->temporary : &semaphore->permanent;
6100
6101 switch (part->kind) {
6102 case RADV_SEMAPHORE_TIMELINE: {
6103 pthread_mutex_lock(&part->timeline.mutex);
6104 radv_timeline_gc_locked(device, &part->timeline);
6105 *pValue = part->timeline.highest_signaled;
6106 pthread_mutex_unlock(&part->timeline.mutex);
6107 return VK_SUCCESS;
6108 }
6109 case RADV_SEMAPHORE_NONE:
6110 case RADV_SEMAPHORE_SYNCOBJ:
6111 case RADV_SEMAPHORE_WINSYS:
6112 unreachable("Invalid semaphore type");
6113 }
6114 unreachable("Unhandled semaphore type");
6115 }
6116
6117
6118 static VkResult
6119 radv_wait_timelines(struct radv_device *device,
6120 const VkSemaphoreWaitInfo* pWaitInfo,
6121 uint64_t abs_timeout)
6122 {
6123 if ((pWaitInfo->flags & VK_SEMAPHORE_WAIT_ANY_BIT_KHR) && pWaitInfo->semaphoreCount > 1) {
6124 for (;;) {
6125 for(uint32_t i = 0; i < pWaitInfo->semaphoreCount; ++i) {
6126 RADV_FROM_HANDLE(radv_semaphore, semaphore, pWaitInfo->pSemaphores[i]);
6127 pthread_mutex_lock(&semaphore->permanent.timeline.mutex);
6128 VkResult result = radv_timeline_wait_locked(device, &semaphore->permanent.timeline, pWaitInfo->pValues[i], 0);
6129 pthread_mutex_unlock(&semaphore->permanent.timeline.mutex);
6130
6131 if (result == VK_SUCCESS)
6132 return VK_SUCCESS;
6133 }
6134 if (radv_get_current_time() > abs_timeout)
6135 return VK_TIMEOUT;
6136 }
6137 }
6138
6139 for(uint32_t i = 0; i < pWaitInfo->semaphoreCount; ++i) {
6140 RADV_FROM_HANDLE(radv_semaphore, semaphore, pWaitInfo->pSemaphores[i]);
6141 pthread_mutex_lock(&semaphore->permanent.timeline.mutex);
6142 VkResult result = radv_timeline_wait_locked(device, &semaphore->permanent.timeline, pWaitInfo->pValues[i], abs_timeout);
6143 pthread_mutex_unlock(&semaphore->permanent.timeline.mutex);
6144
6145 if (result != VK_SUCCESS)
6146 return result;
6147 }
6148 return VK_SUCCESS;
6149 }
6150 VkResult
6151 radv_WaitSemaphores(VkDevice _device,
6152 const VkSemaphoreWaitInfo* pWaitInfo,
6153 uint64_t timeout)
6154 {
6155 RADV_FROM_HANDLE(radv_device, device, _device);
6156 uint64_t abs_timeout = radv_get_absolute_timeout(timeout);
6157 return radv_wait_timelines(device, pWaitInfo, abs_timeout);
6158 }
6159
6160 VkResult
6161 radv_SignalSemaphore(VkDevice _device,
6162 const VkSemaphoreSignalInfo* pSignalInfo)
6163 {
6164 RADV_FROM_HANDLE(radv_device, device, _device);
6165 RADV_FROM_HANDLE(radv_semaphore, semaphore, pSignalInfo->semaphore);
6166
6167 struct radv_semaphore_part *part =
6168 semaphore->temporary.kind != RADV_SEMAPHORE_NONE ? &semaphore->temporary : &semaphore->permanent;
6169
6170 switch(part->kind) {
6171 case RADV_SEMAPHORE_TIMELINE: {
6172 pthread_mutex_lock(&part->timeline.mutex);
6173 radv_timeline_gc_locked(device, &part->timeline);
6174 part->timeline.highest_submitted = MAX2(part->timeline.highest_submitted, pSignalInfo->value);
6175 part->timeline.highest_signaled = MAX2(part->timeline.highest_signaled, pSignalInfo->value);
6176
6177 struct list_head processing_list;
6178 list_inithead(&processing_list);
6179 radv_timeline_trigger_waiters_locked(&part->timeline, &processing_list);
6180 pthread_mutex_unlock(&part->timeline.mutex);
6181
6182 return radv_process_submissions(&processing_list);
6183 }
6184 case RADV_SEMAPHORE_NONE:
6185 case RADV_SEMAPHORE_SYNCOBJ:
6186 case RADV_SEMAPHORE_WINSYS:
6187 unreachable("Invalid semaphore type");
6188 }
6189 return VK_SUCCESS;
6190 }
6191
6192
6193
6194 VkResult radv_CreateEvent(
6195 VkDevice _device,
6196 const VkEventCreateInfo* pCreateInfo,
6197 const VkAllocationCallbacks* pAllocator,
6198 VkEvent* pEvent)
6199 {
6200 RADV_FROM_HANDLE(radv_device, device, _device);
6201 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
6202 sizeof(*event), 8,
6203 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6204
6205 if (!event)
6206 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6207
6208 event->bo = device->ws->buffer_create(device->ws, 8, 8,
6209 RADEON_DOMAIN_GTT,
6210 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
6211 RADV_BO_PRIORITY_FENCE);
6212 if (!event->bo) {
6213 vk_free2(&device->alloc, pAllocator, event);
6214 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
6215 }
6216
6217 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
6218
6219 *pEvent = radv_event_to_handle(event);
6220
6221 return VK_SUCCESS;
6222 }
6223
6224 void radv_DestroyEvent(
6225 VkDevice _device,
6226 VkEvent _event,
6227 const VkAllocationCallbacks* pAllocator)
6228 {
6229 RADV_FROM_HANDLE(radv_device, device, _device);
6230 RADV_FROM_HANDLE(radv_event, event, _event);
6231
6232 if (!event)
6233 return;
6234 device->ws->buffer_destroy(event->bo);
6235 vk_free2(&device->alloc, pAllocator, event);
6236 }
6237
6238 VkResult radv_GetEventStatus(
6239 VkDevice _device,
6240 VkEvent _event)
6241 {
6242 RADV_FROM_HANDLE(radv_event, event, _event);
6243
6244 if (*event->map == 1)
6245 return VK_EVENT_SET;
6246 return VK_EVENT_RESET;
6247 }
6248
6249 VkResult radv_SetEvent(
6250 VkDevice _device,
6251 VkEvent _event)
6252 {
6253 RADV_FROM_HANDLE(radv_event, event, _event);
6254 *event->map = 1;
6255
6256 return VK_SUCCESS;
6257 }
6258
6259 VkResult radv_ResetEvent(
6260 VkDevice _device,
6261 VkEvent _event)
6262 {
6263 RADV_FROM_HANDLE(radv_event, event, _event);
6264 *event->map = 0;
6265
6266 return VK_SUCCESS;
6267 }
6268
6269 VkResult radv_CreateBuffer(
6270 VkDevice _device,
6271 const VkBufferCreateInfo* pCreateInfo,
6272 const VkAllocationCallbacks* pAllocator,
6273 VkBuffer* pBuffer)
6274 {
6275 RADV_FROM_HANDLE(radv_device, device, _device);
6276 struct radv_buffer *buffer;
6277
6278 if (pCreateInfo->size > RADV_MAX_MEMORY_ALLOCATION_SIZE)
6279 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
6280
6281 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
6282
6283 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
6284 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6285 if (buffer == NULL)
6286 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6287
6288 buffer->size = pCreateInfo->size;
6289 buffer->usage = pCreateInfo->usage;
6290 buffer->bo = NULL;
6291 buffer->offset = 0;
6292 buffer->flags = pCreateInfo->flags;
6293
6294 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
6295 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
6296
6297 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
6298 buffer->bo = device->ws->buffer_create(device->ws,
6299 align64(buffer->size, 4096),
6300 4096, 0, RADEON_FLAG_VIRTUAL,
6301 RADV_BO_PRIORITY_VIRTUAL);
6302 if (!buffer->bo) {
6303 vk_free2(&device->alloc, pAllocator, buffer);
6304 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
6305 }
6306 }
6307
6308 *pBuffer = radv_buffer_to_handle(buffer);
6309
6310 return VK_SUCCESS;
6311 }
6312
6313 void radv_DestroyBuffer(
6314 VkDevice _device,
6315 VkBuffer _buffer,
6316 const VkAllocationCallbacks* pAllocator)
6317 {
6318 RADV_FROM_HANDLE(radv_device, device, _device);
6319 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
6320
6321 if (!buffer)
6322 return;
6323
6324 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
6325 device->ws->buffer_destroy(buffer->bo);
6326
6327 vk_free2(&device->alloc, pAllocator, buffer);
6328 }
6329
6330 VkDeviceAddress radv_GetBufferDeviceAddress(
6331 VkDevice device,
6332 const VkBufferDeviceAddressInfo* pInfo)
6333 {
6334 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
6335 return radv_buffer_get_va(buffer->bo) + buffer->offset;
6336 }
6337
6338
6339 uint64_t radv_GetBufferOpaqueCaptureAddress(VkDevice device,
6340 const VkBufferDeviceAddressInfo* pInfo)
6341 {
6342 return 0;
6343 }
6344
6345 uint64_t radv_GetDeviceMemoryOpaqueCaptureAddress(VkDevice device,
6346 const VkDeviceMemoryOpaqueCaptureAddressInfo* pInfo)
6347 {
6348 return 0;
6349 }
6350
6351 static inline unsigned
6352 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
6353 {
6354 if (stencil)
6355 return plane->surface.u.legacy.stencil_tiling_index[level];
6356 else
6357 return plane->surface.u.legacy.tiling_index[level];
6358 }
6359
6360 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
6361 {
6362 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
6363 }
6364
6365 static uint32_t
6366 radv_init_dcc_control_reg(struct radv_device *device,
6367 struct radv_image_view *iview)
6368 {
6369 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
6370 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
6371 unsigned max_compressed_block_size;
6372 unsigned independent_128b_blocks;
6373 unsigned independent_64b_blocks;
6374
6375 if (!radv_dcc_enabled(iview->image, iview->base_mip))
6376 return 0;
6377
6378 if (!device->physical_device->rad_info.has_dedicated_vram) {
6379 /* amdvlk: [min-compressed-block-size] should be set to 32 for
6380 * dGPU and 64 for APU because all of our APUs to date use
6381 * DIMMs which have a request granularity size of 64B while all
6382 * other chips have a 32B request size.
6383 */
6384 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
6385 }
6386
6387 if (device->physical_device->rad_info.chip_class >= GFX10) {
6388 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
6389 independent_64b_blocks = 0;
6390 independent_128b_blocks = 1;
6391 } else {
6392 independent_128b_blocks = 0;
6393
6394 if (iview->image->info.samples > 1) {
6395 if (iview->image->planes[0].surface.bpe == 1)
6396 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
6397 else if (iview->image->planes[0].surface.bpe == 2)
6398 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
6399 }
6400
6401 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
6402 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
6403 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
6404 /* If this DCC image is potentially going to be used in texture
6405 * fetches, we need some special settings.
6406 */
6407 independent_64b_blocks = 1;
6408 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
6409 } else {
6410 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
6411 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
6412 * big as possible for better compression state.
6413 */
6414 independent_64b_blocks = 0;
6415 max_compressed_block_size = max_uncompressed_block_size;
6416 }
6417 }
6418
6419 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
6420 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
6421 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
6422 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks) |
6423 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks);
6424 }
6425
6426 void
6427 radv_initialise_color_surface(struct radv_device *device,
6428 struct radv_color_buffer_info *cb,
6429 struct radv_image_view *iview)
6430 {
6431 const struct vk_format_description *desc;
6432 unsigned ntype, format, swap, endian;
6433 unsigned blend_clamp = 0, blend_bypass = 0;
6434 uint64_t va;
6435 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
6436 const struct radeon_surf *surf = &plane->surface;
6437
6438 desc = vk_format_description(iview->vk_format);
6439
6440 memset(cb, 0, sizeof(*cb));
6441
6442 /* Intensity is implemented as Red, so treat it that way. */
6443 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
6444
6445 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
6446
6447 cb->cb_color_base = va >> 8;
6448
6449 if (device->physical_device->rad_info.chip_class >= GFX9) {
6450 struct gfx9_surf_meta_flags meta;
6451 if (iview->image->dcc_offset)
6452 meta = surf->u.gfx9.dcc;
6453 else
6454 meta = surf->u.gfx9.cmask;
6455
6456 if (device->physical_device->rad_info.chip_class >= GFX10) {
6457 cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6458 S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
6459 S_028EE0_CMASK_PIPE_ALIGNED(surf->u.gfx9.cmask.pipe_aligned) |
6460 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.dcc.pipe_aligned);
6461 } else {
6462 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6463 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
6464 S_028C74_RB_ALIGNED(meta.rb_aligned) |
6465 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
6466 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
6467 }
6468
6469 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
6470 cb->cb_color_base |= surf->tile_swizzle;
6471 } else {
6472 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
6473 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
6474
6475 cb->cb_color_base += level_info->offset >> 8;
6476 if (level_info->mode == RADEON_SURF_MODE_2D)
6477 cb->cb_color_base |= surf->tile_swizzle;
6478
6479 pitch_tile_max = level_info->nblk_x / 8 - 1;
6480 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
6481 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
6482
6483 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
6484 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
6485 cb->cb_color_cmask_slice = surf->u.legacy.cmask_slice_tile_max;
6486
6487 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
6488
6489 if (radv_image_has_fmask(iview->image)) {
6490 if (device->physical_device->rad_info.chip_class >= GFX7)
6491 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(surf->u.legacy.fmask.pitch_in_pixels / 8 - 1);
6492 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(surf->u.legacy.fmask.tiling_index);
6493 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(surf->u.legacy.fmask.slice_tile_max);
6494 } else {
6495 /* This must be set for fast clear to work without FMASK. */
6496 if (device->physical_device->rad_info.chip_class >= GFX7)
6497 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
6498 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
6499 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
6500 }
6501 }
6502
6503 /* CMASK variables */
6504 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6505 va += iview->image->cmask_offset;
6506 cb->cb_color_cmask = va >> 8;
6507
6508 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6509 va += iview->image->dcc_offset;
6510
6511 if (radv_dcc_enabled(iview->image, iview->base_mip) &&
6512 device->physical_device->rad_info.chip_class <= GFX8)
6513 va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
6514
6515 unsigned dcc_tile_swizzle = surf->tile_swizzle;
6516 dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8;
6517
6518 cb->cb_dcc_base = va >> 8;
6519 cb->cb_dcc_base |= dcc_tile_swizzle;
6520
6521 /* GFX10 field has the same base shift as the GFX6 field. */
6522 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
6523 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
6524 S_028C6C_SLICE_MAX_GFX10(max_slice);
6525
6526 if (iview->image->info.samples > 1) {
6527 unsigned log_samples = util_logbase2(iview->image->info.samples);
6528
6529 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
6530 S_028C74_NUM_FRAGMENTS(log_samples);
6531 }
6532
6533 if (radv_image_has_fmask(iview->image)) {
6534 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask_offset;
6535 cb->cb_color_fmask = va >> 8;
6536 cb->cb_color_fmask |= surf->fmask_tile_swizzle;
6537 } else {
6538 cb->cb_color_fmask = cb->cb_color_base;
6539 }
6540
6541 ntype = radv_translate_color_numformat(iview->vk_format,
6542 desc,
6543 vk_format_get_first_non_void_channel(iview->vk_format));
6544 format = radv_translate_colorformat(iview->vk_format);
6545 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
6546 radv_finishme("Illegal color\n");
6547 swap = radv_translate_colorswap(iview->vk_format, false);
6548 endian = radv_colorformat_endian_swap(format);
6549
6550 /* blend clamp should be set for all NORM/SRGB types */
6551 if (ntype == V_028C70_NUMBER_UNORM ||
6552 ntype == V_028C70_NUMBER_SNORM ||
6553 ntype == V_028C70_NUMBER_SRGB)
6554 blend_clamp = 1;
6555
6556 /* set blend bypass according to docs if SINT/UINT or
6557 8/24 COLOR variants */
6558 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
6559 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
6560 format == V_028C70_COLOR_X24_8_32_FLOAT) {
6561 blend_clamp = 0;
6562 blend_bypass = 1;
6563 }
6564 #if 0
6565 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
6566 (format == V_028C70_COLOR_8 ||
6567 format == V_028C70_COLOR_8_8 ||
6568 format == V_028C70_COLOR_8_8_8_8))
6569 ->color_is_int8 = true;
6570 #endif
6571 cb->cb_color_info = S_028C70_FORMAT(format) |
6572 S_028C70_COMP_SWAP(swap) |
6573 S_028C70_BLEND_CLAMP(blend_clamp) |
6574 S_028C70_BLEND_BYPASS(blend_bypass) |
6575 S_028C70_SIMPLE_FLOAT(1) |
6576 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
6577 ntype != V_028C70_NUMBER_SNORM &&
6578 ntype != V_028C70_NUMBER_SRGB &&
6579 format != V_028C70_COLOR_8_24 &&
6580 format != V_028C70_COLOR_24_8) |
6581 S_028C70_NUMBER_TYPE(ntype) |
6582 S_028C70_ENDIAN(endian);
6583 if (radv_image_has_fmask(iview->image)) {
6584 cb->cb_color_info |= S_028C70_COMPRESSION(1);
6585 if (device->physical_device->rad_info.chip_class == GFX6) {
6586 unsigned fmask_bankh = util_logbase2(surf->u.legacy.fmask.bankh);
6587 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
6588 }
6589
6590 if (radv_image_is_tc_compat_cmask(iview->image)) {
6591 /* Allow the texture block to read FMASK directly
6592 * without decompressing it. This bit must be cleared
6593 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
6594 * otherwise the operation doesn't happen.
6595 */
6596 cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
6597
6598 /* Set CMASK into a tiling format that allows the
6599 * texture block to read it.
6600 */
6601 cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
6602 }
6603 }
6604
6605 if (radv_image_has_cmask(iview->image) &&
6606 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
6607 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
6608
6609 if (radv_dcc_enabled(iview->image, iview->base_mip))
6610 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
6611
6612 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
6613
6614 /* This must be set for fast clear to work without FMASK. */
6615 if (!radv_image_has_fmask(iview->image) &&
6616 device->physical_device->rad_info.chip_class == GFX6) {
6617 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
6618 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
6619 }
6620
6621 if (device->physical_device->rad_info.chip_class >= GFX9) {
6622 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
6623
6624 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
6625 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
6626 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
6627 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
6628
6629 if (device->physical_device->rad_info.chip_class >= GFX10) {
6630 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip);
6631
6632 cb->cb_color_attrib3 |= S_028EE0_MIP0_DEPTH(mip0_depth) |
6633 S_028EE0_RESOURCE_TYPE(surf->u.gfx9.resource_type) |
6634 S_028EE0_RESOURCE_LEVEL(1);
6635 } else {
6636 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip);
6637 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
6638 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
6639 }
6640
6641 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
6642 S_028C68_MIP0_HEIGHT(height - 1) |
6643 S_028C68_MAX_MIP(iview->image->info.levels - 1);
6644 }
6645 }
6646
6647 static unsigned
6648 radv_calc_decompress_on_z_planes(struct radv_device *device,
6649 struct radv_image_view *iview)
6650 {
6651 unsigned max_zplanes = 0;
6652
6653 assert(radv_image_is_tc_compat_htile(iview->image));
6654
6655 if (device->physical_device->rad_info.chip_class >= GFX9) {
6656 /* Default value for 32-bit depth surfaces. */
6657 max_zplanes = 4;
6658
6659 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
6660 iview->image->info.samples > 1)
6661 max_zplanes = 2;
6662
6663 max_zplanes = max_zplanes + 1;
6664 } else {
6665 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
6666 /* Do not enable Z plane compression for 16-bit depth
6667 * surfaces because isn't supported on GFX8. Only
6668 * 32-bit depth surfaces are supported by the hardware.
6669 * This allows to maintain shader compatibility and to
6670 * reduce the number of depth decompressions.
6671 */
6672 max_zplanes = 1;
6673 } else {
6674 if (iview->image->info.samples <= 1)
6675 max_zplanes = 5;
6676 else if (iview->image->info.samples <= 4)
6677 max_zplanes = 3;
6678 else
6679 max_zplanes = 2;
6680 }
6681 }
6682
6683 return max_zplanes;
6684 }
6685
6686 void
6687 radv_initialise_ds_surface(struct radv_device *device,
6688 struct radv_ds_buffer_info *ds,
6689 struct radv_image_view *iview)
6690 {
6691 unsigned level = iview->base_mip;
6692 unsigned format, stencil_format;
6693 uint64_t va, s_offs, z_offs;
6694 bool stencil_only = false;
6695 const struct radv_image_plane *plane = &iview->image->planes[0];
6696 const struct radeon_surf *surf = &plane->surface;
6697
6698 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
6699
6700 memset(ds, 0, sizeof(*ds));
6701 switch (iview->image->vk_format) {
6702 case VK_FORMAT_D24_UNORM_S8_UINT:
6703 case VK_FORMAT_X8_D24_UNORM_PACK32:
6704 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
6705 ds->offset_scale = 2.0f;
6706 break;
6707 case VK_FORMAT_D16_UNORM:
6708 case VK_FORMAT_D16_UNORM_S8_UINT:
6709 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
6710 ds->offset_scale = 4.0f;
6711 break;
6712 case VK_FORMAT_D32_SFLOAT:
6713 case VK_FORMAT_D32_SFLOAT_S8_UINT:
6714 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
6715 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
6716 ds->offset_scale = 1.0f;
6717 break;
6718 case VK_FORMAT_S8_UINT:
6719 stencil_only = true;
6720 break;
6721 default:
6722 break;
6723 }
6724
6725 format = radv_translate_dbformat(iview->image->vk_format);
6726 stencil_format = surf->has_stencil ?
6727 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
6728
6729 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
6730 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
6731 S_028008_SLICE_MAX(max_slice);
6732 if (device->physical_device->rad_info.chip_class >= GFX10) {
6733 ds->db_depth_view |= S_028008_SLICE_START_HI(iview->base_layer >> 11) |
6734 S_028008_SLICE_MAX_HI(max_slice >> 11);
6735 }
6736
6737 ds->db_htile_data_base = 0;
6738 ds->db_htile_surface = 0;
6739
6740 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6741 s_offs = z_offs = va;
6742
6743 if (device->physical_device->rad_info.chip_class >= GFX9) {
6744 assert(surf->u.gfx9.surf_offset == 0);
6745 s_offs += surf->u.gfx9.stencil_offset;
6746
6747 ds->db_z_info = S_028038_FORMAT(format) |
6748 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
6749 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6750 S_028038_MAXMIP(iview->image->info.levels - 1) |
6751 S_028038_ZRANGE_PRECISION(1);
6752 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
6753 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
6754
6755 if (device->physical_device->rad_info.chip_class == GFX9) {
6756 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
6757 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
6758 }
6759
6760 ds->db_depth_view |= S_028008_MIPID(level);
6761 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
6762 S_02801C_Y_MAX(iview->image->info.height - 1);
6763
6764 if (radv_htile_enabled(iview->image, level)) {
6765 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
6766
6767 if (radv_image_is_tc_compat_htile(iview->image)) {
6768 unsigned max_zplanes =
6769 radv_calc_decompress_on_z_planes(device, iview);
6770
6771 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
6772
6773 if (device->physical_device->rad_info.chip_class >= GFX10) {
6774 ds->db_z_info |= S_028040_ITERATE_FLUSH(1);
6775 ds->db_stencil_info |= S_028044_ITERATE_FLUSH(1);
6776 } else {
6777 ds->db_z_info |= S_028038_ITERATE_FLUSH(1);
6778 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
6779 }
6780 }
6781
6782 if (!surf->has_stencil)
6783 /* Use all of the htile_buffer for depth if there's no stencil. */
6784 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
6785 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
6786 iview->image->htile_offset;
6787 ds->db_htile_data_base = va >> 8;
6788 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
6789 S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned);
6790
6791 if (device->physical_device->rad_info.chip_class == GFX9) {
6792 ds->db_htile_surface |= S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
6793 }
6794 }
6795 } else {
6796 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
6797
6798 if (stencil_only)
6799 level_info = &surf->u.legacy.stencil_level[level];
6800
6801 z_offs += surf->u.legacy.level[level].offset;
6802 s_offs += surf->u.legacy.stencil_level[level].offset;
6803
6804 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
6805 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
6806 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
6807
6808 if (iview->image->info.samples > 1)
6809 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
6810
6811 if (device->physical_device->rad_info.chip_class >= GFX7) {
6812 struct radeon_info *info = &device->physical_device->rad_info;
6813 unsigned tiling_index = surf->u.legacy.tiling_index[level];
6814 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
6815 unsigned macro_index = surf->u.legacy.macro_tile_index;
6816 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
6817 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
6818 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
6819
6820 if (stencil_only)
6821 tile_mode = stencil_tile_mode;
6822
6823 ds->db_depth_info |=
6824 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
6825 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
6826 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
6827 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
6828 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
6829 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
6830 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
6831 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
6832 } else {
6833 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
6834 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
6835 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
6836 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
6837 if (stencil_only)
6838 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
6839 }
6840
6841 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
6842 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
6843 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
6844
6845 if (radv_htile_enabled(iview->image, level)) {
6846 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
6847
6848 if (!surf->has_stencil &&
6849 !radv_image_is_tc_compat_htile(iview->image))
6850 /* Use all of the htile_buffer for depth if there's no stencil. */
6851 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
6852
6853 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
6854 iview->image->htile_offset;
6855 ds->db_htile_data_base = va >> 8;
6856 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
6857
6858 if (radv_image_is_tc_compat_htile(iview->image)) {
6859 unsigned max_zplanes =
6860 radv_calc_decompress_on_z_planes(device, iview);
6861
6862 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
6863 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
6864 }
6865 }
6866 }
6867
6868 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
6869 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
6870 }
6871
6872 VkResult radv_CreateFramebuffer(
6873 VkDevice _device,
6874 const VkFramebufferCreateInfo* pCreateInfo,
6875 const VkAllocationCallbacks* pAllocator,
6876 VkFramebuffer* pFramebuffer)
6877 {
6878 RADV_FROM_HANDLE(radv_device, device, _device);
6879 struct radv_framebuffer *framebuffer;
6880 const VkFramebufferAttachmentsCreateInfo *imageless_create_info =
6881 vk_find_struct_const(pCreateInfo->pNext,
6882 FRAMEBUFFER_ATTACHMENTS_CREATE_INFO);
6883
6884 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
6885
6886 size_t size = sizeof(*framebuffer);
6887 if (!imageless_create_info)
6888 size += sizeof(struct radv_image_view*) * pCreateInfo->attachmentCount;
6889 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
6890 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6891 if (framebuffer == NULL)
6892 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6893
6894 framebuffer->attachment_count = pCreateInfo->attachmentCount;
6895 framebuffer->width = pCreateInfo->width;
6896 framebuffer->height = pCreateInfo->height;
6897 framebuffer->layers = pCreateInfo->layers;
6898 if (imageless_create_info) {
6899 for (unsigned i = 0; i < imageless_create_info->attachmentImageInfoCount; ++i) {
6900 const VkFramebufferAttachmentImageInfo *attachment =
6901 imageless_create_info->pAttachmentImageInfos + i;
6902 framebuffer->width = MIN2(framebuffer->width, attachment->width);
6903 framebuffer->height = MIN2(framebuffer->height, attachment->height);
6904 framebuffer->layers = MIN2(framebuffer->layers, attachment->layerCount);
6905 }
6906 } else {
6907 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
6908 VkImageView _iview = pCreateInfo->pAttachments[i];
6909 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
6910 framebuffer->attachments[i] = iview;
6911 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
6912 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
6913 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
6914 }
6915 }
6916
6917 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
6918 return VK_SUCCESS;
6919 }
6920
6921 void radv_DestroyFramebuffer(
6922 VkDevice _device,
6923 VkFramebuffer _fb,
6924 const VkAllocationCallbacks* pAllocator)
6925 {
6926 RADV_FROM_HANDLE(radv_device, device, _device);
6927 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
6928
6929 if (!fb)
6930 return;
6931 vk_free2(&device->alloc, pAllocator, fb);
6932 }
6933
6934 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
6935 {
6936 switch (address_mode) {
6937 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
6938 return V_008F30_SQ_TEX_WRAP;
6939 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
6940 return V_008F30_SQ_TEX_MIRROR;
6941 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
6942 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
6943 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
6944 return V_008F30_SQ_TEX_CLAMP_BORDER;
6945 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
6946 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
6947 default:
6948 unreachable("illegal tex wrap mode");
6949 break;
6950 }
6951 }
6952
6953 static unsigned
6954 radv_tex_compare(VkCompareOp op)
6955 {
6956 switch (op) {
6957 case VK_COMPARE_OP_NEVER:
6958 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
6959 case VK_COMPARE_OP_LESS:
6960 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
6961 case VK_COMPARE_OP_EQUAL:
6962 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
6963 case VK_COMPARE_OP_LESS_OR_EQUAL:
6964 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
6965 case VK_COMPARE_OP_GREATER:
6966 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
6967 case VK_COMPARE_OP_NOT_EQUAL:
6968 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
6969 case VK_COMPARE_OP_GREATER_OR_EQUAL:
6970 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
6971 case VK_COMPARE_OP_ALWAYS:
6972 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
6973 default:
6974 unreachable("illegal compare mode");
6975 break;
6976 }
6977 }
6978
6979 static unsigned
6980 radv_tex_filter(VkFilter filter, unsigned max_ansio)
6981 {
6982 switch (filter) {
6983 case VK_FILTER_NEAREST:
6984 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
6985 V_008F38_SQ_TEX_XY_FILTER_POINT);
6986 case VK_FILTER_LINEAR:
6987 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
6988 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
6989 case VK_FILTER_CUBIC_IMG:
6990 default:
6991 fprintf(stderr, "illegal texture filter");
6992 return 0;
6993 }
6994 }
6995
6996 static unsigned
6997 radv_tex_mipfilter(VkSamplerMipmapMode mode)
6998 {
6999 switch (mode) {
7000 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
7001 return V_008F38_SQ_TEX_Z_FILTER_POINT;
7002 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
7003 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
7004 default:
7005 return V_008F38_SQ_TEX_Z_FILTER_NONE;
7006 }
7007 }
7008
7009 static unsigned
7010 radv_tex_bordercolor(VkBorderColor bcolor)
7011 {
7012 switch (bcolor) {
7013 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
7014 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
7015 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
7016 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
7017 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
7018 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
7019 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
7020 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
7021 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
7022 default:
7023 break;
7024 }
7025 return 0;
7026 }
7027
7028 static unsigned
7029 radv_tex_aniso_filter(unsigned filter)
7030 {
7031 if (filter < 2)
7032 return 0;
7033 if (filter < 4)
7034 return 1;
7035 if (filter < 8)
7036 return 2;
7037 if (filter < 16)
7038 return 3;
7039 return 4;
7040 }
7041
7042 static unsigned
7043 radv_tex_filter_mode(VkSamplerReductionMode mode)
7044 {
7045 switch (mode) {
7046 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
7047 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
7048 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
7049 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
7050 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
7051 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
7052 default:
7053 break;
7054 }
7055 return 0;
7056 }
7057
7058 static uint32_t
7059 radv_get_max_anisotropy(struct radv_device *device,
7060 const VkSamplerCreateInfo *pCreateInfo)
7061 {
7062 if (device->force_aniso >= 0)
7063 return device->force_aniso;
7064
7065 if (pCreateInfo->anisotropyEnable &&
7066 pCreateInfo->maxAnisotropy > 1.0f)
7067 return (uint32_t)pCreateInfo->maxAnisotropy;
7068
7069 return 0;
7070 }
7071
7072 static inline int S_FIXED(float value, unsigned frac_bits)
7073 {
7074 return value * (1 << frac_bits);
7075 }
7076
7077 static void
7078 radv_init_sampler(struct radv_device *device,
7079 struct radv_sampler *sampler,
7080 const VkSamplerCreateInfo *pCreateInfo)
7081 {
7082 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
7083 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
7084 bool compat_mode = device->physical_device->rad_info.chip_class == GFX8 ||
7085 device->physical_device->rad_info.chip_class == GFX9;
7086 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
7087 unsigned depth_compare_func = V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
7088 bool trunc_coord = pCreateInfo->minFilter == VK_FILTER_NEAREST && pCreateInfo->magFilter == VK_FILTER_NEAREST;
7089
7090 const struct VkSamplerReductionModeCreateInfo *sampler_reduction =
7091 vk_find_struct_const(pCreateInfo->pNext,
7092 SAMPLER_REDUCTION_MODE_CREATE_INFO);
7093 if (sampler_reduction)
7094 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
7095
7096 if (pCreateInfo->compareEnable)
7097 depth_compare_func = radv_tex_compare(pCreateInfo->compareOp);
7098
7099 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
7100 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
7101 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
7102 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
7103 S_008F30_DEPTH_COMPARE_FUNC(depth_compare_func) |
7104 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
7105 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
7106 S_008F30_ANISO_BIAS(max_aniso_ratio) |
7107 S_008F30_DISABLE_CUBE_WRAP(0) |
7108 S_008F30_COMPAT_MODE(compat_mode) |
7109 S_008F30_FILTER_MODE(filter_mode) |
7110 S_008F30_TRUNC_COORD(trunc_coord));
7111 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
7112 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
7113 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
7114 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
7115 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
7116 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
7117 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
7118 S_008F38_MIP_POINT_PRECLAMP(0));
7119 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
7120 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
7121
7122 if (device->physical_device->rad_info.chip_class >= GFX10) {
7123 sampler->state[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
7124 } else {
7125 sampler->state[2] |=
7126 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
7127 S_008F38_FILTER_PREC_FIX(1) |
7128 S_008F38_ANISO_OVERRIDE_GFX6(device->physical_device->rad_info.chip_class >= GFX8);
7129 }
7130 }
7131
7132 VkResult radv_CreateSampler(
7133 VkDevice _device,
7134 const VkSamplerCreateInfo* pCreateInfo,
7135 const VkAllocationCallbacks* pAllocator,
7136 VkSampler* pSampler)
7137 {
7138 RADV_FROM_HANDLE(radv_device, device, _device);
7139 struct radv_sampler *sampler;
7140
7141 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
7142 vk_find_struct_const(pCreateInfo->pNext,
7143 SAMPLER_YCBCR_CONVERSION_INFO);
7144
7145 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
7146
7147 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
7148 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
7149 if (!sampler)
7150 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
7151
7152 radv_init_sampler(device, sampler, pCreateInfo);
7153
7154 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
7155 *pSampler = radv_sampler_to_handle(sampler);
7156
7157 return VK_SUCCESS;
7158 }
7159
7160 void radv_DestroySampler(
7161 VkDevice _device,
7162 VkSampler _sampler,
7163 const VkAllocationCallbacks* pAllocator)
7164 {
7165 RADV_FROM_HANDLE(radv_device, device, _device);
7166 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
7167
7168 if (!sampler)
7169 return;
7170 vk_free2(&device->alloc, pAllocator, sampler);
7171 }
7172
7173 /* vk_icd.h does not declare this function, so we declare it here to
7174 * suppress Wmissing-prototypes.
7175 */
7176 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
7177 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
7178
7179 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
7180 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
7181 {
7182 /* For the full details on loader interface versioning, see
7183 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
7184 * What follows is a condensed summary, to help you navigate the large and
7185 * confusing official doc.
7186 *
7187 * - Loader interface v0 is incompatible with later versions. We don't
7188 * support it.
7189 *
7190 * - In loader interface v1:
7191 * - The first ICD entrypoint called by the loader is
7192 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
7193 * entrypoint.
7194 * - The ICD must statically expose no other Vulkan symbol unless it is
7195 * linked with -Bsymbolic.
7196 * - Each dispatchable Vulkan handle created by the ICD must be
7197 * a pointer to a struct whose first member is VK_LOADER_DATA. The
7198 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
7199 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
7200 * vkDestroySurfaceKHR(). The ICD must be capable of working with
7201 * such loader-managed surfaces.
7202 *
7203 * - Loader interface v2 differs from v1 in:
7204 * - The first ICD entrypoint called by the loader is
7205 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
7206 * statically expose this entrypoint.
7207 *
7208 * - Loader interface v3 differs from v2 in:
7209 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
7210 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
7211 * because the loader no longer does so.
7212 */
7213 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
7214 return VK_SUCCESS;
7215 }
7216
7217 VkResult radv_GetMemoryFdKHR(VkDevice _device,
7218 const VkMemoryGetFdInfoKHR *pGetFdInfo,
7219 int *pFD)
7220 {
7221 RADV_FROM_HANDLE(radv_device, device, _device);
7222 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
7223
7224 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
7225
7226 /* At the moment, we support only the below handle types. */
7227 assert(pGetFdInfo->handleType ==
7228 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
7229 pGetFdInfo->handleType ==
7230 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
7231
7232 bool ret = radv_get_memory_fd(device, memory, pFD);
7233 if (ret == false)
7234 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
7235 return VK_SUCCESS;
7236 }
7237
7238 static uint32_t radv_compute_valid_memory_types_attempt(struct radv_physical_device *dev,
7239 enum radeon_bo_domain domains,
7240 enum radeon_bo_flag flags,
7241 enum radeon_bo_flag ignore_flags)
7242 {
7243 /* Don't count GTT/CPU as relevant:
7244 *
7245 * - We're not fully consistent between the two.
7246 * - Sometimes VRAM gets VRAM|GTT.
7247 */
7248 const enum radeon_bo_domain relevant_domains = RADEON_DOMAIN_VRAM |
7249 RADEON_DOMAIN_GDS |
7250 RADEON_DOMAIN_OA;
7251 uint32_t bits = 0;
7252 for (unsigned i = 0; i < dev->memory_properties.memoryTypeCount; ++i) {
7253 if ((domains & relevant_domains) != (dev->memory_domains[i] & relevant_domains))
7254 continue;
7255
7256 if ((flags & ~ignore_flags) != (dev->memory_flags[i] & ~ignore_flags))
7257 continue;
7258
7259 bits |= 1u << i;
7260 }
7261
7262 return bits;
7263 }
7264
7265 static uint32_t radv_compute_valid_memory_types(struct radv_physical_device *dev,
7266 enum radeon_bo_domain domains,
7267 enum radeon_bo_flag flags)
7268 {
7269 enum radeon_bo_flag ignore_flags = ~(RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_GTT_WC);
7270 uint32_t bits = radv_compute_valid_memory_types_attempt(dev, domains, flags, ignore_flags);
7271
7272 if (!bits) {
7273 ignore_flags |= RADEON_FLAG_NO_CPU_ACCESS;
7274 bits = radv_compute_valid_memory_types_attempt(dev, domains, flags, ignore_flags);
7275 }
7276
7277 return bits;
7278 }
7279 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
7280 VkExternalMemoryHandleTypeFlagBits handleType,
7281 int fd,
7282 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
7283 {
7284 RADV_FROM_HANDLE(radv_device, device, _device);
7285
7286 switch (handleType) {
7287 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT: {
7288 enum radeon_bo_domain domains;
7289 enum radeon_bo_flag flags;
7290 if (!device->ws->buffer_get_flags_from_fd(device->ws, fd, &domains, &flags))
7291 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7292
7293 pMemoryFdProperties->memoryTypeBits = radv_compute_valid_memory_types(device->physical_device, domains, flags);
7294 return VK_SUCCESS;
7295 }
7296 default:
7297 /* The valid usage section for this function says:
7298 *
7299 * "handleType must not be one of the handle types defined as
7300 * opaque."
7301 *
7302 * So opaque handle types fall into the default "unsupported" case.
7303 */
7304 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7305 }
7306 }
7307
7308 static VkResult radv_import_opaque_fd(struct radv_device *device,
7309 int fd,
7310 uint32_t *syncobj)
7311 {
7312 uint32_t syncobj_handle = 0;
7313 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
7314 if (ret != 0)
7315 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7316
7317 if (*syncobj)
7318 device->ws->destroy_syncobj(device->ws, *syncobj);
7319
7320 *syncobj = syncobj_handle;
7321 close(fd);
7322
7323 return VK_SUCCESS;
7324 }
7325
7326 static VkResult radv_import_sync_fd(struct radv_device *device,
7327 int fd,
7328 uint32_t *syncobj)
7329 {
7330 /* If we create a syncobj we do it locally so that if we have an error, we don't
7331 * leave a syncobj in an undetermined state in the fence. */
7332 uint32_t syncobj_handle = *syncobj;
7333 if (!syncobj_handle) {
7334 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
7335 if (ret) {
7336 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7337 }
7338 }
7339
7340 if (fd == -1) {
7341 device->ws->signal_syncobj(device->ws, syncobj_handle);
7342 } else {
7343 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
7344 if (ret != 0)
7345 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7346 }
7347
7348 *syncobj = syncobj_handle;
7349 if (fd != -1)
7350 close(fd);
7351
7352 return VK_SUCCESS;
7353 }
7354
7355 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
7356 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
7357 {
7358 RADV_FROM_HANDLE(radv_device, device, _device);
7359 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
7360 VkResult result;
7361 struct radv_semaphore_part *dst = NULL;
7362
7363 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
7364 dst = &sem->temporary;
7365 } else {
7366 dst = &sem->permanent;
7367 }
7368
7369 uint32_t syncobj = dst->kind == RADV_SEMAPHORE_SYNCOBJ ? dst->syncobj : 0;
7370
7371 switch(pImportSemaphoreFdInfo->handleType) {
7372 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
7373 result = radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, &syncobj);
7374 break;
7375 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
7376 result = radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, &syncobj);
7377 break;
7378 default:
7379 unreachable("Unhandled semaphore handle type");
7380 }
7381
7382 if (result == VK_SUCCESS) {
7383 dst->syncobj = syncobj;
7384 dst->kind = RADV_SEMAPHORE_SYNCOBJ;
7385 }
7386
7387 return result;
7388 }
7389
7390 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
7391 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
7392 int *pFd)
7393 {
7394 RADV_FROM_HANDLE(radv_device, device, _device);
7395 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
7396 int ret;
7397 uint32_t syncobj_handle;
7398
7399 if (sem->temporary.kind != RADV_SEMAPHORE_NONE) {
7400 assert(sem->temporary.kind == RADV_SEMAPHORE_SYNCOBJ);
7401 syncobj_handle = sem->temporary.syncobj;
7402 } else {
7403 assert(sem->permanent.kind == RADV_SEMAPHORE_SYNCOBJ);
7404 syncobj_handle = sem->permanent.syncobj;
7405 }
7406
7407 switch(pGetFdInfo->handleType) {
7408 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
7409 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
7410 break;
7411 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
7412 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
7413 if (!ret) {
7414 if (sem->temporary.kind != RADV_SEMAPHORE_NONE) {
7415 radv_destroy_semaphore_part(device, &sem->temporary);
7416 } else {
7417 device->ws->reset_syncobj(device->ws, syncobj_handle);
7418 }
7419 }
7420 break;
7421 default:
7422 unreachable("Unhandled semaphore handle type");
7423 }
7424
7425 if (ret)
7426 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7427 return VK_SUCCESS;
7428 }
7429
7430 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
7431 VkPhysicalDevice physicalDevice,
7432 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
7433 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
7434 {
7435 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
7436 VkSemaphoreTypeKHR type = radv_get_semaphore_type(pExternalSemaphoreInfo->pNext, NULL);
7437
7438 if (type == VK_SEMAPHORE_TYPE_TIMELINE) {
7439 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
7440 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
7441 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
7442
7443 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
7444 } else if (pdevice->rad_info.has_syncobj_wait_for_submit &&
7445 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
7446 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
7447 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
7448 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
7449 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
7450 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7451 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
7452 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
7453 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
7454 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
7455 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7456 } else {
7457 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
7458 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
7459 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
7460 }
7461 }
7462
7463 VkResult radv_ImportFenceFdKHR(VkDevice _device,
7464 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
7465 {
7466 RADV_FROM_HANDLE(radv_device, device, _device);
7467 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
7468 uint32_t *syncobj_dst = NULL;
7469
7470
7471 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
7472 syncobj_dst = &fence->temp_syncobj;
7473 } else {
7474 syncobj_dst = &fence->syncobj;
7475 }
7476
7477 switch(pImportFenceFdInfo->handleType) {
7478 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
7479 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
7480 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
7481 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
7482 default:
7483 unreachable("Unhandled fence handle type");
7484 }
7485 }
7486
7487 VkResult radv_GetFenceFdKHR(VkDevice _device,
7488 const VkFenceGetFdInfoKHR *pGetFdInfo,
7489 int *pFd)
7490 {
7491 RADV_FROM_HANDLE(radv_device, device, _device);
7492 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
7493 int ret;
7494 uint32_t syncobj_handle;
7495
7496 if (fence->temp_syncobj)
7497 syncobj_handle = fence->temp_syncobj;
7498 else
7499 syncobj_handle = fence->syncobj;
7500
7501 switch(pGetFdInfo->handleType) {
7502 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
7503 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
7504 break;
7505 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
7506 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
7507 if (!ret) {
7508 if (fence->temp_syncobj) {
7509 close (fence->temp_syncobj);
7510 fence->temp_syncobj = 0;
7511 } else {
7512 device->ws->reset_syncobj(device->ws, syncobj_handle);
7513 }
7514 }
7515 break;
7516 default:
7517 unreachable("Unhandled fence handle type");
7518 }
7519
7520 if (ret)
7521 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7522 return VK_SUCCESS;
7523 }
7524
7525 void radv_GetPhysicalDeviceExternalFenceProperties(
7526 VkPhysicalDevice physicalDevice,
7527 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
7528 VkExternalFenceProperties *pExternalFenceProperties)
7529 {
7530 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
7531
7532 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
7533 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
7534 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
7535 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
7536 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
7537 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
7538 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7539 } else {
7540 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
7541 pExternalFenceProperties->compatibleHandleTypes = 0;
7542 pExternalFenceProperties->externalFenceFeatures = 0;
7543 }
7544 }
7545
7546 VkResult
7547 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
7548 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
7549 const VkAllocationCallbacks* pAllocator,
7550 VkDebugReportCallbackEXT* pCallback)
7551 {
7552 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7553 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
7554 pCreateInfo, pAllocator, &instance->alloc,
7555 pCallback);
7556 }
7557
7558 void
7559 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
7560 VkDebugReportCallbackEXT _callback,
7561 const VkAllocationCallbacks* pAllocator)
7562 {
7563 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7564 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
7565 _callback, pAllocator, &instance->alloc);
7566 }
7567
7568 void
7569 radv_DebugReportMessageEXT(VkInstance _instance,
7570 VkDebugReportFlagsEXT flags,
7571 VkDebugReportObjectTypeEXT objectType,
7572 uint64_t object,
7573 size_t location,
7574 int32_t messageCode,
7575 const char* pLayerPrefix,
7576 const char* pMessage)
7577 {
7578 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7579 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
7580 object, location, messageCode, pLayerPrefix, pMessage);
7581 }
7582
7583 void
7584 radv_GetDeviceGroupPeerMemoryFeatures(
7585 VkDevice device,
7586 uint32_t heapIndex,
7587 uint32_t localDeviceIndex,
7588 uint32_t remoteDeviceIndex,
7589 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
7590 {
7591 assert(localDeviceIndex == remoteDeviceIndex);
7592
7593 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
7594 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
7595 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
7596 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
7597 }
7598
7599 static const VkTimeDomainEXT radv_time_domains[] = {
7600 VK_TIME_DOMAIN_DEVICE_EXT,
7601 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
7602 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
7603 };
7604
7605 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
7606 VkPhysicalDevice physicalDevice,
7607 uint32_t *pTimeDomainCount,
7608 VkTimeDomainEXT *pTimeDomains)
7609 {
7610 int d;
7611 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
7612
7613 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
7614 vk_outarray_append(&out, i) {
7615 *i = radv_time_domains[d];
7616 }
7617 }
7618
7619 return vk_outarray_status(&out);
7620 }
7621
7622 static uint64_t
7623 radv_clock_gettime(clockid_t clock_id)
7624 {
7625 struct timespec current;
7626 int ret;
7627
7628 ret = clock_gettime(clock_id, &current);
7629 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
7630 ret = clock_gettime(CLOCK_MONOTONIC, &current);
7631 if (ret < 0)
7632 return 0;
7633
7634 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
7635 }
7636
7637 VkResult radv_GetCalibratedTimestampsEXT(
7638 VkDevice _device,
7639 uint32_t timestampCount,
7640 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
7641 uint64_t *pTimestamps,
7642 uint64_t *pMaxDeviation)
7643 {
7644 RADV_FROM_HANDLE(radv_device, device, _device);
7645 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
7646 int d;
7647 uint64_t begin, end;
7648 uint64_t max_clock_period = 0;
7649
7650 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
7651
7652 for (d = 0; d < timestampCount; d++) {
7653 switch (pTimestampInfos[d].timeDomain) {
7654 case VK_TIME_DOMAIN_DEVICE_EXT:
7655 pTimestamps[d] = device->ws->query_value(device->ws,
7656 RADEON_TIMESTAMP);
7657 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
7658 max_clock_period = MAX2(max_clock_period, device_period);
7659 break;
7660 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
7661 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
7662 max_clock_period = MAX2(max_clock_period, 1);
7663 break;
7664
7665 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
7666 pTimestamps[d] = begin;
7667 break;
7668 default:
7669 pTimestamps[d] = 0;
7670 break;
7671 }
7672 }
7673
7674 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
7675
7676 /*
7677 * The maximum deviation is the sum of the interval over which we
7678 * perform the sampling and the maximum period of any sampled
7679 * clock. That's because the maximum skew between any two sampled
7680 * clock edges is when the sampled clock with the largest period is
7681 * sampled at the end of that period but right at the beginning of the
7682 * sampling interval and some other clock is sampled right at the
7683 * begining of its sampling period and right at the end of the
7684 * sampling interval. Let's assume the GPU has the longest clock
7685 * period and that the application is sampling GPU and monotonic:
7686 *
7687 * s e
7688 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
7689 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7690 *
7691 * g
7692 * 0 1 2 3
7693 * GPU -----_____-----_____-----_____-----_____
7694 *
7695 * m
7696 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
7697 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7698 *
7699 * Interval <----------------->
7700 * Deviation <-------------------------->
7701 *
7702 * s = read(raw) 2
7703 * g = read(GPU) 1
7704 * m = read(monotonic) 2
7705 * e = read(raw) b
7706 *
7707 * We round the sample interval up by one tick to cover sampling error
7708 * in the interval clock
7709 */
7710
7711 uint64_t sample_interval = end - begin + 1;
7712
7713 *pMaxDeviation = sample_interval + max_clock_period;
7714
7715 return VK_SUCCESS;
7716 }
7717
7718 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
7719 VkPhysicalDevice physicalDevice,
7720 VkSampleCountFlagBits samples,
7721 VkMultisamplePropertiesEXT* pMultisampleProperties)
7722 {
7723 if (samples & (VK_SAMPLE_COUNT_2_BIT |
7724 VK_SAMPLE_COUNT_4_BIT |
7725 VK_SAMPLE_COUNT_8_BIT)) {
7726 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 };
7727 } else {
7728 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 };
7729 }
7730 }