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14ecbd020014404cee96f1eb390e8fe57930166c
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "gfx9d.h"
47 #include "addrlib/gfx9/chip/gfx9_enum.h"
48 #include "util/debug.h"
49
50 static int
51 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
52 {
53 uint32_t mesa_timestamp, llvm_timestamp;
54 uint16_t f = family;
55 memset(uuid, 0, VK_UUID_SIZE);
56 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
57 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
58 return -1;
59
60 memcpy(uuid, &mesa_timestamp, 4);
61 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
62 memcpy((char*)uuid + 8, &f, 2);
63 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
64 return 0;
65 }
66
67 static void
68 radv_get_driver_uuid(void *uuid)
69 {
70 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
71 }
72
73 static void
74 radv_get_device_uuid(struct radeon_info *info, void *uuid)
75 {
76 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
77 }
78
79 static void
80 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
81 {
82 const char *chip_string;
83 char llvm_string[32] = {};
84
85 switch (family) {
86 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
87 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
88 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
89 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
90 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
91 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
92 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
93 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
94 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
95 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
96 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
97 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
98 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
99 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
100 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
101 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
102 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
103 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
104 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
105 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
106 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
107 default: chip_string = "AMD RADV unknown"; break;
108 }
109
110 if (HAVE_LLVM > 0) {
111 snprintf(llvm_string, sizeof(llvm_string),
112 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
113 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
114 }
115
116 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
117 }
118
119 static void
120 radv_physical_device_init_mem_types(struct radv_physical_device *device)
121 {
122 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
123 uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
124 device->rad_info.vram_vis_size);
125
126 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
127 device->memory_properties.memoryHeapCount = 0;
128 if (device->rad_info.vram_size - visible_vram_size > 0) {
129 vram_index = device->memory_properties.memoryHeapCount++;
130 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
131 .size = device->rad_info.vram_size - visible_vram_size,
132 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
133 };
134 }
135 if (visible_vram_size) {
136 visible_vram_index = device->memory_properties.memoryHeapCount++;
137 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
138 .size = visible_vram_size,
139 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
140 };
141 }
142 if (device->rad_info.gart_size > 0) {
143 gart_index = device->memory_properties.memoryHeapCount++;
144 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
145 .size = device->rad_info.gart_size,
146 .flags = 0,
147 };
148 }
149
150 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
151 unsigned type_count = 0;
152 if (vram_index >= 0) {
153 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
154 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
155 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
156 .heapIndex = vram_index,
157 };
158 }
159 if (gart_index >= 0) {
160 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
161 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
162 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
163 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
164 .heapIndex = gart_index,
165 };
166 }
167 if (visible_vram_index >= 0) {
168 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
169 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
170 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
171 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
172 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
173 .heapIndex = visible_vram_index,
174 };
175 }
176 if (gart_index >= 0) {
177 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
178 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
179 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
180 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
181 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
182 .heapIndex = gart_index,
183 };
184 }
185 device->memory_properties.memoryTypeCount = type_count;
186 }
187
188 static void
189 radv_handle_env_var_force_family(struct radv_physical_device *device)
190 {
191 const char *family = getenv("RADV_FORCE_FAMILY");
192 unsigned i;
193
194 if (!family)
195 return;
196
197 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
198 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
199 /* Override family and chip_class. */
200 device->rad_info.family = i;
201
202 if (i >= CHIP_VEGA10)
203 device->rad_info.chip_class = GFX9;
204 else if (i >= CHIP_TONGA)
205 device->rad_info.chip_class = VI;
206 else if (i >= CHIP_BONAIRE)
207 device->rad_info.chip_class = CIK;
208 else
209 device->rad_info.chip_class = SI;
210
211 return;
212 }
213 }
214
215 fprintf(stderr, "radv: Unknown family: %s\n", family);
216 exit(1);
217 }
218
219 static VkResult
220 radv_physical_device_init(struct radv_physical_device *device,
221 struct radv_instance *instance,
222 drmDevicePtr drm_device)
223 {
224 const char *path = drm_device->nodes[DRM_NODE_RENDER];
225 VkResult result;
226 drmVersionPtr version;
227 int fd;
228
229 fd = open(path, O_RDWR | O_CLOEXEC);
230 if (fd < 0)
231 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
232
233 version = drmGetVersion(fd);
234 if (!version) {
235 close(fd);
236 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
237 "failed to get version %s: %m", path);
238 }
239
240 if (strcmp(version->name, "amdgpu")) {
241 drmFreeVersion(version);
242 close(fd);
243 return VK_ERROR_INCOMPATIBLE_DRIVER;
244 }
245 drmFreeVersion(version);
246
247 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
248 device->instance = instance;
249 assert(strlen(path) < ARRAY_SIZE(device->path));
250 strncpy(device->path, path, ARRAY_SIZE(device->path));
251
252 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
253 instance->perftest_flags);
254 if (!device->ws) {
255 result = VK_ERROR_INCOMPATIBLE_DRIVER;
256 goto fail;
257 }
258
259 device->local_fd = fd;
260 device->ws->query_info(device->ws, &device->rad_info);
261
262 radv_handle_env_var_force_family(device);
263
264 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
265
266 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
267 device->ws->destroy(device->ws);
268 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
269 "cannot generate UUID");
270 goto fail;
271 }
272
273 /* These flags affect shader compilation. */
274 uint64_t shader_env_flags =
275 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
276 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
277
278 /* The gpu id is already embeded in the uuid so we just pass "radv"
279 * when creating the cache.
280 */
281 char buf[VK_UUID_SIZE * 2 + 1];
282 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
283 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
284
285 if (device->rad_info.chip_class < VI ||
286 device->rad_info.chip_class > GFX9)
287 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
288
289 radv_get_driver_uuid(&device->device_uuid);
290 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
291
292 if (device->rad_info.family == CHIP_STONEY ||
293 device->rad_info.chip_class >= GFX9) {
294 device->has_rbplus = true;
295 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
296 device->rad_info.family == CHIP_VEGA12 ||
297 device->rad_info.family == CHIP_RAVEN;
298 }
299
300 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
301 * on SI.
302 */
303 device->has_clear_state = device->rad_info.chip_class >= CIK;
304
305 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
306
307 /* Vega10/Raven need a special workaround for a hardware bug. */
308 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
309 device->rad_info.family == CHIP_RAVEN;
310
311 /* Out-of-order primitive rasterization. */
312 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
313 device->rad_info.max_se >= 2;
314 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
315 (device->instance->perftest_flags & RADV_PERFTEST_OUT_OF_ORDER);
316
317 device->dcc_msaa_allowed = device->rad_info.chip_class == VI &&
318 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
319
320 radv_physical_device_init_mem_types(device);
321 radv_fill_device_extension_table(device, &device->supported_extensions);
322
323 result = radv_init_wsi(device);
324 if (result != VK_SUCCESS) {
325 device->ws->destroy(device->ws);
326 goto fail;
327 }
328
329 return VK_SUCCESS;
330
331 fail:
332 close(fd);
333 return result;
334 }
335
336 static void
337 radv_physical_device_finish(struct radv_physical_device *device)
338 {
339 radv_finish_wsi(device);
340 device->ws->destroy(device->ws);
341 disk_cache_destroy(device->disk_cache);
342 close(device->local_fd);
343 }
344
345 static void *
346 default_alloc_func(void *pUserData, size_t size, size_t align,
347 VkSystemAllocationScope allocationScope)
348 {
349 return malloc(size);
350 }
351
352 static void *
353 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
354 size_t align, VkSystemAllocationScope allocationScope)
355 {
356 return realloc(pOriginal, size);
357 }
358
359 static void
360 default_free_func(void *pUserData, void *pMemory)
361 {
362 free(pMemory);
363 }
364
365 static const VkAllocationCallbacks default_alloc = {
366 .pUserData = NULL,
367 .pfnAllocation = default_alloc_func,
368 .pfnReallocation = default_realloc_func,
369 .pfnFree = default_free_func,
370 };
371
372 static const struct debug_control radv_debug_options[] = {
373 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
374 {"nodcc", RADV_DEBUG_NO_DCC},
375 {"shaders", RADV_DEBUG_DUMP_SHADERS},
376 {"nocache", RADV_DEBUG_NO_CACHE},
377 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
378 {"nohiz", RADV_DEBUG_NO_HIZ},
379 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
380 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
381 {"allbos", RADV_DEBUG_ALL_BOS},
382 {"noibs", RADV_DEBUG_NO_IBS},
383 {"spirv", RADV_DEBUG_DUMP_SPIRV},
384 {"vmfaults", RADV_DEBUG_VM_FAULTS},
385 {"zerovram", RADV_DEBUG_ZERO_VRAM},
386 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
387 {"nosisched", RADV_DEBUG_NO_SISCHED},
388 {"preoptir", RADV_DEBUG_PREOPTIR},
389 {NULL, 0}
390 };
391
392 const char *
393 radv_get_debug_option_name(int id)
394 {
395 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
396 return radv_debug_options[id].string;
397 }
398
399 static const struct debug_control radv_perftest_options[] = {
400 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
401 {"sisched", RADV_PERFTEST_SISCHED},
402 {"localbos", RADV_PERFTEST_LOCAL_BOS},
403 {"binning", RADV_PERFTEST_BINNING},
404 {"outoforderrast", RADV_PERFTEST_OUT_OF_ORDER},
405 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
406 {NULL, 0}
407 };
408
409 const char *
410 radv_get_perftest_option_name(int id)
411 {
412 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
413 return radv_perftest_options[id].string;
414 }
415
416 static void
417 radv_handle_per_app_options(struct radv_instance *instance,
418 const VkApplicationInfo *info)
419 {
420 const char *name = info ? info->pApplicationName : NULL;
421
422 if (!name)
423 return;
424
425 if (!strcmp(name, "Talos - Linux - 32bit") ||
426 !strcmp(name, "Talos - Linux - 64bit")) {
427 /* Force enable LLVM sisched for Talos because it looks safe
428 * and it gives few more FPS.
429 */
430 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
431 }
432 }
433
434 static int radv_get_instance_extension_index(const char *name)
435 {
436 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
437 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
438 return i;
439 }
440 return -1;
441 }
442
443
444 VkResult radv_CreateInstance(
445 const VkInstanceCreateInfo* pCreateInfo,
446 const VkAllocationCallbacks* pAllocator,
447 VkInstance* pInstance)
448 {
449 struct radv_instance *instance;
450 VkResult result;
451
452 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
453
454 uint32_t client_version;
455 if (pCreateInfo->pApplicationInfo &&
456 pCreateInfo->pApplicationInfo->apiVersion != 0) {
457 client_version = pCreateInfo->pApplicationInfo->apiVersion;
458 } else {
459 client_version = VK_MAKE_VERSION(1, 0, 0);
460 }
461
462 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
463 client_version > VK_MAKE_VERSION(1, 1, 0xfff)) {
464 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
465 "Client requested version %d.%d.%d",
466 VK_VERSION_MAJOR(client_version),
467 VK_VERSION_MINOR(client_version),
468 VK_VERSION_PATCH(client_version));
469 }
470
471 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
472 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
473 if (!instance)
474 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
475
476 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
477
478 if (pAllocator)
479 instance->alloc = *pAllocator;
480 else
481 instance->alloc = default_alloc;
482
483 instance->apiVersion = client_version;
484 instance->physicalDeviceCount = -1;
485
486 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
487 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
488 int index = radv_get_instance_extension_index(ext_name);
489
490 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
491 vk_free2(&default_alloc, pAllocator, instance);
492 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
493 }
494
495 instance->enabled_extensions.extensions[index] = true;
496 }
497
498 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
499 if (result != VK_SUCCESS) {
500 vk_free2(&default_alloc, pAllocator, instance);
501 return vk_error(result);
502 }
503
504 _mesa_locale_init();
505
506 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
507
508 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
509 radv_debug_options);
510
511 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
512 radv_perftest_options);
513
514 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
515
516 if (instance->debug_flags & RADV_DEBUG_NO_SISCHED) {
517 /* Disable sisched when the user requests it, this is mostly
518 * useful when the driver force-enable sisched for the given
519 * application.
520 */
521 instance->perftest_flags &= ~RADV_PERFTEST_SISCHED;
522 }
523
524 *pInstance = radv_instance_to_handle(instance);
525
526 return VK_SUCCESS;
527 }
528
529 void radv_DestroyInstance(
530 VkInstance _instance,
531 const VkAllocationCallbacks* pAllocator)
532 {
533 RADV_FROM_HANDLE(radv_instance, instance, _instance);
534
535 if (!instance)
536 return;
537
538 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
539 radv_physical_device_finish(instance->physicalDevices + i);
540 }
541
542 VG(VALGRIND_DESTROY_MEMPOOL(instance));
543
544 _mesa_locale_fini();
545
546 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
547
548 vk_free(&instance->alloc, instance);
549 }
550
551 static VkResult
552 radv_enumerate_devices(struct radv_instance *instance)
553 {
554 /* TODO: Check for more devices ? */
555 drmDevicePtr devices[8];
556 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
557 int max_devices;
558
559 instance->physicalDeviceCount = 0;
560
561 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
562 if (max_devices < 1)
563 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
564
565 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
566 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
567 devices[i]->bustype == DRM_BUS_PCI &&
568 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
569
570 result = radv_physical_device_init(instance->physicalDevices +
571 instance->physicalDeviceCount,
572 instance,
573 devices[i]);
574 if (result == VK_SUCCESS)
575 ++instance->physicalDeviceCount;
576 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
577 break;
578 }
579 }
580 drmFreeDevices(devices, max_devices);
581
582 return result;
583 }
584
585 VkResult radv_EnumeratePhysicalDevices(
586 VkInstance _instance,
587 uint32_t* pPhysicalDeviceCount,
588 VkPhysicalDevice* pPhysicalDevices)
589 {
590 RADV_FROM_HANDLE(radv_instance, instance, _instance);
591 VkResult result;
592
593 if (instance->physicalDeviceCount < 0) {
594 result = radv_enumerate_devices(instance);
595 if (result != VK_SUCCESS &&
596 result != VK_ERROR_INCOMPATIBLE_DRIVER)
597 return result;
598 }
599
600 if (!pPhysicalDevices) {
601 *pPhysicalDeviceCount = instance->physicalDeviceCount;
602 } else {
603 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
604 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
605 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
606 }
607
608 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
609 : VK_SUCCESS;
610 }
611
612 VkResult radv_EnumeratePhysicalDeviceGroups(
613 VkInstance _instance,
614 uint32_t* pPhysicalDeviceGroupCount,
615 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
616 {
617 RADV_FROM_HANDLE(radv_instance, instance, _instance);
618 VkResult result;
619
620 if (instance->physicalDeviceCount < 0) {
621 result = radv_enumerate_devices(instance);
622 if (result != VK_SUCCESS &&
623 result != VK_ERROR_INCOMPATIBLE_DRIVER)
624 return result;
625 }
626
627 if (!pPhysicalDeviceGroupProperties) {
628 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
629 } else {
630 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
631 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
632 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
633 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
634 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
635 }
636 }
637 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
638 : VK_SUCCESS;
639 }
640
641 void radv_GetPhysicalDeviceFeatures(
642 VkPhysicalDevice physicalDevice,
643 VkPhysicalDeviceFeatures* pFeatures)
644 {
645 memset(pFeatures, 0, sizeof(*pFeatures));
646
647 *pFeatures = (VkPhysicalDeviceFeatures) {
648 .robustBufferAccess = true,
649 .fullDrawIndexUint32 = true,
650 .imageCubeArray = true,
651 .independentBlend = true,
652 .geometryShader = true,
653 .tessellationShader = true,
654 .sampleRateShading = true,
655 .dualSrcBlend = true,
656 .logicOp = true,
657 .multiDrawIndirect = true,
658 .drawIndirectFirstInstance = true,
659 .depthClamp = true,
660 .depthBiasClamp = true,
661 .fillModeNonSolid = true,
662 .depthBounds = true,
663 .wideLines = true,
664 .largePoints = true,
665 .alphaToOne = true,
666 .multiViewport = true,
667 .samplerAnisotropy = true,
668 .textureCompressionETC2 = false,
669 .textureCompressionASTC_LDR = false,
670 .textureCompressionBC = true,
671 .occlusionQueryPrecise = true,
672 .pipelineStatisticsQuery = true,
673 .vertexPipelineStoresAndAtomics = true,
674 .fragmentStoresAndAtomics = true,
675 .shaderTessellationAndGeometryPointSize = true,
676 .shaderImageGatherExtended = true,
677 .shaderStorageImageExtendedFormats = true,
678 .shaderStorageImageMultisample = false,
679 .shaderUniformBufferArrayDynamicIndexing = true,
680 .shaderSampledImageArrayDynamicIndexing = true,
681 .shaderStorageBufferArrayDynamicIndexing = true,
682 .shaderStorageImageArrayDynamicIndexing = true,
683 .shaderStorageImageReadWithoutFormat = true,
684 .shaderStorageImageWriteWithoutFormat = true,
685 .shaderClipDistance = true,
686 .shaderCullDistance = true,
687 .shaderFloat64 = true,
688 .shaderInt64 = true,
689 .shaderInt16 = false,
690 .sparseBinding = true,
691 .variableMultisampleRate = true,
692 .inheritedQueries = true,
693 };
694 }
695
696 void radv_GetPhysicalDeviceFeatures2(
697 VkPhysicalDevice physicalDevice,
698 VkPhysicalDeviceFeatures2KHR *pFeatures)
699 {
700 vk_foreach_struct(ext, pFeatures->pNext) {
701 switch (ext->sType) {
702 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
703 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
704 features->variablePointersStorageBuffer = true;
705 features->variablePointers = false;
706 break;
707 }
708 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHR: {
709 VkPhysicalDeviceMultiviewFeaturesKHR *features = (VkPhysicalDeviceMultiviewFeaturesKHR*)ext;
710 features->multiview = true;
711 features->multiviewGeometryShader = true;
712 features->multiviewTessellationShader = true;
713 break;
714 }
715 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
716 VkPhysicalDeviceShaderDrawParameterFeatures *features =
717 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
718 features->shaderDrawParameters = true;
719 break;
720 }
721 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
722 VkPhysicalDeviceProtectedMemoryFeatures *features =
723 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
724 features->protectedMemory = false;
725 break;
726 }
727 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
728 VkPhysicalDevice16BitStorageFeatures *features =
729 (VkPhysicalDevice16BitStorageFeatures*)ext;
730 features->storageBuffer16BitAccess = false;
731 features->uniformAndStorageBuffer16BitAccess = false;
732 features->storagePushConstant16 = false;
733 features->storageInputOutput16 = false;
734 break;
735 }
736 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
737 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
738 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
739 features->samplerYcbcrConversion = false;
740 break;
741 }
742 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
743 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
744 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)features;
745 features->shaderInputAttachmentArrayDynamicIndexing = true;
746 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
747 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
748 features->shaderUniformBufferArrayNonUniformIndexing = false;
749 features->shaderSampledImageArrayNonUniformIndexing = false;
750 features->shaderStorageBufferArrayNonUniformIndexing = false;
751 features->shaderStorageImageArrayNonUniformIndexing = false;
752 features->shaderInputAttachmentArrayNonUniformIndexing = false;
753 features->shaderUniformTexelBufferArrayNonUniformIndexing = false;
754 features->shaderStorageTexelBufferArrayNonUniformIndexing = false;
755 features->descriptorBindingUniformBufferUpdateAfterBind = true;
756 features->descriptorBindingSampledImageUpdateAfterBind = true;
757 features->descriptorBindingStorageImageUpdateAfterBind = true;
758 features->descriptorBindingStorageBufferUpdateAfterBind = true;
759 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
760 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
761 features->descriptorBindingUpdateUnusedWhilePending = true;
762 features->descriptorBindingPartiallyBound = true;
763 features->descriptorBindingVariableDescriptorCount = true;
764 features->runtimeDescriptorArray = true;
765 break;
766 }
767 default:
768 break;
769 }
770 }
771 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
772 }
773
774 void radv_GetPhysicalDeviceProperties(
775 VkPhysicalDevice physicalDevice,
776 VkPhysicalDeviceProperties* pProperties)
777 {
778 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
779 VkSampleCountFlags sample_counts = 0xf;
780
781 /* make sure that the entire descriptor set is addressable with a signed
782 * 32-bit int. So the sum of all limits scaled by descriptor size has to
783 * be at most 2 GiB. the combined image & samples object count as one of
784 * both. This limit is for the pipeline layout, not for the set layout, but
785 * there is no set limit, so we just set a pipeline limit. I don't think
786 * any app is going to hit this soon. */
787 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
788 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
789 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
790 32 /* sampler, largest when combined with image */ +
791 64 /* sampled image */ +
792 64 /* storage image */);
793
794 VkPhysicalDeviceLimits limits = {
795 .maxImageDimension1D = (1 << 14),
796 .maxImageDimension2D = (1 << 14),
797 .maxImageDimension3D = (1 << 11),
798 .maxImageDimensionCube = (1 << 14),
799 .maxImageArrayLayers = (1 << 11),
800 .maxTexelBufferElements = 128 * 1024 * 1024,
801 .maxUniformBufferRange = UINT32_MAX,
802 .maxStorageBufferRange = UINT32_MAX,
803 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
804 .maxMemoryAllocationCount = UINT32_MAX,
805 .maxSamplerAllocationCount = 64 * 1024,
806 .bufferImageGranularity = 64, /* A cache line */
807 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
808 .maxBoundDescriptorSets = MAX_SETS,
809 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
810 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
811 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
812 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
813 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
814 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
815 .maxPerStageResources = max_descriptor_set_size,
816 .maxDescriptorSetSamplers = max_descriptor_set_size,
817 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
818 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
819 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
820 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
821 .maxDescriptorSetSampledImages = max_descriptor_set_size,
822 .maxDescriptorSetStorageImages = max_descriptor_set_size,
823 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
824 .maxVertexInputAttributes = 32,
825 .maxVertexInputBindings = 32,
826 .maxVertexInputAttributeOffset = 2047,
827 .maxVertexInputBindingStride = 2048,
828 .maxVertexOutputComponents = 128,
829 .maxTessellationGenerationLevel = 64,
830 .maxTessellationPatchSize = 32,
831 .maxTessellationControlPerVertexInputComponents = 128,
832 .maxTessellationControlPerVertexOutputComponents = 128,
833 .maxTessellationControlPerPatchOutputComponents = 120,
834 .maxTessellationControlTotalOutputComponents = 4096,
835 .maxTessellationEvaluationInputComponents = 128,
836 .maxTessellationEvaluationOutputComponents = 128,
837 .maxGeometryShaderInvocations = 127,
838 .maxGeometryInputComponents = 64,
839 .maxGeometryOutputComponents = 128,
840 .maxGeometryOutputVertices = 256,
841 .maxGeometryTotalOutputComponents = 1024,
842 .maxFragmentInputComponents = 128,
843 .maxFragmentOutputAttachments = 8,
844 .maxFragmentDualSrcAttachments = 1,
845 .maxFragmentCombinedOutputResources = 8,
846 .maxComputeSharedMemorySize = 32768,
847 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
848 .maxComputeWorkGroupInvocations = 2048,
849 .maxComputeWorkGroupSize = {
850 2048,
851 2048,
852 2048
853 },
854 .subPixelPrecisionBits = 4 /* FIXME */,
855 .subTexelPrecisionBits = 4 /* FIXME */,
856 .mipmapPrecisionBits = 4 /* FIXME */,
857 .maxDrawIndexedIndexValue = UINT32_MAX,
858 .maxDrawIndirectCount = UINT32_MAX,
859 .maxSamplerLodBias = 16,
860 .maxSamplerAnisotropy = 16,
861 .maxViewports = MAX_VIEWPORTS,
862 .maxViewportDimensions = { (1 << 14), (1 << 14) },
863 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
864 .viewportSubPixelBits = 13, /* We take a float? */
865 .minMemoryMapAlignment = 4096, /* A page */
866 .minTexelBufferOffsetAlignment = 1,
867 .minUniformBufferOffsetAlignment = 4,
868 .minStorageBufferOffsetAlignment = 4,
869 .minTexelOffset = -32,
870 .maxTexelOffset = 31,
871 .minTexelGatherOffset = -32,
872 .maxTexelGatherOffset = 31,
873 .minInterpolationOffset = -2,
874 .maxInterpolationOffset = 2,
875 .subPixelInterpolationOffsetBits = 8,
876 .maxFramebufferWidth = (1 << 14),
877 .maxFramebufferHeight = (1 << 14),
878 .maxFramebufferLayers = (1 << 10),
879 .framebufferColorSampleCounts = sample_counts,
880 .framebufferDepthSampleCounts = sample_counts,
881 .framebufferStencilSampleCounts = sample_counts,
882 .framebufferNoAttachmentsSampleCounts = sample_counts,
883 .maxColorAttachments = MAX_RTS,
884 .sampledImageColorSampleCounts = sample_counts,
885 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
886 .sampledImageDepthSampleCounts = sample_counts,
887 .sampledImageStencilSampleCounts = sample_counts,
888 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
889 .maxSampleMaskWords = 1,
890 .timestampComputeAndGraphics = true,
891 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
892 .maxClipDistances = 8,
893 .maxCullDistances = 8,
894 .maxCombinedClipAndCullDistances = 8,
895 .discreteQueuePriorities = 1,
896 .pointSizeRange = { 0.125, 255.875 },
897 .lineWidthRange = { 0.0, 7.9921875 },
898 .pointSizeGranularity = (1.0 / 8.0),
899 .lineWidthGranularity = (1.0 / 128.0),
900 .strictLines = false, /* FINISHME */
901 .standardSampleLocations = true,
902 .optimalBufferCopyOffsetAlignment = 128,
903 .optimalBufferCopyRowPitchAlignment = 128,
904 .nonCoherentAtomSize = 64,
905 };
906
907 *pProperties = (VkPhysicalDeviceProperties) {
908 .apiVersion = radv_physical_device_api_version(pdevice),
909 .driverVersion = vk_get_driver_version(),
910 .vendorID = ATI_VENDOR_ID,
911 .deviceID = pdevice->rad_info.pci_id,
912 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
913 .limits = limits,
914 .sparseProperties = {0},
915 };
916
917 strcpy(pProperties->deviceName, pdevice->name);
918 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
919 }
920
921 void radv_GetPhysicalDeviceProperties2(
922 VkPhysicalDevice physicalDevice,
923 VkPhysicalDeviceProperties2KHR *pProperties)
924 {
925 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
926 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
927
928 vk_foreach_struct(ext, pProperties->pNext) {
929 switch (ext->sType) {
930 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
931 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
932 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
933 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
934 break;
935 }
936 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
937 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
938 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
939 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
940 properties->deviceLUIDValid = false;
941 break;
942 }
943 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHR: {
944 VkPhysicalDeviceMultiviewPropertiesKHR *properties = (VkPhysicalDeviceMultiviewPropertiesKHR*)ext;
945 properties->maxMultiviewViewCount = MAX_VIEWS;
946 properties->maxMultiviewInstanceIndex = INT_MAX;
947 break;
948 }
949 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
950 VkPhysicalDevicePointClippingPropertiesKHR *properties =
951 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
952 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
953 break;
954 }
955 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
956 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
957 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
958 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
959 break;
960 }
961 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
962 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
963 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
964 properties->minImportedHostPointerAlignment = 4096;
965 break;
966 }
967 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
968 VkPhysicalDeviceSubgroupProperties *properties =
969 (VkPhysicalDeviceSubgroupProperties*)ext;
970 properties->subgroupSize = 64;
971 properties->supportedStages = VK_SHADER_STAGE_ALL;
972 properties->supportedOperations =
973 VK_SUBGROUP_FEATURE_BASIC_BIT |
974 VK_SUBGROUP_FEATURE_BALLOT_BIT |
975 VK_SUBGROUP_FEATURE_QUAD_BIT |
976 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
977 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT |
978 VK_SUBGROUP_FEATURE_VOTE_BIT;
979 properties->quadOperationsInAllStages = true;
980 break;
981 }
982 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
983 VkPhysicalDeviceMaintenance3Properties *properties =
984 (VkPhysicalDeviceMaintenance3Properties*)ext;
985 /* Make sure everything is addressable by a signed 32-bit int, and
986 * our largest descriptors are 96 bytes. */
987 properties->maxPerSetDescriptors = (1ull << 31) / 96;
988 /* Our buffer size fields allow only this much */
989 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
990 break;
991 }
992 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
993 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
994 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
995 /* GFX6-8 only support single channel min/max filter. */
996 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
997 properties->filterMinmaxSingleComponentFormats = true;
998 break;
999 }
1000 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1001 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1002 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1003
1004 /* Shader engines. */
1005 properties->shaderEngineCount =
1006 pdevice->rad_info.max_se;
1007 properties->shaderArraysPerEngineCount =
1008 pdevice->rad_info.max_sh_per_se;
1009 properties->computeUnitsPerShaderArray =
1010 pdevice->rad_info.num_good_compute_units /
1011 (pdevice->rad_info.max_se *
1012 pdevice->rad_info.max_sh_per_se);
1013 properties->simdPerComputeUnit = 4;
1014 properties->wavefrontsPerSimd =
1015 pdevice->rad_info.family == CHIP_TONGA ||
1016 pdevice->rad_info.family == CHIP_ICELAND ||
1017 pdevice->rad_info.family == CHIP_POLARIS10 ||
1018 pdevice->rad_info.family == CHIP_POLARIS11 ||
1019 pdevice->rad_info.family == CHIP_POLARIS12 ? 8 : 10;
1020 properties->wavefrontSize = 64;
1021
1022 /* SGPR. */
1023 properties->sgprsPerSimd =
1024 radv_get_num_physical_sgprs(pdevice);
1025 properties->minSgprAllocation =
1026 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1027 properties->maxSgprAllocation =
1028 pdevice->rad_info.family == CHIP_TONGA ||
1029 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1030 properties->sgprAllocationGranularity =
1031 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1032
1033 /* VGPR. */
1034 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1035 properties->minVgprAllocation = 4;
1036 properties->maxVgprAllocation = 256;
1037 properties->vgprAllocationGranularity = 4;
1038 break;
1039 }
1040 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1041 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1042 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1043 properties->maxVertexAttribDivisor = UINT32_MAX;
1044 break;
1045 }
1046 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1047 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1048 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1049 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1050 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1051 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1052 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1053 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1054 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1055 properties->robustBufferAccessUpdateAfterBind = false;
1056 properties->quadDivergentImplicitLod = false;
1057
1058 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1059 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1060 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1061 32 /* sampler, largest when combined with image */ +
1062 64 /* sampled image */ +
1063 64 /* storage image */);
1064 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1065 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1066 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1067 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1068 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1069 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1070 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1071 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1072 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1073 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1074 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1075 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1076 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1077 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1078 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1079 break;
1080 }
1081 default:
1082 break;
1083 }
1084 }
1085 }
1086
1087 static void radv_get_physical_device_queue_family_properties(
1088 struct radv_physical_device* pdevice,
1089 uint32_t* pCount,
1090 VkQueueFamilyProperties** pQueueFamilyProperties)
1091 {
1092 int num_queue_families = 1;
1093 int idx;
1094 if (pdevice->rad_info.num_compute_rings > 0 &&
1095 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1096 num_queue_families++;
1097
1098 if (pQueueFamilyProperties == NULL) {
1099 *pCount = num_queue_families;
1100 return;
1101 }
1102
1103 if (!*pCount)
1104 return;
1105
1106 idx = 0;
1107 if (*pCount >= 1) {
1108 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1109 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1110 VK_QUEUE_COMPUTE_BIT |
1111 VK_QUEUE_TRANSFER_BIT |
1112 VK_QUEUE_SPARSE_BINDING_BIT,
1113 .queueCount = 1,
1114 .timestampValidBits = 64,
1115 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1116 };
1117 idx++;
1118 }
1119
1120 if (pdevice->rad_info.num_compute_rings > 0 &&
1121 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1122 if (*pCount > idx) {
1123 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1124 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1125 VK_QUEUE_TRANSFER_BIT |
1126 VK_QUEUE_SPARSE_BINDING_BIT,
1127 .queueCount = pdevice->rad_info.num_compute_rings,
1128 .timestampValidBits = 64,
1129 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1130 };
1131 idx++;
1132 }
1133 }
1134 *pCount = idx;
1135 }
1136
1137 void radv_GetPhysicalDeviceQueueFamilyProperties(
1138 VkPhysicalDevice physicalDevice,
1139 uint32_t* pCount,
1140 VkQueueFamilyProperties* pQueueFamilyProperties)
1141 {
1142 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1143 if (!pQueueFamilyProperties) {
1144 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1145 return;
1146 }
1147 VkQueueFamilyProperties *properties[] = {
1148 pQueueFamilyProperties + 0,
1149 pQueueFamilyProperties + 1,
1150 pQueueFamilyProperties + 2,
1151 };
1152 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1153 assert(*pCount <= 3);
1154 }
1155
1156 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1157 VkPhysicalDevice physicalDevice,
1158 uint32_t* pCount,
1159 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
1160 {
1161 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1162 if (!pQueueFamilyProperties) {
1163 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1164 return;
1165 }
1166 VkQueueFamilyProperties *properties[] = {
1167 &pQueueFamilyProperties[0].queueFamilyProperties,
1168 &pQueueFamilyProperties[1].queueFamilyProperties,
1169 &pQueueFamilyProperties[2].queueFamilyProperties,
1170 };
1171 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1172 assert(*pCount <= 3);
1173 }
1174
1175 void radv_GetPhysicalDeviceMemoryProperties(
1176 VkPhysicalDevice physicalDevice,
1177 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1178 {
1179 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1180
1181 *pMemoryProperties = physical_device->memory_properties;
1182 }
1183
1184 void radv_GetPhysicalDeviceMemoryProperties2(
1185 VkPhysicalDevice physicalDevice,
1186 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
1187 {
1188 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1189 &pMemoryProperties->memoryProperties);
1190 }
1191
1192 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1193 VkDevice _device,
1194 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
1195 const void *pHostPointer,
1196 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1197 {
1198 RADV_FROM_HANDLE(radv_device, device, _device);
1199
1200 switch (handleType)
1201 {
1202 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1203 const struct radv_physical_device *physical_device = device->physical_device;
1204 uint32_t memoryTypeBits = 0;
1205 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1206 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1207 memoryTypeBits = (1 << i);
1208 break;
1209 }
1210 }
1211 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1212 return VK_SUCCESS;
1213 }
1214 default:
1215 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
1216 }
1217 }
1218
1219 static enum radeon_ctx_priority
1220 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1221 {
1222 /* Default to MEDIUM when a specific global priority isn't requested */
1223 if (!pObj)
1224 return RADEON_CTX_PRIORITY_MEDIUM;
1225
1226 switch(pObj->globalPriority) {
1227 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1228 return RADEON_CTX_PRIORITY_REALTIME;
1229 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1230 return RADEON_CTX_PRIORITY_HIGH;
1231 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1232 return RADEON_CTX_PRIORITY_MEDIUM;
1233 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1234 return RADEON_CTX_PRIORITY_LOW;
1235 default:
1236 unreachable("Illegal global priority value");
1237 return RADEON_CTX_PRIORITY_INVALID;
1238 }
1239 }
1240
1241 static int
1242 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1243 uint32_t queue_family_index, int idx,
1244 VkDeviceQueueCreateFlags flags,
1245 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1246 {
1247 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1248 queue->device = device;
1249 queue->queue_family_index = queue_family_index;
1250 queue->queue_idx = idx;
1251 queue->priority = radv_get_queue_global_priority(global_priority);
1252 queue->flags = flags;
1253
1254 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1255 if (!queue->hw_ctx)
1256 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1257
1258 return VK_SUCCESS;
1259 }
1260
1261 static void
1262 radv_queue_finish(struct radv_queue *queue)
1263 {
1264 if (queue->hw_ctx)
1265 queue->device->ws->ctx_destroy(queue->hw_ctx);
1266
1267 if (queue->initial_full_flush_preamble_cs)
1268 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1269 if (queue->initial_preamble_cs)
1270 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1271 if (queue->continue_preamble_cs)
1272 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1273 if (queue->descriptor_bo)
1274 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1275 if (queue->scratch_bo)
1276 queue->device->ws->buffer_destroy(queue->scratch_bo);
1277 if (queue->esgs_ring_bo)
1278 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1279 if (queue->gsvs_ring_bo)
1280 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1281 if (queue->tess_rings_bo)
1282 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1283 if (queue->compute_scratch_bo)
1284 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1285 }
1286
1287 static void
1288 radv_bo_list_init(struct radv_bo_list *bo_list)
1289 {
1290 pthread_mutex_init(&bo_list->mutex, NULL);
1291 bo_list->list.count = bo_list->capacity = 0;
1292 bo_list->list.bos = NULL;
1293 }
1294
1295 static void
1296 radv_bo_list_finish(struct radv_bo_list *bo_list)
1297 {
1298 free(bo_list->list.bos);
1299 pthread_mutex_destroy(&bo_list->mutex);
1300 }
1301
1302 static VkResult radv_bo_list_add(struct radv_bo_list *bo_list, struct radeon_winsys_bo *bo)
1303 {
1304 pthread_mutex_lock(&bo_list->mutex);
1305 if (bo_list->list.count == bo_list->capacity) {
1306 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1307 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1308
1309 if (!data) {
1310 pthread_mutex_unlock(&bo_list->mutex);
1311 return VK_ERROR_OUT_OF_HOST_MEMORY;
1312 }
1313
1314 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1315 bo_list->capacity = capacity;
1316 }
1317
1318 bo_list->list.bos[bo_list->list.count++] = bo;
1319 pthread_mutex_unlock(&bo_list->mutex);
1320 return VK_SUCCESS;
1321 }
1322
1323 static void radv_bo_list_remove(struct radv_bo_list *bo_list, struct radeon_winsys_bo *bo)
1324 {
1325 pthread_mutex_lock(&bo_list->mutex);
1326 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1327 if (bo_list->list.bos[i] == bo) {
1328 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1329 --bo_list->list.count;
1330 break;
1331 }
1332 }
1333 pthread_mutex_unlock(&bo_list->mutex);
1334 }
1335
1336 static void
1337 radv_device_init_gs_info(struct radv_device *device)
1338 {
1339 switch (device->physical_device->rad_info.family) {
1340 case CHIP_OLAND:
1341 case CHIP_HAINAN:
1342 case CHIP_KAVERI:
1343 case CHIP_KABINI:
1344 case CHIP_MULLINS:
1345 case CHIP_ICELAND:
1346 case CHIP_CARRIZO:
1347 case CHIP_STONEY:
1348 device->gs_table_depth = 16;
1349 return;
1350 case CHIP_TAHITI:
1351 case CHIP_PITCAIRN:
1352 case CHIP_VERDE:
1353 case CHIP_BONAIRE:
1354 case CHIP_HAWAII:
1355 case CHIP_TONGA:
1356 case CHIP_FIJI:
1357 case CHIP_POLARIS10:
1358 case CHIP_POLARIS11:
1359 case CHIP_POLARIS12:
1360 case CHIP_VEGA10:
1361 case CHIP_VEGA12:
1362 case CHIP_RAVEN:
1363 device->gs_table_depth = 32;
1364 return;
1365 default:
1366 unreachable("unknown GPU");
1367 }
1368 }
1369
1370 static int radv_get_device_extension_index(const char *name)
1371 {
1372 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1373 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1374 return i;
1375 }
1376 return -1;
1377 }
1378
1379 VkResult radv_CreateDevice(
1380 VkPhysicalDevice physicalDevice,
1381 const VkDeviceCreateInfo* pCreateInfo,
1382 const VkAllocationCallbacks* pAllocator,
1383 VkDevice* pDevice)
1384 {
1385 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1386 VkResult result;
1387 struct radv_device *device;
1388
1389 bool keep_shader_info = false;
1390
1391 /* Check enabled features */
1392 if (pCreateInfo->pEnabledFeatures) {
1393 VkPhysicalDeviceFeatures supported_features;
1394 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1395 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1396 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1397 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1398 for (uint32_t i = 0; i < num_features; i++) {
1399 if (enabled_feature[i] && !supported_feature[i])
1400 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
1401 }
1402 }
1403
1404 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1405 sizeof(*device), 8,
1406 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1407 if (!device)
1408 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1409
1410 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1411 device->instance = physical_device->instance;
1412 device->physical_device = physical_device;
1413
1414 device->ws = physical_device->ws;
1415 if (pAllocator)
1416 device->alloc = *pAllocator;
1417 else
1418 device->alloc = physical_device->instance->alloc;
1419
1420 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1421 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1422 int index = radv_get_device_extension_index(ext_name);
1423 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1424 vk_free(&device->alloc, device);
1425 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
1426 }
1427
1428 device->enabled_extensions.extensions[index] = true;
1429 }
1430
1431 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1432
1433 mtx_init(&device->shader_slab_mutex, mtx_plain);
1434 list_inithead(&device->shader_slabs);
1435
1436 radv_bo_list_init(&device->bo_list);
1437
1438 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1439 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1440 uint32_t qfi = queue_create->queueFamilyIndex;
1441 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1442 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1443
1444 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1445
1446 device->queues[qfi] = vk_alloc(&device->alloc,
1447 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1448 if (!device->queues[qfi]) {
1449 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1450 goto fail;
1451 }
1452
1453 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1454
1455 device->queue_count[qfi] = queue_create->queueCount;
1456
1457 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1458 result = radv_queue_init(device, &device->queues[qfi][q],
1459 qfi, q, queue_create->flags,
1460 global_priority);
1461 if (result != VK_SUCCESS)
1462 goto fail;
1463 }
1464 }
1465
1466 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1467 (device->instance->perftest_flags & RADV_PERFTEST_BINNING);
1468
1469 /* Disabled and not implemented for now. */
1470 device->dfsm_allowed = device->pbb_allowed && false;
1471
1472 #ifdef ANDROID
1473 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1474 #endif
1475
1476 device->llvm_supports_spill = true;
1477
1478 /* The maximum number of scratch waves. Scratch space isn't divided
1479 * evenly between CUs. The number is only a function of the number of CUs.
1480 * We can decrease the constant to decrease the scratch buffer size.
1481 *
1482 * sctx->scratch_waves must be >= the maximum posible size of
1483 * 1 threadgroup, so that the hw doesn't hang from being unable
1484 * to start any.
1485 *
1486 * The recommended value is 4 per CU at most. Higher numbers don't
1487 * bring much benefit, but they still occupy chip resources (think
1488 * async compute). I've seen ~2% performance difference between 4 and 32.
1489 */
1490 uint32_t max_threads_per_block = 2048;
1491 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1492 max_threads_per_block / 64);
1493
1494 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1495
1496 if (device->physical_device->rad_info.chip_class >= CIK) {
1497 /* If the KMD allows it (there is a KMD hw register for it),
1498 * allow launching waves out-of-order.
1499 */
1500 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1501 }
1502
1503 radv_device_init_gs_info(device);
1504
1505 device->tess_offchip_block_dw_size =
1506 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1507 device->has_distributed_tess =
1508 device->physical_device->rad_info.chip_class >= VI &&
1509 device->physical_device->rad_info.max_se >= 2;
1510
1511 if (getenv("RADV_TRACE_FILE")) {
1512 const char *filename = getenv("RADV_TRACE_FILE");
1513
1514 keep_shader_info = true;
1515
1516 if (!radv_init_trace(device))
1517 goto fail;
1518
1519 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1520 radv_dump_enabled_options(device, stderr);
1521 }
1522
1523 device->keep_shader_info = keep_shader_info;
1524
1525 result = radv_device_init_meta(device);
1526 if (result != VK_SUCCESS)
1527 goto fail;
1528
1529 radv_device_init_msaa(device);
1530
1531 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1532 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1533 switch (family) {
1534 case RADV_QUEUE_GENERAL:
1535 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1536 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1537 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1538 break;
1539 case RADV_QUEUE_COMPUTE:
1540 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1541 radeon_emit(device->empty_cs[family], 0);
1542 break;
1543 }
1544 device->ws->cs_finalize(device->empty_cs[family]);
1545 }
1546
1547 if (device->physical_device->rad_info.chip_class >= CIK)
1548 cik_create_gfx_config(device);
1549
1550 VkPipelineCacheCreateInfo ci;
1551 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1552 ci.pNext = NULL;
1553 ci.flags = 0;
1554 ci.pInitialData = NULL;
1555 ci.initialDataSize = 0;
1556 VkPipelineCache pc;
1557 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1558 &ci, NULL, &pc);
1559 if (result != VK_SUCCESS)
1560 goto fail_meta;
1561
1562 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1563
1564 *pDevice = radv_device_to_handle(device);
1565 return VK_SUCCESS;
1566
1567 fail_meta:
1568 radv_device_finish_meta(device);
1569 fail:
1570 radv_bo_list_finish(&device->bo_list);
1571
1572 if (device->trace_bo)
1573 device->ws->buffer_destroy(device->trace_bo);
1574
1575 if (device->gfx_init)
1576 device->ws->buffer_destroy(device->gfx_init);
1577
1578 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1579 for (unsigned q = 0; q < device->queue_count[i]; q++)
1580 radv_queue_finish(&device->queues[i][q]);
1581 if (device->queue_count[i])
1582 vk_free(&device->alloc, device->queues[i]);
1583 }
1584
1585 vk_free(&device->alloc, device);
1586 return result;
1587 }
1588
1589 void radv_DestroyDevice(
1590 VkDevice _device,
1591 const VkAllocationCallbacks* pAllocator)
1592 {
1593 RADV_FROM_HANDLE(radv_device, device, _device);
1594
1595 if (!device)
1596 return;
1597
1598 if (device->trace_bo)
1599 device->ws->buffer_destroy(device->trace_bo);
1600
1601 if (device->gfx_init)
1602 device->ws->buffer_destroy(device->gfx_init);
1603
1604 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1605 for (unsigned q = 0; q < device->queue_count[i]; q++)
1606 radv_queue_finish(&device->queues[i][q]);
1607 if (device->queue_count[i])
1608 vk_free(&device->alloc, device->queues[i]);
1609 if (device->empty_cs[i])
1610 device->ws->cs_destroy(device->empty_cs[i]);
1611 }
1612 radv_device_finish_meta(device);
1613
1614 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1615 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1616
1617 radv_destroy_shader_slabs(device);
1618
1619 radv_bo_list_finish(&device->bo_list);
1620 vk_free(&device->alloc, device);
1621 }
1622
1623 VkResult radv_EnumerateInstanceLayerProperties(
1624 uint32_t* pPropertyCount,
1625 VkLayerProperties* pProperties)
1626 {
1627 if (pProperties == NULL) {
1628 *pPropertyCount = 0;
1629 return VK_SUCCESS;
1630 }
1631
1632 /* None supported at this time */
1633 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1634 }
1635
1636 VkResult radv_EnumerateDeviceLayerProperties(
1637 VkPhysicalDevice physicalDevice,
1638 uint32_t* pPropertyCount,
1639 VkLayerProperties* pProperties)
1640 {
1641 if (pProperties == NULL) {
1642 *pPropertyCount = 0;
1643 return VK_SUCCESS;
1644 }
1645
1646 /* None supported at this time */
1647 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1648 }
1649
1650 void radv_GetDeviceQueue2(
1651 VkDevice _device,
1652 const VkDeviceQueueInfo2* pQueueInfo,
1653 VkQueue* pQueue)
1654 {
1655 RADV_FROM_HANDLE(radv_device, device, _device);
1656 struct radv_queue *queue;
1657
1658 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
1659 if (pQueueInfo->flags != queue->flags) {
1660 /* From the Vulkan 1.1.70 spec:
1661 *
1662 * "The queue returned by vkGetDeviceQueue2 must have the same
1663 * flags value from this structure as that used at device
1664 * creation time in a VkDeviceQueueCreateInfo instance. If no
1665 * matching flags were specified at device creation time then
1666 * pQueue will return VK_NULL_HANDLE."
1667 */
1668 *pQueue = VK_NULL_HANDLE;
1669 return;
1670 }
1671
1672 *pQueue = radv_queue_to_handle(queue);
1673 }
1674
1675 void radv_GetDeviceQueue(
1676 VkDevice _device,
1677 uint32_t queueFamilyIndex,
1678 uint32_t queueIndex,
1679 VkQueue* pQueue)
1680 {
1681 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
1682 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
1683 .queueFamilyIndex = queueFamilyIndex,
1684 .queueIndex = queueIndex
1685 };
1686
1687 radv_GetDeviceQueue2(_device, &info, pQueue);
1688 }
1689
1690 static void
1691 fill_geom_tess_rings(struct radv_queue *queue,
1692 uint32_t *map,
1693 bool add_sample_positions,
1694 uint32_t esgs_ring_size,
1695 struct radeon_winsys_bo *esgs_ring_bo,
1696 uint32_t gsvs_ring_size,
1697 struct radeon_winsys_bo *gsvs_ring_bo,
1698 uint32_t tess_factor_ring_size,
1699 uint32_t tess_offchip_ring_offset,
1700 uint32_t tess_offchip_ring_size,
1701 struct radeon_winsys_bo *tess_rings_bo)
1702 {
1703 uint64_t esgs_va = 0, gsvs_va = 0;
1704 uint64_t tess_va = 0, tess_offchip_va = 0;
1705 uint32_t *desc = &map[4];
1706
1707 if (esgs_ring_bo)
1708 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1709 if (gsvs_ring_bo)
1710 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1711 if (tess_rings_bo) {
1712 tess_va = radv_buffer_get_va(tess_rings_bo);
1713 tess_offchip_va = tess_va + tess_offchip_ring_offset;
1714 }
1715
1716 /* stride 0, num records - size, add tid, swizzle, elsize4,
1717 index stride 64 */
1718 desc[0] = esgs_va;
1719 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1720 S_008F04_STRIDE(0) |
1721 S_008F04_SWIZZLE_ENABLE(true);
1722 desc[2] = esgs_ring_size;
1723 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1724 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1725 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1726 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1727 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1728 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1729 S_008F0C_ELEMENT_SIZE(1) |
1730 S_008F0C_INDEX_STRIDE(3) |
1731 S_008F0C_ADD_TID_ENABLE(true);
1732
1733 desc += 4;
1734 /* GS entry for ES->GS ring */
1735 /* stride 0, num records - size, elsize0,
1736 index stride 0 */
1737 desc[0] = esgs_va;
1738 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1739 S_008F04_STRIDE(0) |
1740 S_008F04_SWIZZLE_ENABLE(false);
1741 desc[2] = esgs_ring_size;
1742 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1743 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1744 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1745 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1746 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1747 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1748 S_008F0C_ELEMENT_SIZE(0) |
1749 S_008F0C_INDEX_STRIDE(0) |
1750 S_008F0C_ADD_TID_ENABLE(false);
1751
1752 desc += 4;
1753 /* VS entry for GS->VS ring */
1754 /* stride 0, num records - size, elsize0,
1755 index stride 0 */
1756 desc[0] = gsvs_va;
1757 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1758 S_008F04_STRIDE(0) |
1759 S_008F04_SWIZZLE_ENABLE(false);
1760 desc[2] = gsvs_ring_size;
1761 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1762 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1763 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1764 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1765 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1766 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1767 S_008F0C_ELEMENT_SIZE(0) |
1768 S_008F0C_INDEX_STRIDE(0) |
1769 S_008F0C_ADD_TID_ENABLE(false);
1770 desc += 4;
1771
1772 /* stride gsvs_itemsize, num records 64
1773 elsize 4, index stride 16 */
1774 /* shader will patch stride and desc[2] */
1775 desc[0] = gsvs_va;
1776 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1777 S_008F04_STRIDE(0) |
1778 S_008F04_SWIZZLE_ENABLE(true);
1779 desc[2] = 0;
1780 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1781 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1782 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1783 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1784 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1785 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1786 S_008F0C_ELEMENT_SIZE(1) |
1787 S_008F0C_INDEX_STRIDE(1) |
1788 S_008F0C_ADD_TID_ENABLE(true);
1789 desc += 4;
1790
1791 desc[0] = tess_va;
1792 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
1793 S_008F04_STRIDE(0) |
1794 S_008F04_SWIZZLE_ENABLE(false);
1795 desc[2] = tess_factor_ring_size;
1796 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1797 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1798 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1799 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1800 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1801 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1802 S_008F0C_ELEMENT_SIZE(0) |
1803 S_008F0C_INDEX_STRIDE(0) |
1804 S_008F0C_ADD_TID_ENABLE(false);
1805 desc += 4;
1806
1807 desc[0] = tess_offchip_va;
1808 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1809 S_008F04_STRIDE(0) |
1810 S_008F04_SWIZZLE_ENABLE(false);
1811 desc[2] = tess_offchip_ring_size;
1812 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1813 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1814 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1815 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1816 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1817 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1818 S_008F0C_ELEMENT_SIZE(0) |
1819 S_008F0C_INDEX_STRIDE(0) |
1820 S_008F0C_ADD_TID_ENABLE(false);
1821 desc += 4;
1822
1823 /* add sample positions after all rings */
1824 memcpy(desc, queue->device->sample_locations_1x, 8);
1825 desc += 2;
1826 memcpy(desc, queue->device->sample_locations_2x, 16);
1827 desc += 4;
1828 memcpy(desc, queue->device->sample_locations_4x, 32);
1829 desc += 8;
1830 memcpy(desc, queue->device->sample_locations_8x, 64);
1831 desc += 16;
1832 memcpy(desc, queue->device->sample_locations_16x, 128);
1833 }
1834
1835 static unsigned
1836 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1837 {
1838 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1839 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1840 device->physical_device->rad_info.family != CHIP_STONEY;
1841 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1842 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1843 device->physical_device->rad_info.max_se;
1844 unsigned offchip_granularity;
1845 unsigned hs_offchip_param;
1846 switch (device->tess_offchip_block_dw_size) {
1847 default:
1848 assert(0);
1849 /* fall through */
1850 case 8192:
1851 offchip_granularity = V_03093C_X_8K_DWORDS;
1852 break;
1853 case 4096:
1854 offchip_granularity = V_03093C_X_4K_DWORDS;
1855 break;
1856 }
1857
1858 switch (device->physical_device->rad_info.chip_class) {
1859 case SI:
1860 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1861 break;
1862 case CIK:
1863 case VI:
1864 case GFX9:
1865 default:
1866 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1867 break;
1868 }
1869
1870 *max_offchip_buffers_p = max_offchip_buffers;
1871 if (device->physical_device->rad_info.chip_class >= CIK) {
1872 if (device->physical_device->rad_info.chip_class >= VI)
1873 --max_offchip_buffers;
1874 hs_offchip_param =
1875 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1876 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1877 } else {
1878 hs_offchip_param =
1879 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1880 }
1881 return hs_offchip_param;
1882 }
1883
1884 static VkResult
1885 radv_get_preamble_cs(struct radv_queue *queue,
1886 uint32_t scratch_size,
1887 uint32_t compute_scratch_size,
1888 uint32_t esgs_ring_size,
1889 uint32_t gsvs_ring_size,
1890 bool needs_tess_rings,
1891 bool needs_sample_positions,
1892 struct radeon_winsys_cs **initial_full_flush_preamble_cs,
1893 struct radeon_winsys_cs **initial_preamble_cs,
1894 struct radeon_winsys_cs **continue_preamble_cs)
1895 {
1896 struct radeon_winsys_bo *scratch_bo = NULL;
1897 struct radeon_winsys_bo *descriptor_bo = NULL;
1898 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1899 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1900 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1901 struct radeon_winsys_bo *tess_rings_bo = NULL;
1902 struct radeon_winsys_cs *dest_cs[3] = {0};
1903 bool add_tess_rings = false, add_sample_positions = false;
1904 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1905 unsigned max_offchip_buffers;
1906 unsigned hs_offchip_param = 0;
1907 unsigned tess_offchip_ring_offset;
1908 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
1909 if (!queue->has_tess_rings) {
1910 if (needs_tess_rings)
1911 add_tess_rings = true;
1912 }
1913 if (!queue->has_sample_positions) {
1914 if (needs_sample_positions)
1915 add_sample_positions = true;
1916 }
1917 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1918 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1919 &max_offchip_buffers);
1920 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
1921 tess_offchip_ring_size = max_offchip_buffers *
1922 queue->device->tess_offchip_block_dw_size * 4;
1923
1924 if (scratch_size <= queue->scratch_size &&
1925 compute_scratch_size <= queue->compute_scratch_size &&
1926 esgs_ring_size <= queue->esgs_ring_size &&
1927 gsvs_ring_size <= queue->gsvs_ring_size &&
1928 !add_tess_rings && !add_sample_positions &&
1929 queue->initial_preamble_cs) {
1930 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1931 *initial_preamble_cs = queue->initial_preamble_cs;
1932 *continue_preamble_cs = queue->continue_preamble_cs;
1933 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1934 *continue_preamble_cs = NULL;
1935 return VK_SUCCESS;
1936 }
1937
1938 if (scratch_size > queue->scratch_size) {
1939 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1940 scratch_size,
1941 4096,
1942 RADEON_DOMAIN_VRAM,
1943 ring_bo_flags);
1944 if (!scratch_bo)
1945 goto fail;
1946 } else
1947 scratch_bo = queue->scratch_bo;
1948
1949 if (compute_scratch_size > queue->compute_scratch_size) {
1950 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1951 compute_scratch_size,
1952 4096,
1953 RADEON_DOMAIN_VRAM,
1954 ring_bo_flags);
1955 if (!compute_scratch_bo)
1956 goto fail;
1957
1958 } else
1959 compute_scratch_bo = queue->compute_scratch_bo;
1960
1961 if (esgs_ring_size > queue->esgs_ring_size) {
1962 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1963 esgs_ring_size,
1964 4096,
1965 RADEON_DOMAIN_VRAM,
1966 ring_bo_flags);
1967 if (!esgs_ring_bo)
1968 goto fail;
1969 } else {
1970 esgs_ring_bo = queue->esgs_ring_bo;
1971 esgs_ring_size = queue->esgs_ring_size;
1972 }
1973
1974 if (gsvs_ring_size > queue->gsvs_ring_size) {
1975 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1976 gsvs_ring_size,
1977 4096,
1978 RADEON_DOMAIN_VRAM,
1979 ring_bo_flags);
1980 if (!gsvs_ring_bo)
1981 goto fail;
1982 } else {
1983 gsvs_ring_bo = queue->gsvs_ring_bo;
1984 gsvs_ring_size = queue->gsvs_ring_size;
1985 }
1986
1987 if (add_tess_rings) {
1988 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
1989 tess_offchip_ring_offset + tess_offchip_ring_size,
1990 256,
1991 RADEON_DOMAIN_VRAM,
1992 ring_bo_flags);
1993 if (!tess_rings_bo)
1994 goto fail;
1995 } else {
1996 tess_rings_bo = queue->tess_rings_bo;
1997 }
1998
1999 if (scratch_bo != queue->scratch_bo ||
2000 esgs_ring_bo != queue->esgs_ring_bo ||
2001 gsvs_ring_bo != queue->gsvs_ring_bo ||
2002 tess_rings_bo != queue->tess_rings_bo ||
2003 add_sample_positions) {
2004 uint32_t size = 0;
2005 if (gsvs_ring_bo || esgs_ring_bo ||
2006 tess_rings_bo || add_sample_positions) {
2007 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2008 if (add_sample_positions)
2009 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
2010 }
2011 else if (scratch_bo)
2012 size = 8; /* 2 dword */
2013
2014 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2015 size,
2016 4096,
2017 RADEON_DOMAIN_VRAM,
2018 RADEON_FLAG_CPU_ACCESS |
2019 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2020 RADEON_FLAG_READ_ONLY);
2021 if (!descriptor_bo)
2022 goto fail;
2023 } else
2024 descriptor_bo = queue->descriptor_bo;
2025
2026 for(int i = 0; i < 3; ++i) {
2027 struct radeon_winsys_cs *cs = NULL;
2028 cs = queue->device->ws->cs_create(queue->device->ws,
2029 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2030 if (!cs)
2031 goto fail;
2032
2033 dest_cs[i] = cs;
2034
2035 if (scratch_bo)
2036 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo, 8);
2037
2038 if (esgs_ring_bo)
2039 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo, 8);
2040
2041 if (gsvs_ring_bo)
2042 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo, 8);
2043
2044 if (tess_rings_bo)
2045 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo, 8);
2046
2047 if (descriptor_bo)
2048 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo, 8);
2049
2050 if (descriptor_bo != queue->descriptor_bo) {
2051 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2052
2053 if (scratch_bo) {
2054 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2055 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2056 S_008F04_SWIZZLE_ENABLE(1);
2057 map[0] = scratch_va;
2058 map[1] = rsrc1;
2059 }
2060
2061 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo ||
2062 add_sample_positions)
2063 fill_geom_tess_rings(queue, map, add_sample_positions,
2064 esgs_ring_size, esgs_ring_bo,
2065 gsvs_ring_size, gsvs_ring_bo,
2066 tess_factor_ring_size,
2067 tess_offchip_ring_offset,
2068 tess_offchip_ring_size,
2069 tess_rings_bo);
2070
2071 queue->device->ws->buffer_unmap(descriptor_bo);
2072 }
2073
2074 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2075 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2076 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2077 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2078 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2079 }
2080
2081 if (esgs_ring_bo || gsvs_ring_bo) {
2082 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2083 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2084 radeon_emit(cs, esgs_ring_size >> 8);
2085 radeon_emit(cs, gsvs_ring_size >> 8);
2086 } else {
2087 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2088 radeon_emit(cs, esgs_ring_size >> 8);
2089 radeon_emit(cs, gsvs_ring_size >> 8);
2090 }
2091 }
2092
2093 if (tess_rings_bo) {
2094 uint64_t tf_va = radv_buffer_get_va(tess_rings_bo);
2095 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2096 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2097 S_030938_SIZE(tess_factor_ring_size / 4));
2098 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2099 tf_va >> 8);
2100 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2101 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2102 S_030944_BASE_HI(tf_va >> 40));
2103 }
2104 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
2105 } else {
2106 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2107 S_008988_SIZE(tess_factor_ring_size / 4));
2108 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2109 tf_va >> 8);
2110 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2111 hs_offchip_param);
2112 }
2113 }
2114
2115 if (descriptor_bo) {
2116 uint64_t va = radv_buffer_get_va(descriptor_bo);
2117 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2118 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2119 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2120 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2121 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2122
2123 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2124 radeon_set_sh_reg_seq(cs, regs[i], 2);
2125 radeon_emit(cs, va);
2126 radeon_emit(cs, va >> 32);
2127 }
2128 } else {
2129 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2130 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2131 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2132 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2133 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2134 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2135
2136 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2137 radeon_set_sh_reg_seq(cs, regs[i], 2);
2138 radeon_emit(cs, va);
2139 radeon_emit(cs, va >> 32);
2140 }
2141 }
2142 }
2143
2144 if (compute_scratch_bo) {
2145 uint64_t scratch_va = radv_buffer_get_va(compute_scratch_bo);
2146 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2147 S_008F04_SWIZZLE_ENABLE(1);
2148
2149 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo, 8);
2150
2151 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2152 radeon_emit(cs, scratch_va);
2153 radeon_emit(cs, rsrc1);
2154 }
2155
2156 if (i == 0) {
2157 si_cs_emit_cache_flush(cs,
2158 queue->device->physical_device->rad_info.chip_class,
2159 NULL, 0,
2160 queue->queue_family_index == RING_COMPUTE &&
2161 queue->device->physical_device->rad_info.chip_class >= CIK,
2162 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2163 RADV_CMD_FLAG_INV_ICACHE |
2164 RADV_CMD_FLAG_INV_SMEM_L1 |
2165 RADV_CMD_FLAG_INV_VMEM_L1 |
2166 RADV_CMD_FLAG_INV_GLOBAL_L2);
2167 } else if (i == 1) {
2168 si_cs_emit_cache_flush(cs,
2169 queue->device->physical_device->rad_info.chip_class,
2170 NULL, 0,
2171 queue->queue_family_index == RING_COMPUTE &&
2172 queue->device->physical_device->rad_info.chip_class >= CIK,
2173 RADV_CMD_FLAG_INV_ICACHE |
2174 RADV_CMD_FLAG_INV_SMEM_L1 |
2175 RADV_CMD_FLAG_INV_VMEM_L1 |
2176 RADV_CMD_FLAG_INV_GLOBAL_L2);
2177 }
2178
2179 if (!queue->device->ws->cs_finalize(cs))
2180 goto fail;
2181 }
2182
2183 if (queue->initial_full_flush_preamble_cs)
2184 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2185
2186 if (queue->initial_preamble_cs)
2187 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2188
2189 if (queue->continue_preamble_cs)
2190 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2191
2192 queue->initial_full_flush_preamble_cs = dest_cs[0];
2193 queue->initial_preamble_cs = dest_cs[1];
2194 queue->continue_preamble_cs = dest_cs[2];
2195
2196 if (scratch_bo != queue->scratch_bo) {
2197 if (queue->scratch_bo)
2198 queue->device->ws->buffer_destroy(queue->scratch_bo);
2199 queue->scratch_bo = scratch_bo;
2200 queue->scratch_size = scratch_size;
2201 }
2202
2203 if (compute_scratch_bo != queue->compute_scratch_bo) {
2204 if (queue->compute_scratch_bo)
2205 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2206 queue->compute_scratch_bo = compute_scratch_bo;
2207 queue->compute_scratch_size = compute_scratch_size;
2208 }
2209
2210 if (esgs_ring_bo != queue->esgs_ring_bo) {
2211 if (queue->esgs_ring_bo)
2212 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2213 queue->esgs_ring_bo = esgs_ring_bo;
2214 queue->esgs_ring_size = esgs_ring_size;
2215 }
2216
2217 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2218 if (queue->gsvs_ring_bo)
2219 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2220 queue->gsvs_ring_bo = gsvs_ring_bo;
2221 queue->gsvs_ring_size = gsvs_ring_size;
2222 }
2223
2224 if (tess_rings_bo != queue->tess_rings_bo) {
2225 queue->tess_rings_bo = tess_rings_bo;
2226 queue->has_tess_rings = true;
2227 }
2228
2229 if (descriptor_bo != queue->descriptor_bo) {
2230 if (queue->descriptor_bo)
2231 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2232
2233 queue->descriptor_bo = descriptor_bo;
2234 }
2235
2236 if (add_sample_positions)
2237 queue->has_sample_positions = true;
2238
2239 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2240 *initial_preamble_cs = queue->initial_preamble_cs;
2241 *continue_preamble_cs = queue->continue_preamble_cs;
2242 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2243 *continue_preamble_cs = NULL;
2244 return VK_SUCCESS;
2245 fail:
2246 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2247 if (dest_cs[i])
2248 queue->device->ws->cs_destroy(dest_cs[i]);
2249 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2250 queue->device->ws->buffer_destroy(descriptor_bo);
2251 if (scratch_bo && scratch_bo != queue->scratch_bo)
2252 queue->device->ws->buffer_destroy(scratch_bo);
2253 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2254 queue->device->ws->buffer_destroy(compute_scratch_bo);
2255 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2256 queue->device->ws->buffer_destroy(esgs_ring_bo);
2257 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2258 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2259 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2260 queue->device->ws->buffer_destroy(tess_rings_bo);
2261 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2262 }
2263
2264 static VkResult radv_alloc_sem_counts(struct radv_winsys_sem_counts *counts,
2265 int num_sems,
2266 const VkSemaphore *sems,
2267 VkFence _fence,
2268 bool reset_temp)
2269 {
2270 int syncobj_idx = 0, sem_idx = 0;
2271
2272 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2273 return VK_SUCCESS;
2274
2275 for (uint32_t i = 0; i < num_sems; i++) {
2276 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2277
2278 if (sem->temp_syncobj || sem->syncobj)
2279 counts->syncobj_count++;
2280 else
2281 counts->sem_count++;
2282 }
2283
2284 if (_fence != VK_NULL_HANDLE) {
2285 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2286 if (fence->temp_syncobj || fence->syncobj)
2287 counts->syncobj_count++;
2288 }
2289
2290 if (counts->syncobj_count) {
2291 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2292 if (!counts->syncobj)
2293 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2294 }
2295
2296 if (counts->sem_count) {
2297 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2298 if (!counts->sem) {
2299 free(counts->syncobj);
2300 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2301 }
2302 }
2303
2304 for (uint32_t i = 0; i < num_sems; i++) {
2305 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2306
2307 if (sem->temp_syncobj) {
2308 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2309 }
2310 else if (sem->syncobj)
2311 counts->syncobj[syncobj_idx++] = sem->syncobj;
2312 else {
2313 assert(sem->sem);
2314 counts->sem[sem_idx++] = sem->sem;
2315 }
2316 }
2317
2318 if (_fence != VK_NULL_HANDLE) {
2319 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2320 if (fence->temp_syncobj)
2321 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2322 else if (fence->syncobj)
2323 counts->syncobj[syncobj_idx++] = fence->syncobj;
2324 }
2325
2326 return VK_SUCCESS;
2327 }
2328
2329 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2330 {
2331 free(sem_info->wait.syncobj);
2332 free(sem_info->wait.sem);
2333 free(sem_info->signal.syncobj);
2334 free(sem_info->signal.sem);
2335 }
2336
2337
2338 static void radv_free_temp_syncobjs(struct radv_device *device,
2339 int num_sems,
2340 const VkSemaphore *sems)
2341 {
2342 for (uint32_t i = 0; i < num_sems; i++) {
2343 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2344
2345 if (sem->temp_syncobj) {
2346 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2347 sem->temp_syncobj = 0;
2348 }
2349 }
2350 }
2351
2352 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
2353 int num_wait_sems,
2354 const VkSemaphore *wait_sems,
2355 int num_signal_sems,
2356 const VkSemaphore *signal_sems,
2357 VkFence fence)
2358 {
2359 VkResult ret;
2360 memset(sem_info, 0, sizeof(*sem_info));
2361
2362 ret = radv_alloc_sem_counts(&sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2363 if (ret)
2364 return ret;
2365 ret = radv_alloc_sem_counts(&sem_info->signal, num_signal_sems, signal_sems, fence, false);
2366 if (ret)
2367 radv_free_sem_info(sem_info);
2368
2369 /* caller can override these */
2370 sem_info->cs_emit_wait = true;
2371 sem_info->cs_emit_signal = true;
2372 return ret;
2373 }
2374
2375 /* Signals fence as soon as all the work currently put on queue is done. */
2376 static VkResult radv_signal_fence(struct radv_queue *queue,
2377 struct radv_fence *fence)
2378 {
2379 int ret;
2380 VkResult result;
2381 struct radv_winsys_sem_info sem_info;
2382
2383 result = radv_alloc_sem_info(&sem_info, 0, NULL, 0, NULL,
2384 radv_fence_to_handle(fence));
2385 if (result != VK_SUCCESS)
2386 return result;
2387
2388 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2389 &queue->device->empty_cs[queue->queue_family_index],
2390 1, NULL, NULL, &sem_info, NULL,
2391 false, fence->fence);
2392 radv_free_sem_info(&sem_info);
2393
2394 /* TODO: find a better error */
2395 if (ret)
2396 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2397
2398 return VK_SUCCESS;
2399 }
2400
2401 VkResult radv_QueueSubmit(
2402 VkQueue _queue,
2403 uint32_t submitCount,
2404 const VkSubmitInfo* pSubmits,
2405 VkFence _fence)
2406 {
2407 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2408 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2409 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2410 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2411 int ret;
2412 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2413 uint32_t scratch_size = 0;
2414 uint32_t compute_scratch_size = 0;
2415 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2416 struct radeon_winsys_cs *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2417 VkResult result;
2418 bool fence_emitted = false;
2419 bool tess_rings_needed = false;
2420 bool sample_positions_needed = false;
2421
2422 /* Do this first so failing to allocate scratch buffers can't result in
2423 * partially executed submissions. */
2424 for (uint32_t i = 0; i < submitCount; i++) {
2425 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2426 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2427 pSubmits[i].pCommandBuffers[j]);
2428
2429 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2430 compute_scratch_size = MAX2(compute_scratch_size,
2431 cmd_buffer->compute_scratch_size_needed);
2432 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2433 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2434 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2435 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2436 }
2437 }
2438
2439 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2440 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2441 sample_positions_needed, &initial_flush_preamble_cs,
2442 &initial_preamble_cs, &continue_preamble_cs);
2443 if (result != VK_SUCCESS)
2444 return result;
2445
2446 for (uint32_t i = 0; i < submitCount; i++) {
2447 struct radeon_winsys_cs **cs_array;
2448 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2449 bool can_patch = true;
2450 uint32_t advance;
2451 struct radv_winsys_sem_info sem_info;
2452
2453 result = radv_alloc_sem_info(&sem_info,
2454 pSubmits[i].waitSemaphoreCount,
2455 pSubmits[i].pWaitSemaphores,
2456 pSubmits[i].signalSemaphoreCount,
2457 pSubmits[i].pSignalSemaphores,
2458 _fence);
2459 if (result != VK_SUCCESS)
2460 return result;
2461
2462 if (!pSubmits[i].commandBufferCount) {
2463 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2464 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2465 &queue->device->empty_cs[queue->queue_family_index],
2466 1, NULL, NULL,
2467 &sem_info, NULL,
2468 false, base_fence);
2469 if (ret) {
2470 radv_loge("failed to submit CS %d\n", i);
2471 abort();
2472 }
2473 fence_emitted = true;
2474 }
2475 radv_free_sem_info(&sem_info);
2476 continue;
2477 }
2478
2479 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
2480 (pSubmits[i].commandBufferCount));
2481
2482 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2483 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2484 pSubmits[i].pCommandBuffers[j]);
2485 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2486
2487 cs_array[j] = cmd_buffer->cs;
2488 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2489 can_patch = false;
2490
2491 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2492 }
2493
2494 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2495 struct radeon_winsys_cs *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2496 advance = MIN2(max_cs_submission,
2497 pSubmits[i].commandBufferCount - j);
2498
2499 if (queue->device->trace_bo)
2500 *queue->device->trace_id_ptr = 0;
2501
2502 sem_info.cs_emit_wait = j == 0;
2503 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2504
2505 pthread_mutex_lock(&queue->device->bo_list.mutex);
2506
2507 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2508 advance, initial_preamble, continue_preamble_cs,
2509 &sem_info, &queue->device->bo_list.list,
2510 can_patch, base_fence);
2511
2512 pthread_mutex_unlock(&queue->device->bo_list.mutex);
2513
2514 if (ret) {
2515 radv_loge("failed to submit CS %d\n", i);
2516 abort();
2517 }
2518 fence_emitted = true;
2519 if (queue->device->trace_bo) {
2520 radv_check_gpu_hangs(queue, cs_array[j]);
2521 }
2522 }
2523
2524 radv_free_temp_syncobjs(queue->device,
2525 pSubmits[i].waitSemaphoreCount,
2526 pSubmits[i].pWaitSemaphores);
2527 radv_free_sem_info(&sem_info);
2528 free(cs_array);
2529 }
2530
2531 if (fence) {
2532 if (!fence_emitted) {
2533 radv_signal_fence(queue, fence);
2534 }
2535 fence->submitted = true;
2536 }
2537
2538 return VK_SUCCESS;
2539 }
2540
2541 VkResult radv_QueueWaitIdle(
2542 VkQueue _queue)
2543 {
2544 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2545
2546 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2547 radv_queue_family_to_ring(queue->queue_family_index),
2548 queue->queue_idx);
2549 return VK_SUCCESS;
2550 }
2551
2552 VkResult radv_DeviceWaitIdle(
2553 VkDevice _device)
2554 {
2555 RADV_FROM_HANDLE(radv_device, device, _device);
2556
2557 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2558 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2559 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2560 }
2561 }
2562 return VK_SUCCESS;
2563 }
2564
2565 VkResult radv_EnumerateInstanceExtensionProperties(
2566 const char* pLayerName,
2567 uint32_t* pPropertyCount,
2568 VkExtensionProperties* pProperties)
2569 {
2570 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2571
2572 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
2573 if (radv_supported_instance_extensions.extensions[i]) {
2574 vk_outarray_append(&out, prop) {
2575 *prop = radv_instance_extensions[i];
2576 }
2577 }
2578 }
2579
2580 return vk_outarray_status(&out);
2581 }
2582
2583 VkResult radv_EnumerateDeviceExtensionProperties(
2584 VkPhysicalDevice physicalDevice,
2585 const char* pLayerName,
2586 uint32_t* pPropertyCount,
2587 VkExtensionProperties* pProperties)
2588 {
2589 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2590 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2591
2592 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
2593 if (device->supported_extensions.extensions[i]) {
2594 vk_outarray_append(&out, prop) {
2595 *prop = radv_device_extensions[i];
2596 }
2597 }
2598 }
2599
2600 return vk_outarray_status(&out);
2601 }
2602
2603 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2604 VkInstance _instance,
2605 const char* pName)
2606 {
2607 RADV_FROM_HANDLE(radv_instance, instance, _instance);
2608
2609 return radv_lookup_entrypoint_checked(pName,
2610 instance ? instance->apiVersion : 0,
2611 instance ? &instance->enabled_extensions : NULL,
2612 NULL);
2613 }
2614
2615 /* The loader wants us to expose a second GetInstanceProcAddr function
2616 * to work around certain LD_PRELOAD issues seen in apps.
2617 */
2618 PUBLIC
2619 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2620 VkInstance instance,
2621 const char* pName);
2622
2623 PUBLIC
2624 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2625 VkInstance instance,
2626 const char* pName)
2627 {
2628 return radv_GetInstanceProcAddr(instance, pName);
2629 }
2630
2631 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2632 VkDevice _device,
2633 const char* pName)
2634 {
2635 RADV_FROM_HANDLE(radv_device, device, _device);
2636
2637 return radv_lookup_entrypoint_checked(pName,
2638 device->instance->apiVersion,
2639 &device->instance->enabled_extensions,
2640 &device->enabled_extensions);
2641 }
2642
2643 bool radv_get_memory_fd(struct radv_device *device,
2644 struct radv_device_memory *memory,
2645 int *pFD)
2646 {
2647 struct radeon_bo_metadata metadata;
2648
2649 if (memory->image) {
2650 radv_init_metadata(device, memory->image, &metadata);
2651 device->ws->buffer_set_metadata(memory->bo, &metadata);
2652 }
2653
2654 return device->ws->buffer_get_fd(device->ws, memory->bo,
2655 pFD);
2656 }
2657
2658 static VkResult radv_alloc_memory(struct radv_device *device,
2659 const VkMemoryAllocateInfo* pAllocateInfo,
2660 const VkAllocationCallbacks* pAllocator,
2661 VkDeviceMemory* pMem)
2662 {
2663 struct radv_device_memory *mem;
2664 VkResult result;
2665 enum radeon_bo_domain domain;
2666 uint32_t flags = 0;
2667 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
2668
2669 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2670
2671 if (pAllocateInfo->allocationSize == 0) {
2672 /* Apparently, this is allowed */
2673 *pMem = VK_NULL_HANDLE;
2674 return VK_SUCCESS;
2675 }
2676
2677 const VkImportMemoryFdInfoKHR *import_info =
2678 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2679 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2680 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2681 const VkExportMemoryAllocateInfoKHR *export_info =
2682 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO_KHR);
2683 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
2684 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
2685
2686 const struct wsi_memory_allocate_info *wsi_info =
2687 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
2688
2689 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2690 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2691 if (mem == NULL)
2692 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2693
2694 if (wsi_info && wsi_info->implicit_sync)
2695 flags |= RADEON_FLAG_IMPLICIT_SYNC;
2696
2697 if (dedicate_info) {
2698 mem->image = radv_image_from_handle(dedicate_info->image);
2699 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2700 } else {
2701 mem->image = NULL;
2702 mem->buffer = NULL;
2703 }
2704
2705 mem->user_ptr = NULL;
2706
2707 if (import_info) {
2708 assert(import_info->handleType ==
2709 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
2710 import_info->handleType ==
2711 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
2712 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2713 NULL, NULL);
2714 if (!mem->bo) {
2715 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2716 goto fail;
2717 } else {
2718 close(import_info->fd);
2719 }
2720 } else if (host_ptr_info) {
2721 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
2722 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
2723 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
2724 pAllocateInfo->allocationSize);
2725 if (!mem->bo) {
2726 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2727 goto fail;
2728 } else {
2729 mem->user_ptr = host_ptr_info->pHostPointer;
2730 }
2731 } else {
2732 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2733 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2734 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
2735 domain = RADEON_DOMAIN_GTT;
2736 else
2737 domain = RADEON_DOMAIN_VRAM;
2738
2739 if (mem_type_index == RADV_MEM_TYPE_VRAM)
2740 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2741 else
2742 flags |= RADEON_FLAG_CPU_ACCESS;
2743
2744 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2745 flags |= RADEON_FLAG_GTT_WC;
2746
2747 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
2748 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
2749
2750 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2751 domain, flags);
2752
2753 if (!mem->bo) {
2754 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2755 goto fail;
2756 }
2757 mem->type_index = mem_type_index;
2758 }
2759
2760 result = radv_bo_list_add(&device->bo_list, mem->bo);
2761 if (result != VK_SUCCESS)
2762 goto fail_bo;
2763
2764 *pMem = radv_device_memory_to_handle(mem);
2765
2766 return VK_SUCCESS;
2767
2768 fail_bo:
2769 device->ws->buffer_destroy(mem->bo);
2770 fail:
2771 vk_free2(&device->alloc, pAllocator, mem);
2772
2773 return result;
2774 }
2775
2776 VkResult radv_AllocateMemory(
2777 VkDevice _device,
2778 const VkMemoryAllocateInfo* pAllocateInfo,
2779 const VkAllocationCallbacks* pAllocator,
2780 VkDeviceMemory* pMem)
2781 {
2782 RADV_FROM_HANDLE(radv_device, device, _device);
2783 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
2784 }
2785
2786 void radv_FreeMemory(
2787 VkDevice _device,
2788 VkDeviceMemory _mem,
2789 const VkAllocationCallbacks* pAllocator)
2790 {
2791 RADV_FROM_HANDLE(radv_device, device, _device);
2792 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2793
2794 if (mem == NULL)
2795 return;
2796
2797 radv_bo_list_remove(&device->bo_list, mem->bo);
2798 device->ws->buffer_destroy(mem->bo);
2799 mem->bo = NULL;
2800
2801 vk_free2(&device->alloc, pAllocator, mem);
2802 }
2803
2804 VkResult radv_MapMemory(
2805 VkDevice _device,
2806 VkDeviceMemory _memory,
2807 VkDeviceSize offset,
2808 VkDeviceSize size,
2809 VkMemoryMapFlags flags,
2810 void** ppData)
2811 {
2812 RADV_FROM_HANDLE(radv_device, device, _device);
2813 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2814
2815 if (mem == NULL) {
2816 *ppData = NULL;
2817 return VK_SUCCESS;
2818 }
2819
2820 if (mem->user_ptr)
2821 *ppData = mem->user_ptr;
2822 else
2823 *ppData = device->ws->buffer_map(mem->bo);
2824
2825 if (*ppData) {
2826 *ppData += offset;
2827 return VK_SUCCESS;
2828 }
2829
2830 return vk_error(VK_ERROR_MEMORY_MAP_FAILED);
2831 }
2832
2833 void radv_UnmapMemory(
2834 VkDevice _device,
2835 VkDeviceMemory _memory)
2836 {
2837 RADV_FROM_HANDLE(radv_device, device, _device);
2838 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2839
2840 if (mem == NULL)
2841 return;
2842
2843 if (mem->user_ptr == NULL)
2844 device->ws->buffer_unmap(mem->bo);
2845 }
2846
2847 VkResult radv_FlushMappedMemoryRanges(
2848 VkDevice _device,
2849 uint32_t memoryRangeCount,
2850 const VkMappedMemoryRange* pMemoryRanges)
2851 {
2852 return VK_SUCCESS;
2853 }
2854
2855 VkResult radv_InvalidateMappedMemoryRanges(
2856 VkDevice _device,
2857 uint32_t memoryRangeCount,
2858 const VkMappedMemoryRange* pMemoryRanges)
2859 {
2860 return VK_SUCCESS;
2861 }
2862
2863 void radv_GetBufferMemoryRequirements(
2864 VkDevice _device,
2865 VkBuffer _buffer,
2866 VkMemoryRequirements* pMemoryRequirements)
2867 {
2868 RADV_FROM_HANDLE(radv_device, device, _device);
2869 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2870
2871 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2872
2873 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2874 pMemoryRequirements->alignment = 4096;
2875 else
2876 pMemoryRequirements->alignment = 16;
2877
2878 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2879 }
2880
2881 void radv_GetBufferMemoryRequirements2(
2882 VkDevice device,
2883 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2884 VkMemoryRequirements2KHR* pMemoryRequirements)
2885 {
2886 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2887 &pMemoryRequirements->memoryRequirements);
2888 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
2889 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2890 switch (ext->sType) {
2891 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2892 VkMemoryDedicatedRequirementsKHR *req =
2893 (VkMemoryDedicatedRequirementsKHR *) ext;
2894 req->requiresDedicatedAllocation = buffer->shareable;
2895 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2896 break;
2897 }
2898 default:
2899 break;
2900 }
2901 }
2902 }
2903
2904 void radv_GetImageMemoryRequirements(
2905 VkDevice _device,
2906 VkImage _image,
2907 VkMemoryRequirements* pMemoryRequirements)
2908 {
2909 RADV_FROM_HANDLE(radv_device, device, _device);
2910 RADV_FROM_HANDLE(radv_image, image, _image);
2911
2912 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2913
2914 pMemoryRequirements->size = image->size;
2915 pMemoryRequirements->alignment = image->alignment;
2916 }
2917
2918 void radv_GetImageMemoryRequirements2(
2919 VkDevice device,
2920 const VkImageMemoryRequirementsInfo2KHR* pInfo,
2921 VkMemoryRequirements2KHR* pMemoryRequirements)
2922 {
2923 radv_GetImageMemoryRequirements(device, pInfo->image,
2924 &pMemoryRequirements->memoryRequirements);
2925
2926 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
2927
2928 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2929 switch (ext->sType) {
2930 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2931 VkMemoryDedicatedRequirementsKHR *req =
2932 (VkMemoryDedicatedRequirementsKHR *) ext;
2933 req->requiresDedicatedAllocation = image->shareable;
2934 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2935 break;
2936 }
2937 default:
2938 break;
2939 }
2940 }
2941 }
2942
2943 void radv_GetImageSparseMemoryRequirements(
2944 VkDevice device,
2945 VkImage image,
2946 uint32_t* pSparseMemoryRequirementCount,
2947 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2948 {
2949 stub();
2950 }
2951
2952 void radv_GetImageSparseMemoryRequirements2(
2953 VkDevice device,
2954 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
2955 uint32_t* pSparseMemoryRequirementCount,
2956 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
2957 {
2958 stub();
2959 }
2960
2961 void radv_GetDeviceMemoryCommitment(
2962 VkDevice device,
2963 VkDeviceMemory memory,
2964 VkDeviceSize* pCommittedMemoryInBytes)
2965 {
2966 *pCommittedMemoryInBytes = 0;
2967 }
2968
2969 VkResult radv_BindBufferMemory2(VkDevice device,
2970 uint32_t bindInfoCount,
2971 const VkBindBufferMemoryInfoKHR *pBindInfos)
2972 {
2973 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2974 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2975 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
2976
2977 if (mem) {
2978 buffer->bo = mem->bo;
2979 buffer->offset = pBindInfos[i].memoryOffset;
2980 } else {
2981 buffer->bo = NULL;
2982 }
2983 }
2984 return VK_SUCCESS;
2985 }
2986
2987 VkResult radv_BindBufferMemory(
2988 VkDevice device,
2989 VkBuffer buffer,
2990 VkDeviceMemory memory,
2991 VkDeviceSize memoryOffset)
2992 {
2993 const VkBindBufferMemoryInfoKHR info = {
2994 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2995 .buffer = buffer,
2996 .memory = memory,
2997 .memoryOffset = memoryOffset
2998 };
2999
3000 return radv_BindBufferMemory2(device, 1, &info);
3001 }
3002
3003 VkResult radv_BindImageMemory2(VkDevice device,
3004 uint32_t bindInfoCount,
3005 const VkBindImageMemoryInfoKHR *pBindInfos)
3006 {
3007 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3008 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3009 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3010
3011 if (mem) {
3012 image->bo = mem->bo;
3013 image->offset = pBindInfos[i].memoryOffset;
3014 } else {
3015 image->bo = NULL;
3016 image->offset = 0;
3017 }
3018 }
3019 return VK_SUCCESS;
3020 }
3021
3022
3023 VkResult radv_BindImageMemory(
3024 VkDevice device,
3025 VkImage image,
3026 VkDeviceMemory memory,
3027 VkDeviceSize memoryOffset)
3028 {
3029 const VkBindImageMemoryInfoKHR info = {
3030 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3031 .image = image,
3032 .memory = memory,
3033 .memoryOffset = memoryOffset
3034 };
3035
3036 return radv_BindImageMemory2(device, 1, &info);
3037 }
3038
3039
3040 static void
3041 radv_sparse_buffer_bind_memory(struct radv_device *device,
3042 const VkSparseBufferMemoryBindInfo *bind)
3043 {
3044 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3045
3046 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3047 struct radv_device_memory *mem = NULL;
3048
3049 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3050 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3051
3052 device->ws->buffer_virtual_bind(buffer->bo,
3053 bind->pBinds[i].resourceOffset,
3054 bind->pBinds[i].size,
3055 mem ? mem->bo : NULL,
3056 bind->pBinds[i].memoryOffset);
3057 }
3058 }
3059
3060 static void
3061 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3062 const VkSparseImageOpaqueMemoryBindInfo *bind)
3063 {
3064 RADV_FROM_HANDLE(radv_image, image, bind->image);
3065
3066 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3067 struct radv_device_memory *mem = NULL;
3068
3069 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3070 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3071
3072 device->ws->buffer_virtual_bind(image->bo,
3073 bind->pBinds[i].resourceOffset,
3074 bind->pBinds[i].size,
3075 mem ? mem->bo : NULL,
3076 bind->pBinds[i].memoryOffset);
3077 }
3078 }
3079
3080 VkResult radv_QueueBindSparse(
3081 VkQueue _queue,
3082 uint32_t bindInfoCount,
3083 const VkBindSparseInfo* pBindInfo,
3084 VkFence _fence)
3085 {
3086 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3087 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3088 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3089 bool fence_emitted = false;
3090
3091 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3092 struct radv_winsys_sem_info sem_info;
3093 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3094 radv_sparse_buffer_bind_memory(queue->device,
3095 pBindInfo[i].pBufferBinds + j);
3096 }
3097
3098 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3099 radv_sparse_image_opaque_bind_memory(queue->device,
3100 pBindInfo[i].pImageOpaqueBinds + j);
3101 }
3102
3103 VkResult result;
3104 result = radv_alloc_sem_info(&sem_info,
3105 pBindInfo[i].waitSemaphoreCount,
3106 pBindInfo[i].pWaitSemaphores,
3107 pBindInfo[i].signalSemaphoreCount,
3108 pBindInfo[i].pSignalSemaphores,
3109 _fence);
3110 if (result != VK_SUCCESS)
3111 return result;
3112
3113 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3114 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3115 &queue->device->empty_cs[queue->queue_family_index],
3116 1, NULL, NULL,
3117 &sem_info, NULL,
3118 false, base_fence);
3119 fence_emitted = true;
3120 if (fence)
3121 fence->submitted = true;
3122 }
3123
3124 radv_free_sem_info(&sem_info);
3125
3126 }
3127
3128 if (fence) {
3129 if (!fence_emitted) {
3130 radv_signal_fence(queue, fence);
3131 }
3132 fence->submitted = true;
3133 }
3134
3135 return VK_SUCCESS;
3136 }
3137
3138 VkResult radv_CreateFence(
3139 VkDevice _device,
3140 const VkFenceCreateInfo* pCreateInfo,
3141 const VkAllocationCallbacks* pAllocator,
3142 VkFence* pFence)
3143 {
3144 RADV_FROM_HANDLE(radv_device, device, _device);
3145 const VkExportFenceCreateInfoKHR *export =
3146 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO_KHR);
3147 VkExternalFenceHandleTypeFlagsKHR handleTypes =
3148 export ? export->handleTypes : 0;
3149
3150 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3151 sizeof(*fence), 8,
3152 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3153
3154 if (!fence)
3155 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3156
3157 fence->submitted = false;
3158 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3159 fence->temp_syncobj = 0;
3160 if (device->always_use_syncobj || handleTypes) {
3161 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3162 if (ret) {
3163 vk_free2(&device->alloc, pAllocator, fence);
3164 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3165 }
3166 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3167 device->ws->signal_syncobj(device->ws, fence->syncobj);
3168 }
3169 fence->fence = NULL;
3170 } else {
3171 fence->fence = device->ws->create_fence();
3172 if (!fence->fence) {
3173 vk_free2(&device->alloc, pAllocator, fence);
3174 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3175 }
3176 fence->syncobj = 0;
3177 }
3178
3179 *pFence = radv_fence_to_handle(fence);
3180
3181 return VK_SUCCESS;
3182 }
3183
3184 void radv_DestroyFence(
3185 VkDevice _device,
3186 VkFence _fence,
3187 const VkAllocationCallbacks* pAllocator)
3188 {
3189 RADV_FROM_HANDLE(radv_device, device, _device);
3190 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3191
3192 if (!fence)
3193 return;
3194
3195 if (fence->temp_syncobj)
3196 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3197 if (fence->syncobj)
3198 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3199 if (fence->fence)
3200 device->ws->destroy_fence(fence->fence);
3201 vk_free2(&device->alloc, pAllocator, fence);
3202 }
3203
3204
3205 static uint64_t radv_get_current_time()
3206 {
3207 struct timespec tv;
3208 clock_gettime(CLOCK_MONOTONIC, &tv);
3209 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3210 }
3211
3212 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3213 {
3214 uint64_t current_time = radv_get_current_time();
3215
3216 timeout = MIN2(UINT64_MAX - current_time, timeout);
3217
3218 return current_time + timeout;
3219 }
3220
3221
3222 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3223 {
3224 for (uint32_t i = 0; i < fenceCount; ++i) {
3225 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3226 if (fence->syncobj || fence->temp_syncobj || (!fence->signalled && !fence->submitted))
3227 return false;
3228 }
3229 return true;
3230 }
3231
3232 VkResult radv_WaitForFences(
3233 VkDevice _device,
3234 uint32_t fenceCount,
3235 const VkFence* pFences,
3236 VkBool32 waitAll,
3237 uint64_t timeout)
3238 {
3239 RADV_FROM_HANDLE(radv_device, device, _device);
3240 timeout = radv_get_absolute_timeout(timeout);
3241
3242 if (device->always_use_syncobj) {
3243 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3244 if (!handles)
3245 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3246
3247 for (uint32_t i = 0; i < fenceCount; ++i) {
3248 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3249 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3250 }
3251
3252 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3253
3254 free(handles);
3255 return success ? VK_SUCCESS : VK_TIMEOUT;
3256 }
3257
3258 if (!waitAll && fenceCount > 1) {
3259 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3260 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3261 uint32_t wait_count = 0;
3262 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3263 if (!fences)
3264 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3265
3266 for (uint32_t i = 0; i < fenceCount; ++i) {
3267 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3268
3269 if (fence->signalled) {
3270 free(fences);
3271 return VK_SUCCESS;
3272 }
3273
3274 fences[wait_count++] = fence->fence;
3275 }
3276
3277 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3278 waitAll, timeout - radv_get_current_time());
3279
3280 free(fences);
3281 return success ? VK_SUCCESS : VK_TIMEOUT;
3282 }
3283
3284 while(radv_get_current_time() <= timeout) {
3285 for (uint32_t i = 0; i < fenceCount; ++i) {
3286 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3287 return VK_SUCCESS;
3288 }
3289 }
3290 return VK_TIMEOUT;
3291 }
3292
3293 for (uint32_t i = 0; i < fenceCount; ++i) {
3294 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3295 bool expired = false;
3296
3297 if (fence->temp_syncobj) {
3298 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3299 return VK_TIMEOUT;
3300 continue;
3301 }
3302
3303 if (fence->syncobj) {
3304 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3305 return VK_TIMEOUT;
3306 continue;
3307 }
3308
3309 if (fence->signalled)
3310 continue;
3311
3312 if (!fence->submitted) {
3313 while(radv_get_current_time() <= timeout && !fence->submitted)
3314 /* Do nothing */;
3315
3316 if (!fence->submitted)
3317 return VK_TIMEOUT;
3318
3319 /* Recheck as it may have been set by submitting operations. */
3320 if (fence->signalled)
3321 continue;
3322 }
3323
3324 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
3325 if (!expired)
3326 return VK_TIMEOUT;
3327
3328 fence->signalled = true;
3329 }
3330
3331 return VK_SUCCESS;
3332 }
3333
3334 VkResult radv_ResetFences(VkDevice _device,
3335 uint32_t fenceCount,
3336 const VkFence *pFences)
3337 {
3338 RADV_FROM_HANDLE(radv_device, device, _device);
3339
3340 for (unsigned i = 0; i < fenceCount; ++i) {
3341 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3342 fence->submitted = fence->signalled = false;
3343
3344 /* Per spec, we first restore the permanent payload, and then reset, so
3345 * having a temp syncobj should not skip resetting the permanent syncobj. */
3346 if (fence->temp_syncobj) {
3347 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3348 fence->temp_syncobj = 0;
3349 }
3350
3351 if (fence->syncobj) {
3352 device->ws->reset_syncobj(device->ws, fence->syncobj);
3353 }
3354 }
3355
3356 return VK_SUCCESS;
3357 }
3358
3359 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3360 {
3361 RADV_FROM_HANDLE(radv_device, device, _device);
3362 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3363
3364 if (fence->temp_syncobj) {
3365 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3366 return success ? VK_SUCCESS : VK_NOT_READY;
3367 }
3368
3369 if (fence->syncobj) {
3370 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3371 return success ? VK_SUCCESS : VK_NOT_READY;
3372 }
3373
3374 if (fence->signalled)
3375 return VK_SUCCESS;
3376 if (!fence->submitted)
3377 return VK_NOT_READY;
3378 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3379 return VK_NOT_READY;
3380
3381 return VK_SUCCESS;
3382 }
3383
3384
3385 // Queue semaphore functions
3386
3387 VkResult radv_CreateSemaphore(
3388 VkDevice _device,
3389 const VkSemaphoreCreateInfo* pCreateInfo,
3390 const VkAllocationCallbacks* pAllocator,
3391 VkSemaphore* pSemaphore)
3392 {
3393 RADV_FROM_HANDLE(radv_device, device, _device);
3394 const VkExportSemaphoreCreateInfoKHR *export =
3395 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
3396 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
3397 export ? export->handleTypes : 0;
3398
3399 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3400 sizeof(*sem), 8,
3401 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3402 if (!sem)
3403 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3404
3405 sem->temp_syncobj = 0;
3406 /* create a syncobject if we are going to export this semaphore */
3407 if (device->always_use_syncobj || handleTypes) {
3408 assert (device->physical_device->rad_info.has_syncobj);
3409 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3410 if (ret) {
3411 vk_free2(&device->alloc, pAllocator, sem);
3412 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3413 }
3414 sem->sem = NULL;
3415 } else {
3416 sem->sem = device->ws->create_sem(device->ws);
3417 if (!sem->sem) {
3418 vk_free2(&device->alloc, pAllocator, sem);
3419 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3420 }
3421 sem->syncobj = 0;
3422 }
3423
3424 *pSemaphore = radv_semaphore_to_handle(sem);
3425 return VK_SUCCESS;
3426 }
3427
3428 void radv_DestroySemaphore(
3429 VkDevice _device,
3430 VkSemaphore _semaphore,
3431 const VkAllocationCallbacks* pAllocator)
3432 {
3433 RADV_FROM_HANDLE(radv_device, device, _device);
3434 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3435 if (!_semaphore)
3436 return;
3437
3438 if (sem->syncobj)
3439 device->ws->destroy_syncobj(device->ws, sem->syncobj);
3440 else
3441 device->ws->destroy_sem(sem->sem);
3442 vk_free2(&device->alloc, pAllocator, sem);
3443 }
3444
3445 VkResult radv_CreateEvent(
3446 VkDevice _device,
3447 const VkEventCreateInfo* pCreateInfo,
3448 const VkAllocationCallbacks* pAllocator,
3449 VkEvent* pEvent)
3450 {
3451 RADV_FROM_HANDLE(radv_device, device, _device);
3452 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
3453 sizeof(*event), 8,
3454 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3455
3456 if (!event)
3457 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3458
3459 event->bo = device->ws->buffer_create(device->ws, 8, 8,
3460 RADEON_DOMAIN_GTT,
3461 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
3462 if (!event->bo) {
3463 vk_free2(&device->alloc, pAllocator, event);
3464 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
3465 }
3466
3467 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
3468
3469 *pEvent = radv_event_to_handle(event);
3470
3471 return VK_SUCCESS;
3472 }
3473
3474 void radv_DestroyEvent(
3475 VkDevice _device,
3476 VkEvent _event,
3477 const VkAllocationCallbacks* pAllocator)
3478 {
3479 RADV_FROM_HANDLE(radv_device, device, _device);
3480 RADV_FROM_HANDLE(radv_event, event, _event);
3481
3482 if (!event)
3483 return;
3484 device->ws->buffer_destroy(event->bo);
3485 vk_free2(&device->alloc, pAllocator, event);
3486 }
3487
3488 VkResult radv_GetEventStatus(
3489 VkDevice _device,
3490 VkEvent _event)
3491 {
3492 RADV_FROM_HANDLE(radv_event, event, _event);
3493
3494 if (*event->map == 1)
3495 return VK_EVENT_SET;
3496 return VK_EVENT_RESET;
3497 }
3498
3499 VkResult radv_SetEvent(
3500 VkDevice _device,
3501 VkEvent _event)
3502 {
3503 RADV_FROM_HANDLE(radv_event, event, _event);
3504 *event->map = 1;
3505
3506 return VK_SUCCESS;
3507 }
3508
3509 VkResult radv_ResetEvent(
3510 VkDevice _device,
3511 VkEvent _event)
3512 {
3513 RADV_FROM_HANDLE(radv_event, event, _event);
3514 *event->map = 0;
3515
3516 return VK_SUCCESS;
3517 }
3518
3519 VkResult radv_CreateBuffer(
3520 VkDevice _device,
3521 const VkBufferCreateInfo* pCreateInfo,
3522 const VkAllocationCallbacks* pAllocator,
3523 VkBuffer* pBuffer)
3524 {
3525 RADV_FROM_HANDLE(radv_device, device, _device);
3526 struct radv_buffer *buffer;
3527
3528 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
3529
3530 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
3531 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3532 if (buffer == NULL)
3533 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3534
3535 buffer->size = pCreateInfo->size;
3536 buffer->usage = pCreateInfo->usage;
3537 buffer->bo = NULL;
3538 buffer->offset = 0;
3539 buffer->flags = pCreateInfo->flags;
3540
3541 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
3542 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR) != NULL;
3543
3544 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
3545 buffer->bo = device->ws->buffer_create(device->ws,
3546 align64(buffer->size, 4096),
3547 4096, 0, RADEON_FLAG_VIRTUAL);
3548 if (!buffer->bo) {
3549 vk_free2(&device->alloc, pAllocator, buffer);
3550 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
3551 }
3552 }
3553
3554 *pBuffer = radv_buffer_to_handle(buffer);
3555
3556 return VK_SUCCESS;
3557 }
3558
3559 void radv_DestroyBuffer(
3560 VkDevice _device,
3561 VkBuffer _buffer,
3562 const VkAllocationCallbacks* pAllocator)
3563 {
3564 RADV_FROM_HANDLE(radv_device, device, _device);
3565 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3566
3567 if (!buffer)
3568 return;
3569
3570 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3571 device->ws->buffer_destroy(buffer->bo);
3572
3573 vk_free2(&device->alloc, pAllocator, buffer);
3574 }
3575
3576 static inline unsigned
3577 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
3578 {
3579 if (stencil)
3580 return image->surface.u.legacy.stencil_tiling_index[level];
3581 else
3582 return image->surface.u.legacy.tiling_index[level];
3583 }
3584
3585 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
3586 {
3587 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
3588 }
3589
3590 static uint32_t
3591 radv_init_dcc_control_reg(struct radv_device *device,
3592 struct radv_image_view *iview)
3593 {
3594 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
3595 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
3596 unsigned max_compressed_block_size;
3597 unsigned independent_64b_blocks;
3598
3599 if (device->physical_device->rad_info.chip_class < VI)
3600 return 0;
3601
3602 if (iview->image->info.samples > 1) {
3603 if (iview->image->surface.bpe == 1)
3604 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3605 else if (iview->image->surface.bpe == 2)
3606 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
3607 }
3608
3609 if (!device->physical_device->rad_info.has_dedicated_vram) {
3610 /* amdvlk: [min-compressed-block-size] should be set to 32 for
3611 * dGPU and 64 for APU because all of our APUs to date use
3612 * DIMMs which have a request granularity size of 64B while all
3613 * other chips have a 32B request size.
3614 */
3615 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
3616 }
3617
3618 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
3619 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
3620 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
3621 /* If this DCC image is potentially going to be used in texture
3622 * fetches, we need some special settings.
3623 */
3624 independent_64b_blocks = 1;
3625 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3626 } else {
3627 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
3628 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
3629 * big as possible for better compression state.
3630 */
3631 independent_64b_blocks = 0;
3632 max_compressed_block_size = max_uncompressed_block_size;
3633 }
3634
3635 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3636 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
3637 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
3638 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
3639 }
3640
3641 static void
3642 radv_initialise_color_surface(struct radv_device *device,
3643 struct radv_color_buffer_info *cb,
3644 struct radv_image_view *iview)
3645 {
3646 const struct vk_format_description *desc;
3647 unsigned ntype, format, swap, endian;
3648 unsigned blend_clamp = 0, blend_bypass = 0;
3649 uint64_t va;
3650 const struct radeon_surf *surf = &iview->image->surface;
3651
3652 desc = vk_format_description(iview->vk_format);
3653
3654 memset(cb, 0, sizeof(*cb));
3655
3656 /* Intensity is implemented as Red, so treat it that way. */
3657 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
3658
3659 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3660
3661 cb->cb_color_base = va >> 8;
3662
3663 if (device->physical_device->rad_info.chip_class >= GFX9) {
3664 struct gfx9_surf_meta_flags meta;
3665 if (iview->image->dcc_offset)
3666 meta = iview->image->surface.u.gfx9.dcc;
3667 else
3668 meta = iview->image->surface.u.gfx9.cmask;
3669
3670 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3671 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
3672 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3673 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3674
3675 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
3676 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3677 } else {
3678 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
3679 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3680
3681 cb->cb_color_base += level_info->offset >> 8;
3682 if (level_info->mode == RADEON_SURF_MODE_2D)
3683 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3684
3685 pitch_tile_max = level_info->nblk_x / 8 - 1;
3686 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
3687 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
3688
3689 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3690 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3691 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
3692
3693 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3694
3695 if (radv_image_has_fmask(iview->image)) {
3696 if (device->physical_device->rad_info.chip_class >= CIK)
3697 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
3698 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
3699 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
3700 } else {
3701 /* This must be set for fast clear to work without FMASK. */
3702 if (device->physical_device->rad_info.chip_class >= CIK)
3703 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3704 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3705 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3706 }
3707 }
3708
3709 /* CMASK variables */
3710 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3711 va += iview->image->cmask.offset;
3712 cb->cb_color_cmask = va >> 8;
3713
3714 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3715 va += iview->image->dcc_offset;
3716 cb->cb_dcc_base = va >> 8;
3717 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
3718
3719 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3720 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3721 S_028C6C_SLICE_MAX(max_slice);
3722
3723 if (iview->image->info.samples > 1) {
3724 unsigned log_samples = util_logbase2(iview->image->info.samples);
3725
3726 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3727 S_028C74_NUM_FRAGMENTS(log_samples);
3728 }
3729
3730 if (radv_image_has_fmask(iview->image)) {
3731 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3732 cb->cb_color_fmask = va >> 8;
3733 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3734 } else {
3735 cb->cb_color_fmask = cb->cb_color_base;
3736 }
3737
3738 ntype = radv_translate_color_numformat(iview->vk_format,
3739 desc,
3740 vk_format_get_first_non_void_channel(iview->vk_format));
3741 format = radv_translate_colorformat(iview->vk_format);
3742 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3743 radv_finishme("Illegal color\n");
3744 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3745 endian = radv_colorformat_endian_swap(format);
3746
3747 /* blend clamp should be set for all NORM/SRGB types */
3748 if (ntype == V_028C70_NUMBER_UNORM ||
3749 ntype == V_028C70_NUMBER_SNORM ||
3750 ntype == V_028C70_NUMBER_SRGB)
3751 blend_clamp = 1;
3752
3753 /* set blend bypass according to docs if SINT/UINT or
3754 8/24 COLOR variants */
3755 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3756 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3757 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3758 blend_clamp = 0;
3759 blend_bypass = 1;
3760 }
3761 #if 0
3762 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3763 (format == V_028C70_COLOR_8 ||
3764 format == V_028C70_COLOR_8_8 ||
3765 format == V_028C70_COLOR_8_8_8_8))
3766 ->color_is_int8 = true;
3767 #endif
3768 cb->cb_color_info = S_028C70_FORMAT(format) |
3769 S_028C70_COMP_SWAP(swap) |
3770 S_028C70_BLEND_CLAMP(blend_clamp) |
3771 S_028C70_BLEND_BYPASS(blend_bypass) |
3772 S_028C70_SIMPLE_FLOAT(1) |
3773 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3774 ntype != V_028C70_NUMBER_SNORM &&
3775 ntype != V_028C70_NUMBER_SRGB &&
3776 format != V_028C70_COLOR_8_24 &&
3777 format != V_028C70_COLOR_24_8) |
3778 S_028C70_NUMBER_TYPE(ntype) |
3779 S_028C70_ENDIAN(endian);
3780 if (radv_image_has_fmask(iview->image)) {
3781 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3782 if (device->physical_device->rad_info.chip_class == SI) {
3783 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3784 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3785 }
3786 }
3787
3788 if (radv_image_has_cmask(iview->image) &&
3789 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3790 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3791
3792 if (radv_dcc_enabled(iview->image, iview->base_mip))
3793 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3794
3795 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
3796
3797 /* This must be set for fast clear to work without FMASK. */
3798 if (!radv_image_has_fmask(iview->image) &&
3799 device->physical_device->rad_info.chip_class == SI) {
3800 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3801 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3802 }
3803
3804 if (device->physical_device->rad_info.chip_class >= GFX9) {
3805 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
3806 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
3807
3808 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3809 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3810 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3811 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
3812 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
3813 S_028C68_MAX_MIP(iview->image->info.levels - 1);
3814 }
3815 }
3816
3817 static unsigned
3818 radv_calc_decompress_on_z_planes(struct radv_device *device,
3819 struct radv_image_view *iview)
3820 {
3821 unsigned max_zplanes = 0;
3822
3823 assert(radv_image_is_tc_compat_htile(iview->image));
3824
3825 if (device->physical_device->rad_info.chip_class >= GFX9) {
3826 /* Default value for 32-bit depth surfaces. */
3827 max_zplanes = 4;
3828
3829 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
3830 iview->image->info.samples > 1)
3831 max_zplanes = 2;
3832
3833 max_zplanes = max_zplanes + 1;
3834 } else {
3835 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
3836 /* Do not enable Z plane compression for 16-bit depth
3837 * surfaces because isn't supported on GFX8. Only
3838 * 32-bit depth surfaces are supported by the hardware.
3839 * This allows to maintain shader compatibility and to
3840 * reduce the number of depth decompressions.
3841 */
3842 max_zplanes = 1;
3843 } else {
3844 if (iview->image->info.samples <= 1)
3845 max_zplanes = 5;
3846 else if (iview->image->info.samples <= 4)
3847 max_zplanes = 3;
3848 else
3849 max_zplanes = 2;
3850 }
3851 }
3852
3853 return max_zplanes;
3854 }
3855
3856 static void
3857 radv_initialise_ds_surface(struct radv_device *device,
3858 struct radv_ds_buffer_info *ds,
3859 struct radv_image_view *iview)
3860 {
3861 unsigned level = iview->base_mip;
3862 unsigned format, stencil_format;
3863 uint64_t va, s_offs, z_offs;
3864 bool stencil_only = false;
3865 memset(ds, 0, sizeof(*ds));
3866 switch (iview->image->vk_format) {
3867 case VK_FORMAT_D24_UNORM_S8_UINT:
3868 case VK_FORMAT_X8_D24_UNORM_PACK32:
3869 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3870 ds->offset_scale = 2.0f;
3871 break;
3872 case VK_FORMAT_D16_UNORM:
3873 case VK_FORMAT_D16_UNORM_S8_UINT:
3874 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3875 ds->offset_scale = 4.0f;
3876 break;
3877 case VK_FORMAT_D32_SFLOAT:
3878 case VK_FORMAT_D32_SFLOAT_S8_UINT:
3879 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3880 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3881 ds->offset_scale = 1.0f;
3882 break;
3883 case VK_FORMAT_S8_UINT:
3884 stencil_only = true;
3885 break;
3886 default:
3887 break;
3888 }
3889
3890 format = radv_translate_dbformat(iview->image->vk_format);
3891 stencil_format = iview->image->surface.has_stencil ?
3892 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
3893
3894 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3895 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
3896 S_028008_SLICE_MAX(max_slice);
3897
3898 ds->db_htile_data_base = 0;
3899 ds->db_htile_surface = 0;
3900
3901 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3902 s_offs = z_offs = va;
3903
3904 if (device->physical_device->rad_info.chip_class >= GFX9) {
3905 assert(iview->image->surface.u.gfx9.surf_offset == 0);
3906 s_offs += iview->image->surface.u.gfx9.stencil_offset;
3907
3908 ds->db_z_info = S_028038_FORMAT(format) |
3909 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
3910 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3911 S_028038_MAXMIP(iview->image->info.levels - 1);
3912 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
3913 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
3914
3915 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3916 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
3917 ds->db_depth_view |= S_028008_MIPID(level);
3918
3919 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
3920 S_02801C_Y_MAX(iview->image->info.height - 1);
3921
3922 if (radv_htile_enabled(iview->image, level)) {
3923 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
3924
3925 if (radv_image_is_tc_compat_htile(iview->image)) {
3926 unsigned max_zplanes =
3927 radv_calc_decompress_on_z_planes(device, iview);
3928
3929 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
3930 S_028038_ITERATE_FLUSH(1);
3931 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
3932 }
3933
3934 if (!iview->image->surface.has_stencil)
3935 /* Use all of the htile_buffer for depth if there's no stencil. */
3936 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
3937 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3938 iview->image->htile_offset;
3939 ds->db_htile_data_base = va >> 8;
3940 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
3941 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
3942 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
3943 }
3944 } else {
3945 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
3946
3947 if (stencil_only)
3948 level_info = &iview->image->surface.u.legacy.stencil_level[level];
3949
3950 z_offs += iview->image->surface.u.legacy.level[level].offset;
3951 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
3952
3953 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
3954 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
3955 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
3956
3957 if (iview->image->info.samples > 1)
3958 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
3959
3960 if (device->physical_device->rad_info.chip_class >= CIK) {
3961 struct radeon_info *info = &device->physical_device->rad_info;
3962 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
3963 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
3964 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
3965 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
3966 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
3967 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
3968
3969 if (stencil_only)
3970 tile_mode = stencil_tile_mode;
3971
3972 ds->db_depth_info |=
3973 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
3974 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
3975 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
3976 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
3977 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
3978 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
3979 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
3980 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
3981 } else {
3982 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
3983 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3984 tile_mode_index = si_tile_mode_index(iview->image, level, true);
3985 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
3986 if (stencil_only)
3987 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3988 }
3989
3990 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
3991 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
3992 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
3993
3994 if (radv_htile_enabled(iview->image, level)) {
3995 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
3996
3997 if (!iview->image->surface.has_stencil &&
3998 !radv_image_is_tc_compat_htile(iview->image))
3999 /* Use all of the htile_buffer for depth if there's no stencil. */
4000 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4001
4002 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4003 iview->image->htile_offset;
4004 ds->db_htile_data_base = va >> 8;
4005 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4006
4007 if (radv_image_is_tc_compat_htile(iview->image)) {
4008 unsigned max_zplanes =
4009 radv_calc_decompress_on_z_planes(device, iview);
4010
4011 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4012 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4013 }
4014 }
4015 }
4016
4017 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4018 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4019 }
4020
4021 VkResult radv_CreateFramebuffer(
4022 VkDevice _device,
4023 const VkFramebufferCreateInfo* pCreateInfo,
4024 const VkAllocationCallbacks* pAllocator,
4025 VkFramebuffer* pFramebuffer)
4026 {
4027 RADV_FROM_HANDLE(radv_device, device, _device);
4028 struct radv_framebuffer *framebuffer;
4029
4030 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4031
4032 size_t size = sizeof(*framebuffer) +
4033 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4034 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4035 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4036 if (framebuffer == NULL)
4037 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
4038
4039 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4040 framebuffer->width = pCreateInfo->width;
4041 framebuffer->height = pCreateInfo->height;
4042 framebuffer->layers = pCreateInfo->layers;
4043 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4044 VkImageView _iview = pCreateInfo->pAttachments[i];
4045 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4046 framebuffer->attachments[i].attachment = iview;
4047 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
4048 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4049 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4050 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4051 }
4052 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4053 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4054 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4055 }
4056
4057 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4058 return VK_SUCCESS;
4059 }
4060
4061 void radv_DestroyFramebuffer(
4062 VkDevice _device,
4063 VkFramebuffer _fb,
4064 const VkAllocationCallbacks* pAllocator)
4065 {
4066 RADV_FROM_HANDLE(radv_device, device, _device);
4067 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4068
4069 if (!fb)
4070 return;
4071 vk_free2(&device->alloc, pAllocator, fb);
4072 }
4073
4074 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4075 {
4076 switch (address_mode) {
4077 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4078 return V_008F30_SQ_TEX_WRAP;
4079 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4080 return V_008F30_SQ_TEX_MIRROR;
4081 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4082 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4083 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4084 return V_008F30_SQ_TEX_CLAMP_BORDER;
4085 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4086 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4087 default:
4088 unreachable("illegal tex wrap mode");
4089 break;
4090 }
4091 }
4092
4093 static unsigned
4094 radv_tex_compare(VkCompareOp op)
4095 {
4096 switch (op) {
4097 case VK_COMPARE_OP_NEVER:
4098 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4099 case VK_COMPARE_OP_LESS:
4100 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4101 case VK_COMPARE_OP_EQUAL:
4102 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4103 case VK_COMPARE_OP_LESS_OR_EQUAL:
4104 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4105 case VK_COMPARE_OP_GREATER:
4106 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4107 case VK_COMPARE_OP_NOT_EQUAL:
4108 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4109 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4110 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4111 case VK_COMPARE_OP_ALWAYS:
4112 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4113 default:
4114 unreachable("illegal compare mode");
4115 break;
4116 }
4117 }
4118
4119 static unsigned
4120 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4121 {
4122 switch (filter) {
4123 case VK_FILTER_NEAREST:
4124 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4125 V_008F38_SQ_TEX_XY_FILTER_POINT);
4126 case VK_FILTER_LINEAR:
4127 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4128 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4129 case VK_FILTER_CUBIC_IMG:
4130 default:
4131 fprintf(stderr, "illegal texture filter");
4132 return 0;
4133 }
4134 }
4135
4136 static unsigned
4137 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4138 {
4139 switch (mode) {
4140 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4141 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4142 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4143 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4144 default:
4145 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4146 }
4147 }
4148
4149 static unsigned
4150 radv_tex_bordercolor(VkBorderColor bcolor)
4151 {
4152 switch (bcolor) {
4153 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4154 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4155 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4156 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4157 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4158 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4159 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4160 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4161 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4162 default:
4163 break;
4164 }
4165 return 0;
4166 }
4167
4168 static unsigned
4169 radv_tex_aniso_filter(unsigned filter)
4170 {
4171 if (filter < 2)
4172 return 0;
4173 if (filter < 4)
4174 return 1;
4175 if (filter < 8)
4176 return 2;
4177 if (filter < 16)
4178 return 3;
4179 return 4;
4180 }
4181
4182 static unsigned
4183 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4184 {
4185 switch (mode) {
4186 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4187 return SQ_IMG_FILTER_MODE_BLEND;
4188 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4189 return SQ_IMG_FILTER_MODE_MIN;
4190 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4191 return SQ_IMG_FILTER_MODE_MAX;
4192 default:
4193 break;
4194 }
4195 return 0;
4196 }
4197
4198 static void
4199 radv_init_sampler(struct radv_device *device,
4200 struct radv_sampler *sampler,
4201 const VkSamplerCreateInfo *pCreateInfo)
4202 {
4203 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
4204 (uint32_t) pCreateInfo->maxAnisotropy : 0;
4205 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4206 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4207 unsigned filter_mode = SQ_IMG_FILTER_MODE_BLEND;
4208
4209 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4210 vk_find_struct_const(pCreateInfo->pNext,
4211 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4212 if (sampler_reduction)
4213 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4214
4215 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4216 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4217 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4218 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4219 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4220 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4221 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4222 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4223 S_008F30_DISABLE_CUBE_WRAP(0) |
4224 S_008F30_COMPAT_MODE(is_vi) |
4225 S_008F30_FILTER_MODE(filter_mode));
4226 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4227 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4228 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4229 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4230 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4231 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4232 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4233 S_008F38_MIP_POINT_PRECLAMP(0) |
4234 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4235 S_008F38_FILTER_PREC_FIX(1) |
4236 S_008F38_ANISO_OVERRIDE(is_vi));
4237 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4238 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4239 }
4240
4241 VkResult radv_CreateSampler(
4242 VkDevice _device,
4243 const VkSamplerCreateInfo* pCreateInfo,
4244 const VkAllocationCallbacks* pAllocator,
4245 VkSampler* pSampler)
4246 {
4247 RADV_FROM_HANDLE(radv_device, device, _device);
4248 struct radv_sampler *sampler;
4249
4250 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4251
4252 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4253 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4254 if (!sampler)
4255 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
4256
4257 radv_init_sampler(device, sampler, pCreateInfo);
4258 *pSampler = radv_sampler_to_handle(sampler);
4259
4260 return VK_SUCCESS;
4261 }
4262
4263 void radv_DestroySampler(
4264 VkDevice _device,
4265 VkSampler _sampler,
4266 const VkAllocationCallbacks* pAllocator)
4267 {
4268 RADV_FROM_HANDLE(radv_device, device, _device);
4269 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4270
4271 if (!sampler)
4272 return;
4273 vk_free2(&device->alloc, pAllocator, sampler);
4274 }
4275
4276 /* vk_icd.h does not declare this function, so we declare it here to
4277 * suppress Wmissing-prototypes.
4278 */
4279 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4280 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4281
4282 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4283 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4284 {
4285 /* For the full details on loader interface versioning, see
4286 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4287 * What follows is a condensed summary, to help you navigate the large and
4288 * confusing official doc.
4289 *
4290 * - Loader interface v0 is incompatible with later versions. We don't
4291 * support it.
4292 *
4293 * - In loader interface v1:
4294 * - The first ICD entrypoint called by the loader is
4295 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4296 * entrypoint.
4297 * - The ICD must statically expose no other Vulkan symbol unless it is
4298 * linked with -Bsymbolic.
4299 * - Each dispatchable Vulkan handle created by the ICD must be
4300 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4301 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4302 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4303 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4304 * such loader-managed surfaces.
4305 *
4306 * - Loader interface v2 differs from v1 in:
4307 * - The first ICD entrypoint called by the loader is
4308 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4309 * statically expose this entrypoint.
4310 *
4311 * - Loader interface v3 differs from v2 in:
4312 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4313 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4314 * because the loader no longer does so.
4315 */
4316 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4317 return VK_SUCCESS;
4318 }
4319
4320 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4321 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4322 int *pFD)
4323 {
4324 RADV_FROM_HANDLE(radv_device, device, _device);
4325 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4326
4327 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4328
4329 /* At the moment, we support only the below handle types. */
4330 assert(pGetFdInfo->handleType ==
4331 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4332 pGetFdInfo->handleType ==
4333 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4334
4335 bool ret = radv_get_memory_fd(device, memory, pFD);
4336 if (ret == false)
4337 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
4338 return VK_SUCCESS;
4339 }
4340
4341 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4342 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
4343 int fd,
4344 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4345 {
4346 switch (handleType) {
4347 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4348 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4349 return VK_SUCCESS;
4350
4351 default:
4352 /* The valid usage section for this function says:
4353 *
4354 * "handleType must not be one of the handle types defined as
4355 * opaque."
4356 *
4357 * So opaque handle types fall into the default "unsupported" case.
4358 */
4359 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4360 }
4361 }
4362
4363 static VkResult radv_import_opaque_fd(struct radv_device *device,
4364 int fd,
4365 uint32_t *syncobj)
4366 {
4367 uint32_t syncobj_handle = 0;
4368 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4369 if (ret != 0)
4370 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4371
4372 if (*syncobj)
4373 device->ws->destroy_syncobj(device->ws, *syncobj);
4374
4375 *syncobj = syncobj_handle;
4376 close(fd);
4377
4378 return VK_SUCCESS;
4379 }
4380
4381 static VkResult radv_import_sync_fd(struct radv_device *device,
4382 int fd,
4383 uint32_t *syncobj)
4384 {
4385 /* If we create a syncobj we do it locally so that if we have an error, we don't
4386 * leave a syncobj in an undetermined state in the fence. */
4387 uint32_t syncobj_handle = *syncobj;
4388 if (!syncobj_handle) {
4389 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4390 if (ret) {
4391 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4392 }
4393 }
4394
4395 if (fd == -1) {
4396 device->ws->signal_syncobj(device->ws, syncobj_handle);
4397 } else {
4398 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
4399 if (ret != 0)
4400 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4401 }
4402
4403 *syncobj = syncobj_handle;
4404 if (fd != -1)
4405 close(fd);
4406
4407 return VK_SUCCESS;
4408 }
4409
4410 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
4411 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
4412 {
4413 RADV_FROM_HANDLE(radv_device, device, _device);
4414 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
4415 uint32_t *syncobj_dst = NULL;
4416
4417 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
4418 syncobj_dst = &sem->temp_syncobj;
4419 } else {
4420 syncobj_dst = &sem->syncobj;
4421 }
4422
4423 switch(pImportSemaphoreFdInfo->handleType) {
4424 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4425 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4426 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4427 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4428 default:
4429 unreachable("Unhandled semaphore handle type");
4430 }
4431 }
4432
4433 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
4434 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
4435 int *pFd)
4436 {
4437 RADV_FROM_HANDLE(radv_device, device, _device);
4438 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
4439 int ret;
4440 uint32_t syncobj_handle;
4441
4442 if (sem->temp_syncobj)
4443 syncobj_handle = sem->temp_syncobj;
4444 else
4445 syncobj_handle = sem->syncobj;
4446
4447 switch(pGetFdInfo->handleType) {
4448 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4449 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4450 break;
4451 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4452 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4453 if (!ret) {
4454 if (sem->temp_syncobj) {
4455 close (sem->temp_syncobj);
4456 sem->temp_syncobj = 0;
4457 } else {
4458 device->ws->reset_syncobj(device->ws, syncobj_handle);
4459 }
4460 }
4461 break;
4462 default:
4463 unreachable("Unhandled semaphore handle type");
4464 }
4465
4466 if (ret)
4467 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4468 return VK_SUCCESS;
4469 }
4470
4471 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
4472 VkPhysicalDevice physicalDevice,
4473 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
4474 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
4475 {
4476 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4477
4478 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
4479 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4480 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4481 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4482 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4483 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4484 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4485 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4486 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
4487 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4488 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4489 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4490 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4491 } else {
4492 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
4493 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
4494 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
4495 }
4496 }
4497
4498 VkResult radv_ImportFenceFdKHR(VkDevice _device,
4499 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
4500 {
4501 RADV_FROM_HANDLE(radv_device, device, _device);
4502 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
4503 uint32_t *syncobj_dst = NULL;
4504
4505
4506 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT_KHR) {
4507 syncobj_dst = &fence->temp_syncobj;
4508 } else {
4509 syncobj_dst = &fence->syncobj;
4510 }
4511
4512 switch(pImportFenceFdInfo->handleType) {
4513 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4514 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4515 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4516 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4517 default:
4518 unreachable("Unhandled fence handle type");
4519 }
4520 }
4521
4522 VkResult radv_GetFenceFdKHR(VkDevice _device,
4523 const VkFenceGetFdInfoKHR *pGetFdInfo,
4524 int *pFd)
4525 {
4526 RADV_FROM_HANDLE(radv_device, device, _device);
4527 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
4528 int ret;
4529 uint32_t syncobj_handle;
4530
4531 if (fence->temp_syncobj)
4532 syncobj_handle = fence->temp_syncobj;
4533 else
4534 syncobj_handle = fence->syncobj;
4535
4536 switch(pGetFdInfo->handleType) {
4537 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4538 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4539 break;
4540 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4541 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4542 if (!ret) {
4543 if (fence->temp_syncobj) {
4544 close (fence->temp_syncobj);
4545 fence->temp_syncobj = 0;
4546 } else {
4547 device->ws->reset_syncobj(device->ws, syncobj_handle);
4548 }
4549 }
4550 break;
4551 default:
4552 unreachable("Unhandled fence handle type");
4553 }
4554
4555 if (ret)
4556 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4557 return VK_SUCCESS;
4558 }
4559
4560 void radv_GetPhysicalDeviceExternalFenceProperties(
4561 VkPhysicalDevice physicalDevice,
4562 const VkPhysicalDeviceExternalFenceInfoKHR* pExternalFenceInfo,
4563 VkExternalFencePropertiesKHR* pExternalFenceProperties)
4564 {
4565 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4566
4567 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4568 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4569 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4570 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4571 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4572 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT_KHR |
4573 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4574 } else {
4575 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
4576 pExternalFenceProperties->compatibleHandleTypes = 0;
4577 pExternalFenceProperties->externalFenceFeatures = 0;
4578 }
4579 }
4580
4581 VkResult
4582 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
4583 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
4584 const VkAllocationCallbacks* pAllocator,
4585 VkDebugReportCallbackEXT* pCallback)
4586 {
4587 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4588 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
4589 pCreateInfo, pAllocator, &instance->alloc,
4590 pCallback);
4591 }
4592
4593 void
4594 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
4595 VkDebugReportCallbackEXT _callback,
4596 const VkAllocationCallbacks* pAllocator)
4597 {
4598 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4599 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
4600 _callback, pAllocator, &instance->alloc);
4601 }
4602
4603 void
4604 radv_DebugReportMessageEXT(VkInstance _instance,
4605 VkDebugReportFlagsEXT flags,
4606 VkDebugReportObjectTypeEXT objectType,
4607 uint64_t object,
4608 size_t location,
4609 int32_t messageCode,
4610 const char* pLayerPrefix,
4611 const char* pMessage)
4612 {
4613 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4614 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
4615 object, location, messageCode, pLayerPrefix, pMessage);
4616 }
4617
4618 void
4619 radv_GetDeviceGroupPeerMemoryFeatures(
4620 VkDevice device,
4621 uint32_t heapIndex,
4622 uint32_t localDeviceIndex,
4623 uint32_t remoteDeviceIndex,
4624 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
4625 {
4626 assert(localDeviceIndex == remoteDeviceIndex);
4627
4628 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
4629 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
4630 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
4631 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
4632 }