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1c0a50c82fa4037d837dbe7f5d4ea2d350eb71e6
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "gfx9d.h"
47 #include "addrlib/gfx9/chip/gfx9_enum.h"
48 #include "util/debug.h"
49
50 static int
51 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
52 {
53 uint32_t mesa_timestamp, llvm_timestamp;
54 uint16_t f = family;
55 memset(uuid, 0, VK_UUID_SIZE);
56 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
57 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
58 return -1;
59
60 memcpy(uuid, &mesa_timestamp, 4);
61 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
62 memcpy((char*)uuid + 8, &f, 2);
63 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
64 return 0;
65 }
66
67 static void
68 radv_get_driver_uuid(void *uuid)
69 {
70 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
71 }
72
73 static void
74 radv_get_device_uuid(struct radeon_info *info, void *uuid)
75 {
76 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
77 }
78
79 static void
80 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
81 {
82 const char *chip_string;
83 char llvm_string[32] = {};
84
85 switch (family) {
86 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
87 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
88 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
89 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
90 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
91 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
92 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
93 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
94 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
95 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
96 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
97 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
98 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
99 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
100 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
101 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
102 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
103 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
104 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
105 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
106 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
107 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
108 default: chip_string = "AMD RADV unknown"; break;
109 }
110
111 snprintf(llvm_string, sizeof(llvm_string),
112 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
113 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
114 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
115 }
116
117 static void
118 radv_physical_device_init_mem_types(struct radv_physical_device *device)
119 {
120 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
121 uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
122 device->rad_info.vram_vis_size);
123
124 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
125 device->memory_properties.memoryHeapCount = 0;
126 if (device->rad_info.vram_size - visible_vram_size > 0) {
127 vram_index = device->memory_properties.memoryHeapCount++;
128 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
129 .size = device->rad_info.vram_size - visible_vram_size,
130 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
131 };
132 }
133 if (visible_vram_size) {
134 visible_vram_index = device->memory_properties.memoryHeapCount++;
135 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
136 .size = visible_vram_size,
137 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
138 };
139 }
140 if (device->rad_info.gart_size > 0) {
141 gart_index = device->memory_properties.memoryHeapCount++;
142 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
143 .size = device->rad_info.gart_size,
144 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
145 };
146 }
147
148 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
149 unsigned type_count = 0;
150 if (vram_index >= 0) {
151 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
152 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
153 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
154 .heapIndex = vram_index,
155 };
156 }
157 if (gart_index >= 0) {
158 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
159 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
160 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
161 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
162 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
163 .heapIndex = gart_index,
164 };
165 }
166 if (visible_vram_index >= 0) {
167 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
168 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
169 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
170 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
171 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
172 .heapIndex = visible_vram_index,
173 };
174 }
175 if (gart_index >= 0) {
176 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
177 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
178 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
179 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
180 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
181 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
182 .heapIndex = gart_index,
183 };
184 }
185 device->memory_properties.memoryTypeCount = type_count;
186 }
187
188 static void
189 radv_handle_env_var_force_family(struct radv_physical_device *device)
190 {
191 const char *family = getenv("RADV_FORCE_FAMILY");
192 unsigned i;
193
194 if (!family)
195 return;
196
197 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
198 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
199 /* Override family and chip_class. */
200 device->rad_info.family = i;
201
202 if (i >= CHIP_VEGA10)
203 device->rad_info.chip_class = GFX9;
204 else if (i >= CHIP_TONGA)
205 device->rad_info.chip_class = VI;
206 else if (i >= CHIP_BONAIRE)
207 device->rad_info.chip_class = CIK;
208 else
209 device->rad_info.chip_class = SI;
210
211 return;
212 }
213 }
214
215 fprintf(stderr, "radv: Unknown family: %s\n", family);
216 exit(1);
217 }
218
219 static VkResult
220 radv_physical_device_init(struct radv_physical_device *device,
221 struct radv_instance *instance,
222 drmDevicePtr drm_device)
223 {
224 const char *path = drm_device->nodes[DRM_NODE_RENDER];
225 VkResult result;
226 drmVersionPtr version;
227 int fd;
228 int master_fd = -1;
229
230 fd = open(path, O_RDWR | O_CLOEXEC);
231 if (fd < 0) {
232 if (instance->debug_flags & RADV_DEBUG_STARTUP)
233 radv_logi("Could not open device '%s'", path);
234
235 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
236 }
237
238 version = drmGetVersion(fd);
239 if (!version) {
240 close(fd);
241
242 if (instance->debug_flags & RADV_DEBUG_STARTUP)
243 radv_logi("Could not get the kernel driver version for device '%s'", path);
244
245 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
246 "failed to get version %s: %m", path);
247 }
248
249 if (strcmp(version->name, "amdgpu")) {
250 drmFreeVersion(version);
251 if (master_fd != -1)
252 close(master_fd);
253 close(fd);
254
255 if (instance->debug_flags & RADV_DEBUG_STARTUP)
256 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
257
258 return VK_ERROR_INCOMPATIBLE_DRIVER;
259 }
260 drmFreeVersion(version);
261
262 if (instance->debug_flags & RADV_DEBUG_STARTUP)
263 radv_logi("Found compatible device '%s'.", path);
264
265 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
266 device->instance = instance;
267 assert(strlen(path) < ARRAY_SIZE(device->path));
268 strncpy(device->path, path, ARRAY_SIZE(device->path));
269
270 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
271 instance->perftest_flags);
272 if (!device->ws) {
273 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
274 goto fail;
275 }
276
277 if (instance->enabled_extensions.KHR_display) {
278 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
279 if (master_fd >= 0) {
280 uint32_t accel_working = 0;
281 struct drm_amdgpu_info request = {
282 .return_pointer = (uintptr_t)&accel_working,
283 .return_size = sizeof(accel_working),
284 .query = AMDGPU_INFO_ACCEL_WORKING
285 };
286
287 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
288 close(master_fd);
289 master_fd = -1;
290 }
291 }
292 }
293
294 device->master_fd = master_fd;
295 device->local_fd = fd;
296 device->ws->query_info(device->ws, &device->rad_info);
297
298 radv_handle_env_var_force_family(device);
299
300 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
301
302 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
303 device->ws->destroy(device->ws);
304 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
305 "cannot generate UUID");
306 goto fail;
307 }
308
309 /* These flags affect shader compilation. */
310 uint64_t shader_env_flags =
311 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
312 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
313
314 /* The gpu id is already embedded in the uuid so we just pass "radv"
315 * when creating the cache.
316 */
317 char buf[VK_UUID_SIZE * 2 + 1];
318 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
319 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
320
321 if (device->rad_info.chip_class < VI ||
322 device->rad_info.chip_class > GFX9)
323 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
324
325 radv_get_driver_uuid(&device->device_uuid);
326 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
327
328 if (device->rad_info.family == CHIP_STONEY ||
329 device->rad_info.chip_class >= GFX9) {
330 device->has_rbplus = true;
331 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
332 device->rad_info.family == CHIP_VEGA12 ||
333 device->rad_info.family == CHIP_RAVEN;
334 }
335
336 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
337 * on SI.
338 */
339 device->has_clear_state = device->rad_info.chip_class >= CIK;
340
341 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
342
343 /* Vega10/Raven need a special workaround for a hardware bug. */
344 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
345 device->rad_info.family == CHIP_RAVEN;
346
347 /* Out-of-order primitive rasterization. */
348 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
349 device->rad_info.max_se >= 2;
350 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
351 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
352
353 device->dcc_msaa_allowed =
354 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
355
356 radv_physical_device_init_mem_types(device);
357 radv_fill_device_extension_table(device, &device->supported_extensions);
358
359 result = radv_init_wsi(device);
360 if (result != VK_SUCCESS) {
361 device->ws->destroy(device->ws);
362 vk_error(instance, result);
363 goto fail;
364 }
365
366 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
367 ac_print_gpu_info(&device->rad_info);
368
369 return VK_SUCCESS;
370
371 fail:
372 close(fd);
373 if (master_fd != -1)
374 close(master_fd);
375 return result;
376 }
377
378 static void
379 radv_physical_device_finish(struct radv_physical_device *device)
380 {
381 radv_finish_wsi(device);
382 device->ws->destroy(device->ws);
383 disk_cache_destroy(device->disk_cache);
384 close(device->local_fd);
385 if (device->master_fd != -1)
386 close(device->master_fd);
387 }
388
389 static void *
390 default_alloc_func(void *pUserData, size_t size, size_t align,
391 VkSystemAllocationScope allocationScope)
392 {
393 return malloc(size);
394 }
395
396 static void *
397 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
398 size_t align, VkSystemAllocationScope allocationScope)
399 {
400 return realloc(pOriginal, size);
401 }
402
403 static void
404 default_free_func(void *pUserData, void *pMemory)
405 {
406 free(pMemory);
407 }
408
409 static const VkAllocationCallbacks default_alloc = {
410 .pUserData = NULL,
411 .pfnAllocation = default_alloc_func,
412 .pfnReallocation = default_realloc_func,
413 .pfnFree = default_free_func,
414 };
415
416 static const struct debug_control radv_debug_options[] = {
417 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
418 {"nodcc", RADV_DEBUG_NO_DCC},
419 {"shaders", RADV_DEBUG_DUMP_SHADERS},
420 {"nocache", RADV_DEBUG_NO_CACHE},
421 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
422 {"nohiz", RADV_DEBUG_NO_HIZ},
423 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
424 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
425 {"allbos", RADV_DEBUG_ALL_BOS},
426 {"noibs", RADV_DEBUG_NO_IBS},
427 {"spirv", RADV_DEBUG_DUMP_SPIRV},
428 {"vmfaults", RADV_DEBUG_VM_FAULTS},
429 {"zerovram", RADV_DEBUG_ZERO_VRAM},
430 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
431 {"nosisched", RADV_DEBUG_NO_SISCHED},
432 {"preoptir", RADV_DEBUG_PREOPTIR},
433 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
434 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
435 {"info", RADV_DEBUG_INFO},
436 {"errors", RADV_DEBUG_ERRORS},
437 {"startup", RADV_DEBUG_STARTUP},
438 {"checkir", RADV_DEBUG_CHECKIR},
439 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
440 {NULL, 0}
441 };
442
443 const char *
444 radv_get_debug_option_name(int id)
445 {
446 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
447 return radv_debug_options[id].string;
448 }
449
450 static const struct debug_control radv_perftest_options[] = {
451 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
452 {"sisched", RADV_PERFTEST_SISCHED},
453 {"localbos", RADV_PERFTEST_LOCAL_BOS},
454 {"binning", RADV_PERFTEST_BINNING},
455 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
456 {NULL, 0}
457 };
458
459 const char *
460 radv_get_perftest_option_name(int id)
461 {
462 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
463 return radv_perftest_options[id].string;
464 }
465
466 static void
467 radv_handle_per_app_options(struct radv_instance *instance,
468 const VkApplicationInfo *info)
469 {
470 const char *name = info ? info->pApplicationName : NULL;
471
472 if (!name)
473 return;
474
475 if (!strcmp(name, "Talos - Linux - 32bit") ||
476 !strcmp(name, "Talos - Linux - 64bit")) {
477 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
478 /* Force enable LLVM sisched for Talos because it looks
479 * safe and it gives few more FPS.
480 */
481 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
482 }
483 }
484 }
485
486 static int radv_get_instance_extension_index(const char *name)
487 {
488 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
489 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
490 return i;
491 }
492 return -1;
493 }
494
495
496 VkResult radv_CreateInstance(
497 const VkInstanceCreateInfo* pCreateInfo,
498 const VkAllocationCallbacks* pAllocator,
499 VkInstance* pInstance)
500 {
501 struct radv_instance *instance;
502 VkResult result;
503
504 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
505
506 uint32_t client_version;
507 if (pCreateInfo->pApplicationInfo &&
508 pCreateInfo->pApplicationInfo->apiVersion != 0) {
509 client_version = pCreateInfo->pApplicationInfo->apiVersion;
510 } else {
511 radv_EnumerateInstanceVersion(&client_version);
512 }
513
514 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
515 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
516 if (!instance)
517 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
518
519 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
520
521 if (pAllocator)
522 instance->alloc = *pAllocator;
523 else
524 instance->alloc = default_alloc;
525
526 instance->apiVersion = client_version;
527 instance->physicalDeviceCount = -1;
528
529 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
530 radv_debug_options);
531
532 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
533 radv_perftest_options);
534
535
536 if (instance->debug_flags & RADV_DEBUG_STARTUP)
537 radv_logi("Created an instance");
538
539 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
540 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
541 int index = radv_get_instance_extension_index(ext_name);
542
543 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
544 vk_free2(&default_alloc, pAllocator, instance);
545 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
546 }
547
548 instance->enabled_extensions.extensions[index] = true;
549 }
550
551 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
552 if (result != VK_SUCCESS) {
553 vk_free2(&default_alloc, pAllocator, instance);
554 return vk_error(instance, result);
555 }
556
557 _mesa_locale_init();
558
559 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
560
561 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
562
563 *pInstance = radv_instance_to_handle(instance);
564
565 return VK_SUCCESS;
566 }
567
568 void radv_DestroyInstance(
569 VkInstance _instance,
570 const VkAllocationCallbacks* pAllocator)
571 {
572 RADV_FROM_HANDLE(radv_instance, instance, _instance);
573
574 if (!instance)
575 return;
576
577 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
578 radv_physical_device_finish(instance->physicalDevices + i);
579 }
580
581 VG(VALGRIND_DESTROY_MEMPOOL(instance));
582
583 _mesa_locale_fini();
584
585 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
586
587 vk_free(&instance->alloc, instance);
588 }
589
590 static VkResult
591 radv_enumerate_devices(struct radv_instance *instance)
592 {
593 /* TODO: Check for more devices ? */
594 drmDevicePtr devices[8];
595 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
596 int max_devices;
597
598 instance->physicalDeviceCount = 0;
599
600 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
601
602 if (instance->debug_flags & RADV_DEBUG_STARTUP)
603 radv_logi("Found %d drm nodes", max_devices);
604
605 if (max_devices < 1)
606 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
607
608 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
609 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
610 devices[i]->bustype == DRM_BUS_PCI &&
611 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
612
613 result = radv_physical_device_init(instance->physicalDevices +
614 instance->physicalDeviceCount,
615 instance,
616 devices[i]);
617 if (result == VK_SUCCESS)
618 ++instance->physicalDeviceCount;
619 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
620 break;
621 }
622 }
623 drmFreeDevices(devices, max_devices);
624
625 return result;
626 }
627
628 VkResult radv_EnumeratePhysicalDevices(
629 VkInstance _instance,
630 uint32_t* pPhysicalDeviceCount,
631 VkPhysicalDevice* pPhysicalDevices)
632 {
633 RADV_FROM_HANDLE(radv_instance, instance, _instance);
634 VkResult result;
635
636 if (instance->physicalDeviceCount < 0) {
637 result = radv_enumerate_devices(instance);
638 if (result != VK_SUCCESS &&
639 result != VK_ERROR_INCOMPATIBLE_DRIVER)
640 return result;
641 }
642
643 if (!pPhysicalDevices) {
644 *pPhysicalDeviceCount = instance->physicalDeviceCount;
645 } else {
646 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
647 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
648 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
649 }
650
651 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
652 : VK_SUCCESS;
653 }
654
655 VkResult radv_EnumeratePhysicalDeviceGroups(
656 VkInstance _instance,
657 uint32_t* pPhysicalDeviceGroupCount,
658 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
659 {
660 RADV_FROM_HANDLE(radv_instance, instance, _instance);
661 VkResult result;
662
663 if (instance->physicalDeviceCount < 0) {
664 result = radv_enumerate_devices(instance);
665 if (result != VK_SUCCESS &&
666 result != VK_ERROR_INCOMPATIBLE_DRIVER)
667 return result;
668 }
669
670 if (!pPhysicalDeviceGroupProperties) {
671 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
672 } else {
673 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
674 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
675 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
676 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
677 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
678 }
679 }
680 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
681 : VK_SUCCESS;
682 }
683
684 void radv_GetPhysicalDeviceFeatures(
685 VkPhysicalDevice physicalDevice,
686 VkPhysicalDeviceFeatures* pFeatures)
687 {
688 memset(pFeatures, 0, sizeof(*pFeatures));
689
690 *pFeatures = (VkPhysicalDeviceFeatures) {
691 .robustBufferAccess = true,
692 .fullDrawIndexUint32 = true,
693 .imageCubeArray = true,
694 .independentBlend = true,
695 .geometryShader = true,
696 .tessellationShader = true,
697 .sampleRateShading = true,
698 .dualSrcBlend = true,
699 .logicOp = true,
700 .multiDrawIndirect = true,
701 .drawIndirectFirstInstance = true,
702 .depthClamp = true,
703 .depthBiasClamp = true,
704 .fillModeNonSolid = true,
705 .depthBounds = true,
706 .wideLines = true,
707 .largePoints = true,
708 .alphaToOne = true,
709 .multiViewport = true,
710 .samplerAnisotropy = true,
711 .textureCompressionETC2 = false,
712 .textureCompressionASTC_LDR = false,
713 .textureCompressionBC = true,
714 .occlusionQueryPrecise = true,
715 .pipelineStatisticsQuery = true,
716 .vertexPipelineStoresAndAtomics = true,
717 .fragmentStoresAndAtomics = true,
718 .shaderTessellationAndGeometryPointSize = true,
719 .shaderImageGatherExtended = true,
720 .shaderStorageImageExtendedFormats = true,
721 .shaderStorageImageMultisample = false,
722 .shaderUniformBufferArrayDynamicIndexing = true,
723 .shaderSampledImageArrayDynamicIndexing = true,
724 .shaderStorageBufferArrayDynamicIndexing = true,
725 .shaderStorageImageArrayDynamicIndexing = true,
726 .shaderStorageImageReadWithoutFormat = true,
727 .shaderStorageImageWriteWithoutFormat = true,
728 .shaderClipDistance = true,
729 .shaderCullDistance = true,
730 .shaderFloat64 = true,
731 .shaderInt64 = true,
732 .shaderInt16 = false,
733 .sparseBinding = true,
734 .variableMultisampleRate = true,
735 .inheritedQueries = true,
736 };
737 }
738
739 void radv_GetPhysicalDeviceFeatures2(
740 VkPhysicalDevice physicalDevice,
741 VkPhysicalDeviceFeatures2KHR *pFeatures)
742 {
743 vk_foreach_struct(ext, pFeatures->pNext) {
744 switch (ext->sType) {
745 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
746 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
747 features->variablePointersStorageBuffer = true;
748 features->variablePointers = false;
749 break;
750 }
751 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHR: {
752 VkPhysicalDeviceMultiviewFeaturesKHR *features = (VkPhysicalDeviceMultiviewFeaturesKHR*)ext;
753 features->multiview = true;
754 features->multiviewGeometryShader = true;
755 features->multiviewTessellationShader = true;
756 break;
757 }
758 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
759 VkPhysicalDeviceShaderDrawParameterFeatures *features =
760 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
761 features->shaderDrawParameters = true;
762 break;
763 }
764 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
765 VkPhysicalDeviceProtectedMemoryFeatures *features =
766 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
767 features->protectedMemory = false;
768 break;
769 }
770 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
771 VkPhysicalDevice16BitStorageFeatures *features =
772 (VkPhysicalDevice16BitStorageFeatures*)ext;
773 features->storageBuffer16BitAccess = false;
774 features->uniformAndStorageBuffer16BitAccess = false;
775 features->storagePushConstant16 = false;
776 features->storageInputOutput16 = false;
777 break;
778 }
779 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
780 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
781 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
782 features->samplerYcbcrConversion = false;
783 break;
784 }
785 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
786 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
787 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
788 features->shaderInputAttachmentArrayDynamicIndexing = true;
789 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
790 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
791 features->shaderUniformBufferArrayNonUniformIndexing = false;
792 features->shaderSampledImageArrayNonUniformIndexing = false;
793 features->shaderStorageBufferArrayNonUniformIndexing = false;
794 features->shaderStorageImageArrayNonUniformIndexing = false;
795 features->shaderInputAttachmentArrayNonUniformIndexing = false;
796 features->shaderUniformTexelBufferArrayNonUniformIndexing = false;
797 features->shaderStorageTexelBufferArrayNonUniformIndexing = false;
798 features->descriptorBindingUniformBufferUpdateAfterBind = true;
799 features->descriptorBindingSampledImageUpdateAfterBind = true;
800 features->descriptorBindingStorageImageUpdateAfterBind = true;
801 features->descriptorBindingStorageBufferUpdateAfterBind = true;
802 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
803 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
804 features->descriptorBindingUpdateUnusedWhilePending = true;
805 features->descriptorBindingPartiallyBound = true;
806 features->descriptorBindingVariableDescriptorCount = true;
807 features->runtimeDescriptorArray = true;
808 break;
809 }
810 default:
811 break;
812 }
813 }
814 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
815 }
816
817 void radv_GetPhysicalDeviceProperties(
818 VkPhysicalDevice physicalDevice,
819 VkPhysicalDeviceProperties* pProperties)
820 {
821 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
822 VkSampleCountFlags sample_counts = 0xf;
823
824 /* make sure that the entire descriptor set is addressable with a signed
825 * 32-bit int. So the sum of all limits scaled by descriptor size has to
826 * be at most 2 GiB. the combined image & samples object count as one of
827 * both. This limit is for the pipeline layout, not for the set layout, but
828 * there is no set limit, so we just set a pipeline limit. I don't think
829 * any app is going to hit this soon. */
830 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
831 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
832 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
833 32 /* sampler, largest when combined with image */ +
834 64 /* sampled image */ +
835 64 /* storage image */);
836
837 VkPhysicalDeviceLimits limits = {
838 .maxImageDimension1D = (1 << 14),
839 .maxImageDimension2D = (1 << 14),
840 .maxImageDimension3D = (1 << 11),
841 .maxImageDimensionCube = (1 << 14),
842 .maxImageArrayLayers = (1 << 11),
843 .maxTexelBufferElements = 128 * 1024 * 1024,
844 .maxUniformBufferRange = UINT32_MAX,
845 .maxStorageBufferRange = UINT32_MAX,
846 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
847 .maxMemoryAllocationCount = UINT32_MAX,
848 .maxSamplerAllocationCount = 64 * 1024,
849 .bufferImageGranularity = 64, /* A cache line */
850 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
851 .maxBoundDescriptorSets = MAX_SETS,
852 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
853 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
854 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
855 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
856 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
857 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
858 .maxPerStageResources = max_descriptor_set_size,
859 .maxDescriptorSetSamplers = max_descriptor_set_size,
860 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
861 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
862 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
863 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
864 .maxDescriptorSetSampledImages = max_descriptor_set_size,
865 .maxDescriptorSetStorageImages = max_descriptor_set_size,
866 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
867 .maxVertexInputAttributes = 32,
868 .maxVertexInputBindings = 32,
869 .maxVertexInputAttributeOffset = 2047,
870 .maxVertexInputBindingStride = 2048,
871 .maxVertexOutputComponents = 128,
872 .maxTessellationGenerationLevel = 64,
873 .maxTessellationPatchSize = 32,
874 .maxTessellationControlPerVertexInputComponents = 128,
875 .maxTessellationControlPerVertexOutputComponents = 128,
876 .maxTessellationControlPerPatchOutputComponents = 120,
877 .maxTessellationControlTotalOutputComponents = 4096,
878 .maxTessellationEvaluationInputComponents = 128,
879 .maxTessellationEvaluationOutputComponents = 128,
880 .maxGeometryShaderInvocations = 127,
881 .maxGeometryInputComponents = 64,
882 .maxGeometryOutputComponents = 128,
883 .maxGeometryOutputVertices = 256,
884 .maxGeometryTotalOutputComponents = 1024,
885 .maxFragmentInputComponents = 128,
886 .maxFragmentOutputAttachments = 8,
887 .maxFragmentDualSrcAttachments = 1,
888 .maxFragmentCombinedOutputResources = 8,
889 .maxComputeSharedMemorySize = 32768,
890 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
891 .maxComputeWorkGroupInvocations = 2048,
892 .maxComputeWorkGroupSize = {
893 2048,
894 2048,
895 2048
896 },
897 .subPixelPrecisionBits = 4 /* FIXME */,
898 .subTexelPrecisionBits = 4 /* FIXME */,
899 .mipmapPrecisionBits = 4 /* FIXME */,
900 .maxDrawIndexedIndexValue = UINT32_MAX,
901 .maxDrawIndirectCount = UINT32_MAX,
902 .maxSamplerLodBias = 16,
903 .maxSamplerAnisotropy = 16,
904 .maxViewports = MAX_VIEWPORTS,
905 .maxViewportDimensions = { (1 << 14), (1 << 14) },
906 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
907 .viewportSubPixelBits = 8,
908 .minMemoryMapAlignment = 4096, /* A page */
909 .minTexelBufferOffsetAlignment = 1,
910 .minUniformBufferOffsetAlignment = 4,
911 .minStorageBufferOffsetAlignment = 4,
912 .minTexelOffset = -32,
913 .maxTexelOffset = 31,
914 .minTexelGatherOffset = -32,
915 .maxTexelGatherOffset = 31,
916 .minInterpolationOffset = -2,
917 .maxInterpolationOffset = 2,
918 .subPixelInterpolationOffsetBits = 8,
919 .maxFramebufferWidth = (1 << 14),
920 .maxFramebufferHeight = (1 << 14),
921 .maxFramebufferLayers = (1 << 10),
922 .framebufferColorSampleCounts = sample_counts,
923 .framebufferDepthSampleCounts = sample_counts,
924 .framebufferStencilSampleCounts = sample_counts,
925 .framebufferNoAttachmentsSampleCounts = sample_counts,
926 .maxColorAttachments = MAX_RTS,
927 .sampledImageColorSampleCounts = sample_counts,
928 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
929 .sampledImageDepthSampleCounts = sample_counts,
930 .sampledImageStencilSampleCounts = sample_counts,
931 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
932 .maxSampleMaskWords = 1,
933 .timestampComputeAndGraphics = true,
934 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
935 .maxClipDistances = 8,
936 .maxCullDistances = 8,
937 .maxCombinedClipAndCullDistances = 8,
938 .discreteQueuePriorities = 1,
939 .pointSizeRange = { 0.125, 255.875 },
940 .lineWidthRange = { 0.0, 7.9921875 },
941 .pointSizeGranularity = (1.0 / 8.0),
942 .lineWidthGranularity = (1.0 / 128.0),
943 .strictLines = false, /* FINISHME */
944 .standardSampleLocations = true,
945 .optimalBufferCopyOffsetAlignment = 128,
946 .optimalBufferCopyRowPitchAlignment = 128,
947 .nonCoherentAtomSize = 64,
948 };
949
950 *pProperties = (VkPhysicalDeviceProperties) {
951 .apiVersion = radv_physical_device_api_version(pdevice),
952 .driverVersion = vk_get_driver_version(),
953 .vendorID = ATI_VENDOR_ID,
954 .deviceID = pdevice->rad_info.pci_id,
955 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
956 .limits = limits,
957 .sparseProperties = {0},
958 };
959
960 strcpy(pProperties->deviceName, pdevice->name);
961 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
962 }
963
964 void radv_GetPhysicalDeviceProperties2(
965 VkPhysicalDevice physicalDevice,
966 VkPhysicalDeviceProperties2KHR *pProperties)
967 {
968 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
969 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
970
971 vk_foreach_struct(ext, pProperties->pNext) {
972 switch (ext->sType) {
973 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
974 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
975 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
976 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
977 break;
978 }
979 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
980 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
981 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
982 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
983 properties->deviceLUIDValid = false;
984 break;
985 }
986 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHR: {
987 VkPhysicalDeviceMultiviewPropertiesKHR *properties = (VkPhysicalDeviceMultiviewPropertiesKHR*)ext;
988 properties->maxMultiviewViewCount = MAX_VIEWS;
989 properties->maxMultiviewInstanceIndex = INT_MAX;
990 break;
991 }
992 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
993 VkPhysicalDevicePointClippingPropertiesKHR *properties =
994 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
995 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
996 break;
997 }
998 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
999 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1000 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1001 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1002 break;
1003 }
1004 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1005 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1006 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1007 properties->minImportedHostPointerAlignment = 4096;
1008 break;
1009 }
1010 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1011 VkPhysicalDeviceSubgroupProperties *properties =
1012 (VkPhysicalDeviceSubgroupProperties*)ext;
1013 properties->subgroupSize = 64;
1014 properties->supportedStages = VK_SHADER_STAGE_ALL;
1015 properties->supportedOperations =
1016 VK_SUBGROUP_FEATURE_BASIC_BIT |
1017 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1018 VK_SUBGROUP_FEATURE_QUAD_BIT |
1019 VK_SUBGROUP_FEATURE_VOTE_BIT;
1020 if (pdevice->rad_info.chip_class >= VI) {
1021 properties->supportedOperations |=
1022 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1023 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1024 }
1025 properties->quadOperationsInAllStages = true;
1026 break;
1027 }
1028 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1029 VkPhysicalDeviceMaintenance3Properties *properties =
1030 (VkPhysicalDeviceMaintenance3Properties*)ext;
1031 /* Make sure everything is addressable by a signed 32-bit int, and
1032 * our largest descriptors are 96 bytes. */
1033 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1034 /* Our buffer size fields allow only this much */
1035 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1036 break;
1037 }
1038 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1039 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1040 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1041 /* GFX6-8 only support single channel min/max filter. */
1042 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1043 properties->filterMinmaxSingleComponentFormats = true;
1044 break;
1045 }
1046 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1047 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1048 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1049
1050 /* Shader engines. */
1051 properties->shaderEngineCount =
1052 pdevice->rad_info.max_se;
1053 properties->shaderArraysPerEngineCount =
1054 pdevice->rad_info.max_sh_per_se;
1055 properties->computeUnitsPerShaderArray =
1056 pdevice->rad_info.num_good_compute_units /
1057 (pdevice->rad_info.max_se *
1058 pdevice->rad_info.max_sh_per_se);
1059 properties->simdPerComputeUnit = 4;
1060 properties->wavefrontsPerSimd =
1061 pdevice->rad_info.family == CHIP_TONGA ||
1062 pdevice->rad_info.family == CHIP_ICELAND ||
1063 pdevice->rad_info.family == CHIP_POLARIS10 ||
1064 pdevice->rad_info.family == CHIP_POLARIS11 ||
1065 pdevice->rad_info.family == CHIP_POLARIS12 ||
1066 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1067 properties->wavefrontSize = 64;
1068
1069 /* SGPR. */
1070 properties->sgprsPerSimd =
1071 radv_get_num_physical_sgprs(pdevice);
1072 properties->minSgprAllocation =
1073 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1074 properties->maxSgprAllocation =
1075 pdevice->rad_info.family == CHIP_TONGA ||
1076 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1077 properties->sgprAllocationGranularity =
1078 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1079
1080 /* VGPR. */
1081 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1082 properties->minVgprAllocation = 4;
1083 properties->maxVgprAllocation = 256;
1084 properties->vgprAllocationGranularity = 4;
1085 break;
1086 }
1087 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1088 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1089 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1090 properties->maxVertexAttribDivisor = UINT32_MAX;
1091 break;
1092 }
1093 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1094 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1095 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1096 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1097 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1098 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1099 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1100 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1101 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1102 properties->robustBufferAccessUpdateAfterBind = false;
1103 properties->quadDivergentImplicitLod = false;
1104
1105 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1106 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1107 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1108 32 /* sampler, largest when combined with image */ +
1109 64 /* sampled image */ +
1110 64 /* storage image */);
1111 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1112 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1113 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1114 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1115 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1116 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1117 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1118 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1119 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1120 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1121 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1122 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1123 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1124 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1125 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1126 break;
1127 }
1128 default:
1129 break;
1130 }
1131 }
1132 }
1133
1134 static void radv_get_physical_device_queue_family_properties(
1135 struct radv_physical_device* pdevice,
1136 uint32_t* pCount,
1137 VkQueueFamilyProperties** pQueueFamilyProperties)
1138 {
1139 int num_queue_families = 1;
1140 int idx;
1141 if (pdevice->rad_info.num_compute_rings > 0 &&
1142 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1143 num_queue_families++;
1144
1145 if (pQueueFamilyProperties == NULL) {
1146 *pCount = num_queue_families;
1147 return;
1148 }
1149
1150 if (!*pCount)
1151 return;
1152
1153 idx = 0;
1154 if (*pCount >= 1) {
1155 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1156 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1157 VK_QUEUE_COMPUTE_BIT |
1158 VK_QUEUE_TRANSFER_BIT |
1159 VK_QUEUE_SPARSE_BINDING_BIT,
1160 .queueCount = 1,
1161 .timestampValidBits = 64,
1162 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1163 };
1164 idx++;
1165 }
1166
1167 if (pdevice->rad_info.num_compute_rings > 0 &&
1168 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1169 if (*pCount > idx) {
1170 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1171 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1172 VK_QUEUE_TRANSFER_BIT |
1173 VK_QUEUE_SPARSE_BINDING_BIT,
1174 .queueCount = pdevice->rad_info.num_compute_rings,
1175 .timestampValidBits = 64,
1176 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1177 };
1178 idx++;
1179 }
1180 }
1181 *pCount = idx;
1182 }
1183
1184 void radv_GetPhysicalDeviceQueueFamilyProperties(
1185 VkPhysicalDevice physicalDevice,
1186 uint32_t* pCount,
1187 VkQueueFamilyProperties* pQueueFamilyProperties)
1188 {
1189 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1190 if (!pQueueFamilyProperties) {
1191 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1192 return;
1193 }
1194 VkQueueFamilyProperties *properties[] = {
1195 pQueueFamilyProperties + 0,
1196 pQueueFamilyProperties + 1,
1197 pQueueFamilyProperties + 2,
1198 };
1199 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1200 assert(*pCount <= 3);
1201 }
1202
1203 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1204 VkPhysicalDevice physicalDevice,
1205 uint32_t* pCount,
1206 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
1207 {
1208 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1209 if (!pQueueFamilyProperties) {
1210 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1211 return;
1212 }
1213 VkQueueFamilyProperties *properties[] = {
1214 &pQueueFamilyProperties[0].queueFamilyProperties,
1215 &pQueueFamilyProperties[1].queueFamilyProperties,
1216 &pQueueFamilyProperties[2].queueFamilyProperties,
1217 };
1218 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1219 assert(*pCount <= 3);
1220 }
1221
1222 void radv_GetPhysicalDeviceMemoryProperties(
1223 VkPhysicalDevice physicalDevice,
1224 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1225 {
1226 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1227
1228 *pMemoryProperties = physical_device->memory_properties;
1229 }
1230
1231 void radv_GetPhysicalDeviceMemoryProperties2(
1232 VkPhysicalDevice physicalDevice,
1233 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
1234 {
1235 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1236 &pMemoryProperties->memoryProperties);
1237 }
1238
1239 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1240 VkDevice _device,
1241 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
1242 const void *pHostPointer,
1243 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1244 {
1245 RADV_FROM_HANDLE(radv_device, device, _device);
1246
1247 switch (handleType)
1248 {
1249 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1250 const struct radv_physical_device *physical_device = device->physical_device;
1251 uint32_t memoryTypeBits = 0;
1252 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1253 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1254 memoryTypeBits = (1 << i);
1255 break;
1256 }
1257 }
1258 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1259 return VK_SUCCESS;
1260 }
1261 default:
1262 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
1263 }
1264 }
1265
1266 static enum radeon_ctx_priority
1267 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1268 {
1269 /* Default to MEDIUM when a specific global priority isn't requested */
1270 if (!pObj)
1271 return RADEON_CTX_PRIORITY_MEDIUM;
1272
1273 switch(pObj->globalPriority) {
1274 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1275 return RADEON_CTX_PRIORITY_REALTIME;
1276 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1277 return RADEON_CTX_PRIORITY_HIGH;
1278 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1279 return RADEON_CTX_PRIORITY_MEDIUM;
1280 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1281 return RADEON_CTX_PRIORITY_LOW;
1282 default:
1283 unreachable("Illegal global priority value");
1284 return RADEON_CTX_PRIORITY_INVALID;
1285 }
1286 }
1287
1288 static int
1289 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1290 uint32_t queue_family_index, int idx,
1291 VkDeviceQueueCreateFlags flags,
1292 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1293 {
1294 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1295 queue->device = device;
1296 queue->queue_family_index = queue_family_index;
1297 queue->queue_idx = idx;
1298 queue->priority = radv_get_queue_global_priority(global_priority);
1299 queue->flags = flags;
1300
1301 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1302 if (!queue->hw_ctx)
1303 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1304
1305 return VK_SUCCESS;
1306 }
1307
1308 static void
1309 radv_queue_finish(struct radv_queue *queue)
1310 {
1311 if (queue->hw_ctx)
1312 queue->device->ws->ctx_destroy(queue->hw_ctx);
1313
1314 if (queue->initial_full_flush_preamble_cs)
1315 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1316 if (queue->initial_preamble_cs)
1317 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1318 if (queue->continue_preamble_cs)
1319 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1320 if (queue->descriptor_bo)
1321 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1322 if (queue->scratch_bo)
1323 queue->device->ws->buffer_destroy(queue->scratch_bo);
1324 if (queue->esgs_ring_bo)
1325 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1326 if (queue->gsvs_ring_bo)
1327 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1328 if (queue->tess_rings_bo)
1329 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1330 if (queue->compute_scratch_bo)
1331 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1332 }
1333
1334 static void
1335 radv_bo_list_init(struct radv_bo_list *bo_list)
1336 {
1337 pthread_mutex_init(&bo_list->mutex, NULL);
1338 bo_list->list.count = bo_list->capacity = 0;
1339 bo_list->list.bos = NULL;
1340 }
1341
1342 static void
1343 radv_bo_list_finish(struct radv_bo_list *bo_list)
1344 {
1345 free(bo_list->list.bos);
1346 pthread_mutex_destroy(&bo_list->mutex);
1347 }
1348
1349 static VkResult radv_bo_list_add(struct radv_device *device,
1350 struct radeon_winsys_bo *bo)
1351 {
1352 struct radv_bo_list *bo_list = &device->bo_list;
1353
1354 if (unlikely(!device->use_global_bo_list))
1355 return VK_SUCCESS;
1356
1357 pthread_mutex_lock(&bo_list->mutex);
1358 if (bo_list->list.count == bo_list->capacity) {
1359 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1360 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1361
1362 if (!data) {
1363 pthread_mutex_unlock(&bo_list->mutex);
1364 return VK_ERROR_OUT_OF_HOST_MEMORY;
1365 }
1366
1367 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1368 bo_list->capacity = capacity;
1369 }
1370
1371 bo_list->list.bos[bo_list->list.count++] = bo;
1372 pthread_mutex_unlock(&bo_list->mutex);
1373 return VK_SUCCESS;
1374 }
1375
1376 static void radv_bo_list_remove(struct radv_device *device,
1377 struct radeon_winsys_bo *bo)
1378 {
1379 struct radv_bo_list *bo_list = &device->bo_list;
1380
1381 if (unlikely(!device->use_global_bo_list))
1382 return;
1383
1384 pthread_mutex_lock(&bo_list->mutex);
1385 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1386 if (bo_list->list.bos[i] == bo) {
1387 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1388 --bo_list->list.count;
1389 break;
1390 }
1391 }
1392 pthread_mutex_unlock(&bo_list->mutex);
1393 }
1394
1395 static void
1396 radv_device_init_gs_info(struct radv_device *device)
1397 {
1398 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1399 device->physical_device->rad_info.family);
1400 }
1401
1402 static int radv_get_device_extension_index(const char *name)
1403 {
1404 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1405 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1406 return i;
1407 }
1408 return -1;
1409 }
1410
1411 VkResult radv_CreateDevice(
1412 VkPhysicalDevice physicalDevice,
1413 const VkDeviceCreateInfo* pCreateInfo,
1414 const VkAllocationCallbacks* pAllocator,
1415 VkDevice* pDevice)
1416 {
1417 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1418 VkResult result;
1419 struct radv_device *device;
1420
1421 bool keep_shader_info = false;
1422
1423 /* Check enabled features */
1424 if (pCreateInfo->pEnabledFeatures) {
1425 VkPhysicalDeviceFeatures supported_features;
1426 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1427 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1428 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1429 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1430 for (uint32_t i = 0; i < num_features; i++) {
1431 if (enabled_feature[i] && !supported_feature[i])
1432 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1433 }
1434 }
1435
1436 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1437 sizeof(*device), 8,
1438 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1439 if (!device)
1440 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1441
1442 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1443 device->instance = physical_device->instance;
1444 device->physical_device = physical_device;
1445
1446 device->ws = physical_device->ws;
1447 if (pAllocator)
1448 device->alloc = *pAllocator;
1449 else
1450 device->alloc = physical_device->instance->alloc;
1451
1452 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1453 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1454 int index = radv_get_device_extension_index(ext_name);
1455 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1456 vk_free(&device->alloc, device);
1457 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1458 }
1459
1460 device->enabled_extensions.extensions[index] = true;
1461 }
1462
1463 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1464
1465 /* With update after bind we can't attach bo's to the command buffer
1466 * from the descriptor set anymore, so we have to use a global BO list.
1467 */
1468 device->use_global_bo_list =
1469 device->enabled_extensions.EXT_descriptor_indexing;
1470
1471 mtx_init(&device->shader_slab_mutex, mtx_plain);
1472 list_inithead(&device->shader_slabs);
1473
1474 radv_bo_list_init(&device->bo_list);
1475
1476 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1477 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1478 uint32_t qfi = queue_create->queueFamilyIndex;
1479 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1480 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1481
1482 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1483
1484 device->queues[qfi] = vk_alloc(&device->alloc,
1485 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1486 if (!device->queues[qfi]) {
1487 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1488 goto fail;
1489 }
1490
1491 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1492
1493 device->queue_count[qfi] = queue_create->queueCount;
1494
1495 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1496 result = radv_queue_init(device, &device->queues[qfi][q],
1497 qfi, q, queue_create->flags,
1498 global_priority);
1499 if (result != VK_SUCCESS)
1500 goto fail;
1501 }
1502 }
1503
1504 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1505 (device->instance->perftest_flags & RADV_PERFTEST_BINNING);
1506
1507 /* Disabled and not implemented for now. */
1508 device->dfsm_allowed = device->pbb_allowed && false;
1509
1510 #ifdef ANDROID
1511 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1512 #endif
1513
1514 /* The maximum number of scratch waves. Scratch space isn't divided
1515 * evenly between CUs. The number is only a function of the number of CUs.
1516 * We can decrease the constant to decrease the scratch buffer size.
1517 *
1518 * sctx->scratch_waves must be >= the maximum possible size of
1519 * 1 threadgroup, so that the hw doesn't hang from being unable
1520 * to start any.
1521 *
1522 * The recommended value is 4 per CU at most. Higher numbers don't
1523 * bring much benefit, but they still occupy chip resources (think
1524 * async compute). I've seen ~2% performance difference between 4 and 32.
1525 */
1526 uint32_t max_threads_per_block = 2048;
1527 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1528 max_threads_per_block / 64);
1529
1530 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1531
1532 if (device->physical_device->rad_info.chip_class >= CIK) {
1533 /* If the KMD allows it (there is a KMD hw register for it),
1534 * allow launching waves out-of-order.
1535 */
1536 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1537 }
1538
1539 radv_device_init_gs_info(device);
1540
1541 device->tess_offchip_block_dw_size =
1542 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1543 device->has_distributed_tess =
1544 device->physical_device->rad_info.chip_class >= VI &&
1545 device->physical_device->rad_info.max_se >= 2;
1546
1547 if (getenv("RADV_TRACE_FILE")) {
1548 const char *filename = getenv("RADV_TRACE_FILE");
1549
1550 keep_shader_info = true;
1551
1552 if (!radv_init_trace(device))
1553 goto fail;
1554
1555 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1556 radv_dump_enabled_options(device, stderr);
1557 }
1558
1559 device->keep_shader_info = keep_shader_info;
1560
1561 result = radv_device_init_meta(device);
1562 if (result != VK_SUCCESS)
1563 goto fail;
1564
1565 radv_device_init_msaa(device);
1566
1567 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1568 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1569 switch (family) {
1570 case RADV_QUEUE_GENERAL:
1571 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1572 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1573 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1574 break;
1575 case RADV_QUEUE_COMPUTE:
1576 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1577 radeon_emit(device->empty_cs[family], 0);
1578 break;
1579 }
1580 device->ws->cs_finalize(device->empty_cs[family]);
1581 }
1582
1583 if (device->physical_device->rad_info.chip_class >= CIK)
1584 cik_create_gfx_config(device);
1585
1586 VkPipelineCacheCreateInfo ci;
1587 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1588 ci.pNext = NULL;
1589 ci.flags = 0;
1590 ci.pInitialData = NULL;
1591 ci.initialDataSize = 0;
1592 VkPipelineCache pc;
1593 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1594 &ci, NULL, &pc);
1595 if (result != VK_SUCCESS)
1596 goto fail_meta;
1597
1598 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1599
1600 *pDevice = radv_device_to_handle(device);
1601 return VK_SUCCESS;
1602
1603 fail_meta:
1604 radv_device_finish_meta(device);
1605 fail:
1606 radv_bo_list_finish(&device->bo_list);
1607
1608 if (device->trace_bo)
1609 device->ws->buffer_destroy(device->trace_bo);
1610
1611 if (device->gfx_init)
1612 device->ws->buffer_destroy(device->gfx_init);
1613
1614 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1615 for (unsigned q = 0; q < device->queue_count[i]; q++)
1616 radv_queue_finish(&device->queues[i][q]);
1617 if (device->queue_count[i])
1618 vk_free(&device->alloc, device->queues[i]);
1619 }
1620
1621 vk_free(&device->alloc, device);
1622 return result;
1623 }
1624
1625 void radv_DestroyDevice(
1626 VkDevice _device,
1627 const VkAllocationCallbacks* pAllocator)
1628 {
1629 RADV_FROM_HANDLE(radv_device, device, _device);
1630
1631 if (!device)
1632 return;
1633
1634 if (device->trace_bo)
1635 device->ws->buffer_destroy(device->trace_bo);
1636
1637 if (device->gfx_init)
1638 device->ws->buffer_destroy(device->gfx_init);
1639
1640 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1641 for (unsigned q = 0; q < device->queue_count[i]; q++)
1642 radv_queue_finish(&device->queues[i][q]);
1643 if (device->queue_count[i])
1644 vk_free(&device->alloc, device->queues[i]);
1645 if (device->empty_cs[i])
1646 device->ws->cs_destroy(device->empty_cs[i]);
1647 }
1648 radv_device_finish_meta(device);
1649
1650 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1651 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1652
1653 radv_destroy_shader_slabs(device);
1654
1655 radv_bo_list_finish(&device->bo_list);
1656 vk_free(&device->alloc, device);
1657 }
1658
1659 VkResult radv_EnumerateInstanceLayerProperties(
1660 uint32_t* pPropertyCount,
1661 VkLayerProperties* pProperties)
1662 {
1663 if (pProperties == NULL) {
1664 *pPropertyCount = 0;
1665 return VK_SUCCESS;
1666 }
1667
1668 /* None supported at this time */
1669 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1670 }
1671
1672 VkResult radv_EnumerateDeviceLayerProperties(
1673 VkPhysicalDevice physicalDevice,
1674 uint32_t* pPropertyCount,
1675 VkLayerProperties* pProperties)
1676 {
1677 if (pProperties == NULL) {
1678 *pPropertyCount = 0;
1679 return VK_SUCCESS;
1680 }
1681
1682 /* None supported at this time */
1683 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1684 }
1685
1686 void radv_GetDeviceQueue2(
1687 VkDevice _device,
1688 const VkDeviceQueueInfo2* pQueueInfo,
1689 VkQueue* pQueue)
1690 {
1691 RADV_FROM_HANDLE(radv_device, device, _device);
1692 struct radv_queue *queue;
1693
1694 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
1695 if (pQueueInfo->flags != queue->flags) {
1696 /* From the Vulkan 1.1.70 spec:
1697 *
1698 * "The queue returned by vkGetDeviceQueue2 must have the same
1699 * flags value from this structure as that used at device
1700 * creation time in a VkDeviceQueueCreateInfo instance. If no
1701 * matching flags were specified at device creation time then
1702 * pQueue will return VK_NULL_HANDLE."
1703 */
1704 *pQueue = VK_NULL_HANDLE;
1705 return;
1706 }
1707
1708 *pQueue = radv_queue_to_handle(queue);
1709 }
1710
1711 void radv_GetDeviceQueue(
1712 VkDevice _device,
1713 uint32_t queueFamilyIndex,
1714 uint32_t queueIndex,
1715 VkQueue* pQueue)
1716 {
1717 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
1718 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
1719 .queueFamilyIndex = queueFamilyIndex,
1720 .queueIndex = queueIndex
1721 };
1722
1723 radv_GetDeviceQueue2(_device, &info, pQueue);
1724 }
1725
1726 static void
1727 fill_geom_tess_rings(struct radv_queue *queue,
1728 uint32_t *map,
1729 bool add_sample_positions,
1730 uint32_t esgs_ring_size,
1731 struct radeon_winsys_bo *esgs_ring_bo,
1732 uint32_t gsvs_ring_size,
1733 struct radeon_winsys_bo *gsvs_ring_bo,
1734 uint32_t tess_factor_ring_size,
1735 uint32_t tess_offchip_ring_offset,
1736 uint32_t tess_offchip_ring_size,
1737 struct radeon_winsys_bo *tess_rings_bo)
1738 {
1739 uint64_t esgs_va = 0, gsvs_va = 0;
1740 uint64_t tess_va = 0, tess_offchip_va = 0;
1741 uint32_t *desc = &map[4];
1742
1743 if (esgs_ring_bo)
1744 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1745 if (gsvs_ring_bo)
1746 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1747 if (tess_rings_bo) {
1748 tess_va = radv_buffer_get_va(tess_rings_bo);
1749 tess_offchip_va = tess_va + tess_offchip_ring_offset;
1750 }
1751
1752 /* stride 0, num records - size, add tid, swizzle, elsize4,
1753 index stride 64 */
1754 desc[0] = esgs_va;
1755 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1756 S_008F04_STRIDE(0) |
1757 S_008F04_SWIZZLE_ENABLE(true);
1758 desc[2] = esgs_ring_size;
1759 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1760 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1761 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1762 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1763 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1764 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1765 S_008F0C_ELEMENT_SIZE(1) |
1766 S_008F0C_INDEX_STRIDE(3) |
1767 S_008F0C_ADD_TID_ENABLE(true);
1768
1769 desc += 4;
1770 /* GS entry for ES->GS ring */
1771 /* stride 0, num records - size, elsize0,
1772 index stride 0 */
1773 desc[0] = esgs_va;
1774 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1775 S_008F04_STRIDE(0) |
1776 S_008F04_SWIZZLE_ENABLE(false);
1777 desc[2] = esgs_ring_size;
1778 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1779 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1780 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1781 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1782 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1783 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1784 S_008F0C_ELEMENT_SIZE(0) |
1785 S_008F0C_INDEX_STRIDE(0) |
1786 S_008F0C_ADD_TID_ENABLE(false);
1787
1788 desc += 4;
1789 /* VS entry for GS->VS ring */
1790 /* stride 0, num records - size, elsize0,
1791 index stride 0 */
1792 desc[0] = gsvs_va;
1793 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1794 S_008F04_STRIDE(0) |
1795 S_008F04_SWIZZLE_ENABLE(false);
1796 desc[2] = gsvs_ring_size;
1797 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1798 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1799 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1800 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1801 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1802 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1803 S_008F0C_ELEMENT_SIZE(0) |
1804 S_008F0C_INDEX_STRIDE(0) |
1805 S_008F0C_ADD_TID_ENABLE(false);
1806 desc += 4;
1807
1808 /* stride gsvs_itemsize, num records 64
1809 elsize 4, index stride 16 */
1810 /* shader will patch stride and desc[2] */
1811 desc[0] = gsvs_va;
1812 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1813 S_008F04_STRIDE(0) |
1814 S_008F04_SWIZZLE_ENABLE(true);
1815 desc[2] = 0;
1816 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1817 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1818 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1819 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1820 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1821 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1822 S_008F0C_ELEMENT_SIZE(1) |
1823 S_008F0C_INDEX_STRIDE(1) |
1824 S_008F0C_ADD_TID_ENABLE(true);
1825 desc += 4;
1826
1827 desc[0] = tess_va;
1828 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
1829 S_008F04_STRIDE(0) |
1830 S_008F04_SWIZZLE_ENABLE(false);
1831 desc[2] = tess_factor_ring_size;
1832 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1833 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1834 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1835 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1836 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1837 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1838 S_008F0C_ELEMENT_SIZE(0) |
1839 S_008F0C_INDEX_STRIDE(0) |
1840 S_008F0C_ADD_TID_ENABLE(false);
1841 desc += 4;
1842
1843 desc[0] = tess_offchip_va;
1844 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1845 S_008F04_STRIDE(0) |
1846 S_008F04_SWIZZLE_ENABLE(false);
1847 desc[2] = tess_offchip_ring_size;
1848 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1849 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1850 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1851 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1852 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1853 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1854 S_008F0C_ELEMENT_SIZE(0) |
1855 S_008F0C_INDEX_STRIDE(0) |
1856 S_008F0C_ADD_TID_ENABLE(false);
1857 desc += 4;
1858
1859 /* add sample positions after all rings */
1860 memcpy(desc, queue->device->sample_locations_1x, 8);
1861 desc += 2;
1862 memcpy(desc, queue->device->sample_locations_2x, 16);
1863 desc += 4;
1864 memcpy(desc, queue->device->sample_locations_4x, 32);
1865 desc += 8;
1866 memcpy(desc, queue->device->sample_locations_8x, 64);
1867 desc += 16;
1868 memcpy(desc, queue->device->sample_locations_16x, 128);
1869 }
1870
1871 static unsigned
1872 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1873 {
1874 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1875 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1876 device->physical_device->rad_info.family != CHIP_STONEY;
1877 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1878 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1879 device->physical_device->rad_info.max_se;
1880 unsigned offchip_granularity;
1881 unsigned hs_offchip_param;
1882 switch (device->tess_offchip_block_dw_size) {
1883 default:
1884 assert(0);
1885 /* fall through */
1886 case 8192:
1887 offchip_granularity = V_03093C_X_8K_DWORDS;
1888 break;
1889 case 4096:
1890 offchip_granularity = V_03093C_X_4K_DWORDS;
1891 break;
1892 }
1893
1894 switch (device->physical_device->rad_info.chip_class) {
1895 case SI:
1896 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1897 break;
1898 case CIK:
1899 case VI:
1900 case GFX9:
1901 default:
1902 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1903 break;
1904 }
1905
1906 *max_offchip_buffers_p = max_offchip_buffers;
1907 if (device->physical_device->rad_info.chip_class >= CIK) {
1908 if (device->physical_device->rad_info.chip_class >= VI)
1909 --max_offchip_buffers;
1910 hs_offchip_param =
1911 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1912 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1913 } else {
1914 hs_offchip_param =
1915 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1916 }
1917 return hs_offchip_param;
1918 }
1919
1920 static void
1921 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
1922 struct radeon_winsys_bo *esgs_ring_bo,
1923 uint32_t esgs_ring_size,
1924 struct radeon_winsys_bo *gsvs_ring_bo,
1925 uint32_t gsvs_ring_size)
1926 {
1927 if (!esgs_ring_bo && !gsvs_ring_bo)
1928 return;
1929
1930 if (esgs_ring_bo)
1931 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo, 8);
1932
1933 if (gsvs_ring_bo)
1934 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo, 8);
1935
1936 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1937 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1938 radeon_emit(cs, esgs_ring_size >> 8);
1939 radeon_emit(cs, gsvs_ring_size >> 8);
1940 } else {
1941 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1942 radeon_emit(cs, esgs_ring_size >> 8);
1943 radeon_emit(cs, gsvs_ring_size >> 8);
1944 }
1945 }
1946
1947 static void
1948 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
1949 unsigned hs_offchip_param, unsigned tf_ring_size,
1950 struct radeon_winsys_bo *tess_rings_bo)
1951 {
1952 uint64_t tf_va;
1953
1954 if (!tess_rings_bo)
1955 return;
1956
1957 tf_va = radv_buffer_get_va(tess_rings_bo);
1958
1959 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo, 8);
1960
1961 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1962 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1963 S_030938_SIZE(tf_ring_size / 4));
1964 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1965 tf_va >> 8);
1966 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1967 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1968 S_030944_BASE_HI(tf_va >> 40));
1969 }
1970 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
1971 hs_offchip_param);
1972 } else {
1973 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1974 S_008988_SIZE(tf_ring_size / 4));
1975 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1976 tf_va >> 8);
1977 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1978 hs_offchip_param);
1979 }
1980 }
1981
1982 static void
1983 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
1984 struct radeon_winsys_bo *compute_scratch_bo)
1985 {
1986 uint64_t scratch_va;
1987
1988 if (!compute_scratch_bo)
1989 return;
1990
1991 scratch_va = radv_buffer_get_va(compute_scratch_bo);
1992
1993 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo, 8);
1994
1995 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1996 radeon_emit(cs, scratch_va);
1997 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1998 S_008F04_SWIZZLE_ENABLE(1));
1999 }
2000
2001 static void
2002 radv_emit_global_shader_pointers(struct radv_queue *queue,
2003 struct radeon_cmdbuf *cs,
2004 struct radeon_winsys_bo *descriptor_bo)
2005 {
2006 uint64_t va;
2007
2008 if (!descriptor_bo)
2009 return;
2010
2011 va = radv_buffer_get_va(descriptor_bo);
2012
2013 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo, 8);
2014
2015 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2016 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2017 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2018 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2019 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2020
2021 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2022 radv_emit_shader_pointer(queue->device, cs, regs[i],
2023 va, true);
2024 }
2025 } else {
2026 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2027 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2028 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2029 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2030 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2031 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2032
2033 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2034 radv_emit_shader_pointer(queue->device, cs, regs[i],
2035 va, true);
2036 }
2037 }
2038 }
2039
2040 static VkResult
2041 radv_get_preamble_cs(struct radv_queue *queue,
2042 uint32_t scratch_size,
2043 uint32_t compute_scratch_size,
2044 uint32_t esgs_ring_size,
2045 uint32_t gsvs_ring_size,
2046 bool needs_tess_rings,
2047 bool needs_sample_positions,
2048 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2049 struct radeon_cmdbuf **initial_preamble_cs,
2050 struct radeon_cmdbuf **continue_preamble_cs)
2051 {
2052 struct radeon_winsys_bo *scratch_bo = NULL;
2053 struct radeon_winsys_bo *descriptor_bo = NULL;
2054 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2055 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2056 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2057 struct radeon_winsys_bo *tess_rings_bo = NULL;
2058 struct radeon_cmdbuf *dest_cs[3] = {0};
2059 bool add_tess_rings = false, add_sample_positions = false;
2060 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2061 unsigned max_offchip_buffers;
2062 unsigned hs_offchip_param = 0;
2063 unsigned tess_offchip_ring_offset;
2064 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2065 if (!queue->has_tess_rings) {
2066 if (needs_tess_rings)
2067 add_tess_rings = true;
2068 }
2069 if (!queue->has_sample_positions) {
2070 if (needs_sample_positions)
2071 add_sample_positions = true;
2072 }
2073 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2074 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2075 &max_offchip_buffers);
2076 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2077 tess_offchip_ring_size = max_offchip_buffers *
2078 queue->device->tess_offchip_block_dw_size * 4;
2079
2080 if (scratch_size <= queue->scratch_size &&
2081 compute_scratch_size <= queue->compute_scratch_size &&
2082 esgs_ring_size <= queue->esgs_ring_size &&
2083 gsvs_ring_size <= queue->gsvs_ring_size &&
2084 !add_tess_rings && !add_sample_positions &&
2085 queue->initial_preamble_cs) {
2086 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2087 *initial_preamble_cs = queue->initial_preamble_cs;
2088 *continue_preamble_cs = queue->continue_preamble_cs;
2089 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2090 *continue_preamble_cs = NULL;
2091 return VK_SUCCESS;
2092 }
2093
2094 if (scratch_size > queue->scratch_size) {
2095 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2096 scratch_size,
2097 4096,
2098 RADEON_DOMAIN_VRAM,
2099 ring_bo_flags);
2100 if (!scratch_bo)
2101 goto fail;
2102 } else
2103 scratch_bo = queue->scratch_bo;
2104
2105 if (compute_scratch_size > queue->compute_scratch_size) {
2106 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2107 compute_scratch_size,
2108 4096,
2109 RADEON_DOMAIN_VRAM,
2110 ring_bo_flags);
2111 if (!compute_scratch_bo)
2112 goto fail;
2113
2114 } else
2115 compute_scratch_bo = queue->compute_scratch_bo;
2116
2117 if (esgs_ring_size > queue->esgs_ring_size) {
2118 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2119 esgs_ring_size,
2120 4096,
2121 RADEON_DOMAIN_VRAM,
2122 ring_bo_flags);
2123 if (!esgs_ring_bo)
2124 goto fail;
2125 } else {
2126 esgs_ring_bo = queue->esgs_ring_bo;
2127 esgs_ring_size = queue->esgs_ring_size;
2128 }
2129
2130 if (gsvs_ring_size > queue->gsvs_ring_size) {
2131 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2132 gsvs_ring_size,
2133 4096,
2134 RADEON_DOMAIN_VRAM,
2135 ring_bo_flags);
2136 if (!gsvs_ring_bo)
2137 goto fail;
2138 } else {
2139 gsvs_ring_bo = queue->gsvs_ring_bo;
2140 gsvs_ring_size = queue->gsvs_ring_size;
2141 }
2142
2143 if (add_tess_rings) {
2144 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2145 tess_offchip_ring_offset + tess_offchip_ring_size,
2146 256,
2147 RADEON_DOMAIN_VRAM,
2148 ring_bo_flags);
2149 if (!tess_rings_bo)
2150 goto fail;
2151 } else {
2152 tess_rings_bo = queue->tess_rings_bo;
2153 }
2154
2155 if (scratch_bo != queue->scratch_bo ||
2156 esgs_ring_bo != queue->esgs_ring_bo ||
2157 gsvs_ring_bo != queue->gsvs_ring_bo ||
2158 tess_rings_bo != queue->tess_rings_bo ||
2159 add_sample_positions) {
2160 uint32_t size = 0;
2161 if (gsvs_ring_bo || esgs_ring_bo ||
2162 tess_rings_bo || add_sample_positions) {
2163 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2164 if (add_sample_positions)
2165 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
2166 }
2167 else if (scratch_bo)
2168 size = 8; /* 2 dword */
2169
2170 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2171 size,
2172 4096,
2173 RADEON_DOMAIN_VRAM,
2174 RADEON_FLAG_CPU_ACCESS |
2175 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2176 RADEON_FLAG_READ_ONLY);
2177 if (!descriptor_bo)
2178 goto fail;
2179 } else
2180 descriptor_bo = queue->descriptor_bo;
2181
2182 for(int i = 0; i < 3; ++i) {
2183 struct radeon_cmdbuf *cs = NULL;
2184 cs = queue->device->ws->cs_create(queue->device->ws,
2185 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2186 if (!cs)
2187 goto fail;
2188
2189 dest_cs[i] = cs;
2190
2191 if (scratch_bo)
2192 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo, 8);
2193
2194 if (descriptor_bo != queue->descriptor_bo) {
2195 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2196
2197 if (scratch_bo) {
2198 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2199 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2200 S_008F04_SWIZZLE_ENABLE(1);
2201 map[0] = scratch_va;
2202 map[1] = rsrc1;
2203 }
2204
2205 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo ||
2206 add_sample_positions)
2207 fill_geom_tess_rings(queue, map, add_sample_positions,
2208 esgs_ring_size, esgs_ring_bo,
2209 gsvs_ring_size, gsvs_ring_bo,
2210 tess_factor_ring_size,
2211 tess_offchip_ring_offset,
2212 tess_offchip_ring_size,
2213 tess_rings_bo);
2214
2215 queue->device->ws->buffer_unmap(descriptor_bo);
2216 }
2217
2218 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2219 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2220 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2221 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2222 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2223 }
2224
2225 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2226 gsvs_ring_bo, gsvs_ring_size);
2227 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2228 tess_factor_ring_size, tess_rings_bo);
2229 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2230 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2231
2232 if (i == 0) {
2233 si_cs_emit_cache_flush(cs,
2234 queue->device->physical_device->rad_info.chip_class,
2235 NULL, 0,
2236 queue->queue_family_index == RING_COMPUTE &&
2237 queue->device->physical_device->rad_info.chip_class >= CIK,
2238 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2239 RADV_CMD_FLAG_INV_ICACHE |
2240 RADV_CMD_FLAG_INV_SMEM_L1 |
2241 RADV_CMD_FLAG_INV_VMEM_L1 |
2242 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2243 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2244 } else if (i == 1) {
2245 si_cs_emit_cache_flush(cs,
2246 queue->device->physical_device->rad_info.chip_class,
2247 NULL, 0,
2248 queue->queue_family_index == RING_COMPUTE &&
2249 queue->device->physical_device->rad_info.chip_class >= CIK,
2250 RADV_CMD_FLAG_INV_ICACHE |
2251 RADV_CMD_FLAG_INV_SMEM_L1 |
2252 RADV_CMD_FLAG_INV_VMEM_L1 |
2253 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2254 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2255 }
2256
2257 if (!queue->device->ws->cs_finalize(cs))
2258 goto fail;
2259 }
2260
2261 if (queue->initial_full_flush_preamble_cs)
2262 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2263
2264 if (queue->initial_preamble_cs)
2265 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2266
2267 if (queue->continue_preamble_cs)
2268 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2269
2270 queue->initial_full_flush_preamble_cs = dest_cs[0];
2271 queue->initial_preamble_cs = dest_cs[1];
2272 queue->continue_preamble_cs = dest_cs[2];
2273
2274 if (scratch_bo != queue->scratch_bo) {
2275 if (queue->scratch_bo)
2276 queue->device->ws->buffer_destroy(queue->scratch_bo);
2277 queue->scratch_bo = scratch_bo;
2278 queue->scratch_size = scratch_size;
2279 }
2280
2281 if (compute_scratch_bo != queue->compute_scratch_bo) {
2282 if (queue->compute_scratch_bo)
2283 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2284 queue->compute_scratch_bo = compute_scratch_bo;
2285 queue->compute_scratch_size = compute_scratch_size;
2286 }
2287
2288 if (esgs_ring_bo != queue->esgs_ring_bo) {
2289 if (queue->esgs_ring_bo)
2290 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2291 queue->esgs_ring_bo = esgs_ring_bo;
2292 queue->esgs_ring_size = esgs_ring_size;
2293 }
2294
2295 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2296 if (queue->gsvs_ring_bo)
2297 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2298 queue->gsvs_ring_bo = gsvs_ring_bo;
2299 queue->gsvs_ring_size = gsvs_ring_size;
2300 }
2301
2302 if (tess_rings_bo != queue->tess_rings_bo) {
2303 queue->tess_rings_bo = tess_rings_bo;
2304 queue->has_tess_rings = true;
2305 }
2306
2307 if (descriptor_bo != queue->descriptor_bo) {
2308 if (queue->descriptor_bo)
2309 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2310
2311 queue->descriptor_bo = descriptor_bo;
2312 }
2313
2314 if (add_sample_positions)
2315 queue->has_sample_positions = true;
2316
2317 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2318 *initial_preamble_cs = queue->initial_preamble_cs;
2319 *continue_preamble_cs = queue->continue_preamble_cs;
2320 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2321 *continue_preamble_cs = NULL;
2322 return VK_SUCCESS;
2323 fail:
2324 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2325 if (dest_cs[i])
2326 queue->device->ws->cs_destroy(dest_cs[i]);
2327 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2328 queue->device->ws->buffer_destroy(descriptor_bo);
2329 if (scratch_bo && scratch_bo != queue->scratch_bo)
2330 queue->device->ws->buffer_destroy(scratch_bo);
2331 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2332 queue->device->ws->buffer_destroy(compute_scratch_bo);
2333 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2334 queue->device->ws->buffer_destroy(esgs_ring_bo);
2335 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2336 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2337 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2338 queue->device->ws->buffer_destroy(tess_rings_bo);
2339 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2340 }
2341
2342 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2343 struct radv_winsys_sem_counts *counts,
2344 int num_sems,
2345 const VkSemaphore *sems,
2346 VkFence _fence,
2347 bool reset_temp)
2348 {
2349 int syncobj_idx = 0, sem_idx = 0;
2350
2351 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2352 return VK_SUCCESS;
2353
2354 for (uint32_t i = 0; i < num_sems; i++) {
2355 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2356
2357 if (sem->temp_syncobj || sem->syncobj)
2358 counts->syncobj_count++;
2359 else
2360 counts->sem_count++;
2361 }
2362
2363 if (_fence != VK_NULL_HANDLE) {
2364 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2365 if (fence->temp_syncobj || fence->syncobj)
2366 counts->syncobj_count++;
2367 }
2368
2369 if (counts->syncobj_count) {
2370 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2371 if (!counts->syncobj)
2372 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2373 }
2374
2375 if (counts->sem_count) {
2376 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2377 if (!counts->sem) {
2378 free(counts->syncobj);
2379 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2380 }
2381 }
2382
2383 for (uint32_t i = 0; i < num_sems; i++) {
2384 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2385
2386 if (sem->temp_syncobj) {
2387 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2388 }
2389 else if (sem->syncobj)
2390 counts->syncobj[syncobj_idx++] = sem->syncobj;
2391 else {
2392 assert(sem->sem);
2393 counts->sem[sem_idx++] = sem->sem;
2394 }
2395 }
2396
2397 if (_fence != VK_NULL_HANDLE) {
2398 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2399 if (fence->temp_syncobj)
2400 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2401 else if (fence->syncobj)
2402 counts->syncobj[syncobj_idx++] = fence->syncobj;
2403 }
2404
2405 return VK_SUCCESS;
2406 }
2407
2408 static void
2409 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2410 {
2411 free(sem_info->wait.syncobj);
2412 free(sem_info->wait.sem);
2413 free(sem_info->signal.syncobj);
2414 free(sem_info->signal.sem);
2415 }
2416
2417
2418 static void radv_free_temp_syncobjs(struct radv_device *device,
2419 int num_sems,
2420 const VkSemaphore *sems)
2421 {
2422 for (uint32_t i = 0; i < num_sems; i++) {
2423 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2424
2425 if (sem->temp_syncobj) {
2426 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2427 sem->temp_syncobj = 0;
2428 }
2429 }
2430 }
2431
2432 static VkResult
2433 radv_alloc_sem_info(struct radv_instance *instance,
2434 struct radv_winsys_sem_info *sem_info,
2435 int num_wait_sems,
2436 const VkSemaphore *wait_sems,
2437 int num_signal_sems,
2438 const VkSemaphore *signal_sems,
2439 VkFence fence)
2440 {
2441 VkResult ret;
2442 memset(sem_info, 0, sizeof(*sem_info));
2443
2444 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2445 if (ret)
2446 return ret;
2447 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2448 if (ret)
2449 radv_free_sem_info(sem_info);
2450
2451 /* caller can override these */
2452 sem_info->cs_emit_wait = true;
2453 sem_info->cs_emit_signal = true;
2454 return ret;
2455 }
2456
2457 /* Signals fence as soon as all the work currently put on queue is done. */
2458 static VkResult radv_signal_fence(struct radv_queue *queue,
2459 struct radv_fence *fence)
2460 {
2461 int ret;
2462 VkResult result;
2463 struct radv_winsys_sem_info sem_info;
2464
2465 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2466 radv_fence_to_handle(fence));
2467 if (result != VK_SUCCESS)
2468 return result;
2469
2470 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2471 &queue->device->empty_cs[queue->queue_family_index],
2472 1, NULL, NULL, &sem_info, NULL,
2473 false, fence->fence);
2474 radv_free_sem_info(&sem_info);
2475
2476 if (ret)
2477 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2478
2479 return VK_SUCCESS;
2480 }
2481
2482 VkResult radv_QueueSubmit(
2483 VkQueue _queue,
2484 uint32_t submitCount,
2485 const VkSubmitInfo* pSubmits,
2486 VkFence _fence)
2487 {
2488 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2489 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2490 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2491 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2492 int ret;
2493 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2494 uint32_t scratch_size = 0;
2495 uint32_t compute_scratch_size = 0;
2496 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2497 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2498 VkResult result;
2499 bool fence_emitted = false;
2500 bool tess_rings_needed = false;
2501 bool sample_positions_needed = false;
2502
2503 /* Do this first so failing to allocate scratch buffers can't result in
2504 * partially executed submissions. */
2505 for (uint32_t i = 0; i < submitCount; i++) {
2506 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2507 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2508 pSubmits[i].pCommandBuffers[j]);
2509
2510 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2511 compute_scratch_size = MAX2(compute_scratch_size,
2512 cmd_buffer->compute_scratch_size_needed);
2513 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2514 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2515 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2516 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2517 }
2518 }
2519
2520 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2521 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2522 sample_positions_needed, &initial_flush_preamble_cs,
2523 &initial_preamble_cs, &continue_preamble_cs);
2524 if (result != VK_SUCCESS)
2525 return result;
2526
2527 for (uint32_t i = 0; i < submitCount; i++) {
2528 struct radeon_cmdbuf **cs_array;
2529 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2530 bool can_patch = true;
2531 uint32_t advance;
2532 struct radv_winsys_sem_info sem_info;
2533
2534 result = radv_alloc_sem_info(queue->device->instance,
2535 &sem_info,
2536 pSubmits[i].waitSemaphoreCount,
2537 pSubmits[i].pWaitSemaphores,
2538 pSubmits[i].signalSemaphoreCount,
2539 pSubmits[i].pSignalSemaphores,
2540 _fence);
2541 if (result != VK_SUCCESS)
2542 return result;
2543
2544 if (!pSubmits[i].commandBufferCount) {
2545 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2546 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2547 &queue->device->empty_cs[queue->queue_family_index],
2548 1, NULL, NULL,
2549 &sem_info, NULL,
2550 false, base_fence);
2551 if (ret) {
2552 radv_loge("failed to submit CS %d\n", i);
2553 abort();
2554 }
2555 fence_emitted = true;
2556 }
2557 radv_free_sem_info(&sem_info);
2558 continue;
2559 }
2560
2561 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
2562 (pSubmits[i].commandBufferCount));
2563
2564 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2565 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2566 pSubmits[i].pCommandBuffers[j]);
2567 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2568
2569 cs_array[j] = cmd_buffer->cs;
2570 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2571 can_patch = false;
2572
2573 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2574 }
2575
2576 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2577 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2578 const struct radv_winsys_bo_list *bo_list = NULL;
2579
2580 advance = MIN2(max_cs_submission,
2581 pSubmits[i].commandBufferCount - j);
2582
2583 if (queue->device->trace_bo)
2584 *queue->device->trace_id_ptr = 0;
2585
2586 sem_info.cs_emit_wait = j == 0;
2587 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2588
2589 if (unlikely(queue->device->use_global_bo_list)) {
2590 pthread_mutex_lock(&queue->device->bo_list.mutex);
2591 bo_list = &queue->device->bo_list.list;
2592 }
2593
2594 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2595 advance, initial_preamble, continue_preamble_cs,
2596 &sem_info, bo_list,
2597 can_patch, base_fence);
2598
2599 if (unlikely(queue->device->use_global_bo_list))
2600 pthread_mutex_unlock(&queue->device->bo_list.mutex);
2601
2602 if (ret) {
2603 radv_loge("failed to submit CS %d\n", i);
2604 abort();
2605 }
2606 fence_emitted = true;
2607 if (queue->device->trace_bo) {
2608 radv_check_gpu_hangs(queue, cs_array[j]);
2609 }
2610 }
2611
2612 radv_free_temp_syncobjs(queue->device,
2613 pSubmits[i].waitSemaphoreCount,
2614 pSubmits[i].pWaitSemaphores);
2615 radv_free_sem_info(&sem_info);
2616 free(cs_array);
2617 }
2618
2619 if (fence) {
2620 if (!fence_emitted) {
2621 result = radv_signal_fence(queue, fence);
2622 if (result != VK_SUCCESS)
2623 return result;
2624 }
2625 fence->submitted = true;
2626 }
2627
2628 return VK_SUCCESS;
2629 }
2630
2631 VkResult radv_QueueWaitIdle(
2632 VkQueue _queue)
2633 {
2634 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2635
2636 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2637 radv_queue_family_to_ring(queue->queue_family_index),
2638 queue->queue_idx);
2639 return VK_SUCCESS;
2640 }
2641
2642 VkResult radv_DeviceWaitIdle(
2643 VkDevice _device)
2644 {
2645 RADV_FROM_HANDLE(radv_device, device, _device);
2646
2647 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2648 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2649 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2650 }
2651 }
2652 return VK_SUCCESS;
2653 }
2654
2655 VkResult radv_EnumerateInstanceExtensionProperties(
2656 const char* pLayerName,
2657 uint32_t* pPropertyCount,
2658 VkExtensionProperties* pProperties)
2659 {
2660 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2661
2662 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
2663 if (radv_supported_instance_extensions.extensions[i]) {
2664 vk_outarray_append(&out, prop) {
2665 *prop = radv_instance_extensions[i];
2666 }
2667 }
2668 }
2669
2670 return vk_outarray_status(&out);
2671 }
2672
2673 VkResult radv_EnumerateDeviceExtensionProperties(
2674 VkPhysicalDevice physicalDevice,
2675 const char* pLayerName,
2676 uint32_t* pPropertyCount,
2677 VkExtensionProperties* pProperties)
2678 {
2679 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2680 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2681
2682 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
2683 if (device->supported_extensions.extensions[i]) {
2684 vk_outarray_append(&out, prop) {
2685 *prop = radv_device_extensions[i];
2686 }
2687 }
2688 }
2689
2690 return vk_outarray_status(&out);
2691 }
2692
2693 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2694 VkInstance _instance,
2695 const char* pName)
2696 {
2697 RADV_FROM_HANDLE(radv_instance, instance, _instance);
2698
2699 return radv_lookup_entrypoint_checked(pName,
2700 instance ? instance->apiVersion : 0,
2701 instance ? &instance->enabled_extensions : NULL,
2702 NULL);
2703 }
2704
2705 /* The loader wants us to expose a second GetInstanceProcAddr function
2706 * to work around certain LD_PRELOAD issues seen in apps.
2707 */
2708 PUBLIC
2709 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2710 VkInstance instance,
2711 const char* pName);
2712
2713 PUBLIC
2714 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2715 VkInstance instance,
2716 const char* pName)
2717 {
2718 return radv_GetInstanceProcAddr(instance, pName);
2719 }
2720
2721 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2722 VkDevice _device,
2723 const char* pName)
2724 {
2725 RADV_FROM_HANDLE(radv_device, device, _device);
2726
2727 return radv_lookup_entrypoint_checked(pName,
2728 device->instance->apiVersion,
2729 &device->instance->enabled_extensions,
2730 &device->enabled_extensions);
2731 }
2732
2733 bool radv_get_memory_fd(struct radv_device *device,
2734 struct radv_device_memory *memory,
2735 int *pFD)
2736 {
2737 struct radeon_bo_metadata metadata;
2738
2739 if (memory->image) {
2740 radv_init_metadata(device, memory->image, &metadata);
2741 device->ws->buffer_set_metadata(memory->bo, &metadata);
2742 }
2743
2744 return device->ws->buffer_get_fd(device->ws, memory->bo,
2745 pFD);
2746 }
2747
2748 static VkResult radv_alloc_memory(struct radv_device *device,
2749 const VkMemoryAllocateInfo* pAllocateInfo,
2750 const VkAllocationCallbacks* pAllocator,
2751 VkDeviceMemory* pMem)
2752 {
2753 struct radv_device_memory *mem;
2754 VkResult result;
2755 enum radeon_bo_domain domain;
2756 uint32_t flags = 0;
2757 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
2758
2759 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2760
2761 if (pAllocateInfo->allocationSize == 0) {
2762 /* Apparently, this is allowed */
2763 *pMem = VK_NULL_HANDLE;
2764 return VK_SUCCESS;
2765 }
2766
2767 const VkImportMemoryFdInfoKHR *import_info =
2768 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2769 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2770 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2771 const VkExportMemoryAllocateInfoKHR *export_info =
2772 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO_KHR);
2773 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
2774 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
2775
2776 const struct wsi_memory_allocate_info *wsi_info =
2777 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
2778
2779 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2780 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2781 if (mem == NULL)
2782 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2783
2784 if (wsi_info && wsi_info->implicit_sync)
2785 flags |= RADEON_FLAG_IMPLICIT_SYNC;
2786
2787 if (dedicate_info) {
2788 mem->image = radv_image_from_handle(dedicate_info->image);
2789 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2790 } else {
2791 mem->image = NULL;
2792 mem->buffer = NULL;
2793 }
2794
2795 mem->user_ptr = NULL;
2796
2797 if (import_info) {
2798 assert(import_info->handleType ==
2799 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
2800 import_info->handleType ==
2801 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
2802 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2803 NULL, NULL);
2804 if (!mem->bo) {
2805 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2806 goto fail;
2807 } else {
2808 close(import_info->fd);
2809 }
2810 } else if (host_ptr_info) {
2811 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
2812 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
2813 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
2814 pAllocateInfo->allocationSize);
2815 if (!mem->bo) {
2816 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2817 goto fail;
2818 } else {
2819 mem->user_ptr = host_ptr_info->pHostPointer;
2820 }
2821 } else {
2822 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2823 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2824 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
2825 domain = RADEON_DOMAIN_GTT;
2826 else
2827 domain = RADEON_DOMAIN_VRAM;
2828
2829 if (mem_type_index == RADV_MEM_TYPE_VRAM)
2830 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2831 else
2832 flags |= RADEON_FLAG_CPU_ACCESS;
2833
2834 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2835 flags |= RADEON_FLAG_GTT_WC;
2836
2837 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
2838 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
2839
2840 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2841 domain, flags);
2842
2843 if (!mem->bo) {
2844 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2845 goto fail;
2846 }
2847 mem->type_index = mem_type_index;
2848 }
2849
2850 result = radv_bo_list_add(device, mem->bo);
2851 if (result != VK_SUCCESS)
2852 goto fail_bo;
2853
2854 *pMem = radv_device_memory_to_handle(mem);
2855
2856 return VK_SUCCESS;
2857
2858 fail_bo:
2859 device->ws->buffer_destroy(mem->bo);
2860 fail:
2861 vk_free2(&device->alloc, pAllocator, mem);
2862
2863 return result;
2864 }
2865
2866 VkResult radv_AllocateMemory(
2867 VkDevice _device,
2868 const VkMemoryAllocateInfo* pAllocateInfo,
2869 const VkAllocationCallbacks* pAllocator,
2870 VkDeviceMemory* pMem)
2871 {
2872 RADV_FROM_HANDLE(radv_device, device, _device);
2873 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
2874 }
2875
2876 void radv_FreeMemory(
2877 VkDevice _device,
2878 VkDeviceMemory _mem,
2879 const VkAllocationCallbacks* pAllocator)
2880 {
2881 RADV_FROM_HANDLE(radv_device, device, _device);
2882 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2883
2884 if (mem == NULL)
2885 return;
2886
2887 radv_bo_list_remove(device, mem->bo);
2888 device->ws->buffer_destroy(mem->bo);
2889 mem->bo = NULL;
2890
2891 vk_free2(&device->alloc, pAllocator, mem);
2892 }
2893
2894 VkResult radv_MapMemory(
2895 VkDevice _device,
2896 VkDeviceMemory _memory,
2897 VkDeviceSize offset,
2898 VkDeviceSize size,
2899 VkMemoryMapFlags flags,
2900 void** ppData)
2901 {
2902 RADV_FROM_HANDLE(radv_device, device, _device);
2903 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2904
2905 if (mem == NULL) {
2906 *ppData = NULL;
2907 return VK_SUCCESS;
2908 }
2909
2910 if (mem->user_ptr)
2911 *ppData = mem->user_ptr;
2912 else
2913 *ppData = device->ws->buffer_map(mem->bo);
2914
2915 if (*ppData) {
2916 *ppData += offset;
2917 return VK_SUCCESS;
2918 }
2919
2920 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
2921 }
2922
2923 void radv_UnmapMemory(
2924 VkDevice _device,
2925 VkDeviceMemory _memory)
2926 {
2927 RADV_FROM_HANDLE(radv_device, device, _device);
2928 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2929
2930 if (mem == NULL)
2931 return;
2932
2933 if (mem->user_ptr == NULL)
2934 device->ws->buffer_unmap(mem->bo);
2935 }
2936
2937 VkResult radv_FlushMappedMemoryRanges(
2938 VkDevice _device,
2939 uint32_t memoryRangeCount,
2940 const VkMappedMemoryRange* pMemoryRanges)
2941 {
2942 return VK_SUCCESS;
2943 }
2944
2945 VkResult radv_InvalidateMappedMemoryRanges(
2946 VkDevice _device,
2947 uint32_t memoryRangeCount,
2948 const VkMappedMemoryRange* pMemoryRanges)
2949 {
2950 return VK_SUCCESS;
2951 }
2952
2953 void radv_GetBufferMemoryRequirements(
2954 VkDevice _device,
2955 VkBuffer _buffer,
2956 VkMemoryRequirements* pMemoryRequirements)
2957 {
2958 RADV_FROM_HANDLE(radv_device, device, _device);
2959 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2960
2961 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2962
2963 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2964 pMemoryRequirements->alignment = 4096;
2965 else
2966 pMemoryRequirements->alignment = 16;
2967
2968 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2969 }
2970
2971 void radv_GetBufferMemoryRequirements2(
2972 VkDevice device,
2973 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2974 VkMemoryRequirements2KHR* pMemoryRequirements)
2975 {
2976 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2977 &pMemoryRequirements->memoryRequirements);
2978 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
2979 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2980 switch (ext->sType) {
2981 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2982 VkMemoryDedicatedRequirementsKHR *req =
2983 (VkMemoryDedicatedRequirementsKHR *) ext;
2984 req->requiresDedicatedAllocation = buffer->shareable;
2985 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2986 break;
2987 }
2988 default:
2989 break;
2990 }
2991 }
2992 }
2993
2994 void radv_GetImageMemoryRequirements(
2995 VkDevice _device,
2996 VkImage _image,
2997 VkMemoryRequirements* pMemoryRequirements)
2998 {
2999 RADV_FROM_HANDLE(radv_device, device, _device);
3000 RADV_FROM_HANDLE(radv_image, image, _image);
3001
3002 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3003
3004 pMemoryRequirements->size = image->size;
3005 pMemoryRequirements->alignment = image->alignment;
3006 }
3007
3008 void radv_GetImageMemoryRequirements2(
3009 VkDevice device,
3010 const VkImageMemoryRequirementsInfo2KHR* pInfo,
3011 VkMemoryRequirements2KHR* pMemoryRequirements)
3012 {
3013 radv_GetImageMemoryRequirements(device, pInfo->image,
3014 &pMemoryRequirements->memoryRequirements);
3015
3016 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3017
3018 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3019 switch (ext->sType) {
3020 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
3021 VkMemoryDedicatedRequirementsKHR *req =
3022 (VkMemoryDedicatedRequirementsKHR *) ext;
3023 req->requiresDedicatedAllocation = image->shareable;
3024 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3025 break;
3026 }
3027 default:
3028 break;
3029 }
3030 }
3031 }
3032
3033 void radv_GetImageSparseMemoryRequirements(
3034 VkDevice device,
3035 VkImage image,
3036 uint32_t* pSparseMemoryRequirementCount,
3037 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3038 {
3039 stub();
3040 }
3041
3042 void radv_GetImageSparseMemoryRequirements2(
3043 VkDevice device,
3044 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
3045 uint32_t* pSparseMemoryRequirementCount,
3046 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
3047 {
3048 stub();
3049 }
3050
3051 void radv_GetDeviceMemoryCommitment(
3052 VkDevice device,
3053 VkDeviceMemory memory,
3054 VkDeviceSize* pCommittedMemoryInBytes)
3055 {
3056 *pCommittedMemoryInBytes = 0;
3057 }
3058
3059 VkResult radv_BindBufferMemory2(VkDevice device,
3060 uint32_t bindInfoCount,
3061 const VkBindBufferMemoryInfoKHR *pBindInfos)
3062 {
3063 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3064 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3065 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3066
3067 if (mem) {
3068 buffer->bo = mem->bo;
3069 buffer->offset = pBindInfos[i].memoryOffset;
3070 } else {
3071 buffer->bo = NULL;
3072 }
3073 }
3074 return VK_SUCCESS;
3075 }
3076
3077 VkResult radv_BindBufferMemory(
3078 VkDevice device,
3079 VkBuffer buffer,
3080 VkDeviceMemory memory,
3081 VkDeviceSize memoryOffset)
3082 {
3083 const VkBindBufferMemoryInfoKHR info = {
3084 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3085 .buffer = buffer,
3086 .memory = memory,
3087 .memoryOffset = memoryOffset
3088 };
3089
3090 return radv_BindBufferMemory2(device, 1, &info);
3091 }
3092
3093 VkResult radv_BindImageMemory2(VkDevice device,
3094 uint32_t bindInfoCount,
3095 const VkBindImageMemoryInfoKHR *pBindInfos)
3096 {
3097 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3098 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3099 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3100
3101 if (mem) {
3102 image->bo = mem->bo;
3103 image->offset = pBindInfos[i].memoryOffset;
3104 } else {
3105 image->bo = NULL;
3106 image->offset = 0;
3107 }
3108 }
3109 return VK_SUCCESS;
3110 }
3111
3112
3113 VkResult radv_BindImageMemory(
3114 VkDevice device,
3115 VkImage image,
3116 VkDeviceMemory memory,
3117 VkDeviceSize memoryOffset)
3118 {
3119 const VkBindImageMemoryInfoKHR info = {
3120 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3121 .image = image,
3122 .memory = memory,
3123 .memoryOffset = memoryOffset
3124 };
3125
3126 return radv_BindImageMemory2(device, 1, &info);
3127 }
3128
3129
3130 static void
3131 radv_sparse_buffer_bind_memory(struct radv_device *device,
3132 const VkSparseBufferMemoryBindInfo *bind)
3133 {
3134 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3135
3136 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3137 struct radv_device_memory *mem = NULL;
3138
3139 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3140 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3141
3142 device->ws->buffer_virtual_bind(buffer->bo,
3143 bind->pBinds[i].resourceOffset,
3144 bind->pBinds[i].size,
3145 mem ? mem->bo : NULL,
3146 bind->pBinds[i].memoryOffset);
3147 }
3148 }
3149
3150 static void
3151 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3152 const VkSparseImageOpaqueMemoryBindInfo *bind)
3153 {
3154 RADV_FROM_HANDLE(radv_image, image, bind->image);
3155
3156 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3157 struct radv_device_memory *mem = NULL;
3158
3159 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3160 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3161
3162 device->ws->buffer_virtual_bind(image->bo,
3163 bind->pBinds[i].resourceOffset,
3164 bind->pBinds[i].size,
3165 mem ? mem->bo : NULL,
3166 bind->pBinds[i].memoryOffset);
3167 }
3168 }
3169
3170 VkResult radv_QueueBindSparse(
3171 VkQueue _queue,
3172 uint32_t bindInfoCount,
3173 const VkBindSparseInfo* pBindInfo,
3174 VkFence _fence)
3175 {
3176 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3177 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3178 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3179 bool fence_emitted = false;
3180 VkResult result;
3181 int ret;
3182
3183 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3184 struct radv_winsys_sem_info sem_info;
3185 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3186 radv_sparse_buffer_bind_memory(queue->device,
3187 pBindInfo[i].pBufferBinds + j);
3188 }
3189
3190 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3191 radv_sparse_image_opaque_bind_memory(queue->device,
3192 pBindInfo[i].pImageOpaqueBinds + j);
3193 }
3194
3195 VkResult result;
3196 result = radv_alloc_sem_info(queue->device->instance,
3197 &sem_info,
3198 pBindInfo[i].waitSemaphoreCount,
3199 pBindInfo[i].pWaitSemaphores,
3200 pBindInfo[i].signalSemaphoreCount,
3201 pBindInfo[i].pSignalSemaphores,
3202 _fence);
3203 if (result != VK_SUCCESS)
3204 return result;
3205
3206 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3207 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3208 &queue->device->empty_cs[queue->queue_family_index],
3209 1, NULL, NULL,
3210 &sem_info, NULL,
3211 false, base_fence);
3212 if (ret) {
3213 radv_loge("failed to submit CS %d\n", i);
3214 abort();
3215 }
3216
3217 fence_emitted = true;
3218 if (fence)
3219 fence->submitted = true;
3220 }
3221
3222 radv_free_sem_info(&sem_info);
3223
3224 }
3225
3226 if (fence) {
3227 if (!fence_emitted) {
3228 result = radv_signal_fence(queue, fence);
3229 if (result != VK_SUCCESS)
3230 return result;
3231 }
3232 fence->submitted = true;
3233 }
3234
3235 return VK_SUCCESS;
3236 }
3237
3238 VkResult radv_CreateFence(
3239 VkDevice _device,
3240 const VkFenceCreateInfo* pCreateInfo,
3241 const VkAllocationCallbacks* pAllocator,
3242 VkFence* pFence)
3243 {
3244 RADV_FROM_HANDLE(radv_device, device, _device);
3245 const VkExportFenceCreateInfoKHR *export =
3246 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO_KHR);
3247 VkExternalFenceHandleTypeFlagsKHR handleTypes =
3248 export ? export->handleTypes : 0;
3249
3250 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3251 sizeof(*fence), 8,
3252 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3253
3254 if (!fence)
3255 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3256
3257 fence->fence_wsi = NULL;
3258 fence->submitted = false;
3259 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3260 fence->temp_syncobj = 0;
3261 if (device->always_use_syncobj || handleTypes) {
3262 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3263 if (ret) {
3264 vk_free2(&device->alloc, pAllocator, fence);
3265 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3266 }
3267 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3268 device->ws->signal_syncobj(device->ws, fence->syncobj);
3269 }
3270 fence->fence = NULL;
3271 } else {
3272 fence->fence = device->ws->create_fence();
3273 if (!fence->fence) {
3274 vk_free2(&device->alloc, pAllocator, fence);
3275 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3276 }
3277 fence->syncobj = 0;
3278 }
3279
3280 *pFence = radv_fence_to_handle(fence);
3281
3282 return VK_SUCCESS;
3283 }
3284
3285 void radv_DestroyFence(
3286 VkDevice _device,
3287 VkFence _fence,
3288 const VkAllocationCallbacks* pAllocator)
3289 {
3290 RADV_FROM_HANDLE(radv_device, device, _device);
3291 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3292
3293 if (!fence)
3294 return;
3295
3296 if (fence->temp_syncobj)
3297 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3298 if (fence->syncobj)
3299 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3300 if (fence->fence)
3301 device->ws->destroy_fence(fence->fence);
3302 if (fence->fence_wsi)
3303 fence->fence_wsi->destroy(fence->fence_wsi);
3304 vk_free2(&device->alloc, pAllocator, fence);
3305 }
3306
3307
3308 static uint64_t radv_get_current_time()
3309 {
3310 struct timespec tv;
3311 clock_gettime(CLOCK_MONOTONIC, &tv);
3312 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3313 }
3314
3315 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3316 {
3317 uint64_t current_time = radv_get_current_time();
3318
3319 timeout = MIN2(UINT64_MAX - current_time, timeout);
3320
3321 return current_time + timeout;
3322 }
3323
3324
3325 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3326 {
3327 for (uint32_t i = 0; i < fenceCount; ++i) {
3328 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3329 if (fence->fence == NULL || fence->syncobj ||
3330 fence->temp_syncobj ||
3331 (!fence->signalled && !fence->submitted))
3332 return false;
3333 }
3334 return true;
3335 }
3336
3337 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3338 {
3339 for (uint32_t i = 0; i < fenceCount; ++i) {
3340 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3341 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3342 return false;
3343 }
3344 return true;
3345 }
3346
3347 VkResult radv_WaitForFences(
3348 VkDevice _device,
3349 uint32_t fenceCount,
3350 const VkFence* pFences,
3351 VkBool32 waitAll,
3352 uint64_t timeout)
3353 {
3354 RADV_FROM_HANDLE(radv_device, device, _device);
3355 timeout = radv_get_absolute_timeout(timeout);
3356
3357 if (device->always_use_syncobj &&
3358 radv_all_fences_syncobj(fenceCount, pFences))
3359 {
3360 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3361 if (!handles)
3362 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3363
3364 for (uint32_t i = 0; i < fenceCount; ++i) {
3365 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3366 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3367 }
3368
3369 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3370
3371 free(handles);
3372 return success ? VK_SUCCESS : VK_TIMEOUT;
3373 }
3374
3375 if (!waitAll && fenceCount > 1) {
3376 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3377 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3378 uint32_t wait_count = 0;
3379 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3380 if (!fences)
3381 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3382
3383 for (uint32_t i = 0; i < fenceCount; ++i) {
3384 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3385
3386 if (fence->signalled) {
3387 free(fences);
3388 return VK_SUCCESS;
3389 }
3390
3391 fences[wait_count++] = fence->fence;
3392 }
3393
3394 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3395 waitAll, timeout - radv_get_current_time());
3396
3397 free(fences);
3398 return success ? VK_SUCCESS : VK_TIMEOUT;
3399 }
3400
3401 while(radv_get_current_time() <= timeout) {
3402 for (uint32_t i = 0; i < fenceCount; ++i) {
3403 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3404 return VK_SUCCESS;
3405 }
3406 }
3407 return VK_TIMEOUT;
3408 }
3409
3410 for (uint32_t i = 0; i < fenceCount; ++i) {
3411 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3412 bool expired = false;
3413
3414 if (fence->temp_syncobj) {
3415 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3416 return VK_TIMEOUT;
3417 continue;
3418 }
3419
3420 if (fence->syncobj) {
3421 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3422 return VK_TIMEOUT;
3423 continue;
3424 }
3425
3426 if (fence->signalled)
3427 continue;
3428
3429 if (fence->fence) {
3430 if (!fence->submitted) {
3431 while(radv_get_current_time() <= timeout &&
3432 !fence->submitted)
3433 /* Do nothing */;
3434
3435 if (!fence->submitted)
3436 return VK_TIMEOUT;
3437
3438 /* Recheck as it may have been set by
3439 * submitting operations. */
3440
3441 if (fence->signalled)
3442 continue;
3443 }
3444
3445 expired = device->ws->fence_wait(device->ws,
3446 fence->fence,
3447 true, timeout);
3448 if (!expired)
3449 return VK_TIMEOUT;
3450 }
3451
3452 if (fence->fence_wsi) {
3453 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3454 if (result != VK_SUCCESS)
3455 return result;
3456 }
3457
3458 fence->signalled = true;
3459 }
3460
3461 return VK_SUCCESS;
3462 }
3463
3464 VkResult radv_ResetFences(VkDevice _device,
3465 uint32_t fenceCount,
3466 const VkFence *pFences)
3467 {
3468 RADV_FROM_HANDLE(radv_device, device, _device);
3469
3470 for (unsigned i = 0; i < fenceCount; ++i) {
3471 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3472 fence->submitted = fence->signalled = false;
3473
3474 /* Per spec, we first restore the permanent payload, and then reset, so
3475 * having a temp syncobj should not skip resetting the permanent syncobj. */
3476 if (fence->temp_syncobj) {
3477 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3478 fence->temp_syncobj = 0;
3479 }
3480
3481 if (fence->syncobj) {
3482 device->ws->reset_syncobj(device->ws, fence->syncobj);
3483 }
3484 }
3485
3486 return VK_SUCCESS;
3487 }
3488
3489 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3490 {
3491 RADV_FROM_HANDLE(radv_device, device, _device);
3492 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3493
3494 if (fence->temp_syncobj) {
3495 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3496 return success ? VK_SUCCESS : VK_NOT_READY;
3497 }
3498
3499 if (fence->syncobj) {
3500 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3501 return success ? VK_SUCCESS : VK_NOT_READY;
3502 }
3503
3504 if (fence->signalled)
3505 return VK_SUCCESS;
3506 if (!fence->submitted)
3507 return VK_NOT_READY;
3508 if (fence->fence) {
3509 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3510 return VK_NOT_READY;
3511 }
3512 if (fence->fence_wsi) {
3513 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
3514
3515 if (result != VK_SUCCESS) {
3516 if (result == VK_TIMEOUT)
3517 return VK_NOT_READY;
3518 return result;
3519 }
3520 }
3521 return VK_SUCCESS;
3522 }
3523
3524
3525 // Queue semaphore functions
3526
3527 VkResult radv_CreateSemaphore(
3528 VkDevice _device,
3529 const VkSemaphoreCreateInfo* pCreateInfo,
3530 const VkAllocationCallbacks* pAllocator,
3531 VkSemaphore* pSemaphore)
3532 {
3533 RADV_FROM_HANDLE(radv_device, device, _device);
3534 const VkExportSemaphoreCreateInfoKHR *export =
3535 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
3536 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
3537 export ? export->handleTypes : 0;
3538
3539 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3540 sizeof(*sem), 8,
3541 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3542 if (!sem)
3543 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3544
3545 sem->temp_syncobj = 0;
3546 /* create a syncobject if we are going to export this semaphore */
3547 if (device->always_use_syncobj || handleTypes) {
3548 assert (device->physical_device->rad_info.has_syncobj);
3549 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3550 if (ret) {
3551 vk_free2(&device->alloc, pAllocator, sem);
3552 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3553 }
3554 sem->sem = NULL;
3555 } else {
3556 sem->sem = device->ws->create_sem(device->ws);
3557 if (!sem->sem) {
3558 vk_free2(&device->alloc, pAllocator, sem);
3559 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3560 }
3561 sem->syncobj = 0;
3562 }
3563
3564 *pSemaphore = radv_semaphore_to_handle(sem);
3565 return VK_SUCCESS;
3566 }
3567
3568 void radv_DestroySemaphore(
3569 VkDevice _device,
3570 VkSemaphore _semaphore,
3571 const VkAllocationCallbacks* pAllocator)
3572 {
3573 RADV_FROM_HANDLE(radv_device, device, _device);
3574 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3575 if (!_semaphore)
3576 return;
3577
3578 if (sem->syncobj)
3579 device->ws->destroy_syncobj(device->ws, sem->syncobj);
3580 else
3581 device->ws->destroy_sem(sem->sem);
3582 vk_free2(&device->alloc, pAllocator, sem);
3583 }
3584
3585 VkResult radv_CreateEvent(
3586 VkDevice _device,
3587 const VkEventCreateInfo* pCreateInfo,
3588 const VkAllocationCallbacks* pAllocator,
3589 VkEvent* pEvent)
3590 {
3591 RADV_FROM_HANDLE(radv_device, device, _device);
3592 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
3593 sizeof(*event), 8,
3594 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3595
3596 if (!event)
3597 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3598
3599 event->bo = device->ws->buffer_create(device->ws, 8, 8,
3600 RADEON_DOMAIN_GTT,
3601 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
3602 if (!event->bo) {
3603 vk_free2(&device->alloc, pAllocator, event);
3604 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3605 }
3606
3607 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
3608
3609 *pEvent = radv_event_to_handle(event);
3610
3611 return VK_SUCCESS;
3612 }
3613
3614 void radv_DestroyEvent(
3615 VkDevice _device,
3616 VkEvent _event,
3617 const VkAllocationCallbacks* pAllocator)
3618 {
3619 RADV_FROM_HANDLE(radv_device, device, _device);
3620 RADV_FROM_HANDLE(radv_event, event, _event);
3621
3622 if (!event)
3623 return;
3624 device->ws->buffer_destroy(event->bo);
3625 vk_free2(&device->alloc, pAllocator, event);
3626 }
3627
3628 VkResult radv_GetEventStatus(
3629 VkDevice _device,
3630 VkEvent _event)
3631 {
3632 RADV_FROM_HANDLE(radv_event, event, _event);
3633
3634 if (*event->map == 1)
3635 return VK_EVENT_SET;
3636 return VK_EVENT_RESET;
3637 }
3638
3639 VkResult radv_SetEvent(
3640 VkDevice _device,
3641 VkEvent _event)
3642 {
3643 RADV_FROM_HANDLE(radv_event, event, _event);
3644 *event->map = 1;
3645
3646 return VK_SUCCESS;
3647 }
3648
3649 VkResult radv_ResetEvent(
3650 VkDevice _device,
3651 VkEvent _event)
3652 {
3653 RADV_FROM_HANDLE(radv_event, event, _event);
3654 *event->map = 0;
3655
3656 return VK_SUCCESS;
3657 }
3658
3659 VkResult radv_CreateBuffer(
3660 VkDevice _device,
3661 const VkBufferCreateInfo* pCreateInfo,
3662 const VkAllocationCallbacks* pAllocator,
3663 VkBuffer* pBuffer)
3664 {
3665 RADV_FROM_HANDLE(radv_device, device, _device);
3666 struct radv_buffer *buffer;
3667
3668 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
3669
3670 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
3671 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3672 if (buffer == NULL)
3673 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3674
3675 buffer->size = pCreateInfo->size;
3676 buffer->usage = pCreateInfo->usage;
3677 buffer->bo = NULL;
3678 buffer->offset = 0;
3679 buffer->flags = pCreateInfo->flags;
3680
3681 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
3682 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR) != NULL;
3683
3684 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
3685 buffer->bo = device->ws->buffer_create(device->ws,
3686 align64(buffer->size, 4096),
3687 4096, 0, RADEON_FLAG_VIRTUAL);
3688 if (!buffer->bo) {
3689 vk_free2(&device->alloc, pAllocator, buffer);
3690 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3691 }
3692 }
3693
3694 *pBuffer = radv_buffer_to_handle(buffer);
3695
3696 return VK_SUCCESS;
3697 }
3698
3699 void radv_DestroyBuffer(
3700 VkDevice _device,
3701 VkBuffer _buffer,
3702 const VkAllocationCallbacks* pAllocator)
3703 {
3704 RADV_FROM_HANDLE(radv_device, device, _device);
3705 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3706
3707 if (!buffer)
3708 return;
3709
3710 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3711 device->ws->buffer_destroy(buffer->bo);
3712
3713 vk_free2(&device->alloc, pAllocator, buffer);
3714 }
3715
3716 static inline unsigned
3717 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
3718 {
3719 if (stencil)
3720 return image->surface.u.legacy.stencil_tiling_index[level];
3721 else
3722 return image->surface.u.legacy.tiling_index[level];
3723 }
3724
3725 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
3726 {
3727 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
3728 }
3729
3730 static uint32_t
3731 radv_init_dcc_control_reg(struct radv_device *device,
3732 struct radv_image_view *iview)
3733 {
3734 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
3735 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
3736 unsigned max_compressed_block_size;
3737 unsigned independent_64b_blocks;
3738
3739 if (device->physical_device->rad_info.chip_class < VI)
3740 return 0;
3741
3742 if (iview->image->info.samples > 1) {
3743 if (iview->image->surface.bpe == 1)
3744 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3745 else if (iview->image->surface.bpe == 2)
3746 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
3747 }
3748
3749 if (!device->physical_device->rad_info.has_dedicated_vram) {
3750 /* amdvlk: [min-compressed-block-size] should be set to 32 for
3751 * dGPU and 64 for APU because all of our APUs to date use
3752 * DIMMs which have a request granularity size of 64B while all
3753 * other chips have a 32B request size.
3754 */
3755 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
3756 }
3757
3758 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
3759 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
3760 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
3761 /* If this DCC image is potentially going to be used in texture
3762 * fetches, we need some special settings.
3763 */
3764 independent_64b_blocks = 1;
3765 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3766 } else {
3767 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
3768 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
3769 * big as possible for better compression state.
3770 */
3771 independent_64b_blocks = 0;
3772 max_compressed_block_size = max_uncompressed_block_size;
3773 }
3774
3775 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3776 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
3777 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
3778 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
3779 }
3780
3781 static void
3782 radv_initialise_color_surface(struct radv_device *device,
3783 struct radv_color_buffer_info *cb,
3784 struct radv_image_view *iview)
3785 {
3786 const struct vk_format_description *desc;
3787 unsigned ntype, format, swap, endian;
3788 unsigned blend_clamp = 0, blend_bypass = 0;
3789 uint64_t va;
3790 const struct radeon_surf *surf = &iview->image->surface;
3791
3792 desc = vk_format_description(iview->vk_format);
3793
3794 memset(cb, 0, sizeof(*cb));
3795
3796 /* Intensity is implemented as Red, so treat it that way. */
3797 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
3798
3799 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3800
3801 cb->cb_color_base = va >> 8;
3802
3803 if (device->physical_device->rad_info.chip_class >= GFX9) {
3804 struct gfx9_surf_meta_flags meta;
3805 if (iview->image->dcc_offset)
3806 meta = iview->image->surface.u.gfx9.dcc;
3807 else
3808 meta = iview->image->surface.u.gfx9.cmask;
3809
3810 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3811 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
3812 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3813 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3814
3815 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
3816 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3817 } else {
3818 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
3819 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3820
3821 cb->cb_color_base += level_info->offset >> 8;
3822 if (level_info->mode == RADEON_SURF_MODE_2D)
3823 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3824
3825 pitch_tile_max = level_info->nblk_x / 8 - 1;
3826 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
3827 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
3828
3829 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3830 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3831 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
3832
3833 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3834
3835 if (radv_image_has_fmask(iview->image)) {
3836 if (device->physical_device->rad_info.chip_class >= CIK)
3837 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
3838 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
3839 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
3840 } else {
3841 /* This must be set for fast clear to work without FMASK. */
3842 if (device->physical_device->rad_info.chip_class >= CIK)
3843 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3844 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3845 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3846 }
3847 }
3848
3849 /* CMASK variables */
3850 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3851 va += iview->image->cmask.offset;
3852 cb->cb_color_cmask = va >> 8;
3853
3854 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3855 va += iview->image->dcc_offset;
3856 cb->cb_dcc_base = va >> 8;
3857 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
3858
3859 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3860 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3861 S_028C6C_SLICE_MAX(max_slice);
3862
3863 if (iview->image->info.samples > 1) {
3864 unsigned log_samples = util_logbase2(iview->image->info.samples);
3865
3866 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3867 S_028C74_NUM_FRAGMENTS(log_samples);
3868 }
3869
3870 if (radv_image_has_fmask(iview->image)) {
3871 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3872 cb->cb_color_fmask = va >> 8;
3873 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3874 } else {
3875 cb->cb_color_fmask = cb->cb_color_base;
3876 }
3877
3878 ntype = radv_translate_color_numformat(iview->vk_format,
3879 desc,
3880 vk_format_get_first_non_void_channel(iview->vk_format));
3881 format = radv_translate_colorformat(iview->vk_format);
3882 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3883 radv_finishme("Illegal color\n");
3884 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3885 endian = radv_colorformat_endian_swap(format);
3886
3887 /* blend clamp should be set for all NORM/SRGB types */
3888 if (ntype == V_028C70_NUMBER_UNORM ||
3889 ntype == V_028C70_NUMBER_SNORM ||
3890 ntype == V_028C70_NUMBER_SRGB)
3891 blend_clamp = 1;
3892
3893 /* set blend bypass according to docs if SINT/UINT or
3894 8/24 COLOR variants */
3895 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3896 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3897 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3898 blend_clamp = 0;
3899 blend_bypass = 1;
3900 }
3901 #if 0
3902 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3903 (format == V_028C70_COLOR_8 ||
3904 format == V_028C70_COLOR_8_8 ||
3905 format == V_028C70_COLOR_8_8_8_8))
3906 ->color_is_int8 = true;
3907 #endif
3908 cb->cb_color_info = S_028C70_FORMAT(format) |
3909 S_028C70_COMP_SWAP(swap) |
3910 S_028C70_BLEND_CLAMP(blend_clamp) |
3911 S_028C70_BLEND_BYPASS(blend_bypass) |
3912 S_028C70_SIMPLE_FLOAT(1) |
3913 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3914 ntype != V_028C70_NUMBER_SNORM &&
3915 ntype != V_028C70_NUMBER_SRGB &&
3916 format != V_028C70_COLOR_8_24 &&
3917 format != V_028C70_COLOR_24_8) |
3918 S_028C70_NUMBER_TYPE(ntype) |
3919 S_028C70_ENDIAN(endian);
3920 if (radv_image_has_fmask(iview->image)) {
3921 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3922 if (device->physical_device->rad_info.chip_class == SI) {
3923 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3924 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3925 }
3926 }
3927
3928 if (radv_image_has_cmask(iview->image) &&
3929 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3930 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3931
3932 if (radv_dcc_enabled(iview->image, iview->base_mip))
3933 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3934
3935 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
3936
3937 /* This must be set for fast clear to work without FMASK. */
3938 if (!radv_image_has_fmask(iview->image) &&
3939 device->physical_device->rad_info.chip_class == SI) {
3940 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3941 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3942 }
3943
3944 if (device->physical_device->rad_info.chip_class >= GFX9) {
3945 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
3946 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
3947
3948 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3949 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3950 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3951 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
3952 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
3953 S_028C68_MAX_MIP(iview->image->info.levels - 1);
3954 }
3955 }
3956
3957 static unsigned
3958 radv_calc_decompress_on_z_planes(struct radv_device *device,
3959 struct radv_image_view *iview)
3960 {
3961 unsigned max_zplanes = 0;
3962
3963 assert(radv_image_is_tc_compat_htile(iview->image));
3964
3965 if (device->physical_device->rad_info.chip_class >= GFX9) {
3966 /* Default value for 32-bit depth surfaces. */
3967 max_zplanes = 4;
3968
3969 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
3970 iview->image->info.samples > 1)
3971 max_zplanes = 2;
3972
3973 max_zplanes = max_zplanes + 1;
3974 } else {
3975 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
3976 /* Do not enable Z plane compression for 16-bit depth
3977 * surfaces because isn't supported on GFX8. Only
3978 * 32-bit depth surfaces are supported by the hardware.
3979 * This allows to maintain shader compatibility and to
3980 * reduce the number of depth decompressions.
3981 */
3982 max_zplanes = 1;
3983 } else {
3984 if (iview->image->info.samples <= 1)
3985 max_zplanes = 5;
3986 else if (iview->image->info.samples <= 4)
3987 max_zplanes = 3;
3988 else
3989 max_zplanes = 2;
3990 }
3991 }
3992
3993 return max_zplanes;
3994 }
3995
3996 static void
3997 radv_initialise_ds_surface(struct radv_device *device,
3998 struct radv_ds_buffer_info *ds,
3999 struct radv_image_view *iview)
4000 {
4001 unsigned level = iview->base_mip;
4002 unsigned format, stencil_format;
4003 uint64_t va, s_offs, z_offs;
4004 bool stencil_only = false;
4005 memset(ds, 0, sizeof(*ds));
4006 switch (iview->image->vk_format) {
4007 case VK_FORMAT_D24_UNORM_S8_UINT:
4008 case VK_FORMAT_X8_D24_UNORM_PACK32:
4009 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4010 ds->offset_scale = 2.0f;
4011 break;
4012 case VK_FORMAT_D16_UNORM:
4013 case VK_FORMAT_D16_UNORM_S8_UINT:
4014 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4015 ds->offset_scale = 4.0f;
4016 break;
4017 case VK_FORMAT_D32_SFLOAT:
4018 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4019 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4020 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4021 ds->offset_scale = 1.0f;
4022 break;
4023 case VK_FORMAT_S8_UINT:
4024 stencil_only = true;
4025 break;
4026 default:
4027 break;
4028 }
4029
4030 format = radv_translate_dbformat(iview->image->vk_format);
4031 stencil_format = iview->image->surface.has_stencil ?
4032 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4033
4034 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4035 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4036 S_028008_SLICE_MAX(max_slice);
4037
4038 ds->db_htile_data_base = 0;
4039 ds->db_htile_surface = 0;
4040
4041 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4042 s_offs = z_offs = va;
4043
4044 if (device->physical_device->rad_info.chip_class >= GFX9) {
4045 assert(iview->image->surface.u.gfx9.surf_offset == 0);
4046 s_offs += iview->image->surface.u.gfx9.stencil_offset;
4047
4048 ds->db_z_info = S_028038_FORMAT(format) |
4049 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4050 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
4051 S_028038_MAXMIP(iview->image->info.levels - 1) |
4052 S_028038_ZRANGE_PRECISION(1);
4053 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4054 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
4055
4056 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
4057 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
4058 ds->db_depth_view |= S_028008_MIPID(level);
4059
4060 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4061 S_02801C_Y_MAX(iview->image->info.height - 1);
4062
4063 if (radv_htile_enabled(iview->image, level)) {
4064 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4065
4066 if (radv_image_is_tc_compat_htile(iview->image)) {
4067 unsigned max_zplanes =
4068 radv_calc_decompress_on_z_planes(device, iview);
4069
4070 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
4071 S_028038_ITERATE_FLUSH(1);
4072 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4073 }
4074
4075 if (!iview->image->surface.has_stencil)
4076 /* Use all of the htile_buffer for depth if there's no stencil. */
4077 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4078 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4079 iview->image->htile_offset;
4080 ds->db_htile_data_base = va >> 8;
4081 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4082 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
4083 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
4084 }
4085 } else {
4086 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
4087
4088 if (stencil_only)
4089 level_info = &iview->image->surface.u.legacy.stencil_level[level];
4090
4091 z_offs += iview->image->surface.u.legacy.level[level].offset;
4092 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
4093
4094 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4095 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4096 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4097
4098 if (iview->image->info.samples > 1)
4099 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4100
4101 if (device->physical_device->rad_info.chip_class >= CIK) {
4102 struct radeon_info *info = &device->physical_device->rad_info;
4103 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
4104 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
4105 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
4106 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4107 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4108 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4109
4110 if (stencil_only)
4111 tile_mode = stencil_tile_mode;
4112
4113 ds->db_depth_info |=
4114 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4115 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4116 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4117 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4118 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4119 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4120 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4121 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4122 } else {
4123 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
4124 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4125 tile_mode_index = si_tile_mode_index(iview->image, level, true);
4126 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4127 if (stencil_only)
4128 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4129 }
4130
4131 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4132 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4133 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4134
4135 if (radv_htile_enabled(iview->image, level)) {
4136 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4137
4138 if (!iview->image->surface.has_stencil &&
4139 !radv_image_is_tc_compat_htile(iview->image))
4140 /* Use all of the htile_buffer for depth if there's no stencil. */
4141 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4142
4143 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4144 iview->image->htile_offset;
4145 ds->db_htile_data_base = va >> 8;
4146 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4147
4148 if (radv_image_is_tc_compat_htile(iview->image)) {
4149 unsigned max_zplanes =
4150 radv_calc_decompress_on_z_planes(device, iview);
4151
4152 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4153 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4154 }
4155 }
4156 }
4157
4158 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4159 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4160 }
4161
4162 VkResult radv_CreateFramebuffer(
4163 VkDevice _device,
4164 const VkFramebufferCreateInfo* pCreateInfo,
4165 const VkAllocationCallbacks* pAllocator,
4166 VkFramebuffer* pFramebuffer)
4167 {
4168 RADV_FROM_HANDLE(radv_device, device, _device);
4169 struct radv_framebuffer *framebuffer;
4170
4171 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4172
4173 size_t size = sizeof(*framebuffer) +
4174 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4175 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4176 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4177 if (framebuffer == NULL)
4178 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4179
4180 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4181 framebuffer->width = pCreateInfo->width;
4182 framebuffer->height = pCreateInfo->height;
4183 framebuffer->layers = pCreateInfo->layers;
4184 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4185 VkImageView _iview = pCreateInfo->pAttachments[i];
4186 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4187 framebuffer->attachments[i].attachment = iview;
4188 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
4189 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4190 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4191 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4192 }
4193 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4194 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4195 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4196 }
4197
4198 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4199 return VK_SUCCESS;
4200 }
4201
4202 void radv_DestroyFramebuffer(
4203 VkDevice _device,
4204 VkFramebuffer _fb,
4205 const VkAllocationCallbacks* pAllocator)
4206 {
4207 RADV_FROM_HANDLE(radv_device, device, _device);
4208 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4209
4210 if (!fb)
4211 return;
4212 vk_free2(&device->alloc, pAllocator, fb);
4213 }
4214
4215 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4216 {
4217 switch (address_mode) {
4218 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4219 return V_008F30_SQ_TEX_WRAP;
4220 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4221 return V_008F30_SQ_TEX_MIRROR;
4222 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4223 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4224 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4225 return V_008F30_SQ_TEX_CLAMP_BORDER;
4226 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4227 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4228 default:
4229 unreachable("illegal tex wrap mode");
4230 break;
4231 }
4232 }
4233
4234 static unsigned
4235 radv_tex_compare(VkCompareOp op)
4236 {
4237 switch (op) {
4238 case VK_COMPARE_OP_NEVER:
4239 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4240 case VK_COMPARE_OP_LESS:
4241 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4242 case VK_COMPARE_OP_EQUAL:
4243 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4244 case VK_COMPARE_OP_LESS_OR_EQUAL:
4245 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4246 case VK_COMPARE_OP_GREATER:
4247 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4248 case VK_COMPARE_OP_NOT_EQUAL:
4249 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4250 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4251 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4252 case VK_COMPARE_OP_ALWAYS:
4253 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4254 default:
4255 unreachable("illegal compare mode");
4256 break;
4257 }
4258 }
4259
4260 static unsigned
4261 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4262 {
4263 switch (filter) {
4264 case VK_FILTER_NEAREST:
4265 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4266 V_008F38_SQ_TEX_XY_FILTER_POINT);
4267 case VK_FILTER_LINEAR:
4268 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4269 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4270 case VK_FILTER_CUBIC_IMG:
4271 default:
4272 fprintf(stderr, "illegal texture filter");
4273 return 0;
4274 }
4275 }
4276
4277 static unsigned
4278 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4279 {
4280 switch (mode) {
4281 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4282 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4283 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4284 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4285 default:
4286 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4287 }
4288 }
4289
4290 static unsigned
4291 radv_tex_bordercolor(VkBorderColor bcolor)
4292 {
4293 switch (bcolor) {
4294 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4295 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4296 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4297 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4298 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4299 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4300 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4301 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4302 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4303 default:
4304 break;
4305 }
4306 return 0;
4307 }
4308
4309 static unsigned
4310 radv_tex_aniso_filter(unsigned filter)
4311 {
4312 if (filter < 2)
4313 return 0;
4314 if (filter < 4)
4315 return 1;
4316 if (filter < 8)
4317 return 2;
4318 if (filter < 16)
4319 return 3;
4320 return 4;
4321 }
4322
4323 static unsigned
4324 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4325 {
4326 switch (mode) {
4327 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4328 return SQ_IMG_FILTER_MODE_BLEND;
4329 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4330 return SQ_IMG_FILTER_MODE_MIN;
4331 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4332 return SQ_IMG_FILTER_MODE_MAX;
4333 default:
4334 break;
4335 }
4336 return 0;
4337 }
4338
4339 static void
4340 radv_init_sampler(struct radv_device *device,
4341 struct radv_sampler *sampler,
4342 const VkSamplerCreateInfo *pCreateInfo)
4343 {
4344 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
4345 (uint32_t) pCreateInfo->maxAnisotropy : 0;
4346 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4347 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4348 unsigned filter_mode = SQ_IMG_FILTER_MODE_BLEND;
4349
4350 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4351 vk_find_struct_const(pCreateInfo->pNext,
4352 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4353 if (sampler_reduction)
4354 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4355
4356 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4357 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4358 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4359 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4360 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4361 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4362 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4363 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4364 S_008F30_DISABLE_CUBE_WRAP(0) |
4365 S_008F30_COMPAT_MODE(is_vi) |
4366 S_008F30_FILTER_MODE(filter_mode));
4367 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4368 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4369 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4370 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4371 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4372 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4373 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4374 S_008F38_MIP_POINT_PRECLAMP(0) |
4375 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4376 S_008F38_FILTER_PREC_FIX(1) |
4377 S_008F38_ANISO_OVERRIDE(is_vi));
4378 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4379 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4380 }
4381
4382 VkResult radv_CreateSampler(
4383 VkDevice _device,
4384 const VkSamplerCreateInfo* pCreateInfo,
4385 const VkAllocationCallbacks* pAllocator,
4386 VkSampler* pSampler)
4387 {
4388 RADV_FROM_HANDLE(radv_device, device, _device);
4389 struct radv_sampler *sampler;
4390
4391 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4392
4393 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4394 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4395 if (!sampler)
4396 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4397
4398 radv_init_sampler(device, sampler, pCreateInfo);
4399 *pSampler = radv_sampler_to_handle(sampler);
4400
4401 return VK_SUCCESS;
4402 }
4403
4404 void radv_DestroySampler(
4405 VkDevice _device,
4406 VkSampler _sampler,
4407 const VkAllocationCallbacks* pAllocator)
4408 {
4409 RADV_FROM_HANDLE(radv_device, device, _device);
4410 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4411
4412 if (!sampler)
4413 return;
4414 vk_free2(&device->alloc, pAllocator, sampler);
4415 }
4416
4417 /* vk_icd.h does not declare this function, so we declare it here to
4418 * suppress Wmissing-prototypes.
4419 */
4420 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4421 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4422
4423 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4424 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4425 {
4426 /* For the full details on loader interface versioning, see
4427 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4428 * What follows is a condensed summary, to help you navigate the large and
4429 * confusing official doc.
4430 *
4431 * - Loader interface v0 is incompatible with later versions. We don't
4432 * support it.
4433 *
4434 * - In loader interface v1:
4435 * - The first ICD entrypoint called by the loader is
4436 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4437 * entrypoint.
4438 * - The ICD must statically expose no other Vulkan symbol unless it is
4439 * linked with -Bsymbolic.
4440 * - Each dispatchable Vulkan handle created by the ICD must be
4441 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4442 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4443 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4444 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4445 * such loader-managed surfaces.
4446 *
4447 * - Loader interface v2 differs from v1 in:
4448 * - The first ICD entrypoint called by the loader is
4449 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4450 * statically expose this entrypoint.
4451 *
4452 * - Loader interface v3 differs from v2 in:
4453 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4454 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4455 * because the loader no longer does so.
4456 */
4457 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4458 return VK_SUCCESS;
4459 }
4460
4461 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4462 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4463 int *pFD)
4464 {
4465 RADV_FROM_HANDLE(radv_device, device, _device);
4466 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4467
4468 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4469
4470 /* At the moment, we support only the below handle types. */
4471 assert(pGetFdInfo->handleType ==
4472 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4473 pGetFdInfo->handleType ==
4474 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4475
4476 bool ret = radv_get_memory_fd(device, memory, pFD);
4477 if (ret == false)
4478 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4479 return VK_SUCCESS;
4480 }
4481
4482 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4483 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
4484 int fd,
4485 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4486 {
4487 RADV_FROM_HANDLE(radv_device, device, _device);
4488
4489 switch (handleType) {
4490 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4491 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4492 return VK_SUCCESS;
4493
4494 default:
4495 /* The valid usage section for this function says:
4496 *
4497 * "handleType must not be one of the handle types defined as
4498 * opaque."
4499 *
4500 * So opaque handle types fall into the default "unsupported" case.
4501 */
4502 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4503 }
4504 }
4505
4506 static VkResult radv_import_opaque_fd(struct radv_device *device,
4507 int fd,
4508 uint32_t *syncobj)
4509 {
4510 uint32_t syncobj_handle = 0;
4511 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4512 if (ret != 0)
4513 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4514
4515 if (*syncobj)
4516 device->ws->destroy_syncobj(device->ws, *syncobj);
4517
4518 *syncobj = syncobj_handle;
4519 close(fd);
4520
4521 return VK_SUCCESS;
4522 }
4523
4524 static VkResult radv_import_sync_fd(struct radv_device *device,
4525 int fd,
4526 uint32_t *syncobj)
4527 {
4528 /* If we create a syncobj we do it locally so that if we have an error, we don't
4529 * leave a syncobj in an undetermined state in the fence. */
4530 uint32_t syncobj_handle = *syncobj;
4531 if (!syncobj_handle) {
4532 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4533 if (ret) {
4534 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4535 }
4536 }
4537
4538 if (fd == -1) {
4539 device->ws->signal_syncobj(device->ws, syncobj_handle);
4540 } else {
4541 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
4542 if (ret != 0)
4543 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4544 }
4545
4546 *syncobj = syncobj_handle;
4547 if (fd != -1)
4548 close(fd);
4549
4550 return VK_SUCCESS;
4551 }
4552
4553 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
4554 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
4555 {
4556 RADV_FROM_HANDLE(radv_device, device, _device);
4557 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
4558 uint32_t *syncobj_dst = NULL;
4559
4560 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
4561 syncobj_dst = &sem->temp_syncobj;
4562 } else {
4563 syncobj_dst = &sem->syncobj;
4564 }
4565
4566 switch(pImportSemaphoreFdInfo->handleType) {
4567 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4568 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4569 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4570 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4571 default:
4572 unreachable("Unhandled semaphore handle type");
4573 }
4574 }
4575
4576 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
4577 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
4578 int *pFd)
4579 {
4580 RADV_FROM_HANDLE(radv_device, device, _device);
4581 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
4582 int ret;
4583 uint32_t syncobj_handle;
4584
4585 if (sem->temp_syncobj)
4586 syncobj_handle = sem->temp_syncobj;
4587 else
4588 syncobj_handle = sem->syncobj;
4589
4590 switch(pGetFdInfo->handleType) {
4591 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4592 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4593 break;
4594 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4595 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4596 if (!ret) {
4597 if (sem->temp_syncobj) {
4598 close (sem->temp_syncobj);
4599 sem->temp_syncobj = 0;
4600 } else {
4601 device->ws->reset_syncobj(device->ws, syncobj_handle);
4602 }
4603 }
4604 break;
4605 default:
4606 unreachable("Unhandled semaphore handle type");
4607 }
4608
4609 if (ret)
4610 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4611 return VK_SUCCESS;
4612 }
4613
4614 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
4615 VkPhysicalDevice physicalDevice,
4616 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
4617 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
4618 {
4619 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4620
4621 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
4622 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4623 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4624 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4625 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4626 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4627 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4628 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4629 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
4630 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4631 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4632 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4633 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4634 } else {
4635 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
4636 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
4637 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
4638 }
4639 }
4640
4641 VkResult radv_ImportFenceFdKHR(VkDevice _device,
4642 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
4643 {
4644 RADV_FROM_HANDLE(radv_device, device, _device);
4645 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
4646 uint32_t *syncobj_dst = NULL;
4647
4648
4649 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT_KHR) {
4650 syncobj_dst = &fence->temp_syncobj;
4651 } else {
4652 syncobj_dst = &fence->syncobj;
4653 }
4654
4655 switch(pImportFenceFdInfo->handleType) {
4656 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4657 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4658 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4659 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4660 default:
4661 unreachable("Unhandled fence handle type");
4662 }
4663 }
4664
4665 VkResult radv_GetFenceFdKHR(VkDevice _device,
4666 const VkFenceGetFdInfoKHR *pGetFdInfo,
4667 int *pFd)
4668 {
4669 RADV_FROM_HANDLE(radv_device, device, _device);
4670 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
4671 int ret;
4672 uint32_t syncobj_handle;
4673
4674 if (fence->temp_syncobj)
4675 syncobj_handle = fence->temp_syncobj;
4676 else
4677 syncobj_handle = fence->syncobj;
4678
4679 switch(pGetFdInfo->handleType) {
4680 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4681 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4682 break;
4683 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4684 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4685 if (!ret) {
4686 if (fence->temp_syncobj) {
4687 close (fence->temp_syncobj);
4688 fence->temp_syncobj = 0;
4689 } else {
4690 device->ws->reset_syncobj(device->ws, syncobj_handle);
4691 }
4692 }
4693 break;
4694 default:
4695 unreachable("Unhandled fence handle type");
4696 }
4697
4698 if (ret)
4699 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4700 return VK_SUCCESS;
4701 }
4702
4703 void radv_GetPhysicalDeviceExternalFenceProperties(
4704 VkPhysicalDevice physicalDevice,
4705 const VkPhysicalDeviceExternalFenceInfoKHR* pExternalFenceInfo,
4706 VkExternalFencePropertiesKHR* pExternalFenceProperties)
4707 {
4708 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4709
4710 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4711 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4712 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4713 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4714 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4715 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT_KHR |
4716 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4717 } else {
4718 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
4719 pExternalFenceProperties->compatibleHandleTypes = 0;
4720 pExternalFenceProperties->externalFenceFeatures = 0;
4721 }
4722 }
4723
4724 VkResult
4725 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
4726 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
4727 const VkAllocationCallbacks* pAllocator,
4728 VkDebugReportCallbackEXT* pCallback)
4729 {
4730 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4731 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
4732 pCreateInfo, pAllocator, &instance->alloc,
4733 pCallback);
4734 }
4735
4736 void
4737 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
4738 VkDebugReportCallbackEXT _callback,
4739 const VkAllocationCallbacks* pAllocator)
4740 {
4741 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4742 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
4743 _callback, pAllocator, &instance->alloc);
4744 }
4745
4746 void
4747 radv_DebugReportMessageEXT(VkInstance _instance,
4748 VkDebugReportFlagsEXT flags,
4749 VkDebugReportObjectTypeEXT objectType,
4750 uint64_t object,
4751 size_t location,
4752 int32_t messageCode,
4753 const char* pLayerPrefix,
4754 const char* pMessage)
4755 {
4756 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4757 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
4758 object, location, messageCode, pLayerPrefix, pMessage);
4759 }
4760
4761 void
4762 radv_GetDeviceGroupPeerMemoryFeatures(
4763 VkDevice device,
4764 uint32_t heapIndex,
4765 uint32_t localDeviceIndex,
4766 uint32_t remoteDeviceIndex,
4767 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
4768 {
4769 assert(localDeviceIndex == remoteDeviceIndex);
4770
4771 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
4772 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
4773 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
4774 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
4775 }