2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
41 #include <amdgpu_drm.h>
42 #include "amdgpu_id.h"
43 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
44 #include "ac_llvm_util.h"
45 #include "vk_format.h"
48 #include "util/debug.h"
51 radv_device_get_cache_uuid(enum radeon_family family
, void *uuid
)
53 uint32_t mesa_timestamp
, llvm_timestamp
;
55 memset(uuid
, 0, VK_UUID_SIZE
);
56 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid
, &mesa_timestamp
) ||
57 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo
, &llvm_timestamp
))
60 memcpy(uuid
, &mesa_timestamp
, 4);
61 memcpy((char*)uuid
+ 4, &llvm_timestamp
, 4);
62 memcpy((char*)uuid
+ 8, &f
, 2);
63 snprintf((char*)uuid
+ 10, VK_UUID_SIZE
- 10, "radv");
68 radv_get_driver_uuid(void *uuid
)
70 ac_compute_driver_uuid(uuid
, VK_UUID_SIZE
);
74 radv_get_device_uuid(struct radeon_info
*info
, void *uuid
)
76 ac_compute_device_uuid(info
, uuid
, VK_UUID_SIZE
);
80 get_chip_name(enum radeon_family family
)
83 case CHIP_TAHITI
: return "AMD RADV TAHITI";
84 case CHIP_PITCAIRN
: return "AMD RADV PITCAIRN";
85 case CHIP_VERDE
: return "AMD RADV CAPE VERDE";
86 case CHIP_OLAND
: return "AMD RADV OLAND";
87 case CHIP_HAINAN
: return "AMD RADV HAINAN";
88 case CHIP_BONAIRE
: return "AMD RADV BONAIRE";
89 case CHIP_KAVERI
: return "AMD RADV KAVERI";
90 case CHIP_KABINI
: return "AMD RADV KABINI";
91 case CHIP_HAWAII
: return "AMD RADV HAWAII";
92 case CHIP_MULLINS
: return "AMD RADV MULLINS";
93 case CHIP_TONGA
: return "AMD RADV TONGA";
94 case CHIP_ICELAND
: return "AMD RADV ICELAND";
95 case CHIP_CARRIZO
: return "AMD RADV CARRIZO";
96 case CHIP_FIJI
: return "AMD RADV FIJI";
97 case CHIP_POLARIS10
: return "AMD RADV POLARIS10";
98 case CHIP_POLARIS11
: return "AMD RADV POLARIS11";
99 case CHIP_POLARIS12
: return "AMD RADV POLARIS12";
100 case CHIP_STONEY
: return "AMD RADV STONEY";
101 case CHIP_VEGA10
: return "AMD RADV VEGA";
102 case CHIP_RAVEN
: return "AMD RADV RAVEN";
103 default: return "AMD RADV unknown";
108 radv_physical_device_init_mem_types(struct radv_physical_device
*device
)
110 STATIC_ASSERT(RADV_MEM_HEAP_COUNT
<= VK_MAX_MEMORY_HEAPS
);
111 uint64_t visible_vram_size
= MIN2(device
->rad_info
.vram_size
,
112 device
->rad_info
.vram_vis_size
);
114 int vram_index
= -1, visible_vram_index
= -1, gart_index
= -1;
115 device
->memory_properties
.memoryHeapCount
= 0;
116 if (device
->rad_info
.vram_size
- visible_vram_size
> 0) {
117 vram_index
= device
->memory_properties
.memoryHeapCount
++;
118 device
->memory_properties
.memoryHeaps
[vram_index
] = (VkMemoryHeap
) {
119 .size
= device
->rad_info
.vram_size
- visible_vram_size
,
120 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
123 if (visible_vram_size
) {
124 visible_vram_index
= device
->memory_properties
.memoryHeapCount
++;
125 device
->memory_properties
.memoryHeaps
[visible_vram_index
] = (VkMemoryHeap
) {
126 .size
= visible_vram_size
,
127 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
130 if (device
->rad_info
.gart_size
> 0) {
131 gart_index
= device
->memory_properties
.memoryHeapCount
++;
132 device
->memory_properties
.memoryHeaps
[gart_index
] = (VkMemoryHeap
) {
133 .size
= device
->rad_info
.gart_size
,
138 STATIC_ASSERT(RADV_MEM_TYPE_COUNT
<= VK_MAX_MEMORY_TYPES
);
139 unsigned type_count
= 0;
140 if (vram_index
>= 0) {
141 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM
;
142 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
143 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
,
144 .heapIndex
= vram_index
,
147 if (gart_index
>= 0) {
148 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_WRITE_COMBINE
;
149 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
150 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
151 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
152 .heapIndex
= gart_index
,
155 if (visible_vram_index
>= 0) {
156 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM_CPU_ACCESS
;
157 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
158 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
159 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
160 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
161 .heapIndex
= visible_vram_index
,
164 if (gart_index
>= 0) {
165 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_CACHED
;
166 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
167 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
168 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
169 VK_MEMORY_PROPERTY_HOST_CACHED_BIT
,
170 .heapIndex
= gart_index
,
173 device
->memory_properties
.memoryTypeCount
= type_count
;
177 radv_physical_device_init(struct radv_physical_device
*device
,
178 struct radv_instance
*instance
,
179 drmDevicePtr drm_device
)
181 const char *path
= drm_device
->nodes
[DRM_NODE_RENDER
];
183 drmVersionPtr version
;
186 fd
= open(path
, O_RDWR
| O_CLOEXEC
);
188 return VK_ERROR_INCOMPATIBLE_DRIVER
;
190 version
= drmGetVersion(fd
);
193 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER
,
194 "failed to get version %s: %m", path
);
197 if (strcmp(version
->name
, "amdgpu")) {
198 drmFreeVersion(version
);
200 return VK_ERROR_INCOMPATIBLE_DRIVER
;
202 drmFreeVersion(version
);
204 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
205 device
->instance
= instance
;
206 assert(strlen(path
) < ARRAY_SIZE(device
->path
));
207 strncpy(device
->path
, path
, ARRAY_SIZE(device
->path
));
209 device
->ws
= radv_amdgpu_winsys_create(fd
, instance
->debug_flags
,
210 instance
->perftest_flags
);
212 result
= VK_ERROR_INCOMPATIBLE_DRIVER
;
216 device
->local_fd
= fd
;
217 device
->ws
->query_info(device
->ws
, &device
->rad_info
);
218 result
= radv_init_wsi(device
);
219 if (result
!= VK_SUCCESS
) {
220 device
->ws
->destroy(device
->ws
);
224 device
->name
= get_chip_name(device
->rad_info
.family
);
226 if (radv_device_get_cache_uuid(device
->rad_info
.family
, device
->cache_uuid
)) {
227 radv_finish_wsi(device
);
228 device
->ws
->destroy(device
->ws
);
229 result
= vk_errorf(VK_ERROR_INITIALIZATION_FAILED
,
230 "cannot generate UUID");
234 /* These flags affect shader compilation. */
235 uint64_t shader_env_flags
=
236 (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
? 0x1 : 0) |
237 (device
->instance
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
? 0x2 : 0);
239 /* The gpu id is already embeded in the uuid so we just pass "radv"
240 * when creating the cache.
242 char buf
[VK_UUID_SIZE
* 2 + 1];
243 disk_cache_format_hex_id(buf
, device
->cache_uuid
, VK_UUID_SIZE
* 2);
244 device
->disk_cache
= disk_cache_create(device
->name
, buf
, shader_env_flags
);
246 fprintf(stderr
, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
248 radv_get_driver_uuid(&device
->device_uuid
);
249 radv_get_device_uuid(&device
->rad_info
, &device
->device_uuid
);
251 if (device
->rad_info
.family
== CHIP_STONEY
||
252 device
->rad_info
.chip_class
>= GFX9
) {
253 device
->has_rbplus
= true;
254 device
->rbplus_allowed
= device
->rad_info
.family
== CHIP_STONEY
;
257 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
260 device
->has_clear_state
= device
->rad_info
.chip_class
>= CIK
;
262 radv_physical_device_init_mem_types(device
);
271 radv_physical_device_finish(struct radv_physical_device
*device
)
273 radv_finish_wsi(device
);
274 device
->ws
->destroy(device
->ws
);
275 disk_cache_destroy(device
->disk_cache
);
276 close(device
->local_fd
);
280 default_alloc_func(void *pUserData
, size_t size
, size_t align
,
281 VkSystemAllocationScope allocationScope
)
287 default_realloc_func(void *pUserData
, void *pOriginal
, size_t size
,
288 size_t align
, VkSystemAllocationScope allocationScope
)
290 return realloc(pOriginal
, size
);
294 default_free_func(void *pUserData
, void *pMemory
)
299 static const VkAllocationCallbacks default_alloc
= {
301 .pfnAllocation
= default_alloc_func
,
302 .pfnReallocation
= default_realloc_func
,
303 .pfnFree
= default_free_func
,
306 static const struct debug_control radv_debug_options
[] = {
307 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS
},
308 {"nodcc", RADV_DEBUG_NO_DCC
},
309 {"shaders", RADV_DEBUG_DUMP_SHADERS
},
310 {"nocache", RADV_DEBUG_NO_CACHE
},
311 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS
},
312 {"nohiz", RADV_DEBUG_NO_HIZ
},
313 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE
},
314 {"unsafemath", RADV_DEBUG_UNSAFE_MATH
},
315 {"allbos", RADV_DEBUG_ALL_BOS
},
316 {"noibs", RADV_DEBUG_NO_IBS
},
317 {"spirv", RADV_DEBUG_DUMP_SPIRV
},
318 {"vmfaults", RADV_DEBUG_VM_FAULTS
},
319 {"zerovram", RADV_DEBUG_ZERO_VRAM
},
320 {"syncshaders", RADV_DEBUG_SYNC_SHADERS
},
325 radv_get_debug_option_name(int id
)
327 assert(id
< ARRAY_SIZE(radv_debug_options
) - 1);
328 return radv_debug_options
[id
].string
;
331 static const struct debug_control radv_perftest_options
[] = {
332 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN
},
333 {"sisched", RADV_PERFTEST_SISCHED
},
338 radv_get_perftest_option_name(int id
)
340 assert(id
< ARRAY_SIZE(radv_debug_options
) - 1);
341 return radv_perftest_options
[id
].string
;
344 VkResult
radv_CreateInstance(
345 const VkInstanceCreateInfo
* pCreateInfo
,
346 const VkAllocationCallbacks
* pAllocator
,
347 VkInstance
* pInstance
)
349 struct radv_instance
*instance
;
351 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO
);
353 uint32_t client_version
;
354 if (pCreateInfo
->pApplicationInfo
&&
355 pCreateInfo
->pApplicationInfo
->apiVersion
!= 0) {
356 client_version
= pCreateInfo
->pApplicationInfo
->apiVersion
;
358 client_version
= VK_MAKE_VERSION(1, 0, 0);
361 if (VK_MAKE_VERSION(1, 0, 0) > client_version
||
362 client_version
> VK_MAKE_VERSION(1, 0, 0xfff)) {
363 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER
,
364 "Client requested version %d.%d.%d",
365 VK_VERSION_MAJOR(client_version
),
366 VK_VERSION_MINOR(client_version
),
367 VK_VERSION_PATCH(client_version
));
370 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
371 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
372 if (!radv_instance_extension_supported(ext_name
))
373 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT
);
376 instance
= vk_alloc2(&default_alloc
, pAllocator
, sizeof(*instance
), 8,
377 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
379 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
381 memset(instance
, 0, sizeof(*instance
));
383 instance
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
386 instance
->alloc
= *pAllocator
;
388 instance
->alloc
= default_alloc
;
390 instance
->apiVersion
= client_version
;
391 instance
->physicalDeviceCount
= -1;
395 VG(VALGRIND_CREATE_MEMPOOL(instance
, 0, false));
397 instance
->debug_flags
= parse_debug_string(getenv("RADV_DEBUG"),
400 instance
->perftest_flags
= parse_debug_string(getenv("RADV_PERFTEST"),
401 radv_perftest_options
);
403 *pInstance
= radv_instance_to_handle(instance
);
408 void radv_DestroyInstance(
409 VkInstance _instance
,
410 const VkAllocationCallbacks
* pAllocator
)
412 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
417 for (int i
= 0; i
< instance
->physicalDeviceCount
; ++i
) {
418 radv_physical_device_finish(instance
->physicalDevices
+ i
);
421 VG(VALGRIND_DESTROY_MEMPOOL(instance
));
425 vk_free(&instance
->alloc
, instance
);
429 radv_enumerate_devices(struct radv_instance
*instance
)
431 /* TODO: Check for more devices ? */
432 drmDevicePtr devices
[8];
433 VkResult result
= VK_ERROR_INCOMPATIBLE_DRIVER
;
436 instance
->physicalDeviceCount
= 0;
438 max_devices
= drmGetDevices2(0, devices
, ARRAY_SIZE(devices
));
440 return VK_ERROR_INCOMPATIBLE_DRIVER
;
442 for (unsigned i
= 0; i
< (unsigned)max_devices
; i
++) {
443 if (devices
[i
]->available_nodes
& 1 << DRM_NODE_RENDER
&&
444 devices
[i
]->bustype
== DRM_BUS_PCI
&&
445 devices
[i
]->deviceinfo
.pci
->vendor_id
== ATI_VENDOR_ID
) {
447 result
= radv_physical_device_init(instance
->physicalDevices
+
448 instance
->physicalDeviceCount
,
451 if (result
== VK_SUCCESS
)
452 ++instance
->physicalDeviceCount
;
453 else if (result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
457 drmFreeDevices(devices
, max_devices
);
462 VkResult
radv_EnumeratePhysicalDevices(
463 VkInstance _instance
,
464 uint32_t* pPhysicalDeviceCount
,
465 VkPhysicalDevice
* pPhysicalDevices
)
467 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
470 if (instance
->physicalDeviceCount
< 0) {
471 result
= radv_enumerate_devices(instance
);
472 if (result
!= VK_SUCCESS
&&
473 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
477 if (!pPhysicalDevices
) {
478 *pPhysicalDeviceCount
= instance
->physicalDeviceCount
;
480 *pPhysicalDeviceCount
= MIN2(*pPhysicalDeviceCount
, instance
->physicalDeviceCount
);
481 for (unsigned i
= 0; i
< *pPhysicalDeviceCount
; ++i
)
482 pPhysicalDevices
[i
] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
485 return *pPhysicalDeviceCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
489 void radv_GetPhysicalDeviceFeatures(
490 VkPhysicalDevice physicalDevice
,
491 VkPhysicalDeviceFeatures
* pFeatures
)
493 memset(pFeatures
, 0, sizeof(*pFeatures
));
495 *pFeatures
= (VkPhysicalDeviceFeatures
) {
496 .robustBufferAccess
= true,
497 .fullDrawIndexUint32
= true,
498 .imageCubeArray
= true,
499 .independentBlend
= true,
500 .geometryShader
= true,
501 .tessellationShader
= true,
502 .sampleRateShading
= true,
503 .dualSrcBlend
= true,
505 .multiDrawIndirect
= true,
506 .drawIndirectFirstInstance
= true,
508 .depthBiasClamp
= true,
509 .fillModeNonSolid
= true,
514 .multiViewport
= true,
515 .samplerAnisotropy
= true,
516 .textureCompressionETC2
= false,
517 .textureCompressionASTC_LDR
= false,
518 .textureCompressionBC
= true,
519 .occlusionQueryPrecise
= true,
520 .pipelineStatisticsQuery
= true,
521 .vertexPipelineStoresAndAtomics
= true,
522 .fragmentStoresAndAtomics
= true,
523 .shaderTessellationAndGeometryPointSize
= true,
524 .shaderImageGatherExtended
= true,
525 .shaderStorageImageExtendedFormats
= true,
526 .shaderStorageImageMultisample
= false,
527 .shaderUniformBufferArrayDynamicIndexing
= true,
528 .shaderSampledImageArrayDynamicIndexing
= true,
529 .shaderStorageBufferArrayDynamicIndexing
= true,
530 .shaderStorageImageArrayDynamicIndexing
= true,
531 .shaderStorageImageReadWithoutFormat
= true,
532 .shaderStorageImageWriteWithoutFormat
= true,
533 .shaderClipDistance
= true,
534 .shaderCullDistance
= true,
535 .shaderFloat64
= true,
537 .shaderInt16
= false,
538 .sparseBinding
= true,
539 .variableMultisampleRate
= true,
540 .inheritedQueries
= true,
544 void radv_GetPhysicalDeviceFeatures2KHR(
545 VkPhysicalDevice physicalDevice
,
546 VkPhysicalDeviceFeatures2KHR
*pFeatures
)
548 vk_foreach_struct(ext
, pFeatures
->pNext
) {
549 switch (ext
->sType
) {
550 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR
: {
551 VkPhysicalDeviceVariablePointerFeaturesKHR
*features
= (void *)ext
;
552 features
->variablePointersStorageBuffer
= true;
553 features
->variablePointers
= false;
556 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHX
: {
557 VkPhysicalDeviceMultiviewFeaturesKHX
*features
= (VkPhysicalDeviceMultiviewFeaturesKHX
*)ext
;
558 features
->multiview
= true;
559 features
->multiviewGeometryShader
= true;
560 features
->multiviewTessellationShader
= true;
567 return radv_GetPhysicalDeviceFeatures(physicalDevice
, &pFeatures
->features
);
570 void radv_GetPhysicalDeviceProperties(
571 VkPhysicalDevice physicalDevice
,
572 VkPhysicalDeviceProperties
* pProperties
)
574 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
575 VkSampleCountFlags sample_counts
= 0xf;
577 /* make sure that the entire descriptor set is addressable with a signed
578 * 32-bit int. So the sum of all limits scaled by descriptor size has to
579 * be at most 2 GiB. the combined image & samples object count as one of
580 * both. This limit is for the pipeline layout, not for the set layout, but
581 * there is no set limit, so we just set a pipeline limit. I don't think
582 * any app is going to hit this soon. */
583 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
) /
584 (32 /* uniform buffer, 32 due to potential space wasted on alignement */ +
585 32 /* storage buffer, 32 due to potential space wasted on alignement */ +
586 32 /* sampler, largest when combined with image */ +
587 64 /* sampled image */ +
588 64 /* storage image */);
590 VkPhysicalDeviceLimits limits
= {
591 .maxImageDimension1D
= (1 << 14),
592 .maxImageDimension2D
= (1 << 14),
593 .maxImageDimension3D
= (1 << 11),
594 .maxImageDimensionCube
= (1 << 14),
595 .maxImageArrayLayers
= (1 << 11),
596 .maxTexelBufferElements
= 128 * 1024 * 1024,
597 .maxUniformBufferRange
= UINT32_MAX
,
598 .maxStorageBufferRange
= UINT32_MAX
,
599 .maxPushConstantsSize
= MAX_PUSH_CONSTANTS_SIZE
,
600 .maxMemoryAllocationCount
= UINT32_MAX
,
601 .maxSamplerAllocationCount
= 64 * 1024,
602 .bufferImageGranularity
= 64, /* A cache line */
603 .sparseAddressSpaceSize
= 0xffffffffu
, /* buffer max size */
604 .maxBoundDescriptorSets
= MAX_SETS
,
605 .maxPerStageDescriptorSamplers
= max_descriptor_set_size
,
606 .maxPerStageDescriptorUniformBuffers
= max_descriptor_set_size
,
607 .maxPerStageDescriptorStorageBuffers
= max_descriptor_set_size
,
608 .maxPerStageDescriptorSampledImages
= max_descriptor_set_size
,
609 .maxPerStageDescriptorStorageImages
= max_descriptor_set_size
,
610 .maxPerStageDescriptorInputAttachments
= max_descriptor_set_size
,
611 .maxPerStageResources
= max_descriptor_set_size
,
612 .maxDescriptorSetSamplers
= max_descriptor_set_size
,
613 .maxDescriptorSetUniformBuffers
= max_descriptor_set_size
,
614 .maxDescriptorSetUniformBuffersDynamic
= MAX_DYNAMIC_BUFFERS
/ 2,
615 .maxDescriptorSetStorageBuffers
= max_descriptor_set_size
,
616 .maxDescriptorSetStorageBuffersDynamic
= MAX_DYNAMIC_BUFFERS
/ 2,
617 .maxDescriptorSetSampledImages
= max_descriptor_set_size
,
618 .maxDescriptorSetStorageImages
= max_descriptor_set_size
,
619 .maxDescriptorSetInputAttachments
= max_descriptor_set_size
,
620 .maxVertexInputAttributes
= 32,
621 .maxVertexInputBindings
= 32,
622 .maxVertexInputAttributeOffset
= 2047,
623 .maxVertexInputBindingStride
= 2048,
624 .maxVertexOutputComponents
= 128,
625 .maxTessellationGenerationLevel
= 64,
626 .maxTessellationPatchSize
= 32,
627 .maxTessellationControlPerVertexInputComponents
= 128,
628 .maxTessellationControlPerVertexOutputComponents
= 128,
629 .maxTessellationControlPerPatchOutputComponents
= 120,
630 .maxTessellationControlTotalOutputComponents
= 4096,
631 .maxTessellationEvaluationInputComponents
= 128,
632 .maxTessellationEvaluationOutputComponents
= 128,
633 .maxGeometryShaderInvocations
= 127,
634 .maxGeometryInputComponents
= 64,
635 .maxGeometryOutputComponents
= 128,
636 .maxGeometryOutputVertices
= 256,
637 .maxGeometryTotalOutputComponents
= 1024,
638 .maxFragmentInputComponents
= 128,
639 .maxFragmentOutputAttachments
= 8,
640 .maxFragmentDualSrcAttachments
= 1,
641 .maxFragmentCombinedOutputResources
= 8,
642 .maxComputeSharedMemorySize
= 32768,
643 .maxComputeWorkGroupCount
= { 65535, 65535, 65535 },
644 .maxComputeWorkGroupInvocations
= 2048,
645 .maxComputeWorkGroupSize
= {
650 .subPixelPrecisionBits
= 4 /* FIXME */,
651 .subTexelPrecisionBits
= 4 /* FIXME */,
652 .mipmapPrecisionBits
= 4 /* FIXME */,
653 .maxDrawIndexedIndexValue
= UINT32_MAX
,
654 .maxDrawIndirectCount
= UINT32_MAX
,
655 .maxSamplerLodBias
= 16,
656 .maxSamplerAnisotropy
= 16,
657 .maxViewports
= MAX_VIEWPORTS
,
658 .maxViewportDimensions
= { (1 << 14), (1 << 14) },
659 .viewportBoundsRange
= { INT16_MIN
, INT16_MAX
},
660 .viewportSubPixelBits
= 13, /* We take a float? */
661 .minMemoryMapAlignment
= 4096, /* A page */
662 .minTexelBufferOffsetAlignment
= 1,
663 .minUniformBufferOffsetAlignment
= 4,
664 .minStorageBufferOffsetAlignment
= 4,
665 .minTexelOffset
= -32,
666 .maxTexelOffset
= 31,
667 .minTexelGatherOffset
= -32,
668 .maxTexelGatherOffset
= 31,
669 .minInterpolationOffset
= -2,
670 .maxInterpolationOffset
= 2,
671 .subPixelInterpolationOffsetBits
= 8,
672 .maxFramebufferWidth
= (1 << 14),
673 .maxFramebufferHeight
= (1 << 14),
674 .maxFramebufferLayers
= (1 << 10),
675 .framebufferColorSampleCounts
= sample_counts
,
676 .framebufferDepthSampleCounts
= sample_counts
,
677 .framebufferStencilSampleCounts
= sample_counts
,
678 .framebufferNoAttachmentsSampleCounts
= sample_counts
,
679 .maxColorAttachments
= MAX_RTS
,
680 .sampledImageColorSampleCounts
= sample_counts
,
681 .sampledImageIntegerSampleCounts
= VK_SAMPLE_COUNT_1_BIT
,
682 .sampledImageDepthSampleCounts
= sample_counts
,
683 .sampledImageStencilSampleCounts
= sample_counts
,
684 .storageImageSampleCounts
= VK_SAMPLE_COUNT_1_BIT
,
685 .maxSampleMaskWords
= 1,
686 .timestampComputeAndGraphics
= true,
687 .timestampPeriod
= 1000000.0 / pdevice
->rad_info
.clock_crystal_freq
,
688 .maxClipDistances
= 8,
689 .maxCullDistances
= 8,
690 .maxCombinedClipAndCullDistances
= 8,
691 .discreteQueuePriorities
= 1,
692 .pointSizeRange
= { 0.125, 255.875 },
693 .lineWidthRange
= { 0.0, 7.9921875 },
694 .pointSizeGranularity
= (1.0 / 8.0),
695 .lineWidthGranularity
= (1.0 / 128.0),
696 .strictLines
= false, /* FINISHME */
697 .standardSampleLocations
= true,
698 .optimalBufferCopyOffsetAlignment
= 128,
699 .optimalBufferCopyRowPitchAlignment
= 128,
700 .nonCoherentAtomSize
= 64,
703 *pProperties
= (VkPhysicalDeviceProperties
) {
704 .apiVersion
= radv_physical_device_api_version(pdevice
),
705 .driverVersion
= vk_get_driver_version(),
706 .vendorID
= ATI_VENDOR_ID
,
707 .deviceID
= pdevice
->rad_info
.pci_id
,
708 .deviceType
= pdevice
->rad_info
.has_dedicated_vram
? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU
: VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU
,
710 .sparseProperties
= {0},
713 strcpy(pProperties
->deviceName
, pdevice
->name
);
714 memcpy(pProperties
->pipelineCacheUUID
, pdevice
->cache_uuid
, VK_UUID_SIZE
);
717 void radv_GetPhysicalDeviceProperties2KHR(
718 VkPhysicalDevice physicalDevice
,
719 VkPhysicalDeviceProperties2KHR
*pProperties
)
721 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
722 radv_GetPhysicalDeviceProperties(physicalDevice
, &pProperties
->properties
);
724 vk_foreach_struct(ext
, pProperties
->pNext
) {
725 switch (ext
->sType
) {
726 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR
: {
727 VkPhysicalDevicePushDescriptorPropertiesKHR
*properties
=
728 (VkPhysicalDevicePushDescriptorPropertiesKHR
*) ext
;
729 properties
->maxPushDescriptors
= MAX_PUSH_DESCRIPTORS
;
732 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR
: {
733 VkPhysicalDeviceIDPropertiesKHR
*properties
= (VkPhysicalDeviceIDPropertiesKHR
*)ext
;
734 memcpy(properties
->driverUUID
, pdevice
->driver_uuid
, VK_UUID_SIZE
);
735 memcpy(properties
->deviceUUID
, pdevice
->device_uuid
, VK_UUID_SIZE
);
736 properties
->deviceLUIDValid
= false;
739 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHX
: {
740 VkPhysicalDeviceMultiviewPropertiesKHX
*properties
= (VkPhysicalDeviceMultiviewPropertiesKHX
*)ext
;
741 properties
->maxMultiviewViewCount
= MAX_VIEWS
;
742 properties
->maxMultiviewInstanceIndex
= INT_MAX
;
745 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR
: {
746 VkPhysicalDevicePointClippingPropertiesKHR
*properties
=
747 (VkPhysicalDevicePointClippingPropertiesKHR
*)ext
;
748 properties
->pointClippingBehavior
= VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR
;
757 static void radv_get_physical_device_queue_family_properties(
758 struct radv_physical_device
* pdevice
,
760 VkQueueFamilyProperties
** pQueueFamilyProperties
)
762 int num_queue_families
= 1;
764 if (pdevice
->rad_info
.num_compute_rings
> 0 &&
765 pdevice
->rad_info
.chip_class
>= CIK
&&
766 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
))
767 num_queue_families
++;
769 if (pQueueFamilyProperties
== NULL
) {
770 *pCount
= num_queue_families
;
779 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
780 .queueFlags
= VK_QUEUE_GRAPHICS_BIT
|
781 VK_QUEUE_COMPUTE_BIT
|
782 VK_QUEUE_TRANSFER_BIT
|
783 VK_QUEUE_SPARSE_BINDING_BIT
,
785 .timestampValidBits
= 64,
786 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
791 if (pdevice
->rad_info
.num_compute_rings
> 0 &&
792 pdevice
->rad_info
.chip_class
>= CIK
&&
793 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
)) {
795 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
796 .queueFlags
= VK_QUEUE_COMPUTE_BIT
|
797 VK_QUEUE_TRANSFER_BIT
|
798 VK_QUEUE_SPARSE_BINDING_BIT
,
799 .queueCount
= pdevice
->rad_info
.num_compute_rings
,
800 .timestampValidBits
= 64,
801 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
809 void radv_GetPhysicalDeviceQueueFamilyProperties(
810 VkPhysicalDevice physicalDevice
,
812 VkQueueFamilyProperties
* pQueueFamilyProperties
)
814 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
815 if (!pQueueFamilyProperties
) {
816 return radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
819 VkQueueFamilyProperties
*properties
[] = {
820 pQueueFamilyProperties
+ 0,
821 pQueueFamilyProperties
+ 1,
822 pQueueFamilyProperties
+ 2,
824 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
825 assert(*pCount
<= 3);
828 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
829 VkPhysicalDevice physicalDevice
,
831 VkQueueFamilyProperties2KHR
*pQueueFamilyProperties
)
833 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
834 if (!pQueueFamilyProperties
) {
835 return radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
838 VkQueueFamilyProperties
*properties
[] = {
839 &pQueueFamilyProperties
[0].queueFamilyProperties
,
840 &pQueueFamilyProperties
[1].queueFamilyProperties
,
841 &pQueueFamilyProperties
[2].queueFamilyProperties
,
843 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
844 assert(*pCount
<= 3);
847 void radv_GetPhysicalDeviceMemoryProperties(
848 VkPhysicalDevice physicalDevice
,
849 VkPhysicalDeviceMemoryProperties
*pMemoryProperties
)
851 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
853 *pMemoryProperties
= physical_device
->memory_properties
;
856 void radv_GetPhysicalDeviceMemoryProperties2KHR(
857 VkPhysicalDevice physicalDevice
,
858 VkPhysicalDeviceMemoryProperties2KHR
*pMemoryProperties
)
860 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice
,
861 &pMemoryProperties
->memoryProperties
);
864 static enum radeon_ctx_priority
865 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT
*pObj
)
867 /* Default to MEDIUM when a specific global priority isn't requested */
869 return RADEON_CTX_PRIORITY_MEDIUM
;
871 switch(pObj
->globalPriority
) {
872 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME
:
873 return RADEON_CTX_PRIORITY_REALTIME
;
874 case VK_QUEUE_GLOBAL_PRIORITY_HIGH
:
875 return RADEON_CTX_PRIORITY_HIGH
;
876 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM
:
877 return RADEON_CTX_PRIORITY_MEDIUM
;
878 case VK_QUEUE_GLOBAL_PRIORITY_LOW
:
879 return RADEON_CTX_PRIORITY_LOW
;
881 unreachable("Illegal global priority value");
882 return RADEON_CTX_PRIORITY_INVALID
;
887 radv_queue_init(struct radv_device
*device
, struct radv_queue
*queue
,
888 int queue_family_index
, int idx
,
889 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
)
891 queue
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
892 queue
->device
= device
;
893 queue
->queue_family_index
= queue_family_index
;
894 queue
->queue_idx
= idx
;
895 queue
->priority
= radv_get_queue_global_priority(global_priority
);
897 queue
->hw_ctx
= device
->ws
->ctx_create(device
->ws
, queue
->priority
);
899 return VK_ERROR_OUT_OF_HOST_MEMORY
;
905 radv_queue_finish(struct radv_queue
*queue
)
908 queue
->device
->ws
->ctx_destroy(queue
->hw_ctx
);
910 if (queue
->initial_full_flush_preamble_cs
)
911 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
912 if (queue
->initial_preamble_cs
)
913 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
914 if (queue
->continue_preamble_cs
)
915 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
916 if (queue
->descriptor_bo
)
917 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
918 if (queue
->scratch_bo
)
919 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
920 if (queue
->esgs_ring_bo
)
921 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
922 if (queue
->gsvs_ring_bo
)
923 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
924 if (queue
->tess_factor_ring_bo
)
925 queue
->device
->ws
->buffer_destroy(queue
->tess_factor_ring_bo
);
926 if (queue
->tess_offchip_ring_bo
)
927 queue
->device
->ws
->buffer_destroy(queue
->tess_offchip_ring_bo
);
928 if (queue
->compute_scratch_bo
)
929 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
933 radv_device_init_gs_info(struct radv_device
*device
)
935 switch (device
->physical_device
->rad_info
.family
) {
944 device
->gs_table_depth
= 16;
958 device
->gs_table_depth
= 32;
961 unreachable("unknown GPU");
965 VkResult
radv_CreateDevice(
966 VkPhysicalDevice physicalDevice
,
967 const VkDeviceCreateInfo
* pCreateInfo
,
968 const VkAllocationCallbacks
* pAllocator
,
971 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
973 struct radv_device
*device
;
975 bool keep_shader_info
= false;
977 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
978 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
979 if (!radv_physical_device_extension_supported(physical_device
, ext_name
))
980 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT
);
982 if (strcmp(ext_name
, VK_AMD_SHADER_INFO_EXTENSION_NAME
) == 0)
983 keep_shader_info
= true;
986 /* Check enabled features */
987 if (pCreateInfo
->pEnabledFeatures
) {
988 VkPhysicalDeviceFeatures supported_features
;
989 radv_GetPhysicalDeviceFeatures(physicalDevice
, &supported_features
);
990 VkBool32
*supported_feature
= (VkBool32
*)&supported_features
;
991 VkBool32
*enabled_feature
= (VkBool32
*)pCreateInfo
->pEnabledFeatures
;
992 unsigned num_features
= sizeof(VkPhysicalDeviceFeatures
) / sizeof(VkBool32
);
993 for (uint32_t i
= 0; i
< num_features
; i
++) {
994 if (enabled_feature
[i
] && !supported_feature
[i
])
995 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT
);
999 device
= vk_alloc2(&physical_device
->instance
->alloc
, pAllocator
,
1001 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
1003 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1005 memset(device
, 0, sizeof(*device
));
1007 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1008 device
->instance
= physical_device
->instance
;
1009 device
->physical_device
= physical_device
;
1011 device
->ws
= physical_device
->ws
;
1013 device
->alloc
= *pAllocator
;
1015 device
->alloc
= physical_device
->instance
->alloc
;
1017 mtx_init(&device
->shader_slab_mutex
, mtx_plain
);
1018 list_inithead(&device
->shader_slabs
);
1020 for (unsigned i
= 0; i
< pCreateInfo
->queueCreateInfoCount
; i
++) {
1021 const VkDeviceQueueCreateInfo
*queue_create
= &pCreateInfo
->pQueueCreateInfos
[i
];
1022 uint32_t qfi
= queue_create
->queueFamilyIndex
;
1023 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
=
1024 vk_find_struct_const(queue_create
->pNext
, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT
);
1026 assert(!global_priority
|| device
->physical_device
->rad_info
.has_ctx_priority
);
1028 device
->queues
[qfi
] = vk_alloc(&device
->alloc
,
1029 queue_create
->queueCount
* sizeof(struct radv_queue
), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
1030 if (!device
->queues
[qfi
]) {
1031 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
1035 memset(device
->queues
[qfi
], 0, queue_create
->queueCount
* sizeof(struct radv_queue
));
1037 device
->queue_count
[qfi
] = queue_create
->queueCount
;
1039 for (unsigned q
= 0; q
< queue_create
->queueCount
; q
++) {
1040 result
= radv_queue_init(device
, &device
->queues
[qfi
][q
], qfi
, q
, global_priority
);
1041 if (result
!= VK_SUCCESS
)
1046 #if HAVE_LLVM < 0x0400
1047 device
->llvm_supports_spill
= false;
1049 device
->llvm_supports_spill
= true;
1052 /* The maximum number of scratch waves. Scratch space isn't divided
1053 * evenly between CUs. The number is only a function of the number of CUs.
1054 * We can decrease the constant to decrease the scratch buffer size.
1056 * sctx->scratch_waves must be >= the maximum posible size of
1057 * 1 threadgroup, so that the hw doesn't hang from being unable
1060 * The recommended value is 4 per CU at most. Higher numbers don't
1061 * bring much benefit, but they still occupy chip resources (think
1062 * async compute). I've seen ~2% performance difference between 4 and 32.
1064 uint32_t max_threads_per_block
= 2048;
1065 device
->scratch_waves
= MAX2(32 * physical_device
->rad_info
.num_good_compute_units
,
1066 max_threads_per_block
/ 64);
1068 radv_device_init_gs_info(device
);
1070 device
->tess_offchip_block_dw_size
=
1071 device
->physical_device
->rad_info
.family
== CHIP_HAWAII
? 4096 : 8192;
1072 device
->has_distributed_tess
=
1073 device
->physical_device
->rad_info
.chip_class
>= VI
&&
1074 device
->physical_device
->rad_info
.max_se
>= 2;
1076 if (getenv("RADV_TRACE_FILE")) {
1077 keep_shader_info
= true;
1079 if (!radv_init_trace(device
))
1083 device
->keep_shader_info
= keep_shader_info
;
1085 result
= radv_device_init_meta(device
);
1086 if (result
!= VK_SUCCESS
)
1089 radv_device_init_msaa(device
);
1091 for (int family
= 0; family
< RADV_MAX_QUEUE_FAMILIES
; ++family
) {
1092 device
->empty_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
1094 case RADV_QUEUE_GENERAL
:
1095 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
1096 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_LOAD_ENABLE(1));
1097 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1099 case RADV_QUEUE_COMPUTE
:
1100 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_NOP
, 0, 0));
1101 radeon_emit(device
->empty_cs
[family
], 0);
1104 device
->ws
->cs_finalize(device
->empty_cs
[family
]);
1107 if (device
->physical_device
->rad_info
.chip_class
>= CIK
)
1108 cik_create_gfx_config(device
);
1110 VkPipelineCacheCreateInfo ci
;
1111 ci
.sType
= VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
;
1114 ci
.pInitialData
= NULL
;
1115 ci
.initialDataSize
= 0;
1117 result
= radv_CreatePipelineCache(radv_device_to_handle(device
),
1119 if (result
!= VK_SUCCESS
)
1122 device
->mem_cache
= radv_pipeline_cache_from_handle(pc
);
1124 *pDevice
= radv_device_to_handle(device
);
1128 if (device
->trace_bo
)
1129 device
->ws
->buffer_destroy(device
->trace_bo
);
1131 if (device
->gfx_init
)
1132 device
->ws
->buffer_destroy(device
->gfx_init
);
1134 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
1135 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
1136 radv_queue_finish(&device
->queues
[i
][q
]);
1137 if (device
->queue_count
[i
])
1138 vk_free(&device
->alloc
, device
->queues
[i
]);
1141 vk_free(&device
->alloc
, device
);
1145 void radv_DestroyDevice(
1147 const VkAllocationCallbacks
* pAllocator
)
1149 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1154 if (device
->trace_bo
)
1155 device
->ws
->buffer_destroy(device
->trace_bo
);
1157 if (device
->gfx_init
)
1158 device
->ws
->buffer_destroy(device
->gfx_init
);
1160 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
1161 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
1162 radv_queue_finish(&device
->queues
[i
][q
]);
1163 if (device
->queue_count
[i
])
1164 vk_free(&device
->alloc
, device
->queues
[i
]);
1165 if (device
->empty_cs
[i
])
1166 device
->ws
->cs_destroy(device
->empty_cs
[i
]);
1168 radv_device_finish_meta(device
);
1170 VkPipelineCache pc
= radv_pipeline_cache_to_handle(device
->mem_cache
);
1171 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
1173 radv_destroy_shader_slabs(device
);
1175 vk_free(&device
->alloc
, device
);
1178 VkResult
radv_EnumerateInstanceLayerProperties(
1179 uint32_t* pPropertyCount
,
1180 VkLayerProperties
* pProperties
)
1182 if (pProperties
== NULL
) {
1183 *pPropertyCount
= 0;
1187 /* None supported at this time */
1188 return vk_error(VK_ERROR_LAYER_NOT_PRESENT
);
1191 VkResult
radv_EnumerateDeviceLayerProperties(
1192 VkPhysicalDevice physicalDevice
,
1193 uint32_t* pPropertyCount
,
1194 VkLayerProperties
* pProperties
)
1196 if (pProperties
== NULL
) {
1197 *pPropertyCount
= 0;
1201 /* None supported at this time */
1202 return vk_error(VK_ERROR_LAYER_NOT_PRESENT
);
1205 void radv_GetDeviceQueue(
1207 uint32_t queueFamilyIndex
,
1208 uint32_t queueIndex
,
1211 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1213 *pQueue
= radv_queue_to_handle(&device
->queues
[queueFamilyIndex
][queueIndex
]);
1217 fill_geom_tess_rings(struct radv_queue
*queue
,
1219 bool add_sample_positions
,
1220 uint32_t esgs_ring_size
,
1221 struct radeon_winsys_bo
*esgs_ring_bo
,
1222 uint32_t gsvs_ring_size
,
1223 struct radeon_winsys_bo
*gsvs_ring_bo
,
1224 uint32_t tess_factor_ring_size
,
1225 struct radeon_winsys_bo
*tess_factor_ring_bo
,
1226 uint32_t tess_offchip_ring_size
,
1227 struct radeon_winsys_bo
*tess_offchip_ring_bo
)
1229 uint64_t esgs_va
= 0, gsvs_va
= 0;
1230 uint64_t tess_factor_va
= 0, tess_offchip_va
= 0;
1231 uint32_t *desc
= &map
[4];
1234 esgs_va
= radv_buffer_get_va(esgs_ring_bo
);
1236 gsvs_va
= radv_buffer_get_va(gsvs_ring_bo
);
1237 if (tess_factor_ring_bo
)
1238 tess_factor_va
= radv_buffer_get_va(tess_factor_ring_bo
);
1239 if (tess_offchip_ring_bo
)
1240 tess_offchip_va
= radv_buffer_get_va(tess_offchip_ring_bo
);
1242 /* stride 0, num records - size, add tid, swizzle, elsize4,
1245 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32) |
1246 S_008F04_STRIDE(0) |
1247 S_008F04_SWIZZLE_ENABLE(true);
1248 desc
[2] = esgs_ring_size
;
1249 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1250 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1251 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1252 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1253 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1254 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1255 S_008F0C_ELEMENT_SIZE(1) |
1256 S_008F0C_INDEX_STRIDE(3) |
1257 S_008F0C_ADD_TID_ENABLE(true);
1260 /* GS entry for ES->GS ring */
1261 /* stride 0, num records - size, elsize0,
1264 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32)|
1265 S_008F04_STRIDE(0) |
1266 S_008F04_SWIZZLE_ENABLE(false);
1267 desc
[2] = esgs_ring_size
;
1268 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1269 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1270 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1271 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1272 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1273 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1274 S_008F0C_ELEMENT_SIZE(0) |
1275 S_008F0C_INDEX_STRIDE(0) |
1276 S_008F0C_ADD_TID_ENABLE(false);
1279 /* VS entry for GS->VS ring */
1280 /* stride 0, num records - size, elsize0,
1283 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32)|
1284 S_008F04_STRIDE(0) |
1285 S_008F04_SWIZZLE_ENABLE(false);
1286 desc
[2] = gsvs_ring_size
;
1287 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1288 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1289 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1290 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1291 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1292 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1293 S_008F0C_ELEMENT_SIZE(0) |
1294 S_008F0C_INDEX_STRIDE(0) |
1295 S_008F0C_ADD_TID_ENABLE(false);
1298 /* stride gsvs_itemsize, num records 64
1299 elsize 4, index stride 16 */
1300 /* shader will patch stride and desc[2] */
1302 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32)|
1303 S_008F04_STRIDE(0) |
1304 S_008F04_SWIZZLE_ENABLE(true);
1306 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1307 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1308 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1309 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1310 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1311 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1312 S_008F0C_ELEMENT_SIZE(1) |
1313 S_008F0C_INDEX_STRIDE(1) |
1314 S_008F0C_ADD_TID_ENABLE(true);
1317 desc
[0] = tess_factor_va
;
1318 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va
>> 32) |
1319 S_008F04_STRIDE(0) |
1320 S_008F04_SWIZZLE_ENABLE(false);
1321 desc
[2] = tess_factor_ring_size
;
1322 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1323 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1324 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1325 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1326 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1327 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1328 S_008F0C_ELEMENT_SIZE(0) |
1329 S_008F0C_INDEX_STRIDE(0) |
1330 S_008F0C_ADD_TID_ENABLE(false);
1333 desc
[0] = tess_offchip_va
;
1334 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va
>> 32) |
1335 S_008F04_STRIDE(0) |
1336 S_008F04_SWIZZLE_ENABLE(false);
1337 desc
[2] = tess_offchip_ring_size
;
1338 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1339 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1340 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1341 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1342 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1343 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1344 S_008F0C_ELEMENT_SIZE(0) |
1345 S_008F0C_INDEX_STRIDE(0) |
1346 S_008F0C_ADD_TID_ENABLE(false);
1349 /* add sample positions after all rings */
1350 memcpy(desc
, queue
->device
->sample_locations_1x
, 8);
1352 memcpy(desc
, queue
->device
->sample_locations_2x
, 16);
1354 memcpy(desc
, queue
->device
->sample_locations_4x
, 32);
1356 memcpy(desc
, queue
->device
->sample_locations_8x
, 64);
1358 memcpy(desc
, queue
->device
->sample_locations_16x
, 128);
1362 radv_get_hs_offchip_param(struct radv_device
*device
, uint32_t *max_offchip_buffers_p
)
1364 bool double_offchip_buffers
= device
->physical_device
->rad_info
.chip_class
>= CIK
&&
1365 device
->physical_device
->rad_info
.family
!= CHIP_CARRIZO
&&
1366 device
->physical_device
->rad_info
.family
!= CHIP_STONEY
;
1367 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
1368 unsigned max_offchip_buffers
= max_offchip_buffers_per_se
*
1369 device
->physical_device
->rad_info
.max_se
;
1370 unsigned offchip_granularity
;
1371 unsigned hs_offchip_param
;
1372 switch (device
->tess_offchip_block_dw_size
) {
1377 offchip_granularity
= V_03093C_X_8K_DWORDS
;
1380 offchip_granularity
= V_03093C_X_4K_DWORDS
;
1384 switch (device
->physical_device
->rad_info
.chip_class
) {
1386 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
1392 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
1396 *max_offchip_buffers_p
= max_offchip_buffers
;
1397 if (device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1398 if (device
->physical_device
->rad_info
.chip_class
>= VI
)
1399 --max_offchip_buffers
;
1401 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
1402 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
1405 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
1407 return hs_offchip_param
;
1411 radv_get_preamble_cs(struct radv_queue
*queue
,
1412 uint32_t scratch_size
,
1413 uint32_t compute_scratch_size
,
1414 uint32_t esgs_ring_size
,
1415 uint32_t gsvs_ring_size
,
1416 bool needs_tess_rings
,
1417 bool needs_sample_positions
,
1418 struct radeon_winsys_cs
**initial_full_flush_preamble_cs
,
1419 struct radeon_winsys_cs
**initial_preamble_cs
,
1420 struct radeon_winsys_cs
**continue_preamble_cs
)
1422 struct radeon_winsys_bo
*scratch_bo
= NULL
;
1423 struct radeon_winsys_bo
*descriptor_bo
= NULL
;
1424 struct radeon_winsys_bo
*compute_scratch_bo
= NULL
;
1425 struct radeon_winsys_bo
*esgs_ring_bo
= NULL
;
1426 struct radeon_winsys_bo
*gsvs_ring_bo
= NULL
;
1427 struct radeon_winsys_bo
*tess_factor_ring_bo
= NULL
;
1428 struct radeon_winsys_bo
*tess_offchip_ring_bo
= NULL
;
1429 struct radeon_winsys_cs
*dest_cs
[3] = {0};
1430 bool add_tess_rings
= false, add_sample_positions
= false;
1431 unsigned tess_factor_ring_size
= 0, tess_offchip_ring_size
= 0;
1432 unsigned max_offchip_buffers
;
1433 unsigned hs_offchip_param
= 0;
1434 uint32_t ring_bo_flags
= RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
;
1435 if (!queue
->has_tess_rings
) {
1436 if (needs_tess_rings
)
1437 add_tess_rings
= true;
1439 if (!queue
->has_sample_positions
) {
1440 if (needs_sample_positions
)
1441 add_sample_positions
= true;
1443 tess_factor_ring_size
= 32768 * queue
->device
->physical_device
->rad_info
.max_se
;
1444 hs_offchip_param
= radv_get_hs_offchip_param(queue
->device
,
1445 &max_offchip_buffers
);
1446 tess_offchip_ring_size
= max_offchip_buffers
*
1447 queue
->device
->tess_offchip_block_dw_size
* 4;
1449 if (scratch_size
<= queue
->scratch_size
&&
1450 compute_scratch_size
<= queue
->compute_scratch_size
&&
1451 esgs_ring_size
<= queue
->esgs_ring_size
&&
1452 gsvs_ring_size
<= queue
->gsvs_ring_size
&&
1453 !add_tess_rings
&& !add_sample_positions
&&
1454 queue
->initial_preamble_cs
) {
1455 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
1456 *initial_preamble_cs
= queue
->initial_preamble_cs
;
1457 *continue_preamble_cs
= queue
->continue_preamble_cs
;
1458 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
1459 *continue_preamble_cs
= NULL
;
1463 if (scratch_size
> queue
->scratch_size
) {
1464 scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1472 scratch_bo
= queue
->scratch_bo
;
1474 if (compute_scratch_size
> queue
->compute_scratch_size
) {
1475 compute_scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1476 compute_scratch_size
,
1480 if (!compute_scratch_bo
)
1484 compute_scratch_bo
= queue
->compute_scratch_bo
;
1486 if (esgs_ring_size
> queue
->esgs_ring_size
) {
1487 esgs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1495 esgs_ring_bo
= queue
->esgs_ring_bo
;
1496 esgs_ring_size
= queue
->esgs_ring_size
;
1499 if (gsvs_ring_size
> queue
->gsvs_ring_size
) {
1500 gsvs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1508 gsvs_ring_bo
= queue
->gsvs_ring_bo
;
1509 gsvs_ring_size
= queue
->gsvs_ring_size
;
1512 if (add_tess_rings
) {
1513 tess_factor_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1514 tess_factor_ring_size
,
1518 if (!tess_factor_ring_bo
)
1520 tess_offchip_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1521 tess_offchip_ring_size
,
1525 if (!tess_offchip_ring_bo
)
1528 tess_factor_ring_bo
= queue
->tess_factor_ring_bo
;
1529 tess_offchip_ring_bo
= queue
->tess_offchip_ring_bo
;
1532 if (scratch_bo
!= queue
->scratch_bo
||
1533 esgs_ring_bo
!= queue
->esgs_ring_bo
||
1534 gsvs_ring_bo
!= queue
->gsvs_ring_bo
||
1535 tess_factor_ring_bo
!= queue
->tess_factor_ring_bo
||
1536 tess_offchip_ring_bo
!= queue
->tess_offchip_ring_bo
|| add_sample_positions
) {
1538 if (gsvs_ring_bo
|| esgs_ring_bo
||
1539 tess_factor_ring_bo
|| tess_offchip_ring_bo
|| add_sample_positions
) {
1540 size
= 112; /* 2 dword + 2 padding + 4 dword * 6 */
1541 if (add_sample_positions
)
1542 size
+= 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1544 else if (scratch_bo
)
1545 size
= 8; /* 2 dword */
1547 descriptor_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1551 RADEON_FLAG_CPU_ACCESS
|RADEON_FLAG_NO_INTERPROCESS_SHARING
);
1555 descriptor_bo
= queue
->descriptor_bo
;
1557 for(int i
= 0; i
< 3; ++i
) {
1558 struct radeon_winsys_cs
*cs
= NULL
;
1559 cs
= queue
->device
->ws
->cs_create(queue
->device
->ws
,
1560 queue
->queue_family_index
? RING_COMPUTE
: RING_GFX
);
1567 radv_cs_add_buffer(queue
->device
->ws
, cs
, scratch_bo
, 8);
1570 radv_cs_add_buffer(queue
->device
->ws
, cs
, esgs_ring_bo
, 8);
1573 radv_cs_add_buffer(queue
->device
->ws
, cs
, gsvs_ring_bo
, 8);
1575 if (tess_factor_ring_bo
)
1576 radv_cs_add_buffer(queue
->device
->ws
, cs
, tess_factor_ring_bo
, 8);
1578 if (tess_offchip_ring_bo
)
1579 radv_cs_add_buffer(queue
->device
->ws
, cs
, tess_offchip_ring_bo
, 8);
1582 radv_cs_add_buffer(queue
->device
->ws
, cs
, descriptor_bo
, 8);
1584 if (descriptor_bo
!= queue
->descriptor_bo
) {
1585 uint32_t *map
= (uint32_t*)queue
->device
->ws
->buffer_map(descriptor_bo
);
1588 uint64_t scratch_va
= radv_buffer_get_va(scratch_bo
);
1589 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
1590 S_008F04_SWIZZLE_ENABLE(1);
1591 map
[0] = scratch_va
;
1595 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_factor_ring_bo
|| tess_offchip_ring_bo
||
1596 add_sample_positions
)
1597 fill_geom_tess_rings(queue
, map
, add_sample_positions
,
1598 esgs_ring_size
, esgs_ring_bo
,
1599 gsvs_ring_size
, gsvs_ring_bo
,
1600 tess_factor_ring_size
, tess_factor_ring_bo
,
1601 tess_offchip_ring_size
, tess_offchip_ring_bo
);
1603 queue
->device
->ws
->buffer_unmap(descriptor_bo
);
1606 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_factor_ring_bo
|| tess_offchip_ring_bo
) {
1607 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1608 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
1609 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1610 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
1613 if (esgs_ring_bo
|| gsvs_ring_bo
) {
1614 if (queue
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1615 radeon_set_uconfig_reg_seq(cs
, R_030900_VGT_ESGS_RING_SIZE
, 2);
1616 radeon_emit(cs
, esgs_ring_size
>> 8);
1617 radeon_emit(cs
, gsvs_ring_size
>> 8);
1619 radeon_set_config_reg_seq(cs
, R_0088C8_VGT_ESGS_RING_SIZE
, 2);
1620 radeon_emit(cs
, esgs_ring_size
>> 8);
1621 radeon_emit(cs
, gsvs_ring_size
>> 8);
1625 if (tess_factor_ring_bo
) {
1626 uint64_t tf_va
= radv_buffer_get_va(tess_factor_ring_bo
);
1627 if (queue
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1628 radeon_set_uconfig_reg(cs
, R_030938_VGT_TF_RING_SIZE
,
1629 S_030938_SIZE(tess_factor_ring_size
/ 4));
1630 radeon_set_uconfig_reg(cs
, R_030940_VGT_TF_MEMORY_BASE
,
1632 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1633 radeon_set_uconfig_reg(cs
, R_030944_VGT_TF_MEMORY_BASE_HI
,
1636 radeon_set_uconfig_reg(cs
, R_03093C_VGT_HS_OFFCHIP_PARAM
, hs_offchip_param
);
1638 radeon_set_config_reg(cs
, R_008988_VGT_TF_RING_SIZE
,
1639 S_008988_SIZE(tess_factor_ring_size
/ 4));
1640 radeon_set_config_reg(cs
, R_0089B8_VGT_TF_MEMORY_BASE
,
1642 radeon_set_config_reg(cs
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
1647 if (descriptor_bo
) {
1648 uint64_t va
= radv_buffer_get_va(descriptor_bo
);
1649 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1650 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
1651 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
1652 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
1653 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
1655 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
1656 radeon_set_sh_reg_seq(cs
, regs
[i
], 2);
1657 radeon_emit(cs
, va
);
1658 radeon_emit(cs
, va
>> 32);
1661 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
1662 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
1663 R_00B230_SPI_SHADER_USER_DATA_GS_0
,
1664 R_00B330_SPI_SHADER_USER_DATA_ES_0
,
1665 R_00B430_SPI_SHADER_USER_DATA_HS_0
,
1666 R_00B530_SPI_SHADER_USER_DATA_LS_0
};
1668 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
1669 radeon_set_sh_reg_seq(cs
, regs
[i
], 2);
1670 radeon_emit(cs
, va
);
1671 radeon_emit(cs
, va
>> 32);
1676 if (compute_scratch_bo
) {
1677 uint64_t scratch_va
= radv_buffer_get_va(compute_scratch_bo
);
1678 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
1679 S_008F04_SWIZZLE_ENABLE(1);
1681 radv_cs_add_buffer(queue
->device
->ws
, cs
, compute_scratch_bo
, 8);
1683 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, 2);
1684 radeon_emit(cs
, scratch_va
);
1685 radeon_emit(cs
, rsrc1
);
1689 si_cs_emit_cache_flush(cs
,
1691 queue
->device
->physical_device
->rad_info
.chip_class
,
1693 queue
->queue_family_index
== RING_COMPUTE
&&
1694 queue
->device
->physical_device
->rad_info
.chip_class
>= CIK
,
1695 (queue
->queue_family_index
== RADV_QUEUE_COMPUTE
? RADV_CMD_FLAG_CS_PARTIAL_FLUSH
: (RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
)) |
1696 RADV_CMD_FLAG_INV_ICACHE
|
1697 RADV_CMD_FLAG_INV_SMEM_L1
|
1698 RADV_CMD_FLAG_INV_VMEM_L1
|
1699 RADV_CMD_FLAG_INV_GLOBAL_L2
);
1700 } else if (i
== 1) {
1701 si_cs_emit_cache_flush(cs
,
1703 queue
->device
->physical_device
->rad_info
.chip_class
,
1705 queue
->queue_family_index
== RING_COMPUTE
&&
1706 queue
->device
->physical_device
->rad_info
.chip_class
>= CIK
,
1707 RADV_CMD_FLAG_INV_ICACHE
|
1708 RADV_CMD_FLAG_INV_SMEM_L1
|
1709 RADV_CMD_FLAG_INV_VMEM_L1
|
1710 RADV_CMD_FLAG_INV_GLOBAL_L2
);
1713 if (!queue
->device
->ws
->cs_finalize(cs
))
1717 if (queue
->initial_full_flush_preamble_cs
)
1718 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
1720 if (queue
->initial_preamble_cs
)
1721 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
1723 if (queue
->continue_preamble_cs
)
1724 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
1726 queue
->initial_full_flush_preamble_cs
= dest_cs
[0];
1727 queue
->initial_preamble_cs
= dest_cs
[1];
1728 queue
->continue_preamble_cs
= dest_cs
[2];
1730 if (scratch_bo
!= queue
->scratch_bo
) {
1731 if (queue
->scratch_bo
)
1732 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
1733 queue
->scratch_bo
= scratch_bo
;
1734 queue
->scratch_size
= scratch_size
;
1737 if (compute_scratch_bo
!= queue
->compute_scratch_bo
) {
1738 if (queue
->compute_scratch_bo
)
1739 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
1740 queue
->compute_scratch_bo
= compute_scratch_bo
;
1741 queue
->compute_scratch_size
= compute_scratch_size
;
1744 if (esgs_ring_bo
!= queue
->esgs_ring_bo
) {
1745 if (queue
->esgs_ring_bo
)
1746 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
1747 queue
->esgs_ring_bo
= esgs_ring_bo
;
1748 queue
->esgs_ring_size
= esgs_ring_size
;
1751 if (gsvs_ring_bo
!= queue
->gsvs_ring_bo
) {
1752 if (queue
->gsvs_ring_bo
)
1753 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
1754 queue
->gsvs_ring_bo
= gsvs_ring_bo
;
1755 queue
->gsvs_ring_size
= gsvs_ring_size
;
1758 if (tess_factor_ring_bo
!= queue
->tess_factor_ring_bo
) {
1759 queue
->tess_factor_ring_bo
= tess_factor_ring_bo
;
1762 if (tess_offchip_ring_bo
!= queue
->tess_offchip_ring_bo
) {
1763 queue
->tess_offchip_ring_bo
= tess_offchip_ring_bo
;
1764 queue
->has_tess_rings
= true;
1767 if (descriptor_bo
!= queue
->descriptor_bo
) {
1768 if (queue
->descriptor_bo
)
1769 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
1771 queue
->descriptor_bo
= descriptor_bo
;
1774 if (add_sample_positions
)
1775 queue
->has_sample_positions
= true;
1777 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
1778 *initial_preamble_cs
= queue
->initial_preamble_cs
;
1779 *continue_preamble_cs
= queue
->continue_preamble_cs
;
1780 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
1781 *continue_preamble_cs
= NULL
;
1784 for (int i
= 0; i
< ARRAY_SIZE(dest_cs
); ++i
)
1786 queue
->device
->ws
->cs_destroy(dest_cs
[i
]);
1787 if (descriptor_bo
&& descriptor_bo
!= queue
->descriptor_bo
)
1788 queue
->device
->ws
->buffer_destroy(descriptor_bo
);
1789 if (scratch_bo
&& scratch_bo
!= queue
->scratch_bo
)
1790 queue
->device
->ws
->buffer_destroy(scratch_bo
);
1791 if (compute_scratch_bo
&& compute_scratch_bo
!= queue
->compute_scratch_bo
)
1792 queue
->device
->ws
->buffer_destroy(compute_scratch_bo
);
1793 if (esgs_ring_bo
&& esgs_ring_bo
!= queue
->esgs_ring_bo
)
1794 queue
->device
->ws
->buffer_destroy(esgs_ring_bo
);
1795 if (gsvs_ring_bo
&& gsvs_ring_bo
!= queue
->gsvs_ring_bo
)
1796 queue
->device
->ws
->buffer_destroy(gsvs_ring_bo
);
1797 if (tess_factor_ring_bo
&& tess_factor_ring_bo
!= queue
->tess_factor_ring_bo
)
1798 queue
->device
->ws
->buffer_destroy(tess_factor_ring_bo
);
1799 if (tess_offchip_ring_bo
&& tess_offchip_ring_bo
!= queue
->tess_offchip_ring_bo
)
1800 queue
->device
->ws
->buffer_destroy(tess_offchip_ring_bo
);
1801 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1804 static VkResult
radv_alloc_sem_counts(struct radv_winsys_sem_counts
*counts
,
1806 const VkSemaphore
*sems
,
1809 int syncobj_idx
= 0, sem_idx
= 0;
1813 for (uint32_t i
= 0; i
< num_sems
; i
++) {
1814 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
1816 if (sem
->temp_syncobj
|| sem
->syncobj
)
1817 counts
->syncobj_count
++;
1819 counts
->sem_count
++;
1822 if (counts
->syncobj_count
) {
1823 counts
->syncobj
= (uint32_t *)malloc(sizeof(uint32_t) * counts
->syncobj_count
);
1824 if (!counts
->syncobj
)
1825 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1828 if (counts
->sem_count
) {
1829 counts
->sem
= (struct radeon_winsys_sem
**)malloc(sizeof(struct radeon_winsys_sem
*) * counts
->sem_count
);
1831 free(counts
->syncobj
);
1832 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1836 for (uint32_t i
= 0; i
< num_sems
; i
++) {
1837 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
1839 if (sem
->temp_syncobj
) {
1840 counts
->syncobj
[syncobj_idx
++] = sem
->temp_syncobj
;
1842 /* after we wait on a temp import - drop it */
1843 sem
->temp_syncobj
= 0;
1846 else if (sem
->syncobj
)
1847 counts
->syncobj
[syncobj_idx
++] = sem
->syncobj
;
1850 counts
->sem
[sem_idx
++] = sem
->sem
;
1857 void radv_free_sem_info(struct radv_winsys_sem_info
*sem_info
)
1859 free(sem_info
->wait
.syncobj
);
1860 free(sem_info
->wait
.sem
);
1861 free(sem_info
->signal
.syncobj
);
1862 free(sem_info
->signal
.sem
);
1865 VkResult
radv_alloc_sem_info(struct radv_winsys_sem_info
*sem_info
,
1867 const VkSemaphore
*wait_sems
,
1868 int num_signal_sems
,
1869 const VkSemaphore
*signal_sems
)
1872 memset(sem_info
, 0, sizeof(*sem_info
));
1874 ret
= radv_alloc_sem_counts(&sem_info
->wait
, num_wait_sems
, wait_sems
, true);
1877 ret
= radv_alloc_sem_counts(&sem_info
->signal
, num_signal_sems
, signal_sems
, false);
1879 radv_free_sem_info(sem_info
);
1881 /* caller can override these */
1882 sem_info
->cs_emit_wait
= true;
1883 sem_info
->cs_emit_signal
= true;
1887 VkResult
radv_QueueSubmit(
1889 uint32_t submitCount
,
1890 const VkSubmitInfo
* pSubmits
,
1893 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
1894 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
1895 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
1896 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
1898 uint32_t max_cs_submission
= queue
->device
->trace_bo
? 1 : UINT32_MAX
;
1899 uint32_t scratch_size
= 0;
1900 uint32_t compute_scratch_size
= 0;
1901 uint32_t esgs_ring_size
= 0, gsvs_ring_size
= 0;
1902 struct radeon_winsys_cs
*initial_preamble_cs
= NULL
, *initial_flush_preamble_cs
= NULL
, *continue_preamble_cs
= NULL
;
1904 bool fence_emitted
= false;
1905 bool tess_rings_needed
= false;
1906 bool sample_positions_needed
= false;
1908 /* Do this first so failing to allocate scratch buffers can't result in
1909 * partially executed submissions. */
1910 for (uint32_t i
= 0; i
< submitCount
; i
++) {
1911 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
1912 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
1913 pSubmits
[i
].pCommandBuffers
[j
]);
1915 scratch_size
= MAX2(scratch_size
, cmd_buffer
->scratch_size_needed
);
1916 compute_scratch_size
= MAX2(compute_scratch_size
,
1917 cmd_buffer
->compute_scratch_size_needed
);
1918 esgs_ring_size
= MAX2(esgs_ring_size
, cmd_buffer
->esgs_ring_size_needed
);
1919 gsvs_ring_size
= MAX2(gsvs_ring_size
, cmd_buffer
->gsvs_ring_size_needed
);
1920 tess_rings_needed
|= cmd_buffer
->tess_rings_needed
;
1921 sample_positions_needed
|= cmd_buffer
->sample_positions_needed
;
1925 result
= radv_get_preamble_cs(queue
, scratch_size
, compute_scratch_size
,
1926 esgs_ring_size
, gsvs_ring_size
, tess_rings_needed
,
1927 sample_positions_needed
, &initial_flush_preamble_cs
,
1928 &initial_preamble_cs
, &continue_preamble_cs
);
1929 if (result
!= VK_SUCCESS
)
1932 for (uint32_t i
= 0; i
< submitCount
; i
++) {
1933 struct radeon_winsys_cs
**cs_array
;
1934 bool do_flush
= !i
|| pSubmits
[i
].pWaitDstStageMask
;
1935 bool can_patch
= true;
1937 struct radv_winsys_sem_info sem_info
;
1939 result
= radv_alloc_sem_info(&sem_info
,
1940 pSubmits
[i
].waitSemaphoreCount
,
1941 pSubmits
[i
].pWaitSemaphores
,
1942 pSubmits
[i
].signalSemaphoreCount
,
1943 pSubmits
[i
].pSignalSemaphores
);
1944 if (result
!= VK_SUCCESS
)
1947 if (!pSubmits
[i
].commandBufferCount
) {
1948 if (pSubmits
[i
].waitSemaphoreCount
|| pSubmits
[i
].signalSemaphoreCount
) {
1949 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
1950 &queue
->device
->empty_cs
[queue
->queue_family_index
],
1955 radv_loge("failed to submit CS %d\n", i
);
1958 fence_emitted
= true;
1960 radv_free_sem_info(&sem_info
);
1964 cs_array
= malloc(sizeof(struct radeon_winsys_cs
*) *
1965 (pSubmits
[i
].commandBufferCount
));
1967 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
1968 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
1969 pSubmits
[i
].pCommandBuffers
[j
]);
1970 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1972 cs_array
[j
] = cmd_buffer
->cs
;
1973 if ((cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT
))
1977 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
+= advance
) {
1978 struct radeon_winsys_cs
*initial_preamble
= (do_flush
&& !j
) ? initial_flush_preamble_cs
: initial_preamble_cs
;
1979 advance
= MIN2(max_cs_submission
,
1980 pSubmits
[i
].commandBufferCount
- j
);
1982 if (queue
->device
->trace_bo
)
1983 *queue
->device
->trace_id_ptr
= 0;
1985 sem_info
.cs_emit_wait
= j
== 0;
1986 sem_info
.cs_emit_signal
= j
+ advance
== pSubmits
[i
].commandBufferCount
;
1988 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, cs_array
+ j
,
1989 advance
, initial_preamble
, continue_preamble_cs
,
1991 can_patch
, base_fence
);
1994 radv_loge("failed to submit CS %d\n", i
);
1997 fence_emitted
= true;
1998 if (queue
->device
->trace_bo
) {
1999 radv_check_gpu_hangs(queue
, cs_array
[j
]);
2003 radv_free_sem_info(&sem_info
);
2008 if (!fence_emitted
) {
2009 struct radv_winsys_sem_info sem_info
= {0};
2010 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
2011 &queue
->device
->empty_cs
[queue
->queue_family_index
],
2012 1, NULL
, NULL
, &sem_info
,
2015 fence
->submitted
= true;
2021 VkResult
radv_QueueWaitIdle(
2024 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
2026 queue
->device
->ws
->ctx_wait_idle(queue
->hw_ctx
,
2027 radv_queue_family_to_ring(queue
->queue_family_index
),
2032 VkResult
radv_DeviceWaitIdle(
2035 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2037 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
2038 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++) {
2039 radv_QueueWaitIdle(radv_queue_to_handle(&device
->queues
[i
][q
]));
2045 PFN_vkVoidFunction
radv_GetInstanceProcAddr(
2046 VkInstance instance
,
2049 return radv_lookup_entrypoint(pName
);
2052 /* The loader wants us to expose a second GetInstanceProcAddr function
2053 * to work around certain LD_PRELOAD issues seen in apps.
2056 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
2057 VkInstance instance
,
2061 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
2062 VkInstance instance
,
2065 return radv_GetInstanceProcAddr(instance
, pName
);
2068 PFN_vkVoidFunction
radv_GetDeviceProcAddr(
2072 return radv_lookup_entrypoint(pName
);
2075 bool radv_get_memory_fd(struct radv_device
*device
,
2076 struct radv_device_memory
*memory
,
2079 struct radeon_bo_metadata metadata
;
2081 if (memory
->image
) {
2082 radv_init_metadata(device
, memory
->image
, &metadata
);
2083 device
->ws
->buffer_set_metadata(memory
->bo
, &metadata
);
2086 return device
->ws
->buffer_get_fd(device
->ws
, memory
->bo
,
2090 VkResult
radv_alloc_memory(VkDevice _device
,
2091 const VkMemoryAllocateInfo
* pAllocateInfo
,
2092 const VkAllocationCallbacks
* pAllocator
,
2093 enum radv_mem_flags_bits mem_flags
,
2094 VkDeviceMemory
* pMem
)
2096 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2097 struct radv_device_memory
*mem
;
2099 enum radeon_bo_domain domain
;
2101 enum radv_mem_type mem_type_index
= device
->physical_device
->mem_type_indices
[pAllocateInfo
->memoryTypeIndex
];
2103 assert(pAllocateInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO
);
2105 if (pAllocateInfo
->allocationSize
== 0) {
2106 /* Apparently, this is allowed */
2107 *pMem
= VK_NULL_HANDLE
;
2111 const VkImportMemoryFdInfoKHR
*import_info
=
2112 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_FD_INFO_KHR
);
2113 const VkMemoryDedicatedAllocateInfoKHR
*dedicate_info
=
2114 vk_find_struct_const(pAllocateInfo
->pNext
, MEMORY_DEDICATED_ALLOCATE_INFO_KHR
);
2116 mem
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*mem
), 8,
2117 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2119 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2121 if (dedicate_info
) {
2122 mem
->image
= radv_image_from_handle(dedicate_info
->image
);
2123 mem
->buffer
= radv_buffer_from_handle(dedicate_info
->buffer
);
2130 assert(import_info
->handleType
==
2131 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
);
2132 mem
->bo
= device
->ws
->buffer_from_fd(device
->ws
, import_info
->fd
,
2135 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR
;
2138 close(import_info
->fd
);
2143 uint64_t alloc_size
= align_u64(pAllocateInfo
->allocationSize
, 4096);
2144 if (mem_type_index
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
||
2145 mem_type_index
== RADV_MEM_TYPE_GTT_CACHED
)
2146 domain
= RADEON_DOMAIN_GTT
;
2148 domain
= RADEON_DOMAIN_VRAM
;
2150 if (mem_type_index
== RADV_MEM_TYPE_VRAM
)
2151 flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
2153 flags
|= RADEON_FLAG_CPU_ACCESS
;
2155 if (mem_type_index
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
)
2156 flags
|= RADEON_FLAG_GTT_WC
;
2158 if (mem_flags
& RADV_MEM_IMPLICIT_SYNC
)
2159 flags
|= RADEON_FLAG_IMPLICIT_SYNC
;
2161 if (!dedicate_info
&& !import_info
)
2162 flags
|= RADEON_FLAG_NO_INTERPROCESS_SHARING
;
2164 mem
->bo
= device
->ws
->buffer_create(device
->ws
, alloc_size
, device
->physical_device
->rad_info
.max_alignment
,
2168 result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2171 mem
->type_index
= mem_type_index
;
2173 *pMem
= radv_device_memory_to_handle(mem
);
2178 vk_free2(&device
->alloc
, pAllocator
, mem
);
2183 VkResult
radv_AllocateMemory(
2185 const VkMemoryAllocateInfo
* pAllocateInfo
,
2186 const VkAllocationCallbacks
* pAllocator
,
2187 VkDeviceMemory
* pMem
)
2189 return radv_alloc_memory(_device
, pAllocateInfo
, pAllocator
, 0, pMem
);
2192 void radv_FreeMemory(
2194 VkDeviceMemory _mem
,
2195 const VkAllocationCallbacks
* pAllocator
)
2197 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2198 RADV_FROM_HANDLE(radv_device_memory
, mem
, _mem
);
2203 device
->ws
->buffer_destroy(mem
->bo
);
2206 vk_free2(&device
->alloc
, pAllocator
, mem
);
2209 VkResult
radv_MapMemory(
2211 VkDeviceMemory _memory
,
2212 VkDeviceSize offset
,
2214 VkMemoryMapFlags flags
,
2217 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2218 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
2225 *ppData
= device
->ws
->buffer_map(mem
->bo
);
2231 return VK_ERROR_MEMORY_MAP_FAILED
;
2234 void radv_UnmapMemory(
2236 VkDeviceMemory _memory
)
2238 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2239 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
2244 device
->ws
->buffer_unmap(mem
->bo
);
2247 VkResult
radv_FlushMappedMemoryRanges(
2249 uint32_t memoryRangeCount
,
2250 const VkMappedMemoryRange
* pMemoryRanges
)
2255 VkResult
radv_InvalidateMappedMemoryRanges(
2257 uint32_t memoryRangeCount
,
2258 const VkMappedMemoryRange
* pMemoryRanges
)
2263 void radv_GetBufferMemoryRequirements(
2266 VkMemoryRequirements
* pMemoryRequirements
)
2268 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2269 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
2271 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
2273 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
2274 pMemoryRequirements
->alignment
= 4096;
2276 pMemoryRequirements
->alignment
= 16;
2278 pMemoryRequirements
->size
= align64(buffer
->size
, pMemoryRequirements
->alignment
);
2281 void radv_GetBufferMemoryRequirements2KHR(
2283 const VkBufferMemoryRequirementsInfo2KHR
* pInfo
,
2284 VkMemoryRequirements2KHR
* pMemoryRequirements
)
2286 radv_GetBufferMemoryRequirements(device
, pInfo
->buffer
,
2287 &pMemoryRequirements
->memoryRequirements
);
2288 RADV_FROM_HANDLE(radv_buffer
, buffer
, pInfo
->buffer
);
2289 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
2290 switch (ext
->sType
) {
2291 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR
: {
2292 VkMemoryDedicatedRequirementsKHR
*req
=
2293 (VkMemoryDedicatedRequirementsKHR
*) ext
;
2294 req
->requiresDedicatedAllocation
= buffer
->shareable
;
2295 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
2304 void radv_GetImageMemoryRequirements(
2307 VkMemoryRequirements
* pMemoryRequirements
)
2309 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2310 RADV_FROM_HANDLE(radv_image
, image
, _image
);
2312 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
2314 pMemoryRequirements
->size
= image
->size
;
2315 pMemoryRequirements
->alignment
= image
->alignment
;
2318 void radv_GetImageMemoryRequirements2KHR(
2320 const VkImageMemoryRequirementsInfo2KHR
* pInfo
,
2321 VkMemoryRequirements2KHR
* pMemoryRequirements
)
2323 radv_GetImageMemoryRequirements(device
, pInfo
->image
,
2324 &pMemoryRequirements
->memoryRequirements
);
2326 RADV_FROM_HANDLE(radv_image
, image
, pInfo
->image
);
2328 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
2329 switch (ext
->sType
) {
2330 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR
: {
2331 VkMemoryDedicatedRequirementsKHR
*req
=
2332 (VkMemoryDedicatedRequirementsKHR
*) ext
;
2333 req
->requiresDedicatedAllocation
= image
->shareable
;
2334 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
2343 void radv_GetImageSparseMemoryRequirements(
2346 uint32_t* pSparseMemoryRequirementCount
,
2347 VkSparseImageMemoryRequirements
* pSparseMemoryRequirements
)
2352 void radv_GetImageSparseMemoryRequirements2KHR(
2354 const VkImageSparseMemoryRequirementsInfo2KHR
* pInfo
,
2355 uint32_t* pSparseMemoryRequirementCount
,
2356 VkSparseImageMemoryRequirements2KHR
* pSparseMemoryRequirements
)
2361 void radv_GetDeviceMemoryCommitment(
2363 VkDeviceMemory memory
,
2364 VkDeviceSize
* pCommittedMemoryInBytes
)
2366 *pCommittedMemoryInBytes
= 0;
2369 VkResult
radv_BindBufferMemory2KHR(VkDevice device
,
2370 uint32_t bindInfoCount
,
2371 const VkBindBufferMemoryInfoKHR
*pBindInfos
)
2373 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
2374 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
2375 RADV_FROM_HANDLE(radv_buffer
, buffer
, pBindInfos
[i
].buffer
);
2378 buffer
->bo
= mem
->bo
;
2379 buffer
->offset
= pBindInfos
[i
].memoryOffset
;
2387 VkResult
radv_BindBufferMemory(
2390 VkDeviceMemory memory
,
2391 VkDeviceSize memoryOffset
)
2393 const VkBindBufferMemoryInfoKHR info
= {
2394 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR
,
2397 .memoryOffset
= memoryOffset
2400 return radv_BindBufferMemory2KHR(device
, 1, &info
);
2403 VkResult
radv_BindImageMemory2KHR(VkDevice device
,
2404 uint32_t bindInfoCount
,
2405 const VkBindImageMemoryInfoKHR
*pBindInfos
)
2407 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
2408 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
2409 RADV_FROM_HANDLE(radv_image
, image
, pBindInfos
[i
].image
);
2412 image
->bo
= mem
->bo
;
2413 image
->offset
= pBindInfos
[i
].memoryOffset
;
2423 VkResult
radv_BindImageMemory(
2426 VkDeviceMemory memory
,
2427 VkDeviceSize memoryOffset
)
2429 const VkBindImageMemoryInfoKHR info
= {
2430 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR
,
2433 .memoryOffset
= memoryOffset
2436 return radv_BindImageMemory2KHR(device
, 1, &info
);
2441 radv_sparse_buffer_bind_memory(struct radv_device
*device
,
2442 const VkSparseBufferMemoryBindInfo
*bind
)
2444 RADV_FROM_HANDLE(radv_buffer
, buffer
, bind
->buffer
);
2446 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
2447 struct radv_device_memory
*mem
= NULL
;
2449 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
2450 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
2452 device
->ws
->buffer_virtual_bind(buffer
->bo
,
2453 bind
->pBinds
[i
].resourceOffset
,
2454 bind
->pBinds
[i
].size
,
2455 mem
? mem
->bo
: NULL
,
2456 bind
->pBinds
[i
].memoryOffset
);
2461 radv_sparse_image_opaque_bind_memory(struct radv_device
*device
,
2462 const VkSparseImageOpaqueMemoryBindInfo
*bind
)
2464 RADV_FROM_HANDLE(radv_image
, image
, bind
->image
);
2466 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
2467 struct radv_device_memory
*mem
= NULL
;
2469 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
2470 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
2472 device
->ws
->buffer_virtual_bind(image
->bo
,
2473 bind
->pBinds
[i
].resourceOffset
,
2474 bind
->pBinds
[i
].size
,
2475 mem
? mem
->bo
: NULL
,
2476 bind
->pBinds
[i
].memoryOffset
);
2480 VkResult
radv_QueueBindSparse(
2482 uint32_t bindInfoCount
,
2483 const VkBindSparseInfo
* pBindInfo
,
2486 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2487 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
2488 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
2489 bool fence_emitted
= false;
2491 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
2492 struct radv_winsys_sem_info sem_info
;
2493 for (uint32_t j
= 0; j
< pBindInfo
[i
].bufferBindCount
; ++j
) {
2494 radv_sparse_buffer_bind_memory(queue
->device
,
2495 pBindInfo
[i
].pBufferBinds
+ j
);
2498 for (uint32_t j
= 0; j
< pBindInfo
[i
].imageOpaqueBindCount
; ++j
) {
2499 radv_sparse_image_opaque_bind_memory(queue
->device
,
2500 pBindInfo
[i
].pImageOpaqueBinds
+ j
);
2504 result
= radv_alloc_sem_info(&sem_info
,
2505 pBindInfo
[i
].waitSemaphoreCount
,
2506 pBindInfo
[i
].pWaitSemaphores
,
2507 pBindInfo
[i
].signalSemaphoreCount
,
2508 pBindInfo
[i
].pSignalSemaphores
);
2509 if (result
!= VK_SUCCESS
)
2512 if (pBindInfo
[i
].waitSemaphoreCount
|| pBindInfo
[i
].signalSemaphoreCount
) {
2513 queue
->device
->ws
->cs_submit(queue
->hw_ctx
, queue
->queue_idx
,
2514 &queue
->device
->empty_cs
[queue
->queue_family_index
],
2518 fence_emitted
= true;
2520 fence
->submitted
= true;
2523 radv_free_sem_info(&sem_info
);
2527 if (fence
&& !fence_emitted
) {
2528 fence
->signalled
= true;
2534 VkResult
radv_CreateFence(
2536 const VkFenceCreateInfo
* pCreateInfo
,
2537 const VkAllocationCallbacks
* pAllocator
,
2540 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2541 struct radv_fence
*fence
= vk_alloc2(&device
->alloc
, pAllocator
,
2543 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2546 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2548 memset(fence
, 0, sizeof(*fence
));
2549 fence
->submitted
= false;
2550 fence
->signalled
= !!(pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
);
2551 fence
->fence
= device
->ws
->create_fence();
2552 if (!fence
->fence
) {
2553 vk_free2(&device
->alloc
, pAllocator
, fence
);
2554 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2557 *pFence
= radv_fence_to_handle(fence
);
2562 void radv_DestroyFence(
2565 const VkAllocationCallbacks
* pAllocator
)
2567 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2568 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2572 device
->ws
->destroy_fence(fence
->fence
);
2573 vk_free2(&device
->alloc
, pAllocator
, fence
);
2576 static uint64_t radv_get_absolute_timeout(uint64_t timeout
)
2578 uint64_t current_time
;
2581 clock_gettime(CLOCK_MONOTONIC
, &tv
);
2582 current_time
= tv
.tv_nsec
+ tv
.tv_sec
*1000000000ull;
2584 timeout
= MIN2(UINT64_MAX
- current_time
, timeout
);
2586 return current_time
+ timeout
;
2589 VkResult
radv_WaitForFences(
2591 uint32_t fenceCount
,
2592 const VkFence
* pFences
,
2596 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2597 timeout
= radv_get_absolute_timeout(timeout
);
2599 if (!waitAll
&& fenceCount
> 1) {
2600 fprintf(stderr
, "radv: WaitForFences without waitAll not implemented yet\n");
2603 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
2604 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
2605 bool expired
= false;
2607 if (fence
->signalled
)
2610 if (!fence
->submitted
)
2613 expired
= device
->ws
->fence_wait(device
->ws
, fence
->fence
, true, timeout
);
2617 fence
->signalled
= true;
2623 VkResult
radv_ResetFences(VkDevice device
,
2624 uint32_t fenceCount
,
2625 const VkFence
*pFences
)
2627 for (unsigned i
= 0; i
< fenceCount
; ++i
) {
2628 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
2629 fence
->submitted
= fence
->signalled
= false;
2635 VkResult
radv_GetFenceStatus(VkDevice _device
, VkFence _fence
)
2637 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2638 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2640 if (fence
->signalled
)
2642 if (!fence
->submitted
)
2643 return VK_NOT_READY
;
2645 if (!device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0))
2646 return VK_NOT_READY
;
2652 // Queue semaphore functions
2654 VkResult
radv_CreateSemaphore(
2656 const VkSemaphoreCreateInfo
* pCreateInfo
,
2657 const VkAllocationCallbacks
* pAllocator
,
2658 VkSemaphore
* pSemaphore
)
2660 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2661 const VkExportSemaphoreCreateInfoKHR
*export
=
2662 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_SEMAPHORE_CREATE_INFO_KHR
);
2663 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes
=
2664 export
? export
->handleTypes
: 0;
2666 struct radv_semaphore
*sem
= vk_alloc2(&device
->alloc
, pAllocator
,
2668 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2670 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2672 sem
->temp_syncobj
= 0;
2673 /* create a syncobject if we are going to export this semaphore */
2675 assert (device
->physical_device
->rad_info
.has_syncobj
);
2676 assert (handleTypes
== VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
);
2677 int ret
= device
->ws
->create_syncobj(device
->ws
, &sem
->syncobj
);
2679 vk_free2(&device
->alloc
, pAllocator
, sem
);
2680 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2684 sem
->sem
= device
->ws
->create_sem(device
->ws
);
2686 vk_free2(&device
->alloc
, pAllocator
, sem
);
2687 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2692 *pSemaphore
= radv_semaphore_to_handle(sem
);
2696 void radv_DestroySemaphore(
2698 VkSemaphore _semaphore
,
2699 const VkAllocationCallbacks
* pAllocator
)
2701 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2702 RADV_FROM_HANDLE(radv_semaphore
, sem
, _semaphore
);
2707 device
->ws
->destroy_syncobj(device
->ws
, sem
->syncobj
);
2709 device
->ws
->destroy_sem(sem
->sem
);
2710 vk_free2(&device
->alloc
, pAllocator
, sem
);
2713 VkResult
radv_CreateEvent(
2715 const VkEventCreateInfo
* pCreateInfo
,
2716 const VkAllocationCallbacks
* pAllocator
,
2719 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2720 struct radv_event
*event
= vk_alloc2(&device
->alloc
, pAllocator
,
2722 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2725 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2727 event
->bo
= device
->ws
->buffer_create(device
->ws
, 8, 8,
2729 RADEON_FLAG_VA_UNCACHED
| RADEON_FLAG_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
);
2731 vk_free2(&device
->alloc
, pAllocator
, event
);
2732 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2735 event
->map
= (uint64_t*)device
->ws
->buffer_map(event
->bo
);
2737 *pEvent
= radv_event_to_handle(event
);
2742 void radv_DestroyEvent(
2745 const VkAllocationCallbacks
* pAllocator
)
2747 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2748 RADV_FROM_HANDLE(radv_event
, event
, _event
);
2752 device
->ws
->buffer_destroy(event
->bo
);
2753 vk_free2(&device
->alloc
, pAllocator
, event
);
2756 VkResult
radv_GetEventStatus(
2760 RADV_FROM_HANDLE(radv_event
, event
, _event
);
2762 if (*event
->map
== 1)
2763 return VK_EVENT_SET
;
2764 return VK_EVENT_RESET
;
2767 VkResult
radv_SetEvent(
2771 RADV_FROM_HANDLE(radv_event
, event
, _event
);
2777 VkResult
radv_ResetEvent(
2781 RADV_FROM_HANDLE(radv_event
, event
, _event
);
2787 VkResult
radv_CreateBuffer(
2789 const VkBufferCreateInfo
* pCreateInfo
,
2790 const VkAllocationCallbacks
* pAllocator
,
2793 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2794 struct radv_buffer
*buffer
;
2796 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO
);
2798 buffer
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*buffer
), 8,
2799 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2801 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2803 buffer
->size
= pCreateInfo
->size
;
2804 buffer
->usage
= pCreateInfo
->usage
;
2807 buffer
->flags
= pCreateInfo
->flags
;
2809 buffer
->shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
2810 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR
) != NULL
;
2812 if (pCreateInfo
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
) {
2813 buffer
->bo
= device
->ws
->buffer_create(device
->ws
,
2814 align64(buffer
->size
, 4096),
2815 4096, 0, RADEON_FLAG_VIRTUAL
);
2817 vk_free2(&device
->alloc
, pAllocator
, buffer
);
2818 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2822 *pBuffer
= radv_buffer_to_handle(buffer
);
2827 void radv_DestroyBuffer(
2830 const VkAllocationCallbacks
* pAllocator
)
2832 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2833 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
2838 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
2839 device
->ws
->buffer_destroy(buffer
->bo
);
2841 vk_free2(&device
->alloc
, pAllocator
, buffer
);
2844 static inline unsigned
2845 si_tile_mode_index(const struct radv_image
*image
, unsigned level
, bool stencil
)
2848 return image
->surface
.u
.legacy
.stencil_tiling_index
[level
];
2850 return image
->surface
.u
.legacy
.tiling_index
[level
];
2853 static uint32_t radv_surface_layer_count(struct radv_image_view
*iview
)
2855 return iview
->type
== VK_IMAGE_VIEW_TYPE_3D
? iview
->extent
.depth
: iview
->layer_count
;
2859 radv_initialise_color_surface(struct radv_device
*device
,
2860 struct radv_color_buffer_info
*cb
,
2861 struct radv_image_view
*iview
)
2863 const struct vk_format_description
*desc
;
2864 unsigned ntype
, format
, swap
, endian
;
2865 unsigned blend_clamp
= 0, blend_bypass
= 0;
2867 const struct radeon_surf
*surf
= &iview
->image
->surface
;
2869 desc
= vk_format_description(iview
->vk_format
);
2871 memset(cb
, 0, sizeof(*cb
));
2873 /* Intensity is implemented as Red, so treat it that way. */
2874 cb
->cb_color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == VK_SWIZZLE_1
);
2876 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
2878 cb
->cb_color_base
= va
>> 8;
2880 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2881 struct gfx9_surf_meta_flags meta
;
2882 if (iview
->image
->dcc_offset
)
2883 meta
= iview
->image
->surface
.u
.gfx9
.dcc
;
2885 meta
= iview
->image
->surface
.u
.gfx9
.cmask
;
2887 cb
->cb_color_attrib
|= S_028C74_COLOR_SW_MODE(iview
->image
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
2888 S_028C74_FMASK_SW_MODE(iview
->image
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
2889 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
2890 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
2892 cb
->cb_color_base
+= iview
->image
->surface
.u
.gfx9
.surf_offset
>> 8;
2893 cb
->cb_color_base
|= iview
->image
->surface
.tile_swizzle
;
2895 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[iview
->base_mip
];
2896 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
2898 cb
->cb_color_base
+= level_info
->offset
>> 8;
2899 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
2900 cb
->cb_color_base
|= iview
->image
->surface
.tile_swizzle
;
2902 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
2903 slice_tile_max
= (level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1;
2904 tile_mode_index
= si_tile_mode_index(iview
->image
, iview
->base_mip
, false);
2906 cb
->cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
2907 cb
->cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
2908 cb
->cb_color_cmask_slice
= iview
->image
->cmask
.slice_tile_max
;
2910 cb
->cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
2911 cb
->micro_tile_mode
= iview
->image
->surface
.micro_tile_mode
;
2913 if (iview
->image
->fmask
.size
) {
2914 if (device
->physical_device
->rad_info
.chip_class
>= CIK
)
2915 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(iview
->image
->fmask
.pitch_in_pixels
/ 8 - 1);
2916 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(iview
->image
->fmask
.tile_mode_index
);
2917 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(iview
->image
->fmask
.slice_tile_max
);
2919 /* This must be set for fast clear to work without FMASK. */
2920 if (device
->physical_device
->rad_info
.chip_class
>= CIK
)
2921 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
2922 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
2923 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
2927 /* CMASK variables */
2928 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
2929 va
+= iview
->image
->cmask
.offset
;
2930 cb
->cb_color_cmask
= va
>> 8;
2932 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
2933 va
+= iview
->image
->dcc_offset
;
2934 cb
->cb_dcc_base
= va
>> 8;
2935 cb
->cb_dcc_base
|= iview
->image
->surface
.tile_swizzle
;
2937 uint32_t max_slice
= radv_surface_layer_count(iview
);
2938 cb
->cb_color_view
= S_028C6C_SLICE_START(iview
->base_layer
) |
2939 S_028C6C_SLICE_MAX(iview
->base_layer
+ max_slice
- 1);
2941 if (iview
->image
->info
.samples
> 1) {
2942 unsigned log_samples
= util_logbase2(iview
->image
->info
.samples
);
2944 cb
->cb_color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
2945 S_028C74_NUM_FRAGMENTS(log_samples
);
2948 if (iview
->image
->fmask
.size
) {
2949 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ iview
->image
->fmask
.offset
;
2950 cb
->cb_color_fmask
= va
>> 8;
2951 cb
->cb_color_fmask
|= iview
->image
->fmask
.tile_swizzle
;
2953 cb
->cb_color_fmask
= cb
->cb_color_base
;
2956 ntype
= radv_translate_color_numformat(iview
->vk_format
,
2958 vk_format_get_first_non_void_channel(iview
->vk_format
));
2959 format
= radv_translate_colorformat(iview
->vk_format
);
2960 if (format
== V_028C70_COLOR_INVALID
|| ntype
== ~0u)
2961 radv_finishme("Illegal color\n");
2962 swap
= radv_translate_colorswap(iview
->vk_format
, FALSE
);
2963 endian
= radv_colorformat_endian_swap(format
);
2965 /* blend clamp should be set for all NORM/SRGB types */
2966 if (ntype
== V_028C70_NUMBER_UNORM
||
2967 ntype
== V_028C70_NUMBER_SNORM
||
2968 ntype
== V_028C70_NUMBER_SRGB
)
2971 /* set blend bypass according to docs if SINT/UINT or
2972 8/24 COLOR variants */
2973 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
2974 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
2975 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
2980 if ((ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) &&
2981 (format
== V_028C70_COLOR_8
||
2982 format
== V_028C70_COLOR_8_8
||
2983 format
== V_028C70_COLOR_8_8_8_8
))
2984 ->color_is_int8
= true;
2986 cb
->cb_color_info
= S_028C70_FORMAT(format
) |
2987 S_028C70_COMP_SWAP(swap
) |
2988 S_028C70_BLEND_CLAMP(blend_clamp
) |
2989 S_028C70_BLEND_BYPASS(blend_bypass
) |
2990 S_028C70_SIMPLE_FLOAT(1) |
2991 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
2992 ntype
!= V_028C70_NUMBER_SNORM
&&
2993 ntype
!= V_028C70_NUMBER_SRGB
&&
2994 format
!= V_028C70_COLOR_8_24
&&
2995 format
!= V_028C70_COLOR_24_8
) |
2996 S_028C70_NUMBER_TYPE(ntype
) |
2997 S_028C70_ENDIAN(endian
);
2998 if ((iview
->image
->info
.samples
> 1) && iview
->image
->fmask
.size
) {
2999 cb
->cb_color_info
|= S_028C70_COMPRESSION(1);
3000 if (device
->physical_device
->rad_info
.chip_class
== SI
) {
3001 unsigned fmask_bankh
= util_logbase2(iview
->image
->fmask
.bank_height
);
3002 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
3006 if (iview
->image
->cmask
.size
&&
3007 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
))
3008 cb
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
3010 if (radv_vi_dcc_enabled(iview
->image
, iview
->base_mip
))
3011 cb
->cb_color_info
|= S_028C70_DCC_ENABLE(1);
3013 if (device
->physical_device
->rad_info
.chip_class
>= VI
) {
3014 unsigned max_uncompressed_block_size
= 2;
3015 if (iview
->image
->info
.samples
> 1) {
3016 if (iview
->image
->surface
.bpe
== 1)
3017 max_uncompressed_block_size
= 0;
3018 else if (iview
->image
->surface
.bpe
== 2)
3019 max_uncompressed_block_size
= 1;
3022 cb
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
3023 S_028C78_INDEPENDENT_64B_BLOCKS(1);
3026 /* This must be set for fast clear to work without FMASK. */
3027 if (!iview
->image
->fmask
.size
&&
3028 device
->physical_device
->rad_info
.chip_class
== SI
) {
3029 unsigned bankh
= util_logbase2(iview
->image
->surface
.u
.legacy
.bankh
);
3030 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
3033 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
3034 unsigned mip0_depth
= iview
->image
->type
== VK_IMAGE_TYPE_3D
?
3035 (iview
->extent
.depth
- 1) : (iview
->image
->info
.array_size
- 1);
3037 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL(iview
->base_mip
);
3038 cb
->cb_color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
3039 S_028C74_RESOURCE_TYPE(iview
->image
->surface
.u
.gfx9
.resource_type
);
3040 cb
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(iview
->extent
.width
- 1) |
3041 S_028C68_MIP0_HEIGHT(iview
->extent
.height
- 1) |
3042 S_028C68_MAX_MIP(iview
->image
->info
.levels
- 1);
3044 cb
->gfx9_epitch
= S_0287A0_EPITCH(iview
->image
->surface
.u
.gfx9
.surf
.epitch
);
3050 radv_initialise_ds_surface(struct radv_device
*device
,
3051 struct radv_ds_buffer_info
*ds
,
3052 struct radv_image_view
*iview
)
3054 unsigned level
= iview
->base_mip
;
3055 unsigned format
, stencil_format
;
3056 uint64_t va
, s_offs
, z_offs
;
3057 bool stencil_only
= false;
3058 memset(ds
, 0, sizeof(*ds
));
3059 switch (iview
->image
->vk_format
) {
3060 case VK_FORMAT_D24_UNORM_S8_UINT
:
3061 case VK_FORMAT_X8_D24_UNORM_PACK32
:
3062 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3063 ds
->offset_scale
= 2.0f
;
3065 case VK_FORMAT_D16_UNORM
:
3066 case VK_FORMAT_D16_UNORM_S8_UINT
:
3067 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3068 ds
->offset_scale
= 4.0f
;
3070 case VK_FORMAT_D32_SFLOAT
:
3071 case VK_FORMAT_D32_SFLOAT_S8_UINT
:
3072 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3073 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3074 ds
->offset_scale
= 1.0f
;
3076 case VK_FORMAT_S8_UINT
:
3077 stencil_only
= true;
3083 format
= radv_translate_dbformat(iview
->image
->vk_format
);
3084 stencil_format
= iview
->image
->surface
.has_stencil
?
3085 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
3087 uint32_t max_slice
= radv_surface_layer_count(iview
);
3088 ds
->db_depth_view
= S_028008_SLICE_START(iview
->base_layer
) |
3089 S_028008_SLICE_MAX(iview
->base_layer
+ max_slice
- 1);
3091 ds
->db_htile_data_base
= 0;
3092 ds
->db_htile_surface
= 0;
3094 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
3095 s_offs
= z_offs
= va
;
3097 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
3098 assert(iview
->image
->surface
.u
.gfx9
.surf_offset
== 0);
3099 s_offs
+= iview
->image
->surface
.u
.gfx9
.stencil_offset
;
3101 ds
->db_z_info
= S_028038_FORMAT(format
) |
3102 S_028038_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
)) |
3103 S_028038_SW_MODE(iview
->image
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
3104 S_028038_MAXMIP(iview
->image
->info
.levels
- 1);
3105 ds
->db_stencil_info
= S_02803C_FORMAT(stencil_format
) |
3106 S_02803C_SW_MODE(iview
->image
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
3108 ds
->db_z_info2
= S_028068_EPITCH(iview
->image
->surface
.u
.gfx9
.surf
.epitch
);
3109 ds
->db_stencil_info2
= S_02806C_EPITCH(iview
->image
->surface
.u
.gfx9
.stencil
.epitch
);
3110 ds
->db_depth_view
|= S_028008_MIPID(level
);
3112 ds
->db_depth_size
= S_02801C_X_MAX(iview
->image
->info
.width
- 1) |
3113 S_02801C_Y_MAX(iview
->image
->info
.height
- 1);
3115 if (radv_htile_enabled(iview
->image
, level
)) {
3116 ds
->db_z_info
|= S_028038_TILE_SURFACE_ENABLE(1);
3118 if (iview
->image
->tc_compatible_htile
) {
3119 unsigned max_zplanes
= 4;
3121 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
&&
3122 iview
->image
->info
.samples
> 1)
3125 ds
->db_z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
+ 1) |
3126 S_028038_ITERATE_FLUSH(1);
3127 ds
->db_stencil_info
|= S_02803C_ITERATE_FLUSH(1);
3130 if (!iview
->image
->surface
.has_stencil
)
3131 /* Use all of the htile_buffer for depth if there's no stencil. */
3132 ds
->db_stencil_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
3133 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
3134 iview
->image
->htile_offset
;
3135 ds
->db_htile_data_base
= va
>> 8;
3136 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
3137 S_028ABC_PIPE_ALIGNED(iview
->image
->surface
.u
.gfx9
.htile
.pipe_aligned
) |
3138 S_028ABC_RB_ALIGNED(iview
->image
->surface
.u
.gfx9
.htile
.rb_aligned
);
3141 const struct legacy_surf_level
*level_info
= &iview
->image
->surface
.u
.legacy
.level
[level
];
3144 level_info
= &iview
->image
->surface
.u
.legacy
.stencil_level
[level
];
3146 z_offs
+= iview
->image
->surface
.u
.legacy
.level
[level
].offset
;
3147 s_offs
+= iview
->image
->surface
.u
.legacy
.stencil_level
[level
].offset
;
3149 ds
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!iview
->image
->tc_compatible_htile
);
3150 ds
->db_z_info
= S_028040_FORMAT(format
) | S_028040_ZRANGE_PRECISION(1);
3151 ds
->db_stencil_info
= S_028044_FORMAT(stencil_format
);
3153 if (iview
->image
->info
.samples
> 1)
3154 ds
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
));
3156 if (device
->physical_device
->rad_info
.chip_class
>= CIK
) {
3157 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
3158 unsigned tiling_index
= iview
->image
->surface
.u
.legacy
.tiling_index
[level
];
3159 unsigned stencil_index
= iview
->image
->surface
.u
.legacy
.stencil_tiling_index
[level
];
3160 unsigned macro_index
= iview
->image
->surface
.u
.legacy
.macro_tile_index
;
3161 unsigned tile_mode
= info
->si_tile_mode_array
[tiling_index
];
3162 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
3163 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
3166 tile_mode
= stencil_tile_mode
;
3168 ds
->db_depth_info
|=
3169 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
3170 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
3171 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
3172 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
3173 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
3174 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
3175 ds
->db_z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
3176 ds
->db_stencil_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
3178 unsigned tile_mode_index
= si_tile_mode_index(iview
->image
, level
, false);
3179 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
3180 tile_mode_index
= si_tile_mode_index(iview
->image
, level
, true);
3181 ds
->db_stencil_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
3183 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
3186 ds
->db_depth_size
= S_028058_PITCH_TILE_MAX((level_info
->nblk_x
/ 8) - 1) |
3187 S_028058_HEIGHT_TILE_MAX((level_info
->nblk_y
/ 8) - 1);
3188 ds
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1);
3190 if (radv_htile_enabled(iview
->image
, level
)) {
3191 ds
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
3193 if (!iview
->image
->surface
.has_stencil
&&
3194 !iview
->image
->tc_compatible_htile
)
3195 /* Use all of the htile_buffer for depth if there's no stencil. */
3196 ds
->db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
3198 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
3199 iview
->image
->htile_offset
;
3200 ds
->db_htile_data_base
= va
>> 8;
3201 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
3203 if (iview
->image
->tc_compatible_htile
) {
3204 ds
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
3206 if (iview
->image
->info
.samples
<= 1)
3207 ds
->db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
3208 else if (iview
->image
->info
.samples
<= 4)
3209 ds
->db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
3211 ds
->db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
3216 ds
->db_z_read_base
= ds
->db_z_write_base
= z_offs
>> 8;
3217 ds
->db_stencil_read_base
= ds
->db_stencil_write_base
= s_offs
>> 8;
3220 VkResult
radv_CreateFramebuffer(
3222 const VkFramebufferCreateInfo
* pCreateInfo
,
3223 const VkAllocationCallbacks
* pAllocator
,
3224 VkFramebuffer
* pFramebuffer
)
3226 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3227 struct radv_framebuffer
*framebuffer
;
3229 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
);
3231 size_t size
= sizeof(*framebuffer
) +
3232 sizeof(struct radv_attachment_info
) * pCreateInfo
->attachmentCount
;
3233 framebuffer
= vk_alloc2(&device
->alloc
, pAllocator
, size
, 8,
3234 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3235 if (framebuffer
== NULL
)
3236 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
3238 framebuffer
->attachment_count
= pCreateInfo
->attachmentCount
;
3239 framebuffer
->width
= pCreateInfo
->width
;
3240 framebuffer
->height
= pCreateInfo
->height
;
3241 framebuffer
->layers
= pCreateInfo
->layers
;
3242 for (uint32_t i
= 0; i
< pCreateInfo
->attachmentCount
; i
++) {
3243 VkImageView _iview
= pCreateInfo
->pAttachments
[i
];
3244 struct radv_image_view
*iview
= radv_image_view_from_handle(_iview
);
3245 framebuffer
->attachments
[i
].attachment
= iview
;
3246 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
) {
3247 radv_initialise_color_surface(device
, &framebuffer
->attachments
[i
].cb
, iview
);
3248 } else if (iview
->aspect_mask
& (VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3249 radv_initialise_ds_surface(device
, &framebuffer
->attachments
[i
].ds
, iview
);
3251 framebuffer
->width
= MIN2(framebuffer
->width
, iview
->extent
.width
);
3252 framebuffer
->height
= MIN2(framebuffer
->height
, iview
->extent
.height
);
3253 framebuffer
->layers
= MIN2(framebuffer
->layers
, radv_surface_layer_count(iview
));
3256 *pFramebuffer
= radv_framebuffer_to_handle(framebuffer
);
3260 void radv_DestroyFramebuffer(
3263 const VkAllocationCallbacks
* pAllocator
)
3265 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3266 RADV_FROM_HANDLE(radv_framebuffer
, fb
, _fb
);
3270 vk_free2(&device
->alloc
, pAllocator
, fb
);
3273 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode
)
3275 switch (address_mode
) {
3276 case VK_SAMPLER_ADDRESS_MODE_REPEAT
:
3277 return V_008F30_SQ_TEX_WRAP
;
3278 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT
:
3279 return V_008F30_SQ_TEX_MIRROR
;
3280 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
:
3281 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
3282 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
:
3283 return V_008F30_SQ_TEX_CLAMP_BORDER
;
3284 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE
:
3285 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
3287 unreachable("illegal tex wrap mode");
3293 radv_tex_compare(VkCompareOp op
)
3296 case VK_COMPARE_OP_NEVER
:
3297 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
3298 case VK_COMPARE_OP_LESS
:
3299 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
3300 case VK_COMPARE_OP_EQUAL
:
3301 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
3302 case VK_COMPARE_OP_LESS_OR_EQUAL
:
3303 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
3304 case VK_COMPARE_OP_GREATER
:
3305 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
3306 case VK_COMPARE_OP_NOT_EQUAL
:
3307 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
3308 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
3309 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
3310 case VK_COMPARE_OP_ALWAYS
:
3311 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
3313 unreachable("illegal compare mode");
3319 radv_tex_filter(VkFilter filter
, unsigned max_ansio
)
3322 case VK_FILTER_NEAREST
:
3323 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
:
3324 V_008F38_SQ_TEX_XY_FILTER_POINT
);
3325 case VK_FILTER_LINEAR
:
3326 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
:
3327 V_008F38_SQ_TEX_XY_FILTER_BILINEAR
);
3328 case VK_FILTER_CUBIC_IMG
:
3330 fprintf(stderr
, "illegal texture filter");
3336 radv_tex_mipfilter(VkSamplerMipmapMode mode
)
3339 case VK_SAMPLER_MIPMAP_MODE_NEAREST
:
3340 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
3341 case VK_SAMPLER_MIPMAP_MODE_LINEAR
:
3342 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
3344 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
3349 radv_tex_bordercolor(VkBorderColor bcolor
)
3352 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
:
3353 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK
:
3354 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
3355 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK
:
3356 case VK_BORDER_COLOR_INT_OPAQUE_BLACK
:
3357 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
3358 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE
:
3359 case VK_BORDER_COLOR_INT_OPAQUE_WHITE
:
3360 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
3368 radv_tex_aniso_filter(unsigned filter
)
3382 radv_init_sampler(struct radv_device
*device
,
3383 struct radv_sampler
*sampler
,
3384 const VkSamplerCreateInfo
*pCreateInfo
)
3386 uint32_t max_aniso
= pCreateInfo
->anisotropyEnable
&& pCreateInfo
->maxAnisotropy
> 1.0 ?
3387 (uint32_t) pCreateInfo
->maxAnisotropy
: 0;
3388 uint32_t max_aniso_ratio
= radv_tex_aniso_filter(max_aniso
);
3389 bool is_vi
= (device
->physical_device
->rad_info
.chip_class
>= VI
);
3391 sampler
->state
[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo
->addressModeU
)) |
3392 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo
->addressModeV
)) |
3393 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo
->addressModeW
)) |
3394 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
3395 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo
->compareOp
)) |
3396 S_008F30_FORCE_UNNORMALIZED(pCreateInfo
->unnormalizedCoordinates
? 1 : 0) |
3397 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
3398 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
3399 S_008F30_DISABLE_CUBE_WRAP(0) |
3400 S_008F30_COMPAT_MODE(is_vi
));
3401 sampler
->state
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo
->minLod
, 0, 15), 8)) |
3402 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo
->maxLod
, 0, 15), 8)) |
3403 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
3404 sampler
->state
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo
->mipLodBias
, -16, 16), 8)) |
3405 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo
->magFilter
, max_aniso
)) |
3406 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo
->minFilter
, max_aniso
)) |
3407 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo
->mipmapMode
)) |
3408 S_008F38_MIP_POINT_PRECLAMP(0) |
3409 S_008F38_DISABLE_LSB_CEIL(1) |
3410 S_008F38_FILTER_PREC_FIX(1) |
3411 S_008F38_ANISO_OVERRIDE(is_vi
));
3412 sampler
->state
[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3413 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo
->borderColor
)));
3416 VkResult
radv_CreateSampler(
3418 const VkSamplerCreateInfo
* pCreateInfo
,
3419 const VkAllocationCallbacks
* pAllocator
,
3420 VkSampler
* pSampler
)
3422 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3423 struct radv_sampler
*sampler
;
3425 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO
);
3427 sampler
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*sampler
), 8,
3428 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3430 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
3432 radv_init_sampler(device
, sampler
, pCreateInfo
);
3433 *pSampler
= radv_sampler_to_handle(sampler
);
3438 void radv_DestroySampler(
3441 const VkAllocationCallbacks
* pAllocator
)
3443 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3444 RADV_FROM_HANDLE(radv_sampler
, sampler
, _sampler
);
3448 vk_free2(&device
->alloc
, pAllocator
, sampler
);
3451 /* vk_icd.h does not declare this function, so we declare it here to
3452 * suppress Wmissing-prototypes.
3454 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3455 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
);
3457 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3458 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
)
3460 /* For the full details on loader interface versioning, see
3461 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3462 * What follows is a condensed summary, to help you navigate the large and
3463 * confusing official doc.
3465 * - Loader interface v0 is incompatible with later versions. We don't
3468 * - In loader interface v1:
3469 * - The first ICD entrypoint called by the loader is
3470 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3472 * - The ICD must statically expose no other Vulkan symbol unless it is
3473 * linked with -Bsymbolic.
3474 * - Each dispatchable Vulkan handle created by the ICD must be
3475 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3476 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3477 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3478 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3479 * such loader-managed surfaces.
3481 * - Loader interface v2 differs from v1 in:
3482 * - The first ICD entrypoint called by the loader is
3483 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3484 * statically expose this entrypoint.
3486 * - Loader interface v3 differs from v2 in:
3487 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3488 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3489 * because the loader no longer does so.
3491 *pSupportedVersion
= MIN2(*pSupportedVersion
, 3u);
3495 VkResult
radv_GetMemoryFdKHR(VkDevice _device
,
3496 const VkMemoryGetFdInfoKHR
*pGetFdInfo
,
3499 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3500 RADV_FROM_HANDLE(radv_device_memory
, memory
, pGetFdInfo
->memory
);
3502 assert(pGetFdInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR
);
3504 /* We support only one handle type. */
3505 assert(pGetFdInfo
->handleType
==
3506 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
);
3508 bool ret
= radv_get_memory_fd(device
, memory
, pFD
);
3510 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
3514 VkResult
radv_GetMemoryFdPropertiesKHR(VkDevice _device
,
3515 VkExternalMemoryHandleTypeFlagBitsKHR handleType
,
3517 VkMemoryFdPropertiesKHR
*pMemoryFdProperties
)
3519 /* The valid usage section for this function says:
3521 * "handleType must not be one of the handle types defined as opaque."
3523 * Since we only handle opaque handles for now, there are no FD properties.
3525 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR
;
3528 VkResult
radv_ImportSemaphoreFdKHR(VkDevice _device
,
3529 const VkImportSemaphoreFdInfoKHR
*pImportSemaphoreFdInfo
)
3531 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3532 RADV_FROM_HANDLE(radv_semaphore
, sem
, pImportSemaphoreFdInfo
->semaphore
);
3533 uint32_t syncobj_handle
= 0;
3534 assert(pImportSemaphoreFdInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
);
3536 int ret
= device
->ws
->import_syncobj(device
->ws
, pImportSemaphoreFdInfo
->fd
, &syncobj_handle
);
3538 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR
;
3540 if (pImportSemaphoreFdInfo
->flags
& VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR
) {
3541 sem
->temp_syncobj
= syncobj_handle
;
3543 sem
->syncobj
= syncobj_handle
;
3545 close(pImportSemaphoreFdInfo
->fd
);
3549 VkResult
radv_GetSemaphoreFdKHR(VkDevice _device
,
3550 const VkSemaphoreGetFdInfoKHR
*pGetFdInfo
,
3553 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3554 RADV_FROM_HANDLE(radv_semaphore
, sem
, pGetFdInfo
->semaphore
);
3556 uint32_t syncobj_handle
;
3558 assert(pGetFdInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
);
3559 if (sem
->temp_syncobj
)
3560 syncobj_handle
= sem
->temp_syncobj
;
3562 syncobj_handle
= sem
->syncobj
;
3563 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
3565 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR
);
3569 void radv_GetPhysicalDeviceExternalSemaphorePropertiesKHR(
3570 VkPhysicalDevice physicalDevice
,
3571 const VkPhysicalDeviceExternalSemaphoreInfoKHR
* pExternalSemaphoreInfo
,
3572 VkExternalSemaphorePropertiesKHR
* pExternalSemaphoreProperties
)
3574 if (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
) {
3575 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
;
3576 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
;
3577 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR
|
3578 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR
;
3580 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= 0;
3581 pExternalSemaphoreProperties
->compatibleHandleTypes
= 0;
3582 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= 0;