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23f5e70321da16098f309c62da5013dfcac16ab5
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "amdgpu_id.h"
43 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
44 #include "ac_llvm_util.h"
45 #include "vk_format.h"
46 #include "sid.h"
47 #include "gfx9d.h"
48 #include "util/debug.h"
49
50 static int
51 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
52 {
53 uint32_t mesa_timestamp, llvm_timestamp;
54 uint16_t f = family;
55 memset(uuid, 0, VK_UUID_SIZE);
56 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
57 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
58 return -1;
59
60 memcpy(uuid, &mesa_timestamp, 4);
61 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
62 memcpy((char*)uuid + 8, &f, 2);
63 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
64 return 0;
65 }
66
67 static void
68 radv_get_driver_uuid(void *uuid)
69 {
70 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
71 }
72
73 static void
74 radv_get_device_uuid(struct radeon_info *info, void *uuid)
75 {
76 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
77 }
78
79 static const VkExtensionProperties instance_extensions[] = {
80 {
81 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
82 .specVersion = 25,
83 },
84 #ifdef VK_USE_PLATFORM_XCB_KHR
85 {
86 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
87 .specVersion = 6,
88 },
89 #endif
90 #ifdef VK_USE_PLATFORM_XLIB_KHR
91 {
92 .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
93 .specVersion = 6,
94 },
95 #endif
96 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
97 {
98 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
99 .specVersion = 6,
100 },
101 #endif
102 {
103 .extensionName = VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2_EXTENSION_NAME,
104 .specVersion = 1,
105 },
106 {
107 .extensionName = VK_KHR_EXTERNAL_MEMORY_CAPABILITIES_EXTENSION_NAME,
108 .specVersion = 1,
109 },
110 {
111 .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_CAPABILITIES_EXTENSION_NAME,
112 .specVersion = 1,
113 },
114 };
115
116 static const VkExtensionProperties common_device_extensions[] = {
117 {
118 .extensionName = VK_KHR_DESCRIPTOR_UPDATE_TEMPLATE_EXTENSION_NAME,
119 .specVersion = 1,
120 },
121 {
122 .extensionName = VK_KHR_INCREMENTAL_PRESENT_EXTENSION_NAME,
123 .specVersion = 1,
124 },
125 {
126 .extensionName = VK_KHR_MAINTENANCE1_EXTENSION_NAME,
127 .specVersion = 1,
128 },
129 {
130 .extensionName = VK_KHR_PUSH_DESCRIPTOR_EXTENSION_NAME,
131 .specVersion = 1,
132 },
133 {
134 .extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
135 .specVersion = 1,
136 },
137 {
138 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
139 .specVersion = 68,
140 },
141 {
142 .extensionName = VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME,
143 .specVersion = 1,
144 },
145 {
146 .extensionName = VK_KHR_SHADER_DRAW_PARAMETERS_EXTENSION_NAME,
147 .specVersion = 1,
148 },
149 {
150 .extensionName = VK_KHR_GET_MEMORY_REQUIREMENTS_2_EXTENSION_NAME,
151 .specVersion = 1,
152 },
153 {
154 .extensionName = VK_KHR_DEDICATED_ALLOCATION_EXTENSION_NAME,
155 .specVersion = 1,
156 },
157 {
158 .extensionName = VK_KHR_EXTERNAL_MEMORY_EXTENSION_NAME,
159 .specVersion = 1,
160 },
161 {
162 .extensionName = VK_KHR_EXTERNAL_MEMORY_FD_EXTENSION_NAME,
163 .specVersion = 1,
164 },
165 {
166 .extensionName = VK_KHR_STORAGE_BUFFER_STORAGE_CLASS_EXTENSION_NAME,
167 .specVersion = 1,
168 },
169 {
170 .extensionName = VK_KHR_VARIABLE_POINTERS_EXTENSION_NAME,
171 .specVersion = 1,
172 },
173 {
174 .extensionName = VK_KHR_IMAGE_FORMAT_LIST_EXTENSION_NAME,
175 .specVersion = 1,
176 },
177 {
178 .extensionName = VK_KHR_BIND_MEMORY_2_EXTENSION_NAME,
179 .specVersion = 1,
180 },
181 {
182 .extensionName = VK_KHR_MAINTENANCE2_EXTENSION_NAME,
183 .specVersion = 1,
184 },
185 {
186 .extensionName = VK_KHR_RELAXED_BLOCK_LAYOUT_EXTENSION_NAME,
187 .specVersion = 1,
188 },
189 };
190
191 static const VkExtensionProperties rasterization_order_extension[] ={
192 {
193 .extensionName = VK_AMD_RASTERIZATION_ORDER_EXTENSION_NAME,
194 .specVersion = 1,
195 },
196 };
197
198 static const VkExtensionProperties ext_sema_device_extensions[] = {
199 {
200 .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_EXTENSION_NAME,
201 .specVersion = 1,
202 },
203 {
204 .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_FD_EXTENSION_NAME,
205 .specVersion = 1,
206 },
207 {
208 .extensionName = VK_KHX_MULTIVIEW_EXTENSION_NAME,
209 .specVersion = 1,
210 },
211 };
212
213 static VkResult
214 radv_extensions_register(struct radv_instance *instance,
215 struct radv_extensions *extensions,
216 const VkExtensionProperties *new_ext,
217 uint32_t num_ext)
218 {
219 size_t new_size;
220 VkExtensionProperties *new_ptr;
221
222 assert(new_ext && num_ext > 0);
223
224 if (!new_ext)
225 return VK_ERROR_INITIALIZATION_FAILED;
226
227 new_size = (extensions->num_ext + num_ext) * sizeof(VkExtensionProperties);
228 new_ptr = vk_realloc(&instance->alloc, extensions->ext_array,
229 new_size, 8, VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
230
231 /* Old array continues to be valid, update nothing */
232 if (!new_ptr)
233 return VK_ERROR_OUT_OF_HOST_MEMORY;
234
235 memcpy(&new_ptr[extensions->num_ext], new_ext,
236 num_ext * sizeof(VkExtensionProperties));
237 extensions->ext_array = new_ptr;
238 extensions->num_ext += num_ext;
239
240 return VK_SUCCESS;
241 }
242
243 static void
244 radv_extensions_finish(struct radv_instance *instance,
245 struct radv_extensions *extensions)
246 {
247 assert(extensions);
248
249 if (!extensions)
250 radv_loge("Attemted to free invalid extension struct\n");
251
252 if (extensions->ext_array)
253 vk_free(&instance->alloc, extensions->ext_array);
254 }
255
256 static bool
257 is_extension_enabled(const VkExtensionProperties *extensions,
258 size_t num_ext,
259 const char *name)
260 {
261 assert(extensions && name);
262
263 for (uint32_t i = 0; i < num_ext; i++) {
264 if (strcmp(name, extensions[i].extensionName) == 0)
265 return true;
266 }
267
268 return false;
269 }
270
271 static const char *
272 get_chip_name(enum radeon_family family)
273 {
274 switch (family) {
275 case CHIP_TAHITI: return "AMD RADV TAHITI";
276 case CHIP_PITCAIRN: return "AMD RADV PITCAIRN";
277 case CHIP_VERDE: return "AMD RADV CAPE VERDE";
278 case CHIP_OLAND: return "AMD RADV OLAND";
279 case CHIP_HAINAN: return "AMD RADV HAINAN";
280 case CHIP_BONAIRE: return "AMD RADV BONAIRE";
281 case CHIP_KAVERI: return "AMD RADV KAVERI";
282 case CHIP_KABINI: return "AMD RADV KABINI";
283 case CHIP_HAWAII: return "AMD RADV HAWAII";
284 case CHIP_MULLINS: return "AMD RADV MULLINS";
285 case CHIP_TONGA: return "AMD RADV TONGA";
286 case CHIP_ICELAND: return "AMD RADV ICELAND";
287 case CHIP_CARRIZO: return "AMD RADV CARRIZO";
288 case CHIP_FIJI: return "AMD RADV FIJI";
289 case CHIP_POLARIS10: return "AMD RADV POLARIS10";
290 case CHIP_POLARIS11: return "AMD RADV POLARIS11";
291 case CHIP_POLARIS12: return "AMD RADV POLARIS12";
292 case CHIP_STONEY: return "AMD RADV STONEY";
293 case CHIP_VEGA10: return "AMD RADV VEGA";
294 case CHIP_RAVEN: return "AMD RADV RAVEN";
295 default: return "AMD RADV unknown";
296 }
297 }
298
299 static VkResult
300 radv_physical_device_init(struct radv_physical_device *device,
301 struct radv_instance *instance,
302 drmDevicePtr drm_device)
303 {
304 const char *path = drm_device->nodes[DRM_NODE_RENDER];
305 VkResult result;
306 drmVersionPtr version;
307 int fd;
308
309 fd = open(path, O_RDWR | O_CLOEXEC);
310 if (fd < 0)
311 return VK_ERROR_INCOMPATIBLE_DRIVER;
312
313 version = drmGetVersion(fd);
314 if (!version) {
315 close(fd);
316 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
317 "failed to get version %s: %m", path);
318 }
319
320 if (strcmp(version->name, "amdgpu")) {
321 drmFreeVersion(version);
322 close(fd);
323 return VK_ERROR_INCOMPATIBLE_DRIVER;
324 }
325 drmFreeVersion(version);
326
327 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
328 device->instance = instance;
329 assert(strlen(path) < ARRAY_SIZE(device->path));
330 strncpy(device->path, path, ARRAY_SIZE(device->path));
331
332 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
333 instance->perftest_flags);
334 if (!device->ws) {
335 result = VK_ERROR_INCOMPATIBLE_DRIVER;
336 goto fail;
337 }
338
339 device->local_fd = fd;
340 device->ws->query_info(device->ws, &device->rad_info);
341 result = radv_init_wsi(device);
342 if (result != VK_SUCCESS) {
343 device->ws->destroy(device->ws);
344 goto fail;
345 }
346
347 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
348 radv_finish_wsi(device);
349 device->ws->destroy(device->ws);
350 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
351 "cannot generate UUID");
352 goto fail;
353 }
354
355 /* These flags affect shader compilation. */
356 uint64_t shader_env_flags =
357 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
358 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
359
360 /* The gpu id is already embeded in the uuid so we just pass "radv"
361 * when creating the cache.
362 */
363 char buf[VK_UUID_SIZE + 1];
364 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE);
365 device->disk_cache = disk_cache_create("radv", buf, shader_env_flags);
366
367 result = radv_extensions_register(instance,
368 &device->extensions,
369 common_device_extensions,
370 ARRAY_SIZE(common_device_extensions));
371 if (result != VK_SUCCESS)
372 goto fail;
373
374 if (device->rad_info.chip_class >= VI && device->rad_info.max_se >= 2) {
375 result = radv_extensions_register(instance,
376 &device->extensions,
377 rasterization_order_extension,
378 ARRAY_SIZE(rasterization_order_extension));
379 if (result != VK_SUCCESS)
380 goto fail;
381 }
382
383 if (device->rad_info.has_syncobj) {
384 result = radv_extensions_register(instance,
385 &device->extensions,
386 ext_sema_device_extensions,
387 ARRAY_SIZE(ext_sema_device_extensions));
388 if (result != VK_SUCCESS)
389 goto fail;
390 }
391
392 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
393 device->name = get_chip_name(device->rad_info.family);
394
395 radv_get_driver_uuid(&device->device_uuid);
396 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
397
398 if (device->rad_info.family == CHIP_STONEY ||
399 device->rad_info.chip_class >= GFX9) {
400 device->has_rbplus = true;
401 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY;
402 }
403
404 return VK_SUCCESS;
405
406 fail:
407 close(fd);
408 return result;
409 }
410
411 static void
412 radv_physical_device_finish(struct radv_physical_device *device)
413 {
414 radv_extensions_finish(device->instance, &device->extensions);
415 radv_finish_wsi(device);
416 device->ws->destroy(device->ws);
417 disk_cache_destroy(device->disk_cache);
418 close(device->local_fd);
419 }
420
421 static void *
422 default_alloc_func(void *pUserData, size_t size, size_t align,
423 VkSystemAllocationScope allocationScope)
424 {
425 return malloc(size);
426 }
427
428 static void *
429 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
430 size_t align, VkSystemAllocationScope allocationScope)
431 {
432 return realloc(pOriginal, size);
433 }
434
435 static void
436 default_free_func(void *pUserData, void *pMemory)
437 {
438 free(pMemory);
439 }
440
441 static const VkAllocationCallbacks default_alloc = {
442 .pUserData = NULL,
443 .pfnAllocation = default_alloc_func,
444 .pfnReallocation = default_realloc_func,
445 .pfnFree = default_free_func,
446 };
447
448 static const struct debug_control radv_debug_options[] = {
449 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
450 {"nodcc", RADV_DEBUG_NO_DCC},
451 {"shaders", RADV_DEBUG_DUMP_SHADERS},
452 {"nocache", RADV_DEBUG_NO_CACHE},
453 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
454 {"nohiz", RADV_DEBUG_NO_HIZ},
455 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
456 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
457 {"allbos", RADV_DEBUG_ALL_BOS},
458 {"noibs", RADV_DEBUG_NO_IBS},
459 {"spirv", RADV_DEBUG_DUMP_SPIRV},
460 {"vmfaults", RADV_DEBUG_VM_FAULTS},
461 {"zerovram", RADV_DEBUG_ZERO_VRAM},
462 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
463 {NULL, 0}
464 };
465
466 const char *
467 radv_get_debug_option_name(int id)
468 {
469 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
470 return radv_debug_options[id].string;
471 }
472
473 static const struct debug_control radv_perftest_options[] = {
474 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
475 {"sisched", RADV_PERFTEST_SISCHED},
476 {NULL, 0}
477 };
478
479 const char *
480 radv_get_perftest_option_name(int id)
481 {
482 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
483 return radv_perftest_options[id].string;
484 }
485
486 VkResult radv_CreateInstance(
487 const VkInstanceCreateInfo* pCreateInfo,
488 const VkAllocationCallbacks* pAllocator,
489 VkInstance* pInstance)
490 {
491 struct radv_instance *instance;
492
493 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
494
495 uint32_t client_version;
496 if (pCreateInfo->pApplicationInfo &&
497 pCreateInfo->pApplicationInfo->apiVersion != 0) {
498 client_version = pCreateInfo->pApplicationInfo->apiVersion;
499 } else {
500 client_version = VK_MAKE_VERSION(1, 0, 0);
501 }
502
503 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
504 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
505 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
506 "Client requested version %d.%d.%d",
507 VK_VERSION_MAJOR(client_version),
508 VK_VERSION_MINOR(client_version),
509 VK_VERSION_PATCH(client_version));
510 }
511
512 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
513 if (!is_extension_enabled(instance_extensions,
514 ARRAY_SIZE(instance_extensions),
515 pCreateInfo->ppEnabledExtensionNames[i]))
516 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
517 }
518
519 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
520 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
521 if (!instance)
522 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
523
524 memset(instance, 0, sizeof(*instance));
525
526 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
527
528 if (pAllocator)
529 instance->alloc = *pAllocator;
530 else
531 instance->alloc = default_alloc;
532
533 instance->apiVersion = client_version;
534 instance->physicalDeviceCount = -1;
535
536 _mesa_locale_init();
537
538 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
539
540 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
541 radv_debug_options);
542
543 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
544 radv_perftest_options);
545
546 *pInstance = radv_instance_to_handle(instance);
547
548 return VK_SUCCESS;
549 }
550
551 void radv_DestroyInstance(
552 VkInstance _instance,
553 const VkAllocationCallbacks* pAllocator)
554 {
555 RADV_FROM_HANDLE(radv_instance, instance, _instance);
556
557 if (!instance)
558 return;
559
560 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
561 radv_physical_device_finish(instance->physicalDevices + i);
562 }
563
564 VG(VALGRIND_DESTROY_MEMPOOL(instance));
565
566 _mesa_locale_fini();
567
568 vk_free(&instance->alloc, instance);
569 }
570
571 static VkResult
572 radv_enumerate_devices(struct radv_instance *instance)
573 {
574 /* TODO: Check for more devices ? */
575 drmDevicePtr devices[8];
576 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
577 int max_devices;
578
579 instance->physicalDeviceCount = 0;
580
581 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
582 if (max_devices < 1)
583 return VK_ERROR_INCOMPATIBLE_DRIVER;
584
585 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
586 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
587 devices[i]->bustype == DRM_BUS_PCI &&
588 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
589
590 result = radv_physical_device_init(instance->physicalDevices +
591 instance->physicalDeviceCount,
592 instance,
593 devices[i]);
594 if (result == VK_SUCCESS)
595 ++instance->physicalDeviceCount;
596 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
597 break;
598 }
599 }
600 drmFreeDevices(devices, max_devices);
601
602 return result;
603 }
604
605 VkResult radv_EnumeratePhysicalDevices(
606 VkInstance _instance,
607 uint32_t* pPhysicalDeviceCount,
608 VkPhysicalDevice* pPhysicalDevices)
609 {
610 RADV_FROM_HANDLE(radv_instance, instance, _instance);
611 VkResult result;
612
613 if (instance->physicalDeviceCount < 0) {
614 result = radv_enumerate_devices(instance);
615 if (result != VK_SUCCESS &&
616 result != VK_ERROR_INCOMPATIBLE_DRIVER)
617 return result;
618 }
619
620 if (!pPhysicalDevices) {
621 *pPhysicalDeviceCount = instance->physicalDeviceCount;
622 } else {
623 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
624 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
625 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
626 }
627
628 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
629 : VK_SUCCESS;
630 }
631
632 void radv_GetPhysicalDeviceFeatures(
633 VkPhysicalDevice physicalDevice,
634 VkPhysicalDeviceFeatures* pFeatures)
635 {
636 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
637 bool is_gfx9 = pdevice->rad_info.chip_class >= GFX9;
638 memset(pFeatures, 0, sizeof(*pFeatures));
639
640 *pFeatures = (VkPhysicalDeviceFeatures) {
641 .robustBufferAccess = true,
642 .fullDrawIndexUint32 = true,
643 .imageCubeArray = true,
644 .independentBlend = true,
645 .geometryShader = !is_gfx9,
646 .tessellationShader = !is_gfx9,
647 .sampleRateShading = true,
648 .dualSrcBlend = true,
649 .logicOp = true,
650 .multiDrawIndirect = true,
651 .drawIndirectFirstInstance = true,
652 .depthClamp = true,
653 .depthBiasClamp = true,
654 .fillModeNonSolid = true,
655 .depthBounds = true,
656 .wideLines = true,
657 .largePoints = true,
658 .alphaToOne = true,
659 .multiViewport = true,
660 .samplerAnisotropy = true,
661 .textureCompressionETC2 = false,
662 .textureCompressionASTC_LDR = false,
663 .textureCompressionBC = true,
664 .occlusionQueryPrecise = true,
665 .pipelineStatisticsQuery = true,
666 .vertexPipelineStoresAndAtomics = true,
667 .fragmentStoresAndAtomics = true,
668 .shaderTessellationAndGeometryPointSize = true,
669 .shaderImageGatherExtended = true,
670 .shaderStorageImageExtendedFormats = true,
671 .shaderStorageImageMultisample = false,
672 .shaderUniformBufferArrayDynamicIndexing = true,
673 .shaderSampledImageArrayDynamicIndexing = true,
674 .shaderStorageBufferArrayDynamicIndexing = true,
675 .shaderStorageImageArrayDynamicIndexing = true,
676 .shaderStorageImageReadWithoutFormat = true,
677 .shaderStorageImageWriteWithoutFormat = true,
678 .shaderClipDistance = true,
679 .shaderCullDistance = true,
680 .shaderFloat64 = true,
681 .shaderInt64 = true,
682 .shaderInt16 = false,
683 .sparseBinding = true,
684 .variableMultisampleRate = true,
685 .inheritedQueries = true,
686 };
687 }
688
689 void radv_GetPhysicalDeviceFeatures2KHR(
690 VkPhysicalDevice physicalDevice,
691 VkPhysicalDeviceFeatures2KHR *pFeatures)
692 {
693 vk_foreach_struct(ext, pFeatures->pNext) {
694 switch (ext->sType) {
695 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
696 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
697 features->variablePointersStorageBuffer = true;
698 features->variablePointers = false;
699 break;
700 }
701 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHX: {
702 VkPhysicalDeviceMultiviewFeaturesKHX *features = (VkPhysicalDeviceMultiviewFeaturesKHX*)ext;
703 features->multiview = true;
704 features->multiviewGeometryShader = true;
705 features->multiviewTessellationShader = true;
706 break;
707 }
708 default:
709 break;
710 }
711 }
712 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
713 }
714
715 void radv_GetPhysicalDeviceProperties(
716 VkPhysicalDevice physicalDevice,
717 VkPhysicalDeviceProperties* pProperties)
718 {
719 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
720 VkSampleCountFlags sample_counts = 0xf;
721
722 /* make sure that the entire descriptor set is addressable with a signed
723 * 32-bit int. So the sum of all limits scaled by descriptor size has to
724 * be at most 2 GiB. the combined image & samples object count as one of
725 * both. This limit is for the pipeline layout, not for the set layout, but
726 * there is no set limit, so we just set a pipeline limit. I don't think
727 * any app is going to hit this soon. */
728 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
729 (32 /* uniform buffer, 32 due to potential space wasted on alignement */ +
730 32 /* storage buffer, 32 due to potential space wasted on alignement */ +
731 32 /* sampler, largest when combined with image */ +
732 64 /* sampled image */ +
733 64 /* storage image */);
734
735 VkPhysicalDeviceLimits limits = {
736 .maxImageDimension1D = (1 << 14),
737 .maxImageDimension2D = (1 << 14),
738 .maxImageDimension3D = (1 << 11),
739 .maxImageDimensionCube = (1 << 14),
740 .maxImageArrayLayers = (1 << 11),
741 .maxTexelBufferElements = 128 * 1024 * 1024,
742 .maxUniformBufferRange = UINT32_MAX,
743 .maxStorageBufferRange = UINT32_MAX,
744 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
745 .maxMemoryAllocationCount = UINT32_MAX,
746 .maxSamplerAllocationCount = 64 * 1024,
747 .bufferImageGranularity = 64, /* A cache line */
748 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
749 .maxBoundDescriptorSets = MAX_SETS,
750 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
751 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
752 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
753 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
754 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
755 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
756 .maxPerStageResources = max_descriptor_set_size,
757 .maxDescriptorSetSamplers = max_descriptor_set_size,
758 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
759 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
760 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
761 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
762 .maxDescriptorSetSampledImages = max_descriptor_set_size,
763 .maxDescriptorSetStorageImages = max_descriptor_set_size,
764 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
765 .maxVertexInputAttributes = 32,
766 .maxVertexInputBindings = 32,
767 .maxVertexInputAttributeOffset = 2047,
768 .maxVertexInputBindingStride = 2048,
769 .maxVertexOutputComponents = 128,
770 .maxTessellationGenerationLevel = 64,
771 .maxTessellationPatchSize = 32,
772 .maxTessellationControlPerVertexInputComponents = 128,
773 .maxTessellationControlPerVertexOutputComponents = 128,
774 .maxTessellationControlPerPatchOutputComponents = 120,
775 .maxTessellationControlTotalOutputComponents = 4096,
776 .maxTessellationEvaluationInputComponents = 128,
777 .maxTessellationEvaluationOutputComponents = 128,
778 .maxGeometryShaderInvocations = 127,
779 .maxGeometryInputComponents = 64,
780 .maxGeometryOutputComponents = 128,
781 .maxGeometryOutputVertices = 256,
782 .maxGeometryTotalOutputComponents = 1024,
783 .maxFragmentInputComponents = 128,
784 .maxFragmentOutputAttachments = 8,
785 .maxFragmentDualSrcAttachments = 1,
786 .maxFragmentCombinedOutputResources = 8,
787 .maxComputeSharedMemorySize = 32768,
788 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
789 .maxComputeWorkGroupInvocations = 2048,
790 .maxComputeWorkGroupSize = {
791 2048,
792 2048,
793 2048
794 },
795 .subPixelPrecisionBits = 4 /* FIXME */,
796 .subTexelPrecisionBits = 4 /* FIXME */,
797 .mipmapPrecisionBits = 4 /* FIXME */,
798 .maxDrawIndexedIndexValue = UINT32_MAX,
799 .maxDrawIndirectCount = UINT32_MAX,
800 .maxSamplerLodBias = 16,
801 .maxSamplerAnisotropy = 16,
802 .maxViewports = MAX_VIEWPORTS,
803 .maxViewportDimensions = { (1 << 14), (1 << 14) },
804 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
805 .viewportSubPixelBits = 13, /* We take a float? */
806 .minMemoryMapAlignment = 4096, /* A page */
807 .minTexelBufferOffsetAlignment = 1,
808 .minUniformBufferOffsetAlignment = 4,
809 .minStorageBufferOffsetAlignment = 4,
810 .minTexelOffset = -32,
811 .maxTexelOffset = 31,
812 .minTexelGatherOffset = -32,
813 .maxTexelGatherOffset = 31,
814 .minInterpolationOffset = -2,
815 .maxInterpolationOffset = 2,
816 .subPixelInterpolationOffsetBits = 8,
817 .maxFramebufferWidth = (1 << 14),
818 .maxFramebufferHeight = (1 << 14),
819 .maxFramebufferLayers = (1 << 10),
820 .framebufferColorSampleCounts = sample_counts,
821 .framebufferDepthSampleCounts = sample_counts,
822 .framebufferStencilSampleCounts = sample_counts,
823 .framebufferNoAttachmentsSampleCounts = sample_counts,
824 .maxColorAttachments = MAX_RTS,
825 .sampledImageColorSampleCounts = sample_counts,
826 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
827 .sampledImageDepthSampleCounts = sample_counts,
828 .sampledImageStencilSampleCounts = sample_counts,
829 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
830 .maxSampleMaskWords = 1,
831 .timestampComputeAndGraphics = true,
832 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
833 .maxClipDistances = 8,
834 .maxCullDistances = 8,
835 .maxCombinedClipAndCullDistances = 8,
836 .discreteQueuePriorities = 1,
837 .pointSizeRange = { 0.125, 255.875 },
838 .lineWidthRange = { 0.0, 7.9921875 },
839 .pointSizeGranularity = (1.0 / 8.0),
840 .lineWidthGranularity = (1.0 / 128.0),
841 .strictLines = false, /* FINISHME */
842 .standardSampleLocations = true,
843 .optimalBufferCopyOffsetAlignment = 128,
844 .optimalBufferCopyRowPitchAlignment = 128,
845 .nonCoherentAtomSize = 64,
846 };
847
848 *pProperties = (VkPhysicalDeviceProperties) {
849 .apiVersion = VK_MAKE_VERSION(1, 0, 42),
850 .driverVersion = vk_get_driver_version(),
851 .vendorID = ATI_VENDOR_ID,
852 .deviceID = pdevice->rad_info.pci_id,
853 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
854 .limits = limits,
855 .sparseProperties = {0},
856 };
857
858 strcpy(pProperties->deviceName, pdevice->name);
859 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
860 }
861
862 void radv_GetPhysicalDeviceProperties2KHR(
863 VkPhysicalDevice physicalDevice,
864 VkPhysicalDeviceProperties2KHR *pProperties)
865 {
866 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
867 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
868
869 vk_foreach_struct(ext, pProperties->pNext) {
870 switch (ext->sType) {
871 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
872 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
873 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
874 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
875 break;
876 }
877 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
878 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
879 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
880 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
881 properties->deviceLUIDValid = false;
882 break;
883 }
884 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHX: {
885 VkPhysicalDeviceMultiviewPropertiesKHX *properties = (VkPhysicalDeviceMultiviewPropertiesKHX*)ext;
886 properties->maxMultiviewViewCount = MAX_VIEWS;
887 properties->maxMultiviewInstanceIndex = INT_MAX;
888 break;
889 }
890 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
891 VkPhysicalDevicePointClippingPropertiesKHR *properties =
892 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
893 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
894 break;
895 }
896 default:
897 break;
898 }
899 }
900 }
901
902 static void radv_get_physical_device_queue_family_properties(
903 struct radv_physical_device* pdevice,
904 uint32_t* pCount,
905 VkQueueFamilyProperties** pQueueFamilyProperties)
906 {
907 int num_queue_families = 1;
908 int idx;
909 if (pdevice->rad_info.num_compute_rings > 0 &&
910 pdevice->rad_info.chip_class >= CIK &&
911 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
912 num_queue_families++;
913
914 if (pQueueFamilyProperties == NULL) {
915 *pCount = num_queue_families;
916 return;
917 }
918
919 if (!*pCount)
920 return;
921
922 idx = 0;
923 if (*pCount >= 1) {
924 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
925 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
926 VK_QUEUE_COMPUTE_BIT |
927 VK_QUEUE_TRANSFER_BIT |
928 VK_QUEUE_SPARSE_BINDING_BIT,
929 .queueCount = 1,
930 .timestampValidBits = 64,
931 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
932 };
933 idx++;
934 }
935
936 if (pdevice->rad_info.num_compute_rings > 0 &&
937 pdevice->rad_info.chip_class >= CIK &&
938 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
939 if (*pCount > idx) {
940 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
941 .queueFlags = VK_QUEUE_COMPUTE_BIT |
942 VK_QUEUE_TRANSFER_BIT |
943 VK_QUEUE_SPARSE_BINDING_BIT,
944 .queueCount = pdevice->rad_info.num_compute_rings,
945 .timestampValidBits = 64,
946 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
947 };
948 idx++;
949 }
950 }
951 *pCount = idx;
952 }
953
954 void radv_GetPhysicalDeviceQueueFamilyProperties(
955 VkPhysicalDevice physicalDevice,
956 uint32_t* pCount,
957 VkQueueFamilyProperties* pQueueFamilyProperties)
958 {
959 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
960 if (!pQueueFamilyProperties) {
961 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
962 return;
963 }
964 VkQueueFamilyProperties *properties[] = {
965 pQueueFamilyProperties + 0,
966 pQueueFamilyProperties + 1,
967 pQueueFamilyProperties + 2,
968 };
969 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
970 assert(*pCount <= 3);
971 }
972
973 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
974 VkPhysicalDevice physicalDevice,
975 uint32_t* pCount,
976 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
977 {
978 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
979 if (!pQueueFamilyProperties) {
980 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
981 return;
982 }
983 VkQueueFamilyProperties *properties[] = {
984 &pQueueFamilyProperties[0].queueFamilyProperties,
985 &pQueueFamilyProperties[1].queueFamilyProperties,
986 &pQueueFamilyProperties[2].queueFamilyProperties,
987 };
988 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
989 assert(*pCount <= 3);
990 }
991
992 void radv_GetPhysicalDeviceMemoryProperties(
993 VkPhysicalDevice physicalDevice,
994 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
995 {
996 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
997
998 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
999
1000 pMemoryProperties->memoryTypeCount = RADV_MEM_TYPE_COUNT;
1001 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM] = (VkMemoryType) {
1002 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
1003 .heapIndex = RADV_MEM_HEAP_VRAM,
1004 };
1005 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_WRITE_COMBINE] = (VkMemoryType) {
1006 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
1007 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
1008 .heapIndex = RADV_MEM_HEAP_GTT,
1009 };
1010 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM_CPU_ACCESS] = (VkMemoryType) {
1011 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
1012 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
1013 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
1014 .heapIndex = RADV_MEM_HEAP_VRAM_CPU_ACCESS,
1015 };
1016 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_CACHED] = (VkMemoryType) {
1017 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
1018 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
1019 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
1020 .heapIndex = RADV_MEM_HEAP_GTT,
1021 };
1022
1023 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
1024 uint64_t visible_vram_size = MIN2(physical_device->rad_info.vram_size,
1025 physical_device->rad_info.vram_vis_size);
1026
1027 pMemoryProperties->memoryHeapCount = RADV_MEM_HEAP_COUNT;
1028 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM] = (VkMemoryHeap) {
1029 .size = physical_device->rad_info.vram_size -
1030 visible_vram_size,
1031 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
1032 };
1033 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = (VkMemoryHeap) {
1034 .size = visible_vram_size,
1035 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
1036 };
1037 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_GTT] = (VkMemoryHeap) {
1038 .size = physical_device->rad_info.gart_size,
1039 .flags = 0,
1040 };
1041 }
1042
1043 void radv_GetPhysicalDeviceMemoryProperties2KHR(
1044 VkPhysicalDevice physicalDevice,
1045 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
1046 {
1047 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1048 &pMemoryProperties->memoryProperties);
1049 }
1050
1051 static int
1052 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1053 int queue_family_index, int idx)
1054 {
1055 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1056 queue->device = device;
1057 queue->queue_family_index = queue_family_index;
1058 queue->queue_idx = idx;
1059
1060 queue->hw_ctx = device->ws->ctx_create(device->ws);
1061 if (!queue->hw_ctx)
1062 return VK_ERROR_OUT_OF_HOST_MEMORY;
1063
1064 return VK_SUCCESS;
1065 }
1066
1067 static void
1068 radv_queue_finish(struct radv_queue *queue)
1069 {
1070 if (queue->hw_ctx)
1071 queue->device->ws->ctx_destroy(queue->hw_ctx);
1072
1073 if (queue->initial_full_flush_preamble_cs)
1074 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1075 if (queue->initial_preamble_cs)
1076 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1077 if (queue->continue_preamble_cs)
1078 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1079 if (queue->descriptor_bo)
1080 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1081 if (queue->scratch_bo)
1082 queue->device->ws->buffer_destroy(queue->scratch_bo);
1083 if (queue->esgs_ring_bo)
1084 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1085 if (queue->gsvs_ring_bo)
1086 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1087 if (queue->tess_factor_ring_bo)
1088 queue->device->ws->buffer_destroy(queue->tess_factor_ring_bo);
1089 if (queue->tess_offchip_ring_bo)
1090 queue->device->ws->buffer_destroy(queue->tess_offchip_ring_bo);
1091 if (queue->compute_scratch_bo)
1092 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1093 }
1094
1095 static void
1096 radv_device_init_gs_info(struct radv_device *device)
1097 {
1098 switch (device->physical_device->rad_info.family) {
1099 case CHIP_OLAND:
1100 case CHIP_HAINAN:
1101 case CHIP_KAVERI:
1102 case CHIP_KABINI:
1103 case CHIP_MULLINS:
1104 case CHIP_ICELAND:
1105 case CHIP_CARRIZO:
1106 case CHIP_STONEY:
1107 device->gs_table_depth = 16;
1108 return;
1109 case CHIP_TAHITI:
1110 case CHIP_PITCAIRN:
1111 case CHIP_VERDE:
1112 case CHIP_BONAIRE:
1113 case CHIP_HAWAII:
1114 case CHIP_TONGA:
1115 case CHIP_FIJI:
1116 case CHIP_POLARIS10:
1117 case CHIP_POLARIS11:
1118 case CHIP_POLARIS12:
1119 case CHIP_VEGA10:
1120 case CHIP_RAVEN:
1121 device->gs_table_depth = 32;
1122 return;
1123 default:
1124 unreachable("unknown GPU");
1125 }
1126 }
1127
1128 VkResult radv_CreateDevice(
1129 VkPhysicalDevice physicalDevice,
1130 const VkDeviceCreateInfo* pCreateInfo,
1131 const VkAllocationCallbacks* pAllocator,
1132 VkDevice* pDevice)
1133 {
1134 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1135 VkResult result;
1136 struct radv_device *device;
1137
1138 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1139 if (!is_extension_enabled(physical_device->extensions.ext_array,
1140 physical_device->extensions.num_ext,
1141 pCreateInfo->ppEnabledExtensionNames[i]))
1142 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
1143 }
1144
1145 /* Check enabled features */
1146 if (pCreateInfo->pEnabledFeatures) {
1147 VkPhysicalDeviceFeatures supported_features;
1148 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1149 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1150 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1151 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1152 for (uint32_t i = 0; i < num_features; i++) {
1153 if (enabled_feature[i] && !supported_feature[i])
1154 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
1155 }
1156 }
1157
1158 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
1159 sizeof(*device), 8,
1160 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1161 if (!device)
1162 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1163
1164 memset(device, 0, sizeof(*device));
1165
1166 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1167 device->instance = physical_device->instance;
1168 device->physical_device = physical_device;
1169
1170 device->ws = physical_device->ws;
1171 if (pAllocator)
1172 device->alloc = *pAllocator;
1173 else
1174 device->alloc = physical_device->instance->alloc;
1175
1176 mtx_init(&device->shader_slab_mutex, mtx_plain);
1177 list_inithead(&device->shader_slabs);
1178
1179 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1180 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1181 uint32_t qfi = queue_create->queueFamilyIndex;
1182
1183 device->queues[qfi] = vk_alloc(&device->alloc,
1184 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1185 if (!device->queues[qfi]) {
1186 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1187 goto fail;
1188 }
1189
1190 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1191
1192 device->queue_count[qfi] = queue_create->queueCount;
1193
1194 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1195 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q);
1196 if (result != VK_SUCCESS)
1197 goto fail;
1198 }
1199 }
1200
1201 #if HAVE_LLVM < 0x0400
1202 device->llvm_supports_spill = false;
1203 #else
1204 device->llvm_supports_spill = true;
1205 #endif
1206
1207 /* The maximum number of scratch waves. Scratch space isn't divided
1208 * evenly between CUs. The number is only a function of the number of CUs.
1209 * We can decrease the constant to decrease the scratch buffer size.
1210 *
1211 * sctx->scratch_waves must be >= the maximum posible size of
1212 * 1 threadgroup, so that the hw doesn't hang from being unable
1213 * to start any.
1214 *
1215 * The recommended value is 4 per CU at most. Higher numbers don't
1216 * bring much benefit, but they still occupy chip resources (think
1217 * async compute). I've seen ~2% performance difference between 4 and 32.
1218 */
1219 uint32_t max_threads_per_block = 2048;
1220 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1221 max_threads_per_block / 64);
1222
1223 radv_device_init_gs_info(device);
1224
1225 device->tess_offchip_block_dw_size =
1226 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1227 device->has_distributed_tess =
1228 device->physical_device->rad_info.chip_class >= VI &&
1229 device->physical_device->rad_info.max_se >= 2;
1230
1231 if (getenv("RADV_TRACE_FILE")) {
1232 if (!radv_init_trace(device))
1233 goto fail;
1234 }
1235
1236 result = radv_device_init_meta(device);
1237 if (result != VK_SUCCESS)
1238 goto fail;
1239
1240 radv_device_init_msaa(device);
1241
1242 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1243 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1244 switch (family) {
1245 case RADV_QUEUE_GENERAL:
1246 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1247 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1248 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1249 break;
1250 case RADV_QUEUE_COMPUTE:
1251 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1252 radeon_emit(device->empty_cs[family], 0);
1253 break;
1254 }
1255 device->ws->cs_finalize(device->empty_cs[family]);
1256 }
1257
1258 if (device->physical_device->rad_info.chip_class >= CIK)
1259 cik_create_gfx_config(device);
1260
1261 VkPipelineCacheCreateInfo ci;
1262 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1263 ci.pNext = NULL;
1264 ci.flags = 0;
1265 ci.pInitialData = NULL;
1266 ci.initialDataSize = 0;
1267 VkPipelineCache pc;
1268 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1269 &ci, NULL, &pc);
1270 if (result != VK_SUCCESS)
1271 goto fail;
1272
1273 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1274
1275 *pDevice = radv_device_to_handle(device);
1276 return VK_SUCCESS;
1277
1278 fail:
1279 if (device->trace_bo)
1280 device->ws->buffer_destroy(device->trace_bo);
1281
1282 if (device->gfx_init)
1283 device->ws->buffer_destroy(device->gfx_init);
1284
1285 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1286 for (unsigned q = 0; q < device->queue_count[i]; q++)
1287 radv_queue_finish(&device->queues[i][q]);
1288 if (device->queue_count[i])
1289 vk_free(&device->alloc, device->queues[i]);
1290 }
1291
1292 vk_free(&device->alloc, device);
1293 return result;
1294 }
1295
1296 void radv_DestroyDevice(
1297 VkDevice _device,
1298 const VkAllocationCallbacks* pAllocator)
1299 {
1300 RADV_FROM_HANDLE(radv_device, device, _device);
1301
1302 if (!device)
1303 return;
1304
1305 if (device->trace_bo)
1306 device->ws->buffer_destroy(device->trace_bo);
1307
1308 if (device->gfx_init)
1309 device->ws->buffer_destroy(device->gfx_init);
1310
1311 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1312 for (unsigned q = 0; q < device->queue_count[i]; q++)
1313 radv_queue_finish(&device->queues[i][q]);
1314 if (device->queue_count[i])
1315 vk_free(&device->alloc, device->queues[i]);
1316 if (device->empty_cs[i])
1317 device->ws->cs_destroy(device->empty_cs[i]);
1318 }
1319 radv_device_finish_meta(device);
1320
1321 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1322 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1323
1324 radv_destroy_shader_slabs(device);
1325
1326 vk_free(&device->alloc, device);
1327 }
1328
1329 VkResult radv_EnumerateInstanceExtensionProperties(
1330 const char* pLayerName,
1331 uint32_t* pPropertyCount,
1332 VkExtensionProperties* pProperties)
1333 {
1334 if (pProperties == NULL) {
1335 *pPropertyCount = ARRAY_SIZE(instance_extensions);
1336 return VK_SUCCESS;
1337 }
1338
1339 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(instance_extensions));
1340 typed_memcpy(pProperties, instance_extensions, *pPropertyCount);
1341
1342 if (*pPropertyCount < ARRAY_SIZE(instance_extensions))
1343 return VK_INCOMPLETE;
1344
1345 return VK_SUCCESS;
1346 }
1347
1348 VkResult radv_EnumerateDeviceExtensionProperties(
1349 VkPhysicalDevice physicalDevice,
1350 const char* pLayerName,
1351 uint32_t* pPropertyCount,
1352 VkExtensionProperties* pProperties)
1353 {
1354 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1355
1356 if (pProperties == NULL) {
1357 *pPropertyCount = pdevice->extensions.num_ext;
1358 return VK_SUCCESS;
1359 }
1360
1361 *pPropertyCount = MIN2(*pPropertyCount, pdevice->extensions.num_ext);
1362 typed_memcpy(pProperties, pdevice->extensions.ext_array, *pPropertyCount);
1363
1364 if (*pPropertyCount < pdevice->extensions.num_ext)
1365 return VK_INCOMPLETE;
1366
1367 return VK_SUCCESS;
1368 }
1369
1370 VkResult radv_EnumerateInstanceLayerProperties(
1371 uint32_t* pPropertyCount,
1372 VkLayerProperties* pProperties)
1373 {
1374 if (pProperties == NULL) {
1375 *pPropertyCount = 0;
1376 return VK_SUCCESS;
1377 }
1378
1379 /* None supported at this time */
1380 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1381 }
1382
1383 VkResult radv_EnumerateDeviceLayerProperties(
1384 VkPhysicalDevice physicalDevice,
1385 uint32_t* pPropertyCount,
1386 VkLayerProperties* pProperties)
1387 {
1388 if (pProperties == NULL) {
1389 *pPropertyCount = 0;
1390 return VK_SUCCESS;
1391 }
1392
1393 /* None supported at this time */
1394 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1395 }
1396
1397 void radv_GetDeviceQueue(
1398 VkDevice _device,
1399 uint32_t queueFamilyIndex,
1400 uint32_t queueIndex,
1401 VkQueue* pQueue)
1402 {
1403 RADV_FROM_HANDLE(radv_device, device, _device);
1404
1405 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
1406 }
1407
1408 static void
1409 fill_geom_tess_rings(struct radv_queue *queue,
1410 uint32_t *map,
1411 bool add_sample_positions,
1412 uint32_t esgs_ring_size,
1413 struct radeon_winsys_bo *esgs_ring_bo,
1414 uint32_t gsvs_ring_size,
1415 struct radeon_winsys_bo *gsvs_ring_bo,
1416 uint32_t tess_factor_ring_size,
1417 struct radeon_winsys_bo *tess_factor_ring_bo,
1418 uint32_t tess_offchip_ring_size,
1419 struct radeon_winsys_bo *tess_offchip_ring_bo)
1420 {
1421 uint64_t esgs_va = 0, gsvs_va = 0;
1422 uint64_t tess_factor_va = 0, tess_offchip_va = 0;
1423 uint32_t *desc = &map[4];
1424
1425 if (esgs_ring_bo)
1426 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1427 if (gsvs_ring_bo)
1428 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1429 if (tess_factor_ring_bo)
1430 tess_factor_va = radv_buffer_get_va(tess_factor_ring_bo);
1431 if (tess_offchip_ring_bo)
1432 tess_offchip_va = radv_buffer_get_va(tess_offchip_ring_bo);
1433
1434 /* stride 0, num records - size, add tid, swizzle, elsize4,
1435 index stride 64 */
1436 desc[0] = esgs_va;
1437 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1438 S_008F04_STRIDE(0) |
1439 S_008F04_SWIZZLE_ENABLE(true);
1440 desc[2] = esgs_ring_size;
1441 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1442 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1443 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1444 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1445 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1446 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1447 S_008F0C_ELEMENT_SIZE(1) |
1448 S_008F0C_INDEX_STRIDE(3) |
1449 S_008F0C_ADD_TID_ENABLE(true);
1450
1451 desc += 4;
1452 /* GS entry for ES->GS ring */
1453 /* stride 0, num records - size, elsize0,
1454 index stride 0 */
1455 desc[0] = esgs_va;
1456 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1457 S_008F04_STRIDE(0) |
1458 S_008F04_SWIZZLE_ENABLE(false);
1459 desc[2] = esgs_ring_size;
1460 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1461 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1462 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1463 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1464 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1465 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1466 S_008F0C_ELEMENT_SIZE(0) |
1467 S_008F0C_INDEX_STRIDE(0) |
1468 S_008F0C_ADD_TID_ENABLE(false);
1469
1470 desc += 4;
1471 /* VS entry for GS->VS ring */
1472 /* stride 0, num records - size, elsize0,
1473 index stride 0 */
1474 desc[0] = gsvs_va;
1475 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1476 S_008F04_STRIDE(0) |
1477 S_008F04_SWIZZLE_ENABLE(false);
1478 desc[2] = gsvs_ring_size;
1479 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1480 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1481 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1482 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1483 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1484 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1485 S_008F0C_ELEMENT_SIZE(0) |
1486 S_008F0C_INDEX_STRIDE(0) |
1487 S_008F0C_ADD_TID_ENABLE(false);
1488 desc += 4;
1489
1490 /* stride gsvs_itemsize, num records 64
1491 elsize 4, index stride 16 */
1492 /* shader will patch stride and desc[2] */
1493 desc[0] = gsvs_va;
1494 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1495 S_008F04_STRIDE(0) |
1496 S_008F04_SWIZZLE_ENABLE(true);
1497 desc[2] = 0;
1498 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1499 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1500 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1501 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1502 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1503 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1504 S_008F0C_ELEMENT_SIZE(1) |
1505 S_008F0C_INDEX_STRIDE(1) |
1506 S_008F0C_ADD_TID_ENABLE(true);
1507 desc += 4;
1508
1509 desc[0] = tess_factor_va;
1510 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va >> 32) |
1511 S_008F04_STRIDE(0) |
1512 S_008F04_SWIZZLE_ENABLE(false);
1513 desc[2] = tess_factor_ring_size;
1514 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1515 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1516 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1517 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1518 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1519 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1520 S_008F0C_ELEMENT_SIZE(0) |
1521 S_008F0C_INDEX_STRIDE(0) |
1522 S_008F0C_ADD_TID_ENABLE(false);
1523 desc += 4;
1524
1525 desc[0] = tess_offchip_va;
1526 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1527 S_008F04_STRIDE(0) |
1528 S_008F04_SWIZZLE_ENABLE(false);
1529 desc[2] = tess_offchip_ring_size;
1530 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1531 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1532 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1533 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1534 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1535 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1536 S_008F0C_ELEMENT_SIZE(0) |
1537 S_008F0C_INDEX_STRIDE(0) |
1538 S_008F0C_ADD_TID_ENABLE(false);
1539 desc += 4;
1540
1541 /* add sample positions after all rings */
1542 memcpy(desc, queue->device->sample_locations_1x, 8);
1543 desc += 2;
1544 memcpy(desc, queue->device->sample_locations_2x, 16);
1545 desc += 4;
1546 memcpy(desc, queue->device->sample_locations_4x, 32);
1547 desc += 8;
1548 memcpy(desc, queue->device->sample_locations_8x, 64);
1549 desc += 16;
1550 memcpy(desc, queue->device->sample_locations_16x, 128);
1551 }
1552
1553 static unsigned
1554 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1555 {
1556 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1557 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1558 device->physical_device->rad_info.family != CHIP_STONEY;
1559 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1560 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1561 device->physical_device->rad_info.max_se;
1562 unsigned offchip_granularity;
1563 unsigned hs_offchip_param;
1564 switch (device->tess_offchip_block_dw_size) {
1565 default:
1566 assert(0);
1567 /* fall through */
1568 case 8192:
1569 offchip_granularity = V_03093C_X_8K_DWORDS;
1570 break;
1571 case 4096:
1572 offchip_granularity = V_03093C_X_4K_DWORDS;
1573 break;
1574 }
1575
1576 switch (device->physical_device->rad_info.chip_class) {
1577 case SI:
1578 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1579 break;
1580 case CIK:
1581 case VI:
1582 case GFX9:
1583 default:
1584 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1585 break;
1586 }
1587
1588 *max_offchip_buffers_p = max_offchip_buffers;
1589 if (device->physical_device->rad_info.chip_class >= CIK) {
1590 if (device->physical_device->rad_info.chip_class >= VI)
1591 --max_offchip_buffers;
1592 hs_offchip_param =
1593 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1594 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1595 } else {
1596 hs_offchip_param =
1597 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1598 }
1599 return hs_offchip_param;
1600 }
1601
1602 static VkResult
1603 radv_get_preamble_cs(struct radv_queue *queue,
1604 uint32_t scratch_size,
1605 uint32_t compute_scratch_size,
1606 uint32_t esgs_ring_size,
1607 uint32_t gsvs_ring_size,
1608 bool needs_tess_rings,
1609 bool needs_sample_positions,
1610 struct radeon_winsys_cs **initial_full_flush_preamble_cs,
1611 struct radeon_winsys_cs **initial_preamble_cs,
1612 struct radeon_winsys_cs **continue_preamble_cs)
1613 {
1614 struct radeon_winsys_bo *scratch_bo = NULL;
1615 struct radeon_winsys_bo *descriptor_bo = NULL;
1616 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1617 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1618 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1619 struct radeon_winsys_bo *tess_factor_ring_bo = NULL;
1620 struct radeon_winsys_bo *tess_offchip_ring_bo = NULL;
1621 struct radeon_winsys_cs *dest_cs[3] = {0};
1622 bool add_tess_rings = false, add_sample_positions = false;
1623 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1624 unsigned max_offchip_buffers;
1625 unsigned hs_offchip_param = 0;
1626 if (!queue->has_tess_rings) {
1627 if (needs_tess_rings)
1628 add_tess_rings = true;
1629 }
1630 if (!queue->has_sample_positions) {
1631 if (needs_sample_positions)
1632 add_sample_positions = true;
1633 }
1634 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1635 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1636 &max_offchip_buffers);
1637 tess_offchip_ring_size = max_offchip_buffers *
1638 queue->device->tess_offchip_block_dw_size * 4;
1639
1640 if (scratch_size <= queue->scratch_size &&
1641 compute_scratch_size <= queue->compute_scratch_size &&
1642 esgs_ring_size <= queue->esgs_ring_size &&
1643 gsvs_ring_size <= queue->gsvs_ring_size &&
1644 !add_tess_rings && !add_sample_positions &&
1645 queue->initial_preamble_cs) {
1646 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1647 *initial_preamble_cs = queue->initial_preamble_cs;
1648 *continue_preamble_cs = queue->continue_preamble_cs;
1649 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1650 *continue_preamble_cs = NULL;
1651 return VK_SUCCESS;
1652 }
1653
1654 if (scratch_size > queue->scratch_size) {
1655 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1656 scratch_size,
1657 4096,
1658 RADEON_DOMAIN_VRAM,
1659 RADEON_FLAG_NO_CPU_ACCESS);
1660 if (!scratch_bo)
1661 goto fail;
1662 } else
1663 scratch_bo = queue->scratch_bo;
1664
1665 if (compute_scratch_size > queue->compute_scratch_size) {
1666 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1667 compute_scratch_size,
1668 4096,
1669 RADEON_DOMAIN_VRAM,
1670 RADEON_FLAG_NO_CPU_ACCESS);
1671 if (!compute_scratch_bo)
1672 goto fail;
1673
1674 } else
1675 compute_scratch_bo = queue->compute_scratch_bo;
1676
1677 if (esgs_ring_size > queue->esgs_ring_size) {
1678 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1679 esgs_ring_size,
1680 4096,
1681 RADEON_DOMAIN_VRAM,
1682 RADEON_FLAG_NO_CPU_ACCESS);
1683 if (!esgs_ring_bo)
1684 goto fail;
1685 } else {
1686 esgs_ring_bo = queue->esgs_ring_bo;
1687 esgs_ring_size = queue->esgs_ring_size;
1688 }
1689
1690 if (gsvs_ring_size > queue->gsvs_ring_size) {
1691 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1692 gsvs_ring_size,
1693 4096,
1694 RADEON_DOMAIN_VRAM,
1695 RADEON_FLAG_NO_CPU_ACCESS);
1696 if (!gsvs_ring_bo)
1697 goto fail;
1698 } else {
1699 gsvs_ring_bo = queue->gsvs_ring_bo;
1700 gsvs_ring_size = queue->gsvs_ring_size;
1701 }
1702
1703 if (add_tess_rings) {
1704 tess_factor_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1705 tess_factor_ring_size,
1706 256,
1707 RADEON_DOMAIN_VRAM,
1708 RADEON_FLAG_NO_CPU_ACCESS);
1709 if (!tess_factor_ring_bo)
1710 goto fail;
1711 tess_offchip_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1712 tess_offchip_ring_size,
1713 256,
1714 RADEON_DOMAIN_VRAM,
1715 RADEON_FLAG_NO_CPU_ACCESS);
1716 if (!tess_offchip_ring_bo)
1717 goto fail;
1718 } else {
1719 tess_factor_ring_bo = queue->tess_factor_ring_bo;
1720 tess_offchip_ring_bo = queue->tess_offchip_ring_bo;
1721 }
1722
1723 if (scratch_bo != queue->scratch_bo ||
1724 esgs_ring_bo != queue->esgs_ring_bo ||
1725 gsvs_ring_bo != queue->gsvs_ring_bo ||
1726 tess_factor_ring_bo != queue->tess_factor_ring_bo ||
1727 tess_offchip_ring_bo != queue->tess_offchip_ring_bo || add_sample_positions) {
1728 uint32_t size = 0;
1729 if (gsvs_ring_bo || esgs_ring_bo ||
1730 tess_factor_ring_bo || tess_offchip_ring_bo || add_sample_positions) {
1731 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
1732 if (add_sample_positions)
1733 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1734 }
1735 else if (scratch_bo)
1736 size = 8; /* 2 dword */
1737
1738 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1739 size,
1740 4096,
1741 RADEON_DOMAIN_VRAM,
1742 RADEON_FLAG_CPU_ACCESS);
1743 if (!descriptor_bo)
1744 goto fail;
1745 } else
1746 descriptor_bo = queue->descriptor_bo;
1747
1748 for(int i = 0; i < 3; ++i) {
1749 struct radeon_winsys_cs *cs = NULL;
1750 cs = queue->device->ws->cs_create(queue->device->ws,
1751 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1752 if (!cs)
1753 goto fail;
1754
1755 dest_cs[i] = cs;
1756
1757 if (scratch_bo)
1758 queue->device->ws->cs_add_buffer(cs, scratch_bo, 8);
1759
1760 if (esgs_ring_bo)
1761 queue->device->ws->cs_add_buffer(cs, esgs_ring_bo, 8);
1762
1763 if (gsvs_ring_bo)
1764 queue->device->ws->cs_add_buffer(cs, gsvs_ring_bo, 8);
1765
1766 if (tess_factor_ring_bo)
1767 queue->device->ws->cs_add_buffer(cs, tess_factor_ring_bo, 8);
1768
1769 if (tess_offchip_ring_bo)
1770 queue->device->ws->cs_add_buffer(cs, tess_offchip_ring_bo, 8);
1771
1772 if (descriptor_bo)
1773 queue->device->ws->cs_add_buffer(cs, descriptor_bo, 8);
1774
1775 if (descriptor_bo != queue->descriptor_bo) {
1776 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1777
1778 if (scratch_bo) {
1779 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
1780 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1781 S_008F04_SWIZZLE_ENABLE(1);
1782 map[0] = scratch_va;
1783 map[1] = rsrc1;
1784 }
1785
1786 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo ||
1787 add_sample_positions)
1788 fill_geom_tess_rings(queue, map, add_sample_positions,
1789 esgs_ring_size, esgs_ring_bo,
1790 gsvs_ring_size, gsvs_ring_bo,
1791 tess_factor_ring_size, tess_factor_ring_bo,
1792 tess_offchip_ring_size, tess_offchip_ring_bo);
1793
1794 queue->device->ws->buffer_unmap(descriptor_bo);
1795 }
1796
1797 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo) {
1798 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1799 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1800 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1801 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1802 }
1803
1804 if (esgs_ring_bo || gsvs_ring_bo) {
1805 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1806 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1807 radeon_emit(cs, esgs_ring_size >> 8);
1808 radeon_emit(cs, gsvs_ring_size >> 8);
1809 } else {
1810 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1811 radeon_emit(cs, esgs_ring_size >> 8);
1812 radeon_emit(cs, gsvs_ring_size >> 8);
1813 }
1814 }
1815
1816 if (tess_factor_ring_bo) {
1817 uint64_t tf_va = radv_buffer_get_va(tess_factor_ring_bo);
1818 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1819 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1820 S_030938_SIZE(tess_factor_ring_size / 4));
1821 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1822 tf_va >> 8);
1823 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1824 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1825 tf_va >> 40);
1826 }
1827 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
1828 } else {
1829 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1830 S_008988_SIZE(tess_factor_ring_size / 4));
1831 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1832 tf_va >> 8);
1833 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1834 hs_offchip_param);
1835 }
1836 }
1837
1838 if (descriptor_bo) {
1839 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1840 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1841 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1842 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1843 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1844 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1845
1846 uint64_t va = radv_buffer_get_va(descriptor_bo);
1847
1848 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1849 radeon_set_sh_reg_seq(cs, regs[i], 2);
1850 radeon_emit(cs, va);
1851 radeon_emit(cs, va >> 32);
1852 }
1853 }
1854
1855 if (compute_scratch_bo) {
1856 uint64_t scratch_va = radv_buffer_get_va(compute_scratch_bo);
1857 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1858 S_008F04_SWIZZLE_ENABLE(1);
1859
1860 queue->device->ws->cs_add_buffer(cs, compute_scratch_bo, 8);
1861
1862 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1863 radeon_emit(cs, scratch_va);
1864 radeon_emit(cs, rsrc1);
1865 }
1866
1867 if (i == 0) {
1868 si_cs_emit_cache_flush(cs,
1869 false,
1870 queue->device->physical_device->rad_info.chip_class,
1871 NULL, 0,
1872 queue->queue_family_index == RING_COMPUTE &&
1873 queue->device->physical_device->rad_info.chip_class >= CIK,
1874 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
1875 RADV_CMD_FLAG_INV_ICACHE |
1876 RADV_CMD_FLAG_INV_SMEM_L1 |
1877 RADV_CMD_FLAG_INV_VMEM_L1 |
1878 RADV_CMD_FLAG_INV_GLOBAL_L2);
1879 } else if (i == 1) {
1880 si_cs_emit_cache_flush(cs,
1881 false,
1882 queue->device->physical_device->rad_info.chip_class,
1883 NULL, 0,
1884 queue->queue_family_index == RING_COMPUTE &&
1885 queue->device->physical_device->rad_info.chip_class >= CIK,
1886 RADV_CMD_FLAG_INV_ICACHE |
1887 RADV_CMD_FLAG_INV_SMEM_L1 |
1888 RADV_CMD_FLAG_INV_VMEM_L1 |
1889 RADV_CMD_FLAG_INV_GLOBAL_L2);
1890 }
1891
1892 if (!queue->device->ws->cs_finalize(cs))
1893 goto fail;
1894 }
1895
1896 if (queue->initial_full_flush_preamble_cs)
1897 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1898
1899 if (queue->initial_preamble_cs)
1900 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1901
1902 if (queue->continue_preamble_cs)
1903 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1904
1905 queue->initial_full_flush_preamble_cs = dest_cs[0];
1906 queue->initial_preamble_cs = dest_cs[1];
1907 queue->continue_preamble_cs = dest_cs[2];
1908
1909 if (scratch_bo != queue->scratch_bo) {
1910 if (queue->scratch_bo)
1911 queue->device->ws->buffer_destroy(queue->scratch_bo);
1912 queue->scratch_bo = scratch_bo;
1913 queue->scratch_size = scratch_size;
1914 }
1915
1916 if (compute_scratch_bo != queue->compute_scratch_bo) {
1917 if (queue->compute_scratch_bo)
1918 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1919 queue->compute_scratch_bo = compute_scratch_bo;
1920 queue->compute_scratch_size = compute_scratch_size;
1921 }
1922
1923 if (esgs_ring_bo != queue->esgs_ring_bo) {
1924 if (queue->esgs_ring_bo)
1925 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1926 queue->esgs_ring_bo = esgs_ring_bo;
1927 queue->esgs_ring_size = esgs_ring_size;
1928 }
1929
1930 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
1931 if (queue->gsvs_ring_bo)
1932 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1933 queue->gsvs_ring_bo = gsvs_ring_bo;
1934 queue->gsvs_ring_size = gsvs_ring_size;
1935 }
1936
1937 if (tess_factor_ring_bo != queue->tess_factor_ring_bo) {
1938 queue->tess_factor_ring_bo = tess_factor_ring_bo;
1939 }
1940
1941 if (tess_offchip_ring_bo != queue->tess_offchip_ring_bo) {
1942 queue->tess_offchip_ring_bo = tess_offchip_ring_bo;
1943 queue->has_tess_rings = true;
1944 }
1945
1946 if (descriptor_bo != queue->descriptor_bo) {
1947 if (queue->descriptor_bo)
1948 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1949
1950 queue->descriptor_bo = descriptor_bo;
1951 }
1952
1953 if (add_sample_positions)
1954 queue->has_sample_positions = true;
1955
1956 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1957 *initial_preamble_cs = queue->initial_preamble_cs;
1958 *continue_preamble_cs = queue->continue_preamble_cs;
1959 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1960 *continue_preamble_cs = NULL;
1961 return VK_SUCCESS;
1962 fail:
1963 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
1964 if (dest_cs[i])
1965 queue->device->ws->cs_destroy(dest_cs[i]);
1966 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
1967 queue->device->ws->buffer_destroy(descriptor_bo);
1968 if (scratch_bo && scratch_bo != queue->scratch_bo)
1969 queue->device->ws->buffer_destroy(scratch_bo);
1970 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
1971 queue->device->ws->buffer_destroy(compute_scratch_bo);
1972 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
1973 queue->device->ws->buffer_destroy(esgs_ring_bo);
1974 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
1975 queue->device->ws->buffer_destroy(gsvs_ring_bo);
1976 if (tess_factor_ring_bo && tess_factor_ring_bo != queue->tess_factor_ring_bo)
1977 queue->device->ws->buffer_destroy(tess_factor_ring_bo);
1978 if (tess_offchip_ring_bo && tess_offchip_ring_bo != queue->tess_offchip_ring_bo)
1979 queue->device->ws->buffer_destroy(tess_offchip_ring_bo);
1980 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1981 }
1982
1983 static VkResult radv_alloc_sem_counts(struct radv_winsys_sem_counts *counts,
1984 int num_sems,
1985 const VkSemaphore *sems,
1986 bool reset_temp)
1987 {
1988 int syncobj_idx = 0, sem_idx = 0;
1989
1990 if (num_sems == 0)
1991 return VK_SUCCESS;
1992 for (uint32_t i = 0; i < num_sems; i++) {
1993 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1994
1995 if (sem->temp_syncobj || sem->syncobj)
1996 counts->syncobj_count++;
1997 else
1998 counts->sem_count++;
1999 }
2000
2001 if (counts->syncobj_count) {
2002 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2003 if (!counts->syncobj)
2004 return VK_ERROR_OUT_OF_HOST_MEMORY;
2005 }
2006
2007 if (counts->sem_count) {
2008 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2009 if (!counts->sem) {
2010 free(counts->syncobj);
2011 return VK_ERROR_OUT_OF_HOST_MEMORY;
2012 }
2013 }
2014
2015 for (uint32_t i = 0; i < num_sems; i++) {
2016 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2017
2018 if (sem->temp_syncobj) {
2019 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2020 if (reset_temp) {
2021 /* after we wait on a temp import - drop it */
2022 sem->temp_syncobj = 0;
2023 }
2024 }
2025 else if (sem->syncobj)
2026 counts->syncobj[syncobj_idx++] = sem->syncobj;
2027 else {
2028 assert(sem->sem);
2029 counts->sem[sem_idx++] = sem->sem;
2030 }
2031 }
2032
2033 return VK_SUCCESS;
2034 }
2035
2036 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2037 {
2038 free(sem_info->wait.syncobj);
2039 free(sem_info->wait.sem);
2040 free(sem_info->signal.syncobj);
2041 free(sem_info->signal.sem);
2042 }
2043
2044 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
2045 int num_wait_sems,
2046 const VkSemaphore *wait_sems,
2047 int num_signal_sems,
2048 const VkSemaphore *signal_sems)
2049 {
2050 VkResult ret;
2051 memset(sem_info, 0, sizeof(*sem_info));
2052
2053 ret = radv_alloc_sem_counts(&sem_info->wait, num_wait_sems, wait_sems, true);
2054 if (ret)
2055 return ret;
2056 ret = radv_alloc_sem_counts(&sem_info->signal, num_signal_sems, signal_sems, false);
2057 if (ret)
2058 radv_free_sem_info(sem_info);
2059
2060 /* caller can override these */
2061 sem_info->cs_emit_wait = true;
2062 sem_info->cs_emit_signal = true;
2063 return ret;
2064 }
2065
2066 VkResult radv_QueueSubmit(
2067 VkQueue _queue,
2068 uint32_t submitCount,
2069 const VkSubmitInfo* pSubmits,
2070 VkFence _fence)
2071 {
2072 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2073 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2074 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2075 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2076 int ret;
2077 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2078 uint32_t scratch_size = 0;
2079 uint32_t compute_scratch_size = 0;
2080 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2081 struct radeon_winsys_cs *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2082 VkResult result;
2083 bool fence_emitted = false;
2084 bool tess_rings_needed = false;
2085 bool sample_positions_needed = false;
2086
2087 /* Do this first so failing to allocate scratch buffers can't result in
2088 * partially executed submissions. */
2089 for (uint32_t i = 0; i < submitCount; i++) {
2090 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2091 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2092 pSubmits[i].pCommandBuffers[j]);
2093
2094 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2095 compute_scratch_size = MAX2(compute_scratch_size,
2096 cmd_buffer->compute_scratch_size_needed);
2097 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2098 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2099 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2100 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2101 }
2102 }
2103
2104 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2105 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2106 sample_positions_needed, &initial_flush_preamble_cs,
2107 &initial_preamble_cs, &continue_preamble_cs);
2108 if (result != VK_SUCCESS)
2109 return result;
2110
2111 for (uint32_t i = 0; i < submitCount; i++) {
2112 struct radeon_winsys_cs **cs_array;
2113 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2114 bool can_patch = true;
2115 uint32_t advance;
2116 struct radv_winsys_sem_info sem_info;
2117
2118 result = radv_alloc_sem_info(&sem_info,
2119 pSubmits[i].waitSemaphoreCount,
2120 pSubmits[i].pWaitSemaphores,
2121 pSubmits[i].signalSemaphoreCount,
2122 pSubmits[i].pSignalSemaphores);
2123 if (result != VK_SUCCESS)
2124 return result;
2125
2126 if (!pSubmits[i].commandBufferCount) {
2127 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2128 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2129 &queue->device->empty_cs[queue->queue_family_index],
2130 1, NULL, NULL,
2131 &sem_info,
2132 false, base_fence);
2133 if (ret) {
2134 radv_loge("failed to submit CS %d\n", i);
2135 abort();
2136 }
2137 fence_emitted = true;
2138 }
2139 radv_free_sem_info(&sem_info);
2140 continue;
2141 }
2142
2143 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
2144 (pSubmits[i].commandBufferCount));
2145
2146 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2147 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2148 pSubmits[i].pCommandBuffers[j]);
2149 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2150
2151 cs_array[j] = cmd_buffer->cs;
2152 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2153 can_patch = false;
2154 }
2155
2156 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2157 struct radeon_winsys_cs *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2158 advance = MIN2(max_cs_submission,
2159 pSubmits[i].commandBufferCount - j);
2160
2161 if (queue->device->trace_bo)
2162 *queue->device->trace_id_ptr = 0;
2163
2164 sem_info.cs_emit_wait = j == 0;
2165 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2166
2167 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2168 advance, initial_preamble, continue_preamble_cs,
2169 &sem_info,
2170 can_patch, base_fence);
2171
2172 if (ret) {
2173 radv_loge("failed to submit CS %d\n", i);
2174 abort();
2175 }
2176 fence_emitted = true;
2177 if (queue->device->trace_bo) {
2178 radv_check_gpu_hangs(queue, cs_array[j]);
2179 }
2180 }
2181
2182 radv_free_sem_info(&sem_info);
2183 free(cs_array);
2184 }
2185
2186 if (fence) {
2187 if (!fence_emitted) {
2188 struct radv_winsys_sem_info sem_info = {0};
2189 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2190 &queue->device->empty_cs[queue->queue_family_index],
2191 1, NULL, NULL, &sem_info,
2192 false, base_fence);
2193 }
2194 fence->submitted = true;
2195 }
2196
2197 return VK_SUCCESS;
2198 }
2199
2200 VkResult radv_QueueWaitIdle(
2201 VkQueue _queue)
2202 {
2203 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2204
2205 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2206 radv_queue_family_to_ring(queue->queue_family_index),
2207 queue->queue_idx);
2208 return VK_SUCCESS;
2209 }
2210
2211 VkResult radv_DeviceWaitIdle(
2212 VkDevice _device)
2213 {
2214 RADV_FROM_HANDLE(radv_device, device, _device);
2215
2216 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2217 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2218 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2219 }
2220 }
2221 return VK_SUCCESS;
2222 }
2223
2224 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2225 VkInstance instance,
2226 const char* pName)
2227 {
2228 return radv_lookup_entrypoint(pName);
2229 }
2230
2231 /* The loader wants us to expose a second GetInstanceProcAddr function
2232 * to work around certain LD_PRELOAD issues seen in apps.
2233 */
2234 PUBLIC
2235 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2236 VkInstance instance,
2237 const char* pName);
2238
2239 PUBLIC
2240 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2241 VkInstance instance,
2242 const char* pName)
2243 {
2244 return radv_GetInstanceProcAddr(instance, pName);
2245 }
2246
2247 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2248 VkDevice device,
2249 const char* pName)
2250 {
2251 return radv_lookup_entrypoint(pName);
2252 }
2253
2254 bool radv_get_memory_fd(struct radv_device *device,
2255 struct radv_device_memory *memory,
2256 int *pFD)
2257 {
2258 struct radeon_bo_metadata metadata;
2259
2260 if (memory->image) {
2261 radv_init_metadata(device, memory->image, &metadata);
2262 device->ws->buffer_set_metadata(memory->bo, &metadata);
2263 }
2264
2265 return device->ws->buffer_get_fd(device->ws, memory->bo,
2266 pFD);
2267 }
2268
2269 VkResult radv_AllocateMemory(
2270 VkDevice _device,
2271 const VkMemoryAllocateInfo* pAllocateInfo,
2272 const VkAllocationCallbacks* pAllocator,
2273 VkDeviceMemory* pMem)
2274 {
2275 RADV_FROM_HANDLE(radv_device, device, _device);
2276 struct radv_device_memory *mem;
2277 VkResult result;
2278 enum radeon_bo_domain domain;
2279 uint32_t flags = 0;
2280
2281 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2282
2283 if (pAllocateInfo->allocationSize == 0) {
2284 /* Apparently, this is allowed */
2285 *pMem = VK_NULL_HANDLE;
2286 return VK_SUCCESS;
2287 }
2288
2289 const VkImportMemoryFdInfoKHR *import_info =
2290 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2291 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2292 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2293
2294 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2295 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2296 if (mem == NULL)
2297 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2298
2299 if (dedicate_info) {
2300 mem->image = radv_image_from_handle(dedicate_info->image);
2301 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2302 } else {
2303 mem->image = NULL;
2304 mem->buffer = NULL;
2305 }
2306
2307 if (import_info) {
2308 assert(import_info->handleType ==
2309 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
2310 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2311 NULL, NULL);
2312 if (!mem->bo) {
2313 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2314 goto fail;
2315 } else {
2316 close(import_info->fd);
2317 goto out_success;
2318 }
2319 }
2320
2321 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2322 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2323 pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_CACHED)
2324 domain = RADEON_DOMAIN_GTT;
2325 else
2326 domain = RADEON_DOMAIN_VRAM;
2327
2328 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_VRAM)
2329 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2330 else
2331 flags |= RADEON_FLAG_CPU_ACCESS;
2332
2333 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2334 flags |= RADEON_FLAG_GTT_WC;
2335
2336 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2337 domain, flags);
2338
2339 if (!mem->bo) {
2340 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2341 goto fail;
2342 }
2343 mem->type_index = pAllocateInfo->memoryTypeIndex;
2344 out_success:
2345 *pMem = radv_device_memory_to_handle(mem);
2346
2347 return VK_SUCCESS;
2348
2349 fail:
2350 vk_free2(&device->alloc, pAllocator, mem);
2351
2352 return result;
2353 }
2354
2355 void radv_FreeMemory(
2356 VkDevice _device,
2357 VkDeviceMemory _mem,
2358 const VkAllocationCallbacks* pAllocator)
2359 {
2360 RADV_FROM_HANDLE(radv_device, device, _device);
2361 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2362
2363 if (mem == NULL)
2364 return;
2365
2366 device->ws->buffer_destroy(mem->bo);
2367 mem->bo = NULL;
2368
2369 vk_free2(&device->alloc, pAllocator, mem);
2370 }
2371
2372 VkResult radv_MapMemory(
2373 VkDevice _device,
2374 VkDeviceMemory _memory,
2375 VkDeviceSize offset,
2376 VkDeviceSize size,
2377 VkMemoryMapFlags flags,
2378 void** ppData)
2379 {
2380 RADV_FROM_HANDLE(radv_device, device, _device);
2381 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2382
2383 if (mem == NULL) {
2384 *ppData = NULL;
2385 return VK_SUCCESS;
2386 }
2387
2388 *ppData = device->ws->buffer_map(mem->bo);
2389 if (*ppData) {
2390 *ppData += offset;
2391 return VK_SUCCESS;
2392 }
2393
2394 return VK_ERROR_MEMORY_MAP_FAILED;
2395 }
2396
2397 void radv_UnmapMemory(
2398 VkDevice _device,
2399 VkDeviceMemory _memory)
2400 {
2401 RADV_FROM_HANDLE(radv_device, device, _device);
2402 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2403
2404 if (mem == NULL)
2405 return;
2406
2407 device->ws->buffer_unmap(mem->bo);
2408 }
2409
2410 VkResult radv_FlushMappedMemoryRanges(
2411 VkDevice _device,
2412 uint32_t memoryRangeCount,
2413 const VkMappedMemoryRange* pMemoryRanges)
2414 {
2415 return VK_SUCCESS;
2416 }
2417
2418 VkResult radv_InvalidateMappedMemoryRanges(
2419 VkDevice _device,
2420 uint32_t memoryRangeCount,
2421 const VkMappedMemoryRange* pMemoryRanges)
2422 {
2423 return VK_SUCCESS;
2424 }
2425
2426 void radv_GetBufferMemoryRequirements(
2427 VkDevice device,
2428 VkBuffer _buffer,
2429 VkMemoryRequirements* pMemoryRequirements)
2430 {
2431 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2432
2433 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2434
2435 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2436 pMemoryRequirements->alignment = 4096;
2437 else
2438 pMemoryRequirements->alignment = 16;
2439
2440 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2441 }
2442
2443 void radv_GetBufferMemoryRequirements2KHR(
2444 VkDevice device,
2445 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2446 VkMemoryRequirements2KHR* pMemoryRequirements)
2447 {
2448 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2449 &pMemoryRequirements->memoryRequirements);
2450
2451 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2452 switch (ext->sType) {
2453 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2454 VkMemoryDedicatedRequirementsKHR *req =
2455 (VkMemoryDedicatedRequirementsKHR *) ext;
2456 req->requiresDedicatedAllocation = false;
2457 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2458 break;
2459 }
2460 default:
2461 break;
2462 }
2463 }
2464 }
2465
2466 void radv_GetImageMemoryRequirements(
2467 VkDevice device,
2468 VkImage _image,
2469 VkMemoryRequirements* pMemoryRequirements)
2470 {
2471 RADV_FROM_HANDLE(radv_image, image, _image);
2472
2473 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2474
2475 pMemoryRequirements->size = image->size;
2476 pMemoryRequirements->alignment = image->alignment;
2477 }
2478
2479 void radv_GetImageMemoryRequirements2KHR(
2480 VkDevice device,
2481 const VkImageMemoryRequirementsInfo2KHR* pInfo,
2482 VkMemoryRequirements2KHR* pMemoryRequirements)
2483 {
2484 radv_GetImageMemoryRequirements(device, pInfo->image,
2485 &pMemoryRequirements->memoryRequirements);
2486
2487 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
2488
2489 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2490 switch (ext->sType) {
2491 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2492 VkMemoryDedicatedRequirementsKHR *req =
2493 (VkMemoryDedicatedRequirementsKHR *) ext;
2494 req->requiresDedicatedAllocation = image->shareable;
2495 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2496 break;
2497 }
2498 default:
2499 break;
2500 }
2501 }
2502 }
2503
2504 void radv_GetImageSparseMemoryRequirements(
2505 VkDevice device,
2506 VkImage image,
2507 uint32_t* pSparseMemoryRequirementCount,
2508 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2509 {
2510 stub();
2511 }
2512
2513 void radv_GetImageSparseMemoryRequirements2KHR(
2514 VkDevice device,
2515 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
2516 uint32_t* pSparseMemoryRequirementCount,
2517 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
2518 {
2519 stub();
2520 }
2521
2522 void radv_GetDeviceMemoryCommitment(
2523 VkDevice device,
2524 VkDeviceMemory memory,
2525 VkDeviceSize* pCommittedMemoryInBytes)
2526 {
2527 *pCommittedMemoryInBytes = 0;
2528 }
2529
2530 VkResult radv_BindBufferMemory2KHR(VkDevice device,
2531 uint32_t bindInfoCount,
2532 const VkBindBufferMemoryInfoKHR *pBindInfos)
2533 {
2534 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2535 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2536 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
2537
2538 if (mem) {
2539 buffer->bo = mem->bo;
2540 buffer->offset = pBindInfos[i].memoryOffset;
2541 } else {
2542 buffer->bo = NULL;
2543 }
2544 }
2545 return VK_SUCCESS;
2546 }
2547
2548 VkResult radv_BindBufferMemory(
2549 VkDevice device,
2550 VkBuffer buffer,
2551 VkDeviceMemory memory,
2552 VkDeviceSize memoryOffset)
2553 {
2554 const VkBindBufferMemoryInfoKHR info = {
2555 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2556 .buffer = buffer,
2557 .memory = memory,
2558 .memoryOffset = memoryOffset
2559 };
2560
2561 return radv_BindBufferMemory2KHR(device, 1, &info);
2562 }
2563
2564 VkResult radv_BindImageMemory2KHR(VkDevice device,
2565 uint32_t bindInfoCount,
2566 const VkBindImageMemoryInfoKHR *pBindInfos)
2567 {
2568 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2569 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2570 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
2571
2572 if (mem) {
2573 image->bo = mem->bo;
2574 image->offset = pBindInfos[i].memoryOffset;
2575 } else {
2576 image->bo = NULL;
2577 image->offset = 0;
2578 }
2579 }
2580 return VK_SUCCESS;
2581 }
2582
2583
2584 VkResult radv_BindImageMemory(
2585 VkDevice device,
2586 VkImage image,
2587 VkDeviceMemory memory,
2588 VkDeviceSize memoryOffset)
2589 {
2590 const VkBindImageMemoryInfoKHR info = {
2591 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2592 .image = image,
2593 .memory = memory,
2594 .memoryOffset = memoryOffset
2595 };
2596
2597 return radv_BindImageMemory2KHR(device, 1, &info);
2598 }
2599
2600
2601 static void
2602 radv_sparse_buffer_bind_memory(struct radv_device *device,
2603 const VkSparseBufferMemoryBindInfo *bind)
2604 {
2605 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
2606
2607 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2608 struct radv_device_memory *mem = NULL;
2609
2610 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2611 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2612
2613 device->ws->buffer_virtual_bind(buffer->bo,
2614 bind->pBinds[i].resourceOffset,
2615 bind->pBinds[i].size,
2616 mem ? mem->bo : NULL,
2617 bind->pBinds[i].memoryOffset);
2618 }
2619 }
2620
2621 static void
2622 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
2623 const VkSparseImageOpaqueMemoryBindInfo *bind)
2624 {
2625 RADV_FROM_HANDLE(radv_image, image, bind->image);
2626
2627 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2628 struct radv_device_memory *mem = NULL;
2629
2630 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2631 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2632
2633 device->ws->buffer_virtual_bind(image->bo,
2634 bind->pBinds[i].resourceOffset,
2635 bind->pBinds[i].size,
2636 mem ? mem->bo : NULL,
2637 bind->pBinds[i].memoryOffset);
2638 }
2639 }
2640
2641 VkResult radv_QueueBindSparse(
2642 VkQueue _queue,
2643 uint32_t bindInfoCount,
2644 const VkBindSparseInfo* pBindInfo,
2645 VkFence _fence)
2646 {
2647 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2648 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2649 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2650 bool fence_emitted = false;
2651
2652 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2653 struct radv_winsys_sem_info sem_info;
2654 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
2655 radv_sparse_buffer_bind_memory(queue->device,
2656 pBindInfo[i].pBufferBinds + j);
2657 }
2658
2659 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
2660 radv_sparse_image_opaque_bind_memory(queue->device,
2661 pBindInfo[i].pImageOpaqueBinds + j);
2662 }
2663
2664 VkResult result;
2665 result = radv_alloc_sem_info(&sem_info,
2666 pBindInfo[i].waitSemaphoreCount,
2667 pBindInfo[i].pWaitSemaphores,
2668 pBindInfo[i].signalSemaphoreCount,
2669 pBindInfo[i].pSignalSemaphores);
2670 if (result != VK_SUCCESS)
2671 return result;
2672
2673 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
2674 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2675 &queue->device->empty_cs[queue->queue_family_index],
2676 1, NULL, NULL,
2677 &sem_info,
2678 false, base_fence);
2679 fence_emitted = true;
2680 if (fence)
2681 fence->submitted = true;
2682 }
2683
2684 radv_free_sem_info(&sem_info);
2685
2686 }
2687
2688 if (fence && !fence_emitted) {
2689 fence->signalled = true;
2690 }
2691
2692 return VK_SUCCESS;
2693 }
2694
2695 VkResult radv_CreateFence(
2696 VkDevice _device,
2697 const VkFenceCreateInfo* pCreateInfo,
2698 const VkAllocationCallbacks* pAllocator,
2699 VkFence* pFence)
2700 {
2701 RADV_FROM_HANDLE(radv_device, device, _device);
2702 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
2703 sizeof(*fence), 8,
2704 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2705
2706 if (!fence)
2707 return VK_ERROR_OUT_OF_HOST_MEMORY;
2708
2709 memset(fence, 0, sizeof(*fence));
2710 fence->submitted = false;
2711 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
2712 fence->fence = device->ws->create_fence();
2713 if (!fence->fence) {
2714 vk_free2(&device->alloc, pAllocator, fence);
2715 return VK_ERROR_OUT_OF_HOST_MEMORY;
2716 }
2717
2718 *pFence = radv_fence_to_handle(fence);
2719
2720 return VK_SUCCESS;
2721 }
2722
2723 void radv_DestroyFence(
2724 VkDevice _device,
2725 VkFence _fence,
2726 const VkAllocationCallbacks* pAllocator)
2727 {
2728 RADV_FROM_HANDLE(radv_device, device, _device);
2729 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2730
2731 if (!fence)
2732 return;
2733 device->ws->destroy_fence(fence->fence);
2734 vk_free2(&device->alloc, pAllocator, fence);
2735 }
2736
2737 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
2738 {
2739 uint64_t current_time;
2740 struct timespec tv;
2741
2742 clock_gettime(CLOCK_MONOTONIC, &tv);
2743 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
2744
2745 timeout = MIN2(UINT64_MAX - current_time, timeout);
2746
2747 return current_time + timeout;
2748 }
2749
2750 VkResult radv_WaitForFences(
2751 VkDevice _device,
2752 uint32_t fenceCount,
2753 const VkFence* pFences,
2754 VkBool32 waitAll,
2755 uint64_t timeout)
2756 {
2757 RADV_FROM_HANDLE(radv_device, device, _device);
2758 timeout = radv_get_absolute_timeout(timeout);
2759
2760 if (!waitAll && fenceCount > 1) {
2761 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
2762 }
2763
2764 for (uint32_t i = 0; i < fenceCount; ++i) {
2765 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2766 bool expired = false;
2767
2768 if (fence->signalled)
2769 continue;
2770
2771 if (!fence->submitted)
2772 return VK_TIMEOUT;
2773
2774 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
2775 if (!expired)
2776 return VK_TIMEOUT;
2777
2778 fence->signalled = true;
2779 }
2780
2781 return VK_SUCCESS;
2782 }
2783
2784 VkResult radv_ResetFences(VkDevice device,
2785 uint32_t fenceCount,
2786 const VkFence *pFences)
2787 {
2788 for (unsigned i = 0; i < fenceCount; ++i) {
2789 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2790 fence->submitted = fence->signalled = false;
2791 }
2792
2793 return VK_SUCCESS;
2794 }
2795
2796 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
2797 {
2798 RADV_FROM_HANDLE(radv_device, device, _device);
2799 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2800
2801 if (fence->signalled)
2802 return VK_SUCCESS;
2803 if (!fence->submitted)
2804 return VK_NOT_READY;
2805
2806 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
2807 return VK_NOT_READY;
2808
2809 return VK_SUCCESS;
2810 }
2811
2812
2813 // Queue semaphore functions
2814
2815 VkResult radv_CreateSemaphore(
2816 VkDevice _device,
2817 const VkSemaphoreCreateInfo* pCreateInfo,
2818 const VkAllocationCallbacks* pAllocator,
2819 VkSemaphore* pSemaphore)
2820 {
2821 RADV_FROM_HANDLE(radv_device, device, _device);
2822 const VkExportSemaphoreCreateInfoKHR *export =
2823 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
2824 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
2825 export ? export->handleTypes : 0;
2826
2827 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
2828 sizeof(*sem), 8,
2829 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2830 if (!sem)
2831 return VK_ERROR_OUT_OF_HOST_MEMORY;
2832
2833 sem->temp_syncobj = 0;
2834 /* create a syncobject if we are going to export this semaphore */
2835 if (handleTypes) {
2836 assert (device->physical_device->rad_info.has_syncobj);
2837 assert (handleTypes == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
2838 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
2839 if (ret) {
2840 vk_free2(&device->alloc, pAllocator, sem);
2841 return VK_ERROR_OUT_OF_HOST_MEMORY;
2842 }
2843 sem->sem = NULL;
2844 } else {
2845 sem->sem = device->ws->create_sem(device->ws);
2846 if (!sem->sem) {
2847 vk_free2(&device->alloc, pAllocator, sem);
2848 return VK_ERROR_OUT_OF_HOST_MEMORY;
2849 }
2850 sem->syncobj = 0;
2851 }
2852
2853 *pSemaphore = radv_semaphore_to_handle(sem);
2854 return VK_SUCCESS;
2855 }
2856
2857 void radv_DestroySemaphore(
2858 VkDevice _device,
2859 VkSemaphore _semaphore,
2860 const VkAllocationCallbacks* pAllocator)
2861 {
2862 RADV_FROM_HANDLE(radv_device, device, _device);
2863 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
2864 if (!_semaphore)
2865 return;
2866
2867 if (sem->syncobj)
2868 device->ws->destroy_syncobj(device->ws, sem->syncobj);
2869 else
2870 device->ws->destroy_sem(sem->sem);
2871 vk_free2(&device->alloc, pAllocator, sem);
2872 }
2873
2874 VkResult radv_CreateEvent(
2875 VkDevice _device,
2876 const VkEventCreateInfo* pCreateInfo,
2877 const VkAllocationCallbacks* pAllocator,
2878 VkEvent* pEvent)
2879 {
2880 RADV_FROM_HANDLE(radv_device, device, _device);
2881 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
2882 sizeof(*event), 8,
2883 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2884
2885 if (!event)
2886 return VK_ERROR_OUT_OF_HOST_MEMORY;
2887
2888 event->bo = device->ws->buffer_create(device->ws, 8, 8,
2889 RADEON_DOMAIN_GTT,
2890 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS);
2891 if (!event->bo) {
2892 vk_free2(&device->alloc, pAllocator, event);
2893 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2894 }
2895
2896 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
2897
2898 *pEvent = radv_event_to_handle(event);
2899
2900 return VK_SUCCESS;
2901 }
2902
2903 void radv_DestroyEvent(
2904 VkDevice _device,
2905 VkEvent _event,
2906 const VkAllocationCallbacks* pAllocator)
2907 {
2908 RADV_FROM_HANDLE(radv_device, device, _device);
2909 RADV_FROM_HANDLE(radv_event, event, _event);
2910
2911 if (!event)
2912 return;
2913 device->ws->buffer_destroy(event->bo);
2914 vk_free2(&device->alloc, pAllocator, event);
2915 }
2916
2917 VkResult radv_GetEventStatus(
2918 VkDevice _device,
2919 VkEvent _event)
2920 {
2921 RADV_FROM_HANDLE(radv_event, event, _event);
2922
2923 if (*event->map == 1)
2924 return VK_EVENT_SET;
2925 return VK_EVENT_RESET;
2926 }
2927
2928 VkResult radv_SetEvent(
2929 VkDevice _device,
2930 VkEvent _event)
2931 {
2932 RADV_FROM_HANDLE(radv_event, event, _event);
2933 *event->map = 1;
2934
2935 return VK_SUCCESS;
2936 }
2937
2938 VkResult radv_ResetEvent(
2939 VkDevice _device,
2940 VkEvent _event)
2941 {
2942 RADV_FROM_HANDLE(radv_event, event, _event);
2943 *event->map = 0;
2944
2945 return VK_SUCCESS;
2946 }
2947
2948 VkResult radv_CreateBuffer(
2949 VkDevice _device,
2950 const VkBufferCreateInfo* pCreateInfo,
2951 const VkAllocationCallbacks* pAllocator,
2952 VkBuffer* pBuffer)
2953 {
2954 RADV_FROM_HANDLE(radv_device, device, _device);
2955 struct radv_buffer *buffer;
2956
2957 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
2958
2959 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
2960 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2961 if (buffer == NULL)
2962 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2963
2964 buffer->size = pCreateInfo->size;
2965 buffer->usage = pCreateInfo->usage;
2966 buffer->bo = NULL;
2967 buffer->offset = 0;
2968 buffer->flags = pCreateInfo->flags;
2969
2970 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
2971 buffer->bo = device->ws->buffer_create(device->ws,
2972 align64(buffer->size, 4096),
2973 4096, 0, RADEON_FLAG_VIRTUAL);
2974 if (!buffer->bo) {
2975 vk_free2(&device->alloc, pAllocator, buffer);
2976 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2977 }
2978 }
2979
2980 *pBuffer = radv_buffer_to_handle(buffer);
2981
2982 return VK_SUCCESS;
2983 }
2984
2985 void radv_DestroyBuffer(
2986 VkDevice _device,
2987 VkBuffer _buffer,
2988 const VkAllocationCallbacks* pAllocator)
2989 {
2990 RADV_FROM_HANDLE(radv_device, device, _device);
2991 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2992
2993 if (!buffer)
2994 return;
2995
2996 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2997 device->ws->buffer_destroy(buffer->bo);
2998
2999 vk_free2(&device->alloc, pAllocator, buffer);
3000 }
3001
3002 static inline unsigned
3003 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
3004 {
3005 if (stencil)
3006 return image->surface.u.legacy.stencil_tiling_index[level];
3007 else
3008 return image->surface.u.legacy.tiling_index[level];
3009 }
3010
3011 static uint32_t radv_surface_layer_count(struct radv_image_view *iview)
3012 {
3013 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : iview->layer_count;
3014 }
3015
3016 static void
3017 radv_initialise_color_surface(struct radv_device *device,
3018 struct radv_color_buffer_info *cb,
3019 struct radv_image_view *iview)
3020 {
3021 const struct vk_format_description *desc;
3022 unsigned ntype, format, swap, endian;
3023 unsigned blend_clamp = 0, blend_bypass = 0;
3024 uint64_t va;
3025 const struct radeon_surf *surf = &iview->image->surface;
3026
3027 desc = vk_format_description(iview->vk_format);
3028
3029 memset(cb, 0, sizeof(*cb));
3030
3031 /* Intensity is implemented as Red, so treat it that way. */
3032 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
3033
3034 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3035
3036 cb->cb_color_base = va >> 8;
3037
3038 if (device->physical_device->rad_info.chip_class >= GFX9) {
3039 struct gfx9_surf_meta_flags meta;
3040 if (iview->image->dcc_offset)
3041 meta = iview->image->surface.u.gfx9.dcc;
3042 else
3043 meta = iview->image->surface.u.gfx9.cmask;
3044
3045 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3046 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
3047 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3048 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3049
3050 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
3051 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3052 } else {
3053 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
3054 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3055
3056 cb->cb_color_base += level_info->offset >> 8;
3057 if (level_info->mode == RADEON_SURF_MODE_2D)
3058 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3059
3060 pitch_tile_max = level_info->nblk_x / 8 - 1;
3061 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
3062 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
3063
3064 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3065 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3066 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
3067
3068 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3069 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
3070
3071 if (iview->image->fmask.size) {
3072 if (device->physical_device->rad_info.chip_class >= CIK)
3073 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
3074 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
3075 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
3076 } else {
3077 /* This must be set for fast clear to work without FMASK. */
3078 if (device->physical_device->rad_info.chip_class >= CIK)
3079 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3080 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3081 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3082 }
3083 }
3084
3085 /* CMASK variables */
3086 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3087 va += iview->image->cmask.offset;
3088 cb->cb_color_cmask = va >> 8;
3089
3090 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3091 va += iview->image->dcc_offset;
3092 cb->cb_dcc_base = va >> 8;
3093 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
3094
3095 uint32_t max_slice = radv_surface_layer_count(iview);
3096 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3097 S_028C6C_SLICE_MAX(iview->base_layer + max_slice - 1);
3098
3099 if (iview->image->info.samples > 1) {
3100 unsigned log_samples = util_logbase2(iview->image->info.samples);
3101
3102 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3103 S_028C74_NUM_FRAGMENTS(log_samples);
3104 }
3105
3106 if (iview->image->fmask.size) {
3107 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3108 cb->cb_color_fmask = va >> 8;
3109 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3110 } else {
3111 cb->cb_color_fmask = cb->cb_color_base;
3112 }
3113
3114 ntype = radv_translate_color_numformat(iview->vk_format,
3115 desc,
3116 vk_format_get_first_non_void_channel(iview->vk_format));
3117 format = radv_translate_colorformat(iview->vk_format);
3118 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3119 radv_finishme("Illegal color\n");
3120 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3121 endian = radv_colorformat_endian_swap(format);
3122
3123 /* blend clamp should be set for all NORM/SRGB types */
3124 if (ntype == V_028C70_NUMBER_UNORM ||
3125 ntype == V_028C70_NUMBER_SNORM ||
3126 ntype == V_028C70_NUMBER_SRGB)
3127 blend_clamp = 1;
3128
3129 /* set blend bypass according to docs if SINT/UINT or
3130 8/24 COLOR variants */
3131 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3132 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3133 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3134 blend_clamp = 0;
3135 blend_bypass = 1;
3136 }
3137 #if 0
3138 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3139 (format == V_028C70_COLOR_8 ||
3140 format == V_028C70_COLOR_8_8 ||
3141 format == V_028C70_COLOR_8_8_8_8))
3142 ->color_is_int8 = true;
3143 #endif
3144 cb->cb_color_info = S_028C70_FORMAT(format) |
3145 S_028C70_COMP_SWAP(swap) |
3146 S_028C70_BLEND_CLAMP(blend_clamp) |
3147 S_028C70_BLEND_BYPASS(blend_bypass) |
3148 S_028C70_SIMPLE_FLOAT(1) |
3149 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3150 ntype != V_028C70_NUMBER_SNORM &&
3151 ntype != V_028C70_NUMBER_SRGB &&
3152 format != V_028C70_COLOR_8_24 &&
3153 format != V_028C70_COLOR_24_8) |
3154 S_028C70_NUMBER_TYPE(ntype) |
3155 S_028C70_ENDIAN(endian);
3156 if ((iview->image->info.samples > 1) && iview->image->fmask.size) {
3157 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3158 if (device->physical_device->rad_info.chip_class == SI) {
3159 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3160 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3161 }
3162 }
3163
3164 if (iview->image->cmask.size &&
3165 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3166 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3167
3168 if (radv_vi_dcc_enabled(iview->image, iview->base_mip))
3169 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3170
3171 if (device->physical_device->rad_info.chip_class >= VI) {
3172 unsigned max_uncompressed_block_size = 2;
3173 if (iview->image->info.samples > 1) {
3174 if (iview->image->surface.bpe == 1)
3175 max_uncompressed_block_size = 0;
3176 else if (iview->image->surface.bpe == 2)
3177 max_uncompressed_block_size = 1;
3178 }
3179
3180 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3181 S_028C78_INDEPENDENT_64B_BLOCKS(1);
3182 }
3183
3184 /* This must be set for fast clear to work without FMASK. */
3185 if (!iview->image->fmask.size &&
3186 device->physical_device->rad_info.chip_class == SI) {
3187 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3188 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3189 }
3190
3191 if (device->physical_device->rad_info.chip_class >= GFX9) {
3192 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
3193 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
3194
3195 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3196 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3197 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3198 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
3199 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
3200 S_028C68_MAX_MIP(iview->image->info.levels - 1);
3201
3202 cb->gfx9_epitch = S_0287A0_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3203
3204 }
3205 }
3206
3207 static void
3208 radv_initialise_ds_surface(struct radv_device *device,
3209 struct radv_ds_buffer_info *ds,
3210 struct radv_image_view *iview)
3211 {
3212 unsigned level = iview->base_mip;
3213 unsigned format, stencil_format;
3214 uint64_t va, s_offs, z_offs;
3215 bool stencil_only = false;
3216 memset(ds, 0, sizeof(*ds));
3217 switch (iview->image->vk_format) {
3218 case VK_FORMAT_D24_UNORM_S8_UINT:
3219 case VK_FORMAT_X8_D24_UNORM_PACK32:
3220 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3221 ds->offset_scale = 2.0f;
3222 break;
3223 case VK_FORMAT_D16_UNORM:
3224 case VK_FORMAT_D16_UNORM_S8_UINT:
3225 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3226 ds->offset_scale = 4.0f;
3227 break;
3228 case VK_FORMAT_D32_SFLOAT:
3229 case VK_FORMAT_D32_SFLOAT_S8_UINT:
3230 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3231 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3232 ds->offset_scale = 1.0f;
3233 break;
3234 case VK_FORMAT_S8_UINT:
3235 stencil_only = true;
3236 break;
3237 default:
3238 break;
3239 }
3240
3241 format = radv_translate_dbformat(iview->image->vk_format);
3242 stencil_format = iview->image->surface.has_stencil ?
3243 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
3244
3245 uint32_t max_slice = radv_surface_layer_count(iview);
3246 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
3247 S_028008_SLICE_MAX(iview->base_layer + max_slice - 1);
3248
3249 ds->db_htile_data_base = 0;
3250 ds->db_htile_surface = 0;
3251
3252 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3253 s_offs = z_offs = va;
3254
3255 if (device->physical_device->rad_info.chip_class >= GFX9) {
3256 assert(iview->image->surface.u.gfx9.surf_offset == 0);
3257 s_offs += iview->image->surface.u.gfx9.stencil_offset;
3258
3259 ds->db_z_info = S_028038_FORMAT(format) |
3260 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
3261 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3262 S_028038_MAXMIP(iview->image->info.levels - 1);
3263 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
3264 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
3265
3266 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3267 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
3268 ds->db_depth_view |= S_028008_MIPID(level);
3269
3270 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
3271 S_02801C_Y_MAX(iview->image->info.height - 1);
3272
3273 if (radv_htile_enabled(iview->image, level)) {
3274 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
3275
3276 if (iview->image->tc_compatible_htile) {
3277 unsigned max_zplanes = 4;
3278
3279 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
3280 iview->image->info.samples > 1)
3281 max_zplanes = 2;
3282
3283 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
3284 S_028038_ITERATE_FLUSH(1);
3285 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
3286 }
3287
3288 if (!iview->image->surface.has_stencil)
3289 /* Use all of the htile_buffer for depth if there's no stencil. */
3290 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
3291 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3292 iview->image->htile_offset;
3293 ds->db_htile_data_base = va >> 8;
3294 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
3295 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
3296 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
3297 }
3298 } else {
3299 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
3300
3301 if (stencil_only)
3302 level_info = &iview->image->surface.u.legacy.stencil_level[level];
3303
3304 z_offs += iview->image->surface.u.legacy.level[level].offset;
3305 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
3306
3307 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!iview->image->tc_compatible_htile);
3308 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
3309 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
3310
3311 if (iview->image->info.samples > 1)
3312 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
3313
3314 if (device->physical_device->rad_info.chip_class >= CIK) {
3315 struct radeon_info *info = &device->physical_device->rad_info;
3316 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
3317 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
3318 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
3319 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
3320 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
3321 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
3322
3323 if (stencil_only)
3324 tile_mode = stencil_tile_mode;
3325
3326 ds->db_depth_info |=
3327 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
3328 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
3329 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
3330 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
3331 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
3332 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
3333 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
3334 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
3335 } else {
3336 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
3337 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3338 tile_mode_index = si_tile_mode_index(iview->image, level, true);
3339 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
3340 if (stencil_only)
3341 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3342 }
3343
3344 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
3345 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
3346 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
3347
3348 if (radv_htile_enabled(iview->image, level)) {
3349 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
3350
3351 if (!iview->image->surface.has_stencil &&
3352 !iview->image->tc_compatible_htile)
3353 /* Use all of the htile_buffer for depth if there's no stencil. */
3354 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
3355
3356 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3357 iview->image->htile_offset;
3358 ds->db_htile_data_base = va >> 8;
3359 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
3360
3361 if (iview->image->tc_compatible_htile) {
3362 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
3363
3364 if (iview->image->info.samples <= 1)
3365 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
3366 else if (iview->image->info.samples <= 4)
3367 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
3368 else
3369 ds->db_z_info|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
3370 }
3371 }
3372 }
3373
3374 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
3375 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
3376 }
3377
3378 VkResult radv_CreateFramebuffer(
3379 VkDevice _device,
3380 const VkFramebufferCreateInfo* pCreateInfo,
3381 const VkAllocationCallbacks* pAllocator,
3382 VkFramebuffer* pFramebuffer)
3383 {
3384 RADV_FROM_HANDLE(radv_device, device, _device);
3385 struct radv_framebuffer *framebuffer;
3386
3387 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
3388
3389 size_t size = sizeof(*framebuffer) +
3390 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
3391 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
3392 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3393 if (framebuffer == NULL)
3394 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3395
3396 framebuffer->attachment_count = pCreateInfo->attachmentCount;
3397 framebuffer->width = pCreateInfo->width;
3398 framebuffer->height = pCreateInfo->height;
3399 framebuffer->layers = pCreateInfo->layers;
3400 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
3401 VkImageView _iview = pCreateInfo->pAttachments[i];
3402 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
3403 framebuffer->attachments[i].attachment = iview;
3404 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
3405 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
3406 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3407 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
3408 }
3409 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
3410 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
3411 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_layer_count(iview));
3412 }
3413
3414 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
3415 return VK_SUCCESS;
3416 }
3417
3418 void radv_DestroyFramebuffer(
3419 VkDevice _device,
3420 VkFramebuffer _fb,
3421 const VkAllocationCallbacks* pAllocator)
3422 {
3423 RADV_FROM_HANDLE(radv_device, device, _device);
3424 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
3425
3426 if (!fb)
3427 return;
3428 vk_free2(&device->alloc, pAllocator, fb);
3429 }
3430
3431 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
3432 {
3433 switch (address_mode) {
3434 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
3435 return V_008F30_SQ_TEX_WRAP;
3436 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
3437 return V_008F30_SQ_TEX_MIRROR;
3438 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
3439 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
3440 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
3441 return V_008F30_SQ_TEX_CLAMP_BORDER;
3442 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
3443 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
3444 default:
3445 unreachable("illegal tex wrap mode");
3446 break;
3447 }
3448 }
3449
3450 static unsigned
3451 radv_tex_compare(VkCompareOp op)
3452 {
3453 switch (op) {
3454 case VK_COMPARE_OP_NEVER:
3455 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
3456 case VK_COMPARE_OP_LESS:
3457 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
3458 case VK_COMPARE_OP_EQUAL:
3459 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
3460 case VK_COMPARE_OP_LESS_OR_EQUAL:
3461 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
3462 case VK_COMPARE_OP_GREATER:
3463 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
3464 case VK_COMPARE_OP_NOT_EQUAL:
3465 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
3466 case VK_COMPARE_OP_GREATER_OR_EQUAL:
3467 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
3468 case VK_COMPARE_OP_ALWAYS:
3469 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
3470 default:
3471 unreachable("illegal compare mode");
3472 break;
3473 }
3474 }
3475
3476 static unsigned
3477 radv_tex_filter(VkFilter filter, unsigned max_ansio)
3478 {
3479 switch (filter) {
3480 case VK_FILTER_NEAREST:
3481 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
3482 V_008F38_SQ_TEX_XY_FILTER_POINT);
3483 case VK_FILTER_LINEAR:
3484 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
3485 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
3486 case VK_FILTER_CUBIC_IMG:
3487 default:
3488 fprintf(stderr, "illegal texture filter");
3489 return 0;
3490 }
3491 }
3492
3493 static unsigned
3494 radv_tex_mipfilter(VkSamplerMipmapMode mode)
3495 {
3496 switch (mode) {
3497 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
3498 return V_008F38_SQ_TEX_Z_FILTER_POINT;
3499 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
3500 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
3501 default:
3502 return V_008F38_SQ_TEX_Z_FILTER_NONE;
3503 }
3504 }
3505
3506 static unsigned
3507 radv_tex_bordercolor(VkBorderColor bcolor)
3508 {
3509 switch (bcolor) {
3510 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
3511 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
3512 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3513 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
3514 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
3515 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3516 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
3517 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
3518 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3519 default:
3520 break;
3521 }
3522 return 0;
3523 }
3524
3525 static unsigned
3526 radv_tex_aniso_filter(unsigned filter)
3527 {
3528 if (filter < 2)
3529 return 0;
3530 if (filter < 4)
3531 return 1;
3532 if (filter < 8)
3533 return 2;
3534 if (filter < 16)
3535 return 3;
3536 return 4;
3537 }
3538
3539 static void
3540 radv_init_sampler(struct radv_device *device,
3541 struct radv_sampler *sampler,
3542 const VkSamplerCreateInfo *pCreateInfo)
3543 {
3544 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
3545 (uint32_t) pCreateInfo->maxAnisotropy : 0;
3546 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
3547 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
3548
3549 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
3550 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
3551 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
3552 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3553 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
3554 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
3555 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3556 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3557 S_008F30_DISABLE_CUBE_WRAP(0) |
3558 S_008F30_COMPAT_MODE(is_vi));
3559 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
3560 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
3561 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3562 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
3563 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
3564 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
3565 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
3566 S_008F38_MIP_POINT_PRECLAMP(0) |
3567 S_008F38_DISABLE_LSB_CEIL(1) |
3568 S_008F38_FILTER_PREC_FIX(1) |
3569 S_008F38_ANISO_OVERRIDE(is_vi));
3570 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3571 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
3572 }
3573
3574 VkResult radv_CreateSampler(
3575 VkDevice _device,
3576 const VkSamplerCreateInfo* pCreateInfo,
3577 const VkAllocationCallbacks* pAllocator,
3578 VkSampler* pSampler)
3579 {
3580 RADV_FROM_HANDLE(radv_device, device, _device);
3581 struct radv_sampler *sampler;
3582
3583 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
3584
3585 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
3586 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3587 if (!sampler)
3588 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3589
3590 radv_init_sampler(device, sampler, pCreateInfo);
3591 *pSampler = radv_sampler_to_handle(sampler);
3592
3593 return VK_SUCCESS;
3594 }
3595
3596 void radv_DestroySampler(
3597 VkDevice _device,
3598 VkSampler _sampler,
3599 const VkAllocationCallbacks* pAllocator)
3600 {
3601 RADV_FROM_HANDLE(radv_device, device, _device);
3602 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
3603
3604 if (!sampler)
3605 return;
3606 vk_free2(&device->alloc, pAllocator, sampler);
3607 }
3608
3609 /* vk_icd.h does not declare this function, so we declare it here to
3610 * suppress Wmissing-prototypes.
3611 */
3612 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3613 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
3614
3615 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3616 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
3617 {
3618 /* For the full details on loader interface versioning, see
3619 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3620 * What follows is a condensed summary, to help you navigate the large and
3621 * confusing official doc.
3622 *
3623 * - Loader interface v0 is incompatible with later versions. We don't
3624 * support it.
3625 *
3626 * - In loader interface v1:
3627 * - The first ICD entrypoint called by the loader is
3628 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3629 * entrypoint.
3630 * - The ICD must statically expose no other Vulkan symbol unless it is
3631 * linked with -Bsymbolic.
3632 * - Each dispatchable Vulkan handle created by the ICD must be
3633 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3634 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3635 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3636 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3637 * such loader-managed surfaces.
3638 *
3639 * - Loader interface v2 differs from v1 in:
3640 * - The first ICD entrypoint called by the loader is
3641 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3642 * statically expose this entrypoint.
3643 *
3644 * - Loader interface v3 differs from v2 in:
3645 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3646 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3647 * because the loader no longer does so.
3648 */
3649 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
3650 return VK_SUCCESS;
3651 }
3652
3653 VkResult radv_GetMemoryFdKHR(VkDevice _device,
3654 const VkMemoryGetFdInfoKHR *pGetFdInfo,
3655 int *pFD)
3656 {
3657 RADV_FROM_HANDLE(radv_device, device, _device);
3658 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
3659
3660 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
3661
3662 /* We support only one handle type. */
3663 assert(pGetFdInfo->handleType ==
3664 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3665
3666 bool ret = radv_get_memory_fd(device, memory, pFD);
3667 if (ret == false)
3668 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
3669 return VK_SUCCESS;
3670 }
3671
3672 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
3673 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
3674 int fd,
3675 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
3676 {
3677 /* The valid usage section for this function says:
3678 *
3679 * "handleType must not be one of the handle types defined as opaque."
3680 *
3681 * Since we only handle opaque handles for now, there are no FD properties.
3682 */
3683 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
3684 }
3685
3686 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
3687 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
3688 {
3689 RADV_FROM_HANDLE(radv_device, device, _device);
3690 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
3691 uint32_t syncobj_handle = 0;
3692 assert(pImportSemaphoreFdInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3693
3694 int ret = device->ws->import_syncobj(device->ws, pImportSemaphoreFdInfo->fd, &syncobj_handle);
3695 if (ret != 0)
3696 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
3697
3698 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
3699 sem->temp_syncobj = syncobj_handle;
3700 } else {
3701 sem->syncobj = syncobj_handle;
3702 }
3703 close(pImportSemaphoreFdInfo->fd);
3704 return VK_SUCCESS;
3705 }
3706
3707 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
3708 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
3709 int *pFd)
3710 {
3711 RADV_FROM_HANDLE(radv_device, device, _device);
3712 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
3713 int ret;
3714 uint32_t syncobj_handle;
3715
3716 assert(pGetFdInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3717 if (sem->temp_syncobj)
3718 syncobj_handle = sem->temp_syncobj;
3719 else
3720 syncobj_handle = sem->syncobj;
3721 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
3722 if (ret)
3723 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3724 return VK_SUCCESS;
3725 }
3726
3727 void radv_GetPhysicalDeviceExternalSemaphorePropertiesKHR(
3728 VkPhysicalDevice physicalDevice,
3729 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
3730 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
3731 {
3732 if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
3733 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3734 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3735 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
3736 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
3737 } else {
3738 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
3739 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
3740 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
3741 }
3742 }