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2ce0c9dbd0fcc14b6776659d51fb74625aa80f5d
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "gfx9d.h"
47 #include "addrlib/gfx9/chip/gfx9_enum.h"
48 #include "util/debug.h"
49
50 static int
51 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
52 {
53 uint32_t mesa_timestamp, llvm_timestamp;
54 uint16_t f = family;
55 memset(uuid, 0, VK_UUID_SIZE);
56 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
57 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
58 return -1;
59
60 memcpy(uuid, &mesa_timestamp, 4);
61 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
62 memcpy((char*)uuid + 8, &f, 2);
63 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
64 return 0;
65 }
66
67 static void
68 radv_get_driver_uuid(void *uuid)
69 {
70 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
71 }
72
73 static void
74 radv_get_device_uuid(struct radeon_info *info, void *uuid)
75 {
76 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
77 }
78
79 static void
80 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
81 {
82 const char *chip_string;
83 char llvm_string[32] = {};
84
85 switch (family) {
86 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
87 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
88 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
89 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
90 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
91 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
92 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
93 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
94 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
95 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
96 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
97 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
98 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
99 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
100 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
101 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
102 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
103 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
104 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
105 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
106 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
107 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
108 default: chip_string = "AMD RADV unknown"; break;
109 }
110
111 if (HAVE_LLVM > 0) {
112 snprintf(llvm_string, sizeof(llvm_string),
113 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
114 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
115 }
116
117 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
118 }
119
120 static void
121 radv_physical_device_init_mem_types(struct radv_physical_device *device)
122 {
123 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
124 uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
125 device->rad_info.vram_vis_size);
126
127 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
128 device->memory_properties.memoryHeapCount = 0;
129 if (device->rad_info.vram_size - visible_vram_size > 0) {
130 vram_index = device->memory_properties.memoryHeapCount++;
131 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
132 .size = device->rad_info.vram_size - visible_vram_size,
133 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
134 };
135 }
136 if (visible_vram_size) {
137 visible_vram_index = device->memory_properties.memoryHeapCount++;
138 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
139 .size = visible_vram_size,
140 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
141 };
142 }
143 if (device->rad_info.gart_size > 0) {
144 gart_index = device->memory_properties.memoryHeapCount++;
145 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
146 .size = device->rad_info.gart_size,
147 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
148 };
149 }
150
151 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
152 unsigned type_count = 0;
153 if (vram_index >= 0) {
154 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
155 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
156 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
157 .heapIndex = vram_index,
158 };
159 }
160 if (gart_index >= 0) {
161 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
162 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
163 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
164 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
165 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
166 .heapIndex = gart_index,
167 };
168 }
169 if (visible_vram_index >= 0) {
170 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
171 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
172 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
173 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
174 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
175 .heapIndex = visible_vram_index,
176 };
177 }
178 if (gart_index >= 0) {
179 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
180 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
181 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
182 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
183 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
184 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
185 .heapIndex = gart_index,
186 };
187 }
188 device->memory_properties.memoryTypeCount = type_count;
189 }
190
191 static void
192 radv_handle_env_var_force_family(struct radv_physical_device *device)
193 {
194 const char *family = getenv("RADV_FORCE_FAMILY");
195 unsigned i;
196
197 if (!family)
198 return;
199
200 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
201 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
202 /* Override family and chip_class. */
203 device->rad_info.family = i;
204
205 if (i >= CHIP_VEGA10)
206 device->rad_info.chip_class = GFX9;
207 else if (i >= CHIP_TONGA)
208 device->rad_info.chip_class = VI;
209 else if (i >= CHIP_BONAIRE)
210 device->rad_info.chip_class = CIK;
211 else
212 device->rad_info.chip_class = SI;
213
214 return;
215 }
216 }
217
218 fprintf(stderr, "radv: Unknown family: %s\n", family);
219 exit(1);
220 }
221
222 static VkResult
223 radv_physical_device_init(struct radv_physical_device *device,
224 struct radv_instance *instance,
225 drmDevicePtr drm_device)
226 {
227 const char *path = drm_device->nodes[DRM_NODE_RENDER];
228 VkResult result;
229 drmVersionPtr version;
230 int fd;
231
232 fd = open(path, O_RDWR | O_CLOEXEC);
233 if (fd < 0)
234 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
235
236 version = drmGetVersion(fd);
237 if (!version) {
238 close(fd);
239 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
240 "failed to get version %s: %m", path);
241 }
242
243 if (strcmp(version->name, "amdgpu")) {
244 drmFreeVersion(version);
245 close(fd);
246 return VK_ERROR_INCOMPATIBLE_DRIVER;
247 }
248 drmFreeVersion(version);
249
250 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
251 device->instance = instance;
252 assert(strlen(path) < ARRAY_SIZE(device->path));
253 strncpy(device->path, path, ARRAY_SIZE(device->path));
254
255 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
256 instance->perftest_flags);
257 if (!device->ws) {
258 result = VK_ERROR_INCOMPATIBLE_DRIVER;
259 goto fail;
260 }
261
262 device->local_fd = fd;
263 device->ws->query_info(device->ws, &device->rad_info);
264
265 radv_handle_env_var_force_family(device);
266
267 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
268
269 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
270 device->ws->destroy(device->ws);
271 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
272 "cannot generate UUID");
273 goto fail;
274 }
275
276 /* These flags affect shader compilation. */
277 uint64_t shader_env_flags =
278 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
279 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
280
281 /* The gpu id is already embedded in the uuid so we just pass "radv"
282 * when creating the cache.
283 */
284 char buf[VK_UUID_SIZE * 2 + 1];
285 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
286 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
287
288 if (device->rad_info.chip_class < VI ||
289 device->rad_info.chip_class > GFX9)
290 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
291
292 radv_get_driver_uuid(&device->device_uuid);
293 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
294
295 if (device->rad_info.family == CHIP_STONEY ||
296 device->rad_info.chip_class >= GFX9) {
297 device->has_rbplus = true;
298 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
299 device->rad_info.family == CHIP_VEGA12 ||
300 device->rad_info.family == CHIP_RAVEN;
301 }
302
303 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
304 * on SI.
305 */
306 device->has_clear_state = device->rad_info.chip_class >= CIK;
307
308 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
309
310 /* Vega10/Raven need a special workaround for a hardware bug. */
311 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
312 device->rad_info.family == CHIP_RAVEN;
313
314 /* Out-of-order primitive rasterization. */
315 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
316 device->rad_info.max_se >= 2;
317 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
318 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
319
320 device->dcc_msaa_allowed = device->rad_info.chip_class == VI &&
321 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
322
323 radv_physical_device_init_mem_types(device);
324 radv_fill_device_extension_table(device, &device->supported_extensions);
325
326 result = radv_init_wsi(device);
327 if (result != VK_SUCCESS) {
328 device->ws->destroy(device->ws);
329 goto fail;
330 }
331
332 return VK_SUCCESS;
333
334 fail:
335 close(fd);
336 return result;
337 }
338
339 static void
340 radv_physical_device_finish(struct radv_physical_device *device)
341 {
342 radv_finish_wsi(device);
343 device->ws->destroy(device->ws);
344 disk_cache_destroy(device->disk_cache);
345 close(device->local_fd);
346 }
347
348 static void *
349 default_alloc_func(void *pUserData, size_t size, size_t align,
350 VkSystemAllocationScope allocationScope)
351 {
352 return malloc(size);
353 }
354
355 static void *
356 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
357 size_t align, VkSystemAllocationScope allocationScope)
358 {
359 return realloc(pOriginal, size);
360 }
361
362 static void
363 default_free_func(void *pUserData, void *pMemory)
364 {
365 free(pMemory);
366 }
367
368 static const VkAllocationCallbacks default_alloc = {
369 .pUserData = NULL,
370 .pfnAllocation = default_alloc_func,
371 .pfnReallocation = default_realloc_func,
372 .pfnFree = default_free_func,
373 };
374
375 static const struct debug_control radv_debug_options[] = {
376 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
377 {"nodcc", RADV_DEBUG_NO_DCC},
378 {"shaders", RADV_DEBUG_DUMP_SHADERS},
379 {"nocache", RADV_DEBUG_NO_CACHE},
380 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
381 {"nohiz", RADV_DEBUG_NO_HIZ},
382 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
383 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
384 {"allbos", RADV_DEBUG_ALL_BOS},
385 {"noibs", RADV_DEBUG_NO_IBS},
386 {"spirv", RADV_DEBUG_DUMP_SPIRV},
387 {"vmfaults", RADV_DEBUG_VM_FAULTS},
388 {"zerovram", RADV_DEBUG_ZERO_VRAM},
389 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
390 {"nosisched", RADV_DEBUG_NO_SISCHED},
391 {"preoptir", RADV_DEBUG_PREOPTIR},
392 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
393 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
394 {NULL, 0}
395 };
396
397 const char *
398 radv_get_debug_option_name(int id)
399 {
400 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
401 return radv_debug_options[id].string;
402 }
403
404 static const struct debug_control radv_perftest_options[] = {
405 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
406 {"sisched", RADV_PERFTEST_SISCHED},
407 {"localbos", RADV_PERFTEST_LOCAL_BOS},
408 {"binning", RADV_PERFTEST_BINNING},
409 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
410 {NULL, 0}
411 };
412
413 const char *
414 radv_get_perftest_option_name(int id)
415 {
416 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
417 return radv_perftest_options[id].string;
418 }
419
420 static void
421 radv_handle_per_app_options(struct radv_instance *instance,
422 const VkApplicationInfo *info)
423 {
424 const char *name = info ? info->pApplicationName : NULL;
425
426 if (!name)
427 return;
428
429 if (!strcmp(name, "Talos - Linux - 32bit") ||
430 !strcmp(name, "Talos - Linux - 64bit")) {
431 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
432 /* Force enable LLVM sisched for Talos because it looks
433 * safe and it gives few more FPS.
434 */
435 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
436 }
437 }
438 }
439
440 static int radv_get_instance_extension_index(const char *name)
441 {
442 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
443 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
444 return i;
445 }
446 return -1;
447 }
448
449
450 VkResult radv_CreateInstance(
451 const VkInstanceCreateInfo* pCreateInfo,
452 const VkAllocationCallbacks* pAllocator,
453 VkInstance* pInstance)
454 {
455 struct radv_instance *instance;
456 VkResult result;
457
458 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
459
460 uint32_t client_version;
461 if (pCreateInfo->pApplicationInfo &&
462 pCreateInfo->pApplicationInfo->apiVersion != 0) {
463 client_version = pCreateInfo->pApplicationInfo->apiVersion;
464 } else {
465 radv_EnumerateInstanceVersion(&client_version);
466 }
467
468 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
469 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
470 if (!instance)
471 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
472
473 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
474
475 if (pAllocator)
476 instance->alloc = *pAllocator;
477 else
478 instance->alloc = default_alloc;
479
480 instance->apiVersion = client_version;
481 instance->physicalDeviceCount = -1;
482
483 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
484 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
485 int index = radv_get_instance_extension_index(ext_name);
486
487 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
488 vk_free2(&default_alloc, pAllocator, instance);
489 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
490 }
491
492 instance->enabled_extensions.extensions[index] = true;
493 }
494
495 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
496 if (result != VK_SUCCESS) {
497 vk_free2(&default_alloc, pAllocator, instance);
498 return vk_error(result);
499 }
500
501 _mesa_locale_init();
502
503 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
504
505 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
506 radv_debug_options);
507
508 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
509 radv_perftest_options);
510
511 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
512
513 *pInstance = radv_instance_to_handle(instance);
514
515 return VK_SUCCESS;
516 }
517
518 void radv_DestroyInstance(
519 VkInstance _instance,
520 const VkAllocationCallbacks* pAllocator)
521 {
522 RADV_FROM_HANDLE(radv_instance, instance, _instance);
523
524 if (!instance)
525 return;
526
527 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
528 radv_physical_device_finish(instance->physicalDevices + i);
529 }
530
531 VG(VALGRIND_DESTROY_MEMPOOL(instance));
532
533 _mesa_locale_fini();
534
535 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
536
537 vk_free(&instance->alloc, instance);
538 }
539
540 static VkResult
541 radv_enumerate_devices(struct radv_instance *instance)
542 {
543 /* TODO: Check for more devices ? */
544 drmDevicePtr devices[8];
545 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
546 int max_devices;
547
548 instance->physicalDeviceCount = 0;
549
550 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
551 if (max_devices < 1)
552 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
553
554 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
555 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
556 devices[i]->bustype == DRM_BUS_PCI &&
557 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
558
559 result = radv_physical_device_init(instance->physicalDevices +
560 instance->physicalDeviceCount,
561 instance,
562 devices[i]);
563 if (result == VK_SUCCESS)
564 ++instance->physicalDeviceCount;
565 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
566 break;
567 }
568 }
569 drmFreeDevices(devices, max_devices);
570
571 return result;
572 }
573
574 VkResult radv_EnumeratePhysicalDevices(
575 VkInstance _instance,
576 uint32_t* pPhysicalDeviceCount,
577 VkPhysicalDevice* pPhysicalDevices)
578 {
579 RADV_FROM_HANDLE(radv_instance, instance, _instance);
580 VkResult result;
581
582 if (instance->physicalDeviceCount < 0) {
583 result = radv_enumerate_devices(instance);
584 if (result != VK_SUCCESS &&
585 result != VK_ERROR_INCOMPATIBLE_DRIVER)
586 return result;
587 }
588
589 if (!pPhysicalDevices) {
590 *pPhysicalDeviceCount = instance->physicalDeviceCount;
591 } else {
592 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
593 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
594 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
595 }
596
597 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
598 : VK_SUCCESS;
599 }
600
601 VkResult radv_EnumeratePhysicalDeviceGroups(
602 VkInstance _instance,
603 uint32_t* pPhysicalDeviceGroupCount,
604 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
605 {
606 RADV_FROM_HANDLE(radv_instance, instance, _instance);
607 VkResult result;
608
609 if (instance->physicalDeviceCount < 0) {
610 result = radv_enumerate_devices(instance);
611 if (result != VK_SUCCESS &&
612 result != VK_ERROR_INCOMPATIBLE_DRIVER)
613 return result;
614 }
615
616 if (!pPhysicalDeviceGroupProperties) {
617 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
618 } else {
619 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
620 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
621 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
622 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
623 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
624 }
625 }
626 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
627 : VK_SUCCESS;
628 }
629
630 void radv_GetPhysicalDeviceFeatures(
631 VkPhysicalDevice physicalDevice,
632 VkPhysicalDeviceFeatures* pFeatures)
633 {
634 memset(pFeatures, 0, sizeof(*pFeatures));
635
636 *pFeatures = (VkPhysicalDeviceFeatures) {
637 .robustBufferAccess = true,
638 .fullDrawIndexUint32 = true,
639 .imageCubeArray = true,
640 .independentBlend = true,
641 .geometryShader = true,
642 .tessellationShader = true,
643 .sampleRateShading = true,
644 .dualSrcBlend = true,
645 .logicOp = true,
646 .multiDrawIndirect = true,
647 .drawIndirectFirstInstance = true,
648 .depthClamp = true,
649 .depthBiasClamp = true,
650 .fillModeNonSolid = true,
651 .depthBounds = true,
652 .wideLines = true,
653 .largePoints = true,
654 .alphaToOne = true,
655 .multiViewport = true,
656 .samplerAnisotropy = true,
657 .textureCompressionETC2 = false,
658 .textureCompressionASTC_LDR = false,
659 .textureCompressionBC = true,
660 .occlusionQueryPrecise = true,
661 .pipelineStatisticsQuery = true,
662 .vertexPipelineStoresAndAtomics = true,
663 .fragmentStoresAndAtomics = true,
664 .shaderTessellationAndGeometryPointSize = true,
665 .shaderImageGatherExtended = true,
666 .shaderStorageImageExtendedFormats = true,
667 .shaderStorageImageMultisample = false,
668 .shaderUniformBufferArrayDynamicIndexing = true,
669 .shaderSampledImageArrayDynamicIndexing = true,
670 .shaderStorageBufferArrayDynamicIndexing = true,
671 .shaderStorageImageArrayDynamicIndexing = true,
672 .shaderStorageImageReadWithoutFormat = true,
673 .shaderStorageImageWriteWithoutFormat = true,
674 .shaderClipDistance = true,
675 .shaderCullDistance = true,
676 .shaderFloat64 = true,
677 .shaderInt64 = true,
678 .shaderInt16 = false,
679 .sparseBinding = true,
680 .variableMultisampleRate = true,
681 .inheritedQueries = true,
682 };
683 }
684
685 void radv_GetPhysicalDeviceFeatures2(
686 VkPhysicalDevice physicalDevice,
687 VkPhysicalDeviceFeatures2KHR *pFeatures)
688 {
689 vk_foreach_struct(ext, pFeatures->pNext) {
690 switch (ext->sType) {
691 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
692 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
693 features->variablePointersStorageBuffer = true;
694 features->variablePointers = false;
695 break;
696 }
697 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHR: {
698 VkPhysicalDeviceMultiviewFeaturesKHR *features = (VkPhysicalDeviceMultiviewFeaturesKHR*)ext;
699 features->multiview = true;
700 features->multiviewGeometryShader = true;
701 features->multiviewTessellationShader = true;
702 break;
703 }
704 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
705 VkPhysicalDeviceShaderDrawParameterFeatures *features =
706 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
707 features->shaderDrawParameters = true;
708 break;
709 }
710 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
711 VkPhysicalDeviceProtectedMemoryFeatures *features =
712 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
713 features->protectedMemory = false;
714 break;
715 }
716 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
717 VkPhysicalDevice16BitStorageFeatures *features =
718 (VkPhysicalDevice16BitStorageFeatures*)ext;
719 features->storageBuffer16BitAccess = false;
720 features->uniformAndStorageBuffer16BitAccess = false;
721 features->storagePushConstant16 = false;
722 features->storageInputOutput16 = false;
723 break;
724 }
725 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
726 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
727 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
728 features->samplerYcbcrConversion = false;
729 break;
730 }
731 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
732 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
733 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)features;
734 features->shaderInputAttachmentArrayDynamicIndexing = true;
735 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
736 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
737 features->shaderUniformBufferArrayNonUniformIndexing = false;
738 features->shaderSampledImageArrayNonUniformIndexing = false;
739 features->shaderStorageBufferArrayNonUniformIndexing = false;
740 features->shaderStorageImageArrayNonUniformIndexing = false;
741 features->shaderInputAttachmentArrayNonUniformIndexing = false;
742 features->shaderUniformTexelBufferArrayNonUniformIndexing = false;
743 features->shaderStorageTexelBufferArrayNonUniformIndexing = false;
744 features->descriptorBindingUniformBufferUpdateAfterBind = true;
745 features->descriptorBindingSampledImageUpdateAfterBind = true;
746 features->descriptorBindingStorageImageUpdateAfterBind = true;
747 features->descriptorBindingStorageBufferUpdateAfterBind = true;
748 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
749 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
750 features->descriptorBindingUpdateUnusedWhilePending = true;
751 features->descriptorBindingPartiallyBound = true;
752 features->descriptorBindingVariableDescriptorCount = true;
753 features->runtimeDescriptorArray = true;
754 break;
755 }
756 default:
757 break;
758 }
759 }
760 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
761 }
762
763 void radv_GetPhysicalDeviceProperties(
764 VkPhysicalDevice physicalDevice,
765 VkPhysicalDeviceProperties* pProperties)
766 {
767 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
768 VkSampleCountFlags sample_counts = 0xf;
769
770 /* make sure that the entire descriptor set is addressable with a signed
771 * 32-bit int. So the sum of all limits scaled by descriptor size has to
772 * be at most 2 GiB. the combined image & samples object count as one of
773 * both. This limit is for the pipeline layout, not for the set layout, but
774 * there is no set limit, so we just set a pipeline limit. I don't think
775 * any app is going to hit this soon. */
776 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
777 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
778 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
779 32 /* sampler, largest when combined with image */ +
780 64 /* sampled image */ +
781 64 /* storage image */);
782
783 VkPhysicalDeviceLimits limits = {
784 .maxImageDimension1D = (1 << 14),
785 .maxImageDimension2D = (1 << 14),
786 .maxImageDimension3D = (1 << 11),
787 .maxImageDimensionCube = (1 << 14),
788 .maxImageArrayLayers = (1 << 11),
789 .maxTexelBufferElements = 128 * 1024 * 1024,
790 .maxUniformBufferRange = UINT32_MAX,
791 .maxStorageBufferRange = UINT32_MAX,
792 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
793 .maxMemoryAllocationCount = UINT32_MAX,
794 .maxSamplerAllocationCount = 64 * 1024,
795 .bufferImageGranularity = 64, /* A cache line */
796 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
797 .maxBoundDescriptorSets = MAX_SETS,
798 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
799 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
800 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
801 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
802 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
803 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
804 .maxPerStageResources = max_descriptor_set_size,
805 .maxDescriptorSetSamplers = max_descriptor_set_size,
806 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
807 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
808 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
809 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
810 .maxDescriptorSetSampledImages = max_descriptor_set_size,
811 .maxDescriptorSetStorageImages = max_descriptor_set_size,
812 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
813 .maxVertexInputAttributes = 32,
814 .maxVertexInputBindings = 32,
815 .maxVertexInputAttributeOffset = 2047,
816 .maxVertexInputBindingStride = 2048,
817 .maxVertexOutputComponents = 128,
818 .maxTessellationGenerationLevel = 64,
819 .maxTessellationPatchSize = 32,
820 .maxTessellationControlPerVertexInputComponents = 128,
821 .maxTessellationControlPerVertexOutputComponents = 128,
822 .maxTessellationControlPerPatchOutputComponents = 120,
823 .maxTessellationControlTotalOutputComponents = 4096,
824 .maxTessellationEvaluationInputComponents = 128,
825 .maxTessellationEvaluationOutputComponents = 128,
826 .maxGeometryShaderInvocations = 127,
827 .maxGeometryInputComponents = 64,
828 .maxGeometryOutputComponents = 128,
829 .maxGeometryOutputVertices = 256,
830 .maxGeometryTotalOutputComponents = 1024,
831 .maxFragmentInputComponents = 128,
832 .maxFragmentOutputAttachments = 8,
833 .maxFragmentDualSrcAttachments = 1,
834 .maxFragmentCombinedOutputResources = 8,
835 .maxComputeSharedMemorySize = 32768,
836 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
837 .maxComputeWorkGroupInvocations = 2048,
838 .maxComputeWorkGroupSize = {
839 2048,
840 2048,
841 2048
842 },
843 .subPixelPrecisionBits = 4 /* FIXME */,
844 .subTexelPrecisionBits = 4 /* FIXME */,
845 .mipmapPrecisionBits = 4 /* FIXME */,
846 .maxDrawIndexedIndexValue = UINT32_MAX,
847 .maxDrawIndirectCount = UINT32_MAX,
848 .maxSamplerLodBias = 16,
849 .maxSamplerAnisotropy = 16,
850 .maxViewports = MAX_VIEWPORTS,
851 .maxViewportDimensions = { (1 << 14), (1 << 14) },
852 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
853 .viewportSubPixelBits = 8,
854 .minMemoryMapAlignment = 4096, /* A page */
855 .minTexelBufferOffsetAlignment = 1,
856 .minUniformBufferOffsetAlignment = 4,
857 .minStorageBufferOffsetAlignment = 4,
858 .minTexelOffset = -32,
859 .maxTexelOffset = 31,
860 .minTexelGatherOffset = -32,
861 .maxTexelGatherOffset = 31,
862 .minInterpolationOffset = -2,
863 .maxInterpolationOffset = 2,
864 .subPixelInterpolationOffsetBits = 8,
865 .maxFramebufferWidth = (1 << 14),
866 .maxFramebufferHeight = (1 << 14),
867 .maxFramebufferLayers = (1 << 10),
868 .framebufferColorSampleCounts = sample_counts,
869 .framebufferDepthSampleCounts = sample_counts,
870 .framebufferStencilSampleCounts = sample_counts,
871 .framebufferNoAttachmentsSampleCounts = sample_counts,
872 .maxColorAttachments = MAX_RTS,
873 .sampledImageColorSampleCounts = sample_counts,
874 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
875 .sampledImageDepthSampleCounts = sample_counts,
876 .sampledImageStencilSampleCounts = sample_counts,
877 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
878 .maxSampleMaskWords = 1,
879 .timestampComputeAndGraphics = true,
880 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
881 .maxClipDistances = 8,
882 .maxCullDistances = 8,
883 .maxCombinedClipAndCullDistances = 8,
884 .discreteQueuePriorities = 1,
885 .pointSizeRange = { 0.125, 255.875 },
886 .lineWidthRange = { 0.0, 7.9921875 },
887 .pointSizeGranularity = (1.0 / 8.0),
888 .lineWidthGranularity = (1.0 / 128.0),
889 .strictLines = false, /* FINISHME */
890 .standardSampleLocations = true,
891 .optimalBufferCopyOffsetAlignment = 128,
892 .optimalBufferCopyRowPitchAlignment = 128,
893 .nonCoherentAtomSize = 64,
894 };
895
896 *pProperties = (VkPhysicalDeviceProperties) {
897 .apiVersion = radv_physical_device_api_version(pdevice),
898 .driverVersion = vk_get_driver_version(),
899 .vendorID = ATI_VENDOR_ID,
900 .deviceID = pdevice->rad_info.pci_id,
901 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
902 .limits = limits,
903 .sparseProperties = {0},
904 };
905
906 strcpy(pProperties->deviceName, pdevice->name);
907 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
908 }
909
910 void radv_GetPhysicalDeviceProperties2(
911 VkPhysicalDevice physicalDevice,
912 VkPhysicalDeviceProperties2KHR *pProperties)
913 {
914 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
915 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
916
917 vk_foreach_struct(ext, pProperties->pNext) {
918 switch (ext->sType) {
919 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
920 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
921 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
922 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
923 break;
924 }
925 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
926 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
927 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
928 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
929 properties->deviceLUIDValid = false;
930 break;
931 }
932 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHR: {
933 VkPhysicalDeviceMultiviewPropertiesKHR *properties = (VkPhysicalDeviceMultiviewPropertiesKHR*)ext;
934 properties->maxMultiviewViewCount = MAX_VIEWS;
935 properties->maxMultiviewInstanceIndex = INT_MAX;
936 break;
937 }
938 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
939 VkPhysicalDevicePointClippingPropertiesKHR *properties =
940 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
941 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
942 break;
943 }
944 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
945 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
946 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
947 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
948 break;
949 }
950 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
951 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
952 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
953 properties->minImportedHostPointerAlignment = 4096;
954 break;
955 }
956 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
957 VkPhysicalDeviceSubgroupProperties *properties =
958 (VkPhysicalDeviceSubgroupProperties*)ext;
959 properties->subgroupSize = 64;
960 properties->supportedStages = VK_SHADER_STAGE_ALL;
961 properties->supportedOperations =
962 VK_SUBGROUP_FEATURE_BASIC_BIT |
963 VK_SUBGROUP_FEATURE_BALLOT_BIT |
964 VK_SUBGROUP_FEATURE_QUAD_BIT |
965 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
966 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT |
967 VK_SUBGROUP_FEATURE_VOTE_BIT;
968 properties->quadOperationsInAllStages = true;
969 break;
970 }
971 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
972 VkPhysicalDeviceMaintenance3Properties *properties =
973 (VkPhysicalDeviceMaintenance3Properties*)ext;
974 /* Make sure everything is addressable by a signed 32-bit int, and
975 * our largest descriptors are 96 bytes. */
976 properties->maxPerSetDescriptors = (1ull << 31) / 96;
977 /* Our buffer size fields allow only this much */
978 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
979 break;
980 }
981 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
982 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
983 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
984 /* GFX6-8 only support single channel min/max filter. */
985 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
986 properties->filterMinmaxSingleComponentFormats = true;
987 break;
988 }
989 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
990 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
991 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
992
993 /* Shader engines. */
994 properties->shaderEngineCount =
995 pdevice->rad_info.max_se;
996 properties->shaderArraysPerEngineCount =
997 pdevice->rad_info.max_sh_per_se;
998 properties->computeUnitsPerShaderArray =
999 pdevice->rad_info.num_good_compute_units /
1000 (pdevice->rad_info.max_se *
1001 pdevice->rad_info.max_sh_per_se);
1002 properties->simdPerComputeUnit = 4;
1003 properties->wavefrontsPerSimd =
1004 pdevice->rad_info.family == CHIP_TONGA ||
1005 pdevice->rad_info.family == CHIP_ICELAND ||
1006 pdevice->rad_info.family == CHIP_POLARIS10 ||
1007 pdevice->rad_info.family == CHIP_POLARIS11 ||
1008 pdevice->rad_info.family == CHIP_POLARIS12 ||
1009 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1010 properties->wavefrontSize = 64;
1011
1012 /* SGPR. */
1013 properties->sgprsPerSimd =
1014 radv_get_num_physical_sgprs(pdevice);
1015 properties->minSgprAllocation =
1016 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1017 properties->maxSgprAllocation =
1018 pdevice->rad_info.family == CHIP_TONGA ||
1019 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1020 properties->sgprAllocationGranularity =
1021 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1022
1023 /* VGPR. */
1024 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1025 properties->minVgprAllocation = 4;
1026 properties->maxVgprAllocation = 256;
1027 properties->vgprAllocationGranularity = 4;
1028 break;
1029 }
1030 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1031 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1032 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1033 properties->maxVertexAttribDivisor = UINT32_MAX;
1034 break;
1035 }
1036 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1037 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1038 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1039 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1040 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1041 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1042 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1043 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1044 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1045 properties->robustBufferAccessUpdateAfterBind = false;
1046 properties->quadDivergentImplicitLod = false;
1047
1048 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1049 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1050 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1051 32 /* sampler, largest when combined with image */ +
1052 64 /* sampled image */ +
1053 64 /* storage image */);
1054 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1055 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1056 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1057 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1058 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1059 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1060 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1061 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1062 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1063 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1064 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1065 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1066 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1067 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1068 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1069 break;
1070 }
1071 default:
1072 break;
1073 }
1074 }
1075 }
1076
1077 static void radv_get_physical_device_queue_family_properties(
1078 struct radv_physical_device* pdevice,
1079 uint32_t* pCount,
1080 VkQueueFamilyProperties** pQueueFamilyProperties)
1081 {
1082 int num_queue_families = 1;
1083 int idx;
1084 if (pdevice->rad_info.num_compute_rings > 0 &&
1085 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1086 num_queue_families++;
1087
1088 if (pQueueFamilyProperties == NULL) {
1089 *pCount = num_queue_families;
1090 return;
1091 }
1092
1093 if (!*pCount)
1094 return;
1095
1096 idx = 0;
1097 if (*pCount >= 1) {
1098 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1099 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1100 VK_QUEUE_COMPUTE_BIT |
1101 VK_QUEUE_TRANSFER_BIT |
1102 VK_QUEUE_SPARSE_BINDING_BIT,
1103 .queueCount = 1,
1104 .timestampValidBits = 64,
1105 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1106 };
1107 idx++;
1108 }
1109
1110 if (pdevice->rad_info.num_compute_rings > 0 &&
1111 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1112 if (*pCount > idx) {
1113 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1114 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1115 VK_QUEUE_TRANSFER_BIT |
1116 VK_QUEUE_SPARSE_BINDING_BIT,
1117 .queueCount = pdevice->rad_info.num_compute_rings,
1118 .timestampValidBits = 64,
1119 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1120 };
1121 idx++;
1122 }
1123 }
1124 *pCount = idx;
1125 }
1126
1127 void radv_GetPhysicalDeviceQueueFamilyProperties(
1128 VkPhysicalDevice physicalDevice,
1129 uint32_t* pCount,
1130 VkQueueFamilyProperties* pQueueFamilyProperties)
1131 {
1132 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1133 if (!pQueueFamilyProperties) {
1134 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1135 return;
1136 }
1137 VkQueueFamilyProperties *properties[] = {
1138 pQueueFamilyProperties + 0,
1139 pQueueFamilyProperties + 1,
1140 pQueueFamilyProperties + 2,
1141 };
1142 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1143 assert(*pCount <= 3);
1144 }
1145
1146 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1147 VkPhysicalDevice physicalDevice,
1148 uint32_t* pCount,
1149 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
1150 {
1151 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1152 if (!pQueueFamilyProperties) {
1153 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1154 return;
1155 }
1156 VkQueueFamilyProperties *properties[] = {
1157 &pQueueFamilyProperties[0].queueFamilyProperties,
1158 &pQueueFamilyProperties[1].queueFamilyProperties,
1159 &pQueueFamilyProperties[2].queueFamilyProperties,
1160 };
1161 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1162 assert(*pCount <= 3);
1163 }
1164
1165 void radv_GetPhysicalDeviceMemoryProperties(
1166 VkPhysicalDevice physicalDevice,
1167 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1168 {
1169 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1170
1171 *pMemoryProperties = physical_device->memory_properties;
1172 }
1173
1174 void radv_GetPhysicalDeviceMemoryProperties2(
1175 VkPhysicalDevice physicalDevice,
1176 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
1177 {
1178 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1179 &pMemoryProperties->memoryProperties);
1180 }
1181
1182 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1183 VkDevice _device,
1184 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
1185 const void *pHostPointer,
1186 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1187 {
1188 RADV_FROM_HANDLE(radv_device, device, _device);
1189
1190 switch (handleType)
1191 {
1192 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1193 const struct radv_physical_device *physical_device = device->physical_device;
1194 uint32_t memoryTypeBits = 0;
1195 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1196 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1197 memoryTypeBits = (1 << i);
1198 break;
1199 }
1200 }
1201 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1202 return VK_SUCCESS;
1203 }
1204 default:
1205 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
1206 }
1207 }
1208
1209 static enum radeon_ctx_priority
1210 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1211 {
1212 /* Default to MEDIUM when a specific global priority isn't requested */
1213 if (!pObj)
1214 return RADEON_CTX_PRIORITY_MEDIUM;
1215
1216 switch(pObj->globalPriority) {
1217 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1218 return RADEON_CTX_PRIORITY_REALTIME;
1219 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1220 return RADEON_CTX_PRIORITY_HIGH;
1221 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1222 return RADEON_CTX_PRIORITY_MEDIUM;
1223 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1224 return RADEON_CTX_PRIORITY_LOW;
1225 default:
1226 unreachable("Illegal global priority value");
1227 return RADEON_CTX_PRIORITY_INVALID;
1228 }
1229 }
1230
1231 static int
1232 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1233 uint32_t queue_family_index, int idx,
1234 VkDeviceQueueCreateFlags flags,
1235 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1236 {
1237 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1238 queue->device = device;
1239 queue->queue_family_index = queue_family_index;
1240 queue->queue_idx = idx;
1241 queue->priority = radv_get_queue_global_priority(global_priority);
1242 queue->flags = flags;
1243
1244 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1245 if (!queue->hw_ctx)
1246 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1247
1248 return VK_SUCCESS;
1249 }
1250
1251 static void
1252 radv_queue_finish(struct radv_queue *queue)
1253 {
1254 if (queue->hw_ctx)
1255 queue->device->ws->ctx_destroy(queue->hw_ctx);
1256
1257 if (queue->initial_full_flush_preamble_cs)
1258 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1259 if (queue->initial_preamble_cs)
1260 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1261 if (queue->continue_preamble_cs)
1262 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1263 if (queue->descriptor_bo)
1264 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1265 if (queue->scratch_bo)
1266 queue->device->ws->buffer_destroy(queue->scratch_bo);
1267 if (queue->esgs_ring_bo)
1268 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1269 if (queue->gsvs_ring_bo)
1270 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1271 if (queue->tess_rings_bo)
1272 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1273 if (queue->compute_scratch_bo)
1274 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1275 }
1276
1277 static void
1278 radv_bo_list_init(struct radv_bo_list *bo_list)
1279 {
1280 pthread_mutex_init(&bo_list->mutex, NULL);
1281 bo_list->list.count = bo_list->capacity = 0;
1282 bo_list->list.bos = NULL;
1283 }
1284
1285 static void
1286 radv_bo_list_finish(struct radv_bo_list *bo_list)
1287 {
1288 free(bo_list->list.bos);
1289 pthread_mutex_destroy(&bo_list->mutex);
1290 }
1291
1292 static VkResult radv_bo_list_add(struct radv_device *device,
1293 struct radeon_winsys_bo *bo)
1294 {
1295 struct radv_bo_list *bo_list = &device->bo_list;
1296
1297 if (unlikely(!device->use_global_bo_list))
1298 return VK_SUCCESS;
1299
1300 pthread_mutex_lock(&bo_list->mutex);
1301 if (bo_list->list.count == bo_list->capacity) {
1302 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1303 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1304
1305 if (!data) {
1306 pthread_mutex_unlock(&bo_list->mutex);
1307 return VK_ERROR_OUT_OF_HOST_MEMORY;
1308 }
1309
1310 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1311 bo_list->capacity = capacity;
1312 }
1313
1314 bo_list->list.bos[bo_list->list.count++] = bo;
1315 pthread_mutex_unlock(&bo_list->mutex);
1316 return VK_SUCCESS;
1317 }
1318
1319 static void radv_bo_list_remove(struct radv_device *device,
1320 struct radeon_winsys_bo *bo)
1321 {
1322 struct radv_bo_list *bo_list = &device->bo_list;
1323
1324 if (unlikely(!device->use_global_bo_list))
1325 return;
1326
1327 pthread_mutex_lock(&bo_list->mutex);
1328 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1329 if (bo_list->list.bos[i] == bo) {
1330 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1331 --bo_list->list.count;
1332 break;
1333 }
1334 }
1335 pthread_mutex_unlock(&bo_list->mutex);
1336 }
1337
1338 static void
1339 radv_device_init_gs_info(struct radv_device *device)
1340 {
1341 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1342 device->physical_device->rad_info.family);
1343 }
1344
1345 static int radv_get_device_extension_index(const char *name)
1346 {
1347 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1348 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1349 return i;
1350 }
1351 return -1;
1352 }
1353
1354 VkResult radv_CreateDevice(
1355 VkPhysicalDevice physicalDevice,
1356 const VkDeviceCreateInfo* pCreateInfo,
1357 const VkAllocationCallbacks* pAllocator,
1358 VkDevice* pDevice)
1359 {
1360 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1361 VkResult result;
1362 struct radv_device *device;
1363
1364 bool keep_shader_info = false;
1365
1366 /* Check enabled features */
1367 if (pCreateInfo->pEnabledFeatures) {
1368 VkPhysicalDeviceFeatures supported_features;
1369 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1370 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1371 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1372 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1373 for (uint32_t i = 0; i < num_features; i++) {
1374 if (enabled_feature[i] && !supported_feature[i])
1375 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
1376 }
1377 }
1378
1379 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1380 sizeof(*device), 8,
1381 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1382 if (!device)
1383 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1384
1385 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1386 device->instance = physical_device->instance;
1387 device->physical_device = physical_device;
1388
1389 device->ws = physical_device->ws;
1390 if (pAllocator)
1391 device->alloc = *pAllocator;
1392 else
1393 device->alloc = physical_device->instance->alloc;
1394
1395 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1396 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1397 int index = radv_get_device_extension_index(ext_name);
1398 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1399 vk_free(&device->alloc, device);
1400 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
1401 }
1402
1403 device->enabled_extensions.extensions[index] = true;
1404 }
1405
1406 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1407
1408 /* With update after bind we can't attach bo's to the command buffer
1409 * from the descriptor set anymore, so we have to use a global BO list.
1410 */
1411 device->use_global_bo_list =
1412 device->enabled_extensions.EXT_descriptor_indexing;
1413
1414 mtx_init(&device->shader_slab_mutex, mtx_plain);
1415 list_inithead(&device->shader_slabs);
1416
1417 radv_bo_list_init(&device->bo_list);
1418
1419 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1420 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1421 uint32_t qfi = queue_create->queueFamilyIndex;
1422 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1423 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1424
1425 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1426
1427 device->queues[qfi] = vk_alloc(&device->alloc,
1428 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1429 if (!device->queues[qfi]) {
1430 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1431 goto fail;
1432 }
1433
1434 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1435
1436 device->queue_count[qfi] = queue_create->queueCount;
1437
1438 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1439 result = radv_queue_init(device, &device->queues[qfi][q],
1440 qfi, q, queue_create->flags,
1441 global_priority);
1442 if (result != VK_SUCCESS)
1443 goto fail;
1444 }
1445 }
1446
1447 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1448 (device->instance->perftest_flags & RADV_PERFTEST_BINNING);
1449
1450 /* Disabled and not implemented for now. */
1451 device->dfsm_allowed = device->pbb_allowed && false;
1452
1453 #ifdef ANDROID
1454 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1455 #endif
1456
1457 /* The maximum number of scratch waves. Scratch space isn't divided
1458 * evenly between CUs. The number is only a function of the number of CUs.
1459 * We can decrease the constant to decrease the scratch buffer size.
1460 *
1461 * sctx->scratch_waves must be >= the maximum possible size of
1462 * 1 threadgroup, so that the hw doesn't hang from being unable
1463 * to start any.
1464 *
1465 * The recommended value is 4 per CU at most. Higher numbers don't
1466 * bring much benefit, but they still occupy chip resources (think
1467 * async compute). I've seen ~2% performance difference between 4 and 32.
1468 */
1469 uint32_t max_threads_per_block = 2048;
1470 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1471 max_threads_per_block / 64);
1472
1473 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1474
1475 if (device->physical_device->rad_info.chip_class >= CIK) {
1476 /* If the KMD allows it (there is a KMD hw register for it),
1477 * allow launching waves out-of-order.
1478 */
1479 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1480 }
1481
1482 radv_device_init_gs_info(device);
1483
1484 device->tess_offchip_block_dw_size =
1485 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1486 device->has_distributed_tess =
1487 device->physical_device->rad_info.chip_class >= VI &&
1488 device->physical_device->rad_info.max_se >= 2;
1489
1490 if (getenv("RADV_TRACE_FILE")) {
1491 const char *filename = getenv("RADV_TRACE_FILE");
1492
1493 keep_shader_info = true;
1494
1495 if (!radv_init_trace(device))
1496 goto fail;
1497
1498 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1499 radv_dump_enabled_options(device, stderr);
1500 }
1501
1502 device->keep_shader_info = keep_shader_info;
1503
1504 result = radv_device_init_meta(device);
1505 if (result != VK_SUCCESS)
1506 goto fail;
1507
1508 radv_device_init_msaa(device);
1509
1510 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1511 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1512 switch (family) {
1513 case RADV_QUEUE_GENERAL:
1514 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1515 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1516 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1517 break;
1518 case RADV_QUEUE_COMPUTE:
1519 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1520 radeon_emit(device->empty_cs[family], 0);
1521 break;
1522 }
1523 device->ws->cs_finalize(device->empty_cs[family]);
1524 }
1525
1526 if (device->physical_device->rad_info.chip_class >= CIK)
1527 cik_create_gfx_config(device);
1528
1529 VkPipelineCacheCreateInfo ci;
1530 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1531 ci.pNext = NULL;
1532 ci.flags = 0;
1533 ci.pInitialData = NULL;
1534 ci.initialDataSize = 0;
1535 VkPipelineCache pc;
1536 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1537 &ci, NULL, &pc);
1538 if (result != VK_SUCCESS)
1539 goto fail_meta;
1540
1541 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1542
1543 *pDevice = radv_device_to_handle(device);
1544 return VK_SUCCESS;
1545
1546 fail_meta:
1547 radv_device_finish_meta(device);
1548 fail:
1549 radv_bo_list_finish(&device->bo_list);
1550
1551 if (device->trace_bo)
1552 device->ws->buffer_destroy(device->trace_bo);
1553
1554 if (device->gfx_init)
1555 device->ws->buffer_destroy(device->gfx_init);
1556
1557 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1558 for (unsigned q = 0; q < device->queue_count[i]; q++)
1559 radv_queue_finish(&device->queues[i][q]);
1560 if (device->queue_count[i])
1561 vk_free(&device->alloc, device->queues[i]);
1562 }
1563
1564 vk_free(&device->alloc, device);
1565 return result;
1566 }
1567
1568 void radv_DestroyDevice(
1569 VkDevice _device,
1570 const VkAllocationCallbacks* pAllocator)
1571 {
1572 RADV_FROM_HANDLE(radv_device, device, _device);
1573
1574 if (!device)
1575 return;
1576
1577 if (device->trace_bo)
1578 device->ws->buffer_destroy(device->trace_bo);
1579
1580 if (device->gfx_init)
1581 device->ws->buffer_destroy(device->gfx_init);
1582
1583 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1584 for (unsigned q = 0; q < device->queue_count[i]; q++)
1585 radv_queue_finish(&device->queues[i][q]);
1586 if (device->queue_count[i])
1587 vk_free(&device->alloc, device->queues[i]);
1588 if (device->empty_cs[i])
1589 device->ws->cs_destroy(device->empty_cs[i]);
1590 }
1591 radv_device_finish_meta(device);
1592
1593 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1594 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1595
1596 radv_destroy_shader_slabs(device);
1597
1598 radv_bo_list_finish(&device->bo_list);
1599 vk_free(&device->alloc, device);
1600 }
1601
1602 VkResult radv_EnumerateInstanceLayerProperties(
1603 uint32_t* pPropertyCount,
1604 VkLayerProperties* pProperties)
1605 {
1606 if (pProperties == NULL) {
1607 *pPropertyCount = 0;
1608 return VK_SUCCESS;
1609 }
1610
1611 /* None supported at this time */
1612 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1613 }
1614
1615 VkResult radv_EnumerateDeviceLayerProperties(
1616 VkPhysicalDevice physicalDevice,
1617 uint32_t* pPropertyCount,
1618 VkLayerProperties* pProperties)
1619 {
1620 if (pProperties == NULL) {
1621 *pPropertyCount = 0;
1622 return VK_SUCCESS;
1623 }
1624
1625 /* None supported at this time */
1626 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1627 }
1628
1629 void radv_GetDeviceQueue2(
1630 VkDevice _device,
1631 const VkDeviceQueueInfo2* pQueueInfo,
1632 VkQueue* pQueue)
1633 {
1634 RADV_FROM_HANDLE(radv_device, device, _device);
1635 struct radv_queue *queue;
1636
1637 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
1638 if (pQueueInfo->flags != queue->flags) {
1639 /* From the Vulkan 1.1.70 spec:
1640 *
1641 * "The queue returned by vkGetDeviceQueue2 must have the same
1642 * flags value from this structure as that used at device
1643 * creation time in a VkDeviceQueueCreateInfo instance. If no
1644 * matching flags were specified at device creation time then
1645 * pQueue will return VK_NULL_HANDLE."
1646 */
1647 *pQueue = VK_NULL_HANDLE;
1648 return;
1649 }
1650
1651 *pQueue = radv_queue_to_handle(queue);
1652 }
1653
1654 void radv_GetDeviceQueue(
1655 VkDevice _device,
1656 uint32_t queueFamilyIndex,
1657 uint32_t queueIndex,
1658 VkQueue* pQueue)
1659 {
1660 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
1661 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
1662 .queueFamilyIndex = queueFamilyIndex,
1663 .queueIndex = queueIndex
1664 };
1665
1666 radv_GetDeviceQueue2(_device, &info, pQueue);
1667 }
1668
1669 static void
1670 fill_geom_tess_rings(struct radv_queue *queue,
1671 uint32_t *map,
1672 bool add_sample_positions,
1673 uint32_t esgs_ring_size,
1674 struct radeon_winsys_bo *esgs_ring_bo,
1675 uint32_t gsvs_ring_size,
1676 struct radeon_winsys_bo *gsvs_ring_bo,
1677 uint32_t tess_factor_ring_size,
1678 uint32_t tess_offchip_ring_offset,
1679 uint32_t tess_offchip_ring_size,
1680 struct radeon_winsys_bo *tess_rings_bo)
1681 {
1682 uint64_t esgs_va = 0, gsvs_va = 0;
1683 uint64_t tess_va = 0, tess_offchip_va = 0;
1684 uint32_t *desc = &map[4];
1685
1686 if (esgs_ring_bo)
1687 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1688 if (gsvs_ring_bo)
1689 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1690 if (tess_rings_bo) {
1691 tess_va = radv_buffer_get_va(tess_rings_bo);
1692 tess_offchip_va = tess_va + tess_offchip_ring_offset;
1693 }
1694
1695 /* stride 0, num records - size, add tid, swizzle, elsize4,
1696 index stride 64 */
1697 desc[0] = esgs_va;
1698 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1699 S_008F04_STRIDE(0) |
1700 S_008F04_SWIZZLE_ENABLE(true);
1701 desc[2] = esgs_ring_size;
1702 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1703 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1704 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1705 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1706 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1707 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1708 S_008F0C_ELEMENT_SIZE(1) |
1709 S_008F0C_INDEX_STRIDE(3) |
1710 S_008F0C_ADD_TID_ENABLE(true);
1711
1712 desc += 4;
1713 /* GS entry for ES->GS ring */
1714 /* stride 0, num records - size, elsize0,
1715 index stride 0 */
1716 desc[0] = esgs_va;
1717 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1718 S_008F04_STRIDE(0) |
1719 S_008F04_SWIZZLE_ENABLE(false);
1720 desc[2] = esgs_ring_size;
1721 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1722 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1723 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1724 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1725 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1726 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1727 S_008F0C_ELEMENT_SIZE(0) |
1728 S_008F0C_INDEX_STRIDE(0) |
1729 S_008F0C_ADD_TID_ENABLE(false);
1730
1731 desc += 4;
1732 /* VS entry for GS->VS ring */
1733 /* stride 0, num records - size, elsize0,
1734 index stride 0 */
1735 desc[0] = gsvs_va;
1736 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1737 S_008F04_STRIDE(0) |
1738 S_008F04_SWIZZLE_ENABLE(false);
1739 desc[2] = gsvs_ring_size;
1740 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1741 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1742 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1743 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1744 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1745 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1746 S_008F0C_ELEMENT_SIZE(0) |
1747 S_008F0C_INDEX_STRIDE(0) |
1748 S_008F0C_ADD_TID_ENABLE(false);
1749 desc += 4;
1750
1751 /* stride gsvs_itemsize, num records 64
1752 elsize 4, index stride 16 */
1753 /* shader will patch stride and desc[2] */
1754 desc[0] = gsvs_va;
1755 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1756 S_008F04_STRIDE(0) |
1757 S_008F04_SWIZZLE_ENABLE(true);
1758 desc[2] = 0;
1759 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1760 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1761 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1762 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1763 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1764 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1765 S_008F0C_ELEMENT_SIZE(1) |
1766 S_008F0C_INDEX_STRIDE(1) |
1767 S_008F0C_ADD_TID_ENABLE(true);
1768 desc += 4;
1769
1770 desc[0] = tess_va;
1771 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
1772 S_008F04_STRIDE(0) |
1773 S_008F04_SWIZZLE_ENABLE(false);
1774 desc[2] = tess_factor_ring_size;
1775 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1776 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1777 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1778 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1779 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1780 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1781 S_008F0C_ELEMENT_SIZE(0) |
1782 S_008F0C_INDEX_STRIDE(0) |
1783 S_008F0C_ADD_TID_ENABLE(false);
1784 desc += 4;
1785
1786 desc[0] = tess_offchip_va;
1787 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1788 S_008F04_STRIDE(0) |
1789 S_008F04_SWIZZLE_ENABLE(false);
1790 desc[2] = tess_offchip_ring_size;
1791 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1792 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1793 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1794 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1795 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1796 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1797 S_008F0C_ELEMENT_SIZE(0) |
1798 S_008F0C_INDEX_STRIDE(0) |
1799 S_008F0C_ADD_TID_ENABLE(false);
1800 desc += 4;
1801
1802 /* add sample positions after all rings */
1803 memcpy(desc, queue->device->sample_locations_1x, 8);
1804 desc += 2;
1805 memcpy(desc, queue->device->sample_locations_2x, 16);
1806 desc += 4;
1807 memcpy(desc, queue->device->sample_locations_4x, 32);
1808 desc += 8;
1809 memcpy(desc, queue->device->sample_locations_8x, 64);
1810 desc += 16;
1811 memcpy(desc, queue->device->sample_locations_16x, 128);
1812 }
1813
1814 static unsigned
1815 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1816 {
1817 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1818 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1819 device->physical_device->rad_info.family != CHIP_STONEY;
1820 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1821 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1822 device->physical_device->rad_info.max_se;
1823 unsigned offchip_granularity;
1824 unsigned hs_offchip_param;
1825 switch (device->tess_offchip_block_dw_size) {
1826 default:
1827 assert(0);
1828 /* fall through */
1829 case 8192:
1830 offchip_granularity = V_03093C_X_8K_DWORDS;
1831 break;
1832 case 4096:
1833 offchip_granularity = V_03093C_X_4K_DWORDS;
1834 break;
1835 }
1836
1837 switch (device->physical_device->rad_info.chip_class) {
1838 case SI:
1839 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1840 break;
1841 case CIK:
1842 case VI:
1843 case GFX9:
1844 default:
1845 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1846 break;
1847 }
1848
1849 *max_offchip_buffers_p = max_offchip_buffers;
1850 if (device->physical_device->rad_info.chip_class >= CIK) {
1851 if (device->physical_device->rad_info.chip_class >= VI)
1852 --max_offchip_buffers;
1853 hs_offchip_param =
1854 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1855 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1856 } else {
1857 hs_offchip_param =
1858 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1859 }
1860 return hs_offchip_param;
1861 }
1862
1863 static VkResult
1864 radv_get_preamble_cs(struct radv_queue *queue,
1865 uint32_t scratch_size,
1866 uint32_t compute_scratch_size,
1867 uint32_t esgs_ring_size,
1868 uint32_t gsvs_ring_size,
1869 bool needs_tess_rings,
1870 bool needs_sample_positions,
1871 struct radeon_winsys_cs **initial_full_flush_preamble_cs,
1872 struct radeon_winsys_cs **initial_preamble_cs,
1873 struct radeon_winsys_cs **continue_preamble_cs)
1874 {
1875 struct radeon_winsys_bo *scratch_bo = NULL;
1876 struct radeon_winsys_bo *descriptor_bo = NULL;
1877 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1878 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1879 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1880 struct radeon_winsys_bo *tess_rings_bo = NULL;
1881 struct radeon_winsys_cs *dest_cs[3] = {0};
1882 bool add_tess_rings = false, add_sample_positions = false;
1883 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1884 unsigned max_offchip_buffers;
1885 unsigned hs_offchip_param = 0;
1886 unsigned tess_offchip_ring_offset;
1887 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
1888 if (!queue->has_tess_rings) {
1889 if (needs_tess_rings)
1890 add_tess_rings = true;
1891 }
1892 if (!queue->has_sample_positions) {
1893 if (needs_sample_positions)
1894 add_sample_positions = true;
1895 }
1896 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1897 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1898 &max_offchip_buffers);
1899 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
1900 tess_offchip_ring_size = max_offchip_buffers *
1901 queue->device->tess_offchip_block_dw_size * 4;
1902
1903 if (scratch_size <= queue->scratch_size &&
1904 compute_scratch_size <= queue->compute_scratch_size &&
1905 esgs_ring_size <= queue->esgs_ring_size &&
1906 gsvs_ring_size <= queue->gsvs_ring_size &&
1907 !add_tess_rings && !add_sample_positions &&
1908 queue->initial_preamble_cs) {
1909 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1910 *initial_preamble_cs = queue->initial_preamble_cs;
1911 *continue_preamble_cs = queue->continue_preamble_cs;
1912 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1913 *continue_preamble_cs = NULL;
1914 return VK_SUCCESS;
1915 }
1916
1917 if (scratch_size > queue->scratch_size) {
1918 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1919 scratch_size,
1920 4096,
1921 RADEON_DOMAIN_VRAM,
1922 ring_bo_flags);
1923 if (!scratch_bo)
1924 goto fail;
1925 } else
1926 scratch_bo = queue->scratch_bo;
1927
1928 if (compute_scratch_size > queue->compute_scratch_size) {
1929 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1930 compute_scratch_size,
1931 4096,
1932 RADEON_DOMAIN_VRAM,
1933 ring_bo_flags);
1934 if (!compute_scratch_bo)
1935 goto fail;
1936
1937 } else
1938 compute_scratch_bo = queue->compute_scratch_bo;
1939
1940 if (esgs_ring_size > queue->esgs_ring_size) {
1941 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1942 esgs_ring_size,
1943 4096,
1944 RADEON_DOMAIN_VRAM,
1945 ring_bo_flags);
1946 if (!esgs_ring_bo)
1947 goto fail;
1948 } else {
1949 esgs_ring_bo = queue->esgs_ring_bo;
1950 esgs_ring_size = queue->esgs_ring_size;
1951 }
1952
1953 if (gsvs_ring_size > queue->gsvs_ring_size) {
1954 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1955 gsvs_ring_size,
1956 4096,
1957 RADEON_DOMAIN_VRAM,
1958 ring_bo_flags);
1959 if (!gsvs_ring_bo)
1960 goto fail;
1961 } else {
1962 gsvs_ring_bo = queue->gsvs_ring_bo;
1963 gsvs_ring_size = queue->gsvs_ring_size;
1964 }
1965
1966 if (add_tess_rings) {
1967 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
1968 tess_offchip_ring_offset + tess_offchip_ring_size,
1969 256,
1970 RADEON_DOMAIN_VRAM,
1971 ring_bo_flags);
1972 if (!tess_rings_bo)
1973 goto fail;
1974 } else {
1975 tess_rings_bo = queue->tess_rings_bo;
1976 }
1977
1978 if (scratch_bo != queue->scratch_bo ||
1979 esgs_ring_bo != queue->esgs_ring_bo ||
1980 gsvs_ring_bo != queue->gsvs_ring_bo ||
1981 tess_rings_bo != queue->tess_rings_bo ||
1982 add_sample_positions) {
1983 uint32_t size = 0;
1984 if (gsvs_ring_bo || esgs_ring_bo ||
1985 tess_rings_bo || add_sample_positions) {
1986 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
1987 if (add_sample_positions)
1988 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1989 }
1990 else if (scratch_bo)
1991 size = 8; /* 2 dword */
1992
1993 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1994 size,
1995 4096,
1996 RADEON_DOMAIN_VRAM,
1997 RADEON_FLAG_CPU_ACCESS |
1998 RADEON_FLAG_NO_INTERPROCESS_SHARING |
1999 RADEON_FLAG_READ_ONLY);
2000 if (!descriptor_bo)
2001 goto fail;
2002 } else
2003 descriptor_bo = queue->descriptor_bo;
2004
2005 for(int i = 0; i < 3; ++i) {
2006 struct radeon_winsys_cs *cs = NULL;
2007 cs = queue->device->ws->cs_create(queue->device->ws,
2008 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2009 if (!cs)
2010 goto fail;
2011
2012 dest_cs[i] = cs;
2013
2014 if (scratch_bo)
2015 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo, 8);
2016
2017 if (esgs_ring_bo)
2018 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo, 8);
2019
2020 if (gsvs_ring_bo)
2021 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo, 8);
2022
2023 if (tess_rings_bo)
2024 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo, 8);
2025
2026 if (descriptor_bo)
2027 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo, 8);
2028
2029 if (descriptor_bo != queue->descriptor_bo) {
2030 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2031
2032 if (scratch_bo) {
2033 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2034 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2035 S_008F04_SWIZZLE_ENABLE(1);
2036 map[0] = scratch_va;
2037 map[1] = rsrc1;
2038 }
2039
2040 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo ||
2041 add_sample_positions)
2042 fill_geom_tess_rings(queue, map, add_sample_positions,
2043 esgs_ring_size, esgs_ring_bo,
2044 gsvs_ring_size, gsvs_ring_bo,
2045 tess_factor_ring_size,
2046 tess_offchip_ring_offset,
2047 tess_offchip_ring_size,
2048 tess_rings_bo);
2049
2050 queue->device->ws->buffer_unmap(descriptor_bo);
2051 }
2052
2053 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2054 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2055 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2056 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2057 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2058 }
2059
2060 if (esgs_ring_bo || gsvs_ring_bo) {
2061 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2062 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2063 radeon_emit(cs, esgs_ring_size >> 8);
2064 radeon_emit(cs, gsvs_ring_size >> 8);
2065 } else {
2066 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2067 radeon_emit(cs, esgs_ring_size >> 8);
2068 radeon_emit(cs, gsvs_ring_size >> 8);
2069 }
2070 }
2071
2072 if (tess_rings_bo) {
2073 uint64_t tf_va = radv_buffer_get_va(tess_rings_bo);
2074 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2075 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2076 S_030938_SIZE(tess_factor_ring_size / 4));
2077 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2078 tf_va >> 8);
2079 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2080 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2081 S_030944_BASE_HI(tf_va >> 40));
2082 }
2083 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
2084 } else {
2085 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2086 S_008988_SIZE(tess_factor_ring_size / 4));
2087 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2088 tf_va >> 8);
2089 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2090 hs_offchip_param);
2091 }
2092 }
2093
2094 if (descriptor_bo) {
2095 uint64_t va = radv_buffer_get_va(descriptor_bo);
2096 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2097 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2098 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2099 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2100 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2101
2102 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2103 radeon_set_sh_reg_seq(cs, regs[i], 2);
2104 radeon_emit(cs, va);
2105 radeon_emit(cs, va >> 32);
2106 }
2107 } else {
2108 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2109 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2110 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2111 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2112 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2113 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2114
2115 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2116 radeon_set_sh_reg_seq(cs, regs[i], 2);
2117 radeon_emit(cs, va);
2118 radeon_emit(cs, va >> 32);
2119 }
2120 }
2121 }
2122
2123 if (compute_scratch_bo) {
2124 uint64_t scratch_va = radv_buffer_get_va(compute_scratch_bo);
2125 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2126 S_008F04_SWIZZLE_ENABLE(1);
2127
2128 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo, 8);
2129
2130 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2131 radeon_emit(cs, scratch_va);
2132 radeon_emit(cs, rsrc1);
2133 }
2134
2135 if (i == 0) {
2136 si_cs_emit_cache_flush(cs,
2137 queue->device->physical_device->rad_info.chip_class,
2138 NULL, 0,
2139 queue->queue_family_index == RING_COMPUTE &&
2140 queue->device->physical_device->rad_info.chip_class >= CIK,
2141 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2142 RADV_CMD_FLAG_INV_ICACHE |
2143 RADV_CMD_FLAG_INV_SMEM_L1 |
2144 RADV_CMD_FLAG_INV_VMEM_L1 |
2145 RADV_CMD_FLAG_INV_GLOBAL_L2);
2146 } else if (i == 1) {
2147 si_cs_emit_cache_flush(cs,
2148 queue->device->physical_device->rad_info.chip_class,
2149 NULL, 0,
2150 queue->queue_family_index == RING_COMPUTE &&
2151 queue->device->physical_device->rad_info.chip_class >= CIK,
2152 RADV_CMD_FLAG_INV_ICACHE |
2153 RADV_CMD_FLAG_INV_SMEM_L1 |
2154 RADV_CMD_FLAG_INV_VMEM_L1 |
2155 RADV_CMD_FLAG_INV_GLOBAL_L2);
2156 }
2157
2158 if (!queue->device->ws->cs_finalize(cs))
2159 goto fail;
2160 }
2161
2162 if (queue->initial_full_flush_preamble_cs)
2163 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2164
2165 if (queue->initial_preamble_cs)
2166 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2167
2168 if (queue->continue_preamble_cs)
2169 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2170
2171 queue->initial_full_flush_preamble_cs = dest_cs[0];
2172 queue->initial_preamble_cs = dest_cs[1];
2173 queue->continue_preamble_cs = dest_cs[2];
2174
2175 if (scratch_bo != queue->scratch_bo) {
2176 if (queue->scratch_bo)
2177 queue->device->ws->buffer_destroy(queue->scratch_bo);
2178 queue->scratch_bo = scratch_bo;
2179 queue->scratch_size = scratch_size;
2180 }
2181
2182 if (compute_scratch_bo != queue->compute_scratch_bo) {
2183 if (queue->compute_scratch_bo)
2184 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2185 queue->compute_scratch_bo = compute_scratch_bo;
2186 queue->compute_scratch_size = compute_scratch_size;
2187 }
2188
2189 if (esgs_ring_bo != queue->esgs_ring_bo) {
2190 if (queue->esgs_ring_bo)
2191 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2192 queue->esgs_ring_bo = esgs_ring_bo;
2193 queue->esgs_ring_size = esgs_ring_size;
2194 }
2195
2196 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2197 if (queue->gsvs_ring_bo)
2198 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2199 queue->gsvs_ring_bo = gsvs_ring_bo;
2200 queue->gsvs_ring_size = gsvs_ring_size;
2201 }
2202
2203 if (tess_rings_bo != queue->tess_rings_bo) {
2204 queue->tess_rings_bo = tess_rings_bo;
2205 queue->has_tess_rings = true;
2206 }
2207
2208 if (descriptor_bo != queue->descriptor_bo) {
2209 if (queue->descriptor_bo)
2210 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2211
2212 queue->descriptor_bo = descriptor_bo;
2213 }
2214
2215 if (add_sample_positions)
2216 queue->has_sample_positions = true;
2217
2218 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2219 *initial_preamble_cs = queue->initial_preamble_cs;
2220 *continue_preamble_cs = queue->continue_preamble_cs;
2221 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2222 *continue_preamble_cs = NULL;
2223 return VK_SUCCESS;
2224 fail:
2225 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2226 if (dest_cs[i])
2227 queue->device->ws->cs_destroy(dest_cs[i]);
2228 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2229 queue->device->ws->buffer_destroy(descriptor_bo);
2230 if (scratch_bo && scratch_bo != queue->scratch_bo)
2231 queue->device->ws->buffer_destroy(scratch_bo);
2232 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2233 queue->device->ws->buffer_destroy(compute_scratch_bo);
2234 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2235 queue->device->ws->buffer_destroy(esgs_ring_bo);
2236 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2237 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2238 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2239 queue->device->ws->buffer_destroy(tess_rings_bo);
2240 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2241 }
2242
2243 static VkResult radv_alloc_sem_counts(struct radv_winsys_sem_counts *counts,
2244 int num_sems,
2245 const VkSemaphore *sems,
2246 VkFence _fence,
2247 bool reset_temp)
2248 {
2249 int syncobj_idx = 0, sem_idx = 0;
2250
2251 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2252 return VK_SUCCESS;
2253
2254 for (uint32_t i = 0; i < num_sems; i++) {
2255 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2256
2257 if (sem->temp_syncobj || sem->syncobj)
2258 counts->syncobj_count++;
2259 else
2260 counts->sem_count++;
2261 }
2262
2263 if (_fence != VK_NULL_HANDLE) {
2264 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2265 if (fence->temp_syncobj || fence->syncobj)
2266 counts->syncobj_count++;
2267 }
2268
2269 if (counts->syncobj_count) {
2270 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2271 if (!counts->syncobj)
2272 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2273 }
2274
2275 if (counts->sem_count) {
2276 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2277 if (!counts->sem) {
2278 free(counts->syncobj);
2279 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2280 }
2281 }
2282
2283 for (uint32_t i = 0; i < num_sems; i++) {
2284 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2285
2286 if (sem->temp_syncobj) {
2287 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2288 }
2289 else if (sem->syncobj)
2290 counts->syncobj[syncobj_idx++] = sem->syncobj;
2291 else {
2292 assert(sem->sem);
2293 counts->sem[sem_idx++] = sem->sem;
2294 }
2295 }
2296
2297 if (_fence != VK_NULL_HANDLE) {
2298 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2299 if (fence->temp_syncobj)
2300 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2301 else if (fence->syncobj)
2302 counts->syncobj[syncobj_idx++] = fence->syncobj;
2303 }
2304
2305 return VK_SUCCESS;
2306 }
2307
2308 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2309 {
2310 free(sem_info->wait.syncobj);
2311 free(sem_info->wait.sem);
2312 free(sem_info->signal.syncobj);
2313 free(sem_info->signal.sem);
2314 }
2315
2316
2317 static void radv_free_temp_syncobjs(struct radv_device *device,
2318 int num_sems,
2319 const VkSemaphore *sems)
2320 {
2321 for (uint32_t i = 0; i < num_sems; i++) {
2322 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2323
2324 if (sem->temp_syncobj) {
2325 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2326 sem->temp_syncobj = 0;
2327 }
2328 }
2329 }
2330
2331 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
2332 int num_wait_sems,
2333 const VkSemaphore *wait_sems,
2334 int num_signal_sems,
2335 const VkSemaphore *signal_sems,
2336 VkFence fence)
2337 {
2338 VkResult ret;
2339 memset(sem_info, 0, sizeof(*sem_info));
2340
2341 ret = radv_alloc_sem_counts(&sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2342 if (ret)
2343 return ret;
2344 ret = radv_alloc_sem_counts(&sem_info->signal, num_signal_sems, signal_sems, fence, false);
2345 if (ret)
2346 radv_free_sem_info(sem_info);
2347
2348 /* caller can override these */
2349 sem_info->cs_emit_wait = true;
2350 sem_info->cs_emit_signal = true;
2351 return ret;
2352 }
2353
2354 /* Signals fence as soon as all the work currently put on queue is done. */
2355 static VkResult radv_signal_fence(struct radv_queue *queue,
2356 struct radv_fence *fence)
2357 {
2358 int ret;
2359 VkResult result;
2360 struct radv_winsys_sem_info sem_info;
2361
2362 result = radv_alloc_sem_info(&sem_info, 0, NULL, 0, NULL,
2363 radv_fence_to_handle(fence));
2364 if (result != VK_SUCCESS)
2365 return result;
2366
2367 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2368 &queue->device->empty_cs[queue->queue_family_index],
2369 1, NULL, NULL, &sem_info, NULL,
2370 false, fence->fence);
2371 radv_free_sem_info(&sem_info);
2372
2373 /* TODO: find a better error */
2374 if (ret)
2375 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2376
2377 return VK_SUCCESS;
2378 }
2379
2380 VkResult radv_QueueSubmit(
2381 VkQueue _queue,
2382 uint32_t submitCount,
2383 const VkSubmitInfo* pSubmits,
2384 VkFence _fence)
2385 {
2386 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2387 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2388 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2389 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2390 int ret;
2391 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2392 uint32_t scratch_size = 0;
2393 uint32_t compute_scratch_size = 0;
2394 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2395 struct radeon_winsys_cs *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2396 VkResult result;
2397 bool fence_emitted = false;
2398 bool tess_rings_needed = false;
2399 bool sample_positions_needed = false;
2400
2401 /* Do this first so failing to allocate scratch buffers can't result in
2402 * partially executed submissions. */
2403 for (uint32_t i = 0; i < submitCount; i++) {
2404 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2405 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2406 pSubmits[i].pCommandBuffers[j]);
2407
2408 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2409 compute_scratch_size = MAX2(compute_scratch_size,
2410 cmd_buffer->compute_scratch_size_needed);
2411 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2412 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2413 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2414 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2415 }
2416 }
2417
2418 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2419 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2420 sample_positions_needed, &initial_flush_preamble_cs,
2421 &initial_preamble_cs, &continue_preamble_cs);
2422 if (result != VK_SUCCESS)
2423 return result;
2424
2425 for (uint32_t i = 0; i < submitCount; i++) {
2426 struct radeon_winsys_cs **cs_array;
2427 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2428 bool can_patch = true;
2429 uint32_t advance;
2430 struct radv_winsys_sem_info sem_info;
2431
2432 result = radv_alloc_sem_info(&sem_info,
2433 pSubmits[i].waitSemaphoreCount,
2434 pSubmits[i].pWaitSemaphores,
2435 pSubmits[i].signalSemaphoreCount,
2436 pSubmits[i].pSignalSemaphores,
2437 _fence);
2438 if (result != VK_SUCCESS)
2439 return result;
2440
2441 if (!pSubmits[i].commandBufferCount) {
2442 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2443 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2444 &queue->device->empty_cs[queue->queue_family_index],
2445 1, NULL, NULL,
2446 &sem_info, NULL,
2447 false, base_fence);
2448 if (ret) {
2449 radv_loge("failed to submit CS %d\n", i);
2450 abort();
2451 }
2452 fence_emitted = true;
2453 }
2454 radv_free_sem_info(&sem_info);
2455 continue;
2456 }
2457
2458 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
2459 (pSubmits[i].commandBufferCount));
2460
2461 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2462 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2463 pSubmits[i].pCommandBuffers[j]);
2464 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2465
2466 cs_array[j] = cmd_buffer->cs;
2467 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2468 can_patch = false;
2469
2470 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2471 }
2472
2473 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2474 struct radeon_winsys_cs *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2475 advance = MIN2(max_cs_submission,
2476 pSubmits[i].commandBufferCount - j);
2477
2478 if (queue->device->trace_bo)
2479 *queue->device->trace_id_ptr = 0;
2480
2481 sem_info.cs_emit_wait = j == 0;
2482 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2483
2484 if (unlikely(queue->device->use_global_bo_list))
2485 pthread_mutex_lock(&queue->device->bo_list.mutex);
2486
2487 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2488 advance, initial_preamble, continue_preamble_cs,
2489 &sem_info, &queue->device->bo_list.list,
2490 can_patch, base_fence);
2491
2492 if (unlikely(queue->device->use_global_bo_list))
2493 pthread_mutex_unlock(&queue->device->bo_list.mutex);
2494
2495 if (ret) {
2496 radv_loge("failed to submit CS %d\n", i);
2497 abort();
2498 }
2499 fence_emitted = true;
2500 if (queue->device->trace_bo) {
2501 radv_check_gpu_hangs(queue, cs_array[j]);
2502 }
2503 }
2504
2505 radv_free_temp_syncobjs(queue->device,
2506 pSubmits[i].waitSemaphoreCount,
2507 pSubmits[i].pWaitSemaphores);
2508 radv_free_sem_info(&sem_info);
2509 free(cs_array);
2510 }
2511
2512 if (fence) {
2513 if (!fence_emitted) {
2514 radv_signal_fence(queue, fence);
2515 }
2516 fence->submitted = true;
2517 }
2518
2519 return VK_SUCCESS;
2520 }
2521
2522 VkResult radv_QueueWaitIdle(
2523 VkQueue _queue)
2524 {
2525 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2526
2527 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2528 radv_queue_family_to_ring(queue->queue_family_index),
2529 queue->queue_idx);
2530 return VK_SUCCESS;
2531 }
2532
2533 VkResult radv_DeviceWaitIdle(
2534 VkDevice _device)
2535 {
2536 RADV_FROM_HANDLE(radv_device, device, _device);
2537
2538 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2539 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2540 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2541 }
2542 }
2543 return VK_SUCCESS;
2544 }
2545
2546 VkResult radv_EnumerateInstanceExtensionProperties(
2547 const char* pLayerName,
2548 uint32_t* pPropertyCount,
2549 VkExtensionProperties* pProperties)
2550 {
2551 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2552
2553 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
2554 if (radv_supported_instance_extensions.extensions[i]) {
2555 vk_outarray_append(&out, prop) {
2556 *prop = radv_instance_extensions[i];
2557 }
2558 }
2559 }
2560
2561 return vk_outarray_status(&out);
2562 }
2563
2564 VkResult radv_EnumerateDeviceExtensionProperties(
2565 VkPhysicalDevice physicalDevice,
2566 const char* pLayerName,
2567 uint32_t* pPropertyCount,
2568 VkExtensionProperties* pProperties)
2569 {
2570 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2571 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2572
2573 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
2574 if (device->supported_extensions.extensions[i]) {
2575 vk_outarray_append(&out, prop) {
2576 *prop = radv_device_extensions[i];
2577 }
2578 }
2579 }
2580
2581 return vk_outarray_status(&out);
2582 }
2583
2584 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2585 VkInstance _instance,
2586 const char* pName)
2587 {
2588 RADV_FROM_HANDLE(radv_instance, instance, _instance);
2589
2590 return radv_lookup_entrypoint_checked(pName,
2591 instance ? instance->apiVersion : 0,
2592 instance ? &instance->enabled_extensions : NULL,
2593 NULL);
2594 }
2595
2596 /* The loader wants us to expose a second GetInstanceProcAddr function
2597 * to work around certain LD_PRELOAD issues seen in apps.
2598 */
2599 PUBLIC
2600 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2601 VkInstance instance,
2602 const char* pName);
2603
2604 PUBLIC
2605 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2606 VkInstance instance,
2607 const char* pName)
2608 {
2609 return radv_GetInstanceProcAddr(instance, pName);
2610 }
2611
2612 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2613 VkDevice _device,
2614 const char* pName)
2615 {
2616 RADV_FROM_HANDLE(radv_device, device, _device);
2617
2618 return radv_lookup_entrypoint_checked(pName,
2619 device->instance->apiVersion,
2620 &device->instance->enabled_extensions,
2621 &device->enabled_extensions);
2622 }
2623
2624 bool radv_get_memory_fd(struct radv_device *device,
2625 struct radv_device_memory *memory,
2626 int *pFD)
2627 {
2628 struct radeon_bo_metadata metadata;
2629
2630 if (memory->image) {
2631 radv_init_metadata(device, memory->image, &metadata);
2632 device->ws->buffer_set_metadata(memory->bo, &metadata);
2633 }
2634
2635 return device->ws->buffer_get_fd(device->ws, memory->bo,
2636 pFD);
2637 }
2638
2639 static VkResult radv_alloc_memory(struct radv_device *device,
2640 const VkMemoryAllocateInfo* pAllocateInfo,
2641 const VkAllocationCallbacks* pAllocator,
2642 VkDeviceMemory* pMem)
2643 {
2644 struct radv_device_memory *mem;
2645 VkResult result;
2646 enum radeon_bo_domain domain;
2647 uint32_t flags = 0;
2648 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
2649
2650 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2651
2652 if (pAllocateInfo->allocationSize == 0) {
2653 /* Apparently, this is allowed */
2654 *pMem = VK_NULL_HANDLE;
2655 return VK_SUCCESS;
2656 }
2657
2658 const VkImportMemoryFdInfoKHR *import_info =
2659 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2660 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2661 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2662 const VkExportMemoryAllocateInfoKHR *export_info =
2663 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO_KHR);
2664 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
2665 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
2666
2667 const struct wsi_memory_allocate_info *wsi_info =
2668 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
2669
2670 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2671 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2672 if (mem == NULL)
2673 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2674
2675 if (wsi_info && wsi_info->implicit_sync)
2676 flags |= RADEON_FLAG_IMPLICIT_SYNC;
2677
2678 if (dedicate_info) {
2679 mem->image = radv_image_from_handle(dedicate_info->image);
2680 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2681 } else {
2682 mem->image = NULL;
2683 mem->buffer = NULL;
2684 }
2685
2686 mem->user_ptr = NULL;
2687
2688 if (import_info) {
2689 assert(import_info->handleType ==
2690 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
2691 import_info->handleType ==
2692 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
2693 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2694 NULL, NULL);
2695 if (!mem->bo) {
2696 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2697 goto fail;
2698 } else {
2699 close(import_info->fd);
2700 }
2701 } else if (host_ptr_info) {
2702 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
2703 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
2704 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
2705 pAllocateInfo->allocationSize);
2706 if (!mem->bo) {
2707 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2708 goto fail;
2709 } else {
2710 mem->user_ptr = host_ptr_info->pHostPointer;
2711 }
2712 } else {
2713 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2714 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2715 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
2716 domain = RADEON_DOMAIN_GTT;
2717 else
2718 domain = RADEON_DOMAIN_VRAM;
2719
2720 if (mem_type_index == RADV_MEM_TYPE_VRAM)
2721 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2722 else
2723 flags |= RADEON_FLAG_CPU_ACCESS;
2724
2725 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2726 flags |= RADEON_FLAG_GTT_WC;
2727
2728 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
2729 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
2730
2731 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2732 domain, flags);
2733
2734 if (!mem->bo) {
2735 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2736 goto fail;
2737 }
2738 mem->type_index = mem_type_index;
2739 }
2740
2741 result = radv_bo_list_add(device, mem->bo);
2742 if (result != VK_SUCCESS)
2743 goto fail_bo;
2744
2745 *pMem = radv_device_memory_to_handle(mem);
2746
2747 return VK_SUCCESS;
2748
2749 fail_bo:
2750 device->ws->buffer_destroy(mem->bo);
2751 fail:
2752 vk_free2(&device->alloc, pAllocator, mem);
2753
2754 return result;
2755 }
2756
2757 VkResult radv_AllocateMemory(
2758 VkDevice _device,
2759 const VkMemoryAllocateInfo* pAllocateInfo,
2760 const VkAllocationCallbacks* pAllocator,
2761 VkDeviceMemory* pMem)
2762 {
2763 RADV_FROM_HANDLE(radv_device, device, _device);
2764 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
2765 }
2766
2767 void radv_FreeMemory(
2768 VkDevice _device,
2769 VkDeviceMemory _mem,
2770 const VkAllocationCallbacks* pAllocator)
2771 {
2772 RADV_FROM_HANDLE(radv_device, device, _device);
2773 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2774
2775 if (mem == NULL)
2776 return;
2777
2778 radv_bo_list_remove(device, mem->bo);
2779 device->ws->buffer_destroy(mem->bo);
2780 mem->bo = NULL;
2781
2782 vk_free2(&device->alloc, pAllocator, mem);
2783 }
2784
2785 VkResult radv_MapMemory(
2786 VkDevice _device,
2787 VkDeviceMemory _memory,
2788 VkDeviceSize offset,
2789 VkDeviceSize size,
2790 VkMemoryMapFlags flags,
2791 void** ppData)
2792 {
2793 RADV_FROM_HANDLE(radv_device, device, _device);
2794 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2795
2796 if (mem == NULL) {
2797 *ppData = NULL;
2798 return VK_SUCCESS;
2799 }
2800
2801 if (mem->user_ptr)
2802 *ppData = mem->user_ptr;
2803 else
2804 *ppData = device->ws->buffer_map(mem->bo);
2805
2806 if (*ppData) {
2807 *ppData += offset;
2808 return VK_SUCCESS;
2809 }
2810
2811 return vk_error(VK_ERROR_MEMORY_MAP_FAILED);
2812 }
2813
2814 void radv_UnmapMemory(
2815 VkDevice _device,
2816 VkDeviceMemory _memory)
2817 {
2818 RADV_FROM_HANDLE(radv_device, device, _device);
2819 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2820
2821 if (mem == NULL)
2822 return;
2823
2824 if (mem->user_ptr == NULL)
2825 device->ws->buffer_unmap(mem->bo);
2826 }
2827
2828 VkResult radv_FlushMappedMemoryRanges(
2829 VkDevice _device,
2830 uint32_t memoryRangeCount,
2831 const VkMappedMemoryRange* pMemoryRanges)
2832 {
2833 return VK_SUCCESS;
2834 }
2835
2836 VkResult radv_InvalidateMappedMemoryRanges(
2837 VkDevice _device,
2838 uint32_t memoryRangeCount,
2839 const VkMappedMemoryRange* pMemoryRanges)
2840 {
2841 return VK_SUCCESS;
2842 }
2843
2844 void radv_GetBufferMemoryRequirements(
2845 VkDevice _device,
2846 VkBuffer _buffer,
2847 VkMemoryRequirements* pMemoryRequirements)
2848 {
2849 RADV_FROM_HANDLE(radv_device, device, _device);
2850 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2851
2852 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2853
2854 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2855 pMemoryRequirements->alignment = 4096;
2856 else
2857 pMemoryRequirements->alignment = 16;
2858
2859 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2860 }
2861
2862 void radv_GetBufferMemoryRequirements2(
2863 VkDevice device,
2864 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2865 VkMemoryRequirements2KHR* pMemoryRequirements)
2866 {
2867 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2868 &pMemoryRequirements->memoryRequirements);
2869 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
2870 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2871 switch (ext->sType) {
2872 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2873 VkMemoryDedicatedRequirementsKHR *req =
2874 (VkMemoryDedicatedRequirementsKHR *) ext;
2875 req->requiresDedicatedAllocation = buffer->shareable;
2876 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2877 break;
2878 }
2879 default:
2880 break;
2881 }
2882 }
2883 }
2884
2885 void radv_GetImageMemoryRequirements(
2886 VkDevice _device,
2887 VkImage _image,
2888 VkMemoryRequirements* pMemoryRequirements)
2889 {
2890 RADV_FROM_HANDLE(radv_device, device, _device);
2891 RADV_FROM_HANDLE(radv_image, image, _image);
2892
2893 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2894
2895 pMemoryRequirements->size = image->size;
2896 pMemoryRequirements->alignment = image->alignment;
2897 }
2898
2899 void radv_GetImageMemoryRequirements2(
2900 VkDevice device,
2901 const VkImageMemoryRequirementsInfo2KHR* pInfo,
2902 VkMemoryRequirements2KHR* pMemoryRequirements)
2903 {
2904 radv_GetImageMemoryRequirements(device, pInfo->image,
2905 &pMemoryRequirements->memoryRequirements);
2906
2907 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
2908
2909 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2910 switch (ext->sType) {
2911 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2912 VkMemoryDedicatedRequirementsKHR *req =
2913 (VkMemoryDedicatedRequirementsKHR *) ext;
2914 req->requiresDedicatedAllocation = image->shareable;
2915 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2916 break;
2917 }
2918 default:
2919 break;
2920 }
2921 }
2922 }
2923
2924 void radv_GetImageSparseMemoryRequirements(
2925 VkDevice device,
2926 VkImage image,
2927 uint32_t* pSparseMemoryRequirementCount,
2928 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2929 {
2930 stub();
2931 }
2932
2933 void radv_GetImageSparseMemoryRequirements2(
2934 VkDevice device,
2935 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
2936 uint32_t* pSparseMemoryRequirementCount,
2937 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
2938 {
2939 stub();
2940 }
2941
2942 void radv_GetDeviceMemoryCommitment(
2943 VkDevice device,
2944 VkDeviceMemory memory,
2945 VkDeviceSize* pCommittedMemoryInBytes)
2946 {
2947 *pCommittedMemoryInBytes = 0;
2948 }
2949
2950 VkResult radv_BindBufferMemory2(VkDevice device,
2951 uint32_t bindInfoCount,
2952 const VkBindBufferMemoryInfoKHR *pBindInfos)
2953 {
2954 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2955 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2956 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
2957
2958 if (mem) {
2959 buffer->bo = mem->bo;
2960 buffer->offset = pBindInfos[i].memoryOffset;
2961 } else {
2962 buffer->bo = NULL;
2963 }
2964 }
2965 return VK_SUCCESS;
2966 }
2967
2968 VkResult radv_BindBufferMemory(
2969 VkDevice device,
2970 VkBuffer buffer,
2971 VkDeviceMemory memory,
2972 VkDeviceSize memoryOffset)
2973 {
2974 const VkBindBufferMemoryInfoKHR info = {
2975 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2976 .buffer = buffer,
2977 .memory = memory,
2978 .memoryOffset = memoryOffset
2979 };
2980
2981 return radv_BindBufferMemory2(device, 1, &info);
2982 }
2983
2984 VkResult radv_BindImageMemory2(VkDevice device,
2985 uint32_t bindInfoCount,
2986 const VkBindImageMemoryInfoKHR *pBindInfos)
2987 {
2988 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2989 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2990 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
2991
2992 if (mem) {
2993 image->bo = mem->bo;
2994 image->offset = pBindInfos[i].memoryOffset;
2995 } else {
2996 image->bo = NULL;
2997 image->offset = 0;
2998 }
2999 }
3000 return VK_SUCCESS;
3001 }
3002
3003
3004 VkResult radv_BindImageMemory(
3005 VkDevice device,
3006 VkImage image,
3007 VkDeviceMemory memory,
3008 VkDeviceSize memoryOffset)
3009 {
3010 const VkBindImageMemoryInfoKHR info = {
3011 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3012 .image = image,
3013 .memory = memory,
3014 .memoryOffset = memoryOffset
3015 };
3016
3017 return radv_BindImageMemory2(device, 1, &info);
3018 }
3019
3020
3021 static void
3022 radv_sparse_buffer_bind_memory(struct radv_device *device,
3023 const VkSparseBufferMemoryBindInfo *bind)
3024 {
3025 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3026
3027 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3028 struct radv_device_memory *mem = NULL;
3029
3030 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3031 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3032
3033 device->ws->buffer_virtual_bind(buffer->bo,
3034 bind->pBinds[i].resourceOffset,
3035 bind->pBinds[i].size,
3036 mem ? mem->bo : NULL,
3037 bind->pBinds[i].memoryOffset);
3038 }
3039 }
3040
3041 static void
3042 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3043 const VkSparseImageOpaqueMemoryBindInfo *bind)
3044 {
3045 RADV_FROM_HANDLE(radv_image, image, bind->image);
3046
3047 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3048 struct radv_device_memory *mem = NULL;
3049
3050 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3051 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3052
3053 device->ws->buffer_virtual_bind(image->bo,
3054 bind->pBinds[i].resourceOffset,
3055 bind->pBinds[i].size,
3056 mem ? mem->bo : NULL,
3057 bind->pBinds[i].memoryOffset);
3058 }
3059 }
3060
3061 VkResult radv_QueueBindSparse(
3062 VkQueue _queue,
3063 uint32_t bindInfoCount,
3064 const VkBindSparseInfo* pBindInfo,
3065 VkFence _fence)
3066 {
3067 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3068 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3069 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3070 bool fence_emitted = false;
3071
3072 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3073 struct radv_winsys_sem_info sem_info;
3074 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3075 radv_sparse_buffer_bind_memory(queue->device,
3076 pBindInfo[i].pBufferBinds + j);
3077 }
3078
3079 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3080 radv_sparse_image_opaque_bind_memory(queue->device,
3081 pBindInfo[i].pImageOpaqueBinds + j);
3082 }
3083
3084 VkResult result;
3085 result = radv_alloc_sem_info(&sem_info,
3086 pBindInfo[i].waitSemaphoreCount,
3087 pBindInfo[i].pWaitSemaphores,
3088 pBindInfo[i].signalSemaphoreCount,
3089 pBindInfo[i].pSignalSemaphores,
3090 _fence);
3091 if (result != VK_SUCCESS)
3092 return result;
3093
3094 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3095 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3096 &queue->device->empty_cs[queue->queue_family_index],
3097 1, NULL, NULL,
3098 &sem_info, NULL,
3099 false, base_fence);
3100 fence_emitted = true;
3101 if (fence)
3102 fence->submitted = true;
3103 }
3104
3105 radv_free_sem_info(&sem_info);
3106
3107 }
3108
3109 if (fence) {
3110 if (!fence_emitted) {
3111 radv_signal_fence(queue, fence);
3112 }
3113 fence->submitted = true;
3114 }
3115
3116 return VK_SUCCESS;
3117 }
3118
3119 VkResult radv_CreateFence(
3120 VkDevice _device,
3121 const VkFenceCreateInfo* pCreateInfo,
3122 const VkAllocationCallbacks* pAllocator,
3123 VkFence* pFence)
3124 {
3125 RADV_FROM_HANDLE(radv_device, device, _device);
3126 const VkExportFenceCreateInfoKHR *export =
3127 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO_KHR);
3128 VkExternalFenceHandleTypeFlagsKHR handleTypes =
3129 export ? export->handleTypes : 0;
3130
3131 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3132 sizeof(*fence), 8,
3133 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3134
3135 if (!fence)
3136 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3137
3138 fence->submitted = false;
3139 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3140 fence->temp_syncobj = 0;
3141 if (device->always_use_syncobj || handleTypes) {
3142 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3143 if (ret) {
3144 vk_free2(&device->alloc, pAllocator, fence);
3145 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3146 }
3147 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3148 device->ws->signal_syncobj(device->ws, fence->syncobj);
3149 }
3150 fence->fence = NULL;
3151 } else {
3152 fence->fence = device->ws->create_fence();
3153 if (!fence->fence) {
3154 vk_free2(&device->alloc, pAllocator, fence);
3155 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3156 }
3157 fence->syncobj = 0;
3158 }
3159
3160 *pFence = radv_fence_to_handle(fence);
3161
3162 return VK_SUCCESS;
3163 }
3164
3165 void radv_DestroyFence(
3166 VkDevice _device,
3167 VkFence _fence,
3168 const VkAllocationCallbacks* pAllocator)
3169 {
3170 RADV_FROM_HANDLE(radv_device, device, _device);
3171 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3172
3173 if (!fence)
3174 return;
3175
3176 if (fence->temp_syncobj)
3177 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3178 if (fence->syncobj)
3179 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3180 if (fence->fence)
3181 device->ws->destroy_fence(fence->fence);
3182 vk_free2(&device->alloc, pAllocator, fence);
3183 }
3184
3185
3186 static uint64_t radv_get_current_time()
3187 {
3188 struct timespec tv;
3189 clock_gettime(CLOCK_MONOTONIC, &tv);
3190 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3191 }
3192
3193 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3194 {
3195 uint64_t current_time = radv_get_current_time();
3196
3197 timeout = MIN2(UINT64_MAX - current_time, timeout);
3198
3199 return current_time + timeout;
3200 }
3201
3202
3203 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3204 {
3205 for (uint32_t i = 0; i < fenceCount; ++i) {
3206 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3207 if (fence->syncobj || fence->temp_syncobj || (!fence->signalled && !fence->submitted))
3208 return false;
3209 }
3210 return true;
3211 }
3212
3213 VkResult radv_WaitForFences(
3214 VkDevice _device,
3215 uint32_t fenceCount,
3216 const VkFence* pFences,
3217 VkBool32 waitAll,
3218 uint64_t timeout)
3219 {
3220 RADV_FROM_HANDLE(radv_device, device, _device);
3221 timeout = radv_get_absolute_timeout(timeout);
3222
3223 if (device->always_use_syncobj) {
3224 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3225 if (!handles)
3226 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3227
3228 for (uint32_t i = 0; i < fenceCount; ++i) {
3229 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3230 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3231 }
3232
3233 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3234
3235 free(handles);
3236 return success ? VK_SUCCESS : VK_TIMEOUT;
3237 }
3238
3239 if (!waitAll && fenceCount > 1) {
3240 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3241 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3242 uint32_t wait_count = 0;
3243 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3244 if (!fences)
3245 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3246
3247 for (uint32_t i = 0; i < fenceCount; ++i) {
3248 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3249
3250 if (fence->signalled) {
3251 free(fences);
3252 return VK_SUCCESS;
3253 }
3254
3255 fences[wait_count++] = fence->fence;
3256 }
3257
3258 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3259 waitAll, timeout - radv_get_current_time());
3260
3261 free(fences);
3262 return success ? VK_SUCCESS : VK_TIMEOUT;
3263 }
3264
3265 while(radv_get_current_time() <= timeout) {
3266 for (uint32_t i = 0; i < fenceCount; ++i) {
3267 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3268 return VK_SUCCESS;
3269 }
3270 }
3271 return VK_TIMEOUT;
3272 }
3273
3274 for (uint32_t i = 0; i < fenceCount; ++i) {
3275 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3276 bool expired = false;
3277
3278 if (fence->temp_syncobj) {
3279 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3280 return VK_TIMEOUT;
3281 continue;
3282 }
3283
3284 if (fence->syncobj) {
3285 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3286 return VK_TIMEOUT;
3287 continue;
3288 }
3289
3290 if (fence->signalled)
3291 continue;
3292
3293 if (!fence->submitted) {
3294 while(radv_get_current_time() <= timeout && !fence->submitted)
3295 /* Do nothing */;
3296
3297 if (!fence->submitted)
3298 return VK_TIMEOUT;
3299
3300 /* Recheck as it may have been set by submitting operations. */
3301 if (fence->signalled)
3302 continue;
3303 }
3304
3305 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
3306 if (!expired)
3307 return VK_TIMEOUT;
3308
3309 fence->signalled = true;
3310 }
3311
3312 return VK_SUCCESS;
3313 }
3314
3315 VkResult radv_ResetFences(VkDevice _device,
3316 uint32_t fenceCount,
3317 const VkFence *pFences)
3318 {
3319 RADV_FROM_HANDLE(radv_device, device, _device);
3320
3321 for (unsigned i = 0; i < fenceCount; ++i) {
3322 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3323 fence->submitted = fence->signalled = false;
3324
3325 /* Per spec, we first restore the permanent payload, and then reset, so
3326 * having a temp syncobj should not skip resetting the permanent syncobj. */
3327 if (fence->temp_syncobj) {
3328 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3329 fence->temp_syncobj = 0;
3330 }
3331
3332 if (fence->syncobj) {
3333 device->ws->reset_syncobj(device->ws, fence->syncobj);
3334 }
3335 }
3336
3337 return VK_SUCCESS;
3338 }
3339
3340 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3341 {
3342 RADV_FROM_HANDLE(radv_device, device, _device);
3343 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3344
3345 if (fence->temp_syncobj) {
3346 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3347 return success ? VK_SUCCESS : VK_NOT_READY;
3348 }
3349
3350 if (fence->syncobj) {
3351 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3352 return success ? VK_SUCCESS : VK_NOT_READY;
3353 }
3354
3355 if (fence->signalled)
3356 return VK_SUCCESS;
3357 if (!fence->submitted)
3358 return VK_NOT_READY;
3359 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3360 return VK_NOT_READY;
3361
3362 return VK_SUCCESS;
3363 }
3364
3365
3366 // Queue semaphore functions
3367
3368 VkResult radv_CreateSemaphore(
3369 VkDevice _device,
3370 const VkSemaphoreCreateInfo* pCreateInfo,
3371 const VkAllocationCallbacks* pAllocator,
3372 VkSemaphore* pSemaphore)
3373 {
3374 RADV_FROM_HANDLE(radv_device, device, _device);
3375 const VkExportSemaphoreCreateInfoKHR *export =
3376 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
3377 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
3378 export ? export->handleTypes : 0;
3379
3380 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3381 sizeof(*sem), 8,
3382 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3383 if (!sem)
3384 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3385
3386 sem->temp_syncobj = 0;
3387 /* create a syncobject if we are going to export this semaphore */
3388 if (device->always_use_syncobj || handleTypes) {
3389 assert (device->physical_device->rad_info.has_syncobj);
3390 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3391 if (ret) {
3392 vk_free2(&device->alloc, pAllocator, sem);
3393 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3394 }
3395 sem->sem = NULL;
3396 } else {
3397 sem->sem = device->ws->create_sem(device->ws);
3398 if (!sem->sem) {
3399 vk_free2(&device->alloc, pAllocator, sem);
3400 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3401 }
3402 sem->syncobj = 0;
3403 }
3404
3405 *pSemaphore = radv_semaphore_to_handle(sem);
3406 return VK_SUCCESS;
3407 }
3408
3409 void radv_DestroySemaphore(
3410 VkDevice _device,
3411 VkSemaphore _semaphore,
3412 const VkAllocationCallbacks* pAllocator)
3413 {
3414 RADV_FROM_HANDLE(radv_device, device, _device);
3415 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3416 if (!_semaphore)
3417 return;
3418
3419 if (sem->syncobj)
3420 device->ws->destroy_syncobj(device->ws, sem->syncobj);
3421 else
3422 device->ws->destroy_sem(sem->sem);
3423 vk_free2(&device->alloc, pAllocator, sem);
3424 }
3425
3426 VkResult radv_CreateEvent(
3427 VkDevice _device,
3428 const VkEventCreateInfo* pCreateInfo,
3429 const VkAllocationCallbacks* pAllocator,
3430 VkEvent* pEvent)
3431 {
3432 RADV_FROM_HANDLE(radv_device, device, _device);
3433 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
3434 sizeof(*event), 8,
3435 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3436
3437 if (!event)
3438 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3439
3440 event->bo = device->ws->buffer_create(device->ws, 8, 8,
3441 RADEON_DOMAIN_GTT,
3442 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
3443 if (!event->bo) {
3444 vk_free2(&device->alloc, pAllocator, event);
3445 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
3446 }
3447
3448 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
3449
3450 *pEvent = radv_event_to_handle(event);
3451
3452 return VK_SUCCESS;
3453 }
3454
3455 void radv_DestroyEvent(
3456 VkDevice _device,
3457 VkEvent _event,
3458 const VkAllocationCallbacks* pAllocator)
3459 {
3460 RADV_FROM_HANDLE(radv_device, device, _device);
3461 RADV_FROM_HANDLE(radv_event, event, _event);
3462
3463 if (!event)
3464 return;
3465 device->ws->buffer_destroy(event->bo);
3466 vk_free2(&device->alloc, pAllocator, event);
3467 }
3468
3469 VkResult radv_GetEventStatus(
3470 VkDevice _device,
3471 VkEvent _event)
3472 {
3473 RADV_FROM_HANDLE(radv_event, event, _event);
3474
3475 if (*event->map == 1)
3476 return VK_EVENT_SET;
3477 return VK_EVENT_RESET;
3478 }
3479
3480 VkResult radv_SetEvent(
3481 VkDevice _device,
3482 VkEvent _event)
3483 {
3484 RADV_FROM_HANDLE(radv_event, event, _event);
3485 *event->map = 1;
3486
3487 return VK_SUCCESS;
3488 }
3489
3490 VkResult radv_ResetEvent(
3491 VkDevice _device,
3492 VkEvent _event)
3493 {
3494 RADV_FROM_HANDLE(radv_event, event, _event);
3495 *event->map = 0;
3496
3497 return VK_SUCCESS;
3498 }
3499
3500 VkResult radv_CreateBuffer(
3501 VkDevice _device,
3502 const VkBufferCreateInfo* pCreateInfo,
3503 const VkAllocationCallbacks* pAllocator,
3504 VkBuffer* pBuffer)
3505 {
3506 RADV_FROM_HANDLE(radv_device, device, _device);
3507 struct radv_buffer *buffer;
3508
3509 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
3510
3511 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
3512 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3513 if (buffer == NULL)
3514 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3515
3516 buffer->size = pCreateInfo->size;
3517 buffer->usage = pCreateInfo->usage;
3518 buffer->bo = NULL;
3519 buffer->offset = 0;
3520 buffer->flags = pCreateInfo->flags;
3521
3522 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
3523 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR) != NULL;
3524
3525 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
3526 buffer->bo = device->ws->buffer_create(device->ws,
3527 align64(buffer->size, 4096),
3528 4096, 0, RADEON_FLAG_VIRTUAL);
3529 if (!buffer->bo) {
3530 vk_free2(&device->alloc, pAllocator, buffer);
3531 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
3532 }
3533 }
3534
3535 *pBuffer = radv_buffer_to_handle(buffer);
3536
3537 return VK_SUCCESS;
3538 }
3539
3540 void radv_DestroyBuffer(
3541 VkDevice _device,
3542 VkBuffer _buffer,
3543 const VkAllocationCallbacks* pAllocator)
3544 {
3545 RADV_FROM_HANDLE(radv_device, device, _device);
3546 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3547
3548 if (!buffer)
3549 return;
3550
3551 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3552 device->ws->buffer_destroy(buffer->bo);
3553
3554 vk_free2(&device->alloc, pAllocator, buffer);
3555 }
3556
3557 static inline unsigned
3558 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
3559 {
3560 if (stencil)
3561 return image->surface.u.legacy.stencil_tiling_index[level];
3562 else
3563 return image->surface.u.legacy.tiling_index[level];
3564 }
3565
3566 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
3567 {
3568 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
3569 }
3570
3571 static uint32_t
3572 radv_init_dcc_control_reg(struct radv_device *device,
3573 struct radv_image_view *iview)
3574 {
3575 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
3576 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
3577 unsigned max_compressed_block_size;
3578 unsigned independent_64b_blocks;
3579
3580 if (device->physical_device->rad_info.chip_class < VI)
3581 return 0;
3582
3583 if (iview->image->info.samples > 1) {
3584 if (iview->image->surface.bpe == 1)
3585 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3586 else if (iview->image->surface.bpe == 2)
3587 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
3588 }
3589
3590 if (!device->physical_device->rad_info.has_dedicated_vram) {
3591 /* amdvlk: [min-compressed-block-size] should be set to 32 for
3592 * dGPU and 64 for APU because all of our APUs to date use
3593 * DIMMs which have a request granularity size of 64B while all
3594 * other chips have a 32B request size.
3595 */
3596 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
3597 }
3598
3599 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
3600 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
3601 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
3602 /* If this DCC image is potentially going to be used in texture
3603 * fetches, we need some special settings.
3604 */
3605 independent_64b_blocks = 1;
3606 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3607 } else {
3608 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
3609 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
3610 * big as possible for better compression state.
3611 */
3612 independent_64b_blocks = 0;
3613 max_compressed_block_size = max_uncompressed_block_size;
3614 }
3615
3616 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3617 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
3618 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
3619 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
3620 }
3621
3622 static void
3623 radv_initialise_color_surface(struct radv_device *device,
3624 struct radv_color_buffer_info *cb,
3625 struct radv_image_view *iview)
3626 {
3627 const struct vk_format_description *desc;
3628 unsigned ntype, format, swap, endian;
3629 unsigned blend_clamp = 0, blend_bypass = 0;
3630 uint64_t va;
3631 const struct radeon_surf *surf = &iview->image->surface;
3632
3633 desc = vk_format_description(iview->vk_format);
3634
3635 memset(cb, 0, sizeof(*cb));
3636
3637 /* Intensity is implemented as Red, so treat it that way. */
3638 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
3639
3640 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3641
3642 cb->cb_color_base = va >> 8;
3643
3644 if (device->physical_device->rad_info.chip_class >= GFX9) {
3645 struct gfx9_surf_meta_flags meta;
3646 if (iview->image->dcc_offset)
3647 meta = iview->image->surface.u.gfx9.dcc;
3648 else
3649 meta = iview->image->surface.u.gfx9.cmask;
3650
3651 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3652 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
3653 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3654 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3655
3656 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
3657 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3658 } else {
3659 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
3660 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3661
3662 cb->cb_color_base += level_info->offset >> 8;
3663 if (level_info->mode == RADEON_SURF_MODE_2D)
3664 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3665
3666 pitch_tile_max = level_info->nblk_x / 8 - 1;
3667 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
3668 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
3669
3670 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3671 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3672 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
3673
3674 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3675
3676 if (radv_image_has_fmask(iview->image)) {
3677 if (device->physical_device->rad_info.chip_class >= CIK)
3678 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
3679 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
3680 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
3681 } else {
3682 /* This must be set for fast clear to work without FMASK. */
3683 if (device->physical_device->rad_info.chip_class >= CIK)
3684 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3685 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3686 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3687 }
3688 }
3689
3690 /* CMASK variables */
3691 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3692 va += iview->image->cmask.offset;
3693 cb->cb_color_cmask = va >> 8;
3694
3695 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3696 va += iview->image->dcc_offset;
3697 cb->cb_dcc_base = va >> 8;
3698 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
3699
3700 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3701 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3702 S_028C6C_SLICE_MAX(max_slice);
3703
3704 if (iview->image->info.samples > 1) {
3705 unsigned log_samples = util_logbase2(iview->image->info.samples);
3706
3707 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3708 S_028C74_NUM_FRAGMENTS(log_samples);
3709 }
3710
3711 if (radv_image_has_fmask(iview->image)) {
3712 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3713 cb->cb_color_fmask = va >> 8;
3714 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3715 } else {
3716 cb->cb_color_fmask = cb->cb_color_base;
3717 }
3718
3719 ntype = radv_translate_color_numformat(iview->vk_format,
3720 desc,
3721 vk_format_get_first_non_void_channel(iview->vk_format));
3722 format = radv_translate_colorformat(iview->vk_format);
3723 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3724 radv_finishme("Illegal color\n");
3725 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3726 endian = radv_colorformat_endian_swap(format);
3727
3728 /* blend clamp should be set for all NORM/SRGB types */
3729 if (ntype == V_028C70_NUMBER_UNORM ||
3730 ntype == V_028C70_NUMBER_SNORM ||
3731 ntype == V_028C70_NUMBER_SRGB)
3732 blend_clamp = 1;
3733
3734 /* set blend bypass according to docs if SINT/UINT or
3735 8/24 COLOR variants */
3736 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3737 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3738 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3739 blend_clamp = 0;
3740 blend_bypass = 1;
3741 }
3742 #if 0
3743 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3744 (format == V_028C70_COLOR_8 ||
3745 format == V_028C70_COLOR_8_8 ||
3746 format == V_028C70_COLOR_8_8_8_8))
3747 ->color_is_int8 = true;
3748 #endif
3749 cb->cb_color_info = S_028C70_FORMAT(format) |
3750 S_028C70_COMP_SWAP(swap) |
3751 S_028C70_BLEND_CLAMP(blend_clamp) |
3752 S_028C70_BLEND_BYPASS(blend_bypass) |
3753 S_028C70_SIMPLE_FLOAT(1) |
3754 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3755 ntype != V_028C70_NUMBER_SNORM &&
3756 ntype != V_028C70_NUMBER_SRGB &&
3757 format != V_028C70_COLOR_8_24 &&
3758 format != V_028C70_COLOR_24_8) |
3759 S_028C70_NUMBER_TYPE(ntype) |
3760 S_028C70_ENDIAN(endian);
3761 if (radv_image_has_fmask(iview->image)) {
3762 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3763 if (device->physical_device->rad_info.chip_class == SI) {
3764 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3765 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3766 }
3767 }
3768
3769 if (radv_image_has_cmask(iview->image) &&
3770 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3771 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3772
3773 if (radv_dcc_enabled(iview->image, iview->base_mip))
3774 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3775
3776 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
3777
3778 /* This must be set for fast clear to work without FMASK. */
3779 if (!radv_image_has_fmask(iview->image) &&
3780 device->physical_device->rad_info.chip_class == SI) {
3781 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3782 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3783 }
3784
3785 if (device->physical_device->rad_info.chip_class >= GFX9) {
3786 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
3787 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
3788
3789 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3790 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3791 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3792 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
3793 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
3794 S_028C68_MAX_MIP(iview->image->info.levels - 1);
3795 }
3796 }
3797
3798 static unsigned
3799 radv_calc_decompress_on_z_planes(struct radv_device *device,
3800 struct radv_image_view *iview)
3801 {
3802 unsigned max_zplanes = 0;
3803
3804 assert(radv_image_is_tc_compat_htile(iview->image));
3805
3806 if (device->physical_device->rad_info.chip_class >= GFX9) {
3807 /* Default value for 32-bit depth surfaces. */
3808 max_zplanes = 4;
3809
3810 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
3811 iview->image->info.samples > 1)
3812 max_zplanes = 2;
3813
3814 max_zplanes = max_zplanes + 1;
3815 } else {
3816 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
3817 /* Do not enable Z plane compression for 16-bit depth
3818 * surfaces because isn't supported on GFX8. Only
3819 * 32-bit depth surfaces are supported by the hardware.
3820 * This allows to maintain shader compatibility and to
3821 * reduce the number of depth decompressions.
3822 */
3823 max_zplanes = 1;
3824 } else {
3825 if (iview->image->info.samples <= 1)
3826 max_zplanes = 5;
3827 else if (iview->image->info.samples <= 4)
3828 max_zplanes = 3;
3829 else
3830 max_zplanes = 2;
3831 }
3832 }
3833
3834 return max_zplanes;
3835 }
3836
3837 static void
3838 radv_initialise_ds_surface(struct radv_device *device,
3839 struct radv_ds_buffer_info *ds,
3840 struct radv_image_view *iview)
3841 {
3842 unsigned level = iview->base_mip;
3843 unsigned format, stencil_format;
3844 uint64_t va, s_offs, z_offs;
3845 bool stencil_only = false;
3846 memset(ds, 0, sizeof(*ds));
3847 switch (iview->image->vk_format) {
3848 case VK_FORMAT_D24_UNORM_S8_UINT:
3849 case VK_FORMAT_X8_D24_UNORM_PACK32:
3850 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3851 ds->offset_scale = 2.0f;
3852 break;
3853 case VK_FORMAT_D16_UNORM:
3854 case VK_FORMAT_D16_UNORM_S8_UINT:
3855 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3856 ds->offset_scale = 4.0f;
3857 break;
3858 case VK_FORMAT_D32_SFLOAT:
3859 case VK_FORMAT_D32_SFLOAT_S8_UINT:
3860 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3861 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3862 ds->offset_scale = 1.0f;
3863 break;
3864 case VK_FORMAT_S8_UINT:
3865 stencil_only = true;
3866 break;
3867 default:
3868 break;
3869 }
3870
3871 format = radv_translate_dbformat(iview->image->vk_format);
3872 stencil_format = iview->image->surface.has_stencil ?
3873 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
3874
3875 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3876 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
3877 S_028008_SLICE_MAX(max_slice);
3878
3879 ds->db_htile_data_base = 0;
3880 ds->db_htile_surface = 0;
3881
3882 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3883 s_offs = z_offs = va;
3884
3885 if (device->physical_device->rad_info.chip_class >= GFX9) {
3886 assert(iview->image->surface.u.gfx9.surf_offset == 0);
3887 s_offs += iview->image->surface.u.gfx9.stencil_offset;
3888
3889 ds->db_z_info = S_028038_FORMAT(format) |
3890 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
3891 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3892 S_028038_MAXMIP(iview->image->info.levels - 1);
3893 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
3894 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
3895
3896 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3897 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
3898 ds->db_depth_view |= S_028008_MIPID(level);
3899
3900 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
3901 S_02801C_Y_MAX(iview->image->info.height - 1);
3902
3903 if (radv_htile_enabled(iview->image, level)) {
3904 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
3905
3906 if (radv_image_is_tc_compat_htile(iview->image)) {
3907 unsigned max_zplanes =
3908 radv_calc_decompress_on_z_planes(device, iview);
3909
3910 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
3911 S_028038_ITERATE_FLUSH(1);
3912 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
3913 }
3914
3915 if (!iview->image->surface.has_stencil)
3916 /* Use all of the htile_buffer for depth if there's no stencil. */
3917 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
3918 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3919 iview->image->htile_offset;
3920 ds->db_htile_data_base = va >> 8;
3921 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
3922 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
3923 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
3924 }
3925 } else {
3926 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
3927
3928 if (stencil_only)
3929 level_info = &iview->image->surface.u.legacy.stencil_level[level];
3930
3931 z_offs += iview->image->surface.u.legacy.level[level].offset;
3932 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
3933
3934 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
3935 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
3936 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
3937
3938 if (iview->image->info.samples > 1)
3939 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
3940
3941 if (device->physical_device->rad_info.chip_class >= CIK) {
3942 struct radeon_info *info = &device->physical_device->rad_info;
3943 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
3944 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
3945 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
3946 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
3947 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
3948 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
3949
3950 if (stencil_only)
3951 tile_mode = stencil_tile_mode;
3952
3953 ds->db_depth_info |=
3954 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
3955 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
3956 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
3957 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
3958 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
3959 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
3960 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
3961 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
3962 } else {
3963 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
3964 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3965 tile_mode_index = si_tile_mode_index(iview->image, level, true);
3966 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
3967 if (stencil_only)
3968 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3969 }
3970
3971 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
3972 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
3973 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
3974
3975 if (radv_htile_enabled(iview->image, level)) {
3976 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
3977
3978 if (!iview->image->surface.has_stencil &&
3979 !radv_image_is_tc_compat_htile(iview->image))
3980 /* Use all of the htile_buffer for depth if there's no stencil. */
3981 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
3982
3983 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3984 iview->image->htile_offset;
3985 ds->db_htile_data_base = va >> 8;
3986 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
3987
3988 if (radv_image_is_tc_compat_htile(iview->image)) {
3989 unsigned max_zplanes =
3990 radv_calc_decompress_on_z_planes(device, iview);
3991
3992 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
3993 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
3994 }
3995 }
3996 }
3997
3998 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
3999 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4000 }
4001
4002 VkResult radv_CreateFramebuffer(
4003 VkDevice _device,
4004 const VkFramebufferCreateInfo* pCreateInfo,
4005 const VkAllocationCallbacks* pAllocator,
4006 VkFramebuffer* pFramebuffer)
4007 {
4008 RADV_FROM_HANDLE(radv_device, device, _device);
4009 struct radv_framebuffer *framebuffer;
4010
4011 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4012
4013 size_t size = sizeof(*framebuffer) +
4014 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4015 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4016 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4017 if (framebuffer == NULL)
4018 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
4019
4020 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4021 framebuffer->width = pCreateInfo->width;
4022 framebuffer->height = pCreateInfo->height;
4023 framebuffer->layers = pCreateInfo->layers;
4024 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4025 VkImageView _iview = pCreateInfo->pAttachments[i];
4026 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4027 framebuffer->attachments[i].attachment = iview;
4028 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
4029 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4030 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4031 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4032 }
4033 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4034 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4035 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4036 }
4037
4038 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4039 return VK_SUCCESS;
4040 }
4041
4042 void radv_DestroyFramebuffer(
4043 VkDevice _device,
4044 VkFramebuffer _fb,
4045 const VkAllocationCallbacks* pAllocator)
4046 {
4047 RADV_FROM_HANDLE(radv_device, device, _device);
4048 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4049
4050 if (!fb)
4051 return;
4052 vk_free2(&device->alloc, pAllocator, fb);
4053 }
4054
4055 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4056 {
4057 switch (address_mode) {
4058 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4059 return V_008F30_SQ_TEX_WRAP;
4060 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4061 return V_008F30_SQ_TEX_MIRROR;
4062 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4063 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4064 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4065 return V_008F30_SQ_TEX_CLAMP_BORDER;
4066 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4067 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4068 default:
4069 unreachable("illegal tex wrap mode");
4070 break;
4071 }
4072 }
4073
4074 static unsigned
4075 radv_tex_compare(VkCompareOp op)
4076 {
4077 switch (op) {
4078 case VK_COMPARE_OP_NEVER:
4079 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4080 case VK_COMPARE_OP_LESS:
4081 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4082 case VK_COMPARE_OP_EQUAL:
4083 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4084 case VK_COMPARE_OP_LESS_OR_EQUAL:
4085 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4086 case VK_COMPARE_OP_GREATER:
4087 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4088 case VK_COMPARE_OP_NOT_EQUAL:
4089 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4090 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4091 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4092 case VK_COMPARE_OP_ALWAYS:
4093 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4094 default:
4095 unreachable("illegal compare mode");
4096 break;
4097 }
4098 }
4099
4100 static unsigned
4101 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4102 {
4103 switch (filter) {
4104 case VK_FILTER_NEAREST:
4105 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4106 V_008F38_SQ_TEX_XY_FILTER_POINT);
4107 case VK_FILTER_LINEAR:
4108 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4109 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4110 case VK_FILTER_CUBIC_IMG:
4111 default:
4112 fprintf(stderr, "illegal texture filter");
4113 return 0;
4114 }
4115 }
4116
4117 static unsigned
4118 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4119 {
4120 switch (mode) {
4121 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4122 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4123 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4124 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4125 default:
4126 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4127 }
4128 }
4129
4130 static unsigned
4131 radv_tex_bordercolor(VkBorderColor bcolor)
4132 {
4133 switch (bcolor) {
4134 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4135 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4136 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4137 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4138 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4139 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4140 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4141 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4142 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4143 default:
4144 break;
4145 }
4146 return 0;
4147 }
4148
4149 static unsigned
4150 radv_tex_aniso_filter(unsigned filter)
4151 {
4152 if (filter < 2)
4153 return 0;
4154 if (filter < 4)
4155 return 1;
4156 if (filter < 8)
4157 return 2;
4158 if (filter < 16)
4159 return 3;
4160 return 4;
4161 }
4162
4163 static unsigned
4164 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4165 {
4166 switch (mode) {
4167 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4168 return SQ_IMG_FILTER_MODE_BLEND;
4169 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4170 return SQ_IMG_FILTER_MODE_MIN;
4171 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4172 return SQ_IMG_FILTER_MODE_MAX;
4173 default:
4174 break;
4175 }
4176 return 0;
4177 }
4178
4179 static void
4180 radv_init_sampler(struct radv_device *device,
4181 struct radv_sampler *sampler,
4182 const VkSamplerCreateInfo *pCreateInfo)
4183 {
4184 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
4185 (uint32_t) pCreateInfo->maxAnisotropy : 0;
4186 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4187 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4188 unsigned filter_mode = SQ_IMG_FILTER_MODE_BLEND;
4189
4190 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4191 vk_find_struct_const(pCreateInfo->pNext,
4192 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4193 if (sampler_reduction)
4194 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4195
4196 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4197 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4198 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4199 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4200 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4201 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4202 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4203 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4204 S_008F30_DISABLE_CUBE_WRAP(0) |
4205 S_008F30_COMPAT_MODE(is_vi) |
4206 S_008F30_FILTER_MODE(filter_mode));
4207 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4208 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4209 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4210 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4211 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4212 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4213 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4214 S_008F38_MIP_POINT_PRECLAMP(0) |
4215 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4216 S_008F38_FILTER_PREC_FIX(1) |
4217 S_008F38_ANISO_OVERRIDE(is_vi));
4218 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4219 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4220 }
4221
4222 VkResult radv_CreateSampler(
4223 VkDevice _device,
4224 const VkSamplerCreateInfo* pCreateInfo,
4225 const VkAllocationCallbacks* pAllocator,
4226 VkSampler* pSampler)
4227 {
4228 RADV_FROM_HANDLE(radv_device, device, _device);
4229 struct radv_sampler *sampler;
4230
4231 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4232
4233 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4234 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4235 if (!sampler)
4236 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
4237
4238 radv_init_sampler(device, sampler, pCreateInfo);
4239 *pSampler = radv_sampler_to_handle(sampler);
4240
4241 return VK_SUCCESS;
4242 }
4243
4244 void radv_DestroySampler(
4245 VkDevice _device,
4246 VkSampler _sampler,
4247 const VkAllocationCallbacks* pAllocator)
4248 {
4249 RADV_FROM_HANDLE(radv_device, device, _device);
4250 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4251
4252 if (!sampler)
4253 return;
4254 vk_free2(&device->alloc, pAllocator, sampler);
4255 }
4256
4257 /* vk_icd.h does not declare this function, so we declare it here to
4258 * suppress Wmissing-prototypes.
4259 */
4260 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4261 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4262
4263 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4264 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4265 {
4266 /* For the full details on loader interface versioning, see
4267 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4268 * What follows is a condensed summary, to help you navigate the large and
4269 * confusing official doc.
4270 *
4271 * - Loader interface v0 is incompatible with later versions. We don't
4272 * support it.
4273 *
4274 * - In loader interface v1:
4275 * - The first ICD entrypoint called by the loader is
4276 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4277 * entrypoint.
4278 * - The ICD must statically expose no other Vulkan symbol unless it is
4279 * linked with -Bsymbolic.
4280 * - Each dispatchable Vulkan handle created by the ICD must be
4281 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4282 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4283 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4284 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4285 * such loader-managed surfaces.
4286 *
4287 * - Loader interface v2 differs from v1 in:
4288 * - The first ICD entrypoint called by the loader is
4289 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4290 * statically expose this entrypoint.
4291 *
4292 * - Loader interface v3 differs from v2 in:
4293 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4294 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4295 * because the loader no longer does so.
4296 */
4297 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4298 return VK_SUCCESS;
4299 }
4300
4301 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4302 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4303 int *pFD)
4304 {
4305 RADV_FROM_HANDLE(radv_device, device, _device);
4306 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4307
4308 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4309
4310 /* At the moment, we support only the below handle types. */
4311 assert(pGetFdInfo->handleType ==
4312 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4313 pGetFdInfo->handleType ==
4314 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4315
4316 bool ret = radv_get_memory_fd(device, memory, pFD);
4317 if (ret == false)
4318 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
4319 return VK_SUCCESS;
4320 }
4321
4322 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4323 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
4324 int fd,
4325 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4326 {
4327 switch (handleType) {
4328 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4329 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4330 return VK_SUCCESS;
4331
4332 default:
4333 /* The valid usage section for this function says:
4334 *
4335 * "handleType must not be one of the handle types defined as
4336 * opaque."
4337 *
4338 * So opaque handle types fall into the default "unsupported" case.
4339 */
4340 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4341 }
4342 }
4343
4344 static VkResult radv_import_opaque_fd(struct radv_device *device,
4345 int fd,
4346 uint32_t *syncobj)
4347 {
4348 uint32_t syncobj_handle = 0;
4349 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4350 if (ret != 0)
4351 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4352
4353 if (*syncobj)
4354 device->ws->destroy_syncobj(device->ws, *syncobj);
4355
4356 *syncobj = syncobj_handle;
4357 close(fd);
4358
4359 return VK_SUCCESS;
4360 }
4361
4362 static VkResult radv_import_sync_fd(struct radv_device *device,
4363 int fd,
4364 uint32_t *syncobj)
4365 {
4366 /* If we create a syncobj we do it locally so that if we have an error, we don't
4367 * leave a syncobj in an undetermined state in the fence. */
4368 uint32_t syncobj_handle = *syncobj;
4369 if (!syncobj_handle) {
4370 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4371 if (ret) {
4372 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4373 }
4374 }
4375
4376 if (fd == -1) {
4377 device->ws->signal_syncobj(device->ws, syncobj_handle);
4378 } else {
4379 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
4380 if (ret != 0)
4381 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4382 }
4383
4384 *syncobj = syncobj_handle;
4385 if (fd != -1)
4386 close(fd);
4387
4388 return VK_SUCCESS;
4389 }
4390
4391 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
4392 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
4393 {
4394 RADV_FROM_HANDLE(radv_device, device, _device);
4395 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
4396 uint32_t *syncobj_dst = NULL;
4397
4398 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
4399 syncobj_dst = &sem->temp_syncobj;
4400 } else {
4401 syncobj_dst = &sem->syncobj;
4402 }
4403
4404 switch(pImportSemaphoreFdInfo->handleType) {
4405 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4406 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4407 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4408 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4409 default:
4410 unreachable("Unhandled semaphore handle type");
4411 }
4412 }
4413
4414 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
4415 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
4416 int *pFd)
4417 {
4418 RADV_FROM_HANDLE(radv_device, device, _device);
4419 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
4420 int ret;
4421 uint32_t syncobj_handle;
4422
4423 if (sem->temp_syncobj)
4424 syncobj_handle = sem->temp_syncobj;
4425 else
4426 syncobj_handle = sem->syncobj;
4427
4428 switch(pGetFdInfo->handleType) {
4429 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4430 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4431 break;
4432 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4433 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4434 if (!ret) {
4435 if (sem->temp_syncobj) {
4436 close (sem->temp_syncobj);
4437 sem->temp_syncobj = 0;
4438 } else {
4439 device->ws->reset_syncobj(device->ws, syncobj_handle);
4440 }
4441 }
4442 break;
4443 default:
4444 unreachable("Unhandled semaphore handle type");
4445 }
4446
4447 if (ret)
4448 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4449 return VK_SUCCESS;
4450 }
4451
4452 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
4453 VkPhysicalDevice physicalDevice,
4454 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
4455 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
4456 {
4457 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4458
4459 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
4460 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4461 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4462 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4463 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4464 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4465 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4466 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4467 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
4468 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4469 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4470 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4471 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4472 } else {
4473 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
4474 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
4475 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
4476 }
4477 }
4478
4479 VkResult radv_ImportFenceFdKHR(VkDevice _device,
4480 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
4481 {
4482 RADV_FROM_HANDLE(radv_device, device, _device);
4483 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
4484 uint32_t *syncobj_dst = NULL;
4485
4486
4487 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT_KHR) {
4488 syncobj_dst = &fence->temp_syncobj;
4489 } else {
4490 syncobj_dst = &fence->syncobj;
4491 }
4492
4493 switch(pImportFenceFdInfo->handleType) {
4494 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4495 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4496 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4497 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4498 default:
4499 unreachable("Unhandled fence handle type");
4500 }
4501 }
4502
4503 VkResult radv_GetFenceFdKHR(VkDevice _device,
4504 const VkFenceGetFdInfoKHR *pGetFdInfo,
4505 int *pFd)
4506 {
4507 RADV_FROM_HANDLE(radv_device, device, _device);
4508 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
4509 int ret;
4510 uint32_t syncobj_handle;
4511
4512 if (fence->temp_syncobj)
4513 syncobj_handle = fence->temp_syncobj;
4514 else
4515 syncobj_handle = fence->syncobj;
4516
4517 switch(pGetFdInfo->handleType) {
4518 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4519 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4520 break;
4521 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4522 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4523 if (!ret) {
4524 if (fence->temp_syncobj) {
4525 close (fence->temp_syncobj);
4526 fence->temp_syncobj = 0;
4527 } else {
4528 device->ws->reset_syncobj(device->ws, syncobj_handle);
4529 }
4530 }
4531 break;
4532 default:
4533 unreachable("Unhandled fence handle type");
4534 }
4535
4536 if (ret)
4537 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4538 return VK_SUCCESS;
4539 }
4540
4541 void radv_GetPhysicalDeviceExternalFenceProperties(
4542 VkPhysicalDevice physicalDevice,
4543 const VkPhysicalDeviceExternalFenceInfoKHR* pExternalFenceInfo,
4544 VkExternalFencePropertiesKHR* pExternalFenceProperties)
4545 {
4546 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4547
4548 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4549 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4550 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4551 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4552 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4553 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT_KHR |
4554 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4555 } else {
4556 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
4557 pExternalFenceProperties->compatibleHandleTypes = 0;
4558 pExternalFenceProperties->externalFenceFeatures = 0;
4559 }
4560 }
4561
4562 VkResult
4563 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
4564 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
4565 const VkAllocationCallbacks* pAllocator,
4566 VkDebugReportCallbackEXT* pCallback)
4567 {
4568 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4569 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
4570 pCreateInfo, pAllocator, &instance->alloc,
4571 pCallback);
4572 }
4573
4574 void
4575 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
4576 VkDebugReportCallbackEXT _callback,
4577 const VkAllocationCallbacks* pAllocator)
4578 {
4579 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4580 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
4581 _callback, pAllocator, &instance->alloc);
4582 }
4583
4584 void
4585 radv_DebugReportMessageEXT(VkInstance _instance,
4586 VkDebugReportFlagsEXT flags,
4587 VkDebugReportObjectTypeEXT objectType,
4588 uint64_t object,
4589 size_t location,
4590 int32_t messageCode,
4591 const char* pLayerPrefix,
4592 const char* pMessage)
4593 {
4594 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4595 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
4596 object, location, messageCode, pLayerPrefix, pMessage);
4597 }
4598
4599 void
4600 radv_GetDeviceGroupPeerMemoryFeatures(
4601 VkDevice device,
4602 uint32_t heapIndex,
4603 uint32_t localDeviceIndex,
4604 uint32_t remoteDeviceIndex,
4605 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
4606 {
4607 assert(localDeviceIndex == remoteDeviceIndex);
4608
4609 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
4610 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
4611 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
4612 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
4613 }