2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
47 #include "util/build_id.h"
48 #include "util/debug.h"
49 #include "util/mesa-sha1.h"
50 #include "compiler/glsl_types.h"
51 #include "util/xmlpool.h"
54 radv_device_get_cache_uuid(enum radeon_family family
, void *uuid
)
57 unsigned char sha1
[20];
58 unsigned ptr_size
= sizeof(void*);
60 memset(uuid
, 0, VK_UUID_SIZE
);
61 _mesa_sha1_init(&ctx
);
63 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid
, &ctx
) ||
64 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo
, &ctx
))
67 _mesa_sha1_update(&ctx
, &family
, sizeof(family
));
68 _mesa_sha1_update(&ctx
, &ptr_size
, sizeof(ptr_size
));
69 _mesa_sha1_final(&ctx
, sha1
);
71 memcpy(uuid
, sha1
, VK_UUID_SIZE
);
76 radv_get_driver_uuid(void *uuid
)
78 ac_compute_driver_uuid(uuid
, VK_UUID_SIZE
);
82 radv_get_device_uuid(struct radeon_info
*info
, void *uuid
)
84 ac_compute_device_uuid(info
, uuid
, VK_UUID_SIZE
);
88 radv_get_device_name(enum radeon_family family
, char *name
, size_t name_len
)
90 const char *chip_string
;
93 case CHIP_TAHITI
: chip_string
= "AMD RADV TAHITI"; break;
94 case CHIP_PITCAIRN
: chip_string
= "AMD RADV PITCAIRN"; break;
95 case CHIP_VERDE
: chip_string
= "AMD RADV CAPE VERDE"; break;
96 case CHIP_OLAND
: chip_string
= "AMD RADV OLAND"; break;
97 case CHIP_HAINAN
: chip_string
= "AMD RADV HAINAN"; break;
98 case CHIP_BONAIRE
: chip_string
= "AMD RADV BONAIRE"; break;
99 case CHIP_KAVERI
: chip_string
= "AMD RADV KAVERI"; break;
100 case CHIP_KABINI
: chip_string
= "AMD RADV KABINI"; break;
101 case CHIP_HAWAII
: chip_string
= "AMD RADV HAWAII"; break;
102 case CHIP_TONGA
: chip_string
= "AMD RADV TONGA"; break;
103 case CHIP_ICELAND
: chip_string
= "AMD RADV ICELAND"; break;
104 case CHIP_CARRIZO
: chip_string
= "AMD RADV CARRIZO"; break;
105 case CHIP_FIJI
: chip_string
= "AMD RADV FIJI"; break;
106 case CHIP_POLARIS10
: chip_string
= "AMD RADV POLARIS10"; break;
107 case CHIP_POLARIS11
: chip_string
= "AMD RADV POLARIS11"; break;
108 case CHIP_POLARIS12
: chip_string
= "AMD RADV POLARIS12"; break;
109 case CHIP_STONEY
: chip_string
= "AMD RADV STONEY"; break;
110 case CHIP_VEGAM
: chip_string
= "AMD RADV VEGA M"; break;
111 case CHIP_VEGA10
: chip_string
= "AMD RADV VEGA10"; break;
112 case CHIP_VEGA12
: chip_string
= "AMD RADV VEGA12"; break;
113 case CHIP_VEGA20
: chip_string
= "AMD RADV VEGA20"; break;
114 case CHIP_RAVEN
: chip_string
= "AMD RADV RAVEN"; break;
115 case CHIP_RAVEN2
: chip_string
= "AMD RADV RAVEN2"; break;
116 case CHIP_NAVI10
: chip_string
= "AMD RADV NAVI10"; break;
117 case CHIP_NAVI12
: chip_string
= "AMD RADV NAVI12"; break;
118 case CHIP_NAVI14
: chip_string
= "AMD RADV NAVI14"; break;
119 default: chip_string
= "AMD RADV unknown"; break;
122 snprintf(name
, name_len
, "%s (LLVM " MESA_LLVM_VERSION_STRING
")", chip_string
);
126 radv_get_visible_vram_size(struct radv_physical_device
*device
)
128 return MIN2(device
->rad_info
.vram_size
, device
->rad_info
.vram_vis_size
);
132 radv_get_vram_size(struct radv_physical_device
*device
)
134 return device
->rad_info
.vram_size
- radv_get_visible_vram_size(device
);
138 radv_physical_device_init_mem_types(struct radv_physical_device
*device
)
140 STATIC_ASSERT(RADV_MEM_HEAP_COUNT
<= VK_MAX_MEMORY_HEAPS
);
141 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
142 uint64_t vram_size
= radv_get_vram_size(device
);
143 int vram_index
= -1, visible_vram_index
= -1, gart_index
= -1;
144 device
->memory_properties
.memoryHeapCount
= 0;
146 vram_index
= device
->memory_properties
.memoryHeapCount
++;
147 device
->memory_properties
.memoryHeaps
[vram_index
] = (VkMemoryHeap
) {
149 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
152 if (visible_vram_size
) {
153 visible_vram_index
= device
->memory_properties
.memoryHeapCount
++;
154 device
->memory_properties
.memoryHeaps
[visible_vram_index
] = (VkMemoryHeap
) {
155 .size
= visible_vram_size
,
156 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
159 if (device
->rad_info
.gart_size
> 0) {
160 gart_index
= device
->memory_properties
.memoryHeapCount
++;
161 device
->memory_properties
.memoryHeaps
[gart_index
] = (VkMemoryHeap
) {
162 .size
= device
->rad_info
.gart_size
,
163 .flags
= device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
167 STATIC_ASSERT(RADV_MEM_TYPE_COUNT
<= VK_MAX_MEMORY_TYPES
);
168 unsigned type_count
= 0;
169 if (vram_index
>= 0) {
170 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM
;
171 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
172 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
,
173 .heapIndex
= vram_index
,
176 if (gart_index
>= 0) {
177 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_WRITE_COMBINE
;
178 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
179 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
180 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
181 (device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
),
182 .heapIndex
= gart_index
,
185 if (visible_vram_index
>= 0) {
186 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM_CPU_ACCESS
;
187 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
188 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
189 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
190 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
191 .heapIndex
= visible_vram_index
,
194 if (gart_index
>= 0) {
195 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_CACHED
;
196 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
197 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
198 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
199 VK_MEMORY_PROPERTY_HOST_CACHED_BIT
|
200 (device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
),
201 .heapIndex
= gart_index
,
204 device
->memory_properties
.memoryTypeCount
= type_count
;
208 radv_handle_env_var_force_family(struct radv_physical_device
*device
)
210 const char *family
= getenv("RADV_FORCE_FAMILY");
216 for (i
= CHIP_TAHITI
; i
< CHIP_LAST
; i
++) {
217 if (!strcmp(family
, ac_get_llvm_processor_name(i
))) {
218 /* Override family and chip_class. */
219 device
->rad_info
.family
= i
;
221 if (i
>= CHIP_NAVI10
)
222 device
->rad_info
.chip_class
= GFX10
;
223 else if (i
>= CHIP_VEGA10
)
224 device
->rad_info
.chip_class
= GFX9
;
225 else if (i
>= CHIP_TONGA
)
226 device
->rad_info
.chip_class
= GFX8
;
227 else if (i
>= CHIP_BONAIRE
)
228 device
->rad_info
.chip_class
= GFX7
;
230 device
->rad_info
.chip_class
= GFX6
;
236 fprintf(stderr
, "radv: Unknown family: %s\n", family
);
241 radv_physical_device_init(struct radv_physical_device
*device
,
242 struct radv_instance
*instance
,
243 drmDevicePtr drm_device
)
245 const char *path
= drm_device
->nodes
[DRM_NODE_RENDER
];
247 drmVersionPtr version
;
251 fd
= open(path
, O_RDWR
| O_CLOEXEC
);
253 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
254 radv_logi("Could not open device '%s'", path
);
256 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
259 version
= drmGetVersion(fd
);
263 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
264 radv_logi("Could not get the kernel driver version for device '%s'", path
);
266 return vk_errorf(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
,
267 "failed to get version %s: %m", path
);
270 if (strcmp(version
->name
, "amdgpu")) {
271 drmFreeVersion(version
);
274 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
275 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path
);
277 return VK_ERROR_INCOMPATIBLE_DRIVER
;
279 drmFreeVersion(version
);
281 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
282 radv_logi("Found compatible device '%s'.", path
);
284 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
285 device
->instance
= instance
;
287 device
->ws
= radv_amdgpu_winsys_create(fd
, instance
->debug_flags
,
288 instance
->perftest_flags
);
290 result
= vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
294 if (instance
->enabled_extensions
.KHR_display
) {
295 master_fd
= open(drm_device
->nodes
[DRM_NODE_PRIMARY
], O_RDWR
| O_CLOEXEC
);
296 if (master_fd
>= 0) {
297 uint32_t accel_working
= 0;
298 struct drm_amdgpu_info request
= {
299 .return_pointer
= (uintptr_t)&accel_working
,
300 .return_size
= sizeof(accel_working
),
301 .query
= AMDGPU_INFO_ACCEL_WORKING
304 if (drmCommandWrite(master_fd
, DRM_AMDGPU_INFO
, &request
, sizeof (struct drm_amdgpu_info
)) < 0 || !accel_working
) {
311 device
->master_fd
= master_fd
;
312 device
->local_fd
= fd
;
313 device
->ws
->query_info(device
->ws
, &device
->rad_info
);
315 radv_handle_env_var_force_family(device
);
317 radv_get_device_name(device
->rad_info
.family
, device
->name
, sizeof(device
->name
));
319 if (radv_device_get_cache_uuid(device
->rad_info
.family
, device
->cache_uuid
)) {
320 device
->ws
->destroy(device
->ws
);
321 result
= vk_errorf(instance
, VK_ERROR_INITIALIZATION_FAILED
,
322 "cannot generate UUID");
326 /* These flags affect shader compilation. */
327 uint64_t shader_env_flags
=
328 (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
? 0x1 : 0) |
329 (device
->instance
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
? 0x2 : 0);
331 /* The gpu id is already embedded in the uuid so we just pass "radv"
332 * when creating the cache.
334 char buf
[VK_UUID_SIZE
* 2 + 1];
335 disk_cache_format_hex_id(buf
, device
->cache_uuid
, VK_UUID_SIZE
* 2);
336 device
->disk_cache
= disk_cache_create(device
->name
, buf
, shader_env_flags
);
338 if (device
->rad_info
.chip_class
< GFX8
||
339 device
->rad_info
.chip_class
> GFX9
)
340 fprintf(stderr
, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
342 radv_get_driver_uuid(&device
->driver_uuid
);
343 radv_get_device_uuid(&device
->rad_info
, &device
->device_uuid
);
345 if (device
->rad_info
.family
== CHIP_STONEY
||
346 device
->rad_info
.chip_class
>= GFX9
) {
347 device
->has_rbplus
= true;
348 device
->rbplus_allowed
= device
->rad_info
.family
== CHIP_STONEY
||
349 device
->rad_info
.family
== CHIP_VEGA12
||
350 device
->rad_info
.family
== CHIP_RAVEN
||
351 device
->rad_info
.family
== CHIP_RAVEN2
||
352 device
->rad_info
.family
== CHIP_RENOIR
;
355 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
358 device
->has_clear_state
= device
->rad_info
.chip_class
>= GFX7
;
360 device
->cpdma_prefetch_writes_memory
= device
->rad_info
.chip_class
<= GFX8
;
362 /* Vega10/Raven need a special workaround for a hardware bug. */
363 device
->has_scissor_bug
= device
->rad_info
.family
== CHIP_VEGA10
||
364 device
->rad_info
.family
== CHIP_RAVEN
;
366 device
->has_tc_compat_zrange_bug
= device
->rad_info
.chip_class
< GFX10
;
368 /* Out-of-order primitive rasterization. */
369 device
->has_out_of_order_rast
= device
->rad_info
.chip_class
>= GFX8
&&
370 device
->rad_info
.max_se
>= 2;
371 device
->out_of_order_rast_allowed
= device
->has_out_of_order_rast
&&
372 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_OUT_OF_ORDER
);
374 device
->dcc_msaa_allowed
=
375 (device
->instance
->perftest_flags
& RADV_PERFTEST_DCC_MSAA
);
377 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
378 device
->has_load_ctx_reg_pkt
= device
->rad_info
.chip_class
>= GFX9
||
379 (device
->rad_info
.chip_class
>= GFX8
&&
380 device
->rad_info
.me_fw_feature
>= 41);
382 device
->has_dcc_constant_encode
= device
->rad_info
.family
== CHIP_RAVEN2
||
383 device
->rad_info
.family
== CHIP_RENOIR
||
384 device
->rad_info
.chip_class
>= GFX10
;
386 device
->use_shader_ballot
= device
->rad_info
.chip_class
>= GFX8
&&
387 device
->instance
->perftest_flags
& RADV_PERFTEST_SHADER_BALLOT
;
389 /* Determine the number of threads per wave for all stages. */
390 device
->cs_wave_size
= 64;
391 device
->ps_wave_size
= 64;
392 device
->ge_wave_size
= 64;
394 if (device
->rad_info
.chip_class
>= GFX10
) {
395 if (device
->instance
->perftest_flags
& RADV_PERFTEST_CS_WAVE_32
)
396 device
->cs_wave_size
= 32;
398 /* For pixel shaders, wave64 is recommanded. */
399 if (device
->instance
->perftest_flags
& RADV_PERFTEST_PS_WAVE_32
)
400 device
->ps_wave_size
= 32;
402 if (device
->instance
->perftest_flags
& RADV_PERFTEST_GE_WAVE_32
)
403 device
->ge_wave_size
= 32;
406 radv_physical_device_init_mem_types(device
);
407 radv_fill_device_extension_table(device
, &device
->supported_extensions
);
409 device
->bus_info
= *drm_device
->businfo
.pci
;
411 if ((device
->instance
->debug_flags
& RADV_DEBUG_INFO
))
412 ac_print_gpu_info(&device
->rad_info
);
414 /* The WSI is structured as a layer on top of the driver, so this has
415 * to be the last part of initialization (at least until we get other
418 result
= radv_init_wsi(device
);
419 if (result
!= VK_SUCCESS
) {
420 device
->ws
->destroy(device
->ws
);
421 vk_error(instance
, result
);
435 radv_physical_device_finish(struct radv_physical_device
*device
)
437 radv_finish_wsi(device
);
438 device
->ws
->destroy(device
->ws
);
439 disk_cache_destroy(device
->disk_cache
);
440 close(device
->local_fd
);
441 if (device
->master_fd
!= -1)
442 close(device
->master_fd
);
446 default_alloc_func(void *pUserData
, size_t size
, size_t align
,
447 VkSystemAllocationScope allocationScope
)
453 default_realloc_func(void *pUserData
, void *pOriginal
, size_t size
,
454 size_t align
, VkSystemAllocationScope allocationScope
)
456 return realloc(pOriginal
, size
);
460 default_free_func(void *pUserData
, void *pMemory
)
465 static const VkAllocationCallbacks default_alloc
= {
467 .pfnAllocation
= default_alloc_func
,
468 .pfnReallocation
= default_realloc_func
,
469 .pfnFree
= default_free_func
,
472 static const struct debug_control radv_debug_options
[] = {
473 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS
},
474 {"nodcc", RADV_DEBUG_NO_DCC
},
475 {"shaders", RADV_DEBUG_DUMP_SHADERS
},
476 {"nocache", RADV_DEBUG_NO_CACHE
},
477 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS
},
478 {"nohiz", RADV_DEBUG_NO_HIZ
},
479 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE
},
480 {"unsafemath", RADV_DEBUG_UNSAFE_MATH
},
481 {"allbos", RADV_DEBUG_ALL_BOS
},
482 {"noibs", RADV_DEBUG_NO_IBS
},
483 {"spirv", RADV_DEBUG_DUMP_SPIRV
},
484 {"vmfaults", RADV_DEBUG_VM_FAULTS
},
485 {"zerovram", RADV_DEBUG_ZERO_VRAM
},
486 {"syncshaders", RADV_DEBUG_SYNC_SHADERS
},
487 {"nosisched", RADV_DEBUG_NO_SISCHED
},
488 {"preoptir", RADV_DEBUG_PREOPTIR
},
489 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS
},
490 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER
},
491 {"info", RADV_DEBUG_INFO
},
492 {"errors", RADV_DEBUG_ERRORS
},
493 {"startup", RADV_DEBUG_STARTUP
},
494 {"checkir", RADV_DEBUG_CHECKIR
},
495 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM
},
496 {"nobinning", RADV_DEBUG_NOBINNING
},
497 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT
},
498 {"nongg", RADV_DEBUG_NO_NGG
},
499 {"noshaderballot", RADV_DEBUG_NO_SHADER_BALLOT
},
500 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS
},
505 radv_get_debug_option_name(int id
)
507 assert(id
< ARRAY_SIZE(radv_debug_options
) - 1);
508 return radv_debug_options
[id
].string
;
511 static const struct debug_control radv_perftest_options
[] = {
512 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN
},
513 {"sisched", RADV_PERFTEST_SISCHED
},
514 {"localbos", RADV_PERFTEST_LOCAL_BOS
},
515 {"dccmsaa", RADV_PERFTEST_DCC_MSAA
},
516 {"bolist", RADV_PERFTEST_BO_LIST
},
517 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT
},
518 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK
},
519 {"cswave32", RADV_PERFTEST_CS_WAVE_32
},
520 {"pswave32", RADV_PERFTEST_PS_WAVE_32
},
521 {"gewave32", RADV_PERFTEST_GE_WAVE_32
},
526 radv_get_perftest_option_name(int id
)
528 assert(id
< ARRAY_SIZE(radv_perftest_options
) - 1);
529 return radv_perftest_options
[id
].string
;
533 radv_handle_per_app_options(struct radv_instance
*instance
,
534 const VkApplicationInfo
*info
)
536 const char *name
= info
? info
->pApplicationName
: NULL
;
541 if (!strcmp(name
, "Talos - Linux - 32bit") ||
542 !strcmp(name
, "Talos - Linux - 64bit")) {
543 if (!(instance
->debug_flags
& RADV_DEBUG_NO_SISCHED
)) {
544 /* Force enable LLVM sisched for Talos because it looks
545 * safe and it gives few more FPS.
547 instance
->perftest_flags
|= RADV_PERFTEST_SISCHED
;
549 } else if (!strcmp(name
, "DOOM_VFR")) {
550 /* Work around a Doom VFR game bug */
551 instance
->debug_flags
|= RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
552 } else if (!strcmp(name
, "MonsterHunterWorld.exe")) {
553 /* Workaround for a WaW hazard when LLVM moves/merges
554 * load/store memory operations.
555 * See https://reviews.llvm.org/D61313
557 if (HAVE_LLVM
< 0x900)
558 instance
->debug_flags
|= RADV_DEBUG_NO_LOAD_STORE_OPT
;
559 } else if (!strcmp(name
, "Wolfenstein: Youngblood")) {
560 if (!(instance
->debug_flags
& RADV_DEBUG_NO_SHADER_BALLOT
)) {
561 /* Force enable VK_AMD_shader_ballot because it looks
562 * safe and it gives a nice boost (+20% on Vega 56 at
565 instance
->perftest_flags
|= RADV_PERFTEST_SHADER_BALLOT
;
570 static int radv_get_instance_extension_index(const char *name
)
572 for (unsigned i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; ++i
) {
573 if (strcmp(name
, radv_instance_extensions
[i
].extensionName
) == 0)
579 static const char radv_dri_options_xml
[] =
581 DRI_CONF_SECTION_QUALITY
582 DRI_CONF_ADAPTIVE_SYNC("true")
586 static void radv_init_dri_options(struct radv_instance
*instance
)
588 driParseOptionInfo(&instance
->available_dri_options
, radv_dri_options_xml
);
589 driParseConfigFiles(&instance
->dri_options
,
590 &instance
->available_dri_options
,
594 VkResult
radv_CreateInstance(
595 const VkInstanceCreateInfo
* pCreateInfo
,
596 const VkAllocationCallbacks
* pAllocator
,
597 VkInstance
* pInstance
)
599 struct radv_instance
*instance
;
602 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO
);
604 uint32_t client_version
;
605 if (pCreateInfo
->pApplicationInfo
&&
606 pCreateInfo
->pApplicationInfo
->apiVersion
!= 0) {
607 client_version
= pCreateInfo
->pApplicationInfo
->apiVersion
;
609 client_version
= VK_API_VERSION_1_0
;
612 instance
= vk_zalloc2(&default_alloc
, pAllocator
, sizeof(*instance
), 8,
613 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
615 return vk_error(NULL
, VK_ERROR_OUT_OF_HOST_MEMORY
);
617 instance
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
620 instance
->alloc
= *pAllocator
;
622 instance
->alloc
= default_alloc
;
624 instance
->apiVersion
= client_version
;
625 instance
->physicalDeviceCount
= -1;
627 instance
->debug_flags
= parse_debug_string(getenv("RADV_DEBUG"),
630 instance
->perftest_flags
= parse_debug_string(getenv("RADV_PERFTEST"),
631 radv_perftest_options
);
634 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
635 radv_logi("Created an instance");
637 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
638 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
639 int index
= radv_get_instance_extension_index(ext_name
);
641 if (index
< 0 || !radv_supported_instance_extensions
.extensions
[index
]) {
642 vk_free2(&default_alloc
, pAllocator
, instance
);
643 return vk_error(instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
646 instance
->enabled_extensions
.extensions
[index
] = true;
649 result
= vk_debug_report_instance_init(&instance
->debug_report_callbacks
);
650 if (result
!= VK_SUCCESS
) {
651 vk_free2(&default_alloc
, pAllocator
, instance
);
652 return vk_error(instance
, result
);
656 glsl_type_singleton_init_or_ref();
658 VG(VALGRIND_CREATE_MEMPOOL(instance
, 0, false));
660 radv_init_dri_options(instance
);
661 radv_handle_per_app_options(instance
, pCreateInfo
->pApplicationInfo
);
663 *pInstance
= radv_instance_to_handle(instance
);
668 void radv_DestroyInstance(
669 VkInstance _instance
,
670 const VkAllocationCallbacks
* pAllocator
)
672 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
677 for (int i
= 0; i
< instance
->physicalDeviceCount
; ++i
) {
678 radv_physical_device_finish(instance
->physicalDevices
+ i
);
681 VG(VALGRIND_DESTROY_MEMPOOL(instance
));
683 glsl_type_singleton_decref();
686 driDestroyOptionCache(&instance
->dri_options
);
687 driDestroyOptionInfo(&instance
->available_dri_options
);
689 vk_debug_report_instance_destroy(&instance
->debug_report_callbacks
);
691 vk_free(&instance
->alloc
, instance
);
695 radv_enumerate_devices(struct radv_instance
*instance
)
697 /* TODO: Check for more devices ? */
698 drmDevicePtr devices
[8];
699 VkResult result
= VK_ERROR_INCOMPATIBLE_DRIVER
;
702 instance
->physicalDeviceCount
= 0;
704 max_devices
= drmGetDevices2(0, devices
, ARRAY_SIZE(devices
));
706 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
707 radv_logi("Found %d drm nodes", max_devices
);
710 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
712 for (unsigned i
= 0; i
< (unsigned)max_devices
; i
++) {
713 if (devices
[i
]->available_nodes
& 1 << DRM_NODE_RENDER
&&
714 devices
[i
]->bustype
== DRM_BUS_PCI
&&
715 devices
[i
]->deviceinfo
.pci
->vendor_id
== ATI_VENDOR_ID
) {
717 result
= radv_physical_device_init(instance
->physicalDevices
+
718 instance
->physicalDeviceCount
,
721 if (result
== VK_SUCCESS
)
722 ++instance
->physicalDeviceCount
;
723 else if (result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
727 drmFreeDevices(devices
, max_devices
);
732 VkResult
radv_EnumeratePhysicalDevices(
733 VkInstance _instance
,
734 uint32_t* pPhysicalDeviceCount
,
735 VkPhysicalDevice
* pPhysicalDevices
)
737 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
740 if (instance
->physicalDeviceCount
< 0) {
741 result
= radv_enumerate_devices(instance
);
742 if (result
!= VK_SUCCESS
&&
743 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
747 if (!pPhysicalDevices
) {
748 *pPhysicalDeviceCount
= instance
->physicalDeviceCount
;
750 *pPhysicalDeviceCount
= MIN2(*pPhysicalDeviceCount
, instance
->physicalDeviceCount
);
751 for (unsigned i
= 0; i
< *pPhysicalDeviceCount
; ++i
)
752 pPhysicalDevices
[i
] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
755 return *pPhysicalDeviceCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
759 VkResult
radv_EnumeratePhysicalDeviceGroups(
760 VkInstance _instance
,
761 uint32_t* pPhysicalDeviceGroupCount
,
762 VkPhysicalDeviceGroupProperties
* pPhysicalDeviceGroupProperties
)
764 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
767 if (instance
->physicalDeviceCount
< 0) {
768 result
= radv_enumerate_devices(instance
);
769 if (result
!= VK_SUCCESS
&&
770 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
774 if (!pPhysicalDeviceGroupProperties
) {
775 *pPhysicalDeviceGroupCount
= instance
->physicalDeviceCount
;
777 *pPhysicalDeviceGroupCount
= MIN2(*pPhysicalDeviceGroupCount
, instance
->physicalDeviceCount
);
778 for (unsigned i
= 0; i
< *pPhysicalDeviceGroupCount
; ++i
) {
779 pPhysicalDeviceGroupProperties
[i
].physicalDeviceCount
= 1;
780 pPhysicalDeviceGroupProperties
[i
].physicalDevices
[0] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
781 pPhysicalDeviceGroupProperties
[i
].subsetAllocation
= false;
784 return *pPhysicalDeviceGroupCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
788 void radv_GetPhysicalDeviceFeatures(
789 VkPhysicalDevice physicalDevice
,
790 VkPhysicalDeviceFeatures
* pFeatures
)
792 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
793 memset(pFeatures
, 0, sizeof(*pFeatures
));
795 *pFeatures
= (VkPhysicalDeviceFeatures
) {
796 .robustBufferAccess
= true,
797 .fullDrawIndexUint32
= true,
798 .imageCubeArray
= true,
799 .independentBlend
= true,
800 .geometryShader
= true,
801 .tessellationShader
= true,
802 .sampleRateShading
= true,
803 .dualSrcBlend
= true,
805 .multiDrawIndirect
= true,
806 .drawIndirectFirstInstance
= true,
808 .depthBiasClamp
= true,
809 .fillModeNonSolid
= true,
814 .multiViewport
= true,
815 .samplerAnisotropy
= true,
816 .textureCompressionETC2
= radv_device_supports_etc(pdevice
),
817 .textureCompressionASTC_LDR
= false,
818 .textureCompressionBC
= true,
819 .occlusionQueryPrecise
= true,
820 .pipelineStatisticsQuery
= true,
821 .vertexPipelineStoresAndAtomics
= true,
822 .fragmentStoresAndAtomics
= true,
823 .shaderTessellationAndGeometryPointSize
= true,
824 .shaderImageGatherExtended
= true,
825 .shaderStorageImageExtendedFormats
= true,
826 .shaderStorageImageMultisample
= pdevice
->rad_info
.chip_class
>= GFX8
,
827 .shaderUniformBufferArrayDynamicIndexing
= true,
828 .shaderSampledImageArrayDynamicIndexing
= true,
829 .shaderStorageBufferArrayDynamicIndexing
= true,
830 .shaderStorageImageArrayDynamicIndexing
= true,
831 .shaderStorageImageReadWithoutFormat
= true,
832 .shaderStorageImageWriteWithoutFormat
= true,
833 .shaderClipDistance
= true,
834 .shaderCullDistance
= true,
835 .shaderFloat64
= true,
837 .shaderInt16
= pdevice
->rad_info
.chip_class
>= GFX9
,
838 .sparseBinding
= true,
839 .variableMultisampleRate
= true,
840 .inheritedQueries
= true,
844 void radv_GetPhysicalDeviceFeatures2(
845 VkPhysicalDevice physicalDevice
,
846 VkPhysicalDeviceFeatures2
*pFeatures
)
848 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
849 vk_foreach_struct(ext
, pFeatures
->pNext
) {
850 switch (ext
->sType
) {
851 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES
: {
852 VkPhysicalDeviceVariablePointersFeatures
*features
= (void *)ext
;
853 features
->variablePointersStorageBuffer
= true;
854 features
->variablePointers
= true;
857 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES
: {
858 VkPhysicalDeviceMultiviewFeatures
*features
= (VkPhysicalDeviceMultiviewFeatures
*)ext
;
859 features
->multiview
= true;
860 features
->multiviewGeometryShader
= true;
861 features
->multiviewTessellationShader
= true;
864 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES
: {
865 VkPhysicalDeviceShaderDrawParametersFeatures
*features
=
866 (VkPhysicalDeviceShaderDrawParametersFeatures
*)ext
;
867 features
->shaderDrawParameters
= true;
870 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES
: {
871 VkPhysicalDeviceProtectedMemoryFeatures
*features
=
872 (VkPhysicalDeviceProtectedMemoryFeatures
*)ext
;
873 features
->protectedMemory
= false;
876 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES
: {
877 VkPhysicalDevice16BitStorageFeatures
*features
=
878 (VkPhysicalDevice16BitStorageFeatures
*)ext
;
879 bool enabled
= pdevice
->rad_info
.chip_class
>= GFX8
;
880 features
->storageBuffer16BitAccess
= enabled
;
881 features
->uniformAndStorageBuffer16BitAccess
= enabled
;
882 features
->storagePushConstant16
= enabled
;
883 features
->storageInputOutput16
= enabled
&& HAVE_LLVM
>= 0x900;
886 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES
: {
887 VkPhysicalDeviceSamplerYcbcrConversionFeatures
*features
=
888 (VkPhysicalDeviceSamplerYcbcrConversionFeatures
*)ext
;
889 features
->samplerYcbcrConversion
= true;
892 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT
: {
893 VkPhysicalDeviceDescriptorIndexingFeaturesEXT
*features
=
894 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT
*)ext
;
895 features
->shaderInputAttachmentArrayDynamicIndexing
= true;
896 features
->shaderUniformTexelBufferArrayDynamicIndexing
= true;
897 features
->shaderStorageTexelBufferArrayDynamicIndexing
= true;
898 features
->shaderUniformBufferArrayNonUniformIndexing
= true;
899 features
->shaderSampledImageArrayNonUniformIndexing
= true;
900 features
->shaderStorageBufferArrayNonUniformIndexing
= true;
901 features
->shaderStorageImageArrayNonUniformIndexing
= true;
902 features
->shaderInputAttachmentArrayNonUniformIndexing
= true;
903 features
->shaderUniformTexelBufferArrayNonUniformIndexing
= true;
904 features
->shaderStorageTexelBufferArrayNonUniformIndexing
= true;
905 features
->descriptorBindingUniformBufferUpdateAfterBind
= true;
906 features
->descriptorBindingSampledImageUpdateAfterBind
= true;
907 features
->descriptorBindingStorageImageUpdateAfterBind
= true;
908 features
->descriptorBindingStorageBufferUpdateAfterBind
= true;
909 features
->descriptorBindingUniformTexelBufferUpdateAfterBind
= true;
910 features
->descriptorBindingStorageTexelBufferUpdateAfterBind
= true;
911 features
->descriptorBindingUpdateUnusedWhilePending
= true;
912 features
->descriptorBindingPartiallyBound
= true;
913 features
->descriptorBindingVariableDescriptorCount
= true;
914 features
->runtimeDescriptorArray
= true;
917 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT
: {
918 VkPhysicalDeviceConditionalRenderingFeaturesEXT
*features
=
919 (VkPhysicalDeviceConditionalRenderingFeaturesEXT
*)ext
;
920 features
->conditionalRendering
= true;
921 features
->inheritedConditionalRendering
= false;
924 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT
: {
925 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*features
=
926 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*)ext
;
927 features
->vertexAttributeInstanceRateDivisor
= VK_TRUE
;
928 features
->vertexAttributeInstanceRateZeroDivisor
= VK_TRUE
;
931 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT
: {
932 VkPhysicalDeviceTransformFeedbackFeaturesEXT
*features
=
933 (VkPhysicalDeviceTransformFeedbackFeaturesEXT
*)ext
;
934 features
->transformFeedback
= true;
935 features
->geometryStreams
= true;
938 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT
: {
939 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT
*features
=
940 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT
*)ext
;
941 features
->scalarBlockLayout
= pdevice
->rad_info
.chip_class
>= GFX7
;
944 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT
: {
945 VkPhysicalDeviceMemoryPriorityFeaturesEXT
*features
=
946 (VkPhysicalDeviceMemoryPriorityFeaturesEXT
*)ext
;
947 features
->memoryPriority
= VK_TRUE
;
950 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT
: {
951 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*features
=
952 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*)ext
;
953 features
->bufferDeviceAddress
= true;
954 features
->bufferDeviceAddressCaptureReplay
= false;
955 features
->bufferDeviceAddressMultiDevice
= false;
958 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT
: {
959 VkPhysicalDeviceDepthClipEnableFeaturesEXT
*features
=
960 (VkPhysicalDeviceDepthClipEnableFeaturesEXT
*)ext
;
961 features
->depthClipEnable
= true;
964 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT
: {
965 VkPhysicalDeviceHostQueryResetFeaturesEXT
*features
=
966 (VkPhysicalDeviceHostQueryResetFeaturesEXT
*)ext
;
967 features
->hostQueryReset
= true;
970 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR
: {
971 VkPhysicalDevice8BitStorageFeaturesKHR
*features
=
972 (VkPhysicalDevice8BitStorageFeaturesKHR
*)ext
;
973 bool enabled
= pdevice
->rad_info
.chip_class
>= GFX8
;
974 features
->storageBuffer8BitAccess
= enabled
;
975 features
->uniformAndStorageBuffer8BitAccess
= enabled
;
976 features
->storagePushConstant8
= enabled
;
979 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR
: {
980 VkPhysicalDeviceFloat16Int8FeaturesKHR
*features
=
981 (VkPhysicalDeviceFloat16Int8FeaturesKHR
*)ext
;
982 features
->shaderFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
&& HAVE_LLVM
>= 0x0800;
983 features
->shaderInt8
= true;
986 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR
: {
987 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR
*features
=
988 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR
*)ext
;
989 features
->shaderBufferInt64Atomics
= HAVE_LLVM
>= 0x0900;
990 features
->shaderSharedInt64Atomics
= HAVE_LLVM
>= 0x0900;
993 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT
: {
994 VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*features
=
995 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*)ext
;
997 features
->inlineUniformBlock
= true;
998 features
->descriptorBindingInlineUniformBlockUpdateAfterBind
= true;
1001 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV
: {
1002 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*features
=
1003 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*)ext
;
1004 features
->computeDerivativeGroupQuads
= false;
1005 features
->computeDerivativeGroupLinear
= true;
1008 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT
: {
1009 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*features
=
1010 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*)ext
;
1011 features
->ycbcrImageArrays
= true;
1014 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR
: {
1015 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR
*features
=
1016 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR
*)ext
;
1017 features
->uniformBufferStandardLayout
= true;
1020 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT
: {
1021 VkPhysicalDeviceIndexTypeUint8FeaturesEXT
*features
=
1022 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT
*)ext
;
1023 features
->indexTypeUint8
= pdevice
->rad_info
.chip_class
>= GFX8
;
1026 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES_KHR
: {
1027 VkPhysicalDeviceImagelessFramebufferFeaturesKHR
*features
=
1028 (VkPhysicalDeviceImagelessFramebufferFeaturesKHR
*)ext
;
1029 features
->imagelessFramebuffer
= true;
1032 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR
: {
1033 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR
*features
=
1034 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR
*)ext
;
1035 features
->pipelineExecutableInfo
= true;
1042 return radv_GetPhysicalDeviceFeatures(physicalDevice
, &pFeatures
->features
);
1045 void radv_GetPhysicalDeviceProperties(
1046 VkPhysicalDevice physicalDevice
,
1047 VkPhysicalDeviceProperties
* pProperties
)
1049 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1050 VkSampleCountFlags sample_counts
= 0xf;
1052 /* make sure that the entire descriptor set is addressable with a signed
1053 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1054 * be at most 2 GiB. the combined image & samples object count as one of
1055 * both. This limit is for the pipeline layout, not for the set layout, but
1056 * there is no set limit, so we just set a pipeline limit. I don't think
1057 * any app is going to hit this soon. */
1058 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
) /
1059 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1060 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1061 32 /* sampler, largest when combined with image */ +
1062 64 /* sampled image */ +
1063 64 /* storage image */);
1065 VkPhysicalDeviceLimits limits
= {
1066 .maxImageDimension1D
= (1 << 14),
1067 .maxImageDimension2D
= (1 << 14),
1068 .maxImageDimension3D
= (1 << 11),
1069 .maxImageDimensionCube
= (1 << 14),
1070 .maxImageArrayLayers
= (1 << 11),
1071 .maxTexelBufferElements
= 128 * 1024 * 1024,
1072 .maxUniformBufferRange
= UINT32_MAX
,
1073 .maxStorageBufferRange
= UINT32_MAX
,
1074 .maxPushConstantsSize
= MAX_PUSH_CONSTANTS_SIZE
,
1075 .maxMemoryAllocationCount
= UINT32_MAX
,
1076 .maxSamplerAllocationCount
= 64 * 1024,
1077 .bufferImageGranularity
= 64, /* A cache line */
1078 .sparseAddressSpaceSize
= 0xffffffffu
, /* buffer max size */
1079 .maxBoundDescriptorSets
= MAX_SETS
,
1080 .maxPerStageDescriptorSamplers
= max_descriptor_set_size
,
1081 .maxPerStageDescriptorUniformBuffers
= max_descriptor_set_size
,
1082 .maxPerStageDescriptorStorageBuffers
= max_descriptor_set_size
,
1083 .maxPerStageDescriptorSampledImages
= max_descriptor_set_size
,
1084 .maxPerStageDescriptorStorageImages
= max_descriptor_set_size
,
1085 .maxPerStageDescriptorInputAttachments
= max_descriptor_set_size
,
1086 .maxPerStageResources
= max_descriptor_set_size
,
1087 .maxDescriptorSetSamplers
= max_descriptor_set_size
,
1088 .maxDescriptorSetUniformBuffers
= max_descriptor_set_size
,
1089 .maxDescriptorSetUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
,
1090 .maxDescriptorSetStorageBuffers
= max_descriptor_set_size
,
1091 .maxDescriptorSetStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
,
1092 .maxDescriptorSetSampledImages
= max_descriptor_set_size
,
1093 .maxDescriptorSetStorageImages
= max_descriptor_set_size
,
1094 .maxDescriptorSetInputAttachments
= max_descriptor_set_size
,
1095 .maxVertexInputAttributes
= MAX_VERTEX_ATTRIBS
,
1096 .maxVertexInputBindings
= MAX_VBS
,
1097 .maxVertexInputAttributeOffset
= 2047,
1098 .maxVertexInputBindingStride
= 2048,
1099 .maxVertexOutputComponents
= 128,
1100 .maxTessellationGenerationLevel
= 64,
1101 .maxTessellationPatchSize
= 32,
1102 .maxTessellationControlPerVertexInputComponents
= 128,
1103 .maxTessellationControlPerVertexOutputComponents
= 128,
1104 .maxTessellationControlPerPatchOutputComponents
= 120,
1105 .maxTessellationControlTotalOutputComponents
= 4096,
1106 .maxTessellationEvaluationInputComponents
= 128,
1107 .maxTessellationEvaluationOutputComponents
= 128,
1108 .maxGeometryShaderInvocations
= 127,
1109 .maxGeometryInputComponents
= 64,
1110 .maxGeometryOutputComponents
= 128,
1111 .maxGeometryOutputVertices
= 256,
1112 .maxGeometryTotalOutputComponents
= 1024,
1113 .maxFragmentInputComponents
= 128,
1114 .maxFragmentOutputAttachments
= 8,
1115 .maxFragmentDualSrcAttachments
= 1,
1116 .maxFragmentCombinedOutputResources
= 8,
1117 .maxComputeSharedMemorySize
= 32768,
1118 .maxComputeWorkGroupCount
= { 65535, 65535, 65535 },
1119 .maxComputeWorkGroupInvocations
= 2048,
1120 .maxComputeWorkGroupSize
= {
1125 .subPixelPrecisionBits
= 8,
1126 .subTexelPrecisionBits
= 8,
1127 .mipmapPrecisionBits
= 8,
1128 .maxDrawIndexedIndexValue
= UINT32_MAX
,
1129 .maxDrawIndirectCount
= UINT32_MAX
,
1130 .maxSamplerLodBias
= 16,
1131 .maxSamplerAnisotropy
= 16,
1132 .maxViewports
= MAX_VIEWPORTS
,
1133 .maxViewportDimensions
= { (1 << 14), (1 << 14) },
1134 .viewportBoundsRange
= { INT16_MIN
, INT16_MAX
},
1135 .viewportSubPixelBits
= 8,
1136 .minMemoryMapAlignment
= 4096, /* A page */
1137 .minTexelBufferOffsetAlignment
= 1,
1138 .minUniformBufferOffsetAlignment
= 4,
1139 .minStorageBufferOffsetAlignment
= 4,
1140 .minTexelOffset
= -32,
1141 .maxTexelOffset
= 31,
1142 .minTexelGatherOffset
= -32,
1143 .maxTexelGatherOffset
= 31,
1144 .minInterpolationOffset
= -2,
1145 .maxInterpolationOffset
= 2,
1146 .subPixelInterpolationOffsetBits
= 8,
1147 .maxFramebufferWidth
= (1 << 14),
1148 .maxFramebufferHeight
= (1 << 14),
1149 .maxFramebufferLayers
= (1 << 10),
1150 .framebufferColorSampleCounts
= sample_counts
,
1151 .framebufferDepthSampleCounts
= sample_counts
,
1152 .framebufferStencilSampleCounts
= sample_counts
,
1153 .framebufferNoAttachmentsSampleCounts
= sample_counts
,
1154 .maxColorAttachments
= MAX_RTS
,
1155 .sampledImageColorSampleCounts
= sample_counts
,
1156 .sampledImageIntegerSampleCounts
= VK_SAMPLE_COUNT_1_BIT
,
1157 .sampledImageDepthSampleCounts
= sample_counts
,
1158 .sampledImageStencilSampleCounts
= sample_counts
,
1159 .storageImageSampleCounts
= pdevice
->rad_info
.chip_class
>= GFX8
? sample_counts
: VK_SAMPLE_COUNT_1_BIT
,
1160 .maxSampleMaskWords
= 1,
1161 .timestampComputeAndGraphics
= true,
1162 .timestampPeriod
= 1000000.0 / pdevice
->rad_info
.clock_crystal_freq
,
1163 .maxClipDistances
= 8,
1164 .maxCullDistances
= 8,
1165 .maxCombinedClipAndCullDistances
= 8,
1166 .discreteQueuePriorities
= 2,
1167 .pointSizeRange
= { 0.0, 8192.0 },
1168 .lineWidthRange
= { 0.0, 7.9921875 },
1169 .pointSizeGranularity
= (1.0 / 8.0),
1170 .lineWidthGranularity
= (1.0 / 128.0),
1171 .strictLines
= false, /* FINISHME */
1172 .standardSampleLocations
= true,
1173 .optimalBufferCopyOffsetAlignment
= 128,
1174 .optimalBufferCopyRowPitchAlignment
= 128,
1175 .nonCoherentAtomSize
= 64,
1178 *pProperties
= (VkPhysicalDeviceProperties
) {
1179 .apiVersion
= radv_physical_device_api_version(pdevice
),
1180 .driverVersion
= vk_get_driver_version(),
1181 .vendorID
= ATI_VENDOR_ID
,
1182 .deviceID
= pdevice
->rad_info
.pci_id
,
1183 .deviceType
= pdevice
->rad_info
.has_dedicated_vram
? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU
: VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU
,
1185 .sparseProperties
= {0},
1188 strcpy(pProperties
->deviceName
, pdevice
->name
);
1189 memcpy(pProperties
->pipelineCacheUUID
, pdevice
->cache_uuid
, VK_UUID_SIZE
);
1192 void radv_GetPhysicalDeviceProperties2(
1193 VkPhysicalDevice physicalDevice
,
1194 VkPhysicalDeviceProperties2
*pProperties
)
1196 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1197 radv_GetPhysicalDeviceProperties(physicalDevice
, &pProperties
->properties
);
1199 vk_foreach_struct(ext
, pProperties
->pNext
) {
1200 switch (ext
->sType
) {
1201 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR
: {
1202 VkPhysicalDevicePushDescriptorPropertiesKHR
*properties
=
1203 (VkPhysicalDevicePushDescriptorPropertiesKHR
*) ext
;
1204 properties
->maxPushDescriptors
= MAX_PUSH_DESCRIPTORS
;
1207 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES
: {
1208 VkPhysicalDeviceIDProperties
*properties
= (VkPhysicalDeviceIDProperties
*)ext
;
1209 memcpy(properties
->driverUUID
, pdevice
->driver_uuid
, VK_UUID_SIZE
);
1210 memcpy(properties
->deviceUUID
, pdevice
->device_uuid
, VK_UUID_SIZE
);
1211 properties
->deviceLUIDValid
= false;
1214 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES
: {
1215 VkPhysicalDeviceMultiviewProperties
*properties
= (VkPhysicalDeviceMultiviewProperties
*)ext
;
1216 properties
->maxMultiviewViewCount
= MAX_VIEWS
;
1217 properties
->maxMultiviewInstanceIndex
= INT_MAX
;
1220 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES
: {
1221 VkPhysicalDevicePointClippingProperties
*properties
=
1222 (VkPhysicalDevicePointClippingProperties
*)ext
;
1223 properties
->pointClippingBehavior
= VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES
;
1226 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT
: {
1227 VkPhysicalDeviceDiscardRectanglePropertiesEXT
*properties
=
1228 (VkPhysicalDeviceDiscardRectanglePropertiesEXT
*)ext
;
1229 properties
->maxDiscardRectangles
= MAX_DISCARD_RECTANGLES
;
1232 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT
: {
1233 VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*properties
=
1234 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*) ext
;
1235 properties
->minImportedHostPointerAlignment
= 4096;
1238 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES
: {
1239 VkPhysicalDeviceSubgroupProperties
*properties
=
1240 (VkPhysicalDeviceSubgroupProperties
*)ext
;
1241 properties
->subgroupSize
= 64;
1242 properties
->supportedStages
= VK_SHADER_STAGE_ALL
;
1243 properties
->supportedOperations
=
1244 VK_SUBGROUP_FEATURE_BASIC_BIT
|
1245 VK_SUBGROUP_FEATURE_BALLOT_BIT
|
1246 VK_SUBGROUP_FEATURE_QUAD_BIT
|
1247 VK_SUBGROUP_FEATURE_VOTE_BIT
;
1248 if (pdevice
->rad_info
.chip_class
>= GFX8
) {
1249 properties
->supportedOperations
|=
1250 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT
|
1251 VK_SUBGROUP_FEATURE_SHUFFLE_BIT
|
1252 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT
;
1254 properties
->quadOperationsInAllStages
= true;
1257 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES
: {
1258 VkPhysicalDeviceMaintenance3Properties
*properties
=
1259 (VkPhysicalDeviceMaintenance3Properties
*)ext
;
1260 /* Make sure everything is addressable by a signed 32-bit int, and
1261 * our largest descriptors are 96 bytes. */
1262 properties
->maxPerSetDescriptors
= (1ull << 31) / 96;
1263 /* Our buffer size fields allow only this much */
1264 properties
->maxMemoryAllocationSize
= 0xFFFFFFFFull
;
1267 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT
: {
1268 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT
*properties
=
1269 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT
*)ext
;
1270 /* GFX6-8 only support single channel min/max filter. */
1271 properties
->filterMinmaxImageComponentMapping
= pdevice
->rad_info
.chip_class
>= GFX9
;
1272 properties
->filterMinmaxSingleComponentFormats
= true;
1275 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD
: {
1276 VkPhysicalDeviceShaderCorePropertiesAMD
*properties
=
1277 (VkPhysicalDeviceShaderCorePropertiesAMD
*)ext
;
1279 /* Shader engines. */
1280 properties
->shaderEngineCount
=
1281 pdevice
->rad_info
.max_se
;
1282 properties
->shaderArraysPerEngineCount
=
1283 pdevice
->rad_info
.max_sh_per_se
;
1284 properties
->computeUnitsPerShaderArray
=
1285 pdevice
->rad_info
.num_good_cu_per_sh
;
1286 properties
->simdPerComputeUnit
= 4;
1287 properties
->wavefrontsPerSimd
=
1288 pdevice
->rad_info
.family
== CHIP_TONGA
||
1289 pdevice
->rad_info
.family
== CHIP_ICELAND
||
1290 pdevice
->rad_info
.family
== CHIP_POLARIS10
||
1291 pdevice
->rad_info
.family
== CHIP_POLARIS11
||
1292 pdevice
->rad_info
.family
== CHIP_POLARIS12
||
1293 pdevice
->rad_info
.family
== CHIP_VEGAM
? 8 : 10;
1294 properties
->wavefrontSize
= 64;
1297 properties
->sgprsPerSimd
=
1298 ac_get_num_physical_sgprs(pdevice
->rad_info
.chip_class
);
1299 properties
->minSgprAllocation
=
1300 pdevice
->rad_info
.chip_class
>= GFX8
? 16 : 8;
1301 properties
->maxSgprAllocation
=
1302 pdevice
->rad_info
.family
== CHIP_TONGA
||
1303 pdevice
->rad_info
.family
== CHIP_ICELAND
? 96 : 104;
1304 properties
->sgprAllocationGranularity
=
1305 pdevice
->rad_info
.chip_class
>= GFX8
? 16 : 8;
1308 properties
->vgprsPerSimd
= RADV_NUM_PHYSICAL_VGPRS
;
1309 properties
->minVgprAllocation
= 4;
1310 properties
->maxVgprAllocation
= 256;
1311 properties
->vgprAllocationGranularity
= 4;
1314 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD
: {
1315 VkPhysicalDeviceShaderCoreProperties2AMD
*properties
=
1316 (VkPhysicalDeviceShaderCoreProperties2AMD
*)ext
;
1318 properties
->shaderCoreFeatures
= 0;
1319 properties
->activeComputeUnitCount
=
1320 pdevice
->rad_info
.num_good_compute_units
;
1323 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT
: {
1324 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*properties
=
1325 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*)ext
;
1326 properties
->maxVertexAttribDivisor
= UINT32_MAX
;
1329 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT
: {
1330 VkPhysicalDeviceDescriptorIndexingPropertiesEXT
*properties
=
1331 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT
*)ext
;
1332 properties
->maxUpdateAfterBindDescriptorsInAllPools
= UINT32_MAX
/ 64;
1333 properties
->shaderUniformBufferArrayNonUniformIndexingNative
= false;
1334 properties
->shaderSampledImageArrayNonUniformIndexingNative
= false;
1335 properties
->shaderStorageBufferArrayNonUniformIndexingNative
= false;
1336 properties
->shaderStorageImageArrayNonUniformIndexingNative
= false;
1337 properties
->shaderInputAttachmentArrayNonUniformIndexingNative
= false;
1338 properties
->robustBufferAccessUpdateAfterBind
= false;
1339 properties
->quadDivergentImplicitLod
= false;
1341 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
-
1342 MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_INLINE_UNIFORM_BLOCK_COUNT
) /
1343 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1344 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1345 32 /* sampler, largest when combined with image */ +
1346 64 /* sampled image */ +
1347 64 /* storage image */);
1348 properties
->maxPerStageDescriptorUpdateAfterBindSamplers
= max_descriptor_set_size
;
1349 properties
->maxPerStageDescriptorUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1350 properties
->maxPerStageDescriptorUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1351 properties
->maxPerStageDescriptorUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1352 properties
->maxPerStageDescriptorUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1353 properties
->maxPerStageDescriptorUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1354 properties
->maxPerStageUpdateAfterBindResources
= max_descriptor_set_size
;
1355 properties
->maxDescriptorSetUpdateAfterBindSamplers
= max_descriptor_set_size
;
1356 properties
->maxDescriptorSetUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1357 properties
->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
;
1358 properties
->maxDescriptorSetUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1359 properties
->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
;
1360 properties
->maxDescriptorSetUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1361 properties
->maxDescriptorSetUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1362 properties
->maxDescriptorSetUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1365 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES
: {
1366 VkPhysicalDeviceProtectedMemoryProperties
*properties
=
1367 (VkPhysicalDeviceProtectedMemoryProperties
*)ext
;
1368 properties
->protectedNoFault
= false;
1371 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT
: {
1372 VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*properties
=
1373 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*)ext
;
1374 properties
->primitiveOverestimationSize
= 0;
1375 properties
->maxExtraPrimitiveOverestimationSize
= 0;
1376 properties
->extraPrimitiveOverestimationSizeGranularity
= 0;
1377 properties
->primitiveUnderestimation
= VK_FALSE
;
1378 properties
->conservativePointAndLineRasterization
= VK_FALSE
;
1379 properties
->degenerateTrianglesRasterized
= VK_FALSE
;
1380 properties
->degenerateLinesRasterized
= VK_FALSE
;
1381 properties
->fullyCoveredFragmentShaderInputVariable
= VK_FALSE
;
1382 properties
->conservativeRasterizationPostDepthCoverage
= VK_FALSE
;
1385 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT
: {
1386 VkPhysicalDevicePCIBusInfoPropertiesEXT
*properties
=
1387 (VkPhysicalDevicePCIBusInfoPropertiesEXT
*)ext
;
1388 properties
->pciDomain
= pdevice
->bus_info
.domain
;
1389 properties
->pciBus
= pdevice
->bus_info
.bus
;
1390 properties
->pciDevice
= pdevice
->bus_info
.dev
;
1391 properties
->pciFunction
= pdevice
->bus_info
.func
;
1394 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR
: {
1395 VkPhysicalDeviceDriverPropertiesKHR
*driver_props
=
1396 (VkPhysicalDeviceDriverPropertiesKHR
*) ext
;
1398 driver_props
->driverID
= VK_DRIVER_ID_MESA_RADV_KHR
;
1399 snprintf(driver_props
->driverName
, VK_MAX_DRIVER_NAME_SIZE_KHR
, "radv");
1400 snprintf(driver_props
->driverInfo
, VK_MAX_DRIVER_INFO_SIZE_KHR
,
1401 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1402 " (LLVM " MESA_LLVM_VERSION_STRING
")");
1404 driver_props
->conformanceVersion
= (VkConformanceVersionKHR
) {
1412 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT
: {
1413 VkPhysicalDeviceTransformFeedbackPropertiesEXT
*properties
=
1414 (VkPhysicalDeviceTransformFeedbackPropertiesEXT
*)ext
;
1415 properties
->maxTransformFeedbackStreams
= MAX_SO_STREAMS
;
1416 properties
->maxTransformFeedbackBuffers
= MAX_SO_BUFFERS
;
1417 properties
->maxTransformFeedbackBufferSize
= UINT32_MAX
;
1418 properties
->maxTransformFeedbackStreamDataSize
= 512;
1419 properties
->maxTransformFeedbackBufferDataSize
= UINT32_MAX
;
1420 properties
->maxTransformFeedbackBufferDataStride
= 512;
1421 properties
->transformFeedbackQueries
= true;
1422 properties
->transformFeedbackStreamsLinesTriangles
= true;
1423 properties
->transformFeedbackRasterizationStreamSelect
= false;
1424 properties
->transformFeedbackDraw
= true;
1427 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT
: {
1428 VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*props
=
1429 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*)ext
;
1431 props
->maxInlineUniformBlockSize
= MAX_INLINE_UNIFORM_BLOCK_SIZE
;
1432 props
->maxPerStageDescriptorInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1433 props
->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1434 props
->maxDescriptorSetInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1435 props
->maxDescriptorSetUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1438 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT
: {
1439 VkPhysicalDeviceSampleLocationsPropertiesEXT
*properties
=
1440 (VkPhysicalDeviceSampleLocationsPropertiesEXT
*)ext
;
1441 properties
->sampleLocationSampleCounts
= VK_SAMPLE_COUNT_2_BIT
|
1442 VK_SAMPLE_COUNT_4_BIT
|
1443 VK_SAMPLE_COUNT_8_BIT
;
1444 properties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2 , 2 };
1445 properties
->sampleLocationCoordinateRange
[0] = 0.0f
;
1446 properties
->sampleLocationCoordinateRange
[1] = 0.9375f
;
1447 properties
->sampleLocationSubPixelBits
= 4;
1448 properties
->variableSampleLocations
= VK_FALSE
;
1451 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES_KHR
: {
1452 VkPhysicalDeviceDepthStencilResolvePropertiesKHR
*properties
=
1453 (VkPhysicalDeviceDepthStencilResolvePropertiesKHR
*)ext
;
1455 /* We support all of the depth resolve modes */
1456 properties
->supportedDepthResolveModes
=
1457 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
|
1458 VK_RESOLVE_MODE_AVERAGE_BIT_KHR
|
1459 VK_RESOLVE_MODE_MIN_BIT_KHR
|
1460 VK_RESOLVE_MODE_MAX_BIT_KHR
;
1462 /* Average doesn't make sense for stencil so we don't support that */
1463 properties
->supportedStencilResolveModes
=
1464 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
|
1465 VK_RESOLVE_MODE_MIN_BIT_KHR
|
1466 VK_RESOLVE_MODE_MAX_BIT_KHR
;
1468 properties
->independentResolveNone
= VK_TRUE
;
1469 properties
->independentResolve
= VK_TRUE
;
1478 static void radv_get_physical_device_queue_family_properties(
1479 struct radv_physical_device
* pdevice
,
1481 VkQueueFamilyProperties
** pQueueFamilyProperties
)
1483 int num_queue_families
= 1;
1485 if (pdevice
->rad_info
.num_compute_rings
> 0 &&
1486 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
))
1487 num_queue_families
++;
1489 if (pQueueFamilyProperties
== NULL
) {
1490 *pCount
= num_queue_families
;
1499 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
1500 .queueFlags
= VK_QUEUE_GRAPHICS_BIT
|
1501 VK_QUEUE_COMPUTE_BIT
|
1502 VK_QUEUE_TRANSFER_BIT
|
1503 VK_QUEUE_SPARSE_BINDING_BIT
,
1505 .timestampValidBits
= 64,
1506 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
1511 if (pdevice
->rad_info
.num_compute_rings
> 0 &&
1512 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
)) {
1513 if (*pCount
> idx
) {
1514 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
1515 .queueFlags
= VK_QUEUE_COMPUTE_BIT
|
1516 VK_QUEUE_TRANSFER_BIT
|
1517 VK_QUEUE_SPARSE_BINDING_BIT
,
1518 .queueCount
= pdevice
->rad_info
.num_compute_rings
,
1519 .timestampValidBits
= 64,
1520 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
1528 void radv_GetPhysicalDeviceQueueFamilyProperties(
1529 VkPhysicalDevice physicalDevice
,
1531 VkQueueFamilyProperties
* pQueueFamilyProperties
)
1533 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1534 if (!pQueueFamilyProperties
) {
1535 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
1538 VkQueueFamilyProperties
*properties
[] = {
1539 pQueueFamilyProperties
+ 0,
1540 pQueueFamilyProperties
+ 1,
1541 pQueueFamilyProperties
+ 2,
1543 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
1544 assert(*pCount
<= 3);
1547 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1548 VkPhysicalDevice physicalDevice
,
1550 VkQueueFamilyProperties2
*pQueueFamilyProperties
)
1552 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1553 if (!pQueueFamilyProperties
) {
1554 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
1557 VkQueueFamilyProperties
*properties
[] = {
1558 &pQueueFamilyProperties
[0].queueFamilyProperties
,
1559 &pQueueFamilyProperties
[1].queueFamilyProperties
,
1560 &pQueueFamilyProperties
[2].queueFamilyProperties
,
1562 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
1563 assert(*pCount
<= 3);
1566 void radv_GetPhysicalDeviceMemoryProperties(
1567 VkPhysicalDevice physicalDevice
,
1568 VkPhysicalDeviceMemoryProperties
*pMemoryProperties
)
1570 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
1572 *pMemoryProperties
= physical_device
->memory_properties
;
1576 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice
,
1577 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memoryBudget
)
1579 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
1580 VkPhysicalDeviceMemoryProperties
*memory_properties
= &device
->memory_properties
;
1581 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
1582 uint64_t vram_size
= radv_get_vram_size(device
);
1583 uint64_t gtt_size
= device
->rad_info
.gart_size
;
1584 uint64_t heap_budget
, heap_usage
;
1586 /* For all memory heaps, the computation of budget is as follow:
1587 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1589 * The Vulkan spec 1.1.97 says that the budget should include any
1590 * currently allocated device memory.
1592 * Note that the application heap usages are not really accurate (eg.
1593 * in presence of shared buffers).
1595 for (int i
= 0; i
< device
->memory_properties
.memoryTypeCount
; i
++) {
1596 uint32_t heap_index
= device
->memory_properties
.memoryTypes
[i
].heapIndex
;
1598 switch (device
->mem_type_indices
[i
]) {
1599 case RADV_MEM_TYPE_VRAM
:
1600 heap_usage
= device
->ws
->query_value(device
->ws
,
1601 RADEON_ALLOCATED_VRAM
);
1603 heap_budget
= vram_size
-
1604 device
->ws
->query_value(device
->ws
, RADEON_VRAM_USAGE
) +
1607 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
1608 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
1610 case RADV_MEM_TYPE_VRAM_CPU_ACCESS
:
1611 heap_usage
= device
->ws
->query_value(device
->ws
,
1612 RADEON_ALLOCATED_VRAM_VIS
);
1614 heap_budget
= visible_vram_size
-
1615 device
->ws
->query_value(device
->ws
, RADEON_VRAM_VIS_USAGE
) +
1618 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
1619 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
1621 case RADV_MEM_TYPE_GTT_WRITE_COMBINE
:
1622 heap_usage
= device
->ws
->query_value(device
->ws
,
1623 RADEON_ALLOCATED_GTT
);
1625 heap_budget
= gtt_size
-
1626 device
->ws
->query_value(device
->ws
, RADEON_GTT_USAGE
) +
1629 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
1630 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
1637 /* The heapBudget and heapUsage values must be zero for array elements
1638 * greater than or equal to
1639 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1641 for (uint32_t i
= memory_properties
->memoryHeapCount
; i
< VK_MAX_MEMORY_HEAPS
; i
++) {
1642 memoryBudget
->heapBudget
[i
] = 0;
1643 memoryBudget
->heapUsage
[i
] = 0;
1647 void radv_GetPhysicalDeviceMemoryProperties2(
1648 VkPhysicalDevice physicalDevice
,
1649 VkPhysicalDeviceMemoryProperties2
*pMemoryProperties
)
1651 radv_GetPhysicalDeviceMemoryProperties(physicalDevice
,
1652 &pMemoryProperties
->memoryProperties
);
1654 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memory_budget
=
1655 vk_find_struct(pMemoryProperties
->pNext
,
1656 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT
);
1658 radv_get_memory_budget_properties(physicalDevice
, memory_budget
);
1661 VkResult
radv_GetMemoryHostPointerPropertiesEXT(
1663 VkExternalMemoryHandleTypeFlagBits handleType
,
1664 const void *pHostPointer
,
1665 VkMemoryHostPointerPropertiesEXT
*pMemoryHostPointerProperties
)
1667 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1671 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
: {
1672 const struct radv_physical_device
*physical_device
= device
->physical_device
;
1673 uint32_t memoryTypeBits
= 0;
1674 for (int i
= 0; i
< physical_device
->memory_properties
.memoryTypeCount
; i
++) {
1675 if (physical_device
->mem_type_indices
[i
] == RADV_MEM_TYPE_GTT_CACHED
) {
1676 memoryTypeBits
= (1 << i
);
1680 pMemoryHostPointerProperties
->memoryTypeBits
= memoryTypeBits
;
1684 return VK_ERROR_INVALID_EXTERNAL_HANDLE
;
1688 static enum radeon_ctx_priority
1689 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT
*pObj
)
1691 /* Default to MEDIUM when a specific global priority isn't requested */
1693 return RADEON_CTX_PRIORITY_MEDIUM
;
1695 switch(pObj
->globalPriority
) {
1696 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT
:
1697 return RADEON_CTX_PRIORITY_REALTIME
;
1698 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT
:
1699 return RADEON_CTX_PRIORITY_HIGH
;
1700 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT
:
1701 return RADEON_CTX_PRIORITY_MEDIUM
;
1702 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT
:
1703 return RADEON_CTX_PRIORITY_LOW
;
1705 unreachable("Illegal global priority value");
1706 return RADEON_CTX_PRIORITY_INVALID
;
1711 radv_queue_init(struct radv_device
*device
, struct radv_queue
*queue
,
1712 uint32_t queue_family_index
, int idx
,
1713 VkDeviceQueueCreateFlags flags
,
1714 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
)
1716 queue
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1717 queue
->device
= device
;
1718 queue
->queue_family_index
= queue_family_index
;
1719 queue
->queue_idx
= idx
;
1720 queue
->priority
= radv_get_queue_global_priority(global_priority
);
1721 queue
->flags
= flags
;
1723 queue
->hw_ctx
= device
->ws
->ctx_create(device
->ws
, queue
->priority
);
1725 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1731 radv_queue_finish(struct radv_queue
*queue
)
1734 queue
->device
->ws
->ctx_destroy(queue
->hw_ctx
);
1736 if (queue
->initial_full_flush_preamble_cs
)
1737 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
1738 if (queue
->initial_preamble_cs
)
1739 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
1740 if (queue
->continue_preamble_cs
)
1741 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
1742 if (queue
->descriptor_bo
)
1743 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
1744 if (queue
->scratch_bo
)
1745 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
1746 if (queue
->esgs_ring_bo
)
1747 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
1748 if (queue
->gsvs_ring_bo
)
1749 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
1750 if (queue
->tess_rings_bo
)
1751 queue
->device
->ws
->buffer_destroy(queue
->tess_rings_bo
);
1752 if (queue
->compute_scratch_bo
)
1753 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
1757 radv_bo_list_init(struct radv_bo_list
*bo_list
)
1759 pthread_mutex_init(&bo_list
->mutex
, NULL
);
1760 bo_list
->list
.count
= bo_list
->capacity
= 0;
1761 bo_list
->list
.bos
= NULL
;
1765 radv_bo_list_finish(struct radv_bo_list
*bo_list
)
1767 free(bo_list
->list
.bos
);
1768 pthread_mutex_destroy(&bo_list
->mutex
);
1771 static VkResult
radv_bo_list_add(struct radv_device
*device
,
1772 struct radeon_winsys_bo
*bo
)
1774 struct radv_bo_list
*bo_list
= &device
->bo_list
;
1779 if (unlikely(!device
->use_global_bo_list
))
1782 pthread_mutex_lock(&bo_list
->mutex
);
1783 if (bo_list
->list
.count
== bo_list
->capacity
) {
1784 unsigned capacity
= MAX2(4, bo_list
->capacity
* 2);
1785 void *data
= realloc(bo_list
->list
.bos
, capacity
* sizeof(struct radeon_winsys_bo
*));
1788 pthread_mutex_unlock(&bo_list
->mutex
);
1789 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1792 bo_list
->list
.bos
= (struct radeon_winsys_bo
**)data
;
1793 bo_list
->capacity
= capacity
;
1796 bo_list
->list
.bos
[bo_list
->list
.count
++] = bo
;
1797 pthread_mutex_unlock(&bo_list
->mutex
);
1801 static void radv_bo_list_remove(struct radv_device
*device
,
1802 struct radeon_winsys_bo
*bo
)
1804 struct radv_bo_list
*bo_list
= &device
->bo_list
;
1809 if (unlikely(!device
->use_global_bo_list
))
1812 pthread_mutex_lock(&bo_list
->mutex
);
1813 for(unsigned i
= 0; i
< bo_list
->list
.count
; ++i
) {
1814 if (bo_list
->list
.bos
[i
] == bo
) {
1815 bo_list
->list
.bos
[i
] = bo_list
->list
.bos
[bo_list
->list
.count
- 1];
1816 --bo_list
->list
.count
;
1820 pthread_mutex_unlock(&bo_list
->mutex
);
1824 radv_device_init_gs_info(struct radv_device
*device
)
1826 device
->gs_table_depth
= ac_get_gs_table_depth(device
->physical_device
->rad_info
.chip_class
,
1827 device
->physical_device
->rad_info
.family
);
1830 static int radv_get_device_extension_index(const char *name
)
1832 for (unsigned i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; ++i
) {
1833 if (strcmp(name
, radv_device_extensions
[i
].extensionName
) == 0)
1840 radv_get_int_debug_option(const char *name
, int default_value
)
1847 result
= default_value
;
1851 result
= strtol(str
, &endptr
, 0);
1852 if (str
== endptr
) {
1853 /* No digits founs. */
1854 result
= default_value
;
1861 VkResult
radv_CreateDevice(
1862 VkPhysicalDevice physicalDevice
,
1863 const VkDeviceCreateInfo
* pCreateInfo
,
1864 const VkAllocationCallbacks
* pAllocator
,
1867 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
1869 struct radv_device
*device
;
1871 bool keep_shader_info
= false;
1873 /* Check enabled features */
1874 if (pCreateInfo
->pEnabledFeatures
) {
1875 VkPhysicalDeviceFeatures supported_features
;
1876 radv_GetPhysicalDeviceFeatures(physicalDevice
, &supported_features
);
1877 VkBool32
*supported_feature
= (VkBool32
*)&supported_features
;
1878 VkBool32
*enabled_feature
= (VkBool32
*)pCreateInfo
->pEnabledFeatures
;
1879 unsigned num_features
= sizeof(VkPhysicalDeviceFeatures
) / sizeof(VkBool32
);
1880 for (uint32_t i
= 0; i
< num_features
; i
++) {
1881 if (enabled_feature
[i
] && !supported_feature
[i
])
1882 return vk_error(physical_device
->instance
, VK_ERROR_FEATURE_NOT_PRESENT
);
1886 device
= vk_zalloc2(&physical_device
->instance
->alloc
, pAllocator
,
1888 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
1890 return vk_error(physical_device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1892 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1893 device
->instance
= physical_device
->instance
;
1894 device
->physical_device
= physical_device
;
1896 device
->ws
= physical_device
->ws
;
1898 device
->alloc
= *pAllocator
;
1900 device
->alloc
= physical_device
->instance
->alloc
;
1902 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
1903 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
1904 int index
= radv_get_device_extension_index(ext_name
);
1905 if (index
< 0 || !physical_device
->supported_extensions
.extensions
[index
]) {
1906 vk_free(&device
->alloc
, device
);
1907 return vk_error(physical_device
->instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
1910 device
->enabled_extensions
.extensions
[index
] = true;
1913 keep_shader_info
= device
->enabled_extensions
.AMD_shader_info
;
1915 /* With update after bind we can't attach bo's to the command buffer
1916 * from the descriptor set anymore, so we have to use a global BO list.
1918 device
->use_global_bo_list
=
1919 (device
->instance
->perftest_flags
& RADV_PERFTEST_BO_LIST
) ||
1920 device
->enabled_extensions
.EXT_descriptor_indexing
||
1921 device
->enabled_extensions
.EXT_buffer_device_address
;
1923 device
->robust_buffer_access
= pCreateInfo
->pEnabledFeatures
&&
1924 pCreateInfo
->pEnabledFeatures
->robustBufferAccess
;
1926 mtx_init(&device
->shader_slab_mutex
, mtx_plain
);
1927 list_inithead(&device
->shader_slabs
);
1929 radv_bo_list_init(&device
->bo_list
);
1931 for (unsigned i
= 0; i
< pCreateInfo
->queueCreateInfoCount
; i
++) {
1932 const VkDeviceQueueCreateInfo
*queue_create
= &pCreateInfo
->pQueueCreateInfos
[i
];
1933 uint32_t qfi
= queue_create
->queueFamilyIndex
;
1934 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
=
1935 vk_find_struct_const(queue_create
->pNext
, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT
);
1937 assert(!global_priority
|| device
->physical_device
->rad_info
.has_ctx_priority
);
1939 device
->queues
[qfi
] = vk_alloc(&device
->alloc
,
1940 queue_create
->queueCount
* sizeof(struct radv_queue
), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
1941 if (!device
->queues
[qfi
]) {
1942 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
1946 memset(device
->queues
[qfi
], 0, queue_create
->queueCount
* sizeof(struct radv_queue
));
1948 device
->queue_count
[qfi
] = queue_create
->queueCount
;
1950 for (unsigned q
= 0; q
< queue_create
->queueCount
; q
++) {
1951 result
= radv_queue_init(device
, &device
->queues
[qfi
][q
],
1952 qfi
, q
, queue_create
->flags
,
1954 if (result
!= VK_SUCCESS
)
1959 device
->pbb_allowed
= device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
1960 !(device
->instance
->debug_flags
& RADV_DEBUG_NOBINNING
);
1962 device
->dfsm_allowed
= device
->pbb_allowed
&&
1963 (device
->physical_device
->rad_info
.family
== CHIP_RAVEN
||
1964 device
->physical_device
->rad_info
.family
== CHIP_RAVEN2
||
1965 device
->physical_device
->rad_info
.family
== CHIP_RENOIR
);
1968 device
->always_use_syncobj
= device
->physical_device
->rad_info
.has_syncobj_wait_for_submit
;
1971 /* The maximum number of scratch waves. Scratch space isn't divided
1972 * evenly between CUs. The number is only a function of the number of CUs.
1973 * We can decrease the constant to decrease the scratch buffer size.
1975 * sctx->scratch_waves must be >= the maximum possible size of
1976 * 1 threadgroup, so that the hw doesn't hang from being unable
1979 * The recommended value is 4 per CU at most. Higher numbers don't
1980 * bring much benefit, but they still occupy chip resources (think
1981 * async compute). I've seen ~2% performance difference between 4 and 32.
1983 uint32_t max_threads_per_block
= 2048;
1984 device
->scratch_waves
= MAX2(32 * physical_device
->rad_info
.num_good_compute_units
,
1985 max_threads_per_block
/ 64);
1987 device
->dispatch_initiator
= S_00B800_COMPUTE_SHADER_EN(1) |
1988 S_00B800_CS_W32_EN(device
->physical_device
->cs_wave_size
== 32);
1990 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
1991 /* If the KMD allows it (there is a KMD hw register for it),
1992 * allow launching waves out-of-order.
1994 device
->dispatch_initiator
|= S_00B800_ORDER_MODE(1);
1997 radv_device_init_gs_info(device
);
1999 device
->tess_offchip_block_dw_size
=
2000 device
->physical_device
->rad_info
.family
== CHIP_HAWAII
? 4096 : 8192;
2001 device
->has_distributed_tess
=
2002 device
->physical_device
->rad_info
.chip_class
>= GFX8
&&
2003 device
->physical_device
->rad_info
.max_se
>= 2;
2005 if (getenv("RADV_TRACE_FILE")) {
2006 const char *filename
= getenv("RADV_TRACE_FILE");
2008 keep_shader_info
= true;
2010 if (!radv_init_trace(device
))
2013 fprintf(stderr
, "*****************************************************************************\n");
2014 fprintf(stderr
, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
2015 fprintf(stderr
, "*****************************************************************************\n");
2017 fprintf(stderr
, "Trace file will be dumped to %s\n", filename
);
2018 radv_dump_enabled_options(device
, stderr
);
2021 device
->keep_shader_info
= keep_shader_info
;
2023 result
= radv_device_init_meta(device
);
2024 if (result
!= VK_SUCCESS
)
2027 radv_device_init_msaa(device
);
2029 for (int family
= 0; family
< RADV_MAX_QUEUE_FAMILIES
; ++family
) {
2030 device
->empty_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
2032 case RADV_QUEUE_GENERAL
:
2033 /* Since amdgpu version 3.6.0, CONTEXT_CONTROL is emitted by the kernel */
2034 if (device
->physical_device
->rad_info
.drm_minor
< 6) {
2035 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2036 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_LOAD_ENABLE(1));
2037 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_SHADOW_ENABLE(1));
2040 case RADV_QUEUE_COMPUTE
:
2041 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_NOP
, 0, 0));
2042 radeon_emit(device
->empty_cs
[family
], 0);
2045 device
->ws
->cs_finalize(device
->empty_cs
[family
]);
2048 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
2049 cik_create_gfx_config(device
);
2051 VkPipelineCacheCreateInfo ci
;
2052 ci
.sType
= VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
;
2055 ci
.pInitialData
= NULL
;
2056 ci
.initialDataSize
= 0;
2058 result
= radv_CreatePipelineCache(radv_device_to_handle(device
),
2060 if (result
!= VK_SUCCESS
)
2063 device
->mem_cache
= radv_pipeline_cache_from_handle(pc
);
2065 device
->force_aniso
=
2066 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2067 if (device
->force_aniso
>= 0) {
2068 fprintf(stderr
, "radv: Forcing anisotropy filter to %ix\n",
2069 1 << util_logbase2(device
->force_aniso
));
2072 *pDevice
= radv_device_to_handle(device
);
2076 radv_device_finish_meta(device
);
2078 radv_bo_list_finish(&device
->bo_list
);
2080 if (device
->trace_bo
)
2081 device
->ws
->buffer_destroy(device
->trace_bo
);
2083 if (device
->gfx_init
)
2084 device
->ws
->buffer_destroy(device
->gfx_init
);
2086 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
2087 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
2088 radv_queue_finish(&device
->queues
[i
][q
]);
2089 if (device
->queue_count
[i
])
2090 vk_free(&device
->alloc
, device
->queues
[i
]);
2093 vk_free(&device
->alloc
, device
);
2097 void radv_DestroyDevice(
2099 const VkAllocationCallbacks
* pAllocator
)
2101 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2106 if (device
->trace_bo
)
2107 device
->ws
->buffer_destroy(device
->trace_bo
);
2109 if (device
->gfx_init
)
2110 device
->ws
->buffer_destroy(device
->gfx_init
);
2112 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
2113 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
2114 radv_queue_finish(&device
->queues
[i
][q
]);
2115 if (device
->queue_count
[i
])
2116 vk_free(&device
->alloc
, device
->queues
[i
]);
2117 if (device
->empty_cs
[i
])
2118 device
->ws
->cs_destroy(device
->empty_cs
[i
]);
2120 radv_device_finish_meta(device
);
2122 VkPipelineCache pc
= radv_pipeline_cache_to_handle(device
->mem_cache
);
2123 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
2125 radv_destroy_shader_slabs(device
);
2127 radv_bo_list_finish(&device
->bo_list
);
2128 vk_free(&device
->alloc
, device
);
2131 VkResult
radv_EnumerateInstanceLayerProperties(
2132 uint32_t* pPropertyCount
,
2133 VkLayerProperties
* pProperties
)
2135 if (pProperties
== NULL
) {
2136 *pPropertyCount
= 0;
2140 /* None supported at this time */
2141 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
2144 VkResult
radv_EnumerateDeviceLayerProperties(
2145 VkPhysicalDevice physicalDevice
,
2146 uint32_t* pPropertyCount
,
2147 VkLayerProperties
* pProperties
)
2149 if (pProperties
== NULL
) {
2150 *pPropertyCount
= 0;
2154 /* None supported at this time */
2155 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
2158 void radv_GetDeviceQueue2(
2160 const VkDeviceQueueInfo2
* pQueueInfo
,
2163 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2164 struct radv_queue
*queue
;
2166 queue
= &device
->queues
[pQueueInfo
->queueFamilyIndex
][pQueueInfo
->queueIndex
];
2167 if (pQueueInfo
->flags
!= queue
->flags
) {
2168 /* From the Vulkan 1.1.70 spec:
2170 * "The queue returned by vkGetDeviceQueue2 must have the same
2171 * flags value from this structure as that used at device
2172 * creation time in a VkDeviceQueueCreateInfo instance. If no
2173 * matching flags were specified at device creation time then
2174 * pQueue will return VK_NULL_HANDLE."
2176 *pQueue
= VK_NULL_HANDLE
;
2180 *pQueue
= radv_queue_to_handle(queue
);
2183 void radv_GetDeviceQueue(
2185 uint32_t queueFamilyIndex
,
2186 uint32_t queueIndex
,
2189 const VkDeviceQueueInfo2 info
= (VkDeviceQueueInfo2
) {
2190 .sType
= VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2
,
2191 .queueFamilyIndex
= queueFamilyIndex
,
2192 .queueIndex
= queueIndex
2195 radv_GetDeviceQueue2(_device
, &info
, pQueue
);
2199 fill_geom_tess_rings(struct radv_queue
*queue
,
2201 bool add_sample_positions
,
2202 uint32_t esgs_ring_size
,
2203 struct radeon_winsys_bo
*esgs_ring_bo
,
2204 uint32_t gsvs_ring_size
,
2205 struct radeon_winsys_bo
*gsvs_ring_bo
,
2206 uint32_t tess_factor_ring_size
,
2207 uint32_t tess_offchip_ring_offset
,
2208 uint32_t tess_offchip_ring_size
,
2209 struct radeon_winsys_bo
*tess_rings_bo
)
2211 uint32_t *desc
= &map
[4];
2214 uint64_t esgs_va
= radv_buffer_get_va(esgs_ring_bo
);
2216 /* stride 0, num records - size, add tid, swizzle, elsize4,
2219 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32) |
2220 S_008F04_SWIZZLE_ENABLE(true);
2221 desc
[2] = esgs_ring_size
;
2222 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2223 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2224 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2225 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2226 S_008F0C_INDEX_STRIDE(3) |
2227 S_008F0C_ADD_TID_ENABLE(1);
2229 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2230 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2231 S_008F0C_OOB_SELECT(2) |
2232 S_008F0C_RESOURCE_LEVEL(1);
2234 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2235 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2236 S_008F0C_ELEMENT_SIZE(1);
2239 /* GS entry for ES->GS ring */
2240 /* stride 0, num records - size, elsize0,
2243 desc
[5] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32);
2244 desc
[6] = esgs_ring_size
;
2245 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2246 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2247 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2248 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2250 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2251 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2252 S_008F0C_OOB_SELECT(2) |
2253 S_008F0C_RESOURCE_LEVEL(1);
2255 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2256 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2263 uint64_t gsvs_va
= radv_buffer_get_va(gsvs_ring_bo
);
2265 /* VS entry for GS->VS ring */
2266 /* stride 0, num records - size, elsize0,
2269 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32);
2270 desc
[2] = gsvs_ring_size
;
2271 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2272 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2273 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2274 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2276 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2277 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2278 S_008F0C_OOB_SELECT(2) |
2279 S_008F0C_RESOURCE_LEVEL(1);
2281 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2282 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2285 /* stride gsvs_itemsize, num records 64
2286 elsize 4, index stride 16 */
2287 /* shader will patch stride and desc[2] */
2289 desc
[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32) |
2290 S_008F04_SWIZZLE_ENABLE(1);
2292 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2293 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2294 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2295 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2296 S_008F0C_INDEX_STRIDE(1) |
2297 S_008F0C_ADD_TID_ENABLE(true);
2299 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2300 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2301 S_008F0C_OOB_SELECT(2) |
2302 S_008F0C_RESOURCE_LEVEL(1);
2304 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2305 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2306 S_008F0C_ELEMENT_SIZE(1);
2313 if (tess_rings_bo
) {
2314 uint64_t tess_va
= radv_buffer_get_va(tess_rings_bo
);
2315 uint64_t tess_offchip_va
= tess_va
+ tess_offchip_ring_offset
;
2318 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_va
>> 32);
2319 desc
[2] = tess_factor_ring_size
;
2320 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2321 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2322 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2323 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2325 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2326 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2327 S_008F0C_OOB_SELECT(3) |
2328 S_008F0C_RESOURCE_LEVEL(1);
2330 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2331 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2334 desc
[4] = tess_offchip_va
;
2335 desc
[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va
>> 32);
2336 desc
[6] = tess_offchip_ring_size
;
2337 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2338 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2339 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2340 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2342 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2343 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2344 S_008F0C_OOB_SELECT(3) |
2345 S_008F0C_RESOURCE_LEVEL(1);
2347 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2348 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2354 if (add_sample_positions
) {
2355 /* add sample positions after all rings */
2356 memcpy(desc
, queue
->device
->sample_locations_1x
, 8);
2358 memcpy(desc
, queue
->device
->sample_locations_2x
, 16);
2360 memcpy(desc
, queue
->device
->sample_locations_4x
, 32);
2362 memcpy(desc
, queue
->device
->sample_locations_8x
, 64);
2367 radv_get_hs_offchip_param(struct radv_device
*device
, uint32_t *max_offchip_buffers_p
)
2369 bool double_offchip_buffers
= device
->physical_device
->rad_info
.chip_class
>= GFX7
&&
2370 device
->physical_device
->rad_info
.family
!= CHIP_CARRIZO
&&
2371 device
->physical_device
->rad_info
.family
!= CHIP_STONEY
;
2372 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
2373 unsigned max_offchip_buffers
;
2374 unsigned offchip_granularity
;
2375 unsigned hs_offchip_param
;
2379 * This must be one less than the maximum number due to a hw limitation.
2380 * Various hardware bugs need thGFX7
2383 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2384 * Gfx7 should limit max_offchip_buffers to 508
2385 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2387 * Follow AMDVLK here.
2389 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2390 max_offchip_buffers_per_se
= 256;
2391 } else if (device
->physical_device
->rad_info
.family
== CHIP_VEGA10
||
2392 device
->physical_device
->rad_info
.chip_class
== GFX7
||
2393 device
->physical_device
->rad_info
.chip_class
== GFX6
)
2394 --max_offchip_buffers_per_se
;
2396 max_offchip_buffers
= max_offchip_buffers_per_se
*
2397 device
->physical_device
->rad_info
.max_se
;
2399 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2400 * around by setting 4K granularity.
2402 if (device
->tess_offchip_block_dw_size
== 4096) {
2403 assert(device
->physical_device
->rad_info
.family
== CHIP_HAWAII
);
2404 offchip_granularity
= V_03093C_X_4K_DWORDS
;
2406 assert(device
->tess_offchip_block_dw_size
== 8192);
2407 offchip_granularity
= V_03093C_X_8K_DWORDS
;
2410 switch (device
->physical_device
->rad_info
.chip_class
) {
2412 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
2417 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
2425 *max_offchip_buffers_p
= max_offchip_buffers
;
2426 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2427 if (device
->physical_device
->rad_info
.chip_class
>= GFX8
)
2428 --max_offchip_buffers
;
2430 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
2431 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
2434 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
2436 return hs_offchip_param
;
2440 radv_emit_gs_ring_sizes(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
2441 struct radeon_winsys_bo
*esgs_ring_bo
,
2442 uint32_t esgs_ring_size
,
2443 struct radeon_winsys_bo
*gsvs_ring_bo
,
2444 uint32_t gsvs_ring_size
)
2446 if (!esgs_ring_bo
&& !gsvs_ring_bo
)
2450 radv_cs_add_buffer(queue
->device
->ws
, cs
, esgs_ring_bo
);
2453 radv_cs_add_buffer(queue
->device
->ws
, cs
, gsvs_ring_bo
);
2455 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2456 radeon_set_uconfig_reg_seq(cs
, R_030900_VGT_ESGS_RING_SIZE
, 2);
2457 radeon_emit(cs
, esgs_ring_size
>> 8);
2458 radeon_emit(cs
, gsvs_ring_size
>> 8);
2460 radeon_set_config_reg_seq(cs
, R_0088C8_VGT_ESGS_RING_SIZE
, 2);
2461 radeon_emit(cs
, esgs_ring_size
>> 8);
2462 radeon_emit(cs
, gsvs_ring_size
>> 8);
2467 radv_emit_tess_factor_ring(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
2468 unsigned hs_offchip_param
, unsigned tf_ring_size
,
2469 struct radeon_winsys_bo
*tess_rings_bo
)
2476 tf_va
= radv_buffer_get_va(tess_rings_bo
);
2478 radv_cs_add_buffer(queue
->device
->ws
, cs
, tess_rings_bo
);
2480 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2481 radeon_set_uconfig_reg(cs
, R_030938_VGT_TF_RING_SIZE
,
2482 S_030938_SIZE(tf_ring_size
/ 4));
2483 radeon_set_uconfig_reg(cs
, R_030940_VGT_TF_MEMORY_BASE
,
2486 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2487 radeon_set_uconfig_reg(cs
, R_030984_VGT_TF_MEMORY_BASE_HI_UMD
,
2488 S_030984_BASE_HI(tf_va
>> 40));
2489 } else if (queue
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
2490 radeon_set_uconfig_reg(cs
, R_030944_VGT_TF_MEMORY_BASE_HI
,
2491 S_030944_BASE_HI(tf_va
>> 40));
2493 radeon_set_uconfig_reg(cs
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
2496 radeon_set_config_reg(cs
, R_008988_VGT_TF_RING_SIZE
,
2497 S_008988_SIZE(tf_ring_size
/ 4));
2498 radeon_set_config_reg(cs
, R_0089B8_VGT_TF_MEMORY_BASE
,
2500 radeon_set_config_reg(cs
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
2506 radv_emit_compute_scratch(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
2507 struct radeon_winsys_bo
*compute_scratch_bo
)
2509 uint64_t scratch_va
;
2511 if (!compute_scratch_bo
)
2514 scratch_va
= radv_buffer_get_va(compute_scratch_bo
);
2516 radv_cs_add_buffer(queue
->device
->ws
, cs
, compute_scratch_bo
);
2518 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, 2);
2519 radeon_emit(cs
, scratch_va
);
2520 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
2521 S_008F04_SWIZZLE_ENABLE(1));
2525 radv_emit_global_shader_pointers(struct radv_queue
*queue
,
2526 struct radeon_cmdbuf
*cs
,
2527 struct radeon_winsys_bo
*descriptor_bo
)
2534 va
= radv_buffer_get_va(descriptor_bo
);
2536 radv_cs_add_buffer(queue
->device
->ws
, cs
, descriptor_bo
);
2538 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2539 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
2540 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
2541 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
2542 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
2544 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
2545 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
2548 } else if (queue
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
2549 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
2550 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
2551 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
2552 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
2554 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
2555 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
2559 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
2560 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
2561 R_00B230_SPI_SHADER_USER_DATA_GS_0
,
2562 R_00B330_SPI_SHADER_USER_DATA_ES_0
,
2563 R_00B430_SPI_SHADER_USER_DATA_HS_0
,
2564 R_00B530_SPI_SHADER_USER_DATA_LS_0
};
2566 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
2567 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
2574 radv_init_graphics_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
2576 struct radv_device
*device
= queue
->device
;
2578 if (device
->gfx_init
) {
2579 uint64_t va
= radv_buffer_get_va(device
->gfx_init
);
2581 radeon_emit(cs
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
2582 radeon_emit(cs
, va
);
2583 radeon_emit(cs
, va
>> 32);
2584 radeon_emit(cs
, device
->gfx_init_size_dw
& 0xffff);
2586 radv_cs_add_buffer(device
->ws
, cs
, device
->gfx_init
);
2588 struct radv_physical_device
*physical_device
= device
->physical_device
;
2589 si_emit_graphics(physical_device
, cs
);
2594 radv_init_compute_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
2596 struct radv_physical_device
*physical_device
= queue
->device
->physical_device
;
2597 si_emit_compute(physical_device
, cs
);
2601 radv_get_preamble_cs(struct radv_queue
*queue
,
2602 uint32_t scratch_size
,
2603 uint32_t compute_scratch_size
,
2604 uint32_t esgs_ring_size
,
2605 uint32_t gsvs_ring_size
,
2606 bool needs_tess_rings
,
2607 bool needs_sample_positions
,
2608 struct radeon_cmdbuf
**initial_full_flush_preamble_cs
,
2609 struct radeon_cmdbuf
**initial_preamble_cs
,
2610 struct radeon_cmdbuf
**continue_preamble_cs
)
2612 struct radeon_winsys_bo
*scratch_bo
= NULL
;
2613 struct radeon_winsys_bo
*descriptor_bo
= NULL
;
2614 struct radeon_winsys_bo
*compute_scratch_bo
= NULL
;
2615 struct radeon_winsys_bo
*esgs_ring_bo
= NULL
;
2616 struct radeon_winsys_bo
*gsvs_ring_bo
= NULL
;
2617 struct radeon_winsys_bo
*tess_rings_bo
= NULL
;
2618 struct radeon_cmdbuf
*dest_cs
[3] = {0};
2619 bool add_tess_rings
= false, add_sample_positions
= false;
2620 unsigned tess_factor_ring_size
= 0, tess_offchip_ring_size
= 0;
2621 unsigned max_offchip_buffers
;
2622 unsigned hs_offchip_param
= 0;
2623 unsigned tess_offchip_ring_offset
;
2624 uint32_t ring_bo_flags
= RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
;
2625 if (!queue
->has_tess_rings
) {
2626 if (needs_tess_rings
)
2627 add_tess_rings
= true;
2629 if (!queue
->has_sample_positions
) {
2630 if (needs_sample_positions
)
2631 add_sample_positions
= true;
2633 tess_factor_ring_size
= 32768 * queue
->device
->physical_device
->rad_info
.max_se
;
2634 hs_offchip_param
= radv_get_hs_offchip_param(queue
->device
,
2635 &max_offchip_buffers
);
2636 tess_offchip_ring_offset
= align(tess_factor_ring_size
, 64 * 1024);
2637 tess_offchip_ring_size
= max_offchip_buffers
*
2638 queue
->device
->tess_offchip_block_dw_size
* 4;
2640 if (scratch_size
<= queue
->scratch_size
&&
2641 compute_scratch_size
<= queue
->compute_scratch_size
&&
2642 esgs_ring_size
<= queue
->esgs_ring_size
&&
2643 gsvs_ring_size
<= queue
->gsvs_ring_size
&&
2644 !add_tess_rings
&& !add_sample_positions
&&
2645 queue
->initial_preamble_cs
) {
2646 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
2647 *initial_preamble_cs
= queue
->initial_preamble_cs
;
2648 *continue_preamble_cs
= queue
->continue_preamble_cs
;
2649 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
2650 *continue_preamble_cs
= NULL
;
2654 if (scratch_size
> queue
->scratch_size
) {
2655 scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2660 RADV_BO_PRIORITY_SCRATCH
);
2664 scratch_bo
= queue
->scratch_bo
;
2666 if (compute_scratch_size
> queue
->compute_scratch_size
) {
2667 compute_scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2668 compute_scratch_size
,
2672 RADV_BO_PRIORITY_SCRATCH
);
2673 if (!compute_scratch_bo
)
2677 compute_scratch_bo
= queue
->compute_scratch_bo
;
2679 if (esgs_ring_size
> queue
->esgs_ring_size
) {
2680 esgs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2685 RADV_BO_PRIORITY_SCRATCH
);
2689 esgs_ring_bo
= queue
->esgs_ring_bo
;
2690 esgs_ring_size
= queue
->esgs_ring_size
;
2693 if (gsvs_ring_size
> queue
->gsvs_ring_size
) {
2694 gsvs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2699 RADV_BO_PRIORITY_SCRATCH
);
2703 gsvs_ring_bo
= queue
->gsvs_ring_bo
;
2704 gsvs_ring_size
= queue
->gsvs_ring_size
;
2707 if (add_tess_rings
) {
2708 tess_rings_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2709 tess_offchip_ring_offset
+ tess_offchip_ring_size
,
2713 RADV_BO_PRIORITY_SCRATCH
);
2717 tess_rings_bo
= queue
->tess_rings_bo
;
2720 if (scratch_bo
!= queue
->scratch_bo
||
2721 esgs_ring_bo
!= queue
->esgs_ring_bo
||
2722 gsvs_ring_bo
!= queue
->gsvs_ring_bo
||
2723 tess_rings_bo
!= queue
->tess_rings_bo
||
2724 add_sample_positions
) {
2726 if (gsvs_ring_bo
|| esgs_ring_bo
||
2727 tess_rings_bo
|| add_sample_positions
) {
2728 size
= 112; /* 2 dword + 2 padding + 4 dword * 6 */
2729 if (add_sample_positions
)
2730 size
+= 128; /* 64+32+16+8 = 120 bytes */
2732 else if (scratch_bo
)
2733 size
= 8; /* 2 dword */
2735 descriptor_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2739 RADEON_FLAG_CPU_ACCESS
|
2740 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
2741 RADEON_FLAG_READ_ONLY
,
2742 RADV_BO_PRIORITY_DESCRIPTOR
);
2746 descriptor_bo
= queue
->descriptor_bo
;
2748 if (descriptor_bo
!= queue
->descriptor_bo
) {
2749 uint32_t *map
= (uint32_t*)queue
->device
->ws
->buffer_map(descriptor_bo
);
2752 uint64_t scratch_va
= radv_buffer_get_va(scratch_bo
);
2753 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
2754 S_008F04_SWIZZLE_ENABLE(1);
2755 map
[0] = scratch_va
;
2759 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
|| add_sample_positions
)
2760 fill_geom_tess_rings(queue
, map
, add_sample_positions
,
2761 esgs_ring_size
, esgs_ring_bo
,
2762 gsvs_ring_size
, gsvs_ring_bo
,
2763 tess_factor_ring_size
,
2764 tess_offchip_ring_offset
,
2765 tess_offchip_ring_size
,
2768 queue
->device
->ws
->buffer_unmap(descriptor_bo
);
2771 for(int i
= 0; i
< 3; ++i
) {
2772 struct radeon_cmdbuf
*cs
= NULL
;
2773 cs
= queue
->device
->ws
->cs_create(queue
->device
->ws
,
2774 queue
->queue_family_index
? RING_COMPUTE
: RING_GFX
);
2781 radv_cs_add_buffer(queue
->device
->ws
, cs
, scratch_bo
);
2783 /* Emit initial configuration. */
2784 switch (queue
->queue_family_index
) {
2785 case RADV_QUEUE_GENERAL
:
2786 radv_init_graphics_state(cs
, queue
);
2788 case RADV_QUEUE_COMPUTE
:
2789 radv_init_compute_state(cs
, queue
);
2791 case RADV_QUEUE_TRANSFER
:
2795 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
) {
2796 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2797 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2799 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2800 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
2803 radv_emit_gs_ring_sizes(queue
, cs
, esgs_ring_bo
, esgs_ring_size
,
2804 gsvs_ring_bo
, gsvs_ring_size
);
2805 radv_emit_tess_factor_ring(queue
, cs
, hs_offchip_param
,
2806 tess_factor_ring_size
, tess_rings_bo
);
2807 radv_emit_global_shader_pointers(queue
, cs
, descriptor_bo
);
2808 radv_emit_compute_scratch(queue
, cs
, compute_scratch_bo
);
2811 si_cs_emit_cache_flush(cs
,
2812 queue
->device
->physical_device
->rad_info
.chip_class
,
2814 queue
->queue_family_index
== RING_COMPUTE
&&
2815 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
2816 (queue
->queue_family_index
== RADV_QUEUE_COMPUTE
? RADV_CMD_FLAG_CS_PARTIAL_FLUSH
: (RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
)) |
2817 RADV_CMD_FLAG_INV_ICACHE
|
2818 RADV_CMD_FLAG_INV_SCACHE
|
2819 RADV_CMD_FLAG_INV_VCACHE
|
2820 RADV_CMD_FLAG_INV_L2
|
2821 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
2822 } else if (i
== 1) {
2823 si_cs_emit_cache_flush(cs
,
2824 queue
->device
->physical_device
->rad_info
.chip_class
,
2826 queue
->queue_family_index
== RING_COMPUTE
&&
2827 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
2828 RADV_CMD_FLAG_INV_ICACHE
|
2829 RADV_CMD_FLAG_INV_SCACHE
|
2830 RADV_CMD_FLAG_INV_VCACHE
|
2831 RADV_CMD_FLAG_INV_L2
|
2832 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
2835 if (!queue
->device
->ws
->cs_finalize(cs
))
2839 if (queue
->initial_full_flush_preamble_cs
)
2840 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
2842 if (queue
->initial_preamble_cs
)
2843 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
2845 if (queue
->continue_preamble_cs
)
2846 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
2848 queue
->initial_full_flush_preamble_cs
= dest_cs
[0];
2849 queue
->initial_preamble_cs
= dest_cs
[1];
2850 queue
->continue_preamble_cs
= dest_cs
[2];
2852 if (scratch_bo
!= queue
->scratch_bo
) {
2853 if (queue
->scratch_bo
)
2854 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
2855 queue
->scratch_bo
= scratch_bo
;
2856 queue
->scratch_size
= scratch_size
;
2859 if (compute_scratch_bo
!= queue
->compute_scratch_bo
) {
2860 if (queue
->compute_scratch_bo
)
2861 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
2862 queue
->compute_scratch_bo
= compute_scratch_bo
;
2863 queue
->compute_scratch_size
= compute_scratch_size
;
2866 if (esgs_ring_bo
!= queue
->esgs_ring_bo
) {
2867 if (queue
->esgs_ring_bo
)
2868 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
2869 queue
->esgs_ring_bo
= esgs_ring_bo
;
2870 queue
->esgs_ring_size
= esgs_ring_size
;
2873 if (gsvs_ring_bo
!= queue
->gsvs_ring_bo
) {
2874 if (queue
->gsvs_ring_bo
)
2875 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
2876 queue
->gsvs_ring_bo
= gsvs_ring_bo
;
2877 queue
->gsvs_ring_size
= gsvs_ring_size
;
2880 if (tess_rings_bo
!= queue
->tess_rings_bo
) {
2881 queue
->tess_rings_bo
= tess_rings_bo
;
2882 queue
->has_tess_rings
= true;
2885 if (descriptor_bo
!= queue
->descriptor_bo
) {
2886 if (queue
->descriptor_bo
)
2887 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
2889 queue
->descriptor_bo
= descriptor_bo
;
2892 if (add_sample_positions
)
2893 queue
->has_sample_positions
= true;
2895 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
2896 *initial_preamble_cs
= queue
->initial_preamble_cs
;
2897 *continue_preamble_cs
= queue
->continue_preamble_cs
;
2898 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
2899 *continue_preamble_cs
= NULL
;
2902 for (int i
= 0; i
< ARRAY_SIZE(dest_cs
); ++i
)
2904 queue
->device
->ws
->cs_destroy(dest_cs
[i
]);
2905 if (descriptor_bo
&& descriptor_bo
!= queue
->descriptor_bo
)
2906 queue
->device
->ws
->buffer_destroy(descriptor_bo
);
2907 if (scratch_bo
&& scratch_bo
!= queue
->scratch_bo
)
2908 queue
->device
->ws
->buffer_destroy(scratch_bo
);
2909 if (compute_scratch_bo
&& compute_scratch_bo
!= queue
->compute_scratch_bo
)
2910 queue
->device
->ws
->buffer_destroy(compute_scratch_bo
);
2911 if (esgs_ring_bo
&& esgs_ring_bo
!= queue
->esgs_ring_bo
)
2912 queue
->device
->ws
->buffer_destroy(esgs_ring_bo
);
2913 if (gsvs_ring_bo
&& gsvs_ring_bo
!= queue
->gsvs_ring_bo
)
2914 queue
->device
->ws
->buffer_destroy(gsvs_ring_bo
);
2915 if (tess_rings_bo
&& tess_rings_bo
!= queue
->tess_rings_bo
)
2916 queue
->device
->ws
->buffer_destroy(tess_rings_bo
);
2917 return vk_error(queue
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2920 static VkResult
radv_alloc_sem_counts(struct radv_instance
*instance
,
2921 struct radv_winsys_sem_counts
*counts
,
2923 const VkSemaphore
*sems
,
2927 int syncobj_idx
= 0, sem_idx
= 0;
2929 if (num_sems
== 0 && _fence
== VK_NULL_HANDLE
)
2932 for (uint32_t i
= 0; i
< num_sems
; i
++) {
2933 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
2935 if (sem
->temp_syncobj
|| sem
->syncobj
)
2936 counts
->syncobj_count
++;
2938 counts
->sem_count
++;
2941 if (_fence
!= VK_NULL_HANDLE
) {
2942 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2943 if (fence
->temp_syncobj
|| fence
->syncobj
)
2944 counts
->syncobj_count
++;
2947 if (counts
->syncobj_count
) {
2948 counts
->syncobj
= (uint32_t *)malloc(sizeof(uint32_t) * counts
->syncobj_count
);
2949 if (!counts
->syncobj
)
2950 return vk_error(instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2953 if (counts
->sem_count
) {
2954 counts
->sem
= (struct radeon_winsys_sem
**)malloc(sizeof(struct radeon_winsys_sem
*) * counts
->sem_count
);
2956 free(counts
->syncobj
);
2957 return vk_error(instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2961 for (uint32_t i
= 0; i
< num_sems
; i
++) {
2962 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
2964 if (sem
->temp_syncobj
) {
2965 counts
->syncobj
[syncobj_idx
++] = sem
->temp_syncobj
;
2967 else if (sem
->syncobj
)
2968 counts
->syncobj
[syncobj_idx
++] = sem
->syncobj
;
2971 counts
->sem
[sem_idx
++] = sem
->sem
;
2975 if (_fence
!= VK_NULL_HANDLE
) {
2976 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2977 if (fence
->temp_syncobj
)
2978 counts
->syncobj
[syncobj_idx
++] = fence
->temp_syncobj
;
2979 else if (fence
->syncobj
)
2980 counts
->syncobj
[syncobj_idx
++] = fence
->syncobj
;
2987 radv_free_sem_info(struct radv_winsys_sem_info
*sem_info
)
2989 free(sem_info
->wait
.syncobj
);
2990 free(sem_info
->wait
.sem
);
2991 free(sem_info
->signal
.syncobj
);
2992 free(sem_info
->signal
.sem
);
2996 static void radv_free_temp_syncobjs(struct radv_device
*device
,
2998 const VkSemaphore
*sems
)
3000 for (uint32_t i
= 0; i
< num_sems
; i
++) {
3001 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
3003 if (sem
->temp_syncobj
) {
3004 device
->ws
->destroy_syncobj(device
->ws
, sem
->temp_syncobj
);
3005 sem
->temp_syncobj
= 0;
3011 radv_alloc_sem_info(struct radv_instance
*instance
,
3012 struct radv_winsys_sem_info
*sem_info
,
3014 const VkSemaphore
*wait_sems
,
3015 int num_signal_sems
,
3016 const VkSemaphore
*signal_sems
,
3020 memset(sem_info
, 0, sizeof(*sem_info
));
3022 ret
= radv_alloc_sem_counts(instance
, &sem_info
->wait
, num_wait_sems
, wait_sems
, VK_NULL_HANDLE
, true);
3025 ret
= radv_alloc_sem_counts(instance
, &sem_info
->signal
, num_signal_sems
, signal_sems
, fence
, false);
3027 radv_free_sem_info(sem_info
);
3029 /* caller can override these */
3030 sem_info
->cs_emit_wait
= true;
3031 sem_info
->cs_emit_signal
= true;
3035 /* Signals fence as soon as all the work currently put on queue is done. */
3036 static VkResult
radv_signal_fence(struct radv_queue
*queue
,
3037 struct radv_fence
*fence
)
3041 struct radv_winsys_sem_info sem_info
;
3043 result
= radv_alloc_sem_info(queue
->device
->instance
, &sem_info
, 0, NULL
, 0, NULL
,
3044 radv_fence_to_handle(fence
));
3045 if (result
!= VK_SUCCESS
)
3048 ret
= queue
->device
->ws
->cs_submit(queue
->hw_ctx
, queue
->queue_idx
,
3049 &queue
->device
->empty_cs
[queue
->queue_family_index
],
3050 1, NULL
, NULL
, &sem_info
, NULL
,
3051 false, fence
->fence
);
3052 radv_free_sem_info(&sem_info
);
3055 return vk_error(queue
->device
->instance
, VK_ERROR_DEVICE_LOST
);
3060 VkResult
radv_QueueSubmit(
3062 uint32_t submitCount
,
3063 const VkSubmitInfo
* pSubmits
,
3066 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
3067 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3068 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
3069 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
3071 uint32_t max_cs_submission
= queue
->device
->trace_bo
? 1 : RADV_MAX_IBS_PER_SUBMIT
;
3072 uint32_t scratch_size
= 0;
3073 uint32_t compute_scratch_size
= 0;
3074 uint32_t esgs_ring_size
= 0, gsvs_ring_size
= 0;
3075 struct radeon_cmdbuf
*initial_preamble_cs
= NULL
, *initial_flush_preamble_cs
= NULL
, *continue_preamble_cs
= NULL
;
3077 bool fence_emitted
= false;
3078 bool tess_rings_needed
= false;
3079 bool sample_positions_needed
= false;
3081 /* Do this first so failing to allocate scratch buffers can't result in
3082 * partially executed submissions. */
3083 for (uint32_t i
= 0; i
< submitCount
; i
++) {
3084 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
3085 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
3086 pSubmits
[i
].pCommandBuffers
[j
]);
3088 scratch_size
= MAX2(scratch_size
, cmd_buffer
->scratch_size_needed
);
3089 compute_scratch_size
= MAX2(compute_scratch_size
,
3090 cmd_buffer
->compute_scratch_size_needed
);
3091 esgs_ring_size
= MAX2(esgs_ring_size
, cmd_buffer
->esgs_ring_size_needed
);
3092 gsvs_ring_size
= MAX2(gsvs_ring_size
, cmd_buffer
->gsvs_ring_size_needed
);
3093 tess_rings_needed
|= cmd_buffer
->tess_rings_needed
;
3094 sample_positions_needed
|= cmd_buffer
->sample_positions_needed
;
3098 result
= radv_get_preamble_cs(queue
, scratch_size
, compute_scratch_size
,
3099 esgs_ring_size
, gsvs_ring_size
, tess_rings_needed
,
3100 sample_positions_needed
, &initial_flush_preamble_cs
,
3101 &initial_preamble_cs
, &continue_preamble_cs
);
3102 if (result
!= VK_SUCCESS
)
3105 for (uint32_t i
= 0; i
< submitCount
; i
++) {
3106 struct radeon_cmdbuf
**cs_array
;
3107 bool do_flush
= !i
|| pSubmits
[i
].pWaitDstStageMask
;
3108 bool can_patch
= true;
3110 struct radv_winsys_sem_info sem_info
;
3112 result
= radv_alloc_sem_info(queue
->device
->instance
,
3114 pSubmits
[i
].waitSemaphoreCount
,
3115 pSubmits
[i
].pWaitSemaphores
,
3116 pSubmits
[i
].signalSemaphoreCount
,
3117 pSubmits
[i
].pSignalSemaphores
,
3119 if (result
!= VK_SUCCESS
)
3122 if (!pSubmits
[i
].commandBufferCount
) {
3123 if (pSubmits
[i
].waitSemaphoreCount
|| pSubmits
[i
].signalSemaphoreCount
) {
3124 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
3125 &queue
->device
->empty_cs
[queue
->queue_family_index
],
3130 radv_loge("failed to submit CS %d\n", i
);
3133 fence_emitted
= true;
3135 radv_free_sem_info(&sem_info
);
3139 cs_array
= malloc(sizeof(struct radeon_cmdbuf
*) *
3140 (pSubmits
[i
].commandBufferCount
));
3142 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
3143 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
3144 pSubmits
[i
].pCommandBuffers
[j
]);
3145 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
3147 cs_array
[j
] = cmd_buffer
->cs
;
3148 if ((cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT
))
3151 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_PENDING
;
3154 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
+= advance
) {
3155 struct radeon_cmdbuf
*initial_preamble
= (do_flush
&& !j
) ? initial_flush_preamble_cs
: initial_preamble_cs
;
3156 const struct radv_winsys_bo_list
*bo_list
= NULL
;
3158 advance
= MIN2(max_cs_submission
,
3159 pSubmits
[i
].commandBufferCount
- j
);
3161 if (queue
->device
->trace_bo
)
3162 *queue
->device
->trace_id_ptr
= 0;
3164 sem_info
.cs_emit_wait
= j
== 0;
3165 sem_info
.cs_emit_signal
= j
+ advance
== pSubmits
[i
].commandBufferCount
;
3167 if (unlikely(queue
->device
->use_global_bo_list
)) {
3168 pthread_mutex_lock(&queue
->device
->bo_list
.mutex
);
3169 bo_list
= &queue
->device
->bo_list
.list
;
3172 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, cs_array
+ j
,
3173 advance
, initial_preamble
, continue_preamble_cs
,
3175 can_patch
, base_fence
);
3177 if (unlikely(queue
->device
->use_global_bo_list
))
3178 pthread_mutex_unlock(&queue
->device
->bo_list
.mutex
);
3181 radv_loge("failed to submit CS %d\n", i
);
3184 fence_emitted
= true;
3185 if (queue
->device
->trace_bo
) {
3186 radv_check_gpu_hangs(queue
, cs_array
[j
]);
3190 radv_free_temp_syncobjs(queue
->device
,
3191 pSubmits
[i
].waitSemaphoreCount
,
3192 pSubmits
[i
].pWaitSemaphores
);
3193 radv_free_sem_info(&sem_info
);
3198 if (!fence_emitted
) {
3199 result
= radv_signal_fence(queue
, fence
);
3200 if (result
!= VK_SUCCESS
)
3208 VkResult
radv_QueueWaitIdle(
3211 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
3213 queue
->device
->ws
->ctx_wait_idle(queue
->hw_ctx
,
3214 radv_queue_family_to_ring(queue
->queue_family_index
),
3219 VkResult
radv_DeviceWaitIdle(
3222 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3224 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
3225 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++) {
3226 radv_QueueWaitIdle(radv_queue_to_handle(&device
->queues
[i
][q
]));
3232 VkResult
radv_EnumerateInstanceExtensionProperties(
3233 const char* pLayerName
,
3234 uint32_t* pPropertyCount
,
3235 VkExtensionProperties
* pProperties
)
3237 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
3239 for (int i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; i
++) {
3240 if (radv_supported_instance_extensions
.extensions
[i
]) {
3241 vk_outarray_append(&out
, prop
) {
3242 *prop
= radv_instance_extensions
[i
];
3247 return vk_outarray_status(&out
);
3250 VkResult
radv_EnumerateDeviceExtensionProperties(
3251 VkPhysicalDevice physicalDevice
,
3252 const char* pLayerName
,
3253 uint32_t* pPropertyCount
,
3254 VkExtensionProperties
* pProperties
)
3256 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
3257 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
3259 for (int i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; i
++) {
3260 if (device
->supported_extensions
.extensions
[i
]) {
3261 vk_outarray_append(&out
, prop
) {
3262 *prop
= radv_device_extensions
[i
];
3267 return vk_outarray_status(&out
);
3270 PFN_vkVoidFunction
radv_GetInstanceProcAddr(
3271 VkInstance _instance
,
3274 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
3275 bool unchecked
= instance
? instance
->debug_flags
& RADV_DEBUG_ALL_ENTRYPOINTS
: false;
3278 return radv_lookup_entrypoint_unchecked(pName
);
3280 return radv_lookup_entrypoint_checked(pName
,
3281 instance
? instance
->apiVersion
: 0,
3282 instance
? &instance
->enabled_extensions
: NULL
,
3287 /* The loader wants us to expose a second GetInstanceProcAddr function
3288 * to work around certain LD_PRELOAD issues seen in apps.
3291 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
3292 VkInstance instance
,
3296 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
3297 VkInstance instance
,
3300 return radv_GetInstanceProcAddr(instance
, pName
);
3304 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
3305 VkInstance _instance
,
3309 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
3310 VkInstance _instance
,
3313 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
3315 return radv_lookup_physical_device_entrypoint_checked(pName
,
3316 instance
? instance
->apiVersion
: 0,
3317 instance
? &instance
->enabled_extensions
: NULL
);
3320 PFN_vkVoidFunction
radv_GetDeviceProcAddr(
3324 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3325 bool unchecked
= device
? device
->instance
->debug_flags
& RADV_DEBUG_ALL_ENTRYPOINTS
: false;
3328 return radv_lookup_entrypoint_unchecked(pName
);
3330 return radv_lookup_entrypoint_checked(pName
,
3331 device
->instance
->apiVersion
,
3332 &device
->instance
->enabled_extensions
,
3333 &device
->enabled_extensions
);
3337 bool radv_get_memory_fd(struct radv_device
*device
,
3338 struct radv_device_memory
*memory
,
3341 struct radeon_bo_metadata metadata
;
3343 if (memory
->image
) {
3344 radv_init_metadata(device
, memory
->image
, &metadata
);
3345 device
->ws
->buffer_set_metadata(memory
->bo
, &metadata
);
3348 return device
->ws
->buffer_get_fd(device
->ws
, memory
->bo
,
3352 static VkResult
radv_alloc_memory(struct radv_device
*device
,
3353 const VkMemoryAllocateInfo
* pAllocateInfo
,
3354 const VkAllocationCallbacks
* pAllocator
,
3355 VkDeviceMemory
* pMem
)
3357 struct radv_device_memory
*mem
;
3359 enum radeon_bo_domain domain
;
3361 enum radv_mem_type mem_type_index
= device
->physical_device
->mem_type_indices
[pAllocateInfo
->memoryTypeIndex
];
3363 assert(pAllocateInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO
);
3365 if (pAllocateInfo
->allocationSize
== 0) {
3366 /* Apparently, this is allowed */
3367 *pMem
= VK_NULL_HANDLE
;
3371 const VkImportMemoryFdInfoKHR
*import_info
=
3372 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_FD_INFO_KHR
);
3373 const VkMemoryDedicatedAllocateInfo
*dedicate_info
=
3374 vk_find_struct_const(pAllocateInfo
->pNext
, MEMORY_DEDICATED_ALLOCATE_INFO
);
3375 const VkExportMemoryAllocateInfo
*export_info
=
3376 vk_find_struct_const(pAllocateInfo
->pNext
, EXPORT_MEMORY_ALLOCATE_INFO
);
3377 const VkImportMemoryHostPointerInfoEXT
*host_ptr_info
=
3378 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_HOST_POINTER_INFO_EXT
);
3380 const struct wsi_memory_allocate_info
*wsi_info
=
3381 vk_find_struct_const(pAllocateInfo
->pNext
, WSI_MEMORY_ALLOCATE_INFO_MESA
);
3383 mem
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*mem
), 8,
3384 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3386 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3388 if (wsi_info
&& wsi_info
->implicit_sync
)
3389 flags
|= RADEON_FLAG_IMPLICIT_SYNC
;
3391 if (dedicate_info
) {
3392 mem
->image
= radv_image_from_handle(dedicate_info
->image
);
3393 mem
->buffer
= radv_buffer_from_handle(dedicate_info
->buffer
);
3399 float priority_float
= 0.5;
3400 const struct VkMemoryPriorityAllocateInfoEXT
*priority_ext
=
3401 vk_find_struct_const(pAllocateInfo
->pNext
,
3402 MEMORY_PRIORITY_ALLOCATE_INFO_EXT
);
3404 priority_float
= priority_ext
->priority
;
3406 unsigned priority
= MIN2(RADV_BO_PRIORITY_APPLICATION_MAX
- 1,
3407 (int)(priority_float
* RADV_BO_PRIORITY_APPLICATION_MAX
));
3409 mem
->user_ptr
= NULL
;
3412 assert(import_info
->handleType
==
3413 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
3414 import_info
->handleType
==
3415 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
3416 mem
->bo
= device
->ws
->buffer_from_fd(device
->ws
, import_info
->fd
,
3417 priority
, NULL
, NULL
);
3419 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
3422 close(import_info
->fd
);
3424 } else if (host_ptr_info
) {
3425 assert(host_ptr_info
->handleType
== VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
);
3426 assert(mem_type_index
== RADV_MEM_TYPE_GTT_CACHED
);
3427 mem
->bo
= device
->ws
->buffer_from_ptr(device
->ws
, host_ptr_info
->pHostPointer
,
3428 pAllocateInfo
->allocationSize
,
3431 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
3434 mem
->user_ptr
= host_ptr_info
->pHostPointer
;
3437 uint64_t alloc_size
= align_u64(pAllocateInfo
->allocationSize
, 4096);
3438 if (mem_type_index
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
||
3439 mem_type_index
== RADV_MEM_TYPE_GTT_CACHED
)
3440 domain
= RADEON_DOMAIN_GTT
;
3442 domain
= RADEON_DOMAIN_VRAM
;
3444 if (mem_type_index
== RADV_MEM_TYPE_VRAM
)
3445 flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
3447 flags
|= RADEON_FLAG_CPU_ACCESS
;
3449 if (mem_type_index
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
)
3450 flags
|= RADEON_FLAG_GTT_WC
;
3452 if (!dedicate_info
&& !import_info
&& (!export_info
|| !export_info
->handleTypes
)) {
3453 flags
|= RADEON_FLAG_NO_INTERPROCESS_SHARING
;
3454 if (device
->use_global_bo_list
) {
3455 flags
|= RADEON_FLAG_PREFER_LOCAL_BO
;
3459 mem
->bo
= device
->ws
->buffer_create(device
->ws
, alloc_size
, device
->physical_device
->rad_info
.max_alignment
,
3460 domain
, flags
, priority
);
3463 result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
3466 mem
->type_index
= mem_type_index
;
3469 result
= radv_bo_list_add(device
, mem
->bo
);
3470 if (result
!= VK_SUCCESS
)
3473 *pMem
= radv_device_memory_to_handle(mem
);
3478 device
->ws
->buffer_destroy(mem
->bo
);
3480 vk_free2(&device
->alloc
, pAllocator
, mem
);
3485 VkResult
radv_AllocateMemory(
3487 const VkMemoryAllocateInfo
* pAllocateInfo
,
3488 const VkAllocationCallbacks
* pAllocator
,
3489 VkDeviceMemory
* pMem
)
3491 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3492 return radv_alloc_memory(device
, pAllocateInfo
, pAllocator
, pMem
);
3495 void radv_FreeMemory(
3497 VkDeviceMemory _mem
,
3498 const VkAllocationCallbacks
* pAllocator
)
3500 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3501 RADV_FROM_HANDLE(radv_device_memory
, mem
, _mem
);
3506 radv_bo_list_remove(device
, mem
->bo
);
3507 device
->ws
->buffer_destroy(mem
->bo
);
3510 vk_free2(&device
->alloc
, pAllocator
, mem
);
3513 VkResult
radv_MapMemory(
3515 VkDeviceMemory _memory
,
3516 VkDeviceSize offset
,
3518 VkMemoryMapFlags flags
,
3521 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3522 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
3530 *ppData
= mem
->user_ptr
;
3532 *ppData
= device
->ws
->buffer_map(mem
->bo
);
3539 return vk_error(device
->instance
, VK_ERROR_MEMORY_MAP_FAILED
);
3542 void radv_UnmapMemory(
3544 VkDeviceMemory _memory
)
3546 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3547 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
3552 if (mem
->user_ptr
== NULL
)
3553 device
->ws
->buffer_unmap(mem
->bo
);
3556 VkResult
radv_FlushMappedMemoryRanges(
3558 uint32_t memoryRangeCount
,
3559 const VkMappedMemoryRange
* pMemoryRanges
)
3564 VkResult
radv_InvalidateMappedMemoryRanges(
3566 uint32_t memoryRangeCount
,
3567 const VkMappedMemoryRange
* pMemoryRanges
)
3572 void radv_GetBufferMemoryRequirements(
3575 VkMemoryRequirements
* pMemoryRequirements
)
3577 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3578 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3580 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
3582 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
3583 pMemoryRequirements
->alignment
= 4096;
3585 pMemoryRequirements
->alignment
= 16;
3587 pMemoryRequirements
->size
= align64(buffer
->size
, pMemoryRequirements
->alignment
);
3590 void radv_GetBufferMemoryRequirements2(
3592 const VkBufferMemoryRequirementsInfo2
*pInfo
,
3593 VkMemoryRequirements2
*pMemoryRequirements
)
3595 radv_GetBufferMemoryRequirements(device
, pInfo
->buffer
,
3596 &pMemoryRequirements
->memoryRequirements
);
3597 RADV_FROM_HANDLE(radv_buffer
, buffer
, pInfo
->buffer
);
3598 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
3599 switch (ext
->sType
) {
3600 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
3601 VkMemoryDedicatedRequirements
*req
=
3602 (VkMemoryDedicatedRequirements
*) ext
;
3603 req
->requiresDedicatedAllocation
= buffer
->shareable
;
3604 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
3613 void radv_GetImageMemoryRequirements(
3616 VkMemoryRequirements
* pMemoryRequirements
)
3618 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3619 RADV_FROM_HANDLE(radv_image
, image
, _image
);
3621 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
3623 pMemoryRequirements
->size
= image
->size
;
3624 pMemoryRequirements
->alignment
= image
->alignment
;
3627 void radv_GetImageMemoryRequirements2(
3629 const VkImageMemoryRequirementsInfo2
*pInfo
,
3630 VkMemoryRequirements2
*pMemoryRequirements
)
3632 radv_GetImageMemoryRequirements(device
, pInfo
->image
,
3633 &pMemoryRequirements
->memoryRequirements
);
3635 RADV_FROM_HANDLE(radv_image
, image
, pInfo
->image
);
3637 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
3638 switch (ext
->sType
) {
3639 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
3640 VkMemoryDedicatedRequirements
*req
=
3641 (VkMemoryDedicatedRequirements
*) ext
;
3642 req
->requiresDedicatedAllocation
= image
->shareable
;
3643 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
3652 void radv_GetImageSparseMemoryRequirements(
3655 uint32_t* pSparseMemoryRequirementCount
,
3656 VkSparseImageMemoryRequirements
* pSparseMemoryRequirements
)
3661 void radv_GetImageSparseMemoryRequirements2(
3663 const VkImageSparseMemoryRequirementsInfo2
*pInfo
,
3664 uint32_t* pSparseMemoryRequirementCount
,
3665 VkSparseImageMemoryRequirements2
*pSparseMemoryRequirements
)
3670 void radv_GetDeviceMemoryCommitment(
3672 VkDeviceMemory memory
,
3673 VkDeviceSize
* pCommittedMemoryInBytes
)
3675 *pCommittedMemoryInBytes
= 0;
3678 VkResult
radv_BindBufferMemory2(VkDevice device
,
3679 uint32_t bindInfoCount
,
3680 const VkBindBufferMemoryInfo
*pBindInfos
)
3682 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
3683 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
3684 RADV_FROM_HANDLE(radv_buffer
, buffer
, pBindInfos
[i
].buffer
);
3687 buffer
->bo
= mem
->bo
;
3688 buffer
->offset
= pBindInfos
[i
].memoryOffset
;
3696 VkResult
radv_BindBufferMemory(
3699 VkDeviceMemory memory
,
3700 VkDeviceSize memoryOffset
)
3702 const VkBindBufferMemoryInfo info
= {
3703 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
3706 .memoryOffset
= memoryOffset
3709 return radv_BindBufferMemory2(device
, 1, &info
);
3712 VkResult
radv_BindImageMemory2(VkDevice device
,
3713 uint32_t bindInfoCount
,
3714 const VkBindImageMemoryInfo
*pBindInfos
)
3716 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
3717 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
3718 RADV_FROM_HANDLE(radv_image
, image
, pBindInfos
[i
].image
);
3721 image
->bo
= mem
->bo
;
3722 image
->offset
= pBindInfos
[i
].memoryOffset
;
3732 VkResult
radv_BindImageMemory(
3735 VkDeviceMemory memory
,
3736 VkDeviceSize memoryOffset
)
3738 const VkBindImageMemoryInfo info
= {
3739 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
3742 .memoryOffset
= memoryOffset
3745 return radv_BindImageMemory2(device
, 1, &info
);
3750 radv_sparse_buffer_bind_memory(struct radv_device
*device
,
3751 const VkSparseBufferMemoryBindInfo
*bind
)
3753 RADV_FROM_HANDLE(radv_buffer
, buffer
, bind
->buffer
);
3755 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
3756 struct radv_device_memory
*mem
= NULL
;
3758 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
3759 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
3761 device
->ws
->buffer_virtual_bind(buffer
->bo
,
3762 bind
->pBinds
[i
].resourceOffset
,
3763 bind
->pBinds
[i
].size
,
3764 mem
? mem
->bo
: NULL
,
3765 bind
->pBinds
[i
].memoryOffset
);
3770 radv_sparse_image_opaque_bind_memory(struct radv_device
*device
,
3771 const VkSparseImageOpaqueMemoryBindInfo
*bind
)
3773 RADV_FROM_HANDLE(radv_image
, image
, bind
->image
);
3775 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
3776 struct radv_device_memory
*mem
= NULL
;
3778 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
3779 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
3781 device
->ws
->buffer_virtual_bind(image
->bo
,
3782 bind
->pBinds
[i
].resourceOffset
,
3783 bind
->pBinds
[i
].size
,
3784 mem
? mem
->bo
: NULL
,
3785 bind
->pBinds
[i
].memoryOffset
);
3789 VkResult
radv_QueueBindSparse(
3791 uint32_t bindInfoCount
,
3792 const VkBindSparseInfo
* pBindInfo
,
3795 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3796 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
3797 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
3798 bool fence_emitted
= false;
3802 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
3803 struct radv_winsys_sem_info sem_info
;
3804 for (uint32_t j
= 0; j
< pBindInfo
[i
].bufferBindCount
; ++j
) {
3805 radv_sparse_buffer_bind_memory(queue
->device
,
3806 pBindInfo
[i
].pBufferBinds
+ j
);
3809 for (uint32_t j
= 0; j
< pBindInfo
[i
].imageOpaqueBindCount
; ++j
) {
3810 radv_sparse_image_opaque_bind_memory(queue
->device
,
3811 pBindInfo
[i
].pImageOpaqueBinds
+ j
);
3815 result
= radv_alloc_sem_info(queue
->device
->instance
,
3817 pBindInfo
[i
].waitSemaphoreCount
,
3818 pBindInfo
[i
].pWaitSemaphores
,
3819 pBindInfo
[i
].signalSemaphoreCount
,
3820 pBindInfo
[i
].pSignalSemaphores
,
3822 if (result
!= VK_SUCCESS
)
3825 if (pBindInfo
[i
].waitSemaphoreCount
|| pBindInfo
[i
].signalSemaphoreCount
) {
3826 ret
= queue
->device
->ws
->cs_submit(queue
->hw_ctx
, queue
->queue_idx
,
3827 &queue
->device
->empty_cs
[queue
->queue_family_index
],
3832 radv_loge("failed to submit CS %d\n", i
);
3836 fence_emitted
= true;
3839 radv_free_sem_info(&sem_info
);
3844 if (!fence_emitted
) {
3845 result
= radv_signal_fence(queue
, fence
);
3846 if (result
!= VK_SUCCESS
)
3854 VkResult
radv_CreateFence(
3856 const VkFenceCreateInfo
* pCreateInfo
,
3857 const VkAllocationCallbacks
* pAllocator
,
3860 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3861 const VkExportFenceCreateInfo
*export
=
3862 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_FENCE_CREATE_INFO
);
3863 VkExternalFenceHandleTypeFlags handleTypes
=
3864 export
? export
->handleTypes
: 0;
3866 struct radv_fence
*fence
= vk_alloc2(&device
->alloc
, pAllocator
,
3868 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3871 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3873 fence
->fence_wsi
= NULL
;
3874 fence
->temp_syncobj
= 0;
3875 if (device
->always_use_syncobj
|| handleTypes
) {
3876 int ret
= device
->ws
->create_syncobj(device
->ws
, &fence
->syncobj
);
3878 vk_free2(&device
->alloc
, pAllocator
, fence
);
3879 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3881 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
) {
3882 device
->ws
->signal_syncobj(device
->ws
, fence
->syncobj
);
3884 fence
->fence
= NULL
;
3886 fence
->fence
= device
->ws
->create_fence();
3887 if (!fence
->fence
) {
3888 vk_free2(&device
->alloc
, pAllocator
, fence
);
3889 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3892 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
)
3893 device
->ws
->signal_fence(fence
->fence
);
3896 *pFence
= radv_fence_to_handle(fence
);
3901 void radv_DestroyFence(
3904 const VkAllocationCallbacks
* pAllocator
)
3906 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3907 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3912 if (fence
->temp_syncobj
)
3913 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
3915 device
->ws
->destroy_syncobj(device
->ws
, fence
->syncobj
);
3917 device
->ws
->destroy_fence(fence
->fence
);
3918 if (fence
->fence_wsi
)
3919 fence
->fence_wsi
->destroy(fence
->fence_wsi
);
3920 vk_free2(&device
->alloc
, pAllocator
, fence
);
3924 uint64_t radv_get_current_time(void)
3927 clock_gettime(CLOCK_MONOTONIC
, &tv
);
3928 return tv
.tv_nsec
+ tv
.tv_sec
*1000000000ull;
3931 static uint64_t radv_get_absolute_timeout(uint64_t timeout
)
3933 uint64_t current_time
= radv_get_current_time();
3935 timeout
= MIN2(UINT64_MAX
- current_time
, timeout
);
3937 return current_time
+ timeout
;
3941 static bool radv_all_fences_plain_and_submitted(struct radv_device
*device
,
3942 uint32_t fenceCount
, const VkFence
*pFences
)
3944 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3945 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3946 if (fence
->fence
== NULL
|| fence
->syncobj
||
3947 fence
->temp_syncobj
|| fence
->fence_wsi
||
3948 (!device
->ws
->is_fence_waitable(fence
->fence
)))
3954 static bool radv_all_fences_syncobj(uint32_t fenceCount
, const VkFence
*pFences
)
3956 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3957 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3958 if (fence
->syncobj
== 0 && fence
->temp_syncobj
== 0)
3964 VkResult
radv_WaitForFences(
3966 uint32_t fenceCount
,
3967 const VkFence
* pFences
,
3971 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3972 timeout
= radv_get_absolute_timeout(timeout
);
3974 if (device
->always_use_syncobj
&&
3975 radv_all_fences_syncobj(fenceCount
, pFences
))
3977 uint32_t *handles
= malloc(sizeof(uint32_t) * fenceCount
);
3979 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3981 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3982 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3983 handles
[i
] = fence
->temp_syncobj
? fence
->temp_syncobj
: fence
->syncobj
;
3986 bool success
= device
->ws
->wait_syncobj(device
->ws
, handles
, fenceCount
, waitAll
, timeout
);
3989 return success
? VK_SUCCESS
: VK_TIMEOUT
;
3992 if (!waitAll
&& fenceCount
> 1) {
3993 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3994 if (device
->physical_device
->rad_info
.drm_minor
>= 10 && radv_all_fences_plain_and_submitted(device
, fenceCount
, pFences
)) {
3995 uint32_t wait_count
= 0;
3996 struct radeon_winsys_fence
**fences
= malloc(sizeof(struct radeon_winsys_fence
*) * fenceCount
);
3998 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4000 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
4001 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
4003 if (device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0)) {
4008 fences
[wait_count
++] = fence
->fence
;
4011 bool success
= device
->ws
->fences_wait(device
->ws
, fences
, wait_count
,
4012 waitAll
, timeout
- radv_get_current_time());
4015 return success
? VK_SUCCESS
: VK_TIMEOUT
;
4018 while(radv_get_current_time() <= timeout
) {
4019 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
4020 if (radv_GetFenceStatus(_device
, pFences
[i
]) == VK_SUCCESS
)
4027 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
4028 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
4029 bool expired
= false;
4031 if (fence
->temp_syncobj
) {
4032 if (!device
->ws
->wait_syncobj(device
->ws
, &fence
->temp_syncobj
, 1, true, timeout
))
4037 if (fence
->syncobj
) {
4038 if (!device
->ws
->wait_syncobj(device
->ws
, &fence
->syncobj
, 1, true, timeout
))
4044 if (!device
->ws
->is_fence_waitable(fence
->fence
)) {
4045 while(!device
->ws
->is_fence_waitable(fence
->fence
) &&
4046 radv_get_current_time() <= timeout
)
4050 expired
= device
->ws
->fence_wait(device
->ws
,
4057 if (fence
->fence_wsi
) {
4058 VkResult result
= fence
->fence_wsi
->wait(fence
->fence_wsi
, timeout
);
4059 if (result
!= VK_SUCCESS
)
4067 VkResult
radv_ResetFences(VkDevice _device
,
4068 uint32_t fenceCount
,
4069 const VkFence
*pFences
)
4071 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4073 for (unsigned i
= 0; i
< fenceCount
; ++i
) {
4074 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
4076 device
->ws
->reset_fence(fence
->fence
);
4078 /* Per spec, we first restore the permanent payload, and then reset, so
4079 * having a temp syncobj should not skip resetting the permanent syncobj. */
4080 if (fence
->temp_syncobj
) {
4081 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
4082 fence
->temp_syncobj
= 0;
4085 if (fence
->syncobj
) {
4086 device
->ws
->reset_syncobj(device
->ws
, fence
->syncobj
);
4093 VkResult
radv_GetFenceStatus(VkDevice _device
, VkFence _fence
)
4095 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4096 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
4098 if (fence
->temp_syncobj
) {
4099 bool success
= device
->ws
->wait_syncobj(device
->ws
, &fence
->temp_syncobj
, 1, true, 0);
4100 return success
? VK_SUCCESS
: VK_NOT_READY
;
4103 if (fence
->syncobj
) {
4104 bool success
= device
->ws
->wait_syncobj(device
->ws
, &fence
->syncobj
, 1, true, 0);
4105 return success
? VK_SUCCESS
: VK_NOT_READY
;
4109 if (!device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0))
4110 return VK_NOT_READY
;
4112 if (fence
->fence_wsi
) {
4113 VkResult result
= fence
->fence_wsi
->wait(fence
->fence_wsi
, 0);
4115 if (result
!= VK_SUCCESS
) {
4116 if (result
== VK_TIMEOUT
)
4117 return VK_NOT_READY
;
4125 // Queue semaphore functions
4127 VkResult
radv_CreateSemaphore(
4129 const VkSemaphoreCreateInfo
* pCreateInfo
,
4130 const VkAllocationCallbacks
* pAllocator
,
4131 VkSemaphore
* pSemaphore
)
4133 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4134 const VkExportSemaphoreCreateInfo
*export
=
4135 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_SEMAPHORE_CREATE_INFO
);
4136 VkExternalSemaphoreHandleTypeFlags handleTypes
=
4137 export
? export
->handleTypes
: 0;
4139 struct radv_semaphore
*sem
= vk_alloc2(&device
->alloc
, pAllocator
,
4141 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4143 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4145 sem
->temp_syncobj
= 0;
4146 /* create a syncobject if we are going to export this semaphore */
4147 if (device
->always_use_syncobj
|| handleTypes
) {
4148 assert (device
->physical_device
->rad_info
.has_syncobj
);
4149 int ret
= device
->ws
->create_syncobj(device
->ws
, &sem
->syncobj
);
4151 vk_free2(&device
->alloc
, pAllocator
, sem
);
4152 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4156 sem
->sem
= device
->ws
->create_sem(device
->ws
);
4158 vk_free2(&device
->alloc
, pAllocator
, sem
);
4159 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4164 *pSemaphore
= radv_semaphore_to_handle(sem
);
4168 void radv_DestroySemaphore(
4170 VkSemaphore _semaphore
,
4171 const VkAllocationCallbacks
* pAllocator
)
4173 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4174 RADV_FROM_HANDLE(radv_semaphore
, sem
, _semaphore
);
4179 device
->ws
->destroy_syncobj(device
->ws
, sem
->syncobj
);
4181 device
->ws
->destroy_sem(sem
->sem
);
4182 vk_free2(&device
->alloc
, pAllocator
, sem
);
4185 VkResult
radv_CreateEvent(
4187 const VkEventCreateInfo
* pCreateInfo
,
4188 const VkAllocationCallbacks
* pAllocator
,
4191 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4192 struct radv_event
*event
= vk_alloc2(&device
->alloc
, pAllocator
,
4194 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4197 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4199 event
->bo
= device
->ws
->buffer_create(device
->ws
, 8, 8,
4201 RADEON_FLAG_VA_UNCACHED
| RADEON_FLAG_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
,
4202 RADV_BO_PRIORITY_FENCE
);
4204 vk_free2(&device
->alloc
, pAllocator
, event
);
4205 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
4208 event
->map
= (uint64_t*)device
->ws
->buffer_map(event
->bo
);
4210 *pEvent
= radv_event_to_handle(event
);
4215 void radv_DestroyEvent(
4218 const VkAllocationCallbacks
* pAllocator
)
4220 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4221 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4225 device
->ws
->buffer_destroy(event
->bo
);
4226 vk_free2(&device
->alloc
, pAllocator
, event
);
4229 VkResult
radv_GetEventStatus(
4233 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4235 if (*event
->map
== 1)
4236 return VK_EVENT_SET
;
4237 return VK_EVENT_RESET
;
4240 VkResult
radv_SetEvent(
4244 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4250 VkResult
radv_ResetEvent(
4254 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4260 VkResult
radv_CreateBuffer(
4262 const VkBufferCreateInfo
* pCreateInfo
,
4263 const VkAllocationCallbacks
* pAllocator
,
4266 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4267 struct radv_buffer
*buffer
;
4269 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO
);
4271 buffer
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*buffer
), 8,
4272 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4274 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4276 buffer
->size
= pCreateInfo
->size
;
4277 buffer
->usage
= pCreateInfo
->usage
;
4280 buffer
->flags
= pCreateInfo
->flags
;
4282 buffer
->shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
4283 EXTERNAL_MEMORY_BUFFER_CREATE_INFO
) != NULL
;
4285 if (pCreateInfo
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
) {
4286 buffer
->bo
= device
->ws
->buffer_create(device
->ws
,
4287 align64(buffer
->size
, 4096),
4288 4096, 0, RADEON_FLAG_VIRTUAL
,
4289 RADV_BO_PRIORITY_VIRTUAL
);
4291 vk_free2(&device
->alloc
, pAllocator
, buffer
);
4292 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
4296 *pBuffer
= radv_buffer_to_handle(buffer
);
4301 void radv_DestroyBuffer(
4304 const VkAllocationCallbacks
* pAllocator
)
4306 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4307 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4312 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
4313 device
->ws
->buffer_destroy(buffer
->bo
);
4315 vk_free2(&device
->alloc
, pAllocator
, buffer
);
4318 VkDeviceAddress
radv_GetBufferDeviceAddressEXT(
4320 const VkBufferDeviceAddressInfoEXT
* pInfo
)
4322 RADV_FROM_HANDLE(radv_buffer
, buffer
, pInfo
->buffer
);
4323 return radv_buffer_get_va(buffer
->bo
) + buffer
->offset
;
4327 static inline unsigned
4328 si_tile_mode_index(const struct radv_image_plane
*plane
, unsigned level
, bool stencil
)
4331 return plane
->surface
.u
.legacy
.stencil_tiling_index
[level
];
4333 return plane
->surface
.u
.legacy
.tiling_index
[level
];
4336 static uint32_t radv_surface_max_layer_count(struct radv_image_view
*iview
)
4338 return iview
->type
== VK_IMAGE_VIEW_TYPE_3D
? iview
->extent
.depth
: (iview
->base_layer
+ iview
->layer_count
);
4342 radv_init_dcc_control_reg(struct radv_device
*device
,
4343 struct radv_image_view
*iview
)
4345 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
4346 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
4347 unsigned max_compressed_block_size
;
4348 unsigned independent_128b_blocks
;
4349 unsigned independent_64b_blocks
;
4351 if (!radv_dcc_enabled(iview
->image
, iview
->base_mip
))
4354 if (!device
->physical_device
->rad_info
.has_dedicated_vram
) {
4355 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4356 * dGPU and 64 for APU because all of our APUs to date use
4357 * DIMMs which have a request granularity size of 64B while all
4358 * other chips have a 32B request size.
4360 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
4363 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4364 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
4365 independent_64b_blocks
= 0;
4366 independent_128b_blocks
= 1;
4368 independent_128b_blocks
= 0;
4370 if (iview
->image
->info
.samples
> 1) {
4371 if (iview
->image
->planes
[0].surface
.bpe
== 1)
4372 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
4373 else if (iview
->image
->planes
[0].surface
.bpe
== 2)
4374 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
4377 if (iview
->image
->usage
& (VK_IMAGE_USAGE_SAMPLED_BIT
|
4378 VK_IMAGE_USAGE_TRANSFER_SRC_BIT
|
4379 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)) {
4380 /* If this DCC image is potentially going to be used in texture
4381 * fetches, we need some special settings.
4383 independent_64b_blocks
= 1;
4384 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
4386 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4387 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4388 * big as possible for better compression state.
4390 independent_64b_blocks
= 0;
4391 max_compressed_block_size
= max_uncompressed_block_size
;
4395 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
4396 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size
) |
4397 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
4398 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks
) |
4399 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks
);
4403 radv_initialise_color_surface(struct radv_device
*device
,
4404 struct radv_color_buffer_info
*cb
,
4405 struct radv_image_view
*iview
)
4407 const struct vk_format_description
*desc
;
4408 unsigned ntype
, format
, swap
, endian
;
4409 unsigned blend_clamp
= 0, blend_bypass
= 0;
4411 const struct radv_image_plane
*plane
= &iview
->image
->planes
[iview
->plane_id
];
4412 const struct radeon_surf
*surf
= &plane
->surface
;
4414 desc
= vk_format_description(iview
->vk_format
);
4416 memset(cb
, 0, sizeof(*cb
));
4418 /* Intensity is implemented as Red, so treat it that way. */
4419 cb
->cb_color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == VK_SWIZZLE_1
);
4421 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ plane
->offset
;
4423 cb
->cb_color_base
= va
>> 8;
4425 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4426 struct gfx9_surf_meta_flags meta
;
4427 if (iview
->image
->dcc_offset
)
4428 meta
= surf
->u
.gfx9
.dcc
;
4430 meta
= surf
->u
.gfx9
.cmask
;
4432 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4433 cb
->cb_color_attrib3
|= S_028EE0_COLOR_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
4434 S_028EE0_FMASK_SW_MODE(surf
->u
.gfx9
.fmask
.swizzle_mode
) |
4435 S_028EE0_CMASK_PIPE_ALIGNED(surf
->u
.gfx9
.cmask
.pipe_aligned
) |
4436 S_028EE0_DCC_PIPE_ALIGNED(surf
->u
.gfx9
.dcc
.pipe_aligned
);
4438 cb
->cb_color_attrib
|= S_028C74_COLOR_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
4439 S_028C74_FMASK_SW_MODE(surf
->u
.gfx9
.fmask
.swizzle_mode
) |
4440 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
4441 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
4442 cb
->cb_mrt_epitch
= S_0287A0_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
4445 cb
->cb_color_base
+= surf
->u
.gfx9
.surf_offset
>> 8;
4446 cb
->cb_color_base
|= surf
->tile_swizzle
;
4448 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[iview
->base_mip
];
4449 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
4451 cb
->cb_color_base
+= level_info
->offset
>> 8;
4452 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
4453 cb
->cb_color_base
|= surf
->tile_swizzle
;
4455 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
4456 slice_tile_max
= (level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1;
4457 tile_mode_index
= si_tile_mode_index(plane
, iview
->base_mip
, false);
4459 cb
->cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
4460 cb
->cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
4461 cb
->cb_color_cmask_slice
= surf
->u
.legacy
.cmask_slice_tile_max
;
4463 cb
->cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
4465 if (radv_image_has_fmask(iview
->image
)) {
4466 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
4467 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(surf
->u
.legacy
.fmask
.pitch_in_pixels
/ 8 - 1);
4468 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(surf
->u
.legacy
.fmask
.tiling_index
);
4469 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(surf
->u
.legacy
.fmask
.slice_tile_max
);
4471 /* This must be set for fast clear to work without FMASK. */
4472 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
4473 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
4474 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
4475 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
4479 /* CMASK variables */
4480 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
4481 va
+= iview
->image
->cmask_offset
;
4482 cb
->cb_color_cmask
= va
>> 8;
4484 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
4485 va
+= iview
->image
->dcc_offset
;
4487 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
) &&
4488 device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4489 va
+= plane
->surface
.u
.legacy
.level
[iview
->base_mip
].dcc_offset
;
4491 unsigned dcc_tile_swizzle
= surf
->tile_swizzle
;
4492 dcc_tile_swizzle
&= (surf
->dcc_alignment
- 1) >> 8;
4494 cb
->cb_dcc_base
= va
>> 8;
4495 cb
->cb_dcc_base
|= dcc_tile_swizzle
;
4497 /* GFX10 field has the same base shift as the GFX6 field. */
4498 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
4499 cb
->cb_color_view
= S_028C6C_SLICE_START(iview
->base_layer
) |
4500 S_028C6C_SLICE_MAX_GFX10(max_slice
);
4502 if (iview
->image
->info
.samples
> 1) {
4503 unsigned log_samples
= util_logbase2(iview
->image
->info
.samples
);
4505 cb
->cb_color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
4506 S_028C74_NUM_FRAGMENTS(log_samples
);
4509 if (radv_image_has_fmask(iview
->image
)) {
4510 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ iview
->image
->fmask_offset
;
4511 cb
->cb_color_fmask
= va
>> 8;
4512 cb
->cb_color_fmask
|= surf
->fmask_tile_swizzle
;
4514 cb
->cb_color_fmask
= cb
->cb_color_base
;
4517 ntype
= radv_translate_color_numformat(iview
->vk_format
,
4519 vk_format_get_first_non_void_channel(iview
->vk_format
));
4520 format
= radv_translate_colorformat(iview
->vk_format
);
4521 if (format
== V_028C70_COLOR_INVALID
|| ntype
== ~0u)
4522 radv_finishme("Illegal color\n");
4523 swap
= radv_translate_colorswap(iview
->vk_format
, false);
4524 endian
= radv_colorformat_endian_swap(format
);
4526 /* blend clamp should be set for all NORM/SRGB types */
4527 if (ntype
== V_028C70_NUMBER_UNORM
||
4528 ntype
== V_028C70_NUMBER_SNORM
||
4529 ntype
== V_028C70_NUMBER_SRGB
)
4532 /* set blend bypass according to docs if SINT/UINT or
4533 8/24 COLOR variants */
4534 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
4535 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
4536 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
4541 if ((ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) &&
4542 (format
== V_028C70_COLOR_8
||
4543 format
== V_028C70_COLOR_8_8
||
4544 format
== V_028C70_COLOR_8_8_8_8
))
4545 ->color_is_int8
= true;
4547 cb
->cb_color_info
= S_028C70_FORMAT(format
) |
4548 S_028C70_COMP_SWAP(swap
) |
4549 S_028C70_BLEND_CLAMP(blend_clamp
) |
4550 S_028C70_BLEND_BYPASS(blend_bypass
) |
4551 S_028C70_SIMPLE_FLOAT(1) |
4552 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
4553 ntype
!= V_028C70_NUMBER_SNORM
&&
4554 ntype
!= V_028C70_NUMBER_SRGB
&&
4555 format
!= V_028C70_COLOR_8_24
&&
4556 format
!= V_028C70_COLOR_24_8
) |
4557 S_028C70_NUMBER_TYPE(ntype
) |
4558 S_028C70_ENDIAN(endian
);
4559 if (radv_image_has_fmask(iview
->image
)) {
4560 cb
->cb_color_info
|= S_028C70_COMPRESSION(1);
4561 if (device
->physical_device
->rad_info
.chip_class
== GFX6
) {
4562 unsigned fmask_bankh
= util_logbase2(surf
->u
.legacy
.fmask
.bankh
);
4563 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
4566 if (radv_image_is_tc_compat_cmask(iview
->image
)) {
4567 /* Allow the texture block to read FMASK directly
4568 * without decompressing it. This bit must be cleared
4569 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
4570 * otherwise the operation doesn't happen.
4572 cb
->cb_color_info
|= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
4574 /* Set CMASK into a tiling format that allows the
4575 * texture block to read it.
4577 cb
->cb_color_info
|= S_028C70_CMASK_ADDR_TYPE(2);
4581 if (radv_image_has_cmask(iview
->image
) &&
4582 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
))
4583 cb
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
4585 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
))
4586 cb
->cb_color_info
|= S_028C70_DCC_ENABLE(1);
4588 cb
->cb_dcc_control
= radv_init_dcc_control_reg(device
, iview
);
4590 /* This must be set for fast clear to work without FMASK. */
4591 if (!radv_image_has_fmask(iview
->image
) &&
4592 device
->physical_device
->rad_info
.chip_class
== GFX6
) {
4593 unsigned bankh
= util_logbase2(surf
->u
.legacy
.bankh
);
4594 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
4597 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4598 const struct vk_format_description
*format_desc
= vk_format_description(iview
->image
->vk_format
);
4600 unsigned mip0_depth
= iview
->image
->type
== VK_IMAGE_TYPE_3D
?
4601 (iview
->extent
.depth
- 1) : (iview
->image
->info
.array_size
- 1);
4602 unsigned width
= iview
->extent
.width
/ (iview
->plane_id
? format_desc
->width_divisor
: 1);
4603 unsigned height
= iview
->extent
.height
/ (iview
->plane_id
? format_desc
->height_divisor
: 1);
4605 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4606 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL_GFX10(iview
->base_mip
);
4608 cb
->cb_color_attrib3
|= S_028EE0_MIP0_DEPTH(mip0_depth
) |
4609 S_028EE0_RESOURCE_TYPE(surf
->u
.gfx9
.resource_type
) |
4610 S_028EE0_RESOURCE_LEVEL(1);
4612 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL_GFX9(iview
->base_mip
);
4613 cb
->cb_color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
4614 S_028C74_RESOURCE_TYPE(surf
->u
.gfx9
.resource_type
);
4617 cb
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(width
- 1) |
4618 S_028C68_MIP0_HEIGHT(height
- 1) |
4619 S_028C68_MAX_MIP(iview
->image
->info
.levels
- 1);
4624 radv_calc_decompress_on_z_planes(struct radv_device
*device
,
4625 struct radv_image_view
*iview
)
4627 unsigned max_zplanes
= 0;
4629 assert(radv_image_is_tc_compat_htile(iview
->image
));
4631 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4632 /* Default value for 32-bit depth surfaces. */
4635 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
&&
4636 iview
->image
->info
.samples
> 1)
4639 max_zplanes
= max_zplanes
+ 1;
4641 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
) {
4642 /* Do not enable Z plane compression for 16-bit depth
4643 * surfaces because isn't supported on GFX8. Only
4644 * 32-bit depth surfaces are supported by the hardware.
4645 * This allows to maintain shader compatibility and to
4646 * reduce the number of depth decompressions.
4650 if (iview
->image
->info
.samples
<= 1)
4652 else if (iview
->image
->info
.samples
<= 4)
4663 radv_initialise_ds_surface(struct radv_device
*device
,
4664 struct radv_ds_buffer_info
*ds
,
4665 struct radv_image_view
*iview
)
4667 unsigned level
= iview
->base_mip
;
4668 unsigned format
, stencil_format
;
4669 uint64_t va
, s_offs
, z_offs
;
4670 bool stencil_only
= false;
4671 const struct radv_image_plane
*plane
= &iview
->image
->planes
[0];
4672 const struct radeon_surf
*surf
= &plane
->surface
;
4674 assert(vk_format_get_plane_count(iview
->image
->vk_format
) == 1);
4676 memset(ds
, 0, sizeof(*ds
));
4677 switch (iview
->image
->vk_format
) {
4678 case VK_FORMAT_D24_UNORM_S8_UINT
:
4679 case VK_FORMAT_X8_D24_UNORM_PACK32
:
4680 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4681 ds
->offset_scale
= 2.0f
;
4683 case VK_FORMAT_D16_UNORM
:
4684 case VK_FORMAT_D16_UNORM_S8_UINT
:
4685 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4686 ds
->offset_scale
= 4.0f
;
4688 case VK_FORMAT_D32_SFLOAT
:
4689 case VK_FORMAT_D32_SFLOAT_S8_UINT
:
4690 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4691 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4692 ds
->offset_scale
= 1.0f
;
4694 case VK_FORMAT_S8_UINT
:
4695 stencil_only
= true;
4701 format
= radv_translate_dbformat(iview
->image
->vk_format
);
4702 stencil_format
= surf
->has_stencil
?
4703 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
4705 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
4706 ds
->db_depth_view
= S_028008_SLICE_START(iview
->base_layer
) |
4707 S_028008_SLICE_MAX(max_slice
);
4708 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4709 ds
->db_depth_view
|= S_028008_SLICE_START_HI(iview
->base_layer
>> 11) |
4710 S_028008_SLICE_MAX_HI(max_slice
>> 11);
4713 ds
->db_htile_data_base
= 0;
4714 ds
->db_htile_surface
= 0;
4716 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
4717 s_offs
= z_offs
= va
;
4719 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4720 assert(surf
->u
.gfx9
.surf_offset
== 0);
4721 s_offs
+= surf
->u
.gfx9
.stencil_offset
;
4723 ds
->db_z_info
= S_028038_FORMAT(format
) |
4724 S_028038_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
)) |
4725 S_028038_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
4726 S_028038_MAXMIP(iview
->image
->info
.levels
- 1) |
4727 S_028038_ZRANGE_PRECISION(1);
4728 ds
->db_stencil_info
= S_02803C_FORMAT(stencil_format
) |
4729 S_02803C_SW_MODE(surf
->u
.gfx9
.stencil
.swizzle_mode
);
4731 if (device
->physical_device
->rad_info
.chip_class
== GFX9
) {
4732 ds
->db_z_info2
= S_028068_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
4733 ds
->db_stencil_info2
= S_02806C_EPITCH(surf
->u
.gfx9
.stencil
.epitch
);
4736 ds
->db_depth_view
|= S_028008_MIPID(level
);
4737 ds
->db_depth_size
= S_02801C_X_MAX(iview
->image
->info
.width
- 1) |
4738 S_02801C_Y_MAX(iview
->image
->info
.height
- 1);
4740 if (radv_htile_enabled(iview
->image
, level
)) {
4741 ds
->db_z_info
|= S_028038_TILE_SURFACE_ENABLE(1);
4743 if (radv_image_is_tc_compat_htile(iview
->image
)) {
4744 unsigned max_zplanes
=
4745 radv_calc_decompress_on_z_planes(device
, iview
);
4747 ds
->db_z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
4749 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4750 ds
->db_z_info
|= S_028040_ITERATE_FLUSH(1);
4751 ds
->db_stencil_info
|= S_028044_ITERATE_FLUSH(1);
4753 ds
->db_z_info
|= S_028038_ITERATE_FLUSH(1);
4754 ds
->db_stencil_info
|= S_02803C_ITERATE_FLUSH(1);
4758 if (!surf
->has_stencil
)
4759 /* Use all of the htile_buffer for depth if there's no stencil. */
4760 ds
->db_stencil_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
4761 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
4762 iview
->image
->htile_offset
;
4763 ds
->db_htile_data_base
= va
>> 8;
4764 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
4765 S_028ABC_PIPE_ALIGNED(surf
->u
.gfx9
.htile
.pipe_aligned
);
4767 if (device
->physical_device
->rad_info
.chip_class
== GFX9
) {
4768 ds
->db_htile_surface
|= S_028ABC_RB_ALIGNED(surf
->u
.gfx9
.htile
.rb_aligned
);
4772 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[level
];
4775 level_info
= &surf
->u
.legacy
.stencil_level
[level
];
4777 z_offs
+= surf
->u
.legacy
.level
[level
].offset
;
4778 s_offs
+= surf
->u
.legacy
.stencil_level
[level
].offset
;
4780 ds
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview
->image
));
4781 ds
->db_z_info
= S_028040_FORMAT(format
) | S_028040_ZRANGE_PRECISION(1);
4782 ds
->db_stencil_info
= S_028044_FORMAT(stencil_format
);
4784 if (iview
->image
->info
.samples
> 1)
4785 ds
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
));
4787 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4788 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
4789 unsigned tiling_index
= surf
->u
.legacy
.tiling_index
[level
];
4790 unsigned stencil_index
= surf
->u
.legacy
.stencil_tiling_index
[level
];
4791 unsigned macro_index
= surf
->u
.legacy
.macro_tile_index
;
4792 unsigned tile_mode
= info
->si_tile_mode_array
[tiling_index
];
4793 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
4794 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
4797 tile_mode
= stencil_tile_mode
;
4799 ds
->db_depth_info
|=
4800 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
4801 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
4802 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
4803 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
4804 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
4805 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
4806 ds
->db_z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
4807 ds
->db_stencil_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
4809 unsigned tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, false);
4810 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
4811 tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, true);
4812 ds
->db_stencil_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
4814 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
4817 ds
->db_depth_size
= S_028058_PITCH_TILE_MAX((level_info
->nblk_x
/ 8) - 1) |
4818 S_028058_HEIGHT_TILE_MAX((level_info
->nblk_y
/ 8) - 1);
4819 ds
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1);
4821 if (radv_htile_enabled(iview
->image
, level
)) {
4822 ds
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
4824 if (!surf
->has_stencil
&&
4825 !radv_image_is_tc_compat_htile(iview
->image
))
4826 /* Use all of the htile_buffer for depth if there's no stencil. */
4827 ds
->db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
4829 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
4830 iview
->image
->htile_offset
;
4831 ds
->db_htile_data_base
= va
>> 8;
4832 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
4834 if (radv_image_is_tc_compat_htile(iview
->image
)) {
4835 unsigned max_zplanes
=
4836 radv_calc_decompress_on_z_planes(device
, iview
);
4838 ds
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
4839 ds
->db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
4844 ds
->db_z_read_base
= ds
->db_z_write_base
= z_offs
>> 8;
4845 ds
->db_stencil_read_base
= ds
->db_stencil_write_base
= s_offs
>> 8;
4848 VkResult
radv_CreateFramebuffer(
4850 const VkFramebufferCreateInfo
* pCreateInfo
,
4851 const VkAllocationCallbacks
* pAllocator
,
4852 VkFramebuffer
* pFramebuffer
)
4854 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4855 struct radv_framebuffer
*framebuffer
;
4856 const VkFramebufferAttachmentsCreateInfoKHR
*imageless_create_info
=
4857 vk_find_struct_const(pCreateInfo
->pNext
,
4858 FRAMEBUFFER_ATTACHMENTS_CREATE_INFO_KHR
);
4860 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
);
4862 size_t size
= sizeof(*framebuffer
);
4863 if (!imageless_create_info
)
4864 size
+= sizeof(struct radv_image_view
*) * pCreateInfo
->attachmentCount
;
4865 framebuffer
= vk_alloc2(&device
->alloc
, pAllocator
, size
, 8,
4866 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4867 if (framebuffer
== NULL
)
4868 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4870 framebuffer
->attachment_count
= pCreateInfo
->attachmentCount
;
4871 framebuffer
->width
= pCreateInfo
->width
;
4872 framebuffer
->height
= pCreateInfo
->height
;
4873 framebuffer
->layers
= pCreateInfo
->layers
;
4874 if (imageless_create_info
) {
4875 for (unsigned i
= 0; i
< imageless_create_info
->attachmentImageInfoCount
; ++i
) {
4876 const VkFramebufferAttachmentImageInfoKHR
*attachment
=
4877 imageless_create_info
->pAttachmentImageInfos
+ i
;
4878 framebuffer
->width
= MIN2(framebuffer
->width
, attachment
->width
);
4879 framebuffer
->height
= MIN2(framebuffer
->height
, attachment
->height
);
4880 framebuffer
->layers
= MIN2(framebuffer
->layers
, attachment
->layerCount
);
4883 for (uint32_t i
= 0; i
< pCreateInfo
->attachmentCount
; i
++) {
4884 VkImageView _iview
= pCreateInfo
->pAttachments
[i
];
4885 struct radv_image_view
*iview
= radv_image_view_from_handle(_iview
);
4886 framebuffer
->attachments
[i
] = iview
;
4887 framebuffer
->width
= MIN2(framebuffer
->width
, iview
->extent
.width
);
4888 framebuffer
->height
= MIN2(framebuffer
->height
, iview
->extent
.height
);
4889 framebuffer
->layers
= MIN2(framebuffer
->layers
, radv_surface_max_layer_count(iview
));
4893 *pFramebuffer
= radv_framebuffer_to_handle(framebuffer
);
4897 void radv_DestroyFramebuffer(
4900 const VkAllocationCallbacks
* pAllocator
)
4902 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4903 RADV_FROM_HANDLE(radv_framebuffer
, fb
, _fb
);
4907 vk_free2(&device
->alloc
, pAllocator
, fb
);
4910 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode
)
4912 switch (address_mode
) {
4913 case VK_SAMPLER_ADDRESS_MODE_REPEAT
:
4914 return V_008F30_SQ_TEX_WRAP
;
4915 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT
:
4916 return V_008F30_SQ_TEX_MIRROR
;
4917 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
:
4918 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
4919 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
:
4920 return V_008F30_SQ_TEX_CLAMP_BORDER
;
4921 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE
:
4922 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
4924 unreachable("illegal tex wrap mode");
4930 radv_tex_compare(VkCompareOp op
)
4933 case VK_COMPARE_OP_NEVER
:
4934 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
4935 case VK_COMPARE_OP_LESS
:
4936 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
4937 case VK_COMPARE_OP_EQUAL
:
4938 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
4939 case VK_COMPARE_OP_LESS_OR_EQUAL
:
4940 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
4941 case VK_COMPARE_OP_GREATER
:
4942 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
4943 case VK_COMPARE_OP_NOT_EQUAL
:
4944 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
4945 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
4946 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
4947 case VK_COMPARE_OP_ALWAYS
:
4948 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
4950 unreachable("illegal compare mode");
4956 radv_tex_filter(VkFilter filter
, unsigned max_ansio
)
4959 case VK_FILTER_NEAREST
:
4960 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
:
4961 V_008F38_SQ_TEX_XY_FILTER_POINT
);
4962 case VK_FILTER_LINEAR
:
4963 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
:
4964 V_008F38_SQ_TEX_XY_FILTER_BILINEAR
);
4965 case VK_FILTER_CUBIC_IMG
:
4967 fprintf(stderr
, "illegal texture filter");
4973 radv_tex_mipfilter(VkSamplerMipmapMode mode
)
4976 case VK_SAMPLER_MIPMAP_MODE_NEAREST
:
4977 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
4978 case VK_SAMPLER_MIPMAP_MODE_LINEAR
:
4979 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
4981 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
4986 radv_tex_bordercolor(VkBorderColor bcolor
)
4989 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
:
4990 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK
:
4991 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
4992 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK
:
4993 case VK_BORDER_COLOR_INT_OPAQUE_BLACK
:
4994 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
4995 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE
:
4996 case VK_BORDER_COLOR_INT_OPAQUE_WHITE
:
4997 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
5005 radv_tex_aniso_filter(unsigned filter
)
5019 radv_tex_filter_mode(VkSamplerReductionModeEXT mode
)
5022 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT
:
5023 return V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
5024 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT
:
5025 return V_008F30_SQ_IMG_FILTER_MODE_MIN
;
5026 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT
:
5027 return V_008F30_SQ_IMG_FILTER_MODE_MAX
;
5035 radv_get_max_anisotropy(struct radv_device
*device
,
5036 const VkSamplerCreateInfo
*pCreateInfo
)
5038 if (device
->force_aniso
>= 0)
5039 return device
->force_aniso
;
5041 if (pCreateInfo
->anisotropyEnable
&&
5042 pCreateInfo
->maxAnisotropy
> 1.0f
)
5043 return (uint32_t)pCreateInfo
->maxAnisotropy
;
5049 radv_init_sampler(struct radv_device
*device
,
5050 struct radv_sampler
*sampler
,
5051 const VkSamplerCreateInfo
*pCreateInfo
)
5053 uint32_t max_aniso
= radv_get_max_anisotropy(device
, pCreateInfo
);
5054 uint32_t max_aniso_ratio
= radv_tex_aniso_filter(max_aniso
);
5055 bool compat_mode
= device
->physical_device
->rad_info
.chip_class
== GFX8
||
5056 device
->physical_device
->rad_info
.chip_class
== GFX9
;
5057 unsigned filter_mode
= V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
5059 const struct VkSamplerReductionModeCreateInfoEXT
*sampler_reduction
=
5060 vk_find_struct_const(pCreateInfo
->pNext
,
5061 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT
);
5062 if (sampler_reduction
)
5063 filter_mode
= radv_tex_filter_mode(sampler_reduction
->reductionMode
);
5065 sampler
->state
[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo
->addressModeU
)) |
5066 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo
->addressModeV
)) |
5067 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo
->addressModeW
)) |
5068 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
5069 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo
->compareOp
)) |
5070 S_008F30_FORCE_UNNORMALIZED(pCreateInfo
->unnormalizedCoordinates
? 1 : 0) |
5071 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
5072 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
5073 S_008F30_DISABLE_CUBE_WRAP(0) |
5074 S_008F30_COMPAT_MODE(compat_mode
) |
5075 S_008F30_FILTER_MODE(filter_mode
));
5076 sampler
->state
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo
->minLod
, 0, 15), 8)) |
5077 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo
->maxLod
, 0, 15), 8)) |
5078 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
5079 sampler
->state
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo
->mipLodBias
, -16, 16), 8)) |
5080 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo
->magFilter
, max_aniso
)) |
5081 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo
->minFilter
, max_aniso
)) |
5082 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo
->mipmapMode
)) |
5083 S_008F38_MIP_POINT_PRECLAMP(0));
5084 sampler
->state
[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
5085 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo
->borderColor
)));
5087 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
5088 sampler
->state
[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
5090 sampler
->state
[2] |=
5091 S_008F38_DISABLE_LSB_CEIL(device
->physical_device
->rad_info
.chip_class
<= GFX8
) |
5092 S_008F38_FILTER_PREC_FIX(1) |
5093 S_008F38_ANISO_OVERRIDE_GFX6(device
->physical_device
->rad_info
.chip_class
>= GFX8
);
5097 VkResult
radv_CreateSampler(
5099 const VkSamplerCreateInfo
* pCreateInfo
,
5100 const VkAllocationCallbacks
* pAllocator
,
5101 VkSampler
* pSampler
)
5103 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5104 struct radv_sampler
*sampler
;
5106 const struct VkSamplerYcbcrConversionInfo
*ycbcr_conversion
=
5107 vk_find_struct_const(pCreateInfo
->pNext
,
5108 SAMPLER_YCBCR_CONVERSION_INFO
);
5110 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO
);
5112 sampler
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*sampler
), 8,
5113 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5115 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5117 radv_init_sampler(device
, sampler
, pCreateInfo
);
5119 sampler
->ycbcr_sampler
= ycbcr_conversion
? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion
->conversion
): NULL
;
5120 *pSampler
= radv_sampler_to_handle(sampler
);
5125 void radv_DestroySampler(
5128 const VkAllocationCallbacks
* pAllocator
)
5130 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5131 RADV_FROM_HANDLE(radv_sampler
, sampler
, _sampler
);
5135 vk_free2(&device
->alloc
, pAllocator
, sampler
);
5138 /* vk_icd.h does not declare this function, so we declare it here to
5139 * suppress Wmissing-prototypes.
5141 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5142 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
);
5144 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5145 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
)
5147 /* For the full details on loader interface versioning, see
5148 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
5149 * What follows is a condensed summary, to help you navigate the large and
5150 * confusing official doc.
5152 * - Loader interface v0 is incompatible with later versions. We don't
5155 * - In loader interface v1:
5156 * - The first ICD entrypoint called by the loader is
5157 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
5159 * - The ICD must statically expose no other Vulkan symbol unless it is
5160 * linked with -Bsymbolic.
5161 * - Each dispatchable Vulkan handle created by the ICD must be
5162 * a pointer to a struct whose first member is VK_LOADER_DATA. The
5163 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
5164 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
5165 * vkDestroySurfaceKHR(). The ICD must be capable of working with
5166 * such loader-managed surfaces.
5168 * - Loader interface v2 differs from v1 in:
5169 * - The first ICD entrypoint called by the loader is
5170 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
5171 * statically expose this entrypoint.
5173 * - Loader interface v3 differs from v2 in:
5174 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
5175 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
5176 * because the loader no longer does so.
5178 *pSupportedVersion
= MIN2(*pSupportedVersion
, 4u);
5182 VkResult
radv_GetMemoryFdKHR(VkDevice _device
,
5183 const VkMemoryGetFdInfoKHR
*pGetFdInfo
,
5186 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5187 RADV_FROM_HANDLE(radv_device_memory
, memory
, pGetFdInfo
->memory
);
5189 assert(pGetFdInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR
);
5191 /* At the moment, we support only the below handle types. */
5192 assert(pGetFdInfo
->handleType
==
5193 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
5194 pGetFdInfo
->handleType
==
5195 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
5197 bool ret
= radv_get_memory_fd(device
, memory
, pFD
);
5199 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
5203 VkResult
radv_GetMemoryFdPropertiesKHR(VkDevice _device
,
5204 VkExternalMemoryHandleTypeFlagBits handleType
,
5206 VkMemoryFdPropertiesKHR
*pMemoryFdProperties
)
5208 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5210 switch (handleType
) {
5211 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
:
5212 pMemoryFdProperties
->memoryTypeBits
= (1 << RADV_MEM_TYPE_COUNT
) - 1;
5216 /* The valid usage section for this function says:
5218 * "handleType must not be one of the handle types defined as
5221 * So opaque handle types fall into the default "unsupported" case.
5223 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5227 static VkResult
radv_import_opaque_fd(struct radv_device
*device
,
5231 uint32_t syncobj_handle
= 0;
5232 int ret
= device
->ws
->import_syncobj(device
->ws
, fd
, &syncobj_handle
);
5234 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5237 device
->ws
->destroy_syncobj(device
->ws
, *syncobj
);
5239 *syncobj
= syncobj_handle
;
5245 static VkResult
radv_import_sync_fd(struct radv_device
*device
,
5249 /* If we create a syncobj we do it locally so that if we have an error, we don't
5250 * leave a syncobj in an undetermined state in the fence. */
5251 uint32_t syncobj_handle
= *syncobj
;
5252 if (!syncobj_handle
) {
5253 int ret
= device
->ws
->create_syncobj(device
->ws
, &syncobj_handle
);
5255 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5260 device
->ws
->signal_syncobj(device
->ws
, syncobj_handle
);
5262 int ret
= device
->ws
->import_syncobj_from_sync_file(device
->ws
, syncobj_handle
, fd
);
5264 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5267 *syncobj
= syncobj_handle
;
5274 VkResult
radv_ImportSemaphoreFdKHR(VkDevice _device
,
5275 const VkImportSemaphoreFdInfoKHR
*pImportSemaphoreFdInfo
)
5277 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5278 RADV_FROM_HANDLE(radv_semaphore
, sem
, pImportSemaphoreFdInfo
->semaphore
);
5279 uint32_t *syncobj_dst
= NULL
;
5281 if (pImportSemaphoreFdInfo
->flags
& VK_SEMAPHORE_IMPORT_TEMPORARY_BIT
) {
5282 syncobj_dst
= &sem
->temp_syncobj
;
5284 syncobj_dst
= &sem
->syncobj
;
5287 switch(pImportSemaphoreFdInfo
->handleType
) {
5288 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5289 return radv_import_opaque_fd(device
, pImportSemaphoreFdInfo
->fd
, syncobj_dst
);
5290 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
5291 return radv_import_sync_fd(device
, pImportSemaphoreFdInfo
->fd
, syncobj_dst
);
5293 unreachable("Unhandled semaphore handle type");
5297 VkResult
radv_GetSemaphoreFdKHR(VkDevice _device
,
5298 const VkSemaphoreGetFdInfoKHR
*pGetFdInfo
,
5301 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5302 RADV_FROM_HANDLE(radv_semaphore
, sem
, pGetFdInfo
->semaphore
);
5304 uint32_t syncobj_handle
;
5306 if (sem
->temp_syncobj
)
5307 syncobj_handle
= sem
->temp_syncobj
;
5309 syncobj_handle
= sem
->syncobj
;
5311 switch(pGetFdInfo
->handleType
) {
5312 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5313 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
5315 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
5316 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
5318 if (sem
->temp_syncobj
) {
5319 close (sem
->temp_syncobj
);
5320 sem
->temp_syncobj
= 0;
5322 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
5327 unreachable("Unhandled semaphore handle type");
5331 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5335 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5336 VkPhysicalDevice physicalDevice
,
5337 const VkPhysicalDeviceExternalSemaphoreInfo
*pExternalSemaphoreInfo
,
5338 VkExternalSemaphoreProperties
*pExternalSemaphoreProperties
)
5340 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
5342 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5343 if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
5344 (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
||
5345 pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
)) {
5346 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
5347 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
5348 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
5349 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
5350 } else if (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
) {
5351 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
5352 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
5353 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
5354 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
5356 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= 0;
5357 pExternalSemaphoreProperties
->compatibleHandleTypes
= 0;
5358 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= 0;
5362 VkResult
radv_ImportFenceFdKHR(VkDevice _device
,
5363 const VkImportFenceFdInfoKHR
*pImportFenceFdInfo
)
5365 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5366 RADV_FROM_HANDLE(radv_fence
, fence
, pImportFenceFdInfo
->fence
);
5367 uint32_t *syncobj_dst
= NULL
;
5370 if (pImportFenceFdInfo
->flags
& VK_FENCE_IMPORT_TEMPORARY_BIT
) {
5371 syncobj_dst
= &fence
->temp_syncobj
;
5373 syncobj_dst
= &fence
->syncobj
;
5376 switch(pImportFenceFdInfo
->handleType
) {
5377 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5378 return radv_import_opaque_fd(device
, pImportFenceFdInfo
->fd
, syncobj_dst
);
5379 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
5380 return radv_import_sync_fd(device
, pImportFenceFdInfo
->fd
, syncobj_dst
);
5382 unreachable("Unhandled fence handle type");
5386 VkResult
radv_GetFenceFdKHR(VkDevice _device
,
5387 const VkFenceGetFdInfoKHR
*pGetFdInfo
,
5390 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5391 RADV_FROM_HANDLE(radv_fence
, fence
, pGetFdInfo
->fence
);
5393 uint32_t syncobj_handle
;
5395 if (fence
->temp_syncobj
)
5396 syncobj_handle
= fence
->temp_syncobj
;
5398 syncobj_handle
= fence
->syncobj
;
5400 switch(pGetFdInfo
->handleType
) {
5401 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5402 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
5404 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
5405 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
5407 if (fence
->temp_syncobj
) {
5408 close (fence
->temp_syncobj
);
5409 fence
->temp_syncobj
= 0;
5411 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
5416 unreachable("Unhandled fence handle type");
5420 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5424 void radv_GetPhysicalDeviceExternalFenceProperties(
5425 VkPhysicalDevice physicalDevice
,
5426 const VkPhysicalDeviceExternalFenceInfo
*pExternalFenceInfo
,
5427 VkExternalFenceProperties
*pExternalFenceProperties
)
5429 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
5431 if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
5432 (pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
||
5433 pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
)) {
5434 pExternalFenceProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
5435 pExternalFenceProperties
->compatibleHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
5436 pExternalFenceProperties
->externalFenceFeatures
= VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT
|
5437 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
5439 pExternalFenceProperties
->exportFromImportedHandleTypes
= 0;
5440 pExternalFenceProperties
->compatibleHandleTypes
= 0;
5441 pExternalFenceProperties
->externalFenceFeatures
= 0;
5446 radv_CreateDebugReportCallbackEXT(VkInstance _instance
,
5447 const VkDebugReportCallbackCreateInfoEXT
* pCreateInfo
,
5448 const VkAllocationCallbacks
* pAllocator
,
5449 VkDebugReportCallbackEXT
* pCallback
)
5451 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
5452 return vk_create_debug_report_callback(&instance
->debug_report_callbacks
,
5453 pCreateInfo
, pAllocator
, &instance
->alloc
,
5458 radv_DestroyDebugReportCallbackEXT(VkInstance _instance
,
5459 VkDebugReportCallbackEXT _callback
,
5460 const VkAllocationCallbacks
* pAllocator
)
5462 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
5463 vk_destroy_debug_report_callback(&instance
->debug_report_callbacks
,
5464 _callback
, pAllocator
, &instance
->alloc
);
5468 radv_DebugReportMessageEXT(VkInstance _instance
,
5469 VkDebugReportFlagsEXT flags
,
5470 VkDebugReportObjectTypeEXT objectType
,
5473 int32_t messageCode
,
5474 const char* pLayerPrefix
,
5475 const char* pMessage
)
5477 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
5478 vk_debug_report(&instance
->debug_report_callbacks
, flags
, objectType
,
5479 object
, location
, messageCode
, pLayerPrefix
, pMessage
);
5483 radv_GetDeviceGroupPeerMemoryFeatures(
5486 uint32_t localDeviceIndex
,
5487 uint32_t remoteDeviceIndex
,
5488 VkPeerMemoryFeatureFlags
* pPeerMemoryFeatures
)
5490 assert(localDeviceIndex
== remoteDeviceIndex
);
5492 *pPeerMemoryFeatures
= VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT
|
5493 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT
|
5494 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT
|
5495 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT
;
5498 static const VkTimeDomainEXT radv_time_domains
[] = {
5499 VK_TIME_DOMAIN_DEVICE_EXT
,
5500 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
,
5501 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
,
5504 VkResult
radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5505 VkPhysicalDevice physicalDevice
,
5506 uint32_t *pTimeDomainCount
,
5507 VkTimeDomainEXT
*pTimeDomains
)
5510 VK_OUTARRAY_MAKE(out
, pTimeDomains
, pTimeDomainCount
);
5512 for (d
= 0; d
< ARRAY_SIZE(radv_time_domains
); d
++) {
5513 vk_outarray_append(&out
, i
) {
5514 *i
= radv_time_domains
[d
];
5518 return vk_outarray_status(&out
);
5522 radv_clock_gettime(clockid_t clock_id
)
5524 struct timespec current
;
5527 ret
= clock_gettime(clock_id
, ¤t
);
5528 if (ret
< 0 && clock_id
== CLOCK_MONOTONIC_RAW
)
5529 ret
= clock_gettime(CLOCK_MONOTONIC
, ¤t
);
5533 return (uint64_t) current
.tv_sec
* 1000000000ULL + current
.tv_nsec
;
5536 VkResult
radv_GetCalibratedTimestampsEXT(
5538 uint32_t timestampCount
,
5539 const VkCalibratedTimestampInfoEXT
*pTimestampInfos
,
5540 uint64_t *pTimestamps
,
5541 uint64_t *pMaxDeviation
)
5543 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5544 uint32_t clock_crystal_freq
= device
->physical_device
->rad_info
.clock_crystal_freq
;
5546 uint64_t begin
, end
;
5547 uint64_t max_clock_period
= 0;
5549 begin
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
5551 for (d
= 0; d
< timestampCount
; d
++) {
5552 switch (pTimestampInfos
[d
].timeDomain
) {
5553 case VK_TIME_DOMAIN_DEVICE_EXT
:
5554 pTimestamps
[d
] = device
->ws
->query_value(device
->ws
,
5556 uint64_t device_period
= DIV_ROUND_UP(1000000, clock_crystal_freq
);
5557 max_clock_period
= MAX2(max_clock_period
, device_period
);
5559 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
:
5560 pTimestamps
[d
] = radv_clock_gettime(CLOCK_MONOTONIC
);
5561 max_clock_period
= MAX2(max_clock_period
, 1);
5564 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
:
5565 pTimestamps
[d
] = begin
;
5573 end
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
5576 * The maximum deviation is the sum of the interval over which we
5577 * perform the sampling and the maximum period of any sampled
5578 * clock. That's because the maximum skew between any two sampled
5579 * clock edges is when the sampled clock with the largest period is
5580 * sampled at the end of that period but right at the beginning of the
5581 * sampling interval and some other clock is sampled right at the
5582 * begining of its sampling period and right at the end of the
5583 * sampling interval. Let's assume the GPU has the longest clock
5584 * period and that the application is sampling GPU and monotonic:
5587 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5588 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5592 * GPU -----_____-----_____-----_____-----_____
5595 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5596 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5598 * Interval <----------------->
5599 * Deviation <-------------------------->
5603 * m = read(monotonic) 2
5606 * We round the sample interval up by one tick to cover sampling error
5607 * in the interval clock
5610 uint64_t sample_interval
= end
- begin
+ 1;
5612 *pMaxDeviation
= sample_interval
+ max_clock_period
;
5617 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
5618 VkPhysicalDevice physicalDevice
,
5619 VkSampleCountFlagBits samples
,
5620 VkMultisamplePropertiesEXT
* pMultisampleProperties
)
5622 if (samples
& (VK_SAMPLE_COUNT_2_BIT
|
5623 VK_SAMPLE_COUNT_4_BIT
|
5624 VK_SAMPLE_COUNT_8_BIT
)) {
5625 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2, 2 };
5627 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 0, 0 };