2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
47 #include "util/build_id.h"
48 #include "util/debug.h"
49 #include "util/mesa-sha1.h"
50 #include "compiler/glsl_types.h"
51 #include "util/xmlpool.h"
54 radv_device_get_cache_uuid(enum radeon_family family
, void *uuid
)
57 unsigned char sha1
[20];
58 unsigned ptr_size
= sizeof(void*);
60 memset(uuid
, 0, VK_UUID_SIZE
);
61 _mesa_sha1_init(&ctx
);
63 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid
, &ctx
) ||
64 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo
, &ctx
))
67 _mesa_sha1_update(&ctx
, &family
, sizeof(family
));
68 _mesa_sha1_update(&ctx
, &ptr_size
, sizeof(ptr_size
));
69 _mesa_sha1_final(&ctx
, sha1
);
71 memcpy(uuid
, sha1
, VK_UUID_SIZE
);
76 radv_get_driver_uuid(void *uuid
)
78 ac_compute_driver_uuid(uuid
, VK_UUID_SIZE
);
82 radv_get_device_uuid(struct radeon_info
*info
, void *uuid
)
84 ac_compute_device_uuid(info
, uuid
, VK_UUID_SIZE
);
88 radv_get_device_name(enum radeon_family family
, char *name
, size_t name_len
)
90 const char *chip_string
;
93 case CHIP_TAHITI
: chip_string
= "AMD RADV TAHITI"; break;
94 case CHIP_PITCAIRN
: chip_string
= "AMD RADV PITCAIRN"; break;
95 case CHIP_VERDE
: chip_string
= "AMD RADV CAPE VERDE"; break;
96 case CHIP_OLAND
: chip_string
= "AMD RADV OLAND"; break;
97 case CHIP_HAINAN
: chip_string
= "AMD RADV HAINAN"; break;
98 case CHIP_BONAIRE
: chip_string
= "AMD RADV BONAIRE"; break;
99 case CHIP_KAVERI
: chip_string
= "AMD RADV KAVERI"; break;
100 case CHIP_KABINI
: chip_string
= "AMD RADV KABINI"; break;
101 case CHIP_HAWAII
: chip_string
= "AMD RADV HAWAII"; break;
102 case CHIP_TONGA
: chip_string
= "AMD RADV TONGA"; break;
103 case CHIP_ICELAND
: chip_string
= "AMD RADV ICELAND"; break;
104 case CHIP_CARRIZO
: chip_string
= "AMD RADV CARRIZO"; break;
105 case CHIP_FIJI
: chip_string
= "AMD RADV FIJI"; break;
106 case CHIP_POLARIS10
: chip_string
= "AMD RADV POLARIS10"; break;
107 case CHIP_POLARIS11
: chip_string
= "AMD RADV POLARIS11"; break;
108 case CHIP_POLARIS12
: chip_string
= "AMD RADV POLARIS12"; break;
109 case CHIP_STONEY
: chip_string
= "AMD RADV STONEY"; break;
110 case CHIP_VEGAM
: chip_string
= "AMD RADV VEGA M"; break;
111 case CHIP_VEGA10
: chip_string
= "AMD RADV VEGA10"; break;
112 case CHIP_VEGA12
: chip_string
= "AMD RADV VEGA12"; break;
113 case CHIP_VEGA20
: chip_string
= "AMD RADV VEGA20"; break;
114 case CHIP_RAVEN
: chip_string
= "AMD RADV RAVEN"; break;
115 case CHIP_RAVEN2
: chip_string
= "AMD RADV RAVEN2"; break;
116 default: chip_string
= "AMD RADV unknown"; break;
119 snprintf(name
, name_len
, "%s (LLVM " MESA_LLVM_VERSION_STRING
")", chip_string
);
123 radv_get_visible_vram_size(struct radv_physical_device
*device
)
125 return MIN2(device
->rad_info
.vram_size
, device
->rad_info
.vram_vis_size
);
129 radv_get_vram_size(struct radv_physical_device
*device
)
131 return device
->rad_info
.vram_size
- radv_get_visible_vram_size(device
);
135 radv_physical_device_init_mem_types(struct radv_physical_device
*device
)
137 STATIC_ASSERT(RADV_MEM_HEAP_COUNT
<= VK_MAX_MEMORY_HEAPS
);
138 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
139 uint64_t vram_size
= radv_get_vram_size(device
);
140 int vram_index
= -1, visible_vram_index
= -1, gart_index
= -1;
141 device
->memory_properties
.memoryHeapCount
= 0;
143 vram_index
= device
->memory_properties
.memoryHeapCount
++;
144 device
->memory_properties
.memoryHeaps
[vram_index
] = (VkMemoryHeap
) {
146 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
149 if (visible_vram_size
) {
150 visible_vram_index
= device
->memory_properties
.memoryHeapCount
++;
151 device
->memory_properties
.memoryHeaps
[visible_vram_index
] = (VkMemoryHeap
) {
152 .size
= visible_vram_size
,
153 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
156 if (device
->rad_info
.gart_size
> 0) {
157 gart_index
= device
->memory_properties
.memoryHeapCount
++;
158 device
->memory_properties
.memoryHeaps
[gart_index
] = (VkMemoryHeap
) {
159 .size
= device
->rad_info
.gart_size
,
160 .flags
= device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
164 STATIC_ASSERT(RADV_MEM_TYPE_COUNT
<= VK_MAX_MEMORY_TYPES
);
165 unsigned type_count
= 0;
166 if (vram_index
>= 0) {
167 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM
;
168 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
169 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
,
170 .heapIndex
= vram_index
,
173 if (gart_index
>= 0) {
174 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_WRITE_COMBINE
;
175 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
176 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
177 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
178 (device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
),
179 .heapIndex
= gart_index
,
182 if (visible_vram_index
>= 0) {
183 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM_CPU_ACCESS
;
184 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
185 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
186 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
187 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
188 .heapIndex
= visible_vram_index
,
191 if (gart_index
>= 0) {
192 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_CACHED
;
193 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
194 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
195 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
196 VK_MEMORY_PROPERTY_HOST_CACHED_BIT
|
197 (device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
),
198 .heapIndex
= gart_index
,
201 device
->memory_properties
.memoryTypeCount
= type_count
;
205 radv_handle_env_var_force_family(struct radv_physical_device
*device
)
207 const char *family
= getenv("RADV_FORCE_FAMILY");
213 for (i
= CHIP_TAHITI
; i
< CHIP_LAST
; i
++) {
214 if (!strcmp(family
, ac_get_llvm_processor_name(i
))) {
215 /* Override family and chip_class. */
216 device
->rad_info
.family
= i
;
218 if (i
>= CHIP_VEGA10
)
219 device
->rad_info
.chip_class
= GFX9
;
220 else if (i
>= CHIP_TONGA
)
221 device
->rad_info
.chip_class
= GFX8
;
222 else if (i
>= CHIP_BONAIRE
)
223 device
->rad_info
.chip_class
= GFX7
;
225 device
->rad_info
.chip_class
= GFX6
;
231 fprintf(stderr
, "radv: Unknown family: %s\n", family
);
236 radv_physical_device_init(struct radv_physical_device
*device
,
237 struct radv_instance
*instance
,
238 drmDevicePtr drm_device
)
240 const char *path
= drm_device
->nodes
[DRM_NODE_RENDER
];
242 drmVersionPtr version
;
246 fd
= open(path
, O_RDWR
| O_CLOEXEC
);
248 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
249 radv_logi("Could not open device '%s'", path
);
251 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
254 version
= drmGetVersion(fd
);
258 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
259 radv_logi("Could not get the kernel driver version for device '%s'", path
);
261 return vk_errorf(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
,
262 "failed to get version %s: %m", path
);
265 if (strcmp(version
->name
, "amdgpu")) {
266 drmFreeVersion(version
);
269 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
270 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path
);
272 return VK_ERROR_INCOMPATIBLE_DRIVER
;
274 drmFreeVersion(version
);
276 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
277 radv_logi("Found compatible device '%s'.", path
);
279 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
280 device
->instance
= instance
;
282 device
->ws
= radv_amdgpu_winsys_create(fd
, instance
->debug_flags
,
283 instance
->perftest_flags
);
285 result
= vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
289 if (instance
->enabled_extensions
.KHR_display
) {
290 master_fd
= open(drm_device
->nodes
[DRM_NODE_PRIMARY
], O_RDWR
| O_CLOEXEC
);
291 if (master_fd
>= 0) {
292 uint32_t accel_working
= 0;
293 struct drm_amdgpu_info request
= {
294 .return_pointer
= (uintptr_t)&accel_working
,
295 .return_size
= sizeof(accel_working
),
296 .query
= AMDGPU_INFO_ACCEL_WORKING
299 if (drmCommandWrite(master_fd
, DRM_AMDGPU_INFO
, &request
, sizeof (struct drm_amdgpu_info
)) < 0 || !accel_working
) {
306 device
->master_fd
= master_fd
;
307 device
->local_fd
= fd
;
308 device
->ws
->query_info(device
->ws
, &device
->rad_info
);
310 radv_handle_env_var_force_family(device
);
312 radv_get_device_name(device
->rad_info
.family
, device
->name
, sizeof(device
->name
));
314 if (radv_device_get_cache_uuid(device
->rad_info
.family
, device
->cache_uuid
)) {
315 device
->ws
->destroy(device
->ws
);
316 result
= vk_errorf(instance
, VK_ERROR_INITIALIZATION_FAILED
,
317 "cannot generate UUID");
321 /* These flags affect shader compilation. */
322 uint64_t shader_env_flags
=
323 (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
? 0x1 : 0) |
324 (device
->instance
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
? 0x2 : 0);
326 /* The gpu id is already embedded in the uuid so we just pass "radv"
327 * when creating the cache.
329 char buf
[VK_UUID_SIZE
* 2 + 1];
330 disk_cache_format_hex_id(buf
, device
->cache_uuid
, VK_UUID_SIZE
* 2);
331 device
->disk_cache
= disk_cache_create(device
->name
, buf
, shader_env_flags
);
333 if (device
->rad_info
.chip_class
< GFX8
||
334 device
->rad_info
.chip_class
> GFX9
)
335 fprintf(stderr
, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
337 radv_get_driver_uuid(&device
->driver_uuid
);
338 radv_get_device_uuid(&device
->rad_info
, &device
->device_uuid
);
340 if (device
->rad_info
.family
== CHIP_STONEY
||
341 device
->rad_info
.chip_class
>= GFX9
) {
342 device
->has_rbplus
= true;
343 device
->rbplus_allowed
= device
->rad_info
.family
== CHIP_STONEY
||
344 device
->rad_info
.family
== CHIP_VEGA12
||
345 device
->rad_info
.family
== CHIP_RAVEN
||
346 device
->rad_info
.family
== CHIP_RAVEN2
;
349 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
352 device
->has_clear_state
= device
->rad_info
.chip_class
>= GFX7
;
354 device
->cpdma_prefetch_writes_memory
= device
->rad_info
.chip_class
<= GFX8
;
356 /* Vega10/Raven need a special workaround for a hardware bug. */
357 device
->has_scissor_bug
= device
->rad_info
.family
== CHIP_VEGA10
||
358 device
->rad_info
.family
== CHIP_RAVEN
;
360 /* Out-of-order primitive rasterization. */
361 device
->has_out_of_order_rast
= device
->rad_info
.chip_class
>= GFX8
&&
362 device
->rad_info
.max_se
>= 2;
363 device
->out_of_order_rast_allowed
= device
->has_out_of_order_rast
&&
364 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_OUT_OF_ORDER
);
366 device
->dcc_msaa_allowed
=
367 (device
->instance
->perftest_flags
& RADV_PERFTEST_DCC_MSAA
);
369 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
370 device
->has_load_ctx_reg_pkt
= device
->rad_info
.chip_class
>= GFX9
||
371 (device
->rad_info
.chip_class
>= GFX8
&&
372 device
->rad_info
.me_fw_feature
>= 41);
374 radv_physical_device_init_mem_types(device
);
375 radv_fill_device_extension_table(device
, &device
->supported_extensions
);
377 device
->bus_info
= *drm_device
->businfo
.pci
;
379 if ((device
->instance
->debug_flags
& RADV_DEBUG_INFO
))
380 ac_print_gpu_info(&device
->rad_info
);
382 /* The WSI is structured as a layer on top of the driver, so this has
383 * to be the last part of initialization (at least until we get other
386 result
= radv_init_wsi(device
);
387 if (result
!= VK_SUCCESS
) {
388 device
->ws
->destroy(device
->ws
);
389 vk_error(instance
, result
);
403 radv_physical_device_finish(struct radv_physical_device
*device
)
405 radv_finish_wsi(device
);
406 device
->ws
->destroy(device
->ws
);
407 disk_cache_destroy(device
->disk_cache
);
408 close(device
->local_fd
);
409 if (device
->master_fd
!= -1)
410 close(device
->master_fd
);
414 default_alloc_func(void *pUserData
, size_t size
, size_t align
,
415 VkSystemAllocationScope allocationScope
)
421 default_realloc_func(void *pUserData
, void *pOriginal
, size_t size
,
422 size_t align
, VkSystemAllocationScope allocationScope
)
424 return realloc(pOriginal
, size
);
428 default_free_func(void *pUserData
, void *pMemory
)
433 static const VkAllocationCallbacks default_alloc
= {
435 .pfnAllocation
= default_alloc_func
,
436 .pfnReallocation
= default_realloc_func
,
437 .pfnFree
= default_free_func
,
440 static const struct debug_control radv_debug_options
[] = {
441 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS
},
442 {"nodcc", RADV_DEBUG_NO_DCC
},
443 {"shaders", RADV_DEBUG_DUMP_SHADERS
},
444 {"nocache", RADV_DEBUG_NO_CACHE
},
445 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS
},
446 {"nohiz", RADV_DEBUG_NO_HIZ
},
447 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE
},
448 {"unsafemath", RADV_DEBUG_UNSAFE_MATH
},
449 {"allbos", RADV_DEBUG_ALL_BOS
},
450 {"noibs", RADV_DEBUG_NO_IBS
},
451 {"spirv", RADV_DEBUG_DUMP_SPIRV
},
452 {"vmfaults", RADV_DEBUG_VM_FAULTS
},
453 {"zerovram", RADV_DEBUG_ZERO_VRAM
},
454 {"syncshaders", RADV_DEBUG_SYNC_SHADERS
},
455 {"nosisched", RADV_DEBUG_NO_SISCHED
},
456 {"preoptir", RADV_DEBUG_PREOPTIR
},
457 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS
},
458 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER
},
459 {"info", RADV_DEBUG_INFO
},
460 {"errors", RADV_DEBUG_ERRORS
},
461 {"startup", RADV_DEBUG_STARTUP
},
462 {"checkir", RADV_DEBUG_CHECKIR
},
463 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM
},
464 {"nobinning", RADV_DEBUG_NOBINNING
},
465 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT
},
470 radv_get_debug_option_name(int id
)
472 assert(id
< ARRAY_SIZE(radv_debug_options
) - 1);
473 return radv_debug_options
[id
].string
;
476 static const struct debug_control radv_perftest_options
[] = {
477 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN
},
478 {"sisched", RADV_PERFTEST_SISCHED
},
479 {"localbos", RADV_PERFTEST_LOCAL_BOS
},
480 {"dccmsaa", RADV_PERFTEST_DCC_MSAA
},
481 {"bolist", RADV_PERFTEST_BO_LIST
},
486 radv_get_perftest_option_name(int id
)
488 assert(id
< ARRAY_SIZE(radv_perftest_options
) - 1);
489 return radv_perftest_options
[id
].string
;
493 radv_handle_per_app_options(struct radv_instance
*instance
,
494 const VkApplicationInfo
*info
)
496 const char *name
= info
? info
->pApplicationName
: NULL
;
501 if (!strcmp(name
, "Talos - Linux - 32bit") ||
502 !strcmp(name
, "Talos - Linux - 64bit")) {
503 if (!(instance
->debug_flags
& RADV_DEBUG_NO_SISCHED
)) {
504 /* Force enable LLVM sisched for Talos because it looks
505 * safe and it gives few more FPS.
507 instance
->perftest_flags
|= RADV_PERFTEST_SISCHED
;
509 } else if (!strcmp(name
, "DOOM_VFR")) {
510 /* Work around a Doom VFR game bug */
511 instance
->debug_flags
|= RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
512 } else if (!strcmp(name
, "MonsterHunterWorld.exe")) {
513 /* Workaround for a WaW hazard when LLVM moves/merges
514 * load/store memory operations.
515 * See https://reviews.llvm.org/D61313
517 if (HAVE_LLVM
< 0x900)
518 instance
->debug_flags
|= RADV_DEBUG_NO_LOAD_STORE_OPT
;
522 static int radv_get_instance_extension_index(const char *name
)
524 for (unsigned i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; ++i
) {
525 if (strcmp(name
, radv_instance_extensions
[i
].extensionName
) == 0)
531 static const char radv_dri_options_xml
[] =
533 DRI_CONF_SECTION_QUALITY
534 DRI_CONF_ADAPTIVE_SYNC("true")
538 static void radv_init_dri_options(struct radv_instance
*instance
)
540 driParseOptionInfo(&instance
->available_dri_options
, radv_dri_options_xml
);
541 driParseConfigFiles(&instance
->dri_options
,
542 &instance
->available_dri_options
,
546 VkResult
radv_CreateInstance(
547 const VkInstanceCreateInfo
* pCreateInfo
,
548 const VkAllocationCallbacks
* pAllocator
,
549 VkInstance
* pInstance
)
551 struct radv_instance
*instance
;
554 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO
);
556 uint32_t client_version
;
557 if (pCreateInfo
->pApplicationInfo
&&
558 pCreateInfo
->pApplicationInfo
->apiVersion
!= 0) {
559 client_version
= pCreateInfo
->pApplicationInfo
->apiVersion
;
561 client_version
= VK_API_VERSION_1_0
;
564 instance
= vk_zalloc2(&default_alloc
, pAllocator
, sizeof(*instance
), 8,
565 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
567 return vk_error(NULL
, VK_ERROR_OUT_OF_HOST_MEMORY
);
569 instance
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
572 instance
->alloc
= *pAllocator
;
574 instance
->alloc
= default_alloc
;
576 instance
->apiVersion
= client_version
;
577 instance
->physicalDeviceCount
= -1;
579 instance
->debug_flags
= parse_debug_string(getenv("RADV_DEBUG"),
582 instance
->perftest_flags
= parse_debug_string(getenv("RADV_PERFTEST"),
583 radv_perftest_options
);
586 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
587 radv_logi("Created an instance");
589 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
590 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
591 int index
= radv_get_instance_extension_index(ext_name
);
593 if (index
< 0 || !radv_supported_instance_extensions
.extensions
[index
]) {
594 vk_free2(&default_alloc
, pAllocator
, instance
);
595 return vk_error(instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
598 instance
->enabled_extensions
.extensions
[index
] = true;
601 result
= vk_debug_report_instance_init(&instance
->debug_report_callbacks
);
602 if (result
!= VK_SUCCESS
) {
603 vk_free2(&default_alloc
, pAllocator
, instance
);
604 return vk_error(instance
, result
);
608 glsl_type_singleton_init_or_ref();
610 VG(VALGRIND_CREATE_MEMPOOL(instance
, 0, false));
612 radv_init_dri_options(instance
);
613 radv_handle_per_app_options(instance
, pCreateInfo
->pApplicationInfo
);
615 *pInstance
= radv_instance_to_handle(instance
);
620 void radv_DestroyInstance(
621 VkInstance _instance
,
622 const VkAllocationCallbacks
* pAllocator
)
624 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
629 for (int i
= 0; i
< instance
->physicalDeviceCount
; ++i
) {
630 radv_physical_device_finish(instance
->physicalDevices
+ i
);
633 VG(VALGRIND_DESTROY_MEMPOOL(instance
));
635 glsl_type_singleton_decref();
638 driDestroyOptionCache(&instance
->dri_options
);
639 driDestroyOptionInfo(&instance
->available_dri_options
);
641 vk_debug_report_instance_destroy(&instance
->debug_report_callbacks
);
643 vk_free(&instance
->alloc
, instance
);
647 radv_enumerate_devices(struct radv_instance
*instance
)
649 /* TODO: Check for more devices ? */
650 drmDevicePtr devices
[8];
651 VkResult result
= VK_ERROR_INCOMPATIBLE_DRIVER
;
654 instance
->physicalDeviceCount
= 0;
656 max_devices
= drmGetDevices2(0, devices
, ARRAY_SIZE(devices
));
658 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
659 radv_logi("Found %d drm nodes", max_devices
);
662 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
664 for (unsigned i
= 0; i
< (unsigned)max_devices
; i
++) {
665 if (devices
[i
]->available_nodes
& 1 << DRM_NODE_RENDER
&&
666 devices
[i
]->bustype
== DRM_BUS_PCI
&&
667 devices
[i
]->deviceinfo
.pci
->vendor_id
== ATI_VENDOR_ID
) {
669 result
= radv_physical_device_init(instance
->physicalDevices
+
670 instance
->physicalDeviceCount
,
673 if (result
== VK_SUCCESS
)
674 ++instance
->physicalDeviceCount
;
675 else if (result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
679 drmFreeDevices(devices
, max_devices
);
684 VkResult
radv_EnumeratePhysicalDevices(
685 VkInstance _instance
,
686 uint32_t* pPhysicalDeviceCount
,
687 VkPhysicalDevice
* pPhysicalDevices
)
689 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
692 if (instance
->physicalDeviceCount
< 0) {
693 result
= radv_enumerate_devices(instance
);
694 if (result
!= VK_SUCCESS
&&
695 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
699 if (!pPhysicalDevices
) {
700 *pPhysicalDeviceCount
= instance
->physicalDeviceCount
;
702 *pPhysicalDeviceCount
= MIN2(*pPhysicalDeviceCount
, instance
->physicalDeviceCount
);
703 for (unsigned i
= 0; i
< *pPhysicalDeviceCount
; ++i
)
704 pPhysicalDevices
[i
] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
707 return *pPhysicalDeviceCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
711 VkResult
radv_EnumeratePhysicalDeviceGroups(
712 VkInstance _instance
,
713 uint32_t* pPhysicalDeviceGroupCount
,
714 VkPhysicalDeviceGroupProperties
* pPhysicalDeviceGroupProperties
)
716 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
719 if (instance
->physicalDeviceCount
< 0) {
720 result
= radv_enumerate_devices(instance
);
721 if (result
!= VK_SUCCESS
&&
722 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
726 if (!pPhysicalDeviceGroupProperties
) {
727 *pPhysicalDeviceGroupCount
= instance
->physicalDeviceCount
;
729 *pPhysicalDeviceGroupCount
= MIN2(*pPhysicalDeviceGroupCount
, instance
->physicalDeviceCount
);
730 for (unsigned i
= 0; i
< *pPhysicalDeviceGroupCount
; ++i
) {
731 pPhysicalDeviceGroupProperties
[i
].physicalDeviceCount
= 1;
732 pPhysicalDeviceGroupProperties
[i
].physicalDevices
[0] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
733 pPhysicalDeviceGroupProperties
[i
].subsetAllocation
= false;
736 return *pPhysicalDeviceGroupCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
740 void radv_GetPhysicalDeviceFeatures(
741 VkPhysicalDevice physicalDevice
,
742 VkPhysicalDeviceFeatures
* pFeatures
)
744 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
745 memset(pFeatures
, 0, sizeof(*pFeatures
));
747 *pFeatures
= (VkPhysicalDeviceFeatures
) {
748 .robustBufferAccess
= true,
749 .fullDrawIndexUint32
= true,
750 .imageCubeArray
= true,
751 .independentBlend
= true,
752 .geometryShader
= true,
753 .tessellationShader
= true,
754 .sampleRateShading
= true,
755 .dualSrcBlend
= true,
757 .multiDrawIndirect
= true,
758 .drawIndirectFirstInstance
= true,
760 .depthBiasClamp
= true,
761 .fillModeNonSolid
= true,
766 .multiViewport
= true,
767 .samplerAnisotropy
= true,
768 .textureCompressionETC2
= radv_device_supports_etc(pdevice
),
769 .textureCompressionASTC_LDR
= false,
770 .textureCompressionBC
= true,
771 .occlusionQueryPrecise
= true,
772 .pipelineStatisticsQuery
= true,
773 .vertexPipelineStoresAndAtomics
= true,
774 .fragmentStoresAndAtomics
= true,
775 .shaderTessellationAndGeometryPointSize
= true,
776 .shaderImageGatherExtended
= true,
777 .shaderStorageImageExtendedFormats
= true,
778 .shaderStorageImageMultisample
= pdevice
->rad_info
.chip_class
>= GFX8
,
779 .shaderUniformBufferArrayDynamicIndexing
= true,
780 .shaderSampledImageArrayDynamicIndexing
= true,
781 .shaderStorageBufferArrayDynamicIndexing
= true,
782 .shaderStorageImageArrayDynamicIndexing
= true,
783 .shaderStorageImageReadWithoutFormat
= true,
784 .shaderStorageImageWriteWithoutFormat
= true,
785 .shaderClipDistance
= true,
786 .shaderCullDistance
= true,
787 .shaderFloat64
= true,
789 .shaderInt16
= pdevice
->rad_info
.chip_class
>= GFX9
,
790 .sparseBinding
= true,
791 .variableMultisampleRate
= true,
792 .inheritedQueries
= true,
796 void radv_GetPhysicalDeviceFeatures2(
797 VkPhysicalDevice physicalDevice
,
798 VkPhysicalDeviceFeatures2
*pFeatures
)
800 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
801 vk_foreach_struct(ext
, pFeatures
->pNext
) {
802 switch (ext
->sType
) {
803 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES
: {
804 VkPhysicalDeviceVariablePointersFeatures
*features
= (void *)ext
;
805 features
->variablePointersStorageBuffer
= true;
806 features
->variablePointers
= true;
809 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES
: {
810 VkPhysicalDeviceMultiviewFeatures
*features
= (VkPhysicalDeviceMultiviewFeatures
*)ext
;
811 features
->multiview
= true;
812 features
->multiviewGeometryShader
= true;
813 features
->multiviewTessellationShader
= true;
816 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES
: {
817 VkPhysicalDeviceShaderDrawParametersFeatures
*features
=
818 (VkPhysicalDeviceShaderDrawParametersFeatures
*)ext
;
819 features
->shaderDrawParameters
= true;
822 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES
: {
823 VkPhysicalDeviceProtectedMemoryFeatures
*features
=
824 (VkPhysicalDeviceProtectedMemoryFeatures
*)ext
;
825 features
->protectedMemory
= false;
828 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES
: {
829 VkPhysicalDevice16BitStorageFeatures
*features
=
830 (VkPhysicalDevice16BitStorageFeatures
*)ext
;
831 bool enabled
= pdevice
->rad_info
.chip_class
>= GFX8
;
832 features
->storageBuffer16BitAccess
= enabled
;
833 features
->uniformAndStorageBuffer16BitAccess
= enabled
;
834 features
->storagePushConstant16
= enabled
;
835 features
->storageInputOutput16
= enabled
&& HAVE_LLVM
>= 0x900;
838 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES
: {
839 VkPhysicalDeviceSamplerYcbcrConversionFeatures
*features
=
840 (VkPhysicalDeviceSamplerYcbcrConversionFeatures
*)ext
;
841 features
->samplerYcbcrConversion
= true;
844 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT
: {
845 VkPhysicalDeviceDescriptorIndexingFeaturesEXT
*features
=
846 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT
*)ext
;
847 features
->shaderInputAttachmentArrayDynamicIndexing
= true;
848 features
->shaderUniformTexelBufferArrayDynamicIndexing
= true;
849 features
->shaderStorageTexelBufferArrayDynamicIndexing
= true;
850 features
->shaderUniformBufferArrayNonUniformIndexing
= true;
851 features
->shaderSampledImageArrayNonUniformIndexing
= true;
852 features
->shaderStorageBufferArrayNonUniformIndexing
= true;
853 features
->shaderStorageImageArrayNonUniformIndexing
= true;
854 features
->shaderInputAttachmentArrayNonUniformIndexing
= true;
855 features
->shaderUniformTexelBufferArrayNonUniformIndexing
= true;
856 features
->shaderStorageTexelBufferArrayNonUniformIndexing
= true;
857 features
->descriptorBindingUniformBufferUpdateAfterBind
= true;
858 features
->descriptorBindingSampledImageUpdateAfterBind
= true;
859 features
->descriptorBindingStorageImageUpdateAfterBind
= true;
860 features
->descriptorBindingStorageBufferUpdateAfterBind
= true;
861 features
->descriptorBindingUniformTexelBufferUpdateAfterBind
= true;
862 features
->descriptorBindingStorageTexelBufferUpdateAfterBind
= true;
863 features
->descriptorBindingUpdateUnusedWhilePending
= true;
864 features
->descriptorBindingPartiallyBound
= true;
865 features
->descriptorBindingVariableDescriptorCount
= true;
866 features
->runtimeDescriptorArray
= true;
869 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT
: {
870 VkPhysicalDeviceConditionalRenderingFeaturesEXT
*features
=
871 (VkPhysicalDeviceConditionalRenderingFeaturesEXT
*)ext
;
872 features
->conditionalRendering
= true;
873 features
->inheritedConditionalRendering
= false;
876 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT
: {
877 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*features
=
878 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*)ext
;
879 features
->vertexAttributeInstanceRateDivisor
= VK_TRUE
;
880 features
->vertexAttributeInstanceRateZeroDivisor
= VK_TRUE
;
883 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT
: {
884 VkPhysicalDeviceTransformFeedbackFeaturesEXT
*features
=
885 (VkPhysicalDeviceTransformFeedbackFeaturesEXT
*)ext
;
886 features
->transformFeedback
= true;
887 features
->geometryStreams
= true;
890 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT
: {
891 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT
*features
=
892 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT
*)ext
;
893 features
->scalarBlockLayout
= pdevice
->rad_info
.chip_class
>= GFX7
;
896 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT
: {
897 VkPhysicalDeviceMemoryPriorityFeaturesEXT
*features
=
898 (VkPhysicalDeviceMemoryPriorityFeaturesEXT
*)ext
;
899 features
->memoryPriority
= VK_TRUE
;
902 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT
: {
903 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*features
=
904 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*)ext
;
905 features
->bufferDeviceAddress
= true;
906 features
->bufferDeviceAddressCaptureReplay
= false;
907 features
->bufferDeviceAddressMultiDevice
= false;
910 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT
: {
911 VkPhysicalDeviceDepthClipEnableFeaturesEXT
*features
=
912 (VkPhysicalDeviceDepthClipEnableFeaturesEXT
*)ext
;
913 features
->depthClipEnable
= true;
916 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT
: {
917 VkPhysicalDeviceHostQueryResetFeaturesEXT
*features
=
918 (VkPhysicalDeviceHostQueryResetFeaturesEXT
*)ext
;
919 features
->hostQueryReset
= true;
922 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR
: {
923 VkPhysicalDevice8BitStorageFeaturesKHR
*features
=
924 (VkPhysicalDevice8BitStorageFeaturesKHR
*)ext
;
925 bool enabled
= pdevice
->rad_info
.chip_class
>= GFX8
;
926 features
->storageBuffer8BitAccess
= enabled
;
927 features
->uniformAndStorageBuffer8BitAccess
= enabled
;
928 features
->storagePushConstant8
= enabled
;
931 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR
: {
932 VkPhysicalDeviceFloat16Int8FeaturesKHR
*features
=
933 (VkPhysicalDeviceFloat16Int8FeaturesKHR
*)ext
;
934 features
->shaderFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
&& HAVE_LLVM
>= 0x0800;
935 features
->shaderInt8
= true;
938 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR
: {
939 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR
*features
=
940 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR
*)ext
;
941 /* TODO: Enable this once the driver supports 64-bit
942 * compare&swap atomic operations.
944 features
->shaderBufferInt64Atomics
= false;
945 features
->shaderSharedInt64Atomics
= false;
948 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT
: {
949 VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*features
=
950 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*)ext
;
952 features
->inlineUniformBlock
= true;
953 features
->descriptorBindingInlineUniformBlockUpdateAfterBind
= true;
956 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV
: {
957 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*features
=
958 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*)ext
;
959 features
->computeDerivativeGroupQuads
= false;
960 features
->computeDerivativeGroupLinear
= true;
963 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT
: {
964 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*features
=
965 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*)ext
;
966 features
->ycbcrImageArrays
= true;
969 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR
: {
970 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR
*features
=
971 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR
*)ext
;
972 features
->uniformBufferStandardLayout
= true;
979 return radv_GetPhysicalDeviceFeatures(physicalDevice
, &pFeatures
->features
);
982 void radv_GetPhysicalDeviceProperties(
983 VkPhysicalDevice physicalDevice
,
984 VkPhysicalDeviceProperties
* pProperties
)
986 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
987 VkSampleCountFlags sample_counts
= 0xf;
989 /* make sure that the entire descriptor set is addressable with a signed
990 * 32-bit int. So the sum of all limits scaled by descriptor size has to
991 * be at most 2 GiB. the combined image & samples object count as one of
992 * both. This limit is for the pipeline layout, not for the set layout, but
993 * there is no set limit, so we just set a pipeline limit. I don't think
994 * any app is going to hit this soon. */
995 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
) /
996 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
997 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
998 32 /* sampler, largest when combined with image */ +
999 64 /* sampled image */ +
1000 64 /* storage image */);
1002 VkPhysicalDeviceLimits limits
= {
1003 .maxImageDimension1D
= (1 << 14),
1004 .maxImageDimension2D
= (1 << 14),
1005 .maxImageDimension3D
= (1 << 11),
1006 .maxImageDimensionCube
= (1 << 14),
1007 .maxImageArrayLayers
= (1 << 11),
1008 .maxTexelBufferElements
= 128 * 1024 * 1024,
1009 .maxUniformBufferRange
= UINT32_MAX
,
1010 .maxStorageBufferRange
= UINT32_MAX
,
1011 .maxPushConstantsSize
= MAX_PUSH_CONSTANTS_SIZE
,
1012 .maxMemoryAllocationCount
= UINT32_MAX
,
1013 .maxSamplerAllocationCount
= 64 * 1024,
1014 .bufferImageGranularity
= 64, /* A cache line */
1015 .sparseAddressSpaceSize
= 0xffffffffu
, /* buffer max size */
1016 .maxBoundDescriptorSets
= MAX_SETS
,
1017 .maxPerStageDescriptorSamplers
= max_descriptor_set_size
,
1018 .maxPerStageDescriptorUniformBuffers
= max_descriptor_set_size
,
1019 .maxPerStageDescriptorStorageBuffers
= max_descriptor_set_size
,
1020 .maxPerStageDescriptorSampledImages
= max_descriptor_set_size
,
1021 .maxPerStageDescriptorStorageImages
= max_descriptor_set_size
,
1022 .maxPerStageDescriptorInputAttachments
= max_descriptor_set_size
,
1023 .maxPerStageResources
= max_descriptor_set_size
,
1024 .maxDescriptorSetSamplers
= max_descriptor_set_size
,
1025 .maxDescriptorSetUniformBuffers
= max_descriptor_set_size
,
1026 .maxDescriptorSetUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
,
1027 .maxDescriptorSetStorageBuffers
= max_descriptor_set_size
,
1028 .maxDescriptorSetStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
,
1029 .maxDescriptorSetSampledImages
= max_descriptor_set_size
,
1030 .maxDescriptorSetStorageImages
= max_descriptor_set_size
,
1031 .maxDescriptorSetInputAttachments
= max_descriptor_set_size
,
1032 .maxVertexInputAttributes
= MAX_VERTEX_ATTRIBS
,
1033 .maxVertexInputBindings
= MAX_VBS
,
1034 .maxVertexInputAttributeOffset
= 2047,
1035 .maxVertexInputBindingStride
= 2048,
1036 .maxVertexOutputComponents
= 128,
1037 .maxTessellationGenerationLevel
= 64,
1038 .maxTessellationPatchSize
= 32,
1039 .maxTessellationControlPerVertexInputComponents
= 128,
1040 .maxTessellationControlPerVertexOutputComponents
= 128,
1041 .maxTessellationControlPerPatchOutputComponents
= 120,
1042 .maxTessellationControlTotalOutputComponents
= 4096,
1043 .maxTessellationEvaluationInputComponents
= 128,
1044 .maxTessellationEvaluationOutputComponents
= 128,
1045 .maxGeometryShaderInvocations
= 127,
1046 .maxGeometryInputComponents
= 64,
1047 .maxGeometryOutputComponents
= 128,
1048 .maxGeometryOutputVertices
= 256,
1049 .maxGeometryTotalOutputComponents
= 1024,
1050 .maxFragmentInputComponents
= 128,
1051 .maxFragmentOutputAttachments
= 8,
1052 .maxFragmentDualSrcAttachments
= 1,
1053 .maxFragmentCombinedOutputResources
= 8,
1054 .maxComputeSharedMemorySize
= 32768,
1055 .maxComputeWorkGroupCount
= { 65535, 65535, 65535 },
1056 .maxComputeWorkGroupInvocations
= 2048,
1057 .maxComputeWorkGroupSize
= {
1062 .subPixelPrecisionBits
= 8,
1063 .subTexelPrecisionBits
= 8,
1064 .mipmapPrecisionBits
= 8,
1065 .maxDrawIndexedIndexValue
= UINT32_MAX
,
1066 .maxDrawIndirectCount
= UINT32_MAX
,
1067 .maxSamplerLodBias
= 16,
1068 .maxSamplerAnisotropy
= 16,
1069 .maxViewports
= MAX_VIEWPORTS
,
1070 .maxViewportDimensions
= { (1 << 14), (1 << 14) },
1071 .viewportBoundsRange
= { INT16_MIN
, INT16_MAX
},
1072 .viewportSubPixelBits
= 8,
1073 .minMemoryMapAlignment
= 4096, /* A page */
1074 .minTexelBufferOffsetAlignment
= 1,
1075 .minUniformBufferOffsetAlignment
= 4,
1076 .minStorageBufferOffsetAlignment
= 4,
1077 .minTexelOffset
= -32,
1078 .maxTexelOffset
= 31,
1079 .minTexelGatherOffset
= -32,
1080 .maxTexelGatherOffset
= 31,
1081 .minInterpolationOffset
= -2,
1082 .maxInterpolationOffset
= 2,
1083 .subPixelInterpolationOffsetBits
= 8,
1084 .maxFramebufferWidth
= (1 << 14),
1085 .maxFramebufferHeight
= (1 << 14),
1086 .maxFramebufferLayers
= (1 << 10),
1087 .framebufferColorSampleCounts
= sample_counts
,
1088 .framebufferDepthSampleCounts
= sample_counts
,
1089 .framebufferStencilSampleCounts
= sample_counts
,
1090 .framebufferNoAttachmentsSampleCounts
= sample_counts
,
1091 .maxColorAttachments
= MAX_RTS
,
1092 .sampledImageColorSampleCounts
= sample_counts
,
1093 .sampledImageIntegerSampleCounts
= VK_SAMPLE_COUNT_1_BIT
,
1094 .sampledImageDepthSampleCounts
= sample_counts
,
1095 .sampledImageStencilSampleCounts
= sample_counts
,
1096 .storageImageSampleCounts
= pdevice
->rad_info
.chip_class
>= GFX8
? sample_counts
: VK_SAMPLE_COUNT_1_BIT
,
1097 .maxSampleMaskWords
= 1,
1098 .timestampComputeAndGraphics
= true,
1099 .timestampPeriod
= 1000000.0 / pdevice
->rad_info
.clock_crystal_freq
,
1100 .maxClipDistances
= 8,
1101 .maxCullDistances
= 8,
1102 .maxCombinedClipAndCullDistances
= 8,
1103 .discreteQueuePriorities
= 2,
1104 .pointSizeRange
= { 0.0, 8192.0 },
1105 .lineWidthRange
= { 0.0, 7.9921875 },
1106 .pointSizeGranularity
= (1.0 / 8.0),
1107 .lineWidthGranularity
= (1.0 / 128.0),
1108 .strictLines
= false, /* FINISHME */
1109 .standardSampleLocations
= true,
1110 .optimalBufferCopyOffsetAlignment
= 128,
1111 .optimalBufferCopyRowPitchAlignment
= 128,
1112 .nonCoherentAtomSize
= 64,
1115 *pProperties
= (VkPhysicalDeviceProperties
) {
1116 .apiVersion
= radv_physical_device_api_version(pdevice
),
1117 .driverVersion
= vk_get_driver_version(),
1118 .vendorID
= ATI_VENDOR_ID
,
1119 .deviceID
= pdevice
->rad_info
.pci_id
,
1120 .deviceType
= pdevice
->rad_info
.has_dedicated_vram
? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU
: VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU
,
1122 .sparseProperties
= {0},
1125 strcpy(pProperties
->deviceName
, pdevice
->name
);
1126 memcpy(pProperties
->pipelineCacheUUID
, pdevice
->cache_uuid
, VK_UUID_SIZE
);
1129 void radv_GetPhysicalDeviceProperties2(
1130 VkPhysicalDevice physicalDevice
,
1131 VkPhysicalDeviceProperties2
*pProperties
)
1133 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1134 radv_GetPhysicalDeviceProperties(physicalDevice
, &pProperties
->properties
);
1136 vk_foreach_struct(ext
, pProperties
->pNext
) {
1137 switch (ext
->sType
) {
1138 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR
: {
1139 VkPhysicalDevicePushDescriptorPropertiesKHR
*properties
=
1140 (VkPhysicalDevicePushDescriptorPropertiesKHR
*) ext
;
1141 properties
->maxPushDescriptors
= MAX_PUSH_DESCRIPTORS
;
1144 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES
: {
1145 VkPhysicalDeviceIDProperties
*properties
= (VkPhysicalDeviceIDProperties
*)ext
;
1146 memcpy(properties
->driverUUID
, pdevice
->driver_uuid
, VK_UUID_SIZE
);
1147 memcpy(properties
->deviceUUID
, pdevice
->device_uuid
, VK_UUID_SIZE
);
1148 properties
->deviceLUIDValid
= false;
1151 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES
: {
1152 VkPhysicalDeviceMultiviewProperties
*properties
= (VkPhysicalDeviceMultiviewProperties
*)ext
;
1153 properties
->maxMultiviewViewCount
= MAX_VIEWS
;
1154 properties
->maxMultiviewInstanceIndex
= INT_MAX
;
1157 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES
: {
1158 VkPhysicalDevicePointClippingProperties
*properties
=
1159 (VkPhysicalDevicePointClippingProperties
*)ext
;
1160 properties
->pointClippingBehavior
= VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES
;
1163 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT
: {
1164 VkPhysicalDeviceDiscardRectanglePropertiesEXT
*properties
=
1165 (VkPhysicalDeviceDiscardRectanglePropertiesEXT
*)ext
;
1166 properties
->maxDiscardRectangles
= MAX_DISCARD_RECTANGLES
;
1169 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT
: {
1170 VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*properties
=
1171 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*) ext
;
1172 properties
->minImportedHostPointerAlignment
= 4096;
1175 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES
: {
1176 VkPhysicalDeviceSubgroupProperties
*properties
=
1177 (VkPhysicalDeviceSubgroupProperties
*)ext
;
1178 properties
->subgroupSize
= 64;
1179 properties
->supportedStages
= VK_SHADER_STAGE_ALL
;
1180 properties
->supportedOperations
=
1181 VK_SUBGROUP_FEATURE_BASIC_BIT
|
1182 VK_SUBGROUP_FEATURE_BALLOT_BIT
|
1183 VK_SUBGROUP_FEATURE_QUAD_BIT
|
1184 VK_SUBGROUP_FEATURE_VOTE_BIT
;
1185 if (pdevice
->rad_info
.chip_class
>= GFX8
) {
1186 properties
->supportedOperations
|=
1187 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT
|
1188 VK_SUBGROUP_FEATURE_SHUFFLE_BIT
|
1189 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT
;
1191 properties
->quadOperationsInAllStages
= true;
1194 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES
: {
1195 VkPhysicalDeviceMaintenance3Properties
*properties
=
1196 (VkPhysicalDeviceMaintenance3Properties
*)ext
;
1197 /* Make sure everything is addressable by a signed 32-bit int, and
1198 * our largest descriptors are 96 bytes. */
1199 properties
->maxPerSetDescriptors
= (1ull << 31) / 96;
1200 /* Our buffer size fields allow only this much */
1201 properties
->maxMemoryAllocationSize
= 0xFFFFFFFFull
;
1204 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT
: {
1205 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT
*properties
=
1206 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT
*)ext
;
1207 /* GFX6-8 only support single channel min/max filter. */
1208 properties
->filterMinmaxImageComponentMapping
= pdevice
->rad_info
.chip_class
>= GFX9
;
1209 properties
->filterMinmaxSingleComponentFormats
= true;
1212 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD
: {
1213 VkPhysicalDeviceShaderCorePropertiesAMD
*properties
=
1214 (VkPhysicalDeviceShaderCorePropertiesAMD
*)ext
;
1216 /* Shader engines. */
1217 properties
->shaderEngineCount
=
1218 pdevice
->rad_info
.max_se
;
1219 properties
->shaderArraysPerEngineCount
=
1220 pdevice
->rad_info
.max_sh_per_se
;
1221 properties
->computeUnitsPerShaderArray
=
1222 pdevice
->rad_info
.num_good_cu_per_sh
;
1223 properties
->simdPerComputeUnit
= 4;
1224 properties
->wavefrontsPerSimd
=
1225 pdevice
->rad_info
.family
== CHIP_TONGA
||
1226 pdevice
->rad_info
.family
== CHIP_ICELAND
||
1227 pdevice
->rad_info
.family
== CHIP_POLARIS10
||
1228 pdevice
->rad_info
.family
== CHIP_POLARIS11
||
1229 pdevice
->rad_info
.family
== CHIP_POLARIS12
||
1230 pdevice
->rad_info
.family
== CHIP_VEGAM
? 8 : 10;
1231 properties
->wavefrontSize
= 64;
1234 properties
->sgprsPerSimd
=
1235 ac_get_num_physical_sgprs(pdevice
->rad_info
.chip_class
);
1236 properties
->minSgprAllocation
=
1237 pdevice
->rad_info
.chip_class
>= GFX8
? 16 : 8;
1238 properties
->maxSgprAllocation
=
1239 pdevice
->rad_info
.family
== CHIP_TONGA
||
1240 pdevice
->rad_info
.family
== CHIP_ICELAND
? 96 : 104;
1241 properties
->sgprAllocationGranularity
=
1242 pdevice
->rad_info
.chip_class
>= GFX8
? 16 : 8;
1245 properties
->vgprsPerSimd
= RADV_NUM_PHYSICAL_VGPRS
;
1246 properties
->minVgprAllocation
= 4;
1247 properties
->maxVgprAllocation
= 256;
1248 properties
->vgprAllocationGranularity
= 4;
1251 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT
: {
1252 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*properties
=
1253 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*)ext
;
1254 properties
->maxVertexAttribDivisor
= UINT32_MAX
;
1257 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT
: {
1258 VkPhysicalDeviceDescriptorIndexingPropertiesEXT
*properties
=
1259 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT
*)ext
;
1260 properties
->maxUpdateAfterBindDescriptorsInAllPools
= UINT32_MAX
/ 64;
1261 properties
->shaderUniformBufferArrayNonUniformIndexingNative
= false;
1262 properties
->shaderSampledImageArrayNonUniformIndexingNative
= false;
1263 properties
->shaderStorageBufferArrayNonUniformIndexingNative
= false;
1264 properties
->shaderStorageImageArrayNonUniformIndexingNative
= false;
1265 properties
->shaderInputAttachmentArrayNonUniformIndexingNative
= false;
1266 properties
->robustBufferAccessUpdateAfterBind
= false;
1267 properties
->quadDivergentImplicitLod
= false;
1269 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
-
1270 MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_INLINE_UNIFORM_BLOCK_COUNT
) /
1271 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1272 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1273 32 /* sampler, largest when combined with image */ +
1274 64 /* sampled image */ +
1275 64 /* storage image */);
1276 properties
->maxPerStageDescriptorUpdateAfterBindSamplers
= max_descriptor_set_size
;
1277 properties
->maxPerStageDescriptorUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1278 properties
->maxPerStageDescriptorUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1279 properties
->maxPerStageDescriptorUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1280 properties
->maxPerStageDescriptorUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1281 properties
->maxPerStageDescriptorUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1282 properties
->maxPerStageUpdateAfterBindResources
= max_descriptor_set_size
;
1283 properties
->maxDescriptorSetUpdateAfterBindSamplers
= max_descriptor_set_size
;
1284 properties
->maxDescriptorSetUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1285 properties
->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
;
1286 properties
->maxDescriptorSetUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1287 properties
->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
;
1288 properties
->maxDescriptorSetUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1289 properties
->maxDescriptorSetUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1290 properties
->maxDescriptorSetUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1293 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES
: {
1294 VkPhysicalDeviceProtectedMemoryProperties
*properties
=
1295 (VkPhysicalDeviceProtectedMemoryProperties
*)ext
;
1296 properties
->protectedNoFault
= false;
1299 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT
: {
1300 VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*properties
=
1301 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*)ext
;
1302 properties
->primitiveOverestimationSize
= 0;
1303 properties
->maxExtraPrimitiveOverestimationSize
= 0;
1304 properties
->extraPrimitiveOverestimationSizeGranularity
= 0;
1305 properties
->primitiveUnderestimation
= VK_FALSE
;
1306 properties
->conservativePointAndLineRasterization
= VK_FALSE
;
1307 properties
->degenerateTrianglesRasterized
= VK_FALSE
;
1308 properties
->degenerateLinesRasterized
= VK_FALSE
;
1309 properties
->fullyCoveredFragmentShaderInputVariable
= VK_FALSE
;
1310 properties
->conservativeRasterizationPostDepthCoverage
= VK_FALSE
;
1313 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT
: {
1314 VkPhysicalDevicePCIBusInfoPropertiesEXT
*properties
=
1315 (VkPhysicalDevicePCIBusInfoPropertiesEXT
*)ext
;
1316 properties
->pciDomain
= pdevice
->bus_info
.domain
;
1317 properties
->pciBus
= pdevice
->bus_info
.bus
;
1318 properties
->pciDevice
= pdevice
->bus_info
.dev
;
1319 properties
->pciFunction
= pdevice
->bus_info
.func
;
1322 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR
: {
1323 VkPhysicalDeviceDriverPropertiesKHR
*driver_props
=
1324 (VkPhysicalDeviceDriverPropertiesKHR
*) ext
;
1326 driver_props
->driverID
= VK_DRIVER_ID_MESA_RADV_KHR
;
1327 memset(driver_props
->driverName
, 0, VK_MAX_DRIVER_NAME_SIZE_KHR
);
1328 strcpy(driver_props
->driverName
, "radv");
1330 memset(driver_props
->driverInfo
, 0, VK_MAX_DRIVER_INFO_SIZE_KHR
);
1331 snprintf(driver_props
->driverInfo
, VK_MAX_DRIVER_INFO_SIZE_KHR
,
1332 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1333 " (LLVM " MESA_LLVM_VERSION_STRING
")");
1335 driver_props
->conformanceVersion
= (VkConformanceVersionKHR
) {
1343 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT
: {
1344 VkPhysicalDeviceTransformFeedbackPropertiesEXT
*properties
=
1345 (VkPhysicalDeviceTransformFeedbackPropertiesEXT
*)ext
;
1346 properties
->maxTransformFeedbackStreams
= MAX_SO_STREAMS
;
1347 properties
->maxTransformFeedbackBuffers
= MAX_SO_BUFFERS
;
1348 properties
->maxTransformFeedbackBufferSize
= UINT32_MAX
;
1349 properties
->maxTransformFeedbackStreamDataSize
= 512;
1350 properties
->maxTransformFeedbackBufferDataSize
= UINT32_MAX
;
1351 properties
->maxTransformFeedbackBufferDataStride
= 512;
1352 properties
->transformFeedbackQueries
= true;
1353 properties
->transformFeedbackStreamsLinesTriangles
= true;
1354 properties
->transformFeedbackRasterizationStreamSelect
= false;
1355 properties
->transformFeedbackDraw
= true;
1358 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT
: {
1359 VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*props
=
1360 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*)ext
;
1362 props
->maxInlineUniformBlockSize
= MAX_INLINE_UNIFORM_BLOCK_SIZE
;
1363 props
->maxPerStageDescriptorInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1364 props
->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1365 props
->maxDescriptorSetInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1366 props
->maxDescriptorSetUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1369 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT
: {
1370 VkPhysicalDeviceSampleLocationsPropertiesEXT
*properties
=
1371 (VkPhysicalDeviceSampleLocationsPropertiesEXT
*)ext
;
1372 properties
->sampleLocationSampleCounts
= VK_SAMPLE_COUNT_2_BIT
|
1373 VK_SAMPLE_COUNT_4_BIT
|
1374 VK_SAMPLE_COUNT_8_BIT
;
1375 properties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2 , 2 };
1376 properties
->sampleLocationCoordinateRange
[0] = 0.0f
;
1377 properties
->sampleLocationCoordinateRange
[1] = 0.9375f
;
1378 properties
->sampleLocationSubPixelBits
= 4;
1379 properties
->variableSampleLocations
= VK_FALSE
;
1388 static void radv_get_physical_device_queue_family_properties(
1389 struct radv_physical_device
* pdevice
,
1391 VkQueueFamilyProperties
** pQueueFamilyProperties
)
1393 int num_queue_families
= 1;
1395 if (pdevice
->rad_info
.num_compute_rings
> 0 &&
1396 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
))
1397 num_queue_families
++;
1399 if (pQueueFamilyProperties
== NULL
) {
1400 *pCount
= num_queue_families
;
1409 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
1410 .queueFlags
= VK_QUEUE_GRAPHICS_BIT
|
1411 VK_QUEUE_COMPUTE_BIT
|
1412 VK_QUEUE_TRANSFER_BIT
|
1413 VK_QUEUE_SPARSE_BINDING_BIT
,
1415 .timestampValidBits
= 64,
1416 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
1421 if (pdevice
->rad_info
.num_compute_rings
> 0 &&
1422 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
)) {
1423 if (*pCount
> idx
) {
1424 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
1425 .queueFlags
= VK_QUEUE_COMPUTE_BIT
|
1426 VK_QUEUE_TRANSFER_BIT
|
1427 VK_QUEUE_SPARSE_BINDING_BIT
,
1428 .queueCount
= pdevice
->rad_info
.num_compute_rings
,
1429 .timestampValidBits
= 64,
1430 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
1438 void radv_GetPhysicalDeviceQueueFamilyProperties(
1439 VkPhysicalDevice physicalDevice
,
1441 VkQueueFamilyProperties
* pQueueFamilyProperties
)
1443 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1444 if (!pQueueFamilyProperties
) {
1445 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
1448 VkQueueFamilyProperties
*properties
[] = {
1449 pQueueFamilyProperties
+ 0,
1450 pQueueFamilyProperties
+ 1,
1451 pQueueFamilyProperties
+ 2,
1453 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
1454 assert(*pCount
<= 3);
1457 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1458 VkPhysicalDevice physicalDevice
,
1460 VkQueueFamilyProperties2
*pQueueFamilyProperties
)
1462 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1463 if (!pQueueFamilyProperties
) {
1464 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
1467 VkQueueFamilyProperties
*properties
[] = {
1468 &pQueueFamilyProperties
[0].queueFamilyProperties
,
1469 &pQueueFamilyProperties
[1].queueFamilyProperties
,
1470 &pQueueFamilyProperties
[2].queueFamilyProperties
,
1472 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
1473 assert(*pCount
<= 3);
1476 void radv_GetPhysicalDeviceMemoryProperties(
1477 VkPhysicalDevice physicalDevice
,
1478 VkPhysicalDeviceMemoryProperties
*pMemoryProperties
)
1480 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
1482 *pMemoryProperties
= physical_device
->memory_properties
;
1486 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice
,
1487 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memoryBudget
)
1489 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
1490 VkPhysicalDeviceMemoryProperties
*memory_properties
= &device
->memory_properties
;
1491 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
1492 uint64_t vram_size
= radv_get_vram_size(device
);
1493 uint64_t gtt_size
= device
->rad_info
.gart_size
;
1494 uint64_t heap_budget
, heap_usage
;
1496 /* For all memory heaps, the computation of budget is as follow:
1497 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1499 * The Vulkan spec 1.1.97 says that the budget should include any
1500 * currently allocated device memory.
1502 * Note that the application heap usages are not really accurate (eg.
1503 * in presence of shared buffers).
1506 heap_usage
= device
->ws
->query_value(device
->ws
,
1507 RADEON_ALLOCATED_VRAM
);
1509 heap_budget
= vram_size
-
1510 device
->ws
->query_value(device
->ws
, RADEON_VRAM_USAGE
) +
1513 memoryBudget
->heapBudget
[RADV_MEM_HEAP_VRAM
] = heap_budget
;
1514 memoryBudget
->heapUsage
[RADV_MEM_HEAP_VRAM
] = heap_usage
;
1517 if (visible_vram_size
) {
1518 heap_usage
= device
->ws
->query_value(device
->ws
,
1519 RADEON_ALLOCATED_VRAM_VIS
);
1521 heap_budget
= visible_vram_size
-
1522 device
->ws
->query_value(device
->ws
, RADEON_VRAM_VIS_USAGE
) +
1525 memoryBudget
->heapBudget
[RADV_MEM_HEAP_VRAM_CPU_ACCESS
] = heap_budget
;
1526 memoryBudget
->heapUsage
[RADV_MEM_HEAP_VRAM_CPU_ACCESS
] = heap_usage
;
1530 heap_usage
= device
->ws
->query_value(device
->ws
,
1531 RADEON_ALLOCATED_GTT
);
1533 heap_budget
= gtt_size
-
1534 device
->ws
->query_value(device
->ws
, RADEON_GTT_USAGE
) +
1537 memoryBudget
->heapBudget
[RADV_MEM_HEAP_GTT
] = heap_budget
;
1538 memoryBudget
->heapUsage
[RADV_MEM_HEAP_GTT
] = heap_usage
;
1541 /* The heapBudget and heapUsage values must be zero for array elements
1542 * greater than or equal to
1543 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1545 for (uint32_t i
= memory_properties
->memoryHeapCount
; i
< VK_MAX_MEMORY_HEAPS
; i
++) {
1546 memoryBudget
->heapBudget
[i
] = 0;
1547 memoryBudget
->heapUsage
[i
] = 0;
1551 void radv_GetPhysicalDeviceMemoryProperties2(
1552 VkPhysicalDevice physicalDevice
,
1553 VkPhysicalDeviceMemoryProperties2
*pMemoryProperties
)
1555 radv_GetPhysicalDeviceMemoryProperties(physicalDevice
,
1556 &pMemoryProperties
->memoryProperties
);
1558 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memory_budget
=
1559 vk_find_struct(pMemoryProperties
->pNext
,
1560 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT
);
1562 radv_get_memory_budget_properties(physicalDevice
, memory_budget
);
1565 VkResult
radv_GetMemoryHostPointerPropertiesEXT(
1567 VkExternalMemoryHandleTypeFlagBits handleType
,
1568 const void *pHostPointer
,
1569 VkMemoryHostPointerPropertiesEXT
*pMemoryHostPointerProperties
)
1571 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1575 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
: {
1576 const struct radv_physical_device
*physical_device
= device
->physical_device
;
1577 uint32_t memoryTypeBits
= 0;
1578 for (int i
= 0; i
< physical_device
->memory_properties
.memoryTypeCount
; i
++) {
1579 if (physical_device
->mem_type_indices
[i
] == RADV_MEM_TYPE_GTT_CACHED
) {
1580 memoryTypeBits
= (1 << i
);
1584 pMemoryHostPointerProperties
->memoryTypeBits
= memoryTypeBits
;
1588 return VK_ERROR_INVALID_EXTERNAL_HANDLE
;
1592 static enum radeon_ctx_priority
1593 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT
*pObj
)
1595 /* Default to MEDIUM when a specific global priority isn't requested */
1597 return RADEON_CTX_PRIORITY_MEDIUM
;
1599 switch(pObj
->globalPriority
) {
1600 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT
:
1601 return RADEON_CTX_PRIORITY_REALTIME
;
1602 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT
:
1603 return RADEON_CTX_PRIORITY_HIGH
;
1604 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT
:
1605 return RADEON_CTX_PRIORITY_MEDIUM
;
1606 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT
:
1607 return RADEON_CTX_PRIORITY_LOW
;
1609 unreachable("Illegal global priority value");
1610 return RADEON_CTX_PRIORITY_INVALID
;
1615 radv_queue_init(struct radv_device
*device
, struct radv_queue
*queue
,
1616 uint32_t queue_family_index
, int idx
,
1617 VkDeviceQueueCreateFlags flags
,
1618 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
)
1620 queue
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1621 queue
->device
= device
;
1622 queue
->queue_family_index
= queue_family_index
;
1623 queue
->queue_idx
= idx
;
1624 queue
->priority
= radv_get_queue_global_priority(global_priority
);
1625 queue
->flags
= flags
;
1627 queue
->hw_ctx
= device
->ws
->ctx_create(device
->ws
, queue
->priority
);
1629 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1635 radv_queue_finish(struct radv_queue
*queue
)
1638 queue
->device
->ws
->ctx_destroy(queue
->hw_ctx
);
1640 if (queue
->initial_full_flush_preamble_cs
)
1641 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
1642 if (queue
->initial_preamble_cs
)
1643 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
1644 if (queue
->continue_preamble_cs
)
1645 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
1646 if (queue
->descriptor_bo
)
1647 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
1648 if (queue
->scratch_bo
)
1649 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
1650 if (queue
->esgs_ring_bo
)
1651 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
1652 if (queue
->gsvs_ring_bo
)
1653 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
1654 if (queue
->tess_rings_bo
)
1655 queue
->device
->ws
->buffer_destroy(queue
->tess_rings_bo
);
1656 if (queue
->compute_scratch_bo
)
1657 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
1661 radv_bo_list_init(struct radv_bo_list
*bo_list
)
1663 pthread_mutex_init(&bo_list
->mutex
, NULL
);
1664 bo_list
->list
.count
= bo_list
->capacity
= 0;
1665 bo_list
->list
.bos
= NULL
;
1669 radv_bo_list_finish(struct radv_bo_list
*bo_list
)
1671 free(bo_list
->list
.bos
);
1672 pthread_mutex_destroy(&bo_list
->mutex
);
1675 static VkResult
radv_bo_list_add(struct radv_device
*device
,
1676 struct radeon_winsys_bo
*bo
)
1678 struct radv_bo_list
*bo_list
= &device
->bo_list
;
1683 if (unlikely(!device
->use_global_bo_list
))
1686 pthread_mutex_lock(&bo_list
->mutex
);
1687 if (bo_list
->list
.count
== bo_list
->capacity
) {
1688 unsigned capacity
= MAX2(4, bo_list
->capacity
* 2);
1689 void *data
= realloc(bo_list
->list
.bos
, capacity
* sizeof(struct radeon_winsys_bo
*));
1692 pthread_mutex_unlock(&bo_list
->mutex
);
1693 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1696 bo_list
->list
.bos
= (struct radeon_winsys_bo
**)data
;
1697 bo_list
->capacity
= capacity
;
1700 bo_list
->list
.bos
[bo_list
->list
.count
++] = bo
;
1701 pthread_mutex_unlock(&bo_list
->mutex
);
1705 static void radv_bo_list_remove(struct radv_device
*device
,
1706 struct radeon_winsys_bo
*bo
)
1708 struct radv_bo_list
*bo_list
= &device
->bo_list
;
1713 if (unlikely(!device
->use_global_bo_list
))
1716 pthread_mutex_lock(&bo_list
->mutex
);
1717 for(unsigned i
= 0; i
< bo_list
->list
.count
; ++i
) {
1718 if (bo_list
->list
.bos
[i
] == bo
) {
1719 bo_list
->list
.bos
[i
] = bo_list
->list
.bos
[bo_list
->list
.count
- 1];
1720 --bo_list
->list
.count
;
1724 pthread_mutex_unlock(&bo_list
->mutex
);
1728 radv_device_init_gs_info(struct radv_device
*device
)
1730 device
->gs_table_depth
= ac_get_gs_table_depth(device
->physical_device
->rad_info
.chip_class
,
1731 device
->physical_device
->rad_info
.family
);
1734 static int radv_get_device_extension_index(const char *name
)
1736 for (unsigned i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; ++i
) {
1737 if (strcmp(name
, radv_device_extensions
[i
].extensionName
) == 0)
1744 radv_get_int_debug_option(const char *name
, int default_value
)
1751 result
= default_value
;
1755 result
= strtol(str
, &endptr
, 0);
1756 if (str
== endptr
) {
1757 /* No digits founs. */
1758 result
= default_value
;
1765 VkResult
radv_CreateDevice(
1766 VkPhysicalDevice physicalDevice
,
1767 const VkDeviceCreateInfo
* pCreateInfo
,
1768 const VkAllocationCallbacks
* pAllocator
,
1771 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
1773 struct radv_device
*device
;
1775 bool keep_shader_info
= false;
1777 /* Check enabled features */
1778 if (pCreateInfo
->pEnabledFeatures
) {
1779 VkPhysicalDeviceFeatures supported_features
;
1780 radv_GetPhysicalDeviceFeatures(physicalDevice
, &supported_features
);
1781 VkBool32
*supported_feature
= (VkBool32
*)&supported_features
;
1782 VkBool32
*enabled_feature
= (VkBool32
*)pCreateInfo
->pEnabledFeatures
;
1783 unsigned num_features
= sizeof(VkPhysicalDeviceFeatures
) / sizeof(VkBool32
);
1784 for (uint32_t i
= 0; i
< num_features
; i
++) {
1785 if (enabled_feature
[i
] && !supported_feature
[i
])
1786 return vk_error(physical_device
->instance
, VK_ERROR_FEATURE_NOT_PRESENT
);
1790 device
= vk_zalloc2(&physical_device
->instance
->alloc
, pAllocator
,
1792 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
1794 return vk_error(physical_device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1796 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1797 device
->instance
= physical_device
->instance
;
1798 device
->physical_device
= physical_device
;
1800 device
->ws
= physical_device
->ws
;
1802 device
->alloc
= *pAllocator
;
1804 device
->alloc
= physical_device
->instance
->alloc
;
1806 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
1807 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
1808 int index
= radv_get_device_extension_index(ext_name
);
1809 if (index
< 0 || !physical_device
->supported_extensions
.extensions
[index
]) {
1810 vk_free(&device
->alloc
, device
);
1811 return vk_error(physical_device
->instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
1814 device
->enabled_extensions
.extensions
[index
] = true;
1817 keep_shader_info
= device
->enabled_extensions
.AMD_shader_info
;
1819 /* With update after bind we can't attach bo's to the command buffer
1820 * from the descriptor set anymore, so we have to use a global BO list.
1822 device
->use_global_bo_list
=
1823 (device
->instance
->perftest_flags
& RADV_PERFTEST_BO_LIST
) ||
1824 device
->enabled_extensions
.EXT_descriptor_indexing
||
1825 device
->enabled_extensions
.EXT_buffer_device_address
;
1827 mtx_init(&device
->shader_slab_mutex
, mtx_plain
);
1828 list_inithead(&device
->shader_slabs
);
1830 radv_bo_list_init(&device
->bo_list
);
1832 for (unsigned i
= 0; i
< pCreateInfo
->queueCreateInfoCount
; i
++) {
1833 const VkDeviceQueueCreateInfo
*queue_create
= &pCreateInfo
->pQueueCreateInfos
[i
];
1834 uint32_t qfi
= queue_create
->queueFamilyIndex
;
1835 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
=
1836 vk_find_struct_const(queue_create
->pNext
, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT
);
1838 assert(!global_priority
|| device
->physical_device
->rad_info
.has_ctx_priority
);
1840 device
->queues
[qfi
] = vk_alloc(&device
->alloc
,
1841 queue_create
->queueCount
* sizeof(struct radv_queue
), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
1842 if (!device
->queues
[qfi
]) {
1843 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
1847 memset(device
->queues
[qfi
], 0, queue_create
->queueCount
* sizeof(struct radv_queue
));
1849 device
->queue_count
[qfi
] = queue_create
->queueCount
;
1851 for (unsigned q
= 0; q
< queue_create
->queueCount
; q
++) {
1852 result
= radv_queue_init(device
, &device
->queues
[qfi
][q
],
1853 qfi
, q
, queue_create
->flags
,
1855 if (result
!= VK_SUCCESS
)
1860 device
->pbb_allowed
= device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
1861 !(device
->instance
->debug_flags
& RADV_DEBUG_NOBINNING
);
1863 /* Disabled and not implemented for now. */
1864 device
->dfsm_allowed
= device
->pbb_allowed
&&
1865 (device
->physical_device
->rad_info
.family
== CHIP_RAVEN
||
1866 device
->physical_device
->rad_info
.family
== CHIP_RAVEN2
);
1869 device
->always_use_syncobj
= device
->physical_device
->rad_info
.has_syncobj_wait_for_submit
;
1872 /* The maximum number of scratch waves. Scratch space isn't divided
1873 * evenly between CUs. The number is only a function of the number of CUs.
1874 * We can decrease the constant to decrease the scratch buffer size.
1876 * sctx->scratch_waves must be >= the maximum possible size of
1877 * 1 threadgroup, so that the hw doesn't hang from being unable
1880 * The recommended value is 4 per CU at most. Higher numbers don't
1881 * bring much benefit, but they still occupy chip resources (think
1882 * async compute). I've seen ~2% performance difference between 4 and 32.
1884 uint32_t max_threads_per_block
= 2048;
1885 device
->scratch_waves
= MAX2(32 * physical_device
->rad_info
.num_good_compute_units
,
1886 max_threads_per_block
/ 64);
1888 device
->dispatch_initiator
= S_00B800_COMPUTE_SHADER_EN(1);
1890 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
1891 /* If the KMD allows it (there is a KMD hw register for it),
1892 * allow launching waves out-of-order.
1894 device
->dispatch_initiator
|= S_00B800_ORDER_MODE(1);
1897 radv_device_init_gs_info(device
);
1899 device
->tess_offchip_block_dw_size
=
1900 device
->physical_device
->rad_info
.family
== CHIP_HAWAII
? 4096 : 8192;
1901 device
->has_distributed_tess
=
1902 device
->physical_device
->rad_info
.chip_class
>= GFX8
&&
1903 device
->physical_device
->rad_info
.max_se
>= 2;
1905 if (getenv("RADV_TRACE_FILE")) {
1906 const char *filename
= getenv("RADV_TRACE_FILE");
1908 keep_shader_info
= true;
1910 if (!radv_init_trace(device
))
1913 fprintf(stderr
, "*****************************************************************************\n");
1914 fprintf(stderr
, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1915 fprintf(stderr
, "*****************************************************************************\n");
1917 fprintf(stderr
, "Trace file will be dumped to %s\n", filename
);
1918 radv_dump_enabled_options(device
, stderr
);
1921 device
->keep_shader_info
= keep_shader_info
;
1923 result
= radv_device_init_meta(device
);
1924 if (result
!= VK_SUCCESS
)
1927 radv_device_init_msaa(device
);
1929 for (int family
= 0; family
< RADV_MAX_QUEUE_FAMILIES
; ++family
) {
1930 device
->empty_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
1932 case RADV_QUEUE_GENERAL
:
1933 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
1934 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_LOAD_ENABLE(1));
1935 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1937 case RADV_QUEUE_COMPUTE
:
1938 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_NOP
, 0, 0));
1939 radeon_emit(device
->empty_cs
[family
], 0);
1942 device
->ws
->cs_finalize(device
->empty_cs
[family
]);
1945 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
1946 cik_create_gfx_config(device
);
1948 VkPipelineCacheCreateInfo ci
;
1949 ci
.sType
= VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
;
1952 ci
.pInitialData
= NULL
;
1953 ci
.initialDataSize
= 0;
1955 result
= radv_CreatePipelineCache(radv_device_to_handle(device
),
1957 if (result
!= VK_SUCCESS
)
1960 device
->mem_cache
= radv_pipeline_cache_from_handle(pc
);
1962 device
->force_aniso
=
1963 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
1964 if (device
->force_aniso
>= 0) {
1965 fprintf(stderr
, "radv: Forcing anisotropy filter to %ix\n",
1966 1 << util_logbase2(device
->force_aniso
));
1969 *pDevice
= radv_device_to_handle(device
);
1973 radv_device_finish_meta(device
);
1975 radv_bo_list_finish(&device
->bo_list
);
1977 if (device
->trace_bo
)
1978 device
->ws
->buffer_destroy(device
->trace_bo
);
1980 if (device
->gfx_init
)
1981 device
->ws
->buffer_destroy(device
->gfx_init
);
1983 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
1984 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
1985 radv_queue_finish(&device
->queues
[i
][q
]);
1986 if (device
->queue_count
[i
])
1987 vk_free(&device
->alloc
, device
->queues
[i
]);
1990 vk_free(&device
->alloc
, device
);
1994 void radv_DestroyDevice(
1996 const VkAllocationCallbacks
* pAllocator
)
1998 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2003 if (device
->trace_bo
)
2004 device
->ws
->buffer_destroy(device
->trace_bo
);
2006 if (device
->gfx_init
)
2007 device
->ws
->buffer_destroy(device
->gfx_init
);
2009 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
2010 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
2011 radv_queue_finish(&device
->queues
[i
][q
]);
2012 if (device
->queue_count
[i
])
2013 vk_free(&device
->alloc
, device
->queues
[i
]);
2014 if (device
->empty_cs
[i
])
2015 device
->ws
->cs_destroy(device
->empty_cs
[i
]);
2017 radv_device_finish_meta(device
);
2019 VkPipelineCache pc
= radv_pipeline_cache_to_handle(device
->mem_cache
);
2020 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
2022 radv_destroy_shader_slabs(device
);
2024 radv_bo_list_finish(&device
->bo_list
);
2025 vk_free(&device
->alloc
, device
);
2028 VkResult
radv_EnumerateInstanceLayerProperties(
2029 uint32_t* pPropertyCount
,
2030 VkLayerProperties
* pProperties
)
2032 if (pProperties
== NULL
) {
2033 *pPropertyCount
= 0;
2037 /* None supported at this time */
2038 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
2041 VkResult
radv_EnumerateDeviceLayerProperties(
2042 VkPhysicalDevice physicalDevice
,
2043 uint32_t* pPropertyCount
,
2044 VkLayerProperties
* pProperties
)
2046 if (pProperties
== NULL
) {
2047 *pPropertyCount
= 0;
2051 /* None supported at this time */
2052 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
2055 void radv_GetDeviceQueue2(
2057 const VkDeviceQueueInfo2
* pQueueInfo
,
2060 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2061 struct radv_queue
*queue
;
2063 queue
= &device
->queues
[pQueueInfo
->queueFamilyIndex
][pQueueInfo
->queueIndex
];
2064 if (pQueueInfo
->flags
!= queue
->flags
) {
2065 /* From the Vulkan 1.1.70 spec:
2067 * "The queue returned by vkGetDeviceQueue2 must have the same
2068 * flags value from this structure as that used at device
2069 * creation time in a VkDeviceQueueCreateInfo instance. If no
2070 * matching flags were specified at device creation time then
2071 * pQueue will return VK_NULL_HANDLE."
2073 *pQueue
= VK_NULL_HANDLE
;
2077 *pQueue
= radv_queue_to_handle(queue
);
2080 void radv_GetDeviceQueue(
2082 uint32_t queueFamilyIndex
,
2083 uint32_t queueIndex
,
2086 const VkDeviceQueueInfo2 info
= (VkDeviceQueueInfo2
) {
2087 .sType
= VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2
,
2088 .queueFamilyIndex
= queueFamilyIndex
,
2089 .queueIndex
= queueIndex
2092 radv_GetDeviceQueue2(_device
, &info
, pQueue
);
2096 fill_geom_tess_rings(struct radv_queue
*queue
,
2098 bool add_sample_positions
,
2099 uint32_t esgs_ring_size
,
2100 struct radeon_winsys_bo
*esgs_ring_bo
,
2101 uint32_t gsvs_ring_size
,
2102 struct radeon_winsys_bo
*gsvs_ring_bo
,
2103 uint32_t tess_factor_ring_size
,
2104 uint32_t tess_offchip_ring_offset
,
2105 uint32_t tess_offchip_ring_size
,
2106 struct radeon_winsys_bo
*tess_rings_bo
)
2108 uint32_t *desc
= &map
[4];
2111 uint64_t esgs_va
= radv_buffer_get_va(esgs_ring_bo
);
2113 /* stride 0, num records - size, add tid, swizzle, elsize4,
2116 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32) |
2117 S_008F04_STRIDE(0) |
2118 S_008F04_SWIZZLE_ENABLE(true);
2119 desc
[2] = esgs_ring_size
;
2120 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2121 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2122 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2123 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2124 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2125 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2126 S_008F0C_ELEMENT_SIZE(1) |
2127 S_008F0C_INDEX_STRIDE(3) |
2128 S_008F0C_ADD_TID_ENABLE(true);
2130 /* GS entry for ES->GS ring */
2131 /* stride 0, num records - size, elsize0,
2134 desc
[5] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32)|
2135 S_008F04_STRIDE(0) |
2136 S_008F04_SWIZZLE_ENABLE(false);
2137 desc
[6] = esgs_ring_size
;
2138 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2139 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2140 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2141 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2142 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2143 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2144 S_008F0C_ELEMENT_SIZE(0) |
2145 S_008F0C_INDEX_STRIDE(0) |
2146 S_008F0C_ADD_TID_ENABLE(false);
2152 uint64_t gsvs_va
= radv_buffer_get_va(gsvs_ring_bo
);
2154 /* VS entry for GS->VS ring */
2155 /* stride 0, num records - size, elsize0,
2158 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32)|
2159 S_008F04_STRIDE(0) |
2160 S_008F04_SWIZZLE_ENABLE(false);
2161 desc
[2] = gsvs_ring_size
;
2162 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2163 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2164 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2165 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2166 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2167 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2168 S_008F0C_ELEMENT_SIZE(0) |
2169 S_008F0C_INDEX_STRIDE(0) |
2170 S_008F0C_ADD_TID_ENABLE(false);
2172 /* stride gsvs_itemsize, num records 64
2173 elsize 4, index stride 16 */
2174 /* shader will patch stride and desc[2] */
2176 desc
[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32)|
2177 S_008F04_STRIDE(0) |
2178 S_008F04_SWIZZLE_ENABLE(true);
2180 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2181 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2182 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2183 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2184 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2185 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2186 S_008F0C_ELEMENT_SIZE(1) |
2187 S_008F0C_INDEX_STRIDE(1) |
2188 S_008F0C_ADD_TID_ENABLE(true);
2193 if (tess_rings_bo
) {
2194 uint64_t tess_va
= radv_buffer_get_va(tess_rings_bo
);
2195 uint64_t tess_offchip_va
= tess_va
+ tess_offchip_ring_offset
;
2198 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_va
>> 32) |
2199 S_008F04_STRIDE(0) |
2200 S_008F04_SWIZZLE_ENABLE(false);
2201 desc
[2] = tess_factor_ring_size
;
2202 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2203 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2204 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2205 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2206 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2207 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2208 S_008F0C_ELEMENT_SIZE(0) |
2209 S_008F0C_INDEX_STRIDE(0) |
2210 S_008F0C_ADD_TID_ENABLE(false);
2212 desc
[4] = tess_offchip_va
;
2213 desc
[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va
>> 32) |
2214 S_008F04_STRIDE(0) |
2215 S_008F04_SWIZZLE_ENABLE(false);
2216 desc
[6] = tess_offchip_ring_size
;
2217 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2218 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2219 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2220 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2221 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2222 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2223 S_008F0C_ELEMENT_SIZE(0) |
2224 S_008F0C_INDEX_STRIDE(0) |
2225 S_008F0C_ADD_TID_ENABLE(false);
2230 if (add_sample_positions
) {
2231 /* add sample positions after all rings */
2232 memcpy(desc
, queue
->device
->sample_locations_1x
, 8);
2234 memcpy(desc
, queue
->device
->sample_locations_2x
, 16);
2236 memcpy(desc
, queue
->device
->sample_locations_4x
, 32);
2238 memcpy(desc
, queue
->device
->sample_locations_8x
, 64);
2243 radv_get_hs_offchip_param(struct radv_device
*device
, uint32_t *max_offchip_buffers_p
)
2245 bool double_offchip_buffers
= device
->physical_device
->rad_info
.chip_class
>= GFX7
&&
2246 device
->physical_device
->rad_info
.family
!= CHIP_CARRIZO
&&
2247 device
->physical_device
->rad_info
.family
!= CHIP_STONEY
;
2248 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
2249 unsigned max_offchip_buffers
;
2250 unsigned offchip_granularity
;
2251 unsigned hs_offchip_param
;
2255 * This must be one less than the maximum number due to a hw limitation.
2256 * Various hardware bugs need thGFX7
2259 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2260 * Gfx7 should limit max_offchip_buffers to 508
2261 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2263 * Follow AMDVLK here.
2265 if (device
->physical_device
->rad_info
.family
== CHIP_VEGA10
||
2266 device
->physical_device
->rad_info
.chip_class
== GFX7
||
2267 device
->physical_device
->rad_info
.chip_class
== GFX6
)
2268 --max_offchip_buffers_per_se
;
2270 max_offchip_buffers
= max_offchip_buffers_per_se
*
2271 device
->physical_device
->rad_info
.max_se
;
2273 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2274 * around by setting 4K granularity.
2276 if (device
->tess_offchip_block_dw_size
== 4096) {
2277 assert(device
->physical_device
->rad_info
.family
== CHIP_HAWAII
);
2278 offchip_granularity
= V_03093C_X_4K_DWORDS
;
2280 assert(device
->tess_offchip_block_dw_size
== 8192);
2281 offchip_granularity
= V_03093C_X_8K_DWORDS
;
2284 switch (device
->physical_device
->rad_info
.chip_class
) {
2286 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
2292 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
2296 *max_offchip_buffers_p
= max_offchip_buffers
;
2297 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2298 if (device
->physical_device
->rad_info
.chip_class
>= GFX8
)
2299 --max_offchip_buffers
;
2301 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
2302 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
2305 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
2307 return hs_offchip_param
;
2311 radv_emit_gs_ring_sizes(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
2312 struct radeon_winsys_bo
*esgs_ring_bo
,
2313 uint32_t esgs_ring_size
,
2314 struct radeon_winsys_bo
*gsvs_ring_bo
,
2315 uint32_t gsvs_ring_size
)
2317 if (!esgs_ring_bo
&& !gsvs_ring_bo
)
2321 radv_cs_add_buffer(queue
->device
->ws
, cs
, esgs_ring_bo
);
2324 radv_cs_add_buffer(queue
->device
->ws
, cs
, gsvs_ring_bo
);
2326 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2327 radeon_set_uconfig_reg_seq(cs
, R_030900_VGT_ESGS_RING_SIZE
, 2);
2328 radeon_emit(cs
, esgs_ring_size
>> 8);
2329 radeon_emit(cs
, gsvs_ring_size
>> 8);
2331 radeon_set_config_reg_seq(cs
, R_0088C8_VGT_ESGS_RING_SIZE
, 2);
2332 radeon_emit(cs
, esgs_ring_size
>> 8);
2333 radeon_emit(cs
, gsvs_ring_size
>> 8);
2338 radv_emit_tess_factor_ring(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
2339 unsigned hs_offchip_param
, unsigned tf_ring_size
,
2340 struct radeon_winsys_bo
*tess_rings_bo
)
2347 tf_va
= radv_buffer_get_va(tess_rings_bo
);
2349 radv_cs_add_buffer(queue
->device
->ws
, cs
, tess_rings_bo
);
2351 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2352 radeon_set_uconfig_reg(cs
, R_030938_VGT_TF_RING_SIZE
,
2353 S_030938_SIZE(tf_ring_size
/ 4));
2354 radeon_set_uconfig_reg(cs
, R_030940_VGT_TF_MEMORY_BASE
,
2356 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2357 radeon_set_uconfig_reg(cs
, R_030944_VGT_TF_MEMORY_BASE_HI
,
2358 S_030944_BASE_HI(tf_va
>> 40));
2360 radeon_set_uconfig_reg(cs
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
2363 radeon_set_config_reg(cs
, R_008988_VGT_TF_RING_SIZE
,
2364 S_008988_SIZE(tf_ring_size
/ 4));
2365 radeon_set_config_reg(cs
, R_0089B8_VGT_TF_MEMORY_BASE
,
2367 radeon_set_config_reg(cs
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
2373 radv_emit_compute_scratch(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
2374 struct radeon_winsys_bo
*compute_scratch_bo
)
2376 uint64_t scratch_va
;
2378 if (!compute_scratch_bo
)
2381 scratch_va
= radv_buffer_get_va(compute_scratch_bo
);
2383 radv_cs_add_buffer(queue
->device
->ws
, cs
, compute_scratch_bo
);
2385 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, 2);
2386 radeon_emit(cs
, scratch_va
);
2387 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
2388 S_008F04_SWIZZLE_ENABLE(1));
2392 radv_emit_global_shader_pointers(struct radv_queue
*queue
,
2393 struct radeon_cmdbuf
*cs
,
2394 struct radeon_winsys_bo
*descriptor_bo
)
2401 va
= radv_buffer_get_va(descriptor_bo
);
2403 radv_cs_add_buffer(queue
->device
->ws
, cs
, descriptor_bo
);
2405 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2406 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
2407 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
2408 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
2409 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
2411 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
2412 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
2416 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
2417 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
2418 R_00B230_SPI_SHADER_USER_DATA_GS_0
,
2419 R_00B330_SPI_SHADER_USER_DATA_ES_0
,
2420 R_00B430_SPI_SHADER_USER_DATA_HS_0
,
2421 R_00B530_SPI_SHADER_USER_DATA_LS_0
};
2423 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
2424 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
2431 radv_init_graphics_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
2433 struct radv_device
*device
= queue
->device
;
2435 if (device
->gfx_init
) {
2436 uint64_t va
= radv_buffer_get_va(device
->gfx_init
);
2438 radeon_emit(cs
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
2439 radeon_emit(cs
, va
);
2440 radeon_emit(cs
, va
>> 32);
2441 radeon_emit(cs
, device
->gfx_init_size_dw
& 0xffff);
2443 radv_cs_add_buffer(device
->ws
, cs
, device
->gfx_init
);
2445 struct radv_physical_device
*physical_device
= device
->physical_device
;
2446 si_emit_graphics(physical_device
, cs
);
2451 radv_init_compute_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
2453 struct radv_physical_device
*physical_device
= queue
->device
->physical_device
;
2454 si_emit_compute(physical_device
, cs
);
2458 radv_get_preamble_cs(struct radv_queue
*queue
,
2459 uint32_t scratch_size
,
2460 uint32_t compute_scratch_size
,
2461 uint32_t esgs_ring_size
,
2462 uint32_t gsvs_ring_size
,
2463 bool needs_tess_rings
,
2464 bool needs_sample_positions
,
2465 struct radeon_cmdbuf
**initial_full_flush_preamble_cs
,
2466 struct radeon_cmdbuf
**initial_preamble_cs
,
2467 struct radeon_cmdbuf
**continue_preamble_cs
)
2469 struct radeon_winsys_bo
*scratch_bo
= NULL
;
2470 struct radeon_winsys_bo
*descriptor_bo
= NULL
;
2471 struct radeon_winsys_bo
*compute_scratch_bo
= NULL
;
2472 struct radeon_winsys_bo
*esgs_ring_bo
= NULL
;
2473 struct radeon_winsys_bo
*gsvs_ring_bo
= NULL
;
2474 struct radeon_winsys_bo
*tess_rings_bo
= NULL
;
2475 struct radeon_cmdbuf
*dest_cs
[3] = {0};
2476 bool add_tess_rings
= false, add_sample_positions
= false;
2477 unsigned tess_factor_ring_size
= 0, tess_offchip_ring_size
= 0;
2478 unsigned max_offchip_buffers
;
2479 unsigned hs_offchip_param
= 0;
2480 unsigned tess_offchip_ring_offset
;
2481 uint32_t ring_bo_flags
= RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
;
2482 if (!queue
->has_tess_rings
) {
2483 if (needs_tess_rings
)
2484 add_tess_rings
= true;
2486 if (!queue
->has_sample_positions
) {
2487 if (needs_sample_positions
)
2488 add_sample_positions
= true;
2490 tess_factor_ring_size
= 32768 * queue
->device
->physical_device
->rad_info
.max_se
;
2491 hs_offchip_param
= radv_get_hs_offchip_param(queue
->device
,
2492 &max_offchip_buffers
);
2493 tess_offchip_ring_offset
= align(tess_factor_ring_size
, 64 * 1024);
2494 tess_offchip_ring_size
= max_offchip_buffers
*
2495 queue
->device
->tess_offchip_block_dw_size
* 4;
2497 if (scratch_size
<= queue
->scratch_size
&&
2498 compute_scratch_size
<= queue
->compute_scratch_size
&&
2499 esgs_ring_size
<= queue
->esgs_ring_size
&&
2500 gsvs_ring_size
<= queue
->gsvs_ring_size
&&
2501 !add_tess_rings
&& !add_sample_positions
&&
2502 queue
->initial_preamble_cs
) {
2503 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
2504 *initial_preamble_cs
= queue
->initial_preamble_cs
;
2505 *continue_preamble_cs
= queue
->continue_preamble_cs
;
2506 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
2507 *continue_preamble_cs
= NULL
;
2511 if (scratch_size
> queue
->scratch_size
) {
2512 scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2517 RADV_BO_PRIORITY_SCRATCH
);
2521 scratch_bo
= queue
->scratch_bo
;
2523 if (compute_scratch_size
> queue
->compute_scratch_size
) {
2524 compute_scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2525 compute_scratch_size
,
2529 RADV_BO_PRIORITY_SCRATCH
);
2530 if (!compute_scratch_bo
)
2534 compute_scratch_bo
= queue
->compute_scratch_bo
;
2536 if (esgs_ring_size
> queue
->esgs_ring_size
) {
2537 esgs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2542 RADV_BO_PRIORITY_SCRATCH
);
2546 esgs_ring_bo
= queue
->esgs_ring_bo
;
2547 esgs_ring_size
= queue
->esgs_ring_size
;
2550 if (gsvs_ring_size
> queue
->gsvs_ring_size
) {
2551 gsvs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2556 RADV_BO_PRIORITY_SCRATCH
);
2560 gsvs_ring_bo
= queue
->gsvs_ring_bo
;
2561 gsvs_ring_size
= queue
->gsvs_ring_size
;
2564 if (add_tess_rings
) {
2565 tess_rings_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2566 tess_offchip_ring_offset
+ tess_offchip_ring_size
,
2570 RADV_BO_PRIORITY_SCRATCH
);
2574 tess_rings_bo
= queue
->tess_rings_bo
;
2577 if (scratch_bo
!= queue
->scratch_bo
||
2578 esgs_ring_bo
!= queue
->esgs_ring_bo
||
2579 gsvs_ring_bo
!= queue
->gsvs_ring_bo
||
2580 tess_rings_bo
!= queue
->tess_rings_bo
||
2581 add_sample_positions
) {
2583 if (gsvs_ring_bo
|| esgs_ring_bo
||
2584 tess_rings_bo
|| add_sample_positions
) {
2585 size
= 112; /* 2 dword + 2 padding + 4 dword * 6 */
2586 if (add_sample_positions
)
2587 size
+= 128; /* 64+32+16+8 = 120 bytes */
2589 else if (scratch_bo
)
2590 size
= 8; /* 2 dword */
2592 descriptor_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2596 RADEON_FLAG_CPU_ACCESS
|
2597 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
2598 RADEON_FLAG_READ_ONLY
,
2599 RADV_BO_PRIORITY_DESCRIPTOR
);
2603 descriptor_bo
= queue
->descriptor_bo
;
2605 if (descriptor_bo
!= queue
->descriptor_bo
) {
2606 uint32_t *map
= (uint32_t*)queue
->device
->ws
->buffer_map(descriptor_bo
);
2609 uint64_t scratch_va
= radv_buffer_get_va(scratch_bo
);
2610 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
2611 S_008F04_SWIZZLE_ENABLE(1);
2612 map
[0] = scratch_va
;
2616 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
|| add_sample_positions
)
2617 fill_geom_tess_rings(queue
, map
, add_sample_positions
,
2618 esgs_ring_size
, esgs_ring_bo
,
2619 gsvs_ring_size
, gsvs_ring_bo
,
2620 tess_factor_ring_size
,
2621 tess_offchip_ring_offset
,
2622 tess_offchip_ring_size
,
2625 queue
->device
->ws
->buffer_unmap(descriptor_bo
);
2628 for(int i
= 0; i
< 3; ++i
) {
2629 struct radeon_cmdbuf
*cs
= NULL
;
2630 cs
= queue
->device
->ws
->cs_create(queue
->device
->ws
,
2631 queue
->queue_family_index
? RING_COMPUTE
: RING_GFX
);
2638 radv_cs_add_buffer(queue
->device
->ws
, cs
, scratch_bo
);
2640 /* Emit initial configuration. */
2641 switch (queue
->queue_family_index
) {
2642 case RADV_QUEUE_GENERAL
:
2643 radv_init_graphics_state(cs
, queue
);
2645 case RADV_QUEUE_COMPUTE
:
2646 radv_init_compute_state(cs
, queue
);
2648 case RADV_QUEUE_TRANSFER
:
2652 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
) {
2653 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2654 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2655 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2656 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
2659 radv_emit_gs_ring_sizes(queue
, cs
, esgs_ring_bo
, esgs_ring_size
,
2660 gsvs_ring_bo
, gsvs_ring_size
);
2661 radv_emit_tess_factor_ring(queue
, cs
, hs_offchip_param
,
2662 tess_factor_ring_size
, tess_rings_bo
);
2663 radv_emit_global_shader_pointers(queue
, cs
, descriptor_bo
);
2664 radv_emit_compute_scratch(queue
, cs
, compute_scratch_bo
);
2667 si_cs_emit_cache_flush(cs
,
2668 queue
->device
->physical_device
->rad_info
.chip_class
,
2670 queue
->queue_family_index
== RING_COMPUTE
&&
2671 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
2672 (queue
->queue_family_index
== RADV_QUEUE_COMPUTE
? RADV_CMD_FLAG_CS_PARTIAL_FLUSH
: (RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
)) |
2673 RADV_CMD_FLAG_INV_ICACHE
|
2674 RADV_CMD_FLAG_INV_SMEM_L1
|
2675 RADV_CMD_FLAG_INV_VMEM_L1
|
2676 RADV_CMD_FLAG_INV_GLOBAL_L2
|
2677 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
2678 } else if (i
== 1) {
2679 si_cs_emit_cache_flush(cs
,
2680 queue
->device
->physical_device
->rad_info
.chip_class
,
2682 queue
->queue_family_index
== RING_COMPUTE
&&
2683 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
2684 RADV_CMD_FLAG_INV_ICACHE
|
2685 RADV_CMD_FLAG_INV_SMEM_L1
|
2686 RADV_CMD_FLAG_INV_VMEM_L1
|
2687 RADV_CMD_FLAG_INV_GLOBAL_L2
|
2688 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
2691 if (!queue
->device
->ws
->cs_finalize(cs
))
2695 if (queue
->initial_full_flush_preamble_cs
)
2696 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
2698 if (queue
->initial_preamble_cs
)
2699 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
2701 if (queue
->continue_preamble_cs
)
2702 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
2704 queue
->initial_full_flush_preamble_cs
= dest_cs
[0];
2705 queue
->initial_preamble_cs
= dest_cs
[1];
2706 queue
->continue_preamble_cs
= dest_cs
[2];
2708 if (scratch_bo
!= queue
->scratch_bo
) {
2709 if (queue
->scratch_bo
)
2710 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
2711 queue
->scratch_bo
= scratch_bo
;
2712 queue
->scratch_size
= scratch_size
;
2715 if (compute_scratch_bo
!= queue
->compute_scratch_bo
) {
2716 if (queue
->compute_scratch_bo
)
2717 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
2718 queue
->compute_scratch_bo
= compute_scratch_bo
;
2719 queue
->compute_scratch_size
= compute_scratch_size
;
2722 if (esgs_ring_bo
!= queue
->esgs_ring_bo
) {
2723 if (queue
->esgs_ring_bo
)
2724 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
2725 queue
->esgs_ring_bo
= esgs_ring_bo
;
2726 queue
->esgs_ring_size
= esgs_ring_size
;
2729 if (gsvs_ring_bo
!= queue
->gsvs_ring_bo
) {
2730 if (queue
->gsvs_ring_bo
)
2731 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
2732 queue
->gsvs_ring_bo
= gsvs_ring_bo
;
2733 queue
->gsvs_ring_size
= gsvs_ring_size
;
2736 if (tess_rings_bo
!= queue
->tess_rings_bo
) {
2737 queue
->tess_rings_bo
= tess_rings_bo
;
2738 queue
->has_tess_rings
= true;
2741 if (descriptor_bo
!= queue
->descriptor_bo
) {
2742 if (queue
->descriptor_bo
)
2743 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
2745 queue
->descriptor_bo
= descriptor_bo
;
2748 if (add_sample_positions
)
2749 queue
->has_sample_positions
= true;
2751 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
2752 *initial_preamble_cs
= queue
->initial_preamble_cs
;
2753 *continue_preamble_cs
= queue
->continue_preamble_cs
;
2754 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
2755 *continue_preamble_cs
= NULL
;
2758 for (int i
= 0; i
< ARRAY_SIZE(dest_cs
); ++i
)
2760 queue
->device
->ws
->cs_destroy(dest_cs
[i
]);
2761 if (descriptor_bo
&& descriptor_bo
!= queue
->descriptor_bo
)
2762 queue
->device
->ws
->buffer_destroy(descriptor_bo
);
2763 if (scratch_bo
&& scratch_bo
!= queue
->scratch_bo
)
2764 queue
->device
->ws
->buffer_destroy(scratch_bo
);
2765 if (compute_scratch_bo
&& compute_scratch_bo
!= queue
->compute_scratch_bo
)
2766 queue
->device
->ws
->buffer_destroy(compute_scratch_bo
);
2767 if (esgs_ring_bo
&& esgs_ring_bo
!= queue
->esgs_ring_bo
)
2768 queue
->device
->ws
->buffer_destroy(esgs_ring_bo
);
2769 if (gsvs_ring_bo
&& gsvs_ring_bo
!= queue
->gsvs_ring_bo
)
2770 queue
->device
->ws
->buffer_destroy(gsvs_ring_bo
);
2771 if (tess_rings_bo
&& tess_rings_bo
!= queue
->tess_rings_bo
)
2772 queue
->device
->ws
->buffer_destroy(tess_rings_bo
);
2773 return vk_error(queue
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2776 static VkResult
radv_alloc_sem_counts(struct radv_instance
*instance
,
2777 struct radv_winsys_sem_counts
*counts
,
2779 const VkSemaphore
*sems
,
2783 int syncobj_idx
= 0, sem_idx
= 0;
2785 if (num_sems
== 0 && _fence
== VK_NULL_HANDLE
)
2788 for (uint32_t i
= 0; i
< num_sems
; i
++) {
2789 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
2791 if (sem
->temp_syncobj
|| sem
->syncobj
)
2792 counts
->syncobj_count
++;
2794 counts
->sem_count
++;
2797 if (_fence
!= VK_NULL_HANDLE
) {
2798 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2799 if (fence
->temp_syncobj
|| fence
->syncobj
)
2800 counts
->syncobj_count
++;
2803 if (counts
->syncobj_count
) {
2804 counts
->syncobj
= (uint32_t *)malloc(sizeof(uint32_t) * counts
->syncobj_count
);
2805 if (!counts
->syncobj
)
2806 return vk_error(instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2809 if (counts
->sem_count
) {
2810 counts
->sem
= (struct radeon_winsys_sem
**)malloc(sizeof(struct radeon_winsys_sem
*) * counts
->sem_count
);
2812 free(counts
->syncobj
);
2813 return vk_error(instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2817 for (uint32_t i
= 0; i
< num_sems
; i
++) {
2818 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
2820 if (sem
->temp_syncobj
) {
2821 counts
->syncobj
[syncobj_idx
++] = sem
->temp_syncobj
;
2823 else if (sem
->syncobj
)
2824 counts
->syncobj
[syncobj_idx
++] = sem
->syncobj
;
2827 counts
->sem
[sem_idx
++] = sem
->sem
;
2831 if (_fence
!= VK_NULL_HANDLE
) {
2832 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2833 if (fence
->temp_syncobj
)
2834 counts
->syncobj
[syncobj_idx
++] = fence
->temp_syncobj
;
2835 else if (fence
->syncobj
)
2836 counts
->syncobj
[syncobj_idx
++] = fence
->syncobj
;
2843 radv_free_sem_info(struct radv_winsys_sem_info
*sem_info
)
2845 free(sem_info
->wait
.syncobj
);
2846 free(sem_info
->wait
.sem
);
2847 free(sem_info
->signal
.syncobj
);
2848 free(sem_info
->signal
.sem
);
2852 static void radv_free_temp_syncobjs(struct radv_device
*device
,
2854 const VkSemaphore
*sems
)
2856 for (uint32_t i
= 0; i
< num_sems
; i
++) {
2857 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
2859 if (sem
->temp_syncobj
) {
2860 device
->ws
->destroy_syncobj(device
->ws
, sem
->temp_syncobj
);
2861 sem
->temp_syncobj
= 0;
2867 radv_alloc_sem_info(struct radv_instance
*instance
,
2868 struct radv_winsys_sem_info
*sem_info
,
2870 const VkSemaphore
*wait_sems
,
2871 int num_signal_sems
,
2872 const VkSemaphore
*signal_sems
,
2876 memset(sem_info
, 0, sizeof(*sem_info
));
2878 ret
= radv_alloc_sem_counts(instance
, &sem_info
->wait
, num_wait_sems
, wait_sems
, VK_NULL_HANDLE
, true);
2881 ret
= radv_alloc_sem_counts(instance
, &sem_info
->signal
, num_signal_sems
, signal_sems
, fence
, false);
2883 radv_free_sem_info(sem_info
);
2885 /* caller can override these */
2886 sem_info
->cs_emit_wait
= true;
2887 sem_info
->cs_emit_signal
= true;
2891 /* Signals fence as soon as all the work currently put on queue is done. */
2892 static VkResult
radv_signal_fence(struct radv_queue
*queue
,
2893 struct radv_fence
*fence
)
2897 struct radv_winsys_sem_info sem_info
;
2899 result
= radv_alloc_sem_info(queue
->device
->instance
, &sem_info
, 0, NULL
, 0, NULL
,
2900 radv_fence_to_handle(fence
));
2901 if (result
!= VK_SUCCESS
)
2904 ret
= queue
->device
->ws
->cs_submit(queue
->hw_ctx
, queue
->queue_idx
,
2905 &queue
->device
->empty_cs
[queue
->queue_family_index
],
2906 1, NULL
, NULL
, &sem_info
, NULL
,
2907 false, fence
->fence
);
2908 radv_free_sem_info(&sem_info
);
2911 return vk_error(queue
->device
->instance
, VK_ERROR_DEVICE_LOST
);
2916 VkResult
radv_QueueSubmit(
2918 uint32_t submitCount
,
2919 const VkSubmitInfo
* pSubmits
,
2922 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
2923 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2924 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
2925 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
2927 uint32_t max_cs_submission
= queue
->device
->trace_bo
? 1 : RADV_MAX_IBS_PER_SUBMIT
;
2928 uint32_t scratch_size
= 0;
2929 uint32_t compute_scratch_size
= 0;
2930 uint32_t esgs_ring_size
= 0, gsvs_ring_size
= 0;
2931 struct radeon_cmdbuf
*initial_preamble_cs
= NULL
, *initial_flush_preamble_cs
= NULL
, *continue_preamble_cs
= NULL
;
2933 bool fence_emitted
= false;
2934 bool tess_rings_needed
= false;
2935 bool sample_positions_needed
= false;
2937 /* Do this first so failing to allocate scratch buffers can't result in
2938 * partially executed submissions. */
2939 for (uint32_t i
= 0; i
< submitCount
; i
++) {
2940 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
2941 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
2942 pSubmits
[i
].pCommandBuffers
[j
]);
2944 scratch_size
= MAX2(scratch_size
, cmd_buffer
->scratch_size_needed
);
2945 compute_scratch_size
= MAX2(compute_scratch_size
,
2946 cmd_buffer
->compute_scratch_size_needed
);
2947 esgs_ring_size
= MAX2(esgs_ring_size
, cmd_buffer
->esgs_ring_size_needed
);
2948 gsvs_ring_size
= MAX2(gsvs_ring_size
, cmd_buffer
->gsvs_ring_size_needed
);
2949 tess_rings_needed
|= cmd_buffer
->tess_rings_needed
;
2950 sample_positions_needed
|= cmd_buffer
->sample_positions_needed
;
2954 result
= radv_get_preamble_cs(queue
, scratch_size
, compute_scratch_size
,
2955 esgs_ring_size
, gsvs_ring_size
, tess_rings_needed
,
2956 sample_positions_needed
, &initial_flush_preamble_cs
,
2957 &initial_preamble_cs
, &continue_preamble_cs
);
2958 if (result
!= VK_SUCCESS
)
2961 for (uint32_t i
= 0; i
< submitCount
; i
++) {
2962 struct radeon_cmdbuf
**cs_array
;
2963 bool do_flush
= !i
|| pSubmits
[i
].pWaitDstStageMask
;
2964 bool can_patch
= true;
2966 struct radv_winsys_sem_info sem_info
;
2968 result
= radv_alloc_sem_info(queue
->device
->instance
,
2970 pSubmits
[i
].waitSemaphoreCount
,
2971 pSubmits
[i
].pWaitSemaphores
,
2972 pSubmits
[i
].signalSemaphoreCount
,
2973 pSubmits
[i
].pSignalSemaphores
,
2975 if (result
!= VK_SUCCESS
)
2978 if (!pSubmits
[i
].commandBufferCount
) {
2979 if (pSubmits
[i
].waitSemaphoreCount
|| pSubmits
[i
].signalSemaphoreCount
) {
2980 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
2981 &queue
->device
->empty_cs
[queue
->queue_family_index
],
2986 radv_loge("failed to submit CS %d\n", i
);
2989 fence_emitted
= true;
2991 radv_free_sem_info(&sem_info
);
2995 cs_array
= malloc(sizeof(struct radeon_cmdbuf
*) *
2996 (pSubmits
[i
].commandBufferCount
));
2998 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
2999 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
3000 pSubmits
[i
].pCommandBuffers
[j
]);
3001 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
3003 cs_array
[j
] = cmd_buffer
->cs
;
3004 if ((cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT
))
3007 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_PENDING
;
3010 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
+= advance
) {
3011 struct radeon_cmdbuf
*initial_preamble
= (do_flush
&& !j
) ? initial_flush_preamble_cs
: initial_preamble_cs
;
3012 const struct radv_winsys_bo_list
*bo_list
= NULL
;
3014 advance
= MIN2(max_cs_submission
,
3015 pSubmits
[i
].commandBufferCount
- j
);
3017 if (queue
->device
->trace_bo
)
3018 *queue
->device
->trace_id_ptr
= 0;
3020 sem_info
.cs_emit_wait
= j
== 0;
3021 sem_info
.cs_emit_signal
= j
+ advance
== pSubmits
[i
].commandBufferCount
;
3023 if (unlikely(queue
->device
->use_global_bo_list
)) {
3024 pthread_mutex_lock(&queue
->device
->bo_list
.mutex
);
3025 bo_list
= &queue
->device
->bo_list
.list
;
3028 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, cs_array
+ j
,
3029 advance
, initial_preamble
, continue_preamble_cs
,
3031 can_patch
, base_fence
);
3033 if (unlikely(queue
->device
->use_global_bo_list
))
3034 pthread_mutex_unlock(&queue
->device
->bo_list
.mutex
);
3037 radv_loge("failed to submit CS %d\n", i
);
3040 fence_emitted
= true;
3041 if (queue
->device
->trace_bo
) {
3042 radv_check_gpu_hangs(queue
, cs_array
[j
]);
3046 radv_free_temp_syncobjs(queue
->device
,
3047 pSubmits
[i
].waitSemaphoreCount
,
3048 pSubmits
[i
].pWaitSemaphores
);
3049 radv_free_sem_info(&sem_info
);
3054 if (!fence_emitted
) {
3055 result
= radv_signal_fence(queue
, fence
);
3056 if (result
!= VK_SUCCESS
)
3064 VkResult
radv_QueueWaitIdle(
3067 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
3069 queue
->device
->ws
->ctx_wait_idle(queue
->hw_ctx
,
3070 radv_queue_family_to_ring(queue
->queue_family_index
),
3075 VkResult
radv_DeviceWaitIdle(
3078 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3080 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
3081 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++) {
3082 radv_QueueWaitIdle(radv_queue_to_handle(&device
->queues
[i
][q
]));
3088 VkResult
radv_EnumerateInstanceExtensionProperties(
3089 const char* pLayerName
,
3090 uint32_t* pPropertyCount
,
3091 VkExtensionProperties
* pProperties
)
3093 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
3095 for (int i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; i
++) {
3096 if (radv_supported_instance_extensions
.extensions
[i
]) {
3097 vk_outarray_append(&out
, prop
) {
3098 *prop
= radv_instance_extensions
[i
];
3103 return vk_outarray_status(&out
);
3106 VkResult
radv_EnumerateDeviceExtensionProperties(
3107 VkPhysicalDevice physicalDevice
,
3108 const char* pLayerName
,
3109 uint32_t* pPropertyCount
,
3110 VkExtensionProperties
* pProperties
)
3112 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
3113 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
3115 for (int i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; i
++) {
3116 if (device
->supported_extensions
.extensions
[i
]) {
3117 vk_outarray_append(&out
, prop
) {
3118 *prop
= radv_device_extensions
[i
];
3123 return vk_outarray_status(&out
);
3126 PFN_vkVoidFunction
radv_GetInstanceProcAddr(
3127 VkInstance _instance
,
3130 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
3132 return radv_lookup_entrypoint_checked(pName
,
3133 instance
? instance
->apiVersion
: 0,
3134 instance
? &instance
->enabled_extensions
: NULL
,
3138 /* The loader wants us to expose a second GetInstanceProcAddr function
3139 * to work around certain LD_PRELOAD issues seen in apps.
3142 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
3143 VkInstance instance
,
3147 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
3148 VkInstance instance
,
3151 return radv_GetInstanceProcAddr(instance
, pName
);
3155 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
3156 VkInstance _instance
,
3160 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
3161 VkInstance _instance
,
3164 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
3166 return radv_lookup_physical_device_entrypoint_checked(pName
,
3167 instance
? instance
->apiVersion
: 0,
3168 instance
? &instance
->enabled_extensions
: NULL
);
3171 PFN_vkVoidFunction
radv_GetDeviceProcAddr(
3175 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3177 return radv_lookup_entrypoint_checked(pName
,
3178 device
->instance
->apiVersion
,
3179 &device
->instance
->enabled_extensions
,
3180 &device
->enabled_extensions
);
3183 bool radv_get_memory_fd(struct radv_device
*device
,
3184 struct radv_device_memory
*memory
,
3187 struct radeon_bo_metadata metadata
;
3189 if (memory
->image
) {
3190 radv_init_metadata(device
, memory
->image
, &metadata
);
3191 device
->ws
->buffer_set_metadata(memory
->bo
, &metadata
);
3194 return device
->ws
->buffer_get_fd(device
->ws
, memory
->bo
,
3198 static VkResult
radv_alloc_memory(struct radv_device
*device
,
3199 const VkMemoryAllocateInfo
* pAllocateInfo
,
3200 const VkAllocationCallbacks
* pAllocator
,
3201 VkDeviceMemory
* pMem
)
3203 struct radv_device_memory
*mem
;
3205 enum radeon_bo_domain domain
;
3207 enum radv_mem_type mem_type_index
= device
->physical_device
->mem_type_indices
[pAllocateInfo
->memoryTypeIndex
];
3209 assert(pAllocateInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO
);
3211 if (pAllocateInfo
->allocationSize
== 0) {
3212 /* Apparently, this is allowed */
3213 *pMem
= VK_NULL_HANDLE
;
3217 const VkImportMemoryFdInfoKHR
*import_info
=
3218 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_FD_INFO_KHR
);
3219 const VkMemoryDedicatedAllocateInfo
*dedicate_info
=
3220 vk_find_struct_const(pAllocateInfo
->pNext
, MEMORY_DEDICATED_ALLOCATE_INFO
);
3221 const VkExportMemoryAllocateInfo
*export_info
=
3222 vk_find_struct_const(pAllocateInfo
->pNext
, EXPORT_MEMORY_ALLOCATE_INFO
);
3223 const VkImportMemoryHostPointerInfoEXT
*host_ptr_info
=
3224 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_HOST_POINTER_INFO_EXT
);
3226 const struct wsi_memory_allocate_info
*wsi_info
=
3227 vk_find_struct_const(pAllocateInfo
->pNext
, WSI_MEMORY_ALLOCATE_INFO_MESA
);
3229 mem
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*mem
), 8,
3230 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3232 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3234 if (wsi_info
&& wsi_info
->implicit_sync
)
3235 flags
|= RADEON_FLAG_IMPLICIT_SYNC
;
3237 if (dedicate_info
) {
3238 mem
->image
= radv_image_from_handle(dedicate_info
->image
);
3239 mem
->buffer
= radv_buffer_from_handle(dedicate_info
->buffer
);
3245 float priority_float
= 0.5;
3246 const struct VkMemoryPriorityAllocateInfoEXT
*priority_ext
=
3247 vk_find_struct_const(pAllocateInfo
->pNext
,
3248 MEMORY_PRIORITY_ALLOCATE_INFO_EXT
);
3250 priority_float
= priority_ext
->priority
;
3252 unsigned priority
= MIN2(RADV_BO_PRIORITY_APPLICATION_MAX
- 1,
3253 (int)(priority_float
* RADV_BO_PRIORITY_APPLICATION_MAX
));
3255 mem
->user_ptr
= NULL
;
3258 assert(import_info
->handleType
==
3259 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
3260 import_info
->handleType
==
3261 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
3262 mem
->bo
= device
->ws
->buffer_from_fd(device
->ws
, import_info
->fd
,
3263 priority
, NULL
, NULL
);
3265 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
3268 close(import_info
->fd
);
3270 } else if (host_ptr_info
) {
3271 assert(host_ptr_info
->handleType
== VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
);
3272 assert(mem_type_index
== RADV_MEM_TYPE_GTT_CACHED
);
3273 mem
->bo
= device
->ws
->buffer_from_ptr(device
->ws
, host_ptr_info
->pHostPointer
,
3274 pAllocateInfo
->allocationSize
,
3277 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
3280 mem
->user_ptr
= host_ptr_info
->pHostPointer
;
3283 uint64_t alloc_size
= align_u64(pAllocateInfo
->allocationSize
, 4096);
3284 if (mem_type_index
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
||
3285 mem_type_index
== RADV_MEM_TYPE_GTT_CACHED
)
3286 domain
= RADEON_DOMAIN_GTT
;
3288 domain
= RADEON_DOMAIN_VRAM
;
3290 if (mem_type_index
== RADV_MEM_TYPE_VRAM
)
3291 flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
3293 flags
|= RADEON_FLAG_CPU_ACCESS
;
3295 if (mem_type_index
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
)
3296 flags
|= RADEON_FLAG_GTT_WC
;
3298 if (!dedicate_info
&& !import_info
&& (!export_info
|| !export_info
->handleTypes
)) {
3299 flags
|= RADEON_FLAG_NO_INTERPROCESS_SHARING
;
3300 if (device
->use_global_bo_list
) {
3301 flags
|= RADEON_FLAG_PREFER_LOCAL_BO
;
3305 mem
->bo
= device
->ws
->buffer_create(device
->ws
, alloc_size
, device
->physical_device
->rad_info
.max_alignment
,
3306 domain
, flags
, priority
);
3309 result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
3312 mem
->type_index
= mem_type_index
;
3315 result
= radv_bo_list_add(device
, mem
->bo
);
3316 if (result
!= VK_SUCCESS
)
3319 *pMem
= radv_device_memory_to_handle(mem
);
3324 device
->ws
->buffer_destroy(mem
->bo
);
3326 vk_free2(&device
->alloc
, pAllocator
, mem
);
3331 VkResult
radv_AllocateMemory(
3333 const VkMemoryAllocateInfo
* pAllocateInfo
,
3334 const VkAllocationCallbacks
* pAllocator
,
3335 VkDeviceMemory
* pMem
)
3337 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3338 return radv_alloc_memory(device
, pAllocateInfo
, pAllocator
, pMem
);
3341 void radv_FreeMemory(
3343 VkDeviceMemory _mem
,
3344 const VkAllocationCallbacks
* pAllocator
)
3346 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3347 RADV_FROM_HANDLE(radv_device_memory
, mem
, _mem
);
3352 radv_bo_list_remove(device
, mem
->bo
);
3353 device
->ws
->buffer_destroy(mem
->bo
);
3356 vk_free2(&device
->alloc
, pAllocator
, mem
);
3359 VkResult
radv_MapMemory(
3361 VkDeviceMemory _memory
,
3362 VkDeviceSize offset
,
3364 VkMemoryMapFlags flags
,
3367 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3368 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
3376 *ppData
= mem
->user_ptr
;
3378 *ppData
= device
->ws
->buffer_map(mem
->bo
);
3385 return vk_error(device
->instance
, VK_ERROR_MEMORY_MAP_FAILED
);
3388 void radv_UnmapMemory(
3390 VkDeviceMemory _memory
)
3392 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3393 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
3398 if (mem
->user_ptr
== NULL
)
3399 device
->ws
->buffer_unmap(mem
->bo
);
3402 VkResult
radv_FlushMappedMemoryRanges(
3404 uint32_t memoryRangeCount
,
3405 const VkMappedMemoryRange
* pMemoryRanges
)
3410 VkResult
radv_InvalidateMappedMemoryRanges(
3412 uint32_t memoryRangeCount
,
3413 const VkMappedMemoryRange
* pMemoryRanges
)
3418 void radv_GetBufferMemoryRequirements(
3421 VkMemoryRequirements
* pMemoryRequirements
)
3423 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3424 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3426 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
3428 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
3429 pMemoryRequirements
->alignment
= 4096;
3431 pMemoryRequirements
->alignment
= 16;
3433 pMemoryRequirements
->size
= align64(buffer
->size
, pMemoryRequirements
->alignment
);
3436 void radv_GetBufferMemoryRequirements2(
3438 const VkBufferMemoryRequirementsInfo2
*pInfo
,
3439 VkMemoryRequirements2
*pMemoryRequirements
)
3441 radv_GetBufferMemoryRequirements(device
, pInfo
->buffer
,
3442 &pMemoryRequirements
->memoryRequirements
);
3443 RADV_FROM_HANDLE(radv_buffer
, buffer
, pInfo
->buffer
);
3444 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
3445 switch (ext
->sType
) {
3446 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
3447 VkMemoryDedicatedRequirements
*req
=
3448 (VkMemoryDedicatedRequirements
*) ext
;
3449 req
->requiresDedicatedAllocation
= buffer
->shareable
;
3450 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
3459 void radv_GetImageMemoryRequirements(
3462 VkMemoryRequirements
* pMemoryRequirements
)
3464 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3465 RADV_FROM_HANDLE(radv_image
, image
, _image
);
3467 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
3469 pMemoryRequirements
->size
= image
->size
;
3470 pMemoryRequirements
->alignment
= image
->alignment
;
3473 void radv_GetImageMemoryRequirements2(
3475 const VkImageMemoryRequirementsInfo2
*pInfo
,
3476 VkMemoryRequirements2
*pMemoryRequirements
)
3478 radv_GetImageMemoryRequirements(device
, pInfo
->image
,
3479 &pMemoryRequirements
->memoryRequirements
);
3481 RADV_FROM_HANDLE(radv_image
, image
, pInfo
->image
);
3483 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
3484 switch (ext
->sType
) {
3485 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
3486 VkMemoryDedicatedRequirements
*req
=
3487 (VkMemoryDedicatedRequirements
*) ext
;
3488 req
->requiresDedicatedAllocation
= image
->shareable
;
3489 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
3498 void radv_GetImageSparseMemoryRequirements(
3501 uint32_t* pSparseMemoryRequirementCount
,
3502 VkSparseImageMemoryRequirements
* pSparseMemoryRequirements
)
3507 void radv_GetImageSparseMemoryRequirements2(
3509 const VkImageSparseMemoryRequirementsInfo2
*pInfo
,
3510 uint32_t* pSparseMemoryRequirementCount
,
3511 VkSparseImageMemoryRequirements2
*pSparseMemoryRequirements
)
3516 void radv_GetDeviceMemoryCommitment(
3518 VkDeviceMemory memory
,
3519 VkDeviceSize
* pCommittedMemoryInBytes
)
3521 *pCommittedMemoryInBytes
= 0;
3524 VkResult
radv_BindBufferMemory2(VkDevice device
,
3525 uint32_t bindInfoCount
,
3526 const VkBindBufferMemoryInfo
*pBindInfos
)
3528 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
3529 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
3530 RADV_FROM_HANDLE(radv_buffer
, buffer
, pBindInfos
[i
].buffer
);
3533 buffer
->bo
= mem
->bo
;
3534 buffer
->offset
= pBindInfos
[i
].memoryOffset
;
3542 VkResult
radv_BindBufferMemory(
3545 VkDeviceMemory memory
,
3546 VkDeviceSize memoryOffset
)
3548 const VkBindBufferMemoryInfo info
= {
3549 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
3552 .memoryOffset
= memoryOffset
3555 return radv_BindBufferMemory2(device
, 1, &info
);
3558 VkResult
radv_BindImageMemory2(VkDevice device
,
3559 uint32_t bindInfoCount
,
3560 const VkBindImageMemoryInfo
*pBindInfos
)
3562 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
3563 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
3564 RADV_FROM_HANDLE(radv_image
, image
, pBindInfos
[i
].image
);
3567 image
->bo
= mem
->bo
;
3568 image
->offset
= pBindInfos
[i
].memoryOffset
;
3578 VkResult
radv_BindImageMemory(
3581 VkDeviceMemory memory
,
3582 VkDeviceSize memoryOffset
)
3584 const VkBindImageMemoryInfo info
= {
3585 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
3588 .memoryOffset
= memoryOffset
3591 return radv_BindImageMemory2(device
, 1, &info
);
3596 radv_sparse_buffer_bind_memory(struct radv_device
*device
,
3597 const VkSparseBufferMemoryBindInfo
*bind
)
3599 RADV_FROM_HANDLE(radv_buffer
, buffer
, bind
->buffer
);
3601 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
3602 struct radv_device_memory
*mem
= NULL
;
3604 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
3605 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
3607 device
->ws
->buffer_virtual_bind(buffer
->bo
,
3608 bind
->pBinds
[i
].resourceOffset
,
3609 bind
->pBinds
[i
].size
,
3610 mem
? mem
->bo
: NULL
,
3611 bind
->pBinds
[i
].memoryOffset
);
3616 radv_sparse_image_opaque_bind_memory(struct radv_device
*device
,
3617 const VkSparseImageOpaqueMemoryBindInfo
*bind
)
3619 RADV_FROM_HANDLE(radv_image
, image
, bind
->image
);
3621 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
3622 struct radv_device_memory
*mem
= NULL
;
3624 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
3625 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
3627 device
->ws
->buffer_virtual_bind(image
->bo
,
3628 bind
->pBinds
[i
].resourceOffset
,
3629 bind
->pBinds
[i
].size
,
3630 mem
? mem
->bo
: NULL
,
3631 bind
->pBinds
[i
].memoryOffset
);
3635 VkResult
radv_QueueBindSparse(
3637 uint32_t bindInfoCount
,
3638 const VkBindSparseInfo
* pBindInfo
,
3641 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3642 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
3643 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
3644 bool fence_emitted
= false;
3648 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
3649 struct radv_winsys_sem_info sem_info
;
3650 for (uint32_t j
= 0; j
< pBindInfo
[i
].bufferBindCount
; ++j
) {
3651 radv_sparse_buffer_bind_memory(queue
->device
,
3652 pBindInfo
[i
].pBufferBinds
+ j
);
3655 for (uint32_t j
= 0; j
< pBindInfo
[i
].imageOpaqueBindCount
; ++j
) {
3656 radv_sparse_image_opaque_bind_memory(queue
->device
,
3657 pBindInfo
[i
].pImageOpaqueBinds
+ j
);
3661 result
= radv_alloc_sem_info(queue
->device
->instance
,
3663 pBindInfo
[i
].waitSemaphoreCount
,
3664 pBindInfo
[i
].pWaitSemaphores
,
3665 pBindInfo
[i
].signalSemaphoreCount
,
3666 pBindInfo
[i
].pSignalSemaphores
,
3668 if (result
!= VK_SUCCESS
)
3671 if (pBindInfo
[i
].waitSemaphoreCount
|| pBindInfo
[i
].signalSemaphoreCount
) {
3672 ret
= queue
->device
->ws
->cs_submit(queue
->hw_ctx
, queue
->queue_idx
,
3673 &queue
->device
->empty_cs
[queue
->queue_family_index
],
3678 radv_loge("failed to submit CS %d\n", i
);
3682 fence_emitted
= true;
3685 radv_free_sem_info(&sem_info
);
3690 if (!fence_emitted
) {
3691 result
= radv_signal_fence(queue
, fence
);
3692 if (result
!= VK_SUCCESS
)
3700 VkResult
radv_CreateFence(
3702 const VkFenceCreateInfo
* pCreateInfo
,
3703 const VkAllocationCallbacks
* pAllocator
,
3706 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3707 const VkExportFenceCreateInfo
*export
=
3708 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_FENCE_CREATE_INFO
);
3709 VkExternalFenceHandleTypeFlags handleTypes
=
3710 export
? export
->handleTypes
: 0;
3712 struct radv_fence
*fence
= vk_alloc2(&device
->alloc
, pAllocator
,
3714 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3717 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3719 fence
->fence_wsi
= NULL
;
3720 fence
->temp_syncobj
= 0;
3721 if (device
->always_use_syncobj
|| handleTypes
) {
3722 int ret
= device
->ws
->create_syncobj(device
->ws
, &fence
->syncobj
);
3724 vk_free2(&device
->alloc
, pAllocator
, fence
);
3725 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3727 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
) {
3728 device
->ws
->signal_syncobj(device
->ws
, fence
->syncobj
);
3730 fence
->fence
= NULL
;
3732 fence
->fence
= device
->ws
->create_fence();
3733 if (!fence
->fence
) {
3734 vk_free2(&device
->alloc
, pAllocator
, fence
);
3735 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3738 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
)
3739 device
->ws
->signal_fence(fence
->fence
);
3742 *pFence
= radv_fence_to_handle(fence
);
3747 void radv_DestroyFence(
3750 const VkAllocationCallbacks
* pAllocator
)
3752 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3753 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3758 if (fence
->temp_syncobj
)
3759 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
3761 device
->ws
->destroy_syncobj(device
->ws
, fence
->syncobj
);
3763 device
->ws
->destroy_fence(fence
->fence
);
3764 if (fence
->fence_wsi
)
3765 fence
->fence_wsi
->destroy(fence
->fence_wsi
);
3766 vk_free2(&device
->alloc
, pAllocator
, fence
);
3770 uint64_t radv_get_current_time(void)
3773 clock_gettime(CLOCK_MONOTONIC
, &tv
);
3774 return tv
.tv_nsec
+ tv
.tv_sec
*1000000000ull;
3777 static uint64_t radv_get_absolute_timeout(uint64_t timeout
)
3779 uint64_t current_time
= radv_get_current_time();
3781 timeout
= MIN2(UINT64_MAX
- current_time
, timeout
);
3783 return current_time
+ timeout
;
3787 static bool radv_all_fences_plain_and_submitted(struct radv_device
*device
,
3788 uint32_t fenceCount
, const VkFence
*pFences
)
3790 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3791 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3792 if (fence
->fence
== NULL
|| fence
->syncobj
||
3793 fence
->temp_syncobj
|| fence
->fence_wsi
||
3794 (!device
->ws
->is_fence_waitable(fence
->fence
)))
3800 static bool radv_all_fences_syncobj(uint32_t fenceCount
, const VkFence
*pFences
)
3802 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3803 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3804 if (fence
->syncobj
== 0 && fence
->temp_syncobj
== 0)
3810 VkResult
radv_WaitForFences(
3812 uint32_t fenceCount
,
3813 const VkFence
* pFences
,
3817 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3818 timeout
= radv_get_absolute_timeout(timeout
);
3820 if (device
->always_use_syncobj
&&
3821 radv_all_fences_syncobj(fenceCount
, pFences
))
3823 uint32_t *handles
= malloc(sizeof(uint32_t) * fenceCount
);
3825 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3827 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3828 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3829 handles
[i
] = fence
->temp_syncobj
? fence
->temp_syncobj
: fence
->syncobj
;
3832 bool success
= device
->ws
->wait_syncobj(device
->ws
, handles
, fenceCount
, waitAll
, timeout
);
3835 return success
? VK_SUCCESS
: VK_TIMEOUT
;
3838 if (!waitAll
&& fenceCount
> 1) {
3839 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3840 if (device
->physical_device
->rad_info
.drm_minor
>= 10 && radv_all_fences_plain_and_submitted(device
, fenceCount
, pFences
)) {
3841 uint32_t wait_count
= 0;
3842 struct radeon_winsys_fence
**fences
= malloc(sizeof(struct radeon_winsys_fence
*) * fenceCount
);
3844 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3846 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3847 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3849 if (device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0)) {
3854 fences
[wait_count
++] = fence
->fence
;
3857 bool success
= device
->ws
->fences_wait(device
->ws
, fences
, wait_count
,
3858 waitAll
, timeout
- radv_get_current_time());
3861 return success
? VK_SUCCESS
: VK_TIMEOUT
;
3864 while(radv_get_current_time() <= timeout
) {
3865 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3866 if (radv_GetFenceStatus(_device
, pFences
[i
]) == VK_SUCCESS
)
3873 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3874 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3875 bool expired
= false;
3877 if (fence
->temp_syncobj
) {
3878 if (!device
->ws
->wait_syncobj(device
->ws
, &fence
->temp_syncobj
, 1, true, timeout
))
3883 if (fence
->syncobj
) {
3884 if (!device
->ws
->wait_syncobj(device
->ws
, &fence
->syncobj
, 1, true, timeout
))
3890 if (!device
->ws
->is_fence_waitable(fence
->fence
)) {
3891 while(!device
->ws
->is_fence_waitable(fence
->fence
) &&
3892 radv_get_current_time() <= timeout
)
3896 expired
= device
->ws
->fence_wait(device
->ws
,
3903 if (fence
->fence_wsi
) {
3904 VkResult result
= fence
->fence_wsi
->wait(fence
->fence_wsi
, timeout
);
3905 if (result
!= VK_SUCCESS
)
3913 VkResult
radv_ResetFences(VkDevice _device
,
3914 uint32_t fenceCount
,
3915 const VkFence
*pFences
)
3917 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3919 for (unsigned i
= 0; i
< fenceCount
; ++i
) {
3920 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3922 device
->ws
->reset_fence(fence
->fence
);
3924 /* Per spec, we first restore the permanent payload, and then reset, so
3925 * having a temp syncobj should not skip resetting the permanent syncobj. */
3926 if (fence
->temp_syncobj
) {
3927 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
3928 fence
->temp_syncobj
= 0;
3931 if (fence
->syncobj
) {
3932 device
->ws
->reset_syncobj(device
->ws
, fence
->syncobj
);
3939 VkResult
radv_GetFenceStatus(VkDevice _device
, VkFence _fence
)
3941 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3942 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3944 if (fence
->temp_syncobj
) {
3945 bool success
= device
->ws
->wait_syncobj(device
->ws
, &fence
->temp_syncobj
, 1, true, 0);
3946 return success
? VK_SUCCESS
: VK_NOT_READY
;
3949 if (fence
->syncobj
) {
3950 bool success
= device
->ws
->wait_syncobj(device
->ws
, &fence
->syncobj
, 1, true, 0);
3951 return success
? VK_SUCCESS
: VK_NOT_READY
;
3955 if (!device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0))
3956 return VK_NOT_READY
;
3958 if (fence
->fence_wsi
) {
3959 VkResult result
= fence
->fence_wsi
->wait(fence
->fence_wsi
, 0);
3961 if (result
!= VK_SUCCESS
) {
3962 if (result
== VK_TIMEOUT
)
3963 return VK_NOT_READY
;
3971 // Queue semaphore functions
3973 VkResult
radv_CreateSemaphore(
3975 const VkSemaphoreCreateInfo
* pCreateInfo
,
3976 const VkAllocationCallbacks
* pAllocator
,
3977 VkSemaphore
* pSemaphore
)
3979 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3980 const VkExportSemaphoreCreateInfo
*export
=
3981 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_SEMAPHORE_CREATE_INFO
);
3982 VkExternalSemaphoreHandleTypeFlags handleTypes
=
3983 export
? export
->handleTypes
: 0;
3985 struct radv_semaphore
*sem
= vk_alloc2(&device
->alloc
, pAllocator
,
3987 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3989 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3991 sem
->temp_syncobj
= 0;
3992 /* create a syncobject if we are going to export this semaphore */
3993 if (device
->always_use_syncobj
|| handleTypes
) {
3994 assert (device
->physical_device
->rad_info
.has_syncobj
);
3995 int ret
= device
->ws
->create_syncobj(device
->ws
, &sem
->syncobj
);
3997 vk_free2(&device
->alloc
, pAllocator
, sem
);
3998 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4002 sem
->sem
= device
->ws
->create_sem(device
->ws
);
4004 vk_free2(&device
->alloc
, pAllocator
, sem
);
4005 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4010 *pSemaphore
= radv_semaphore_to_handle(sem
);
4014 void radv_DestroySemaphore(
4016 VkSemaphore _semaphore
,
4017 const VkAllocationCallbacks
* pAllocator
)
4019 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4020 RADV_FROM_HANDLE(radv_semaphore
, sem
, _semaphore
);
4025 device
->ws
->destroy_syncobj(device
->ws
, sem
->syncobj
);
4027 device
->ws
->destroy_sem(sem
->sem
);
4028 vk_free2(&device
->alloc
, pAllocator
, sem
);
4031 VkResult
radv_CreateEvent(
4033 const VkEventCreateInfo
* pCreateInfo
,
4034 const VkAllocationCallbacks
* pAllocator
,
4037 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4038 struct radv_event
*event
= vk_alloc2(&device
->alloc
, pAllocator
,
4040 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4043 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4045 event
->bo
= device
->ws
->buffer_create(device
->ws
, 8, 8,
4047 RADEON_FLAG_VA_UNCACHED
| RADEON_FLAG_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
,
4048 RADV_BO_PRIORITY_FENCE
);
4050 vk_free2(&device
->alloc
, pAllocator
, event
);
4051 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
4054 event
->map
= (uint64_t*)device
->ws
->buffer_map(event
->bo
);
4056 *pEvent
= radv_event_to_handle(event
);
4061 void radv_DestroyEvent(
4064 const VkAllocationCallbacks
* pAllocator
)
4066 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4067 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4071 device
->ws
->buffer_destroy(event
->bo
);
4072 vk_free2(&device
->alloc
, pAllocator
, event
);
4075 VkResult
radv_GetEventStatus(
4079 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4081 if (*event
->map
== 1)
4082 return VK_EVENT_SET
;
4083 return VK_EVENT_RESET
;
4086 VkResult
radv_SetEvent(
4090 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4096 VkResult
radv_ResetEvent(
4100 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4106 VkResult
radv_CreateBuffer(
4108 const VkBufferCreateInfo
* pCreateInfo
,
4109 const VkAllocationCallbacks
* pAllocator
,
4112 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4113 struct radv_buffer
*buffer
;
4115 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO
);
4117 buffer
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*buffer
), 8,
4118 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4120 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4122 buffer
->size
= pCreateInfo
->size
;
4123 buffer
->usage
= pCreateInfo
->usage
;
4126 buffer
->flags
= pCreateInfo
->flags
;
4128 buffer
->shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
4129 EXTERNAL_MEMORY_BUFFER_CREATE_INFO
) != NULL
;
4131 if (pCreateInfo
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
) {
4132 buffer
->bo
= device
->ws
->buffer_create(device
->ws
,
4133 align64(buffer
->size
, 4096),
4134 4096, 0, RADEON_FLAG_VIRTUAL
,
4135 RADV_BO_PRIORITY_VIRTUAL
);
4137 vk_free2(&device
->alloc
, pAllocator
, buffer
);
4138 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
4142 *pBuffer
= radv_buffer_to_handle(buffer
);
4147 void radv_DestroyBuffer(
4150 const VkAllocationCallbacks
* pAllocator
)
4152 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4153 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4158 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
4159 device
->ws
->buffer_destroy(buffer
->bo
);
4161 vk_free2(&device
->alloc
, pAllocator
, buffer
);
4164 VkDeviceAddress
radv_GetBufferDeviceAddressEXT(
4166 const VkBufferDeviceAddressInfoEXT
* pInfo
)
4168 RADV_FROM_HANDLE(radv_buffer
, buffer
, pInfo
->buffer
);
4169 return radv_buffer_get_va(buffer
->bo
) + buffer
->offset
;
4173 static inline unsigned
4174 si_tile_mode_index(const struct radv_image_plane
*plane
, unsigned level
, bool stencil
)
4177 return plane
->surface
.u
.legacy
.stencil_tiling_index
[level
];
4179 return plane
->surface
.u
.legacy
.tiling_index
[level
];
4182 static uint32_t radv_surface_max_layer_count(struct radv_image_view
*iview
)
4184 return iview
->type
== VK_IMAGE_VIEW_TYPE_3D
? iview
->extent
.depth
: (iview
->base_layer
+ iview
->layer_count
);
4188 radv_init_dcc_control_reg(struct radv_device
*device
,
4189 struct radv_image_view
*iview
)
4191 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
4192 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
4193 unsigned max_compressed_block_size
;
4194 unsigned independent_64b_blocks
;
4196 if (!radv_image_has_dcc(iview
->image
))
4199 if (iview
->image
->info
.samples
> 1) {
4200 if (iview
->image
->planes
[0].surface
.bpe
== 1)
4201 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
4202 else if (iview
->image
->planes
[0].surface
.bpe
== 2)
4203 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
4206 if (!device
->physical_device
->rad_info
.has_dedicated_vram
) {
4207 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4208 * dGPU and 64 for APU because all of our APUs to date use
4209 * DIMMs which have a request granularity size of 64B while all
4210 * other chips have a 32B request size.
4212 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
4215 if (iview
->image
->usage
& (VK_IMAGE_USAGE_SAMPLED_BIT
|
4216 VK_IMAGE_USAGE_TRANSFER_SRC_BIT
|
4217 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)) {
4218 /* If this DCC image is potentially going to be used in texture
4219 * fetches, we need some special settings.
4221 independent_64b_blocks
= 1;
4222 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
4224 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4225 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4226 * big as possible for better compression state.
4228 independent_64b_blocks
= 0;
4229 max_compressed_block_size
= max_uncompressed_block_size
;
4232 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
4233 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size
) |
4234 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
4235 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks
);
4239 radv_initialise_color_surface(struct radv_device
*device
,
4240 struct radv_color_buffer_info
*cb
,
4241 struct radv_image_view
*iview
)
4243 const struct vk_format_description
*desc
;
4244 unsigned ntype
, format
, swap
, endian
;
4245 unsigned blend_clamp
= 0, blend_bypass
= 0;
4247 const struct radv_image_plane
*plane
= &iview
->image
->planes
[iview
->plane_id
];
4248 const struct radeon_surf
*surf
= &plane
->surface
;
4250 desc
= vk_format_description(iview
->vk_format
);
4252 memset(cb
, 0, sizeof(*cb
));
4254 /* Intensity is implemented as Red, so treat it that way. */
4255 cb
->cb_color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == VK_SWIZZLE_1
);
4257 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ plane
->offset
;
4259 cb
->cb_color_base
= va
>> 8;
4261 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4262 struct gfx9_surf_meta_flags meta
;
4263 if (iview
->image
->dcc_offset
)
4264 meta
= surf
->u
.gfx9
.dcc
;
4266 meta
= surf
->u
.gfx9
.cmask
;
4268 cb
->cb_color_attrib
|= S_028C74_COLOR_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
4269 S_028C74_FMASK_SW_MODE(surf
->u
.gfx9
.fmask
.swizzle_mode
) |
4270 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
4271 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
4273 cb
->cb_color_base
+= surf
->u
.gfx9
.surf_offset
>> 8;
4274 cb
->cb_color_base
|= surf
->tile_swizzle
;
4276 cb
->cb_mrt_epitch
= S_0287A0_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
4278 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[iview
->base_mip
];
4279 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
4281 cb
->cb_color_base
+= level_info
->offset
>> 8;
4282 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
4283 cb
->cb_color_base
|= surf
->tile_swizzle
;
4285 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
4286 slice_tile_max
= (level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1;
4287 tile_mode_index
= si_tile_mode_index(plane
, iview
->base_mip
, false);
4289 cb
->cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
4290 cb
->cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
4291 cb
->cb_color_cmask_slice
= iview
->image
->cmask
.slice_tile_max
;
4293 cb
->cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
4295 if (radv_image_has_fmask(iview
->image
)) {
4296 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
4297 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(iview
->image
->fmask
.pitch_in_pixels
/ 8 - 1);
4298 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(iview
->image
->fmask
.tile_mode_index
);
4299 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(iview
->image
->fmask
.slice_tile_max
);
4301 /* This must be set for fast clear to work without FMASK. */
4302 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
4303 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
4304 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
4305 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
4309 /* CMASK variables */
4310 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
4311 va
+= iview
->image
->cmask
.offset
;
4312 cb
->cb_color_cmask
= va
>> 8;
4314 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
4315 va
+= iview
->image
->dcc_offset
;
4316 cb
->cb_dcc_base
= va
>> 8;
4317 cb
->cb_dcc_base
|= surf
->tile_swizzle
;
4319 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
4320 cb
->cb_color_view
= S_028C6C_SLICE_START(iview
->base_layer
) |
4321 S_028C6C_SLICE_MAX(max_slice
);
4323 if (iview
->image
->info
.samples
> 1) {
4324 unsigned log_samples
= util_logbase2(iview
->image
->info
.samples
);
4326 cb
->cb_color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
4327 S_028C74_NUM_FRAGMENTS(log_samples
);
4330 if (radv_image_has_fmask(iview
->image
)) {
4331 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ iview
->image
->fmask
.offset
;
4332 cb
->cb_color_fmask
= va
>> 8;
4333 cb
->cb_color_fmask
|= iview
->image
->fmask
.tile_swizzle
;
4335 cb
->cb_color_fmask
= cb
->cb_color_base
;
4338 ntype
= radv_translate_color_numformat(iview
->vk_format
,
4340 vk_format_get_first_non_void_channel(iview
->vk_format
));
4341 format
= radv_translate_colorformat(iview
->vk_format
);
4342 if (format
== V_028C70_COLOR_INVALID
|| ntype
== ~0u)
4343 radv_finishme("Illegal color\n");
4344 swap
= radv_translate_colorswap(iview
->vk_format
, FALSE
);
4345 endian
= radv_colorformat_endian_swap(format
);
4347 /* blend clamp should be set for all NORM/SRGB types */
4348 if (ntype
== V_028C70_NUMBER_UNORM
||
4349 ntype
== V_028C70_NUMBER_SNORM
||
4350 ntype
== V_028C70_NUMBER_SRGB
)
4353 /* set blend bypass according to docs if SINT/UINT or
4354 8/24 COLOR variants */
4355 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
4356 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
4357 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
4362 if ((ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) &&
4363 (format
== V_028C70_COLOR_8
||
4364 format
== V_028C70_COLOR_8_8
||
4365 format
== V_028C70_COLOR_8_8_8_8
))
4366 ->color_is_int8
= true;
4368 cb
->cb_color_info
= S_028C70_FORMAT(format
) |
4369 S_028C70_COMP_SWAP(swap
) |
4370 S_028C70_BLEND_CLAMP(blend_clamp
) |
4371 S_028C70_BLEND_BYPASS(blend_bypass
) |
4372 S_028C70_SIMPLE_FLOAT(1) |
4373 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
4374 ntype
!= V_028C70_NUMBER_SNORM
&&
4375 ntype
!= V_028C70_NUMBER_SRGB
&&
4376 format
!= V_028C70_COLOR_8_24
&&
4377 format
!= V_028C70_COLOR_24_8
) |
4378 S_028C70_NUMBER_TYPE(ntype
) |
4379 S_028C70_ENDIAN(endian
);
4380 if (radv_image_has_fmask(iview
->image
)) {
4381 cb
->cb_color_info
|= S_028C70_COMPRESSION(1);
4382 if (device
->physical_device
->rad_info
.chip_class
== GFX6
) {
4383 unsigned fmask_bankh
= util_logbase2(iview
->image
->fmask
.bank_height
);
4384 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
4388 if (radv_image_has_cmask(iview
->image
) &&
4389 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
))
4390 cb
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
4392 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
))
4393 cb
->cb_color_info
|= S_028C70_DCC_ENABLE(1);
4395 cb
->cb_dcc_control
= radv_init_dcc_control_reg(device
, iview
);
4397 /* This must be set for fast clear to work without FMASK. */
4398 if (!radv_image_has_fmask(iview
->image
) &&
4399 device
->physical_device
->rad_info
.chip_class
== GFX6
) {
4400 unsigned bankh
= util_logbase2(surf
->u
.legacy
.bankh
);
4401 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
4404 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4405 const struct vk_format_description
*format_desc
= vk_format_description(iview
->image
->vk_format
);
4407 unsigned mip0_depth
= iview
->image
->type
== VK_IMAGE_TYPE_3D
?
4408 (iview
->extent
.depth
- 1) : (iview
->image
->info
.array_size
- 1);
4409 unsigned width
= iview
->extent
.width
/ (iview
->plane_id
? format_desc
->width_divisor
: 1);
4410 unsigned height
= iview
->extent
.height
/ (iview
->plane_id
? format_desc
->height_divisor
: 1);
4412 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL(iview
->base_mip
);
4413 cb
->cb_color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
4414 S_028C74_RESOURCE_TYPE(surf
->u
.gfx9
.resource_type
);
4415 cb
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(width
- 1) |
4416 S_028C68_MIP0_HEIGHT(height
- 1) |
4417 S_028C68_MAX_MIP(iview
->image
->info
.levels
- 1);
4422 radv_calc_decompress_on_z_planes(struct radv_device
*device
,
4423 struct radv_image_view
*iview
)
4425 unsigned max_zplanes
= 0;
4427 assert(radv_image_is_tc_compat_htile(iview
->image
));
4429 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4430 /* Default value for 32-bit depth surfaces. */
4433 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
&&
4434 iview
->image
->info
.samples
> 1)
4437 max_zplanes
= max_zplanes
+ 1;
4439 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
) {
4440 /* Do not enable Z plane compression for 16-bit depth
4441 * surfaces because isn't supported on GFX8. Only
4442 * 32-bit depth surfaces are supported by the hardware.
4443 * This allows to maintain shader compatibility and to
4444 * reduce the number of depth decompressions.
4448 if (iview
->image
->info
.samples
<= 1)
4450 else if (iview
->image
->info
.samples
<= 4)
4461 radv_initialise_ds_surface(struct radv_device
*device
,
4462 struct radv_ds_buffer_info
*ds
,
4463 struct radv_image_view
*iview
)
4465 unsigned level
= iview
->base_mip
;
4466 unsigned format
, stencil_format
;
4467 uint64_t va
, s_offs
, z_offs
;
4468 bool stencil_only
= false;
4469 const struct radv_image_plane
*plane
= &iview
->image
->planes
[0];
4470 const struct radeon_surf
*surf
= &plane
->surface
;
4472 assert(vk_format_get_plane_count(iview
->image
->vk_format
) == 1);
4474 memset(ds
, 0, sizeof(*ds
));
4475 switch (iview
->image
->vk_format
) {
4476 case VK_FORMAT_D24_UNORM_S8_UINT
:
4477 case VK_FORMAT_X8_D24_UNORM_PACK32
:
4478 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4479 ds
->offset_scale
= 2.0f
;
4481 case VK_FORMAT_D16_UNORM
:
4482 case VK_FORMAT_D16_UNORM_S8_UINT
:
4483 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4484 ds
->offset_scale
= 4.0f
;
4486 case VK_FORMAT_D32_SFLOAT
:
4487 case VK_FORMAT_D32_SFLOAT_S8_UINT
:
4488 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4489 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4490 ds
->offset_scale
= 1.0f
;
4492 case VK_FORMAT_S8_UINT
:
4493 stencil_only
= true;
4499 format
= radv_translate_dbformat(iview
->image
->vk_format
);
4500 stencil_format
= surf
->has_stencil
?
4501 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
4503 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
4504 ds
->db_depth_view
= S_028008_SLICE_START(iview
->base_layer
) |
4505 S_028008_SLICE_MAX(max_slice
);
4507 ds
->db_htile_data_base
= 0;
4508 ds
->db_htile_surface
= 0;
4510 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
4511 s_offs
= z_offs
= va
;
4513 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4514 assert(surf
->u
.gfx9
.surf_offset
== 0);
4515 s_offs
+= surf
->u
.gfx9
.stencil_offset
;
4517 ds
->db_z_info
= S_028038_FORMAT(format
) |
4518 S_028038_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
)) |
4519 S_028038_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
4520 S_028038_MAXMIP(iview
->image
->info
.levels
- 1) |
4521 S_028038_ZRANGE_PRECISION(1);
4522 ds
->db_stencil_info
= S_02803C_FORMAT(stencil_format
) |
4523 S_02803C_SW_MODE(surf
->u
.gfx9
.stencil
.swizzle_mode
);
4525 ds
->db_z_info2
= S_028068_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
4526 ds
->db_stencil_info2
= S_02806C_EPITCH(surf
->u
.gfx9
.stencil
.epitch
);
4527 ds
->db_depth_view
|= S_028008_MIPID(level
);
4529 ds
->db_depth_size
= S_02801C_X_MAX(iview
->image
->info
.width
- 1) |
4530 S_02801C_Y_MAX(iview
->image
->info
.height
- 1);
4532 if (radv_htile_enabled(iview
->image
, level
)) {
4533 ds
->db_z_info
|= S_028038_TILE_SURFACE_ENABLE(1);
4535 if (radv_image_is_tc_compat_htile(iview
->image
)) {
4536 unsigned max_zplanes
=
4537 radv_calc_decompress_on_z_planes(device
, iview
);
4539 ds
->db_z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
) |
4540 S_028038_ITERATE_FLUSH(1);
4541 ds
->db_stencil_info
|= S_02803C_ITERATE_FLUSH(1);
4544 if (!surf
->has_stencil
)
4545 /* Use all of the htile_buffer for depth if there's no stencil. */
4546 ds
->db_stencil_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
4547 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
4548 iview
->image
->htile_offset
;
4549 ds
->db_htile_data_base
= va
>> 8;
4550 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
4551 S_028ABC_PIPE_ALIGNED(surf
->u
.gfx9
.htile
.pipe_aligned
) |
4552 S_028ABC_RB_ALIGNED(surf
->u
.gfx9
.htile
.rb_aligned
);
4555 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[level
];
4558 level_info
= &surf
->u
.legacy
.stencil_level
[level
];
4560 z_offs
+= surf
->u
.legacy
.level
[level
].offset
;
4561 s_offs
+= surf
->u
.legacy
.stencil_level
[level
].offset
;
4563 ds
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview
->image
));
4564 ds
->db_z_info
= S_028040_FORMAT(format
) | S_028040_ZRANGE_PRECISION(1);
4565 ds
->db_stencil_info
= S_028044_FORMAT(stencil_format
);
4567 if (iview
->image
->info
.samples
> 1)
4568 ds
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
));
4570 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4571 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
4572 unsigned tiling_index
= surf
->u
.legacy
.tiling_index
[level
];
4573 unsigned stencil_index
= surf
->u
.legacy
.stencil_tiling_index
[level
];
4574 unsigned macro_index
= surf
->u
.legacy
.macro_tile_index
;
4575 unsigned tile_mode
= info
->si_tile_mode_array
[tiling_index
];
4576 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
4577 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
4580 tile_mode
= stencil_tile_mode
;
4582 ds
->db_depth_info
|=
4583 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
4584 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
4585 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
4586 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
4587 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
4588 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
4589 ds
->db_z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
4590 ds
->db_stencil_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
4592 unsigned tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, false);
4593 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
4594 tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, true);
4595 ds
->db_stencil_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
4597 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
4600 ds
->db_depth_size
= S_028058_PITCH_TILE_MAX((level_info
->nblk_x
/ 8) - 1) |
4601 S_028058_HEIGHT_TILE_MAX((level_info
->nblk_y
/ 8) - 1);
4602 ds
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1);
4604 if (radv_htile_enabled(iview
->image
, level
)) {
4605 ds
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
4607 if (!surf
->has_stencil
&&
4608 !radv_image_is_tc_compat_htile(iview
->image
))
4609 /* Use all of the htile_buffer for depth if there's no stencil. */
4610 ds
->db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
4612 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
4613 iview
->image
->htile_offset
;
4614 ds
->db_htile_data_base
= va
>> 8;
4615 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
4617 if (radv_image_is_tc_compat_htile(iview
->image
)) {
4618 unsigned max_zplanes
=
4619 radv_calc_decompress_on_z_planes(device
, iview
);
4621 ds
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
4622 ds
->db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
4627 ds
->db_z_read_base
= ds
->db_z_write_base
= z_offs
>> 8;
4628 ds
->db_stencil_read_base
= ds
->db_stencil_write_base
= s_offs
>> 8;
4631 VkResult
radv_CreateFramebuffer(
4633 const VkFramebufferCreateInfo
* pCreateInfo
,
4634 const VkAllocationCallbacks
* pAllocator
,
4635 VkFramebuffer
* pFramebuffer
)
4637 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4638 struct radv_framebuffer
*framebuffer
;
4640 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
);
4642 size_t size
= sizeof(*framebuffer
) +
4643 sizeof(struct radv_attachment_info
) * pCreateInfo
->attachmentCount
;
4644 framebuffer
= vk_alloc2(&device
->alloc
, pAllocator
, size
, 8,
4645 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4646 if (framebuffer
== NULL
)
4647 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4649 framebuffer
->attachment_count
= pCreateInfo
->attachmentCount
;
4650 framebuffer
->width
= pCreateInfo
->width
;
4651 framebuffer
->height
= pCreateInfo
->height
;
4652 framebuffer
->layers
= pCreateInfo
->layers
;
4653 for (uint32_t i
= 0; i
< pCreateInfo
->attachmentCount
; i
++) {
4654 VkImageView _iview
= pCreateInfo
->pAttachments
[i
];
4655 struct radv_image_view
*iview
= radv_image_view_from_handle(_iview
);
4656 framebuffer
->attachments
[i
].attachment
= iview
;
4657 if (iview
->aspect_mask
& (VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4658 radv_initialise_ds_surface(device
, &framebuffer
->attachments
[i
].ds
, iview
);
4660 radv_initialise_color_surface(device
, &framebuffer
->attachments
[i
].cb
, iview
);
4662 framebuffer
->width
= MIN2(framebuffer
->width
, iview
->extent
.width
);
4663 framebuffer
->height
= MIN2(framebuffer
->height
, iview
->extent
.height
);
4664 framebuffer
->layers
= MIN2(framebuffer
->layers
, radv_surface_max_layer_count(iview
));
4667 *pFramebuffer
= radv_framebuffer_to_handle(framebuffer
);
4671 void radv_DestroyFramebuffer(
4674 const VkAllocationCallbacks
* pAllocator
)
4676 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4677 RADV_FROM_HANDLE(radv_framebuffer
, fb
, _fb
);
4681 vk_free2(&device
->alloc
, pAllocator
, fb
);
4684 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode
)
4686 switch (address_mode
) {
4687 case VK_SAMPLER_ADDRESS_MODE_REPEAT
:
4688 return V_008F30_SQ_TEX_WRAP
;
4689 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT
:
4690 return V_008F30_SQ_TEX_MIRROR
;
4691 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
:
4692 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
4693 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
:
4694 return V_008F30_SQ_TEX_CLAMP_BORDER
;
4695 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE
:
4696 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
4698 unreachable("illegal tex wrap mode");
4704 radv_tex_compare(VkCompareOp op
)
4707 case VK_COMPARE_OP_NEVER
:
4708 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
4709 case VK_COMPARE_OP_LESS
:
4710 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
4711 case VK_COMPARE_OP_EQUAL
:
4712 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
4713 case VK_COMPARE_OP_LESS_OR_EQUAL
:
4714 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
4715 case VK_COMPARE_OP_GREATER
:
4716 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
4717 case VK_COMPARE_OP_NOT_EQUAL
:
4718 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
4719 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
4720 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
4721 case VK_COMPARE_OP_ALWAYS
:
4722 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
4724 unreachable("illegal compare mode");
4730 radv_tex_filter(VkFilter filter
, unsigned max_ansio
)
4733 case VK_FILTER_NEAREST
:
4734 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
:
4735 V_008F38_SQ_TEX_XY_FILTER_POINT
);
4736 case VK_FILTER_LINEAR
:
4737 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
:
4738 V_008F38_SQ_TEX_XY_FILTER_BILINEAR
);
4739 case VK_FILTER_CUBIC_IMG
:
4741 fprintf(stderr
, "illegal texture filter");
4747 radv_tex_mipfilter(VkSamplerMipmapMode mode
)
4750 case VK_SAMPLER_MIPMAP_MODE_NEAREST
:
4751 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
4752 case VK_SAMPLER_MIPMAP_MODE_LINEAR
:
4753 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
4755 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
4760 radv_tex_bordercolor(VkBorderColor bcolor
)
4763 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
:
4764 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK
:
4765 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
4766 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK
:
4767 case VK_BORDER_COLOR_INT_OPAQUE_BLACK
:
4768 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
4769 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE
:
4770 case VK_BORDER_COLOR_INT_OPAQUE_WHITE
:
4771 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
4779 radv_tex_aniso_filter(unsigned filter
)
4793 radv_tex_filter_mode(VkSamplerReductionModeEXT mode
)
4796 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT
:
4797 return V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
4798 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT
:
4799 return V_008F30_SQ_IMG_FILTER_MODE_MIN
;
4800 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT
:
4801 return V_008F30_SQ_IMG_FILTER_MODE_MAX
;
4809 radv_get_max_anisotropy(struct radv_device
*device
,
4810 const VkSamplerCreateInfo
*pCreateInfo
)
4812 if (device
->force_aniso
>= 0)
4813 return device
->force_aniso
;
4815 if (pCreateInfo
->anisotropyEnable
&&
4816 pCreateInfo
->maxAnisotropy
> 1.0f
)
4817 return (uint32_t)pCreateInfo
->maxAnisotropy
;
4823 radv_init_sampler(struct radv_device
*device
,
4824 struct radv_sampler
*sampler
,
4825 const VkSamplerCreateInfo
*pCreateInfo
)
4827 uint32_t max_aniso
= radv_get_max_anisotropy(device
, pCreateInfo
);
4828 uint32_t max_aniso_ratio
= radv_tex_aniso_filter(max_aniso
);
4829 bool is_vi
= (device
->physical_device
->rad_info
.chip_class
>= GFX8
);
4830 unsigned filter_mode
= V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
4832 const struct VkSamplerReductionModeCreateInfoEXT
*sampler_reduction
=
4833 vk_find_struct_const(pCreateInfo
->pNext
,
4834 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT
);
4835 if (sampler_reduction
)
4836 filter_mode
= radv_tex_filter_mode(sampler_reduction
->reductionMode
);
4838 sampler
->state
[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo
->addressModeU
)) |
4839 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo
->addressModeV
)) |
4840 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo
->addressModeW
)) |
4841 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
4842 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo
->compareOp
)) |
4843 S_008F30_FORCE_UNNORMALIZED(pCreateInfo
->unnormalizedCoordinates
? 1 : 0) |
4844 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
4845 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
4846 S_008F30_DISABLE_CUBE_WRAP(0) |
4847 S_008F30_COMPAT_MODE(is_vi
) |
4848 S_008F30_FILTER_MODE(filter_mode
));
4849 sampler
->state
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo
->minLod
, 0, 15), 8)) |
4850 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo
->maxLod
, 0, 15), 8)) |
4851 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
4852 sampler
->state
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo
->mipLodBias
, -16, 16), 8)) |
4853 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo
->magFilter
, max_aniso
)) |
4854 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo
->minFilter
, max_aniso
)) |
4855 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo
->mipmapMode
)) |
4856 S_008F38_MIP_POINT_PRECLAMP(0) |
4857 S_008F38_DISABLE_LSB_CEIL(device
->physical_device
->rad_info
.chip_class
<= GFX8
) |
4858 S_008F38_FILTER_PREC_FIX(1) |
4859 S_008F38_ANISO_OVERRIDE(is_vi
));
4860 sampler
->state
[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4861 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo
->borderColor
)));
4864 VkResult
radv_CreateSampler(
4866 const VkSamplerCreateInfo
* pCreateInfo
,
4867 const VkAllocationCallbacks
* pAllocator
,
4868 VkSampler
* pSampler
)
4870 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4871 struct radv_sampler
*sampler
;
4873 const struct VkSamplerYcbcrConversionInfo
*ycbcr_conversion
=
4874 vk_find_struct_const(pCreateInfo
->pNext
,
4875 SAMPLER_YCBCR_CONVERSION_INFO
);
4877 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO
);
4879 sampler
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*sampler
), 8,
4880 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4882 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4884 radv_init_sampler(device
, sampler
, pCreateInfo
);
4886 sampler
->ycbcr_sampler
= ycbcr_conversion
? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion
->conversion
): NULL
;
4887 *pSampler
= radv_sampler_to_handle(sampler
);
4892 void radv_DestroySampler(
4895 const VkAllocationCallbacks
* pAllocator
)
4897 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4898 RADV_FROM_HANDLE(radv_sampler
, sampler
, _sampler
);
4902 vk_free2(&device
->alloc
, pAllocator
, sampler
);
4905 /* vk_icd.h does not declare this function, so we declare it here to
4906 * suppress Wmissing-prototypes.
4908 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4909 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
);
4911 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4912 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
)
4914 /* For the full details on loader interface versioning, see
4915 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4916 * What follows is a condensed summary, to help you navigate the large and
4917 * confusing official doc.
4919 * - Loader interface v0 is incompatible with later versions. We don't
4922 * - In loader interface v1:
4923 * - The first ICD entrypoint called by the loader is
4924 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4926 * - The ICD must statically expose no other Vulkan symbol unless it is
4927 * linked with -Bsymbolic.
4928 * - Each dispatchable Vulkan handle created by the ICD must be
4929 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4930 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4931 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4932 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4933 * such loader-managed surfaces.
4935 * - Loader interface v2 differs from v1 in:
4936 * - The first ICD entrypoint called by the loader is
4937 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4938 * statically expose this entrypoint.
4940 * - Loader interface v3 differs from v2 in:
4941 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4942 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4943 * because the loader no longer does so.
4945 *pSupportedVersion
= MIN2(*pSupportedVersion
, 4u);
4949 VkResult
radv_GetMemoryFdKHR(VkDevice _device
,
4950 const VkMemoryGetFdInfoKHR
*pGetFdInfo
,
4953 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4954 RADV_FROM_HANDLE(radv_device_memory
, memory
, pGetFdInfo
->memory
);
4956 assert(pGetFdInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR
);
4958 /* At the moment, we support only the below handle types. */
4959 assert(pGetFdInfo
->handleType
==
4960 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
4961 pGetFdInfo
->handleType
==
4962 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
4964 bool ret
= radv_get_memory_fd(device
, memory
, pFD
);
4966 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
4970 VkResult
radv_GetMemoryFdPropertiesKHR(VkDevice _device
,
4971 VkExternalMemoryHandleTypeFlagBits handleType
,
4973 VkMemoryFdPropertiesKHR
*pMemoryFdProperties
)
4975 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4977 switch (handleType
) {
4978 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
:
4979 pMemoryFdProperties
->memoryTypeBits
= (1 << RADV_MEM_TYPE_COUNT
) - 1;
4983 /* The valid usage section for this function says:
4985 * "handleType must not be one of the handle types defined as
4988 * So opaque handle types fall into the default "unsupported" case.
4990 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
4994 static VkResult
radv_import_opaque_fd(struct radv_device
*device
,
4998 uint32_t syncobj_handle
= 0;
4999 int ret
= device
->ws
->import_syncobj(device
->ws
, fd
, &syncobj_handle
);
5001 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5004 device
->ws
->destroy_syncobj(device
->ws
, *syncobj
);
5006 *syncobj
= syncobj_handle
;
5012 static VkResult
radv_import_sync_fd(struct radv_device
*device
,
5016 /* If we create a syncobj we do it locally so that if we have an error, we don't
5017 * leave a syncobj in an undetermined state in the fence. */
5018 uint32_t syncobj_handle
= *syncobj
;
5019 if (!syncobj_handle
) {
5020 int ret
= device
->ws
->create_syncobj(device
->ws
, &syncobj_handle
);
5022 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5027 device
->ws
->signal_syncobj(device
->ws
, syncobj_handle
);
5029 int ret
= device
->ws
->import_syncobj_from_sync_file(device
->ws
, syncobj_handle
, fd
);
5031 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5034 *syncobj
= syncobj_handle
;
5041 VkResult
radv_ImportSemaphoreFdKHR(VkDevice _device
,
5042 const VkImportSemaphoreFdInfoKHR
*pImportSemaphoreFdInfo
)
5044 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5045 RADV_FROM_HANDLE(radv_semaphore
, sem
, pImportSemaphoreFdInfo
->semaphore
);
5046 uint32_t *syncobj_dst
= NULL
;
5048 if (pImportSemaphoreFdInfo
->flags
& VK_SEMAPHORE_IMPORT_TEMPORARY_BIT
) {
5049 syncobj_dst
= &sem
->temp_syncobj
;
5051 syncobj_dst
= &sem
->syncobj
;
5054 switch(pImportSemaphoreFdInfo
->handleType
) {
5055 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5056 return radv_import_opaque_fd(device
, pImportSemaphoreFdInfo
->fd
, syncobj_dst
);
5057 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
5058 return radv_import_sync_fd(device
, pImportSemaphoreFdInfo
->fd
, syncobj_dst
);
5060 unreachable("Unhandled semaphore handle type");
5064 VkResult
radv_GetSemaphoreFdKHR(VkDevice _device
,
5065 const VkSemaphoreGetFdInfoKHR
*pGetFdInfo
,
5068 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5069 RADV_FROM_HANDLE(radv_semaphore
, sem
, pGetFdInfo
->semaphore
);
5071 uint32_t syncobj_handle
;
5073 if (sem
->temp_syncobj
)
5074 syncobj_handle
= sem
->temp_syncobj
;
5076 syncobj_handle
= sem
->syncobj
;
5078 switch(pGetFdInfo
->handleType
) {
5079 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5080 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
5082 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
5083 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
5085 if (sem
->temp_syncobj
) {
5086 close (sem
->temp_syncobj
);
5087 sem
->temp_syncobj
= 0;
5089 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
5094 unreachable("Unhandled semaphore handle type");
5098 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5102 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5103 VkPhysicalDevice physicalDevice
,
5104 const VkPhysicalDeviceExternalSemaphoreInfo
*pExternalSemaphoreInfo
,
5105 VkExternalSemaphoreProperties
*pExternalSemaphoreProperties
)
5107 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
5109 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5110 if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
5111 (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
||
5112 pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
)) {
5113 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
5114 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
5115 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
5116 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
5117 } else if (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
) {
5118 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
5119 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
5120 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
5121 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
5123 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= 0;
5124 pExternalSemaphoreProperties
->compatibleHandleTypes
= 0;
5125 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= 0;
5129 VkResult
radv_ImportFenceFdKHR(VkDevice _device
,
5130 const VkImportFenceFdInfoKHR
*pImportFenceFdInfo
)
5132 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5133 RADV_FROM_HANDLE(radv_fence
, fence
, pImportFenceFdInfo
->fence
);
5134 uint32_t *syncobj_dst
= NULL
;
5137 if (pImportFenceFdInfo
->flags
& VK_FENCE_IMPORT_TEMPORARY_BIT
) {
5138 syncobj_dst
= &fence
->temp_syncobj
;
5140 syncobj_dst
= &fence
->syncobj
;
5143 switch(pImportFenceFdInfo
->handleType
) {
5144 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5145 return radv_import_opaque_fd(device
, pImportFenceFdInfo
->fd
, syncobj_dst
);
5146 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
5147 return radv_import_sync_fd(device
, pImportFenceFdInfo
->fd
, syncobj_dst
);
5149 unreachable("Unhandled fence handle type");
5153 VkResult
radv_GetFenceFdKHR(VkDevice _device
,
5154 const VkFenceGetFdInfoKHR
*pGetFdInfo
,
5157 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5158 RADV_FROM_HANDLE(radv_fence
, fence
, pGetFdInfo
->fence
);
5160 uint32_t syncobj_handle
;
5162 if (fence
->temp_syncobj
)
5163 syncobj_handle
= fence
->temp_syncobj
;
5165 syncobj_handle
= fence
->syncobj
;
5167 switch(pGetFdInfo
->handleType
) {
5168 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5169 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
5171 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
5172 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
5174 if (fence
->temp_syncobj
) {
5175 close (fence
->temp_syncobj
);
5176 fence
->temp_syncobj
= 0;
5178 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
5183 unreachable("Unhandled fence handle type");
5187 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5191 void radv_GetPhysicalDeviceExternalFenceProperties(
5192 VkPhysicalDevice physicalDevice
,
5193 const VkPhysicalDeviceExternalFenceInfo
*pExternalFenceInfo
,
5194 VkExternalFenceProperties
*pExternalFenceProperties
)
5196 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
5198 if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
5199 (pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
||
5200 pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
)) {
5201 pExternalFenceProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
5202 pExternalFenceProperties
->compatibleHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
5203 pExternalFenceProperties
->externalFenceFeatures
= VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT
|
5204 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
5206 pExternalFenceProperties
->exportFromImportedHandleTypes
= 0;
5207 pExternalFenceProperties
->compatibleHandleTypes
= 0;
5208 pExternalFenceProperties
->externalFenceFeatures
= 0;
5213 radv_CreateDebugReportCallbackEXT(VkInstance _instance
,
5214 const VkDebugReportCallbackCreateInfoEXT
* pCreateInfo
,
5215 const VkAllocationCallbacks
* pAllocator
,
5216 VkDebugReportCallbackEXT
* pCallback
)
5218 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
5219 return vk_create_debug_report_callback(&instance
->debug_report_callbacks
,
5220 pCreateInfo
, pAllocator
, &instance
->alloc
,
5225 radv_DestroyDebugReportCallbackEXT(VkInstance _instance
,
5226 VkDebugReportCallbackEXT _callback
,
5227 const VkAllocationCallbacks
* pAllocator
)
5229 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
5230 vk_destroy_debug_report_callback(&instance
->debug_report_callbacks
,
5231 _callback
, pAllocator
, &instance
->alloc
);
5235 radv_DebugReportMessageEXT(VkInstance _instance
,
5236 VkDebugReportFlagsEXT flags
,
5237 VkDebugReportObjectTypeEXT objectType
,
5240 int32_t messageCode
,
5241 const char* pLayerPrefix
,
5242 const char* pMessage
)
5244 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
5245 vk_debug_report(&instance
->debug_report_callbacks
, flags
, objectType
,
5246 object
, location
, messageCode
, pLayerPrefix
, pMessage
);
5250 radv_GetDeviceGroupPeerMemoryFeatures(
5253 uint32_t localDeviceIndex
,
5254 uint32_t remoteDeviceIndex
,
5255 VkPeerMemoryFeatureFlags
* pPeerMemoryFeatures
)
5257 assert(localDeviceIndex
== remoteDeviceIndex
);
5259 *pPeerMemoryFeatures
= VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT
|
5260 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT
|
5261 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT
|
5262 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT
;
5265 static const VkTimeDomainEXT radv_time_domains
[] = {
5266 VK_TIME_DOMAIN_DEVICE_EXT
,
5267 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
,
5268 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
,
5271 VkResult
radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5272 VkPhysicalDevice physicalDevice
,
5273 uint32_t *pTimeDomainCount
,
5274 VkTimeDomainEXT
*pTimeDomains
)
5277 VK_OUTARRAY_MAKE(out
, pTimeDomains
, pTimeDomainCount
);
5279 for (d
= 0; d
< ARRAY_SIZE(radv_time_domains
); d
++) {
5280 vk_outarray_append(&out
, i
) {
5281 *i
= radv_time_domains
[d
];
5285 return vk_outarray_status(&out
);
5289 radv_clock_gettime(clockid_t clock_id
)
5291 struct timespec current
;
5294 ret
= clock_gettime(clock_id
, ¤t
);
5295 if (ret
< 0 && clock_id
== CLOCK_MONOTONIC_RAW
)
5296 ret
= clock_gettime(CLOCK_MONOTONIC
, ¤t
);
5300 return (uint64_t) current
.tv_sec
* 1000000000ULL + current
.tv_nsec
;
5303 VkResult
radv_GetCalibratedTimestampsEXT(
5305 uint32_t timestampCount
,
5306 const VkCalibratedTimestampInfoEXT
*pTimestampInfos
,
5307 uint64_t *pTimestamps
,
5308 uint64_t *pMaxDeviation
)
5310 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5311 uint32_t clock_crystal_freq
= device
->physical_device
->rad_info
.clock_crystal_freq
;
5313 uint64_t begin
, end
;
5314 uint64_t max_clock_period
= 0;
5316 begin
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
5318 for (d
= 0; d
< timestampCount
; d
++) {
5319 switch (pTimestampInfos
[d
].timeDomain
) {
5320 case VK_TIME_DOMAIN_DEVICE_EXT
:
5321 pTimestamps
[d
] = device
->ws
->query_value(device
->ws
,
5323 uint64_t device_period
= DIV_ROUND_UP(1000000, clock_crystal_freq
);
5324 max_clock_period
= MAX2(max_clock_period
, device_period
);
5326 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
:
5327 pTimestamps
[d
] = radv_clock_gettime(CLOCK_MONOTONIC
);
5328 max_clock_period
= MAX2(max_clock_period
, 1);
5331 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
:
5332 pTimestamps
[d
] = begin
;
5340 end
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
5343 * The maximum deviation is the sum of the interval over which we
5344 * perform the sampling and the maximum period of any sampled
5345 * clock. That's because the maximum skew between any two sampled
5346 * clock edges is when the sampled clock with the largest period is
5347 * sampled at the end of that period but right at the beginning of the
5348 * sampling interval and some other clock is sampled right at the
5349 * begining of its sampling period and right at the end of the
5350 * sampling interval. Let's assume the GPU has the longest clock
5351 * period and that the application is sampling GPU and monotonic:
5354 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5355 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5359 * GPU -----_____-----_____-----_____-----_____
5362 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5363 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5365 * Interval <----------------->
5366 * Deviation <-------------------------->
5370 * m = read(monotonic) 2
5373 * We round the sample interval up by one tick to cover sampling error
5374 * in the interval clock
5377 uint64_t sample_interval
= end
- begin
+ 1;
5379 *pMaxDeviation
= sample_interval
+ max_clock_period
;
5384 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
5385 VkPhysicalDevice physicalDevice
,
5386 VkSampleCountFlagBits samples
,
5387 VkMultisamplePropertiesEXT
* pMultisampleProperties
)
5389 if (samples
& (VK_SAMPLE_COUNT_2_BIT
|
5390 VK_SAMPLE_COUNT_4_BIT
|
5391 VK_SAMPLE_COUNT_8_BIT
)) {
5392 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2, 2 };
5394 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 0, 0 };