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488ed0b62250a3698f41b5da872155986798dad4
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "git_sha1.h"
47 #include "gfx9d.h"
48 #include "util/build_id.h"
49 #include "util/debug.h"
50 #include "util/mesa-sha1.h"
51
52 static int
53 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
54 {
55 struct mesa_sha1 ctx;
56 unsigned char sha1[20];
57 unsigned ptr_size = sizeof(void*);
58
59 memset(uuid, 0, VK_UUID_SIZE);
60 _mesa_sha1_init(&ctx);
61
62 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
63 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
64 return -1;
65
66 _mesa_sha1_update(&ctx, &family, sizeof(family));
67 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
68 _mesa_sha1_final(&ctx, sha1);
69
70 memcpy(uuid, sha1, VK_UUID_SIZE);
71 return 0;
72 }
73
74 static void
75 radv_get_driver_uuid(void *uuid)
76 {
77 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
78 }
79
80 static void
81 radv_get_device_uuid(struct radeon_info *info, void *uuid)
82 {
83 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
84 }
85
86 static void
87 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
88 {
89 const char *chip_string;
90 char llvm_string[32] = {};
91
92 switch (family) {
93 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
94 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
95 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
96 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
97 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
98 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
99 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
100 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
101 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
102 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
103 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
104 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
105 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
106 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
107 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
108 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
109 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
110 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
111 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
112 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
113 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
114 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
115 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
116 default: chip_string = "AMD RADV unknown"; break;
117 }
118
119 snprintf(llvm_string, sizeof(llvm_string),
120 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
121 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
122 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
123 }
124
125 static uint64_t
126 radv_get_visible_vram_size(struct radv_physical_device *device)
127 {
128 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
129 }
130
131 static uint64_t
132 radv_get_vram_size(struct radv_physical_device *device)
133 {
134 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
135 }
136
137 static void
138 radv_physical_device_init_mem_types(struct radv_physical_device *device)
139 {
140 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
141 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
142 uint64_t vram_size = radv_get_vram_size(device);
143 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
144 device->memory_properties.memoryHeapCount = 0;
145 if (vram_size > 0) {
146 vram_index = device->memory_properties.memoryHeapCount++;
147 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
148 .size = vram_size,
149 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
150 };
151 }
152 if (visible_vram_size) {
153 visible_vram_index = device->memory_properties.memoryHeapCount++;
154 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
155 .size = visible_vram_size,
156 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
157 };
158 }
159 if (device->rad_info.gart_size > 0) {
160 gart_index = device->memory_properties.memoryHeapCount++;
161 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
162 .size = device->rad_info.gart_size,
163 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
164 };
165 }
166
167 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
168 unsigned type_count = 0;
169 if (vram_index >= 0) {
170 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
171 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
172 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
173 .heapIndex = vram_index,
174 };
175 }
176 if (gart_index >= 0) {
177 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
178 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
179 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
180 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
181 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
182 .heapIndex = gart_index,
183 };
184 }
185 if (visible_vram_index >= 0) {
186 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
187 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
188 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
189 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
190 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
191 .heapIndex = visible_vram_index,
192 };
193 }
194 if (gart_index >= 0) {
195 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
196 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
197 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
198 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
199 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
200 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
201 .heapIndex = gart_index,
202 };
203 }
204 device->memory_properties.memoryTypeCount = type_count;
205 }
206
207 static void
208 radv_handle_env_var_force_family(struct radv_physical_device *device)
209 {
210 const char *family = getenv("RADV_FORCE_FAMILY");
211 unsigned i;
212
213 if (!family)
214 return;
215
216 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
217 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
218 /* Override family and chip_class. */
219 device->rad_info.family = i;
220
221 if (i >= CHIP_VEGA10)
222 device->rad_info.chip_class = GFX9;
223 else if (i >= CHIP_TONGA)
224 device->rad_info.chip_class = VI;
225 else if (i >= CHIP_BONAIRE)
226 device->rad_info.chip_class = CIK;
227 else
228 device->rad_info.chip_class = SI;
229
230 return;
231 }
232 }
233
234 fprintf(stderr, "radv: Unknown family: %s\n", family);
235 exit(1);
236 }
237
238 static VkResult
239 radv_physical_device_init(struct radv_physical_device *device,
240 struct radv_instance *instance,
241 drmDevicePtr drm_device)
242 {
243 const char *path = drm_device->nodes[DRM_NODE_RENDER];
244 VkResult result;
245 drmVersionPtr version;
246 int fd;
247 int master_fd = -1;
248
249 fd = open(path, O_RDWR | O_CLOEXEC);
250 if (fd < 0) {
251 if (instance->debug_flags & RADV_DEBUG_STARTUP)
252 radv_logi("Could not open device '%s'", path);
253
254 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
255 }
256
257 version = drmGetVersion(fd);
258 if (!version) {
259 close(fd);
260
261 if (instance->debug_flags & RADV_DEBUG_STARTUP)
262 radv_logi("Could not get the kernel driver version for device '%s'", path);
263
264 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
265 "failed to get version %s: %m", path);
266 }
267
268 if (strcmp(version->name, "amdgpu")) {
269 drmFreeVersion(version);
270 close(fd);
271
272 if (instance->debug_flags & RADV_DEBUG_STARTUP)
273 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
274
275 return VK_ERROR_INCOMPATIBLE_DRIVER;
276 }
277 drmFreeVersion(version);
278
279 if (instance->debug_flags & RADV_DEBUG_STARTUP)
280 radv_logi("Found compatible device '%s'.", path);
281
282 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
283 device->instance = instance;
284
285 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
286 instance->perftest_flags);
287 if (!device->ws) {
288 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
289 goto fail;
290 }
291
292 if (instance->enabled_extensions.KHR_display) {
293 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
294 if (master_fd >= 0) {
295 uint32_t accel_working = 0;
296 struct drm_amdgpu_info request = {
297 .return_pointer = (uintptr_t)&accel_working,
298 .return_size = sizeof(accel_working),
299 .query = AMDGPU_INFO_ACCEL_WORKING
300 };
301
302 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
303 close(master_fd);
304 master_fd = -1;
305 }
306 }
307 }
308
309 device->master_fd = master_fd;
310 device->local_fd = fd;
311 device->ws->query_info(device->ws, &device->rad_info);
312
313 radv_handle_env_var_force_family(device);
314
315 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
316
317 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
318 device->ws->destroy(device->ws);
319 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
320 "cannot generate UUID");
321 goto fail;
322 }
323
324 /* These flags affect shader compilation. */
325 uint64_t shader_env_flags =
326 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
327 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
328
329 /* The gpu id is already embedded in the uuid so we just pass "radv"
330 * when creating the cache.
331 */
332 char buf[VK_UUID_SIZE * 2 + 1];
333 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
334 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
335
336 if (device->rad_info.chip_class < VI ||
337 device->rad_info.chip_class > GFX9)
338 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
339
340 radv_get_driver_uuid(&device->device_uuid);
341 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
342
343 if (device->rad_info.family == CHIP_STONEY ||
344 device->rad_info.chip_class >= GFX9) {
345 device->has_rbplus = true;
346 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
347 device->rad_info.family == CHIP_VEGA12 ||
348 device->rad_info.family == CHIP_RAVEN ||
349 device->rad_info.family == CHIP_RAVEN2;
350 }
351
352 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
353 * on SI.
354 */
355 device->has_clear_state = device->rad_info.chip_class >= CIK;
356
357 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
358
359 /* Vega10/Raven need a special workaround for a hardware bug. */
360 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
361 device->rad_info.family == CHIP_RAVEN;
362
363 /* Out-of-order primitive rasterization. */
364 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
365 device->rad_info.max_se >= 2;
366 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
367 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
368
369 device->dcc_msaa_allowed =
370 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
371
372 radv_physical_device_init_mem_types(device);
373 radv_fill_device_extension_table(device, &device->supported_extensions);
374
375 device->bus_info = *drm_device->businfo.pci;
376
377 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
378 ac_print_gpu_info(&device->rad_info);
379
380 /* The WSI is structured as a layer on top of the driver, so this has
381 * to be the last part of initialization (at least until we get other
382 * semi-layers).
383 */
384 result = radv_init_wsi(device);
385 if (result != VK_SUCCESS) {
386 device->ws->destroy(device->ws);
387 vk_error(instance, result);
388 goto fail;
389 }
390
391 return VK_SUCCESS;
392
393 fail:
394 close(fd);
395 if (master_fd != -1)
396 close(master_fd);
397 return result;
398 }
399
400 static void
401 radv_physical_device_finish(struct radv_physical_device *device)
402 {
403 radv_finish_wsi(device);
404 device->ws->destroy(device->ws);
405 disk_cache_destroy(device->disk_cache);
406 close(device->local_fd);
407 if (device->master_fd != -1)
408 close(device->master_fd);
409 }
410
411 static void *
412 default_alloc_func(void *pUserData, size_t size, size_t align,
413 VkSystemAllocationScope allocationScope)
414 {
415 return malloc(size);
416 }
417
418 static void *
419 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
420 size_t align, VkSystemAllocationScope allocationScope)
421 {
422 return realloc(pOriginal, size);
423 }
424
425 static void
426 default_free_func(void *pUserData, void *pMemory)
427 {
428 free(pMemory);
429 }
430
431 static const VkAllocationCallbacks default_alloc = {
432 .pUserData = NULL,
433 .pfnAllocation = default_alloc_func,
434 .pfnReallocation = default_realloc_func,
435 .pfnFree = default_free_func,
436 };
437
438 static const struct debug_control radv_debug_options[] = {
439 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
440 {"nodcc", RADV_DEBUG_NO_DCC},
441 {"shaders", RADV_DEBUG_DUMP_SHADERS},
442 {"nocache", RADV_DEBUG_NO_CACHE},
443 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
444 {"nohiz", RADV_DEBUG_NO_HIZ},
445 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
446 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
447 {"allbos", RADV_DEBUG_ALL_BOS},
448 {"noibs", RADV_DEBUG_NO_IBS},
449 {"spirv", RADV_DEBUG_DUMP_SPIRV},
450 {"vmfaults", RADV_DEBUG_VM_FAULTS},
451 {"zerovram", RADV_DEBUG_ZERO_VRAM},
452 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
453 {"nosisched", RADV_DEBUG_NO_SISCHED},
454 {"preoptir", RADV_DEBUG_PREOPTIR},
455 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
456 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
457 {"info", RADV_DEBUG_INFO},
458 {"errors", RADV_DEBUG_ERRORS},
459 {"startup", RADV_DEBUG_STARTUP},
460 {"checkir", RADV_DEBUG_CHECKIR},
461 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
462 {"nobinning", RADV_DEBUG_NOBINNING},
463 {NULL, 0}
464 };
465
466 const char *
467 radv_get_debug_option_name(int id)
468 {
469 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
470 return radv_debug_options[id].string;
471 }
472
473 static const struct debug_control radv_perftest_options[] = {
474 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
475 {"sisched", RADV_PERFTEST_SISCHED},
476 {"localbos", RADV_PERFTEST_LOCAL_BOS},
477 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
478 {NULL, 0}
479 };
480
481 const char *
482 radv_get_perftest_option_name(int id)
483 {
484 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
485 return radv_perftest_options[id].string;
486 }
487
488 static void
489 radv_handle_per_app_options(struct radv_instance *instance,
490 const VkApplicationInfo *info)
491 {
492 const char *name = info ? info->pApplicationName : NULL;
493
494 if (!name)
495 return;
496
497 if (!strcmp(name, "Talos - Linux - 32bit") ||
498 !strcmp(name, "Talos - Linux - 64bit")) {
499 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
500 /* Force enable LLVM sisched for Talos because it looks
501 * safe and it gives few more FPS.
502 */
503 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
504 }
505 } else if (!strcmp(name, "DOOM_VFR")) {
506 /* Work around a Doom VFR game bug */
507 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
508 }
509 }
510
511 static int radv_get_instance_extension_index(const char *name)
512 {
513 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
514 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
515 return i;
516 }
517 return -1;
518 }
519
520
521 VkResult radv_CreateInstance(
522 const VkInstanceCreateInfo* pCreateInfo,
523 const VkAllocationCallbacks* pAllocator,
524 VkInstance* pInstance)
525 {
526 struct radv_instance *instance;
527 VkResult result;
528
529 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
530
531 uint32_t client_version;
532 if (pCreateInfo->pApplicationInfo &&
533 pCreateInfo->pApplicationInfo->apiVersion != 0) {
534 client_version = pCreateInfo->pApplicationInfo->apiVersion;
535 } else {
536 radv_EnumerateInstanceVersion(&client_version);
537 }
538
539 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
540 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
541 if (!instance)
542 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
543
544 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
545
546 if (pAllocator)
547 instance->alloc = *pAllocator;
548 else
549 instance->alloc = default_alloc;
550
551 instance->apiVersion = client_version;
552 instance->physicalDeviceCount = -1;
553
554 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
555 radv_debug_options);
556
557 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
558 radv_perftest_options);
559
560
561 if (instance->debug_flags & RADV_DEBUG_STARTUP)
562 radv_logi("Created an instance");
563
564 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
565 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
566 int index = radv_get_instance_extension_index(ext_name);
567
568 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
569 vk_free2(&default_alloc, pAllocator, instance);
570 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
571 }
572
573 instance->enabled_extensions.extensions[index] = true;
574 }
575
576 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
577 if (result != VK_SUCCESS) {
578 vk_free2(&default_alloc, pAllocator, instance);
579 return vk_error(instance, result);
580 }
581
582 _mesa_locale_init();
583
584 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
585
586 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
587
588 *pInstance = radv_instance_to_handle(instance);
589
590 return VK_SUCCESS;
591 }
592
593 void radv_DestroyInstance(
594 VkInstance _instance,
595 const VkAllocationCallbacks* pAllocator)
596 {
597 RADV_FROM_HANDLE(radv_instance, instance, _instance);
598
599 if (!instance)
600 return;
601
602 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
603 radv_physical_device_finish(instance->physicalDevices + i);
604 }
605
606 VG(VALGRIND_DESTROY_MEMPOOL(instance));
607
608 _mesa_locale_fini();
609
610 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
611
612 vk_free(&instance->alloc, instance);
613 }
614
615 static VkResult
616 radv_enumerate_devices(struct radv_instance *instance)
617 {
618 /* TODO: Check for more devices ? */
619 drmDevicePtr devices[8];
620 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
621 int max_devices;
622
623 instance->physicalDeviceCount = 0;
624
625 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
626
627 if (instance->debug_flags & RADV_DEBUG_STARTUP)
628 radv_logi("Found %d drm nodes", max_devices);
629
630 if (max_devices < 1)
631 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
632
633 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
634 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
635 devices[i]->bustype == DRM_BUS_PCI &&
636 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
637
638 result = radv_physical_device_init(instance->physicalDevices +
639 instance->physicalDeviceCount,
640 instance,
641 devices[i]);
642 if (result == VK_SUCCESS)
643 ++instance->physicalDeviceCount;
644 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
645 break;
646 }
647 }
648 drmFreeDevices(devices, max_devices);
649
650 return result;
651 }
652
653 VkResult radv_EnumeratePhysicalDevices(
654 VkInstance _instance,
655 uint32_t* pPhysicalDeviceCount,
656 VkPhysicalDevice* pPhysicalDevices)
657 {
658 RADV_FROM_HANDLE(radv_instance, instance, _instance);
659 VkResult result;
660
661 if (instance->physicalDeviceCount < 0) {
662 result = radv_enumerate_devices(instance);
663 if (result != VK_SUCCESS &&
664 result != VK_ERROR_INCOMPATIBLE_DRIVER)
665 return result;
666 }
667
668 if (!pPhysicalDevices) {
669 *pPhysicalDeviceCount = instance->physicalDeviceCount;
670 } else {
671 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
672 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
673 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
674 }
675
676 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
677 : VK_SUCCESS;
678 }
679
680 VkResult radv_EnumeratePhysicalDeviceGroups(
681 VkInstance _instance,
682 uint32_t* pPhysicalDeviceGroupCount,
683 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
684 {
685 RADV_FROM_HANDLE(radv_instance, instance, _instance);
686 VkResult result;
687
688 if (instance->physicalDeviceCount < 0) {
689 result = radv_enumerate_devices(instance);
690 if (result != VK_SUCCESS &&
691 result != VK_ERROR_INCOMPATIBLE_DRIVER)
692 return result;
693 }
694
695 if (!pPhysicalDeviceGroupProperties) {
696 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
697 } else {
698 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
699 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
700 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
701 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
702 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
703 }
704 }
705 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
706 : VK_SUCCESS;
707 }
708
709 void radv_GetPhysicalDeviceFeatures(
710 VkPhysicalDevice physicalDevice,
711 VkPhysicalDeviceFeatures* pFeatures)
712 {
713 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
714 memset(pFeatures, 0, sizeof(*pFeatures));
715
716 *pFeatures = (VkPhysicalDeviceFeatures) {
717 .robustBufferAccess = true,
718 .fullDrawIndexUint32 = true,
719 .imageCubeArray = true,
720 .independentBlend = true,
721 .geometryShader = true,
722 .tessellationShader = true,
723 .sampleRateShading = true,
724 .dualSrcBlend = true,
725 .logicOp = true,
726 .multiDrawIndirect = true,
727 .drawIndirectFirstInstance = true,
728 .depthClamp = true,
729 .depthBiasClamp = true,
730 .fillModeNonSolid = true,
731 .depthBounds = true,
732 .wideLines = true,
733 .largePoints = true,
734 .alphaToOne = true,
735 .multiViewport = true,
736 .samplerAnisotropy = true,
737 .textureCompressionETC2 = pdevice->rad_info.chip_class >= GFX9 ||
738 pdevice->rad_info.family == CHIP_STONEY,
739 .textureCompressionASTC_LDR = false,
740 .textureCompressionBC = true,
741 .occlusionQueryPrecise = true,
742 .pipelineStatisticsQuery = true,
743 .vertexPipelineStoresAndAtomics = true,
744 .fragmentStoresAndAtomics = true,
745 .shaderTessellationAndGeometryPointSize = true,
746 .shaderImageGatherExtended = true,
747 .shaderStorageImageExtendedFormats = true,
748 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= VI,
749 .shaderUniformBufferArrayDynamicIndexing = true,
750 .shaderSampledImageArrayDynamicIndexing = true,
751 .shaderStorageBufferArrayDynamicIndexing = true,
752 .shaderStorageImageArrayDynamicIndexing = true,
753 .shaderStorageImageReadWithoutFormat = true,
754 .shaderStorageImageWriteWithoutFormat = true,
755 .shaderClipDistance = true,
756 .shaderCullDistance = true,
757 .shaderFloat64 = true,
758 .shaderInt64 = true,
759 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
760 .sparseBinding = true,
761 .variableMultisampleRate = true,
762 .inheritedQueries = true,
763 };
764 }
765
766 void radv_GetPhysicalDeviceFeatures2(
767 VkPhysicalDevice physicalDevice,
768 VkPhysicalDeviceFeatures2 *pFeatures)
769 {
770 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
771 vk_foreach_struct(ext, pFeatures->pNext) {
772 switch (ext->sType) {
773 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES: {
774 VkPhysicalDeviceVariablePointerFeatures *features = (void *)ext;
775 features->variablePointersStorageBuffer = true;
776 features->variablePointers = true;
777 break;
778 }
779 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
780 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
781 features->multiview = true;
782 features->multiviewGeometryShader = true;
783 features->multiviewTessellationShader = true;
784 break;
785 }
786 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
787 VkPhysicalDeviceShaderDrawParameterFeatures *features =
788 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
789 features->shaderDrawParameters = true;
790 break;
791 }
792 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
793 VkPhysicalDeviceProtectedMemoryFeatures *features =
794 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
795 features->protectedMemory = false;
796 break;
797 }
798 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
799 VkPhysicalDevice16BitStorageFeatures *features =
800 (VkPhysicalDevice16BitStorageFeatures*)ext;
801 bool enabled = pdevice->rad_info.chip_class >= VI;
802 features->storageBuffer16BitAccess = enabled;
803 features->uniformAndStorageBuffer16BitAccess = enabled;
804 features->storagePushConstant16 = enabled;
805 features->storageInputOutput16 = enabled;
806 break;
807 }
808 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
809 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
810 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
811 features->samplerYcbcrConversion = false;
812 break;
813 }
814 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
815 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
816 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
817 features->shaderInputAttachmentArrayDynamicIndexing = true;
818 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
819 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
820 features->shaderUniformBufferArrayNonUniformIndexing = false;
821 features->shaderSampledImageArrayNonUniformIndexing = false;
822 features->shaderStorageBufferArrayNonUniformIndexing = false;
823 features->shaderStorageImageArrayNonUniformIndexing = false;
824 features->shaderInputAttachmentArrayNonUniformIndexing = false;
825 features->shaderUniformTexelBufferArrayNonUniformIndexing = false;
826 features->shaderStorageTexelBufferArrayNonUniformIndexing = false;
827 features->descriptorBindingUniformBufferUpdateAfterBind = true;
828 features->descriptorBindingSampledImageUpdateAfterBind = true;
829 features->descriptorBindingStorageImageUpdateAfterBind = true;
830 features->descriptorBindingStorageBufferUpdateAfterBind = true;
831 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
832 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
833 features->descriptorBindingUpdateUnusedWhilePending = true;
834 features->descriptorBindingPartiallyBound = true;
835 features->descriptorBindingVariableDescriptorCount = true;
836 features->runtimeDescriptorArray = true;
837 break;
838 }
839 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
840 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
841 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
842 features->conditionalRendering = true;
843 features->inheritedConditionalRendering = false;
844 break;
845 }
846 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
847 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
848 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
849 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
850 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
851 break;
852 }
853 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
854 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
855 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
856 features->transformFeedback = true;
857 features->geometryStreams = true;
858 break;
859 }
860 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
861 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
862 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
863 features->scalarBlockLayout = pdevice->rad_info.chip_class >= CIK;
864 break;
865 }
866 default:
867 break;
868 }
869 }
870 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
871 }
872
873 void radv_GetPhysicalDeviceProperties(
874 VkPhysicalDevice physicalDevice,
875 VkPhysicalDeviceProperties* pProperties)
876 {
877 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
878 VkSampleCountFlags sample_counts = 0xf;
879
880 /* make sure that the entire descriptor set is addressable with a signed
881 * 32-bit int. So the sum of all limits scaled by descriptor size has to
882 * be at most 2 GiB. the combined image & samples object count as one of
883 * both. This limit is for the pipeline layout, not for the set layout, but
884 * there is no set limit, so we just set a pipeline limit. I don't think
885 * any app is going to hit this soon. */
886 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
887 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
888 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
889 32 /* sampler, largest when combined with image */ +
890 64 /* sampled image */ +
891 64 /* storage image */);
892
893 VkPhysicalDeviceLimits limits = {
894 .maxImageDimension1D = (1 << 14),
895 .maxImageDimension2D = (1 << 14),
896 .maxImageDimension3D = (1 << 11),
897 .maxImageDimensionCube = (1 << 14),
898 .maxImageArrayLayers = (1 << 11),
899 .maxTexelBufferElements = 128 * 1024 * 1024,
900 .maxUniformBufferRange = UINT32_MAX,
901 .maxStorageBufferRange = UINT32_MAX,
902 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
903 .maxMemoryAllocationCount = UINT32_MAX,
904 .maxSamplerAllocationCount = 64 * 1024,
905 .bufferImageGranularity = 64, /* A cache line */
906 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
907 .maxBoundDescriptorSets = MAX_SETS,
908 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
909 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
910 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
911 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
912 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
913 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
914 .maxPerStageResources = max_descriptor_set_size,
915 .maxDescriptorSetSamplers = max_descriptor_set_size,
916 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
917 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
918 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
919 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
920 .maxDescriptorSetSampledImages = max_descriptor_set_size,
921 .maxDescriptorSetStorageImages = max_descriptor_set_size,
922 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
923 .maxVertexInputAttributes = 32,
924 .maxVertexInputBindings = 32,
925 .maxVertexInputAttributeOffset = 2047,
926 .maxVertexInputBindingStride = 2048,
927 .maxVertexOutputComponents = 128,
928 .maxTessellationGenerationLevel = 64,
929 .maxTessellationPatchSize = 32,
930 .maxTessellationControlPerVertexInputComponents = 128,
931 .maxTessellationControlPerVertexOutputComponents = 128,
932 .maxTessellationControlPerPatchOutputComponents = 120,
933 .maxTessellationControlTotalOutputComponents = 4096,
934 .maxTessellationEvaluationInputComponents = 128,
935 .maxTessellationEvaluationOutputComponents = 128,
936 .maxGeometryShaderInvocations = 127,
937 .maxGeometryInputComponents = 64,
938 .maxGeometryOutputComponents = 128,
939 .maxGeometryOutputVertices = 256,
940 .maxGeometryTotalOutputComponents = 1024,
941 .maxFragmentInputComponents = 128,
942 .maxFragmentOutputAttachments = 8,
943 .maxFragmentDualSrcAttachments = 1,
944 .maxFragmentCombinedOutputResources = 8,
945 .maxComputeSharedMemorySize = 32768,
946 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
947 .maxComputeWorkGroupInvocations = 2048,
948 .maxComputeWorkGroupSize = {
949 2048,
950 2048,
951 2048
952 },
953 .subPixelPrecisionBits = 8,
954 .subTexelPrecisionBits = 8,
955 .mipmapPrecisionBits = 8,
956 .maxDrawIndexedIndexValue = UINT32_MAX,
957 .maxDrawIndirectCount = UINT32_MAX,
958 .maxSamplerLodBias = 16,
959 .maxSamplerAnisotropy = 16,
960 .maxViewports = MAX_VIEWPORTS,
961 .maxViewportDimensions = { (1 << 14), (1 << 14) },
962 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
963 .viewportSubPixelBits = 8,
964 .minMemoryMapAlignment = 4096, /* A page */
965 .minTexelBufferOffsetAlignment = 1,
966 .minUniformBufferOffsetAlignment = 4,
967 .minStorageBufferOffsetAlignment = 4,
968 .minTexelOffset = -32,
969 .maxTexelOffset = 31,
970 .minTexelGatherOffset = -32,
971 .maxTexelGatherOffset = 31,
972 .minInterpolationOffset = -2,
973 .maxInterpolationOffset = 2,
974 .subPixelInterpolationOffsetBits = 8,
975 .maxFramebufferWidth = (1 << 14),
976 .maxFramebufferHeight = (1 << 14),
977 .maxFramebufferLayers = (1 << 10),
978 .framebufferColorSampleCounts = sample_counts,
979 .framebufferDepthSampleCounts = sample_counts,
980 .framebufferStencilSampleCounts = sample_counts,
981 .framebufferNoAttachmentsSampleCounts = sample_counts,
982 .maxColorAttachments = MAX_RTS,
983 .sampledImageColorSampleCounts = sample_counts,
984 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
985 .sampledImageDepthSampleCounts = sample_counts,
986 .sampledImageStencilSampleCounts = sample_counts,
987 .storageImageSampleCounts = pdevice->rad_info.chip_class >= VI ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
988 .maxSampleMaskWords = 1,
989 .timestampComputeAndGraphics = true,
990 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
991 .maxClipDistances = 8,
992 .maxCullDistances = 8,
993 .maxCombinedClipAndCullDistances = 8,
994 .discreteQueuePriorities = 2,
995 .pointSizeRange = { 0.125, 255.875 },
996 .lineWidthRange = { 0.0, 7.9921875 },
997 .pointSizeGranularity = (1.0 / 8.0),
998 .lineWidthGranularity = (1.0 / 128.0),
999 .strictLines = false, /* FINISHME */
1000 .standardSampleLocations = true,
1001 .optimalBufferCopyOffsetAlignment = 128,
1002 .optimalBufferCopyRowPitchAlignment = 128,
1003 .nonCoherentAtomSize = 64,
1004 };
1005
1006 *pProperties = (VkPhysicalDeviceProperties) {
1007 .apiVersion = radv_physical_device_api_version(pdevice),
1008 .driverVersion = vk_get_driver_version(),
1009 .vendorID = ATI_VENDOR_ID,
1010 .deviceID = pdevice->rad_info.pci_id,
1011 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1012 .limits = limits,
1013 .sparseProperties = {0},
1014 };
1015
1016 strcpy(pProperties->deviceName, pdevice->name);
1017 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1018 }
1019
1020 void radv_GetPhysicalDeviceProperties2(
1021 VkPhysicalDevice physicalDevice,
1022 VkPhysicalDeviceProperties2 *pProperties)
1023 {
1024 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1025 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1026
1027 vk_foreach_struct(ext, pProperties->pNext) {
1028 switch (ext->sType) {
1029 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1030 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1031 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1032 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1033 break;
1034 }
1035 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1036 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1037 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1038 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1039 properties->deviceLUIDValid = false;
1040 break;
1041 }
1042 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1043 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1044 properties->maxMultiviewViewCount = MAX_VIEWS;
1045 properties->maxMultiviewInstanceIndex = INT_MAX;
1046 break;
1047 }
1048 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1049 VkPhysicalDevicePointClippingProperties *properties =
1050 (VkPhysicalDevicePointClippingProperties*)ext;
1051 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1052 break;
1053 }
1054 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1055 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1056 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1057 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1058 break;
1059 }
1060 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1061 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1062 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1063 properties->minImportedHostPointerAlignment = 4096;
1064 break;
1065 }
1066 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1067 VkPhysicalDeviceSubgroupProperties *properties =
1068 (VkPhysicalDeviceSubgroupProperties*)ext;
1069 properties->subgroupSize = 64;
1070 properties->supportedStages = VK_SHADER_STAGE_ALL;
1071 properties->supportedOperations =
1072 VK_SUBGROUP_FEATURE_BASIC_BIT |
1073 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1074 VK_SUBGROUP_FEATURE_QUAD_BIT |
1075 VK_SUBGROUP_FEATURE_VOTE_BIT;
1076 if (pdevice->rad_info.chip_class >= VI) {
1077 properties->supportedOperations |=
1078 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1079 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1080 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1081 }
1082 properties->quadOperationsInAllStages = true;
1083 break;
1084 }
1085 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1086 VkPhysicalDeviceMaintenance3Properties *properties =
1087 (VkPhysicalDeviceMaintenance3Properties*)ext;
1088 /* Make sure everything is addressable by a signed 32-bit int, and
1089 * our largest descriptors are 96 bytes. */
1090 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1091 /* Our buffer size fields allow only this much */
1092 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1093 break;
1094 }
1095 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1096 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1097 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1098 /* GFX6-8 only support single channel min/max filter. */
1099 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1100 properties->filterMinmaxSingleComponentFormats = true;
1101 break;
1102 }
1103 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1104 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1105 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1106
1107 /* Shader engines. */
1108 properties->shaderEngineCount =
1109 pdevice->rad_info.max_se;
1110 properties->shaderArraysPerEngineCount =
1111 pdevice->rad_info.max_sh_per_se;
1112 properties->computeUnitsPerShaderArray =
1113 pdevice->rad_info.num_good_cu_per_sh;
1114 properties->simdPerComputeUnit = 4;
1115 properties->wavefrontsPerSimd =
1116 pdevice->rad_info.family == CHIP_TONGA ||
1117 pdevice->rad_info.family == CHIP_ICELAND ||
1118 pdevice->rad_info.family == CHIP_POLARIS10 ||
1119 pdevice->rad_info.family == CHIP_POLARIS11 ||
1120 pdevice->rad_info.family == CHIP_POLARIS12 ||
1121 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1122 properties->wavefrontSize = 64;
1123
1124 /* SGPR. */
1125 properties->sgprsPerSimd =
1126 radv_get_num_physical_sgprs(pdevice);
1127 properties->minSgprAllocation =
1128 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1129 properties->maxSgprAllocation =
1130 pdevice->rad_info.family == CHIP_TONGA ||
1131 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1132 properties->sgprAllocationGranularity =
1133 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1134
1135 /* VGPR. */
1136 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1137 properties->minVgprAllocation = 4;
1138 properties->maxVgprAllocation = 256;
1139 properties->vgprAllocationGranularity = 4;
1140 break;
1141 }
1142 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1143 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1144 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1145 properties->maxVertexAttribDivisor = UINT32_MAX;
1146 break;
1147 }
1148 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1149 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1150 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1151 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1152 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1153 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1154 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1155 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1156 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1157 properties->robustBufferAccessUpdateAfterBind = false;
1158 properties->quadDivergentImplicitLod = false;
1159
1160 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1161 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1162 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1163 32 /* sampler, largest when combined with image */ +
1164 64 /* sampled image */ +
1165 64 /* storage image */);
1166 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1167 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1168 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1169 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1170 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1171 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1172 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1173 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1174 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1175 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1176 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1177 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1178 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1179 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1180 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1181 break;
1182 }
1183 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1184 VkPhysicalDeviceProtectedMemoryProperties *properties =
1185 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1186 properties->protectedNoFault = false;
1187 break;
1188 }
1189 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1190 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1191 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1192 properties->primitiveOverestimationSize = 0;
1193 properties->maxExtraPrimitiveOverestimationSize = 0;
1194 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1195 properties->primitiveUnderestimation = VK_FALSE;
1196 properties->conservativePointAndLineRasterization = VK_FALSE;
1197 properties->degenerateTrianglesRasterized = VK_FALSE;
1198 properties->degenerateLinesRasterized = VK_FALSE;
1199 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1200 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1201 break;
1202 }
1203 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1204 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1205 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1206 properties->pciDomain = pdevice->bus_info.domain;
1207 properties->pciBus = pdevice->bus_info.bus;
1208 properties->pciDevice = pdevice->bus_info.dev;
1209 properties->pciFunction = pdevice->bus_info.func;
1210 break;
1211 }
1212 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1213 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1214 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1215
1216 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1217 memset(driver_props->driverName, 0, VK_MAX_DRIVER_NAME_SIZE_KHR);
1218 strcpy(driver_props->driverName, "radv");
1219
1220 memset(driver_props->driverInfo, 0, VK_MAX_DRIVER_INFO_SIZE_KHR);
1221 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1222 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1223 " (LLVM %d.%d.%d)",
1224 (HAVE_LLVM >> 8) & 0xff, HAVE_LLVM & 0xff,
1225 MESA_LLVM_VERSION_PATCH);
1226
1227 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1228 .major = 1,
1229 .minor = 1,
1230 .subminor = 2,
1231 .patch = 0,
1232 };
1233 break;
1234 }
1235 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1236 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1237 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1238 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1239 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1240 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1241 properties->maxTransformFeedbackStreamDataSize = 512;
1242 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1243 properties->maxTransformFeedbackBufferDataStride = 512;
1244 properties->transformFeedbackQueries = true;
1245 properties->transformFeedbackStreamsLinesTriangles = false;
1246 properties->transformFeedbackRasterizationStreamSelect = false;
1247 properties->transformFeedbackDraw = true;
1248 break;
1249 }
1250 default:
1251 break;
1252 }
1253 }
1254 }
1255
1256 static void radv_get_physical_device_queue_family_properties(
1257 struct radv_physical_device* pdevice,
1258 uint32_t* pCount,
1259 VkQueueFamilyProperties** pQueueFamilyProperties)
1260 {
1261 int num_queue_families = 1;
1262 int idx;
1263 if (pdevice->rad_info.num_compute_rings > 0 &&
1264 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1265 num_queue_families++;
1266
1267 if (pQueueFamilyProperties == NULL) {
1268 *pCount = num_queue_families;
1269 return;
1270 }
1271
1272 if (!*pCount)
1273 return;
1274
1275 idx = 0;
1276 if (*pCount >= 1) {
1277 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1278 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1279 VK_QUEUE_COMPUTE_BIT |
1280 VK_QUEUE_TRANSFER_BIT |
1281 VK_QUEUE_SPARSE_BINDING_BIT,
1282 .queueCount = 1,
1283 .timestampValidBits = 64,
1284 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1285 };
1286 idx++;
1287 }
1288
1289 if (pdevice->rad_info.num_compute_rings > 0 &&
1290 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1291 if (*pCount > idx) {
1292 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1293 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1294 VK_QUEUE_TRANSFER_BIT |
1295 VK_QUEUE_SPARSE_BINDING_BIT,
1296 .queueCount = pdevice->rad_info.num_compute_rings,
1297 .timestampValidBits = 64,
1298 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1299 };
1300 idx++;
1301 }
1302 }
1303 *pCount = idx;
1304 }
1305
1306 void radv_GetPhysicalDeviceQueueFamilyProperties(
1307 VkPhysicalDevice physicalDevice,
1308 uint32_t* pCount,
1309 VkQueueFamilyProperties* pQueueFamilyProperties)
1310 {
1311 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1312 if (!pQueueFamilyProperties) {
1313 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1314 return;
1315 }
1316 VkQueueFamilyProperties *properties[] = {
1317 pQueueFamilyProperties + 0,
1318 pQueueFamilyProperties + 1,
1319 pQueueFamilyProperties + 2,
1320 };
1321 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1322 assert(*pCount <= 3);
1323 }
1324
1325 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1326 VkPhysicalDevice physicalDevice,
1327 uint32_t* pCount,
1328 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1329 {
1330 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1331 if (!pQueueFamilyProperties) {
1332 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1333 return;
1334 }
1335 VkQueueFamilyProperties *properties[] = {
1336 &pQueueFamilyProperties[0].queueFamilyProperties,
1337 &pQueueFamilyProperties[1].queueFamilyProperties,
1338 &pQueueFamilyProperties[2].queueFamilyProperties,
1339 };
1340 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1341 assert(*pCount <= 3);
1342 }
1343
1344 void radv_GetPhysicalDeviceMemoryProperties(
1345 VkPhysicalDevice physicalDevice,
1346 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1347 {
1348 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1349
1350 *pMemoryProperties = physical_device->memory_properties;
1351 }
1352
1353 static void
1354 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1355 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1356 {
1357 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1358 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1359 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1360 uint64_t vram_size = radv_get_vram_size(device);
1361 uint64_t gtt_size = device->rad_info.gart_size;
1362 uint64_t heap_budget, heap_usage;
1363
1364 /* For all memory heaps, the computation of budget is as follow:
1365 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1366 *
1367 * The Vulkan spec 1.1.97 says that the budget should include any
1368 * currently allocated device memory.
1369 *
1370 * Note that the application heap usages are not really accurate (eg.
1371 * in presence of shared buffers).
1372 */
1373 if (vram_size) {
1374 heap_usage = device->ws->query_value(device->ws,
1375 RADEON_ALLOCATED_VRAM);
1376
1377 heap_budget = vram_size -
1378 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1379 heap_usage;
1380
1381 memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM] = heap_budget;
1382 memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM] = heap_usage;
1383 }
1384
1385 if (visible_vram_size) {
1386 heap_usage = device->ws->query_value(device->ws,
1387 RADEON_ALLOCATED_VRAM_VIS);
1388
1389 heap_budget = visible_vram_size -
1390 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1391 heap_usage;
1392
1393 memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_budget;
1394 memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_usage;
1395 }
1396
1397 if (gtt_size) {
1398 heap_usage = device->ws->query_value(device->ws,
1399 RADEON_ALLOCATED_GTT);
1400
1401 heap_budget = gtt_size -
1402 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1403 heap_usage;
1404
1405 memoryBudget->heapBudget[RADV_MEM_HEAP_GTT] = heap_budget;
1406 memoryBudget->heapUsage[RADV_MEM_HEAP_GTT] = heap_usage;
1407 }
1408
1409 /* The heapBudget and heapUsage values must be zero for array elements
1410 * greater than or equal to
1411 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1412 */
1413 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1414 memoryBudget->heapBudget[i] = 0;
1415 memoryBudget->heapUsage[i] = 0;
1416 }
1417 }
1418
1419 void radv_GetPhysicalDeviceMemoryProperties2(
1420 VkPhysicalDevice physicalDevice,
1421 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1422 {
1423 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1424 &pMemoryProperties->memoryProperties);
1425
1426 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1427 vk_find_struct(pMemoryProperties->pNext,
1428 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1429 if (memory_budget)
1430 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1431 }
1432
1433 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1434 VkDevice _device,
1435 VkExternalMemoryHandleTypeFlagBits handleType,
1436 const void *pHostPointer,
1437 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1438 {
1439 RADV_FROM_HANDLE(radv_device, device, _device);
1440
1441 switch (handleType)
1442 {
1443 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1444 const struct radv_physical_device *physical_device = device->physical_device;
1445 uint32_t memoryTypeBits = 0;
1446 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1447 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1448 memoryTypeBits = (1 << i);
1449 break;
1450 }
1451 }
1452 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1453 return VK_SUCCESS;
1454 }
1455 default:
1456 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1457 }
1458 }
1459
1460 static enum radeon_ctx_priority
1461 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1462 {
1463 /* Default to MEDIUM when a specific global priority isn't requested */
1464 if (!pObj)
1465 return RADEON_CTX_PRIORITY_MEDIUM;
1466
1467 switch(pObj->globalPriority) {
1468 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1469 return RADEON_CTX_PRIORITY_REALTIME;
1470 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1471 return RADEON_CTX_PRIORITY_HIGH;
1472 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1473 return RADEON_CTX_PRIORITY_MEDIUM;
1474 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1475 return RADEON_CTX_PRIORITY_LOW;
1476 default:
1477 unreachable("Illegal global priority value");
1478 return RADEON_CTX_PRIORITY_INVALID;
1479 }
1480 }
1481
1482 static int
1483 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1484 uint32_t queue_family_index, int idx,
1485 VkDeviceQueueCreateFlags flags,
1486 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1487 {
1488 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1489 queue->device = device;
1490 queue->queue_family_index = queue_family_index;
1491 queue->queue_idx = idx;
1492 queue->priority = radv_get_queue_global_priority(global_priority);
1493 queue->flags = flags;
1494
1495 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1496 if (!queue->hw_ctx)
1497 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1498
1499 return VK_SUCCESS;
1500 }
1501
1502 static void
1503 radv_queue_finish(struct radv_queue *queue)
1504 {
1505 if (queue->hw_ctx)
1506 queue->device->ws->ctx_destroy(queue->hw_ctx);
1507
1508 if (queue->initial_full_flush_preamble_cs)
1509 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1510 if (queue->initial_preamble_cs)
1511 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1512 if (queue->continue_preamble_cs)
1513 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1514 if (queue->descriptor_bo)
1515 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1516 if (queue->scratch_bo)
1517 queue->device->ws->buffer_destroy(queue->scratch_bo);
1518 if (queue->esgs_ring_bo)
1519 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1520 if (queue->gsvs_ring_bo)
1521 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1522 if (queue->tess_rings_bo)
1523 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1524 if (queue->compute_scratch_bo)
1525 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1526 }
1527
1528 static void
1529 radv_bo_list_init(struct radv_bo_list *bo_list)
1530 {
1531 pthread_mutex_init(&bo_list->mutex, NULL);
1532 bo_list->list.count = bo_list->capacity = 0;
1533 bo_list->list.bos = NULL;
1534 }
1535
1536 static void
1537 radv_bo_list_finish(struct radv_bo_list *bo_list)
1538 {
1539 free(bo_list->list.bos);
1540 pthread_mutex_destroy(&bo_list->mutex);
1541 }
1542
1543 static VkResult radv_bo_list_add(struct radv_device *device,
1544 struct radeon_winsys_bo *bo)
1545 {
1546 struct radv_bo_list *bo_list = &device->bo_list;
1547
1548 if (unlikely(!device->use_global_bo_list))
1549 return VK_SUCCESS;
1550
1551 pthread_mutex_lock(&bo_list->mutex);
1552 if (bo_list->list.count == bo_list->capacity) {
1553 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1554 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1555
1556 if (!data) {
1557 pthread_mutex_unlock(&bo_list->mutex);
1558 return VK_ERROR_OUT_OF_HOST_MEMORY;
1559 }
1560
1561 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1562 bo_list->capacity = capacity;
1563 }
1564
1565 bo_list->list.bos[bo_list->list.count++] = bo;
1566 pthread_mutex_unlock(&bo_list->mutex);
1567 return VK_SUCCESS;
1568 }
1569
1570 static void radv_bo_list_remove(struct radv_device *device,
1571 struct radeon_winsys_bo *bo)
1572 {
1573 struct radv_bo_list *bo_list = &device->bo_list;
1574
1575 if (unlikely(!device->use_global_bo_list))
1576 return;
1577
1578 pthread_mutex_lock(&bo_list->mutex);
1579 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1580 if (bo_list->list.bos[i] == bo) {
1581 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1582 --bo_list->list.count;
1583 break;
1584 }
1585 }
1586 pthread_mutex_unlock(&bo_list->mutex);
1587 }
1588
1589 static void
1590 radv_device_init_gs_info(struct radv_device *device)
1591 {
1592 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1593 device->physical_device->rad_info.family);
1594 }
1595
1596 static int radv_get_device_extension_index(const char *name)
1597 {
1598 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1599 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1600 return i;
1601 }
1602 return -1;
1603 }
1604
1605 static int
1606 radv_get_int_debug_option(const char *name, int default_value)
1607 {
1608 const char *str;
1609 int result;
1610
1611 str = getenv(name);
1612 if (!str) {
1613 result = default_value;
1614 } else {
1615 char *endptr;
1616
1617 result = strtol(str, &endptr, 0);
1618 if (str == endptr) {
1619 /* No digits founs. */
1620 result = default_value;
1621 }
1622 }
1623
1624 return result;
1625 }
1626
1627 VkResult radv_CreateDevice(
1628 VkPhysicalDevice physicalDevice,
1629 const VkDeviceCreateInfo* pCreateInfo,
1630 const VkAllocationCallbacks* pAllocator,
1631 VkDevice* pDevice)
1632 {
1633 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1634 VkResult result;
1635 struct radv_device *device;
1636
1637 bool keep_shader_info = false;
1638
1639 /* Check enabled features */
1640 if (pCreateInfo->pEnabledFeatures) {
1641 VkPhysicalDeviceFeatures supported_features;
1642 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1643 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1644 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1645 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1646 for (uint32_t i = 0; i < num_features; i++) {
1647 if (enabled_feature[i] && !supported_feature[i])
1648 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1649 }
1650 }
1651
1652 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1653 sizeof(*device), 8,
1654 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1655 if (!device)
1656 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1657
1658 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1659 device->instance = physical_device->instance;
1660 device->physical_device = physical_device;
1661
1662 device->ws = physical_device->ws;
1663 if (pAllocator)
1664 device->alloc = *pAllocator;
1665 else
1666 device->alloc = physical_device->instance->alloc;
1667
1668 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1669 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1670 int index = radv_get_device_extension_index(ext_name);
1671 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1672 vk_free(&device->alloc, device);
1673 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1674 }
1675
1676 device->enabled_extensions.extensions[index] = true;
1677 }
1678
1679 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1680
1681 /* With update after bind we can't attach bo's to the command buffer
1682 * from the descriptor set anymore, so we have to use a global BO list.
1683 */
1684 device->use_global_bo_list =
1685 device->enabled_extensions.EXT_descriptor_indexing;
1686
1687 mtx_init(&device->shader_slab_mutex, mtx_plain);
1688 list_inithead(&device->shader_slabs);
1689
1690 radv_bo_list_init(&device->bo_list);
1691
1692 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1693 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1694 uint32_t qfi = queue_create->queueFamilyIndex;
1695 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1696 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1697
1698 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1699
1700 device->queues[qfi] = vk_alloc(&device->alloc,
1701 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1702 if (!device->queues[qfi]) {
1703 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1704 goto fail;
1705 }
1706
1707 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1708
1709 device->queue_count[qfi] = queue_create->queueCount;
1710
1711 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1712 result = radv_queue_init(device, &device->queues[qfi][q],
1713 qfi, q, queue_create->flags,
1714 global_priority);
1715 if (result != VK_SUCCESS)
1716 goto fail;
1717 }
1718 }
1719
1720 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1721 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1722
1723 /* Disabled and not implemented for now. */
1724 device->dfsm_allowed = device->pbb_allowed &&
1725 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1726 device->physical_device->rad_info.family == CHIP_RAVEN2);
1727
1728 #ifdef ANDROID
1729 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1730 #endif
1731
1732 /* The maximum number of scratch waves. Scratch space isn't divided
1733 * evenly between CUs. The number is only a function of the number of CUs.
1734 * We can decrease the constant to decrease the scratch buffer size.
1735 *
1736 * sctx->scratch_waves must be >= the maximum possible size of
1737 * 1 threadgroup, so that the hw doesn't hang from being unable
1738 * to start any.
1739 *
1740 * The recommended value is 4 per CU at most. Higher numbers don't
1741 * bring much benefit, but they still occupy chip resources (think
1742 * async compute). I've seen ~2% performance difference between 4 and 32.
1743 */
1744 uint32_t max_threads_per_block = 2048;
1745 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1746 max_threads_per_block / 64);
1747
1748 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1749
1750 if (device->physical_device->rad_info.chip_class >= CIK) {
1751 /* If the KMD allows it (there is a KMD hw register for it),
1752 * allow launching waves out-of-order.
1753 */
1754 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1755 }
1756
1757 radv_device_init_gs_info(device);
1758
1759 device->tess_offchip_block_dw_size =
1760 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1761 device->has_distributed_tess =
1762 device->physical_device->rad_info.chip_class >= VI &&
1763 device->physical_device->rad_info.max_se >= 2;
1764
1765 if (getenv("RADV_TRACE_FILE")) {
1766 const char *filename = getenv("RADV_TRACE_FILE");
1767
1768 keep_shader_info = true;
1769
1770 if (!radv_init_trace(device))
1771 goto fail;
1772
1773 fprintf(stderr, "*****************************************************************************\n");
1774 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1775 fprintf(stderr, "*****************************************************************************\n");
1776
1777 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1778 radv_dump_enabled_options(device, stderr);
1779 }
1780
1781 device->keep_shader_info = keep_shader_info;
1782
1783 result = radv_device_init_meta(device);
1784 if (result != VK_SUCCESS)
1785 goto fail;
1786
1787 radv_device_init_msaa(device);
1788
1789 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1790 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1791 switch (family) {
1792 case RADV_QUEUE_GENERAL:
1793 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1794 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1795 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1796 break;
1797 case RADV_QUEUE_COMPUTE:
1798 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1799 radeon_emit(device->empty_cs[family], 0);
1800 break;
1801 }
1802 device->ws->cs_finalize(device->empty_cs[family]);
1803 }
1804
1805 if (device->physical_device->rad_info.chip_class >= CIK)
1806 cik_create_gfx_config(device);
1807
1808 VkPipelineCacheCreateInfo ci;
1809 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1810 ci.pNext = NULL;
1811 ci.flags = 0;
1812 ci.pInitialData = NULL;
1813 ci.initialDataSize = 0;
1814 VkPipelineCache pc;
1815 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1816 &ci, NULL, &pc);
1817 if (result != VK_SUCCESS)
1818 goto fail_meta;
1819
1820 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1821
1822 device->force_aniso =
1823 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
1824 if (device->force_aniso >= 0) {
1825 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
1826 1 << util_logbase2(device->force_aniso));
1827 }
1828
1829 *pDevice = radv_device_to_handle(device);
1830 return VK_SUCCESS;
1831
1832 fail_meta:
1833 radv_device_finish_meta(device);
1834 fail:
1835 radv_bo_list_finish(&device->bo_list);
1836
1837 if (device->trace_bo)
1838 device->ws->buffer_destroy(device->trace_bo);
1839
1840 if (device->gfx_init)
1841 device->ws->buffer_destroy(device->gfx_init);
1842
1843 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1844 for (unsigned q = 0; q < device->queue_count[i]; q++)
1845 radv_queue_finish(&device->queues[i][q]);
1846 if (device->queue_count[i])
1847 vk_free(&device->alloc, device->queues[i]);
1848 }
1849
1850 vk_free(&device->alloc, device);
1851 return result;
1852 }
1853
1854 void radv_DestroyDevice(
1855 VkDevice _device,
1856 const VkAllocationCallbacks* pAllocator)
1857 {
1858 RADV_FROM_HANDLE(radv_device, device, _device);
1859
1860 if (!device)
1861 return;
1862
1863 if (device->trace_bo)
1864 device->ws->buffer_destroy(device->trace_bo);
1865
1866 if (device->gfx_init)
1867 device->ws->buffer_destroy(device->gfx_init);
1868
1869 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1870 for (unsigned q = 0; q < device->queue_count[i]; q++)
1871 radv_queue_finish(&device->queues[i][q]);
1872 if (device->queue_count[i])
1873 vk_free(&device->alloc, device->queues[i]);
1874 if (device->empty_cs[i])
1875 device->ws->cs_destroy(device->empty_cs[i]);
1876 }
1877 radv_device_finish_meta(device);
1878
1879 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1880 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1881
1882 radv_destroy_shader_slabs(device);
1883
1884 radv_bo_list_finish(&device->bo_list);
1885 vk_free(&device->alloc, device);
1886 }
1887
1888 VkResult radv_EnumerateInstanceLayerProperties(
1889 uint32_t* pPropertyCount,
1890 VkLayerProperties* pProperties)
1891 {
1892 if (pProperties == NULL) {
1893 *pPropertyCount = 0;
1894 return VK_SUCCESS;
1895 }
1896
1897 /* None supported at this time */
1898 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1899 }
1900
1901 VkResult radv_EnumerateDeviceLayerProperties(
1902 VkPhysicalDevice physicalDevice,
1903 uint32_t* pPropertyCount,
1904 VkLayerProperties* pProperties)
1905 {
1906 if (pProperties == NULL) {
1907 *pPropertyCount = 0;
1908 return VK_SUCCESS;
1909 }
1910
1911 /* None supported at this time */
1912 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1913 }
1914
1915 void radv_GetDeviceQueue2(
1916 VkDevice _device,
1917 const VkDeviceQueueInfo2* pQueueInfo,
1918 VkQueue* pQueue)
1919 {
1920 RADV_FROM_HANDLE(radv_device, device, _device);
1921 struct radv_queue *queue;
1922
1923 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
1924 if (pQueueInfo->flags != queue->flags) {
1925 /* From the Vulkan 1.1.70 spec:
1926 *
1927 * "The queue returned by vkGetDeviceQueue2 must have the same
1928 * flags value from this structure as that used at device
1929 * creation time in a VkDeviceQueueCreateInfo instance. If no
1930 * matching flags were specified at device creation time then
1931 * pQueue will return VK_NULL_HANDLE."
1932 */
1933 *pQueue = VK_NULL_HANDLE;
1934 return;
1935 }
1936
1937 *pQueue = radv_queue_to_handle(queue);
1938 }
1939
1940 void radv_GetDeviceQueue(
1941 VkDevice _device,
1942 uint32_t queueFamilyIndex,
1943 uint32_t queueIndex,
1944 VkQueue* pQueue)
1945 {
1946 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
1947 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
1948 .queueFamilyIndex = queueFamilyIndex,
1949 .queueIndex = queueIndex
1950 };
1951
1952 radv_GetDeviceQueue2(_device, &info, pQueue);
1953 }
1954
1955 static void
1956 fill_geom_tess_rings(struct radv_queue *queue,
1957 uint32_t *map,
1958 bool add_sample_positions,
1959 uint32_t esgs_ring_size,
1960 struct radeon_winsys_bo *esgs_ring_bo,
1961 uint32_t gsvs_ring_size,
1962 struct radeon_winsys_bo *gsvs_ring_bo,
1963 uint32_t tess_factor_ring_size,
1964 uint32_t tess_offchip_ring_offset,
1965 uint32_t tess_offchip_ring_size,
1966 struct radeon_winsys_bo *tess_rings_bo)
1967 {
1968 uint64_t esgs_va = 0, gsvs_va = 0;
1969 uint64_t tess_va = 0, tess_offchip_va = 0;
1970 uint32_t *desc = &map[4];
1971
1972 if (esgs_ring_bo)
1973 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1974 if (gsvs_ring_bo)
1975 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1976 if (tess_rings_bo) {
1977 tess_va = radv_buffer_get_va(tess_rings_bo);
1978 tess_offchip_va = tess_va + tess_offchip_ring_offset;
1979 }
1980
1981 /* stride 0, num records - size, add tid, swizzle, elsize4,
1982 index stride 64 */
1983 desc[0] = esgs_va;
1984 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1985 S_008F04_STRIDE(0) |
1986 S_008F04_SWIZZLE_ENABLE(true);
1987 desc[2] = esgs_ring_size;
1988 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1989 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1990 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1991 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1992 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1993 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1994 S_008F0C_ELEMENT_SIZE(1) |
1995 S_008F0C_INDEX_STRIDE(3) |
1996 S_008F0C_ADD_TID_ENABLE(true);
1997
1998 desc += 4;
1999 /* GS entry for ES->GS ring */
2000 /* stride 0, num records - size, elsize0,
2001 index stride 0 */
2002 desc[0] = esgs_va;
2003 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
2004 S_008F04_STRIDE(0) |
2005 S_008F04_SWIZZLE_ENABLE(false);
2006 desc[2] = esgs_ring_size;
2007 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2008 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2009 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2010 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2011 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2012 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2013 S_008F0C_ELEMENT_SIZE(0) |
2014 S_008F0C_INDEX_STRIDE(0) |
2015 S_008F0C_ADD_TID_ENABLE(false);
2016
2017 desc += 4;
2018 /* VS entry for GS->VS ring */
2019 /* stride 0, num records - size, elsize0,
2020 index stride 0 */
2021 desc[0] = gsvs_va;
2022 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2023 S_008F04_STRIDE(0) |
2024 S_008F04_SWIZZLE_ENABLE(false);
2025 desc[2] = gsvs_ring_size;
2026 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2027 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2028 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2029 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2030 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2031 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2032 S_008F0C_ELEMENT_SIZE(0) |
2033 S_008F0C_INDEX_STRIDE(0) |
2034 S_008F0C_ADD_TID_ENABLE(false);
2035 desc += 4;
2036
2037 /* stride gsvs_itemsize, num records 64
2038 elsize 4, index stride 16 */
2039 /* shader will patch stride and desc[2] */
2040 desc[0] = gsvs_va;
2041 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2042 S_008F04_STRIDE(0) |
2043 S_008F04_SWIZZLE_ENABLE(true);
2044 desc[2] = 0;
2045 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2046 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2047 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2048 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2049 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2050 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2051 S_008F0C_ELEMENT_SIZE(1) |
2052 S_008F0C_INDEX_STRIDE(1) |
2053 S_008F0C_ADD_TID_ENABLE(true);
2054 desc += 4;
2055
2056 desc[0] = tess_va;
2057 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
2058 S_008F04_STRIDE(0) |
2059 S_008F04_SWIZZLE_ENABLE(false);
2060 desc[2] = tess_factor_ring_size;
2061 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2062 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2063 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2064 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2065 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2066 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2067 S_008F0C_ELEMENT_SIZE(0) |
2068 S_008F0C_INDEX_STRIDE(0) |
2069 S_008F0C_ADD_TID_ENABLE(false);
2070 desc += 4;
2071
2072 desc[0] = tess_offchip_va;
2073 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
2074 S_008F04_STRIDE(0) |
2075 S_008F04_SWIZZLE_ENABLE(false);
2076 desc[2] = tess_offchip_ring_size;
2077 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2078 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2079 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2080 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2081 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2082 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2083 S_008F0C_ELEMENT_SIZE(0) |
2084 S_008F0C_INDEX_STRIDE(0) |
2085 S_008F0C_ADD_TID_ENABLE(false);
2086 desc += 4;
2087
2088 /* add sample positions after all rings */
2089 memcpy(desc, queue->device->sample_locations_1x, 8);
2090 desc += 2;
2091 memcpy(desc, queue->device->sample_locations_2x, 16);
2092 desc += 4;
2093 memcpy(desc, queue->device->sample_locations_4x, 32);
2094 desc += 8;
2095 memcpy(desc, queue->device->sample_locations_8x, 64);
2096 }
2097
2098 static unsigned
2099 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2100 {
2101 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
2102 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2103 device->physical_device->rad_info.family != CHIP_STONEY;
2104 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2105 unsigned max_offchip_buffers;
2106 unsigned offchip_granularity;
2107 unsigned hs_offchip_param;
2108
2109 /*
2110 * Per RadeonSI:
2111 * This must be one less than the maximum number due to a hw limitation.
2112 * Various hardware bugs in SI, CIK, and GFX9 need this.
2113 *
2114 * Per AMDVLK:
2115 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2116 * Gfx7 should limit max_offchip_buffers to 508
2117 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2118 *
2119 * Follow AMDVLK here.
2120 */
2121 if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2122 device->physical_device->rad_info.chip_class == CIK ||
2123 device->physical_device->rad_info.chip_class == SI)
2124 --max_offchip_buffers_per_se;
2125
2126 max_offchip_buffers = max_offchip_buffers_per_se *
2127 device->physical_device->rad_info.max_se;
2128
2129 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2130 * around by setting 4K granularity.
2131 */
2132 if (device->tess_offchip_block_dw_size == 4096) {
2133 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2134 offchip_granularity = V_03093C_X_4K_DWORDS;
2135 } else {
2136 assert(device->tess_offchip_block_dw_size == 8192);
2137 offchip_granularity = V_03093C_X_8K_DWORDS;
2138 }
2139
2140 switch (device->physical_device->rad_info.chip_class) {
2141 case SI:
2142 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2143 break;
2144 case CIK:
2145 case VI:
2146 case GFX9:
2147 default:
2148 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2149 break;
2150 }
2151
2152 *max_offchip_buffers_p = max_offchip_buffers;
2153 if (device->physical_device->rad_info.chip_class >= CIK) {
2154 if (device->physical_device->rad_info.chip_class >= VI)
2155 --max_offchip_buffers;
2156 hs_offchip_param =
2157 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2158 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2159 } else {
2160 hs_offchip_param =
2161 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2162 }
2163 return hs_offchip_param;
2164 }
2165
2166 static void
2167 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2168 struct radeon_winsys_bo *esgs_ring_bo,
2169 uint32_t esgs_ring_size,
2170 struct radeon_winsys_bo *gsvs_ring_bo,
2171 uint32_t gsvs_ring_size)
2172 {
2173 if (!esgs_ring_bo && !gsvs_ring_bo)
2174 return;
2175
2176 if (esgs_ring_bo)
2177 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2178
2179 if (gsvs_ring_bo)
2180 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2181
2182 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2183 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2184 radeon_emit(cs, esgs_ring_size >> 8);
2185 radeon_emit(cs, gsvs_ring_size >> 8);
2186 } else {
2187 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2188 radeon_emit(cs, esgs_ring_size >> 8);
2189 radeon_emit(cs, gsvs_ring_size >> 8);
2190 }
2191 }
2192
2193 static void
2194 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2195 unsigned hs_offchip_param, unsigned tf_ring_size,
2196 struct radeon_winsys_bo *tess_rings_bo)
2197 {
2198 uint64_t tf_va;
2199
2200 if (!tess_rings_bo)
2201 return;
2202
2203 tf_va = radv_buffer_get_va(tess_rings_bo);
2204
2205 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2206
2207 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2208 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2209 S_030938_SIZE(tf_ring_size / 4));
2210 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2211 tf_va >> 8);
2212 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2213 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2214 S_030944_BASE_HI(tf_va >> 40));
2215 }
2216 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2217 hs_offchip_param);
2218 } else {
2219 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2220 S_008988_SIZE(tf_ring_size / 4));
2221 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2222 tf_va >> 8);
2223 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2224 hs_offchip_param);
2225 }
2226 }
2227
2228 static void
2229 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2230 struct radeon_winsys_bo *compute_scratch_bo)
2231 {
2232 uint64_t scratch_va;
2233
2234 if (!compute_scratch_bo)
2235 return;
2236
2237 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2238
2239 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2240
2241 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2242 radeon_emit(cs, scratch_va);
2243 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2244 S_008F04_SWIZZLE_ENABLE(1));
2245 }
2246
2247 static void
2248 radv_emit_global_shader_pointers(struct radv_queue *queue,
2249 struct radeon_cmdbuf *cs,
2250 struct radeon_winsys_bo *descriptor_bo)
2251 {
2252 uint64_t va;
2253
2254 if (!descriptor_bo)
2255 return;
2256
2257 va = radv_buffer_get_va(descriptor_bo);
2258
2259 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2260
2261 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2262 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2263 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2264 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2265 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2266
2267 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2268 radv_emit_shader_pointer(queue->device, cs, regs[i],
2269 va, true);
2270 }
2271 } else {
2272 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2273 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2274 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2275 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2276 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2277 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2278
2279 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2280 radv_emit_shader_pointer(queue->device, cs, regs[i],
2281 va, true);
2282 }
2283 }
2284 }
2285
2286 static void
2287 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2288 {
2289 struct radv_device *device = queue->device;
2290
2291 if (device->gfx_init) {
2292 uint64_t va = radv_buffer_get_va(device->gfx_init);
2293
2294 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2295 radeon_emit(cs, va);
2296 radeon_emit(cs, va >> 32);
2297 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2298
2299 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2300 } else {
2301 struct radv_physical_device *physical_device = device->physical_device;
2302 si_emit_graphics(physical_device, cs);
2303 }
2304 }
2305
2306 static void
2307 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2308 {
2309 struct radv_physical_device *physical_device = queue->device->physical_device;
2310 si_emit_compute(physical_device, cs);
2311 }
2312
2313 static VkResult
2314 radv_get_preamble_cs(struct radv_queue *queue,
2315 uint32_t scratch_size,
2316 uint32_t compute_scratch_size,
2317 uint32_t esgs_ring_size,
2318 uint32_t gsvs_ring_size,
2319 bool needs_tess_rings,
2320 bool needs_sample_positions,
2321 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2322 struct radeon_cmdbuf **initial_preamble_cs,
2323 struct radeon_cmdbuf **continue_preamble_cs)
2324 {
2325 struct radeon_winsys_bo *scratch_bo = NULL;
2326 struct radeon_winsys_bo *descriptor_bo = NULL;
2327 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2328 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2329 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2330 struct radeon_winsys_bo *tess_rings_bo = NULL;
2331 struct radeon_cmdbuf *dest_cs[3] = {0};
2332 bool add_tess_rings = false, add_sample_positions = false;
2333 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2334 unsigned max_offchip_buffers;
2335 unsigned hs_offchip_param = 0;
2336 unsigned tess_offchip_ring_offset;
2337 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2338 if (!queue->has_tess_rings) {
2339 if (needs_tess_rings)
2340 add_tess_rings = true;
2341 }
2342 if (!queue->has_sample_positions) {
2343 if (needs_sample_positions)
2344 add_sample_positions = true;
2345 }
2346 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2347 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2348 &max_offchip_buffers);
2349 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2350 tess_offchip_ring_size = max_offchip_buffers *
2351 queue->device->tess_offchip_block_dw_size * 4;
2352
2353 if (scratch_size <= queue->scratch_size &&
2354 compute_scratch_size <= queue->compute_scratch_size &&
2355 esgs_ring_size <= queue->esgs_ring_size &&
2356 gsvs_ring_size <= queue->gsvs_ring_size &&
2357 !add_tess_rings && !add_sample_positions &&
2358 queue->initial_preamble_cs) {
2359 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2360 *initial_preamble_cs = queue->initial_preamble_cs;
2361 *continue_preamble_cs = queue->continue_preamble_cs;
2362 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2363 *continue_preamble_cs = NULL;
2364 return VK_SUCCESS;
2365 }
2366
2367 if (scratch_size > queue->scratch_size) {
2368 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2369 scratch_size,
2370 4096,
2371 RADEON_DOMAIN_VRAM,
2372 ring_bo_flags);
2373 if (!scratch_bo)
2374 goto fail;
2375 } else
2376 scratch_bo = queue->scratch_bo;
2377
2378 if (compute_scratch_size > queue->compute_scratch_size) {
2379 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2380 compute_scratch_size,
2381 4096,
2382 RADEON_DOMAIN_VRAM,
2383 ring_bo_flags);
2384 if (!compute_scratch_bo)
2385 goto fail;
2386
2387 } else
2388 compute_scratch_bo = queue->compute_scratch_bo;
2389
2390 if (esgs_ring_size > queue->esgs_ring_size) {
2391 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2392 esgs_ring_size,
2393 4096,
2394 RADEON_DOMAIN_VRAM,
2395 ring_bo_flags);
2396 if (!esgs_ring_bo)
2397 goto fail;
2398 } else {
2399 esgs_ring_bo = queue->esgs_ring_bo;
2400 esgs_ring_size = queue->esgs_ring_size;
2401 }
2402
2403 if (gsvs_ring_size > queue->gsvs_ring_size) {
2404 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2405 gsvs_ring_size,
2406 4096,
2407 RADEON_DOMAIN_VRAM,
2408 ring_bo_flags);
2409 if (!gsvs_ring_bo)
2410 goto fail;
2411 } else {
2412 gsvs_ring_bo = queue->gsvs_ring_bo;
2413 gsvs_ring_size = queue->gsvs_ring_size;
2414 }
2415
2416 if (add_tess_rings) {
2417 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2418 tess_offchip_ring_offset + tess_offchip_ring_size,
2419 256,
2420 RADEON_DOMAIN_VRAM,
2421 ring_bo_flags);
2422 if (!tess_rings_bo)
2423 goto fail;
2424 } else {
2425 tess_rings_bo = queue->tess_rings_bo;
2426 }
2427
2428 if (scratch_bo != queue->scratch_bo ||
2429 esgs_ring_bo != queue->esgs_ring_bo ||
2430 gsvs_ring_bo != queue->gsvs_ring_bo ||
2431 tess_rings_bo != queue->tess_rings_bo ||
2432 add_sample_positions) {
2433 uint32_t size = 0;
2434 if (gsvs_ring_bo || esgs_ring_bo ||
2435 tess_rings_bo || add_sample_positions) {
2436 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2437 if (add_sample_positions)
2438 size += 128; /* 64+32+16+8 = 120 bytes */
2439 }
2440 else if (scratch_bo)
2441 size = 8; /* 2 dword */
2442
2443 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2444 size,
2445 4096,
2446 RADEON_DOMAIN_VRAM,
2447 RADEON_FLAG_CPU_ACCESS |
2448 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2449 RADEON_FLAG_READ_ONLY);
2450 if (!descriptor_bo)
2451 goto fail;
2452 } else
2453 descriptor_bo = queue->descriptor_bo;
2454
2455 for(int i = 0; i < 3; ++i) {
2456 struct radeon_cmdbuf *cs = NULL;
2457 cs = queue->device->ws->cs_create(queue->device->ws,
2458 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2459 if (!cs)
2460 goto fail;
2461
2462 dest_cs[i] = cs;
2463
2464 if (scratch_bo)
2465 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2466
2467 /* Emit initial configuration. */
2468 switch (queue->queue_family_index) {
2469 case RADV_QUEUE_GENERAL:
2470 radv_init_graphics_state(cs, queue);
2471 break;
2472 case RADV_QUEUE_COMPUTE:
2473 radv_init_compute_state(cs, queue);
2474 break;
2475 case RADV_QUEUE_TRANSFER:
2476 break;
2477 }
2478
2479 if (descriptor_bo != queue->descriptor_bo) {
2480 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2481
2482 if (scratch_bo) {
2483 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2484 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2485 S_008F04_SWIZZLE_ENABLE(1);
2486 map[0] = scratch_va;
2487 map[1] = rsrc1;
2488 }
2489
2490 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo ||
2491 add_sample_positions)
2492 fill_geom_tess_rings(queue, map, add_sample_positions,
2493 esgs_ring_size, esgs_ring_bo,
2494 gsvs_ring_size, gsvs_ring_bo,
2495 tess_factor_ring_size,
2496 tess_offchip_ring_offset,
2497 tess_offchip_ring_size,
2498 tess_rings_bo);
2499
2500 queue->device->ws->buffer_unmap(descriptor_bo);
2501 }
2502
2503 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2504 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2505 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2506 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2507 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2508 }
2509
2510 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2511 gsvs_ring_bo, gsvs_ring_size);
2512 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2513 tess_factor_ring_size, tess_rings_bo);
2514 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2515 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2516
2517 if (i == 0) {
2518 si_cs_emit_cache_flush(cs,
2519 queue->device->physical_device->rad_info.chip_class,
2520 NULL, 0,
2521 queue->queue_family_index == RING_COMPUTE &&
2522 queue->device->physical_device->rad_info.chip_class >= CIK,
2523 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2524 RADV_CMD_FLAG_INV_ICACHE |
2525 RADV_CMD_FLAG_INV_SMEM_L1 |
2526 RADV_CMD_FLAG_INV_VMEM_L1 |
2527 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2528 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2529 } else if (i == 1) {
2530 si_cs_emit_cache_flush(cs,
2531 queue->device->physical_device->rad_info.chip_class,
2532 NULL, 0,
2533 queue->queue_family_index == RING_COMPUTE &&
2534 queue->device->physical_device->rad_info.chip_class >= CIK,
2535 RADV_CMD_FLAG_INV_ICACHE |
2536 RADV_CMD_FLAG_INV_SMEM_L1 |
2537 RADV_CMD_FLAG_INV_VMEM_L1 |
2538 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2539 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2540 }
2541
2542 if (!queue->device->ws->cs_finalize(cs))
2543 goto fail;
2544 }
2545
2546 if (queue->initial_full_flush_preamble_cs)
2547 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2548
2549 if (queue->initial_preamble_cs)
2550 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2551
2552 if (queue->continue_preamble_cs)
2553 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2554
2555 queue->initial_full_flush_preamble_cs = dest_cs[0];
2556 queue->initial_preamble_cs = dest_cs[1];
2557 queue->continue_preamble_cs = dest_cs[2];
2558
2559 if (scratch_bo != queue->scratch_bo) {
2560 if (queue->scratch_bo)
2561 queue->device->ws->buffer_destroy(queue->scratch_bo);
2562 queue->scratch_bo = scratch_bo;
2563 queue->scratch_size = scratch_size;
2564 }
2565
2566 if (compute_scratch_bo != queue->compute_scratch_bo) {
2567 if (queue->compute_scratch_bo)
2568 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2569 queue->compute_scratch_bo = compute_scratch_bo;
2570 queue->compute_scratch_size = compute_scratch_size;
2571 }
2572
2573 if (esgs_ring_bo != queue->esgs_ring_bo) {
2574 if (queue->esgs_ring_bo)
2575 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2576 queue->esgs_ring_bo = esgs_ring_bo;
2577 queue->esgs_ring_size = esgs_ring_size;
2578 }
2579
2580 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2581 if (queue->gsvs_ring_bo)
2582 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2583 queue->gsvs_ring_bo = gsvs_ring_bo;
2584 queue->gsvs_ring_size = gsvs_ring_size;
2585 }
2586
2587 if (tess_rings_bo != queue->tess_rings_bo) {
2588 queue->tess_rings_bo = tess_rings_bo;
2589 queue->has_tess_rings = true;
2590 }
2591
2592 if (descriptor_bo != queue->descriptor_bo) {
2593 if (queue->descriptor_bo)
2594 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2595
2596 queue->descriptor_bo = descriptor_bo;
2597 }
2598
2599 if (add_sample_positions)
2600 queue->has_sample_positions = true;
2601
2602 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2603 *initial_preamble_cs = queue->initial_preamble_cs;
2604 *continue_preamble_cs = queue->continue_preamble_cs;
2605 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2606 *continue_preamble_cs = NULL;
2607 return VK_SUCCESS;
2608 fail:
2609 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2610 if (dest_cs[i])
2611 queue->device->ws->cs_destroy(dest_cs[i]);
2612 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2613 queue->device->ws->buffer_destroy(descriptor_bo);
2614 if (scratch_bo && scratch_bo != queue->scratch_bo)
2615 queue->device->ws->buffer_destroy(scratch_bo);
2616 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2617 queue->device->ws->buffer_destroy(compute_scratch_bo);
2618 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2619 queue->device->ws->buffer_destroy(esgs_ring_bo);
2620 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2621 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2622 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2623 queue->device->ws->buffer_destroy(tess_rings_bo);
2624 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2625 }
2626
2627 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2628 struct radv_winsys_sem_counts *counts,
2629 int num_sems,
2630 const VkSemaphore *sems,
2631 VkFence _fence,
2632 bool reset_temp)
2633 {
2634 int syncobj_idx = 0, sem_idx = 0;
2635
2636 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2637 return VK_SUCCESS;
2638
2639 for (uint32_t i = 0; i < num_sems; i++) {
2640 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2641
2642 if (sem->temp_syncobj || sem->syncobj)
2643 counts->syncobj_count++;
2644 else
2645 counts->sem_count++;
2646 }
2647
2648 if (_fence != VK_NULL_HANDLE) {
2649 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2650 if (fence->temp_syncobj || fence->syncobj)
2651 counts->syncobj_count++;
2652 }
2653
2654 if (counts->syncobj_count) {
2655 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2656 if (!counts->syncobj)
2657 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2658 }
2659
2660 if (counts->sem_count) {
2661 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2662 if (!counts->sem) {
2663 free(counts->syncobj);
2664 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2665 }
2666 }
2667
2668 for (uint32_t i = 0; i < num_sems; i++) {
2669 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2670
2671 if (sem->temp_syncobj) {
2672 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2673 }
2674 else if (sem->syncobj)
2675 counts->syncobj[syncobj_idx++] = sem->syncobj;
2676 else {
2677 assert(sem->sem);
2678 counts->sem[sem_idx++] = sem->sem;
2679 }
2680 }
2681
2682 if (_fence != VK_NULL_HANDLE) {
2683 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2684 if (fence->temp_syncobj)
2685 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2686 else if (fence->syncobj)
2687 counts->syncobj[syncobj_idx++] = fence->syncobj;
2688 }
2689
2690 return VK_SUCCESS;
2691 }
2692
2693 static void
2694 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2695 {
2696 free(sem_info->wait.syncobj);
2697 free(sem_info->wait.sem);
2698 free(sem_info->signal.syncobj);
2699 free(sem_info->signal.sem);
2700 }
2701
2702
2703 static void radv_free_temp_syncobjs(struct radv_device *device,
2704 int num_sems,
2705 const VkSemaphore *sems)
2706 {
2707 for (uint32_t i = 0; i < num_sems; i++) {
2708 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2709
2710 if (sem->temp_syncobj) {
2711 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2712 sem->temp_syncobj = 0;
2713 }
2714 }
2715 }
2716
2717 static VkResult
2718 radv_alloc_sem_info(struct radv_instance *instance,
2719 struct radv_winsys_sem_info *sem_info,
2720 int num_wait_sems,
2721 const VkSemaphore *wait_sems,
2722 int num_signal_sems,
2723 const VkSemaphore *signal_sems,
2724 VkFence fence)
2725 {
2726 VkResult ret;
2727 memset(sem_info, 0, sizeof(*sem_info));
2728
2729 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2730 if (ret)
2731 return ret;
2732 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2733 if (ret)
2734 radv_free_sem_info(sem_info);
2735
2736 /* caller can override these */
2737 sem_info->cs_emit_wait = true;
2738 sem_info->cs_emit_signal = true;
2739 return ret;
2740 }
2741
2742 /* Signals fence as soon as all the work currently put on queue is done. */
2743 static VkResult radv_signal_fence(struct radv_queue *queue,
2744 struct radv_fence *fence)
2745 {
2746 int ret;
2747 VkResult result;
2748 struct radv_winsys_sem_info sem_info;
2749
2750 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2751 radv_fence_to_handle(fence));
2752 if (result != VK_SUCCESS)
2753 return result;
2754
2755 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2756 &queue->device->empty_cs[queue->queue_family_index],
2757 1, NULL, NULL, &sem_info, NULL,
2758 false, fence->fence);
2759 radv_free_sem_info(&sem_info);
2760
2761 if (ret)
2762 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2763
2764 return VK_SUCCESS;
2765 }
2766
2767 VkResult radv_QueueSubmit(
2768 VkQueue _queue,
2769 uint32_t submitCount,
2770 const VkSubmitInfo* pSubmits,
2771 VkFence _fence)
2772 {
2773 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2774 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2775 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2776 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2777 int ret;
2778 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2779 uint32_t scratch_size = 0;
2780 uint32_t compute_scratch_size = 0;
2781 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2782 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2783 VkResult result;
2784 bool fence_emitted = false;
2785 bool tess_rings_needed = false;
2786 bool sample_positions_needed = false;
2787
2788 /* Do this first so failing to allocate scratch buffers can't result in
2789 * partially executed submissions. */
2790 for (uint32_t i = 0; i < submitCount; i++) {
2791 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2792 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2793 pSubmits[i].pCommandBuffers[j]);
2794
2795 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2796 compute_scratch_size = MAX2(compute_scratch_size,
2797 cmd_buffer->compute_scratch_size_needed);
2798 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2799 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2800 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2801 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2802 }
2803 }
2804
2805 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2806 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2807 sample_positions_needed, &initial_flush_preamble_cs,
2808 &initial_preamble_cs, &continue_preamble_cs);
2809 if (result != VK_SUCCESS)
2810 return result;
2811
2812 for (uint32_t i = 0; i < submitCount; i++) {
2813 struct radeon_cmdbuf **cs_array;
2814 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2815 bool can_patch = true;
2816 uint32_t advance;
2817 struct radv_winsys_sem_info sem_info;
2818
2819 result = radv_alloc_sem_info(queue->device->instance,
2820 &sem_info,
2821 pSubmits[i].waitSemaphoreCount,
2822 pSubmits[i].pWaitSemaphores,
2823 pSubmits[i].signalSemaphoreCount,
2824 pSubmits[i].pSignalSemaphores,
2825 _fence);
2826 if (result != VK_SUCCESS)
2827 return result;
2828
2829 if (!pSubmits[i].commandBufferCount) {
2830 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2831 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2832 &queue->device->empty_cs[queue->queue_family_index],
2833 1, NULL, NULL,
2834 &sem_info, NULL,
2835 false, base_fence);
2836 if (ret) {
2837 radv_loge("failed to submit CS %d\n", i);
2838 abort();
2839 }
2840 fence_emitted = true;
2841 }
2842 radv_free_sem_info(&sem_info);
2843 continue;
2844 }
2845
2846 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
2847 (pSubmits[i].commandBufferCount));
2848
2849 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2850 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2851 pSubmits[i].pCommandBuffers[j]);
2852 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2853
2854 cs_array[j] = cmd_buffer->cs;
2855 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2856 can_patch = false;
2857
2858 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2859 }
2860
2861 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2862 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2863 const struct radv_winsys_bo_list *bo_list = NULL;
2864
2865 advance = MIN2(max_cs_submission,
2866 pSubmits[i].commandBufferCount - j);
2867
2868 if (queue->device->trace_bo)
2869 *queue->device->trace_id_ptr = 0;
2870
2871 sem_info.cs_emit_wait = j == 0;
2872 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2873
2874 if (unlikely(queue->device->use_global_bo_list)) {
2875 pthread_mutex_lock(&queue->device->bo_list.mutex);
2876 bo_list = &queue->device->bo_list.list;
2877 }
2878
2879 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2880 advance, initial_preamble, continue_preamble_cs,
2881 &sem_info, bo_list,
2882 can_patch, base_fence);
2883
2884 if (unlikely(queue->device->use_global_bo_list))
2885 pthread_mutex_unlock(&queue->device->bo_list.mutex);
2886
2887 if (ret) {
2888 radv_loge("failed to submit CS %d\n", i);
2889 abort();
2890 }
2891 fence_emitted = true;
2892 if (queue->device->trace_bo) {
2893 radv_check_gpu_hangs(queue, cs_array[j]);
2894 }
2895 }
2896
2897 radv_free_temp_syncobjs(queue->device,
2898 pSubmits[i].waitSemaphoreCount,
2899 pSubmits[i].pWaitSemaphores);
2900 radv_free_sem_info(&sem_info);
2901 free(cs_array);
2902 }
2903
2904 if (fence) {
2905 if (!fence_emitted) {
2906 result = radv_signal_fence(queue, fence);
2907 if (result != VK_SUCCESS)
2908 return result;
2909 }
2910 fence->submitted = true;
2911 }
2912
2913 return VK_SUCCESS;
2914 }
2915
2916 VkResult radv_QueueWaitIdle(
2917 VkQueue _queue)
2918 {
2919 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2920
2921 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2922 radv_queue_family_to_ring(queue->queue_family_index),
2923 queue->queue_idx);
2924 return VK_SUCCESS;
2925 }
2926
2927 VkResult radv_DeviceWaitIdle(
2928 VkDevice _device)
2929 {
2930 RADV_FROM_HANDLE(radv_device, device, _device);
2931
2932 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2933 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2934 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2935 }
2936 }
2937 return VK_SUCCESS;
2938 }
2939
2940 VkResult radv_EnumerateInstanceExtensionProperties(
2941 const char* pLayerName,
2942 uint32_t* pPropertyCount,
2943 VkExtensionProperties* pProperties)
2944 {
2945 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2946
2947 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
2948 if (radv_supported_instance_extensions.extensions[i]) {
2949 vk_outarray_append(&out, prop) {
2950 *prop = radv_instance_extensions[i];
2951 }
2952 }
2953 }
2954
2955 return vk_outarray_status(&out);
2956 }
2957
2958 VkResult radv_EnumerateDeviceExtensionProperties(
2959 VkPhysicalDevice physicalDevice,
2960 const char* pLayerName,
2961 uint32_t* pPropertyCount,
2962 VkExtensionProperties* pProperties)
2963 {
2964 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2965 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2966
2967 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
2968 if (device->supported_extensions.extensions[i]) {
2969 vk_outarray_append(&out, prop) {
2970 *prop = radv_device_extensions[i];
2971 }
2972 }
2973 }
2974
2975 return vk_outarray_status(&out);
2976 }
2977
2978 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2979 VkInstance _instance,
2980 const char* pName)
2981 {
2982 RADV_FROM_HANDLE(radv_instance, instance, _instance);
2983
2984 return radv_lookup_entrypoint_checked(pName,
2985 instance ? instance->apiVersion : 0,
2986 instance ? &instance->enabled_extensions : NULL,
2987 NULL);
2988 }
2989
2990 /* The loader wants us to expose a second GetInstanceProcAddr function
2991 * to work around certain LD_PRELOAD issues seen in apps.
2992 */
2993 PUBLIC
2994 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2995 VkInstance instance,
2996 const char* pName);
2997
2998 PUBLIC
2999 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3000 VkInstance instance,
3001 const char* pName)
3002 {
3003 return radv_GetInstanceProcAddr(instance, pName);
3004 }
3005
3006 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3007 VkDevice _device,
3008 const char* pName)
3009 {
3010 RADV_FROM_HANDLE(radv_device, device, _device);
3011
3012 return radv_lookup_entrypoint_checked(pName,
3013 device->instance->apiVersion,
3014 &device->instance->enabled_extensions,
3015 &device->enabled_extensions);
3016 }
3017
3018 bool radv_get_memory_fd(struct radv_device *device,
3019 struct radv_device_memory *memory,
3020 int *pFD)
3021 {
3022 struct radeon_bo_metadata metadata;
3023
3024 if (memory->image) {
3025 radv_init_metadata(device, memory->image, &metadata);
3026 device->ws->buffer_set_metadata(memory->bo, &metadata);
3027 }
3028
3029 return device->ws->buffer_get_fd(device->ws, memory->bo,
3030 pFD);
3031 }
3032
3033 static VkResult radv_alloc_memory(struct radv_device *device,
3034 const VkMemoryAllocateInfo* pAllocateInfo,
3035 const VkAllocationCallbacks* pAllocator,
3036 VkDeviceMemory* pMem)
3037 {
3038 struct radv_device_memory *mem;
3039 VkResult result;
3040 enum radeon_bo_domain domain;
3041 uint32_t flags = 0;
3042 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3043
3044 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3045
3046 if (pAllocateInfo->allocationSize == 0) {
3047 /* Apparently, this is allowed */
3048 *pMem = VK_NULL_HANDLE;
3049 return VK_SUCCESS;
3050 }
3051
3052 const VkImportMemoryFdInfoKHR *import_info =
3053 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3054 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3055 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3056 const VkExportMemoryAllocateInfo *export_info =
3057 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3058 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3059 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3060
3061 const struct wsi_memory_allocate_info *wsi_info =
3062 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3063
3064 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3065 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3066 if (mem == NULL)
3067 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3068
3069 if (wsi_info && wsi_info->implicit_sync)
3070 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3071
3072 if (dedicate_info) {
3073 mem->image = radv_image_from_handle(dedicate_info->image);
3074 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3075 } else {
3076 mem->image = NULL;
3077 mem->buffer = NULL;
3078 }
3079
3080 mem->user_ptr = NULL;
3081
3082 if (import_info) {
3083 assert(import_info->handleType ==
3084 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3085 import_info->handleType ==
3086 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3087 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3088 NULL, NULL);
3089 if (!mem->bo) {
3090 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3091 goto fail;
3092 } else {
3093 close(import_info->fd);
3094 }
3095 } else if (host_ptr_info) {
3096 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3097 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3098 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3099 pAllocateInfo->allocationSize);
3100 if (!mem->bo) {
3101 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3102 goto fail;
3103 } else {
3104 mem->user_ptr = host_ptr_info->pHostPointer;
3105 }
3106 } else {
3107 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3108 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3109 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3110 domain = RADEON_DOMAIN_GTT;
3111 else
3112 domain = RADEON_DOMAIN_VRAM;
3113
3114 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3115 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3116 else
3117 flags |= RADEON_FLAG_CPU_ACCESS;
3118
3119 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3120 flags |= RADEON_FLAG_GTT_WC;
3121
3122 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
3123 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3124
3125 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3126 domain, flags);
3127
3128 if (!mem->bo) {
3129 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3130 goto fail;
3131 }
3132 mem->type_index = mem_type_index;
3133 }
3134
3135 result = radv_bo_list_add(device, mem->bo);
3136 if (result != VK_SUCCESS)
3137 goto fail_bo;
3138
3139 *pMem = radv_device_memory_to_handle(mem);
3140
3141 return VK_SUCCESS;
3142
3143 fail_bo:
3144 device->ws->buffer_destroy(mem->bo);
3145 fail:
3146 vk_free2(&device->alloc, pAllocator, mem);
3147
3148 return result;
3149 }
3150
3151 VkResult radv_AllocateMemory(
3152 VkDevice _device,
3153 const VkMemoryAllocateInfo* pAllocateInfo,
3154 const VkAllocationCallbacks* pAllocator,
3155 VkDeviceMemory* pMem)
3156 {
3157 RADV_FROM_HANDLE(radv_device, device, _device);
3158 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3159 }
3160
3161 void radv_FreeMemory(
3162 VkDevice _device,
3163 VkDeviceMemory _mem,
3164 const VkAllocationCallbacks* pAllocator)
3165 {
3166 RADV_FROM_HANDLE(radv_device, device, _device);
3167 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3168
3169 if (mem == NULL)
3170 return;
3171
3172 radv_bo_list_remove(device, mem->bo);
3173 device->ws->buffer_destroy(mem->bo);
3174 mem->bo = NULL;
3175
3176 vk_free2(&device->alloc, pAllocator, mem);
3177 }
3178
3179 VkResult radv_MapMemory(
3180 VkDevice _device,
3181 VkDeviceMemory _memory,
3182 VkDeviceSize offset,
3183 VkDeviceSize size,
3184 VkMemoryMapFlags flags,
3185 void** ppData)
3186 {
3187 RADV_FROM_HANDLE(radv_device, device, _device);
3188 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3189
3190 if (mem == NULL) {
3191 *ppData = NULL;
3192 return VK_SUCCESS;
3193 }
3194
3195 if (mem->user_ptr)
3196 *ppData = mem->user_ptr;
3197 else
3198 *ppData = device->ws->buffer_map(mem->bo);
3199
3200 if (*ppData) {
3201 *ppData += offset;
3202 return VK_SUCCESS;
3203 }
3204
3205 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3206 }
3207
3208 void radv_UnmapMemory(
3209 VkDevice _device,
3210 VkDeviceMemory _memory)
3211 {
3212 RADV_FROM_HANDLE(radv_device, device, _device);
3213 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3214
3215 if (mem == NULL)
3216 return;
3217
3218 if (mem->user_ptr == NULL)
3219 device->ws->buffer_unmap(mem->bo);
3220 }
3221
3222 VkResult radv_FlushMappedMemoryRanges(
3223 VkDevice _device,
3224 uint32_t memoryRangeCount,
3225 const VkMappedMemoryRange* pMemoryRanges)
3226 {
3227 return VK_SUCCESS;
3228 }
3229
3230 VkResult radv_InvalidateMappedMemoryRanges(
3231 VkDevice _device,
3232 uint32_t memoryRangeCount,
3233 const VkMappedMemoryRange* pMemoryRanges)
3234 {
3235 return VK_SUCCESS;
3236 }
3237
3238 void radv_GetBufferMemoryRequirements(
3239 VkDevice _device,
3240 VkBuffer _buffer,
3241 VkMemoryRequirements* pMemoryRequirements)
3242 {
3243 RADV_FROM_HANDLE(radv_device, device, _device);
3244 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3245
3246 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3247
3248 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3249 pMemoryRequirements->alignment = 4096;
3250 else
3251 pMemoryRequirements->alignment = 16;
3252
3253 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3254 }
3255
3256 void radv_GetBufferMemoryRequirements2(
3257 VkDevice device,
3258 const VkBufferMemoryRequirementsInfo2 *pInfo,
3259 VkMemoryRequirements2 *pMemoryRequirements)
3260 {
3261 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3262 &pMemoryRequirements->memoryRequirements);
3263 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3264 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3265 switch (ext->sType) {
3266 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3267 VkMemoryDedicatedRequirements *req =
3268 (VkMemoryDedicatedRequirements *) ext;
3269 req->requiresDedicatedAllocation = buffer->shareable;
3270 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3271 break;
3272 }
3273 default:
3274 break;
3275 }
3276 }
3277 }
3278
3279 void radv_GetImageMemoryRequirements(
3280 VkDevice _device,
3281 VkImage _image,
3282 VkMemoryRequirements* pMemoryRequirements)
3283 {
3284 RADV_FROM_HANDLE(radv_device, device, _device);
3285 RADV_FROM_HANDLE(radv_image, image, _image);
3286
3287 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3288
3289 pMemoryRequirements->size = image->size;
3290 pMemoryRequirements->alignment = image->alignment;
3291 }
3292
3293 void radv_GetImageMemoryRequirements2(
3294 VkDevice device,
3295 const VkImageMemoryRequirementsInfo2 *pInfo,
3296 VkMemoryRequirements2 *pMemoryRequirements)
3297 {
3298 radv_GetImageMemoryRequirements(device, pInfo->image,
3299 &pMemoryRequirements->memoryRequirements);
3300
3301 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3302
3303 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3304 switch (ext->sType) {
3305 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3306 VkMemoryDedicatedRequirements *req =
3307 (VkMemoryDedicatedRequirements *) ext;
3308 req->requiresDedicatedAllocation = image->shareable;
3309 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3310 break;
3311 }
3312 default:
3313 break;
3314 }
3315 }
3316 }
3317
3318 void radv_GetImageSparseMemoryRequirements(
3319 VkDevice device,
3320 VkImage image,
3321 uint32_t* pSparseMemoryRequirementCount,
3322 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3323 {
3324 stub();
3325 }
3326
3327 void radv_GetImageSparseMemoryRequirements2(
3328 VkDevice device,
3329 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3330 uint32_t* pSparseMemoryRequirementCount,
3331 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3332 {
3333 stub();
3334 }
3335
3336 void radv_GetDeviceMemoryCommitment(
3337 VkDevice device,
3338 VkDeviceMemory memory,
3339 VkDeviceSize* pCommittedMemoryInBytes)
3340 {
3341 *pCommittedMemoryInBytes = 0;
3342 }
3343
3344 VkResult radv_BindBufferMemory2(VkDevice device,
3345 uint32_t bindInfoCount,
3346 const VkBindBufferMemoryInfo *pBindInfos)
3347 {
3348 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3349 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3350 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3351
3352 if (mem) {
3353 buffer->bo = mem->bo;
3354 buffer->offset = pBindInfos[i].memoryOffset;
3355 } else {
3356 buffer->bo = NULL;
3357 }
3358 }
3359 return VK_SUCCESS;
3360 }
3361
3362 VkResult radv_BindBufferMemory(
3363 VkDevice device,
3364 VkBuffer buffer,
3365 VkDeviceMemory memory,
3366 VkDeviceSize memoryOffset)
3367 {
3368 const VkBindBufferMemoryInfo info = {
3369 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3370 .buffer = buffer,
3371 .memory = memory,
3372 .memoryOffset = memoryOffset
3373 };
3374
3375 return radv_BindBufferMemory2(device, 1, &info);
3376 }
3377
3378 VkResult radv_BindImageMemory2(VkDevice device,
3379 uint32_t bindInfoCount,
3380 const VkBindImageMemoryInfo *pBindInfos)
3381 {
3382 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3383 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3384 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3385
3386 if (mem) {
3387 image->bo = mem->bo;
3388 image->offset = pBindInfos[i].memoryOffset;
3389 } else {
3390 image->bo = NULL;
3391 image->offset = 0;
3392 }
3393 }
3394 return VK_SUCCESS;
3395 }
3396
3397
3398 VkResult radv_BindImageMemory(
3399 VkDevice device,
3400 VkImage image,
3401 VkDeviceMemory memory,
3402 VkDeviceSize memoryOffset)
3403 {
3404 const VkBindImageMemoryInfo info = {
3405 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3406 .image = image,
3407 .memory = memory,
3408 .memoryOffset = memoryOffset
3409 };
3410
3411 return radv_BindImageMemory2(device, 1, &info);
3412 }
3413
3414
3415 static void
3416 radv_sparse_buffer_bind_memory(struct radv_device *device,
3417 const VkSparseBufferMemoryBindInfo *bind)
3418 {
3419 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3420
3421 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3422 struct radv_device_memory *mem = NULL;
3423
3424 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3425 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3426
3427 device->ws->buffer_virtual_bind(buffer->bo,
3428 bind->pBinds[i].resourceOffset,
3429 bind->pBinds[i].size,
3430 mem ? mem->bo : NULL,
3431 bind->pBinds[i].memoryOffset);
3432 }
3433 }
3434
3435 static void
3436 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3437 const VkSparseImageOpaqueMemoryBindInfo *bind)
3438 {
3439 RADV_FROM_HANDLE(radv_image, image, bind->image);
3440
3441 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3442 struct radv_device_memory *mem = NULL;
3443
3444 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3445 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3446
3447 device->ws->buffer_virtual_bind(image->bo,
3448 bind->pBinds[i].resourceOffset,
3449 bind->pBinds[i].size,
3450 mem ? mem->bo : NULL,
3451 bind->pBinds[i].memoryOffset);
3452 }
3453 }
3454
3455 VkResult radv_QueueBindSparse(
3456 VkQueue _queue,
3457 uint32_t bindInfoCount,
3458 const VkBindSparseInfo* pBindInfo,
3459 VkFence _fence)
3460 {
3461 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3462 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3463 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3464 bool fence_emitted = false;
3465 VkResult result;
3466 int ret;
3467
3468 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3469 struct radv_winsys_sem_info sem_info;
3470 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3471 radv_sparse_buffer_bind_memory(queue->device,
3472 pBindInfo[i].pBufferBinds + j);
3473 }
3474
3475 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3476 radv_sparse_image_opaque_bind_memory(queue->device,
3477 pBindInfo[i].pImageOpaqueBinds + j);
3478 }
3479
3480 VkResult result;
3481 result = radv_alloc_sem_info(queue->device->instance,
3482 &sem_info,
3483 pBindInfo[i].waitSemaphoreCount,
3484 pBindInfo[i].pWaitSemaphores,
3485 pBindInfo[i].signalSemaphoreCount,
3486 pBindInfo[i].pSignalSemaphores,
3487 _fence);
3488 if (result != VK_SUCCESS)
3489 return result;
3490
3491 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3492 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3493 &queue->device->empty_cs[queue->queue_family_index],
3494 1, NULL, NULL,
3495 &sem_info, NULL,
3496 false, base_fence);
3497 if (ret) {
3498 radv_loge("failed to submit CS %d\n", i);
3499 abort();
3500 }
3501
3502 fence_emitted = true;
3503 if (fence)
3504 fence->submitted = true;
3505 }
3506
3507 radv_free_sem_info(&sem_info);
3508
3509 }
3510
3511 if (fence) {
3512 if (!fence_emitted) {
3513 result = radv_signal_fence(queue, fence);
3514 if (result != VK_SUCCESS)
3515 return result;
3516 }
3517 fence->submitted = true;
3518 }
3519
3520 return VK_SUCCESS;
3521 }
3522
3523 VkResult radv_CreateFence(
3524 VkDevice _device,
3525 const VkFenceCreateInfo* pCreateInfo,
3526 const VkAllocationCallbacks* pAllocator,
3527 VkFence* pFence)
3528 {
3529 RADV_FROM_HANDLE(radv_device, device, _device);
3530 const VkExportFenceCreateInfo *export =
3531 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3532 VkExternalFenceHandleTypeFlags handleTypes =
3533 export ? export->handleTypes : 0;
3534
3535 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3536 sizeof(*fence), 8,
3537 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3538
3539 if (!fence)
3540 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3541
3542 fence->fence_wsi = NULL;
3543 fence->submitted = false;
3544 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3545 fence->temp_syncobj = 0;
3546 if (device->always_use_syncobj || handleTypes) {
3547 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3548 if (ret) {
3549 vk_free2(&device->alloc, pAllocator, fence);
3550 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3551 }
3552 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3553 device->ws->signal_syncobj(device->ws, fence->syncobj);
3554 }
3555 fence->fence = NULL;
3556 } else {
3557 fence->fence = device->ws->create_fence();
3558 if (!fence->fence) {
3559 vk_free2(&device->alloc, pAllocator, fence);
3560 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3561 }
3562 fence->syncobj = 0;
3563 }
3564
3565 *pFence = radv_fence_to_handle(fence);
3566
3567 return VK_SUCCESS;
3568 }
3569
3570 void radv_DestroyFence(
3571 VkDevice _device,
3572 VkFence _fence,
3573 const VkAllocationCallbacks* pAllocator)
3574 {
3575 RADV_FROM_HANDLE(radv_device, device, _device);
3576 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3577
3578 if (!fence)
3579 return;
3580
3581 if (fence->temp_syncobj)
3582 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3583 if (fence->syncobj)
3584 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3585 if (fence->fence)
3586 device->ws->destroy_fence(fence->fence);
3587 if (fence->fence_wsi)
3588 fence->fence_wsi->destroy(fence->fence_wsi);
3589 vk_free2(&device->alloc, pAllocator, fence);
3590 }
3591
3592
3593 static uint64_t radv_get_current_time()
3594 {
3595 struct timespec tv;
3596 clock_gettime(CLOCK_MONOTONIC, &tv);
3597 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3598 }
3599
3600 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3601 {
3602 uint64_t current_time = radv_get_current_time();
3603
3604 timeout = MIN2(UINT64_MAX - current_time, timeout);
3605
3606 return current_time + timeout;
3607 }
3608
3609
3610 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3611 {
3612 for (uint32_t i = 0; i < fenceCount; ++i) {
3613 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3614 if (fence->fence == NULL || fence->syncobj ||
3615 fence->temp_syncobj ||
3616 (!fence->signalled && !fence->submitted))
3617 return false;
3618 }
3619 return true;
3620 }
3621
3622 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3623 {
3624 for (uint32_t i = 0; i < fenceCount; ++i) {
3625 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3626 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3627 return false;
3628 }
3629 return true;
3630 }
3631
3632 VkResult radv_WaitForFences(
3633 VkDevice _device,
3634 uint32_t fenceCount,
3635 const VkFence* pFences,
3636 VkBool32 waitAll,
3637 uint64_t timeout)
3638 {
3639 RADV_FROM_HANDLE(radv_device, device, _device);
3640 timeout = radv_get_absolute_timeout(timeout);
3641
3642 if (device->always_use_syncobj &&
3643 radv_all_fences_syncobj(fenceCount, pFences))
3644 {
3645 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3646 if (!handles)
3647 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3648
3649 for (uint32_t i = 0; i < fenceCount; ++i) {
3650 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3651 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3652 }
3653
3654 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3655
3656 free(handles);
3657 return success ? VK_SUCCESS : VK_TIMEOUT;
3658 }
3659
3660 if (!waitAll && fenceCount > 1) {
3661 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3662 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3663 uint32_t wait_count = 0;
3664 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3665 if (!fences)
3666 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3667
3668 for (uint32_t i = 0; i < fenceCount; ++i) {
3669 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3670
3671 if (fence->signalled) {
3672 free(fences);
3673 return VK_SUCCESS;
3674 }
3675
3676 fences[wait_count++] = fence->fence;
3677 }
3678
3679 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3680 waitAll, timeout - radv_get_current_time());
3681
3682 free(fences);
3683 return success ? VK_SUCCESS : VK_TIMEOUT;
3684 }
3685
3686 while(radv_get_current_time() <= timeout) {
3687 for (uint32_t i = 0; i < fenceCount; ++i) {
3688 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3689 return VK_SUCCESS;
3690 }
3691 }
3692 return VK_TIMEOUT;
3693 }
3694
3695 for (uint32_t i = 0; i < fenceCount; ++i) {
3696 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3697 bool expired = false;
3698
3699 if (fence->temp_syncobj) {
3700 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3701 return VK_TIMEOUT;
3702 continue;
3703 }
3704
3705 if (fence->syncobj) {
3706 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3707 return VK_TIMEOUT;
3708 continue;
3709 }
3710
3711 if (fence->signalled)
3712 continue;
3713
3714 if (fence->fence) {
3715 if (!fence->submitted) {
3716 while(radv_get_current_time() <= timeout &&
3717 !fence->submitted)
3718 /* Do nothing */;
3719
3720 if (!fence->submitted)
3721 return VK_TIMEOUT;
3722
3723 /* Recheck as it may have been set by
3724 * submitting operations. */
3725
3726 if (fence->signalled)
3727 continue;
3728 }
3729
3730 expired = device->ws->fence_wait(device->ws,
3731 fence->fence,
3732 true, timeout);
3733 if (!expired)
3734 return VK_TIMEOUT;
3735 }
3736
3737 if (fence->fence_wsi) {
3738 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3739 if (result != VK_SUCCESS)
3740 return result;
3741 }
3742
3743 fence->signalled = true;
3744 }
3745
3746 return VK_SUCCESS;
3747 }
3748
3749 VkResult radv_ResetFences(VkDevice _device,
3750 uint32_t fenceCount,
3751 const VkFence *pFences)
3752 {
3753 RADV_FROM_HANDLE(radv_device, device, _device);
3754
3755 for (unsigned i = 0; i < fenceCount; ++i) {
3756 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3757 fence->submitted = fence->signalled = false;
3758
3759 /* Per spec, we first restore the permanent payload, and then reset, so
3760 * having a temp syncobj should not skip resetting the permanent syncobj. */
3761 if (fence->temp_syncobj) {
3762 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3763 fence->temp_syncobj = 0;
3764 }
3765
3766 if (fence->syncobj) {
3767 device->ws->reset_syncobj(device->ws, fence->syncobj);
3768 }
3769 }
3770
3771 return VK_SUCCESS;
3772 }
3773
3774 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3775 {
3776 RADV_FROM_HANDLE(radv_device, device, _device);
3777 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3778
3779 if (fence->temp_syncobj) {
3780 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3781 return success ? VK_SUCCESS : VK_NOT_READY;
3782 }
3783
3784 if (fence->syncobj) {
3785 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3786 return success ? VK_SUCCESS : VK_NOT_READY;
3787 }
3788
3789 if (fence->signalled)
3790 return VK_SUCCESS;
3791 if (!fence->submitted)
3792 return VK_NOT_READY;
3793 if (fence->fence) {
3794 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3795 return VK_NOT_READY;
3796 }
3797 if (fence->fence_wsi) {
3798 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
3799
3800 if (result != VK_SUCCESS) {
3801 if (result == VK_TIMEOUT)
3802 return VK_NOT_READY;
3803 return result;
3804 }
3805 }
3806 return VK_SUCCESS;
3807 }
3808
3809
3810 // Queue semaphore functions
3811
3812 VkResult radv_CreateSemaphore(
3813 VkDevice _device,
3814 const VkSemaphoreCreateInfo* pCreateInfo,
3815 const VkAllocationCallbacks* pAllocator,
3816 VkSemaphore* pSemaphore)
3817 {
3818 RADV_FROM_HANDLE(radv_device, device, _device);
3819 const VkExportSemaphoreCreateInfo *export =
3820 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
3821 VkExternalSemaphoreHandleTypeFlags handleTypes =
3822 export ? export->handleTypes : 0;
3823
3824 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3825 sizeof(*sem), 8,
3826 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3827 if (!sem)
3828 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3829
3830 sem->temp_syncobj = 0;
3831 /* create a syncobject if we are going to export this semaphore */
3832 if (device->always_use_syncobj || handleTypes) {
3833 assert (device->physical_device->rad_info.has_syncobj);
3834 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3835 if (ret) {
3836 vk_free2(&device->alloc, pAllocator, sem);
3837 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3838 }
3839 sem->sem = NULL;
3840 } else {
3841 sem->sem = device->ws->create_sem(device->ws);
3842 if (!sem->sem) {
3843 vk_free2(&device->alloc, pAllocator, sem);
3844 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3845 }
3846 sem->syncobj = 0;
3847 }
3848
3849 *pSemaphore = radv_semaphore_to_handle(sem);
3850 return VK_SUCCESS;
3851 }
3852
3853 void radv_DestroySemaphore(
3854 VkDevice _device,
3855 VkSemaphore _semaphore,
3856 const VkAllocationCallbacks* pAllocator)
3857 {
3858 RADV_FROM_HANDLE(radv_device, device, _device);
3859 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3860 if (!_semaphore)
3861 return;
3862
3863 if (sem->syncobj)
3864 device->ws->destroy_syncobj(device->ws, sem->syncobj);
3865 else
3866 device->ws->destroy_sem(sem->sem);
3867 vk_free2(&device->alloc, pAllocator, sem);
3868 }
3869
3870 VkResult radv_CreateEvent(
3871 VkDevice _device,
3872 const VkEventCreateInfo* pCreateInfo,
3873 const VkAllocationCallbacks* pAllocator,
3874 VkEvent* pEvent)
3875 {
3876 RADV_FROM_HANDLE(radv_device, device, _device);
3877 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
3878 sizeof(*event), 8,
3879 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3880
3881 if (!event)
3882 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3883
3884 event->bo = device->ws->buffer_create(device->ws, 8, 8,
3885 RADEON_DOMAIN_GTT,
3886 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
3887 if (!event->bo) {
3888 vk_free2(&device->alloc, pAllocator, event);
3889 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3890 }
3891
3892 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
3893
3894 *pEvent = radv_event_to_handle(event);
3895
3896 return VK_SUCCESS;
3897 }
3898
3899 void radv_DestroyEvent(
3900 VkDevice _device,
3901 VkEvent _event,
3902 const VkAllocationCallbacks* pAllocator)
3903 {
3904 RADV_FROM_HANDLE(radv_device, device, _device);
3905 RADV_FROM_HANDLE(radv_event, event, _event);
3906
3907 if (!event)
3908 return;
3909 device->ws->buffer_destroy(event->bo);
3910 vk_free2(&device->alloc, pAllocator, event);
3911 }
3912
3913 VkResult radv_GetEventStatus(
3914 VkDevice _device,
3915 VkEvent _event)
3916 {
3917 RADV_FROM_HANDLE(radv_event, event, _event);
3918
3919 if (*event->map == 1)
3920 return VK_EVENT_SET;
3921 return VK_EVENT_RESET;
3922 }
3923
3924 VkResult radv_SetEvent(
3925 VkDevice _device,
3926 VkEvent _event)
3927 {
3928 RADV_FROM_HANDLE(radv_event, event, _event);
3929 *event->map = 1;
3930
3931 return VK_SUCCESS;
3932 }
3933
3934 VkResult radv_ResetEvent(
3935 VkDevice _device,
3936 VkEvent _event)
3937 {
3938 RADV_FROM_HANDLE(radv_event, event, _event);
3939 *event->map = 0;
3940
3941 return VK_SUCCESS;
3942 }
3943
3944 VkResult radv_CreateBuffer(
3945 VkDevice _device,
3946 const VkBufferCreateInfo* pCreateInfo,
3947 const VkAllocationCallbacks* pAllocator,
3948 VkBuffer* pBuffer)
3949 {
3950 RADV_FROM_HANDLE(radv_device, device, _device);
3951 struct radv_buffer *buffer;
3952
3953 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
3954
3955 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
3956 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3957 if (buffer == NULL)
3958 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3959
3960 buffer->size = pCreateInfo->size;
3961 buffer->usage = pCreateInfo->usage;
3962 buffer->bo = NULL;
3963 buffer->offset = 0;
3964 buffer->flags = pCreateInfo->flags;
3965
3966 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
3967 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
3968
3969 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
3970 buffer->bo = device->ws->buffer_create(device->ws,
3971 align64(buffer->size, 4096),
3972 4096, 0, RADEON_FLAG_VIRTUAL);
3973 if (!buffer->bo) {
3974 vk_free2(&device->alloc, pAllocator, buffer);
3975 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3976 }
3977 }
3978
3979 *pBuffer = radv_buffer_to_handle(buffer);
3980
3981 return VK_SUCCESS;
3982 }
3983
3984 void radv_DestroyBuffer(
3985 VkDevice _device,
3986 VkBuffer _buffer,
3987 const VkAllocationCallbacks* pAllocator)
3988 {
3989 RADV_FROM_HANDLE(radv_device, device, _device);
3990 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3991
3992 if (!buffer)
3993 return;
3994
3995 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3996 device->ws->buffer_destroy(buffer->bo);
3997
3998 vk_free2(&device->alloc, pAllocator, buffer);
3999 }
4000
4001 static inline unsigned
4002 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
4003 {
4004 if (stencil)
4005 return image->surface.u.legacy.stencil_tiling_index[level];
4006 else
4007 return image->surface.u.legacy.tiling_index[level];
4008 }
4009
4010 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4011 {
4012 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4013 }
4014
4015 static uint32_t
4016 radv_init_dcc_control_reg(struct radv_device *device,
4017 struct radv_image_view *iview)
4018 {
4019 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4020 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4021 unsigned max_compressed_block_size;
4022 unsigned independent_64b_blocks;
4023
4024 if (!radv_image_has_dcc(iview->image))
4025 return 0;
4026
4027 if (iview->image->info.samples > 1) {
4028 if (iview->image->surface.bpe == 1)
4029 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4030 else if (iview->image->surface.bpe == 2)
4031 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4032 }
4033
4034 if (!device->physical_device->rad_info.has_dedicated_vram) {
4035 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4036 * dGPU and 64 for APU because all of our APUs to date use
4037 * DIMMs which have a request granularity size of 64B while all
4038 * other chips have a 32B request size.
4039 */
4040 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4041 }
4042
4043 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4044 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4045 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4046 /* If this DCC image is potentially going to be used in texture
4047 * fetches, we need some special settings.
4048 */
4049 independent_64b_blocks = 1;
4050 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4051 } else {
4052 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4053 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4054 * big as possible for better compression state.
4055 */
4056 independent_64b_blocks = 0;
4057 max_compressed_block_size = max_uncompressed_block_size;
4058 }
4059
4060 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4061 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4062 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4063 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
4064 }
4065
4066 static void
4067 radv_initialise_color_surface(struct radv_device *device,
4068 struct radv_color_buffer_info *cb,
4069 struct radv_image_view *iview)
4070 {
4071 const struct vk_format_description *desc;
4072 unsigned ntype, format, swap, endian;
4073 unsigned blend_clamp = 0, blend_bypass = 0;
4074 uint64_t va;
4075 const struct radeon_surf *surf = &iview->image->surface;
4076
4077 desc = vk_format_description(iview->vk_format);
4078
4079 memset(cb, 0, sizeof(*cb));
4080
4081 /* Intensity is implemented as Red, so treat it that way. */
4082 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4083
4084 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4085
4086 cb->cb_color_base = va >> 8;
4087
4088 if (device->physical_device->rad_info.chip_class >= GFX9) {
4089 struct gfx9_surf_meta_flags meta;
4090 if (iview->image->dcc_offset)
4091 meta = iview->image->surface.u.gfx9.dcc;
4092 else
4093 meta = iview->image->surface.u.gfx9.cmask;
4094
4095 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
4096 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
4097 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4098 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4099
4100 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
4101 cb->cb_color_base |= iview->image->surface.tile_swizzle;
4102 } else {
4103 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4104 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4105
4106 cb->cb_color_base += level_info->offset >> 8;
4107 if (level_info->mode == RADEON_SURF_MODE_2D)
4108 cb->cb_color_base |= iview->image->surface.tile_swizzle;
4109
4110 pitch_tile_max = level_info->nblk_x / 8 - 1;
4111 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4112 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
4113
4114 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4115 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4116 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
4117
4118 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4119
4120 if (radv_image_has_fmask(iview->image)) {
4121 if (device->physical_device->rad_info.chip_class >= CIK)
4122 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
4123 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
4124 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
4125 } else {
4126 /* This must be set for fast clear to work without FMASK. */
4127 if (device->physical_device->rad_info.chip_class >= CIK)
4128 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4129 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4130 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4131 }
4132 }
4133
4134 /* CMASK variables */
4135 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4136 va += iview->image->cmask.offset;
4137 cb->cb_color_cmask = va >> 8;
4138
4139 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4140 va += iview->image->dcc_offset;
4141 cb->cb_dcc_base = va >> 8;
4142 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
4143
4144 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4145 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4146 S_028C6C_SLICE_MAX(max_slice);
4147
4148 if (iview->image->info.samples > 1) {
4149 unsigned log_samples = util_logbase2(iview->image->info.samples);
4150
4151 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4152 S_028C74_NUM_FRAGMENTS(log_samples);
4153 }
4154
4155 if (radv_image_has_fmask(iview->image)) {
4156 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
4157 cb->cb_color_fmask = va >> 8;
4158 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
4159 } else {
4160 cb->cb_color_fmask = cb->cb_color_base;
4161 }
4162
4163 ntype = radv_translate_color_numformat(iview->vk_format,
4164 desc,
4165 vk_format_get_first_non_void_channel(iview->vk_format));
4166 format = radv_translate_colorformat(iview->vk_format);
4167 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4168 radv_finishme("Illegal color\n");
4169 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4170 endian = radv_colorformat_endian_swap(format);
4171
4172 /* blend clamp should be set for all NORM/SRGB types */
4173 if (ntype == V_028C70_NUMBER_UNORM ||
4174 ntype == V_028C70_NUMBER_SNORM ||
4175 ntype == V_028C70_NUMBER_SRGB)
4176 blend_clamp = 1;
4177
4178 /* set blend bypass according to docs if SINT/UINT or
4179 8/24 COLOR variants */
4180 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4181 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4182 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4183 blend_clamp = 0;
4184 blend_bypass = 1;
4185 }
4186 #if 0
4187 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4188 (format == V_028C70_COLOR_8 ||
4189 format == V_028C70_COLOR_8_8 ||
4190 format == V_028C70_COLOR_8_8_8_8))
4191 ->color_is_int8 = true;
4192 #endif
4193 cb->cb_color_info = S_028C70_FORMAT(format) |
4194 S_028C70_COMP_SWAP(swap) |
4195 S_028C70_BLEND_CLAMP(blend_clamp) |
4196 S_028C70_BLEND_BYPASS(blend_bypass) |
4197 S_028C70_SIMPLE_FLOAT(1) |
4198 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4199 ntype != V_028C70_NUMBER_SNORM &&
4200 ntype != V_028C70_NUMBER_SRGB &&
4201 format != V_028C70_COLOR_8_24 &&
4202 format != V_028C70_COLOR_24_8) |
4203 S_028C70_NUMBER_TYPE(ntype) |
4204 S_028C70_ENDIAN(endian);
4205 if (radv_image_has_fmask(iview->image)) {
4206 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4207 if (device->physical_device->rad_info.chip_class == SI) {
4208 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
4209 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4210 }
4211 }
4212
4213 if (radv_image_has_cmask(iview->image) &&
4214 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4215 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4216
4217 if (radv_dcc_enabled(iview->image, iview->base_mip))
4218 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4219
4220 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4221
4222 /* This must be set for fast clear to work without FMASK. */
4223 if (!radv_image_has_fmask(iview->image) &&
4224 device->physical_device->rad_info.chip_class == SI) {
4225 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
4226 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4227 }
4228
4229 if (device->physical_device->rad_info.chip_class >= GFX9) {
4230 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4231 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4232
4233 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
4234 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4235 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
4236 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
4237 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
4238 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4239 }
4240 }
4241
4242 static unsigned
4243 radv_calc_decompress_on_z_planes(struct radv_device *device,
4244 struct radv_image_view *iview)
4245 {
4246 unsigned max_zplanes = 0;
4247
4248 assert(radv_image_is_tc_compat_htile(iview->image));
4249
4250 if (device->physical_device->rad_info.chip_class >= GFX9) {
4251 /* Default value for 32-bit depth surfaces. */
4252 max_zplanes = 4;
4253
4254 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4255 iview->image->info.samples > 1)
4256 max_zplanes = 2;
4257
4258 max_zplanes = max_zplanes + 1;
4259 } else {
4260 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4261 /* Do not enable Z plane compression for 16-bit depth
4262 * surfaces because isn't supported on GFX8. Only
4263 * 32-bit depth surfaces are supported by the hardware.
4264 * This allows to maintain shader compatibility and to
4265 * reduce the number of depth decompressions.
4266 */
4267 max_zplanes = 1;
4268 } else {
4269 if (iview->image->info.samples <= 1)
4270 max_zplanes = 5;
4271 else if (iview->image->info.samples <= 4)
4272 max_zplanes = 3;
4273 else
4274 max_zplanes = 2;
4275 }
4276 }
4277
4278 return max_zplanes;
4279 }
4280
4281 static void
4282 radv_initialise_ds_surface(struct radv_device *device,
4283 struct radv_ds_buffer_info *ds,
4284 struct radv_image_view *iview)
4285 {
4286 unsigned level = iview->base_mip;
4287 unsigned format, stencil_format;
4288 uint64_t va, s_offs, z_offs;
4289 bool stencil_only = false;
4290 memset(ds, 0, sizeof(*ds));
4291 switch (iview->image->vk_format) {
4292 case VK_FORMAT_D24_UNORM_S8_UINT:
4293 case VK_FORMAT_X8_D24_UNORM_PACK32:
4294 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4295 ds->offset_scale = 2.0f;
4296 break;
4297 case VK_FORMAT_D16_UNORM:
4298 case VK_FORMAT_D16_UNORM_S8_UINT:
4299 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4300 ds->offset_scale = 4.0f;
4301 break;
4302 case VK_FORMAT_D32_SFLOAT:
4303 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4304 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4305 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4306 ds->offset_scale = 1.0f;
4307 break;
4308 case VK_FORMAT_S8_UINT:
4309 stencil_only = true;
4310 break;
4311 default:
4312 break;
4313 }
4314
4315 format = radv_translate_dbformat(iview->image->vk_format);
4316 stencil_format = iview->image->surface.has_stencil ?
4317 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4318
4319 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4320 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4321 S_028008_SLICE_MAX(max_slice);
4322
4323 ds->db_htile_data_base = 0;
4324 ds->db_htile_surface = 0;
4325
4326 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4327 s_offs = z_offs = va;
4328
4329 if (device->physical_device->rad_info.chip_class >= GFX9) {
4330 assert(iview->image->surface.u.gfx9.surf_offset == 0);
4331 s_offs += iview->image->surface.u.gfx9.stencil_offset;
4332
4333 ds->db_z_info = S_028038_FORMAT(format) |
4334 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4335 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
4336 S_028038_MAXMIP(iview->image->info.levels - 1) |
4337 S_028038_ZRANGE_PRECISION(1);
4338 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4339 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
4340
4341 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
4342 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
4343 ds->db_depth_view |= S_028008_MIPID(level);
4344
4345 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4346 S_02801C_Y_MAX(iview->image->info.height - 1);
4347
4348 if (radv_htile_enabled(iview->image, level)) {
4349 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4350
4351 if (radv_image_is_tc_compat_htile(iview->image)) {
4352 unsigned max_zplanes =
4353 radv_calc_decompress_on_z_planes(device, iview);
4354
4355 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
4356 S_028038_ITERATE_FLUSH(1);
4357 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4358 }
4359
4360 if (!iview->image->surface.has_stencil)
4361 /* Use all of the htile_buffer for depth if there's no stencil. */
4362 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4363 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4364 iview->image->htile_offset;
4365 ds->db_htile_data_base = va >> 8;
4366 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4367 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
4368 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
4369 }
4370 } else {
4371 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
4372
4373 if (stencil_only)
4374 level_info = &iview->image->surface.u.legacy.stencil_level[level];
4375
4376 z_offs += iview->image->surface.u.legacy.level[level].offset;
4377 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
4378
4379 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4380 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4381 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4382
4383 if (iview->image->info.samples > 1)
4384 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4385
4386 if (device->physical_device->rad_info.chip_class >= CIK) {
4387 struct radeon_info *info = &device->physical_device->rad_info;
4388 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
4389 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
4390 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
4391 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4392 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4393 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4394
4395 if (stencil_only)
4396 tile_mode = stencil_tile_mode;
4397
4398 ds->db_depth_info |=
4399 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4400 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4401 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4402 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4403 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4404 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4405 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4406 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4407 } else {
4408 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
4409 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4410 tile_mode_index = si_tile_mode_index(iview->image, level, true);
4411 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4412 if (stencil_only)
4413 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4414 }
4415
4416 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4417 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4418 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4419
4420 if (radv_htile_enabled(iview->image, level)) {
4421 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4422
4423 if (!iview->image->surface.has_stencil &&
4424 !radv_image_is_tc_compat_htile(iview->image))
4425 /* Use all of the htile_buffer for depth if there's no stencil. */
4426 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4427
4428 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4429 iview->image->htile_offset;
4430 ds->db_htile_data_base = va >> 8;
4431 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4432
4433 if (radv_image_is_tc_compat_htile(iview->image)) {
4434 unsigned max_zplanes =
4435 radv_calc_decompress_on_z_planes(device, iview);
4436
4437 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4438 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4439 }
4440 }
4441 }
4442
4443 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4444 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4445 }
4446
4447 VkResult radv_CreateFramebuffer(
4448 VkDevice _device,
4449 const VkFramebufferCreateInfo* pCreateInfo,
4450 const VkAllocationCallbacks* pAllocator,
4451 VkFramebuffer* pFramebuffer)
4452 {
4453 RADV_FROM_HANDLE(radv_device, device, _device);
4454 struct radv_framebuffer *framebuffer;
4455
4456 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4457
4458 size_t size = sizeof(*framebuffer) +
4459 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4460 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4461 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4462 if (framebuffer == NULL)
4463 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4464
4465 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4466 framebuffer->width = pCreateInfo->width;
4467 framebuffer->height = pCreateInfo->height;
4468 framebuffer->layers = pCreateInfo->layers;
4469 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4470 VkImageView _iview = pCreateInfo->pAttachments[i];
4471 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4472 framebuffer->attachments[i].attachment = iview;
4473 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
4474 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4475 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4476 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4477 }
4478 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4479 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4480 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4481 }
4482
4483 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4484 return VK_SUCCESS;
4485 }
4486
4487 void radv_DestroyFramebuffer(
4488 VkDevice _device,
4489 VkFramebuffer _fb,
4490 const VkAllocationCallbacks* pAllocator)
4491 {
4492 RADV_FROM_HANDLE(radv_device, device, _device);
4493 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4494
4495 if (!fb)
4496 return;
4497 vk_free2(&device->alloc, pAllocator, fb);
4498 }
4499
4500 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4501 {
4502 switch (address_mode) {
4503 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4504 return V_008F30_SQ_TEX_WRAP;
4505 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4506 return V_008F30_SQ_TEX_MIRROR;
4507 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4508 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4509 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4510 return V_008F30_SQ_TEX_CLAMP_BORDER;
4511 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4512 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4513 default:
4514 unreachable("illegal tex wrap mode");
4515 break;
4516 }
4517 }
4518
4519 static unsigned
4520 radv_tex_compare(VkCompareOp op)
4521 {
4522 switch (op) {
4523 case VK_COMPARE_OP_NEVER:
4524 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4525 case VK_COMPARE_OP_LESS:
4526 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4527 case VK_COMPARE_OP_EQUAL:
4528 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4529 case VK_COMPARE_OP_LESS_OR_EQUAL:
4530 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4531 case VK_COMPARE_OP_GREATER:
4532 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4533 case VK_COMPARE_OP_NOT_EQUAL:
4534 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4535 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4536 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4537 case VK_COMPARE_OP_ALWAYS:
4538 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4539 default:
4540 unreachable("illegal compare mode");
4541 break;
4542 }
4543 }
4544
4545 static unsigned
4546 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4547 {
4548 switch (filter) {
4549 case VK_FILTER_NEAREST:
4550 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4551 V_008F38_SQ_TEX_XY_FILTER_POINT);
4552 case VK_FILTER_LINEAR:
4553 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4554 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4555 case VK_FILTER_CUBIC_IMG:
4556 default:
4557 fprintf(stderr, "illegal texture filter");
4558 return 0;
4559 }
4560 }
4561
4562 static unsigned
4563 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4564 {
4565 switch (mode) {
4566 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4567 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4568 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4569 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4570 default:
4571 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4572 }
4573 }
4574
4575 static unsigned
4576 radv_tex_bordercolor(VkBorderColor bcolor)
4577 {
4578 switch (bcolor) {
4579 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4580 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4581 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4582 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4583 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4584 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4585 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4586 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4587 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4588 default:
4589 break;
4590 }
4591 return 0;
4592 }
4593
4594 static unsigned
4595 radv_tex_aniso_filter(unsigned filter)
4596 {
4597 if (filter < 2)
4598 return 0;
4599 if (filter < 4)
4600 return 1;
4601 if (filter < 8)
4602 return 2;
4603 if (filter < 16)
4604 return 3;
4605 return 4;
4606 }
4607
4608 static unsigned
4609 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4610 {
4611 switch (mode) {
4612 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4613 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4614 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4615 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
4616 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4617 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
4618 default:
4619 break;
4620 }
4621 return 0;
4622 }
4623
4624 static uint32_t
4625 radv_get_max_anisotropy(struct radv_device *device,
4626 const VkSamplerCreateInfo *pCreateInfo)
4627 {
4628 if (device->force_aniso >= 0)
4629 return device->force_aniso;
4630
4631 if (pCreateInfo->anisotropyEnable &&
4632 pCreateInfo->maxAnisotropy > 1.0f)
4633 return (uint32_t)pCreateInfo->maxAnisotropy;
4634
4635 return 0;
4636 }
4637
4638 static void
4639 radv_init_sampler(struct radv_device *device,
4640 struct radv_sampler *sampler,
4641 const VkSamplerCreateInfo *pCreateInfo)
4642 {
4643 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
4644 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4645 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4646 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4647
4648 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4649 vk_find_struct_const(pCreateInfo->pNext,
4650 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4651 if (sampler_reduction)
4652 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4653
4654 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4655 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4656 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4657 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4658 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4659 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4660 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4661 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4662 S_008F30_DISABLE_CUBE_WRAP(0) |
4663 S_008F30_COMPAT_MODE(is_vi) |
4664 S_008F30_FILTER_MODE(filter_mode));
4665 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4666 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4667 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4668 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4669 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4670 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4671 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4672 S_008F38_MIP_POINT_PRECLAMP(0) |
4673 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4674 S_008F38_FILTER_PREC_FIX(1) |
4675 S_008F38_ANISO_OVERRIDE(is_vi));
4676 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4677 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4678 }
4679
4680 VkResult radv_CreateSampler(
4681 VkDevice _device,
4682 const VkSamplerCreateInfo* pCreateInfo,
4683 const VkAllocationCallbacks* pAllocator,
4684 VkSampler* pSampler)
4685 {
4686 RADV_FROM_HANDLE(radv_device, device, _device);
4687 struct radv_sampler *sampler;
4688
4689 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4690
4691 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4692 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4693 if (!sampler)
4694 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4695
4696 radv_init_sampler(device, sampler, pCreateInfo);
4697 *pSampler = radv_sampler_to_handle(sampler);
4698
4699 return VK_SUCCESS;
4700 }
4701
4702 void radv_DestroySampler(
4703 VkDevice _device,
4704 VkSampler _sampler,
4705 const VkAllocationCallbacks* pAllocator)
4706 {
4707 RADV_FROM_HANDLE(radv_device, device, _device);
4708 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4709
4710 if (!sampler)
4711 return;
4712 vk_free2(&device->alloc, pAllocator, sampler);
4713 }
4714
4715 /* vk_icd.h does not declare this function, so we declare it here to
4716 * suppress Wmissing-prototypes.
4717 */
4718 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4719 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4720
4721 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4722 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4723 {
4724 /* For the full details on loader interface versioning, see
4725 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4726 * What follows is a condensed summary, to help you navigate the large and
4727 * confusing official doc.
4728 *
4729 * - Loader interface v0 is incompatible with later versions. We don't
4730 * support it.
4731 *
4732 * - In loader interface v1:
4733 * - The first ICD entrypoint called by the loader is
4734 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4735 * entrypoint.
4736 * - The ICD must statically expose no other Vulkan symbol unless it is
4737 * linked with -Bsymbolic.
4738 * - Each dispatchable Vulkan handle created by the ICD must be
4739 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4740 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4741 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4742 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4743 * such loader-managed surfaces.
4744 *
4745 * - Loader interface v2 differs from v1 in:
4746 * - The first ICD entrypoint called by the loader is
4747 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4748 * statically expose this entrypoint.
4749 *
4750 * - Loader interface v3 differs from v2 in:
4751 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4752 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4753 * because the loader no longer does so.
4754 */
4755 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4756 return VK_SUCCESS;
4757 }
4758
4759 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4760 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4761 int *pFD)
4762 {
4763 RADV_FROM_HANDLE(radv_device, device, _device);
4764 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4765
4766 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4767
4768 /* At the moment, we support only the below handle types. */
4769 assert(pGetFdInfo->handleType ==
4770 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
4771 pGetFdInfo->handleType ==
4772 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4773
4774 bool ret = radv_get_memory_fd(device, memory, pFD);
4775 if (ret == false)
4776 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4777 return VK_SUCCESS;
4778 }
4779
4780 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4781 VkExternalMemoryHandleTypeFlagBits handleType,
4782 int fd,
4783 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4784 {
4785 RADV_FROM_HANDLE(radv_device, device, _device);
4786
4787 switch (handleType) {
4788 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4789 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4790 return VK_SUCCESS;
4791
4792 default:
4793 /* The valid usage section for this function says:
4794 *
4795 * "handleType must not be one of the handle types defined as
4796 * opaque."
4797 *
4798 * So opaque handle types fall into the default "unsupported" case.
4799 */
4800 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4801 }
4802 }
4803
4804 static VkResult radv_import_opaque_fd(struct radv_device *device,
4805 int fd,
4806 uint32_t *syncobj)
4807 {
4808 uint32_t syncobj_handle = 0;
4809 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4810 if (ret != 0)
4811 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4812
4813 if (*syncobj)
4814 device->ws->destroy_syncobj(device->ws, *syncobj);
4815
4816 *syncobj = syncobj_handle;
4817 close(fd);
4818
4819 return VK_SUCCESS;
4820 }
4821
4822 static VkResult radv_import_sync_fd(struct radv_device *device,
4823 int fd,
4824 uint32_t *syncobj)
4825 {
4826 /* If we create a syncobj we do it locally so that if we have an error, we don't
4827 * leave a syncobj in an undetermined state in the fence. */
4828 uint32_t syncobj_handle = *syncobj;
4829 if (!syncobj_handle) {
4830 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4831 if (ret) {
4832 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4833 }
4834 }
4835
4836 if (fd == -1) {
4837 device->ws->signal_syncobj(device->ws, syncobj_handle);
4838 } else {
4839 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
4840 if (ret != 0)
4841 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4842 }
4843
4844 *syncobj = syncobj_handle;
4845 if (fd != -1)
4846 close(fd);
4847
4848 return VK_SUCCESS;
4849 }
4850
4851 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
4852 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
4853 {
4854 RADV_FROM_HANDLE(radv_device, device, _device);
4855 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
4856 uint32_t *syncobj_dst = NULL;
4857
4858 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
4859 syncobj_dst = &sem->temp_syncobj;
4860 } else {
4861 syncobj_dst = &sem->syncobj;
4862 }
4863
4864 switch(pImportSemaphoreFdInfo->handleType) {
4865 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
4866 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4867 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
4868 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4869 default:
4870 unreachable("Unhandled semaphore handle type");
4871 }
4872 }
4873
4874 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
4875 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
4876 int *pFd)
4877 {
4878 RADV_FROM_HANDLE(radv_device, device, _device);
4879 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
4880 int ret;
4881 uint32_t syncobj_handle;
4882
4883 if (sem->temp_syncobj)
4884 syncobj_handle = sem->temp_syncobj;
4885 else
4886 syncobj_handle = sem->syncobj;
4887
4888 switch(pGetFdInfo->handleType) {
4889 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
4890 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4891 break;
4892 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
4893 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4894 if (!ret) {
4895 if (sem->temp_syncobj) {
4896 close (sem->temp_syncobj);
4897 sem->temp_syncobj = 0;
4898 } else {
4899 device->ws->reset_syncobj(device->ws, syncobj_handle);
4900 }
4901 }
4902 break;
4903 default:
4904 unreachable("Unhandled semaphore handle type");
4905 }
4906
4907 if (ret)
4908 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4909 return VK_SUCCESS;
4910 }
4911
4912 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
4913 VkPhysicalDevice physicalDevice,
4914 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
4915 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
4916 {
4917 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4918
4919 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
4920 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4921 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
4922 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
4923 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
4924 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
4925 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
4926 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
4927 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
4928 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
4929 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
4930 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
4931 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
4932 } else {
4933 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
4934 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
4935 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
4936 }
4937 }
4938
4939 VkResult radv_ImportFenceFdKHR(VkDevice _device,
4940 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
4941 {
4942 RADV_FROM_HANDLE(radv_device, device, _device);
4943 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
4944 uint32_t *syncobj_dst = NULL;
4945
4946
4947 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
4948 syncobj_dst = &fence->temp_syncobj;
4949 } else {
4950 syncobj_dst = &fence->syncobj;
4951 }
4952
4953 switch(pImportFenceFdInfo->handleType) {
4954 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
4955 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4956 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
4957 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4958 default:
4959 unreachable("Unhandled fence handle type");
4960 }
4961 }
4962
4963 VkResult radv_GetFenceFdKHR(VkDevice _device,
4964 const VkFenceGetFdInfoKHR *pGetFdInfo,
4965 int *pFd)
4966 {
4967 RADV_FROM_HANDLE(radv_device, device, _device);
4968 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
4969 int ret;
4970 uint32_t syncobj_handle;
4971
4972 if (fence->temp_syncobj)
4973 syncobj_handle = fence->temp_syncobj;
4974 else
4975 syncobj_handle = fence->syncobj;
4976
4977 switch(pGetFdInfo->handleType) {
4978 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
4979 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4980 break;
4981 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
4982 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4983 if (!ret) {
4984 if (fence->temp_syncobj) {
4985 close (fence->temp_syncobj);
4986 fence->temp_syncobj = 0;
4987 } else {
4988 device->ws->reset_syncobj(device->ws, syncobj_handle);
4989 }
4990 }
4991 break;
4992 default:
4993 unreachable("Unhandled fence handle type");
4994 }
4995
4996 if (ret)
4997 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4998 return VK_SUCCESS;
4999 }
5000
5001 void radv_GetPhysicalDeviceExternalFenceProperties(
5002 VkPhysicalDevice physicalDevice,
5003 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5004 VkExternalFenceProperties *pExternalFenceProperties)
5005 {
5006 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5007
5008 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5009 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5010 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5011 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5012 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5013 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5014 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5015 } else {
5016 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5017 pExternalFenceProperties->compatibleHandleTypes = 0;
5018 pExternalFenceProperties->externalFenceFeatures = 0;
5019 }
5020 }
5021
5022 VkResult
5023 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5024 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5025 const VkAllocationCallbacks* pAllocator,
5026 VkDebugReportCallbackEXT* pCallback)
5027 {
5028 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5029 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5030 pCreateInfo, pAllocator, &instance->alloc,
5031 pCallback);
5032 }
5033
5034 void
5035 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5036 VkDebugReportCallbackEXT _callback,
5037 const VkAllocationCallbacks* pAllocator)
5038 {
5039 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5040 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5041 _callback, pAllocator, &instance->alloc);
5042 }
5043
5044 void
5045 radv_DebugReportMessageEXT(VkInstance _instance,
5046 VkDebugReportFlagsEXT flags,
5047 VkDebugReportObjectTypeEXT objectType,
5048 uint64_t object,
5049 size_t location,
5050 int32_t messageCode,
5051 const char* pLayerPrefix,
5052 const char* pMessage)
5053 {
5054 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5055 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5056 object, location, messageCode, pLayerPrefix, pMessage);
5057 }
5058
5059 void
5060 radv_GetDeviceGroupPeerMemoryFeatures(
5061 VkDevice device,
5062 uint32_t heapIndex,
5063 uint32_t localDeviceIndex,
5064 uint32_t remoteDeviceIndex,
5065 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5066 {
5067 assert(localDeviceIndex == remoteDeviceIndex);
5068
5069 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5070 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5071 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5072 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5073 }
5074
5075 static const VkTimeDomainEXT radv_time_domains[] = {
5076 VK_TIME_DOMAIN_DEVICE_EXT,
5077 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5078 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5079 };
5080
5081 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5082 VkPhysicalDevice physicalDevice,
5083 uint32_t *pTimeDomainCount,
5084 VkTimeDomainEXT *pTimeDomains)
5085 {
5086 int d;
5087 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5088
5089 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5090 vk_outarray_append(&out, i) {
5091 *i = radv_time_domains[d];
5092 }
5093 }
5094
5095 return vk_outarray_status(&out);
5096 }
5097
5098 static uint64_t
5099 radv_clock_gettime(clockid_t clock_id)
5100 {
5101 struct timespec current;
5102 int ret;
5103
5104 ret = clock_gettime(clock_id, &current);
5105 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5106 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5107 if (ret < 0)
5108 return 0;
5109
5110 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5111 }
5112
5113 VkResult radv_GetCalibratedTimestampsEXT(
5114 VkDevice _device,
5115 uint32_t timestampCount,
5116 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5117 uint64_t *pTimestamps,
5118 uint64_t *pMaxDeviation)
5119 {
5120 RADV_FROM_HANDLE(radv_device, device, _device);
5121 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5122 int d;
5123 uint64_t begin, end;
5124 uint64_t max_clock_period = 0;
5125
5126 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5127
5128 for (d = 0; d < timestampCount; d++) {
5129 switch (pTimestampInfos[d].timeDomain) {
5130 case VK_TIME_DOMAIN_DEVICE_EXT:
5131 pTimestamps[d] = device->ws->query_value(device->ws,
5132 RADEON_TIMESTAMP);
5133 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5134 max_clock_period = MAX2(max_clock_period, device_period);
5135 break;
5136 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5137 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5138 max_clock_period = MAX2(max_clock_period, 1);
5139 break;
5140
5141 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5142 pTimestamps[d] = begin;
5143 break;
5144 default:
5145 pTimestamps[d] = 0;
5146 break;
5147 }
5148 }
5149
5150 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5151
5152 /*
5153 * The maximum deviation is the sum of the interval over which we
5154 * perform the sampling and the maximum period of any sampled
5155 * clock. That's because the maximum skew between any two sampled
5156 * clock edges is when the sampled clock with the largest period is
5157 * sampled at the end of that period but right at the beginning of the
5158 * sampling interval and some other clock is sampled right at the
5159 * begining of its sampling period and right at the end of the
5160 * sampling interval. Let's assume the GPU has the longest clock
5161 * period and that the application is sampling GPU and monotonic:
5162 *
5163 * s e
5164 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5165 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5166 *
5167 * g
5168 * 0 1 2 3
5169 * GPU -----_____-----_____-----_____-----_____
5170 *
5171 * m
5172 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5173 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5174 *
5175 * Interval <----------------->
5176 * Deviation <-------------------------->
5177 *
5178 * s = read(raw) 2
5179 * g = read(GPU) 1
5180 * m = read(monotonic) 2
5181 * e = read(raw) b
5182 *
5183 * We round the sample interval up by one tick to cover sampling error
5184 * in the interval clock
5185 */
5186
5187 uint64_t sample_interval = end - begin + 1;
5188
5189 *pMaxDeviation = sample_interval + max_clock_period;
5190
5191 return VK_SUCCESS;
5192 }