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50dbe061d50cb38e57cd7919aceb51d45edf274d
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "gfx9d.h"
47 #include "util/debug.h"
48
49 static int
50 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
51 {
52 uint32_t mesa_timestamp, llvm_timestamp;
53 uint16_t f = family;
54 memset(uuid, 0, VK_UUID_SIZE);
55 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
56 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
57 return -1;
58
59 memcpy(uuid, &mesa_timestamp, 4);
60 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
61 memcpy((char*)uuid + 8, &f, 2);
62 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
63 return 0;
64 }
65
66 static void
67 radv_get_driver_uuid(void *uuid)
68 {
69 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
70 }
71
72 static void
73 radv_get_device_uuid(struct radeon_info *info, void *uuid)
74 {
75 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
76 }
77
78 static const char *
79 get_chip_name(enum radeon_family family)
80 {
81 switch (family) {
82 case CHIP_TAHITI: return "AMD RADV TAHITI";
83 case CHIP_PITCAIRN: return "AMD RADV PITCAIRN";
84 case CHIP_VERDE: return "AMD RADV CAPE VERDE";
85 case CHIP_OLAND: return "AMD RADV OLAND";
86 case CHIP_HAINAN: return "AMD RADV HAINAN";
87 case CHIP_BONAIRE: return "AMD RADV BONAIRE";
88 case CHIP_KAVERI: return "AMD RADV KAVERI";
89 case CHIP_KABINI: return "AMD RADV KABINI";
90 case CHIP_HAWAII: return "AMD RADV HAWAII";
91 case CHIP_MULLINS: return "AMD RADV MULLINS";
92 case CHIP_TONGA: return "AMD RADV TONGA";
93 case CHIP_ICELAND: return "AMD RADV ICELAND";
94 case CHIP_CARRIZO: return "AMD RADV CARRIZO";
95 case CHIP_FIJI: return "AMD RADV FIJI";
96 case CHIP_POLARIS10: return "AMD RADV POLARIS10";
97 case CHIP_POLARIS11: return "AMD RADV POLARIS11";
98 case CHIP_POLARIS12: return "AMD RADV POLARIS12";
99 case CHIP_STONEY: return "AMD RADV STONEY";
100 case CHIP_VEGA10: return "AMD RADV VEGA";
101 case CHIP_RAVEN: return "AMD RADV RAVEN";
102 default: return "AMD RADV unknown";
103 }
104 }
105
106 static void
107 radv_physical_device_init_mem_types(struct radv_physical_device *device)
108 {
109 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
110 uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
111 device->rad_info.vram_vis_size);
112
113 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
114 device->memory_properties.memoryHeapCount = 0;
115 if (device->rad_info.vram_size - visible_vram_size > 0) {
116 vram_index = device->memory_properties.memoryHeapCount++;
117 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
118 .size = device->rad_info.vram_size - visible_vram_size,
119 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
120 };
121 }
122 if (visible_vram_size) {
123 visible_vram_index = device->memory_properties.memoryHeapCount++;
124 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
125 .size = visible_vram_size,
126 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
127 };
128 }
129 if (device->rad_info.gart_size > 0) {
130 gart_index = device->memory_properties.memoryHeapCount++;
131 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
132 .size = device->rad_info.gart_size,
133 .flags = 0,
134 };
135 }
136
137 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
138 unsigned type_count = 0;
139 if (vram_index >= 0) {
140 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
141 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
142 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
143 .heapIndex = vram_index,
144 };
145 }
146 if (gart_index >= 0) {
147 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
148 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
149 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
150 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
151 .heapIndex = gart_index,
152 };
153 }
154 if (visible_vram_index >= 0) {
155 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
156 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
157 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
158 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
159 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
160 .heapIndex = visible_vram_index,
161 };
162 }
163 if (gart_index >= 0) {
164 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
165 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
166 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
167 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
168 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
169 .heapIndex = gart_index,
170 };
171 }
172 device->memory_properties.memoryTypeCount = type_count;
173 }
174
175 static VkResult
176 radv_physical_device_init(struct radv_physical_device *device,
177 struct radv_instance *instance,
178 drmDevicePtr drm_device)
179 {
180 const char *path = drm_device->nodes[DRM_NODE_RENDER];
181 VkResult result;
182 drmVersionPtr version;
183 int fd;
184
185 fd = open(path, O_RDWR | O_CLOEXEC);
186 if (fd < 0)
187 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
188
189 version = drmGetVersion(fd);
190 if (!version) {
191 close(fd);
192 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
193 "failed to get version %s: %m", path);
194 }
195
196 if (strcmp(version->name, "amdgpu")) {
197 drmFreeVersion(version);
198 close(fd);
199 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
200 }
201 drmFreeVersion(version);
202
203 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
204 device->instance = instance;
205 assert(strlen(path) < ARRAY_SIZE(device->path));
206 strncpy(device->path, path, ARRAY_SIZE(device->path));
207
208 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
209 instance->perftest_flags);
210 if (!device->ws) {
211 result = VK_ERROR_INCOMPATIBLE_DRIVER;
212 goto fail;
213 }
214
215 device->local_fd = fd;
216 device->ws->query_info(device->ws, &device->rad_info);
217 result = radv_init_wsi(device);
218 if (result != VK_SUCCESS) {
219 device->ws->destroy(device->ws);
220 goto fail;
221 }
222
223 device->name = get_chip_name(device->rad_info.family);
224
225 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
226 radv_finish_wsi(device);
227 device->ws->destroy(device->ws);
228 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
229 "cannot generate UUID");
230 goto fail;
231 }
232
233 /* These flags affect shader compilation. */
234 uint64_t shader_env_flags =
235 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
236 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
237
238 /* The gpu id is already embeded in the uuid so we just pass "radv"
239 * when creating the cache.
240 */
241 char buf[VK_UUID_SIZE * 2 + 1];
242 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
243 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
244
245 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
246
247 radv_get_driver_uuid(&device->device_uuid);
248 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
249
250 if (device->rad_info.family == CHIP_STONEY ||
251 device->rad_info.chip_class >= GFX9) {
252 device->has_rbplus = true;
253 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY;
254 }
255
256 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
257 * on SI.
258 */
259 device->has_clear_state = device->rad_info.chip_class >= CIK;
260
261 radv_physical_device_init_mem_types(device);
262 return VK_SUCCESS;
263
264 fail:
265 close(fd);
266 return result;
267 }
268
269 static void
270 radv_physical_device_finish(struct radv_physical_device *device)
271 {
272 radv_finish_wsi(device);
273 device->ws->destroy(device->ws);
274 disk_cache_destroy(device->disk_cache);
275 close(device->local_fd);
276 }
277
278 static void *
279 default_alloc_func(void *pUserData, size_t size, size_t align,
280 VkSystemAllocationScope allocationScope)
281 {
282 return malloc(size);
283 }
284
285 static void *
286 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
287 size_t align, VkSystemAllocationScope allocationScope)
288 {
289 return realloc(pOriginal, size);
290 }
291
292 static void
293 default_free_func(void *pUserData, void *pMemory)
294 {
295 free(pMemory);
296 }
297
298 static const VkAllocationCallbacks default_alloc = {
299 .pUserData = NULL,
300 .pfnAllocation = default_alloc_func,
301 .pfnReallocation = default_realloc_func,
302 .pfnFree = default_free_func,
303 };
304
305 static const struct debug_control radv_debug_options[] = {
306 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
307 {"nodcc", RADV_DEBUG_NO_DCC},
308 {"shaders", RADV_DEBUG_DUMP_SHADERS},
309 {"nocache", RADV_DEBUG_NO_CACHE},
310 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
311 {"nohiz", RADV_DEBUG_NO_HIZ},
312 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
313 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
314 {"allbos", RADV_DEBUG_ALL_BOS},
315 {"noibs", RADV_DEBUG_NO_IBS},
316 {"spirv", RADV_DEBUG_DUMP_SPIRV},
317 {"vmfaults", RADV_DEBUG_VM_FAULTS},
318 {"zerovram", RADV_DEBUG_ZERO_VRAM},
319 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
320 {"nosisched", RADV_DEBUG_NO_SISCHED},
321 {NULL, 0}
322 };
323
324 const char *
325 radv_get_debug_option_name(int id)
326 {
327 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
328 return radv_debug_options[id].string;
329 }
330
331 static const struct debug_control radv_perftest_options[] = {
332 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
333 {"sisched", RADV_PERFTEST_SISCHED},
334 {NULL, 0}
335 };
336
337 const char *
338 radv_get_perftest_option_name(int id)
339 {
340 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
341 return radv_perftest_options[id].string;
342 }
343
344 static void
345 radv_handle_per_app_options(struct radv_instance *instance,
346 const VkApplicationInfo *info)
347 {
348 const char *name = info ? info->pApplicationName : NULL;
349
350 if (!name)
351 return;
352
353 if (!strcmp(name, "Talos - Linux - 32bit") ||
354 !strcmp(name, "Talos - Linux - 64bit")) {
355 /* Force enable LLVM sisched for Talos because it looks safe
356 * and it gives few more FPS.
357 */
358 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
359 }
360 }
361
362 VkResult radv_CreateInstance(
363 const VkInstanceCreateInfo* pCreateInfo,
364 const VkAllocationCallbacks* pAllocator,
365 VkInstance* pInstance)
366 {
367 struct radv_instance *instance;
368
369 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
370
371 uint32_t client_version;
372 if (pCreateInfo->pApplicationInfo &&
373 pCreateInfo->pApplicationInfo->apiVersion != 0) {
374 client_version = pCreateInfo->pApplicationInfo->apiVersion;
375 } else {
376 client_version = VK_MAKE_VERSION(1, 0, 0);
377 }
378
379 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
380 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
381 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
382 "Client requested version %d.%d.%d",
383 VK_VERSION_MAJOR(client_version),
384 VK_VERSION_MINOR(client_version),
385 VK_VERSION_PATCH(client_version));
386 }
387
388 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
389 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
390 if (!radv_instance_extension_supported(ext_name))
391 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
392 }
393
394 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
395 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
396 if (!instance)
397 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
398
399 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
400
401 if (pAllocator)
402 instance->alloc = *pAllocator;
403 else
404 instance->alloc = default_alloc;
405
406 instance->apiVersion = client_version;
407 instance->physicalDeviceCount = -1;
408
409 _mesa_locale_init();
410
411 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
412
413 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
414 radv_debug_options);
415
416 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
417 radv_perftest_options);
418
419 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
420
421 if (instance->debug_flags & RADV_DEBUG_NO_SISCHED) {
422 /* Disable sisched when the user requests it, this is mostly
423 * useful when the driver force-enable sisched for the given
424 * application.
425 */
426 instance->perftest_flags &= ~RADV_PERFTEST_SISCHED;
427 }
428
429 *pInstance = radv_instance_to_handle(instance);
430
431 return VK_SUCCESS;
432 }
433
434 void radv_DestroyInstance(
435 VkInstance _instance,
436 const VkAllocationCallbacks* pAllocator)
437 {
438 RADV_FROM_HANDLE(radv_instance, instance, _instance);
439
440 if (!instance)
441 return;
442
443 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
444 radv_physical_device_finish(instance->physicalDevices + i);
445 }
446
447 VG(VALGRIND_DESTROY_MEMPOOL(instance));
448
449 _mesa_locale_fini();
450
451 vk_free(&instance->alloc, instance);
452 }
453
454 static VkResult
455 radv_enumerate_devices(struct radv_instance *instance)
456 {
457 /* TODO: Check for more devices ? */
458 drmDevicePtr devices[8];
459 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
460 int max_devices;
461
462 instance->physicalDeviceCount = 0;
463
464 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
465 if (max_devices < 1)
466 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
467
468 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
469 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
470 devices[i]->bustype == DRM_BUS_PCI &&
471 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
472
473 result = radv_physical_device_init(instance->physicalDevices +
474 instance->physicalDeviceCount,
475 instance,
476 devices[i]);
477 if (result == VK_SUCCESS)
478 ++instance->physicalDeviceCount;
479 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
480 break;
481 }
482 }
483 drmFreeDevices(devices, max_devices);
484
485 return result;
486 }
487
488 VkResult radv_EnumeratePhysicalDevices(
489 VkInstance _instance,
490 uint32_t* pPhysicalDeviceCount,
491 VkPhysicalDevice* pPhysicalDevices)
492 {
493 RADV_FROM_HANDLE(radv_instance, instance, _instance);
494 VkResult result;
495
496 if (instance->physicalDeviceCount < 0) {
497 result = radv_enumerate_devices(instance);
498 if (result != VK_SUCCESS &&
499 result != VK_ERROR_INCOMPATIBLE_DRIVER)
500 return result;
501 }
502
503 if (!pPhysicalDevices) {
504 *pPhysicalDeviceCount = instance->physicalDeviceCount;
505 } else {
506 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
507 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
508 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
509 }
510
511 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
512 : VK_SUCCESS;
513 }
514
515 void radv_GetPhysicalDeviceFeatures(
516 VkPhysicalDevice physicalDevice,
517 VkPhysicalDeviceFeatures* pFeatures)
518 {
519 memset(pFeatures, 0, sizeof(*pFeatures));
520
521 *pFeatures = (VkPhysicalDeviceFeatures) {
522 .robustBufferAccess = true,
523 .fullDrawIndexUint32 = true,
524 .imageCubeArray = true,
525 .independentBlend = true,
526 .geometryShader = true,
527 .tessellationShader = true,
528 .sampleRateShading = true,
529 .dualSrcBlend = true,
530 .logicOp = true,
531 .multiDrawIndirect = true,
532 .drawIndirectFirstInstance = true,
533 .depthClamp = true,
534 .depthBiasClamp = true,
535 .fillModeNonSolid = true,
536 .depthBounds = true,
537 .wideLines = true,
538 .largePoints = true,
539 .alphaToOne = true,
540 .multiViewport = true,
541 .samplerAnisotropy = true,
542 .textureCompressionETC2 = false,
543 .textureCompressionASTC_LDR = false,
544 .textureCompressionBC = true,
545 .occlusionQueryPrecise = true,
546 .pipelineStatisticsQuery = true,
547 .vertexPipelineStoresAndAtomics = true,
548 .fragmentStoresAndAtomics = true,
549 .shaderTessellationAndGeometryPointSize = true,
550 .shaderImageGatherExtended = true,
551 .shaderStorageImageExtendedFormats = true,
552 .shaderStorageImageMultisample = false,
553 .shaderUniformBufferArrayDynamicIndexing = true,
554 .shaderSampledImageArrayDynamicIndexing = true,
555 .shaderStorageBufferArrayDynamicIndexing = true,
556 .shaderStorageImageArrayDynamicIndexing = true,
557 .shaderStorageImageReadWithoutFormat = true,
558 .shaderStorageImageWriteWithoutFormat = true,
559 .shaderClipDistance = true,
560 .shaderCullDistance = true,
561 .shaderFloat64 = true,
562 .shaderInt64 = true,
563 .shaderInt16 = false,
564 .sparseBinding = true,
565 .variableMultisampleRate = true,
566 .inheritedQueries = true,
567 };
568 }
569
570 void radv_GetPhysicalDeviceFeatures2KHR(
571 VkPhysicalDevice physicalDevice,
572 VkPhysicalDeviceFeatures2KHR *pFeatures)
573 {
574 vk_foreach_struct(ext, pFeatures->pNext) {
575 switch (ext->sType) {
576 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
577 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
578 features->variablePointersStorageBuffer = true;
579 features->variablePointers = false;
580 break;
581 }
582 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHX: {
583 VkPhysicalDeviceMultiviewFeaturesKHX *features = (VkPhysicalDeviceMultiviewFeaturesKHX*)ext;
584 features->multiview = true;
585 features->multiviewGeometryShader = true;
586 features->multiviewTessellationShader = true;
587 break;
588 }
589 default:
590 break;
591 }
592 }
593 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
594 }
595
596 void radv_GetPhysicalDeviceProperties(
597 VkPhysicalDevice physicalDevice,
598 VkPhysicalDeviceProperties* pProperties)
599 {
600 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
601 VkSampleCountFlags sample_counts = 0xf;
602
603 /* make sure that the entire descriptor set is addressable with a signed
604 * 32-bit int. So the sum of all limits scaled by descriptor size has to
605 * be at most 2 GiB. the combined image & samples object count as one of
606 * both. This limit is for the pipeline layout, not for the set layout, but
607 * there is no set limit, so we just set a pipeline limit. I don't think
608 * any app is going to hit this soon. */
609 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
610 (32 /* uniform buffer, 32 due to potential space wasted on alignement */ +
611 32 /* storage buffer, 32 due to potential space wasted on alignement */ +
612 32 /* sampler, largest when combined with image */ +
613 64 /* sampled image */ +
614 64 /* storage image */);
615
616 VkPhysicalDeviceLimits limits = {
617 .maxImageDimension1D = (1 << 14),
618 .maxImageDimension2D = (1 << 14),
619 .maxImageDimension3D = (1 << 11),
620 .maxImageDimensionCube = (1 << 14),
621 .maxImageArrayLayers = (1 << 11),
622 .maxTexelBufferElements = 128 * 1024 * 1024,
623 .maxUniformBufferRange = UINT32_MAX,
624 .maxStorageBufferRange = UINT32_MAX,
625 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
626 .maxMemoryAllocationCount = UINT32_MAX,
627 .maxSamplerAllocationCount = 64 * 1024,
628 .bufferImageGranularity = 64, /* A cache line */
629 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
630 .maxBoundDescriptorSets = MAX_SETS,
631 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
632 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
633 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
634 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
635 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
636 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
637 .maxPerStageResources = max_descriptor_set_size,
638 .maxDescriptorSetSamplers = max_descriptor_set_size,
639 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
640 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
641 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
642 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
643 .maxDescriptorSetSampledImages = max_descriptor_set_size,
644 .maxDescriptorSetStorageImages = max_descriptor_set_size,
645 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
646 .maxVertexInputAttributes = 32,
647 .maxVertexInputBindings = 32,
648 .maxVertexInputAttributeOffset = 2047,
649 .maxVertexInputBindingStride = 2048,
650 .maxVertexOutputComponents = 128,
651 .maxTessellationGenerationLevel = 64,
652 .maxTessellationPatchSize = 32,
653 .maxTessellationControlPerVertexInputComponents = 128,
654 .maxTessellationControlPerVertexOutputComponents = 128,
655 .maxTessellationControlPerPatchOutputComponents = 120,
656 .maxTessellationControlTotalOutputComponents = 4096,
657 .maxTessellationEvaluationInputComponents = 128,
658 .maxTessellationEvaluationOutputComponents = 128,
659 .maxGeometryShaderInvocations = 127,
660 .maxGeometryInputComponents = 64,
661 .maxGeometryOutputComponents = 128,
662 .maxGeometryOutputVertices = 256,
663 .maxGeometryTotalOutputComponents = 1024,
664 .maxFragmentInputComponents = 128,
665 .maxFragmentOutputAttachments = 8,
666 .maxFragmentDualSrcAttachments = 1,
667 .maxFragmentCombinedOutputResources = 8,
668 .maxComputeSharedMemorySize = 32768,
669 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
670 .maxComputeWorkGroupInvocations = 2048,
671 .maxComputeWorkGroupSize = {
672 2048,
673 2048,
674 2048
675 },
676 .subPixelPrecisionBits = 4 /* FIXME */,
677 .subTexelPrecisionBits = 4 /* FIXME */,
678 .mipmapPrecisionBits = 4 /* FIXME */,
679 .maxDrawIndexedIndexValue = UINT32_MAX,
680 .maxDrawIndirectCount = UINT32_MAX,
681 .maxSamplerLodBias = 16,
682 .maxSamplerAnisotropy = 16,
683 .maxViewports = MAX_VIEWPORTS,
684 .maxViewportDimensions = { (1 << 14), (1 << 14) },
685 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
686 .viewportSubPixelBits = 13, /* We take a float? */
687 .minMemoryMapAlignment = 4096, /* A page */
688 .minTexelBufferOffsetAlignment = 1,
689 .minUniformBufferOffsetAlignment = 4,
690 .minStorageBufferOffsetAlignment = 4,
691 .minTexelOffset = -32,
692 .maxTexelOffset = 31,
693 .minTexelGatherOffset = -32,
694 .maxTexelGatherOffset = 31,
695 .minInterpolationOffset = -2,
696 .maxInterpolationOffset = 2,
697 .subPixelInterpolationOffsetBits = 8,
698 .maxFramebufferWidth = (1 << 14),
699 .maxFramebufferHeight = (1 << 14),
700 .maxFramebufferLayers = (1 << 10),
701 .framebufferColorSampleCounts = sample_counts,
702 .framebufferDepthSampleCounts = sample_counts,
703 .framebufferStencilSampleCounts = sample_counts,
704 .framebufferNoAttachmentsSampleCounts = sample_counts,
705 .maxColorAttachments = MAX_RTS,
706 .sampledImageColorSampleCounts = sample_counts,
707 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
708 .sampledImageDepthSampleCounts = sample_counts,
709 .sampledImageStencilSampleCounts = sample_counts,
710 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
711 .maxSampleMaskWords = 1,
712 .timestampComputeAndGraphics = true,
713 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
714 .maxClipDistances = 8,
715 .maxCullDistances = 8,
716 .maxCombinedClipAndCullDistances = 8,
717 .discreteQueuePriorities = 1,
718 .pointSizeRange = { 0.125, 255.875 },
719 .lineWidthRange = { 0.0, 7.9921875 },
720 .pointSizeGranularity = (1.0 / 8.0),
721 .lineWidthGranularity = (1.0 / 128.0),
722 .strictLines = false, /* FINISHME */
723 .standardSampleLocations = true,
724 .optimalBufferCopyOffsetAlignment = 128,
725 .optimalBufferCopyRowPitchAlignment = 128,
726 .nonCoherentAtomSize = 64,
727 };
728
729 *pProperties = (VkPhysicalDeviceProperties) {
730 .apiVersion = radv_physical_device_api_version(pdevice),
731 .driverVersion = vk_get_driver_version(),
732 .vendorID = ATI_VENDOR_ID,
733 .deviceID = pdevice->rad_info.pci_id,
734 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
735 .limits = limits,
736 .sparseProperties = {0},
737 };
738
739 strcpy(pProperties->deviceName, pdevice->name);
740 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
741 }
742
743 void radv_GetPhysicalDeviceProperties2KHR(
744 VkPhysicalDevice physicalDevice,
745 VkPhysicalDeviceProperties2KHR *pProperties)
746 {
747 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
748 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
749
750 vk_foreach_struct(ext, pProperties->pNext) {
751 switch (ext->sType) {
752 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
753 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
754 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
755 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
756 break;
757 }
758 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
759 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
760 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
761 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
762 properties->deviceLUIDValid = false;
763 break;
764 }
765 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHX: {
766 VkPhysicalDeviceMultiviewPropertiesKHX *properties = (VkPhysicalDeviceMultiviewPropertiesKHX*)ext;
767 properties->maxMultiviewViewCount = MAX_VIEWS;
768 properties->maxMultiviewInstanceIndex = INT_MAX;
769 break;
770 }
771 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
772 VkPhysicalDevicePointClippingPropertiesKHR *properties =
773 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
774 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
775 break;
776 }
777 default:
778 break;
779 }
780 }
781 }
782
783 static void radv_get_physical_device_queue_family_properties(
784 struct radv_physical_device* pdevice,
785 uint32_t* pCount,
786 VkQueueFamilyProperties** pQueueFamilyProperties)
787 {
788 int num_queue_families = 1;
789 int idx;
790 if (pdevice->rad_info.num_compute_rings > 0 &&
791 pdevice->rad_info.chip_class >= CIK &&
792 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
793 num_queue_families++;
794
795 if (pQueueFamilyProperties == NULL) {
796 *pCount = num_queue_families;
797 return;
798 }
799
800 if (!*pCount)
801 return;
802
803 idx = 0;
804 if (*pCount >= 1) {
805 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
806 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
807 VK_QUEUE_COMPUTE_BIT |
808 VK_QUEUE_TRANSFER_BIT |
809 VK_QUEUE_SPARSE_BINDING_BIT,
810 .queueCount = 1,
811 .timestampValidBits = 64,
812 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
813 };
814 idx++;
815 }
816
817 if (pdevice->rad_info.num_compute_rings > 0 &&
818 pdevice->rad_info.chip_class >= CIK &&
819 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
820 if (*pCount > idx) {
821 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
822 .queueFlags = VK_QUEUE_COMPUTE_BIT |
823 VK_QUEUE_TRANSFER_BIT |
824 VK_QUEUE_SPARSE_BINDING_BIT,
825 .queueCount = pdevice->rad_info.num_compute_rings,
826 .timestampValidBits = 64,
827 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
828 };
829 idx++;
830 }
831 }
832 *pCount = idx;
833 }
834
835 void radv_GetPhysicalDeviceQueueFamilyProperties(
836 VkPhysicalDevice physicalDevice,
837 uint32_t* pCount,
838 VkQueueFamilyProperties* pQueueFamilyProperties)
839 {
840 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
841 if (!pQueueFamilyProperties) {
842 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
843 return;
844 }
845 VkQueueFamilyProperties *properties[] = {
846 pQueueFamilyProperties + 0,
847 pQueueFamilyProperties + 1,
848 pQueueFamilyProperties + 2,
849 };
850 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
851 assert(*pCount <= 3);
852 }
853
854 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
855 VkPhysicalDevice physicalDevice,
856 uint32_t* pCount,
857 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
858 {
859 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
860 if (!pQueueFamilyProperties) {
861 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
862 return;
863 }
864 VkQueueFamilyProperties *properties[] = {
865 &pQueueFamilyProperties[0].queueFamilyProperties,
866 &pQueueFamilyProperties[1].queueFamilyProperties,
867 &pQueueFamilyProperties[2].queueFamilyProperties,
868 };
869 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
870 assert(*pCount <= 3);
871 }
872
873 void radv_GetPhysicalDeviceMemoryProperties(
874 VkPhysicalDevice physicalDevice,
875 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
876 {
877 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
878
879 *pMemoryProperties = physical_device->memory_properties;
880 }
881
882 void radv_GetPhysicalDeviceMemoryProperties2KHR(
883 VkPhysicalDevice physicalDevice,
884 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
885 {
886 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
887 &pMemoryProperties->memoryProperties);
888 }
889
890 static enum radeon_ctx_priority
891 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
892 {
893 /* Default to MEDIUM when a specific global priority isn't requested */
894 if (!pObj)
895 return RADEON_CTX_PRIORITY_MEDIUM;
896
897 switch(pObj->globalPriority) {
898 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME:
899 return RADEON_CTX_PRIORITY_REALTIME;
900 case VK_QUEUE_GLOBAL_PRIORITY_HIGH:
901 return RADEON_CTX_PRIORITY_HIGH;
902 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM:
903 return RADEON_CTX_PRIORITY_MEDIUM;
904 case VK_QUEUE_GLOBAL_PRIORITY_LOW:
905 return RADEON_CTX_PRIORITY_LOW;
906 default:
907 unreachable("Illegal global priority value");
908 return RADEON_CTX_PRIORITY_INVALID;
909 }
910 }
911
912 static int
913 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
914 int queue_family_index, int idx,
915 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
916 {
917 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
918 queue->device = device;
919 queue->queue_family_index = queue_family_index;
920 queue->queue_idx = idx;
921 queue->priority = radv_get_queue_global_priority(global_priority);
922
923 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
924 if (!queue->hw_ctx)
925 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
926
927 return VK_SUCCESS;
928 }
929
930 static void
931 radv_queue_finish(struct radv_queue *queue)
932 {
933 if (queue->hw_ctx)
934 queue->device->ws->ctx_destroy(queue->hw_ctx);
935
936 if (queue->initial_full_flush_preamble_cs)
937 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
938 if (queue->initial_preamble_cs)
939 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
940 if (queue->continue_preamble_cs)
941 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
942 if (queue->descriptor_bo)
943 queue->device->ws->buffer_destroy(queue->descriptor_bo);
944 if (queue->scratch_bo)
945 queue->device->ws->buffer_destroy(queue->scratch_bo);
946 if (queue->esgs_ring_bo)
947 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
948 if (queue->gsvs_ring_bo)
949 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
950 if (queue->tess_factor_ring_bo)
951 queue->device->ws->buffer_destroy(queue->tess_factor_ring_bo);
952 if (queue->tess_offchip_ring_bo)
953 queue->device->ws->buffer_destroy(queue->tess_offchip_ring_bo);
954 if (queue->compute_scratch_bo)
955 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
956 }
957
958 static void
959 radv_device_init_gs_info(struct radv_device *device)
960 {
961 switch (device->physical_device->rad_info.family) {
962 case CHIP_OLAND:
963 case CHIP_HAINAN:
964 case CHIP_KAVERI:
965 case CHIP_KABINI:
966 case CHIP_MULLINS:
967 case CHIP_ICELAND:
968 case CHIP_CARRIZO:
969 case CHIP_STONEY:
970 device->gs_table_depth = 16;
971 return;
972 case CHIP_TAHITI:
973 case CHIP_PITCAIRN:
974 case CHIP_VERDE:
975 case CHIP_BONAIRE:
976 case CHIP_HAWAII:
977 case CHIP_TONGA:
978 case CHIP_FIJI:
979 case CHIP_POLARIS10:
980 case CHIP_POLARIS11:
981 case CHIP_POLARIS12:
982 case CHIP_VEGA10:
983 case CHIP_RAVEN:
984 device->gs_table_depth = 32;
985 return;
986 default:
987 unreachable("unknown GPU");
988 }
989 }
990
991 VkResult radv_CreateDevice(
992 VkPhysicalDevice physicalDevice,
993 const VkDeviceCreateInfo* pCreateInfo,
994 const VkAllocationCallbacks* pAllocator,
995 VkDevice* pDevice)
996 {
997 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
998 VkResult result;
999 struct radv_device *device;
1000
1001 bool keep_shader_info = false;
1002
1003 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1004 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1005 if (!radv_physical_device_extension_supported(physical_device, ext_name))
1006 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
1007
1008 if (strcmp(ext_name, VK_AMD_SHADER_INFO_EXTENSION_NAME) == 0)
1009 keep_shader_info = true;
1010 }
1011
1012 /* Check enabled features */
1013 if (pCreateInfo->pEnabledFeatures) {
1014 VkPhysicalDeviceFeatures supported_features;
1015 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1016 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1017 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1018 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1019 for (uint32_t i = 0; i < num_features; i++) {
1020 if (enabled_feature[i] && !supported_feature[i])
1021 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
1022 }
1023 }
1024
1025 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1026 sizeof(*device), 8,
1027 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1028 if (!device)
1029 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1030
1031 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1032 device->instance = physical_device->instance;
1033 device->physical_device = physical_device;
1034
1035 device->ws = physical_device->ws;
1036 if (pAllocator)
1037 device->alloc = *pAllocator;
1038 else
1039 device->alloc = physical_device->instance->alloc;
1040
1041 mtx_init(&device->shader_slab_mutex, mtx_plain);
1042 list_inithead(&device->shader_slabs);
1043
1044 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1045 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1046 uint32_t qfi = queue_create->queueFamilyIndex;
1047 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1048 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1049
1050 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1051
1052 device->queues[qfi] = vk_alloc(&device->alloc,
1053 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1054 if (!device->queues[qfi]) {
1055 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1056 goto fail;
1057 }
1058
1059 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1060
1061 device->queue_count[qfi] = queue_create->queueCount;
1062
1063 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1064 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q, global_priority);
1065 if (result != VK_SUCCESS)
1066 goto fail;
1067 }
1068 }
1069
1070 #if HAVE_LLVM < 0x0400
1071 device->llvm_supports_spill = false;
1072 #else
1073 device->llvm_supports_spill = true;
1074 #endif
1075
1076 /* The maximum number of scratch waves. Scratch space isn't divided
1077 * evenly between CUs. The number is only a function of the number of CUs.
1078 * We can decrease the constant to decrease the scratch buffer size.
1079 *
1080 * sctx->scratch_waves must be >= the maximum posible size of
1081 * 1 threadgroup, so that the hw doesn't hang from being unable
1082 * to start any.
1083 *
1084 * The recommended value is 4 per CU at most. Higher numbers don't
1085 * bring much benefit, but they still occupy chip resources (think
1086 * async compute). I've seen ~2% performance difference between 4 and 32.
1087 */
1088 uint32_t max_threads_per_block = 2048;
1089 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1090 max_threads_per_block / 64);
1091
1092 radv_device_init_gs_info(device);
1093
1094 device->tess_offchip_block_dw_size =
1095 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1096 device->has_distributed_tess =
1097 device->physical_device->rad_info.chip_class >= VI &&
1098 device->physical_device->rad_info.max_se >= 2;
1099
1100 if (getenv("RADV_TRACE_FILE")) {
1101 keep_shader_info = true;
1102
1103 if (!radv_init_trace(device))
1104 goto fail;
1105 }
1106
1107 device->keep_shader_info = keep_shader_info;
1108
1109 result = radv_device_init_meta(device);
1110 if (result != VK_SUCCESS)
1111 goto fail;
1112
1113 radv_device_init_msaa(device);
1114
1115 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1116 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1117 switch (family) {
1118 case RADV_QUEUE_GENERAL:
1119 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1120 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1121 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1122 break;
1123 case RADV_QUEUE_COMPUTE:
1124 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1125 radeon_emit(device->empty_cs[family], 0);
1126 break;
1127 }
1128 device->ws->cs_finalize(device->empty_cs[family]);
1129 }
1130
1131 if (device->physical_device->rad_info.chip_class >= CIK)
1132 cik_create_gfx_config(device);
1133
1134 VkPipelineCacheCreateInfo ci;
1135 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1136 ci.pNext = NULL;
1137 ci.flags = 0;
1138 ci.pInitialData = NULL;
1139 ci.initialDataSize = 0;
1140 VkPipelineCache pc;
1141 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1142 &ci, NULL, &pc);
1143 if (result != VK_SUCCESS)
1144 goto fail;
1145
1146 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1147
1148 *pDevice = radv_device_to_handle(device);
1149 return VK_SUCCESS;
1150
1151 fail:
1152 if (device->trace_bo)
1153 device->ws->buffer_destroy(device->trace_bo);
1154
1155 if (device->gfx_init)
1156 device->ws->buffer_destroy(device->gfx_init);
1157
1158 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1159 for (unsigned q = 0; q < device->queue_count[i]; q++)
1160 radv_queue_finish(&device->queues[i][q]);
1161 if (device->queue_count[i])
1162 vk_free(&device->alloc, device->queues[i]);
1163 }
1164
1165 vk_free(&device->alloc, device);
1166 return result;
1167 }
1168
1169 void radv_DestroyDevice(
1170 VkDevice _device,
1171 const VkAllocationCallbacks* pAllocator)
1172 {
1173 RADV_FROM_HANDLE(radv_device, device, _device);
1174
1175 if (!device)
1176 return;
1177
1178 if (device->trace_bo)
1179 device->ws->buffer_destroy(device->trace_bo);
1180
1181 if (device->gfx_init)
1182 device->ws->buffer_destroy(device->gfx_init);
1183
1184 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1185 for (unsigned q = 0; q < device->queue_count[i]; q++)
1186 radv_queue_finish(&device->queues[i][q]);
1187 if (device->queue_count[i])
1188 vk_free(&device->alloc, device->queues[i]);
1189 if (device->empty_cs[i])
1190 device->ws->cs_destroy(device->empty_cs[i]);
1191 }
1192 radv_device_finish_meta(device);
1193
1194 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1195 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1196
1197 radv_destroy_shader_slabs(device);
1198
1199 vk_free(&device->alloc, device);
1200 }
1201
1202 VkResult radv_EnumerateInstanceLayerProperties(
1203 uint32_t* pPropertyCount,
1204 VkLayerProperties* pProperties)
1205 {
1206 if (pProperties == NULL) {
1207 *pPropertyCount = 0;
1208 return VK_SUCCESS;
1209 }
1210
1211 /* None supported at this time */
1212 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1213 }
1214
1215 VkResult radv_EnumerateDeviceLayerProperties(
1216 VkPhysicalDevice physicalDevice,
1217 uint32_t* pPropertyCount,
1218 VkLayerProperties* pProperties)
1219 {
1220 if (pProperties == NULL) {
1221 *pPropertyCount = 0;
1222 return VK_SUCCESS;
1223 }
1224
1225 /* None supported at this time */
1226 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1227 }
1228
1229 void radv_GetDeviceQueue(
1230 VkDevice _device,
1231 uint32_t queueFamilyIndex,
1232 uint32_t queueIndex,
1233 VkQueue* pQueue)
1234 {
1235 RADV_FROM_HANDLE(radv_device, device, _device);
1236
1237 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
1238 }
1239
1240 static void
1241 fill_geom_tess_rings(struct radv_queue *queue,
1242 uint32_t *map,
1243 bool add_sample_positions,
1244 uint32_t esgs_ring_size,
1245 struct radeon_winsys_bo *esgs_ring_bo,
1246 uint32_t gsvs_ring_size,
1247 struct radeon_winsys_bo *gsvs_ring_bo,
1248 uint32_t tess_factor_ring_size,
1249 struct radeon_winsys_bo *tess_factor_ring_bo,
1250 uint32_t tess_offchip_ring_size,
1251 struct radeon_winsys_bo *tess_offchip_ring_bo)
1252 {
1253 uint64_t esgs_va = 0, gsvs_va = 0;
1254 uint64_t tess_factor_va = 0, tess_offchip_va = 0;
1255 uint32_t *desc = &map[4];
1256
1257 if (esgs_ring_bo)
1258 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1259 if (gsvs_ring_bo)
1260 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1261 if (tess_factor_ring_bo)
1262 tess_factor_va = radv_buffer_get_va(tess_factor_ring_bo);
1263 if (tess_offchip_ring_bo)
1264 tess_offchip_va = radv_buffer_get_va(tess_offchip_ring_bo);
1265
1266 /* stride 0, num records - size, add tid, swizzle, elsize4,
1267 index stride 64 */
1268 desc[0] = esgs_va;
1269 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1270 S_008F04_STRIDE(0) |
1271 S_008F04_SWIZZLE_ENABLE(true);
1272 desc[2] = esgs_ring_size;
1273 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1274 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1275 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1276 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1277 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1278 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1279 S_008F0C_ELEMENT_SIZE(1) |
1280 S_008F0C_INDEX_STRIDE(3) |
1281 S_008F0C_ADD_TID_ENABLE(true);
1282
1283 desc += 4;
1284 /* GS entry for ES->GS ring */
1285 /* stride 0, num records - size, elsize0,
1286 index stride 0 */
1287 desc[0] = esgs_va;
1288 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1289 S_008F04_STRIDE(0) |
1290 S_008F04_SWIZZLE_ENABLE(false);
1291 desc[2] = esgs_ring_size;
1292 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1293 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1294 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1295 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1296 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1297 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1298 S_008F0C_ELEMENT_SIZE(0) |
1299 S_008F0C_INDEX_STRIDE(0) |
1300 S_008F0C_ADD_TID_ENABLE(false);
1301
1302 desc += 4;
1303 /* VS entry for GS->VS ring */
1304 /* stride 0, num records - size, elsize0,
1305 index stride 0 */
1306 desc[0] = gsvs_va;
1307 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1308 S_008F04_STRIDE(0) |
1309 S_008F04_SWIZZLE_ENABLE(false);
1310 desc[2] = gsvs_ring_size;
1311 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1312 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1313 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1314 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1315 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1316 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1317 S_008F0C_ELEMENT_SIZE(0) |
1318 S_008F0C_INDEX_STRIDE(0) |
1319 S_008F0C_ADD_TID_ENABLE(false);
1320 desc += 4;
1321
1322 /* stride gsvs_itemsize, num records 64
1323 elsize 4, index stride 16 */
1324 /* shader will patch stride and desc[2] */
1325 desc[0] = gsvs_va;
1326 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1327 S_008F04_STRIDE(0) |
1328 S_008F04_SWIZZLE_ENABLE(true);
1329 desc[2] = 0;
1330 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1331 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1332 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1333 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1334 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1335 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1336 S_008F0C_ELEMENT_SIZE(1) |
1337 S_008F0C_INDEX_STRIDE(1) |
1338 S_008F0C_ADD_TID_ENABLE(true);
1339 desc += 4;
1340
1341 desc[0] = tess_factor_va;
1342 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va >> 32) |
1343 S_008F04_STRIDE(0) |
1344 S_008F04_SWIZZLE_ENABLE(false);
1345 desc[2] = tess_factor_ring_size;
1346 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1347 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1348 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1349 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1350 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1351 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1352 S_008F0C_ELEMENT_SIZE(0) |
1353 S_008F0C_INDEX_STRIDE(0) |
1354 S_008F0C_ADD_TID_ENABLE(false);
1355 desc += 4;
1356
1357 desc[0] = tess_offchip_va;
1358 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1359 S_008F04_STRIDE(0) |
1360 S_008F04_SWIZZLE_ENABLE(false);
1361 desc[2] = tess_offchip_ring_size;
1362 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1363 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1364 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1365 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1366 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1367 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1368 S_008F0C_ELEMENT_SIZE(0) |
1369 S_008F0C_INDEX_STRIDE(0) |
1370 S_008F0C_ADD_TID_ENABLE(false);
1371 desc += 4;
1372
1373 /* add sample positions after all rings */
1374 memcpy(desc, queue->device->sample_locations_1x, 8);
1375 desc += 2;
1376 memcpy(desc, queue->device->sample_locations_2x, 16);
1377 desc += 4;
1378 memcpy(desc, queue->device->sample_locations_4x, 32);
1379 desc += 8;
1380 memcpy(desc, queue->device->sample_locations_8x, 64);
1381 desc += 16;
1382 memcpy(desc, queue->device->sample_locations_16x, 128);
1383 }
1384
1385 static unsigned
1386 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1387 {
1388 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1389 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1390 device->physical_device->rad_info.family != CHIP_STONEY;
1391 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1392 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1393 device->physical_device->rad_info.max_se;
1394 unsigned offchip_granularity;
1395 unsigned hs_offchip_param;
1396 switch (device->tess_offchip_block_dw_size) {
1397 default:
1398 assert(0);
1399 /* fall through */
1400 case 8192:
1401 offchip_granularity = V_03093C_X_8K_DWORDS;
1402 break;
1403 case 4096:
1404 offchip_granularity = V_03093C_X_4K_DWORDS;
1405 break;
1406 }
1407
1408 switch (device->physical_device->rad_info.chip_class) {
1409 case SI:
1410 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1411 break;
1412 case CIK:
1413 case VI:
1414 case GFX9:
1415 default:
1416 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1417 break;
1418 }
1419
1420 *max_offchip_buffers_p = max_offchip_buffers;
1421 if (device->physical_device->rad_info.chip_class >= CIK) {
1422 if (device->physical_device->rad_info.chip_class >= VI)
1423 --max_offchip_buffers;
1424 hs_offchip_param =
1425 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1426 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1427 } else {
1428 hs_offchip_param =
1429 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1430 }
1431 return hs_offchip_param;
1432 }
1433
1434 static VkResult
1435 radv_get_preamble_cs(struct radv_queue *queue,
1436 uint32_t scratch_size,
1437 uint32_t compute_scratch_size,
1438 uint32_t esgs_ring_size,
1439 uint32_t gsvs_ring_size,
1440 bool needs_tess_rings,
1441 bool needs_sample_positions,
1442 struct radeon_winsys_cs **initial_full_flush_preamble_cs,
1443 struct radeon_winsys_cs **initial_preamble_cs,
1444 struct radeon_winsys_cs **continue_preamble_cs)
1445 {
1446 struct radeon_winsys_bo *scratch_bo = NULL;
1447 struct radeon_winsys_bo *descriptor_bo = NULL;
1448 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1449 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1450 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1451 struct radeon_winsys_bo *tess_factor_ring_bo = NULL;
1452 struct radeon_winsys_bo *tess_offchip_ring_bo = NULL;
1453 struct radeon_winsys_cs *dest_cs[3] = {0};
1454 bool add_tess_rings = false, add_sample_positions = false;
1455 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1456 unsigned max_offchip_buffers;
1457 unsigned hs_offchip_param = 0;
1458 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
1459 if (!queue->has_tess_rings) {
1460 if (needs_tess_rings)
1461 add_tess_rings = true;
1462 }
1463 if (!queue->has_sample_positions) {
1464 if (needs_sample_positions)
1465 add_sample_positions = true;
1466 }
1467 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1468 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1469 &max_offchip_buffers);
1470 tess_offchip_ring_size = max_offchip_buffers *
1471 queue->device->tess_offchip_block_dw_size * 4;
1472
1473 if (scratch_size <= queue->scratch_size &&
1474 compute_scratch_size <= queue->compute_scratch_size &&
1475 esgs_ring_size <= queue->esgs_ring_size &&
1476 gsvs_ring_size <= queue->gsvs_ring_size &&
1477 !add_tess_rings && !add_sample_positions &&
1478 queue->initial_preamble_cs) {
1479 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1480 *initial_preamble_cs = queue->initial_preamble_cs;
1481 *continue_preamble_cs = queue->continue_preamble_cs;
1482 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1483 *continue_preamble_cs = NULL;
1484 return VK_SUCCESS;
1485 }
1486
1487 if (scratch_size > queue->scratch_size) {
1488 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1489 scratch_size,
1490 4096,
1491 RADEON_DOMAIN_VRAM,
1492 ring_bo_flags);
1493 if (!scratch_bo)
1494 goto fail;
1495 } else
1496 scratch_bo = queue->scratch_bo;
1497
1498 if (compute_scratch_size > queue->compute_scratch_size) {
1499 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1500 compute_scratch_size,
1501 4096,
1502 RADEON_DOMAIN_VRAM,
1503 ring_bo_flags);
1504 if (!compute_scratch_bo)
1505 goto fail;
1506
1507 } else
1508 compute_scratch_bo = queue->compute_scratch_bo;
1509
1510 if (esgs_ring_size > queue->esgs_ring_size) {
1511 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1512 esgs_ring_size,
1513 4096,
1514 RADEON_DOMAIN_VRAM,
1515 ring_bo_flags);
1516 if (!esgs_ring_bo)
1517 goto fail;
1518 } else {
1519 esgs_ring_bo = queue->esgs_ring_bo;
1520 esgs_ring_size = queue->esgs_ring_size;
1521 }
1522
1523 if (gsvs_ring_size > queue->gsvs_ring_size) {
1524 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1525 gsvs_ring_size,
1526 4096,
1527 RADEON_DOMAIN_VRAM,
1528 ring_bo_flags);
1529 if (!gsvs_ring_bo)
1530 goto fail;
1531 } else {
1532 gsvs_ring_bo = queue->gsvs_ring_bo;
1533 gsvs_ring_size = queue->gsvs_ring_size;
1534 }
1535
1536 if (add_tess_rings) {
1537 tess_factor_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1538 tess_factor_ring_size,
1539 256,
1540 RADEON_DOMAIN_VRAM,
1541 ring_bo_flags);
1542 if (!tess_factor_ring_bo)
1543 goto fail;
1544 tess_offchip_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1545 tess_offchip_ring_size,
1546 256,
1547 RADEON_DOMAIN_VRAM,
1548 ring_bo_flags);
1549 if (!tess_offchip_ring_bo)
1550 goto fail;
1551 } else {
1552 tess_factor_ring_bo = queue->tess_factor_ring_bo;
1553 tess_offchip_ring_bo = queue->tess_offchip_ring_bo;
1554 }
1555
1556 if (scratch_bo != queue->scratch_bo ||
1557 esgs_ring_bo != queue->esgs_ring_bo ||
1558 gsvs_ring_bo != queue->gsvs_ring_bo ||
1559 tess_factor_ring_bo != queue->tess_factor_ring_bo ||
1560 tess_offchip_ring_bo != queue->tess_offchip_ring_bo || add_sample_positions) {
1561 uint32_t size = 0;
1562 if (gsvs_ring_bo || esgs_ring_bo ||
1563 tess_factor_ring_bo || tess_offchip_ring_bo || add_sample_positions) {
1564 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
1565 if (add_sample_positions)
1566 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1567 }
1568 else if (scratch_bo)
1569 size = 8; /* 2 dword */
1570
1571 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1572 size,
1573 4096,
1574 RADEON_DOMAIN_VRAM,
1575 RADEON_FLAG_CPU_ACCESS|RADEON_FLAG_NO_INTERPROCESS_SHARING);
1576 if (!descriptor_bo)
1577 goto fail;
1578 } else
1579 descriptor_bo = queue->descriptor_bo;
1580
1581 for(int i = 0; i < 3; ++i) {
1582 struct radeon_winsys_cs *cs = NULL;
1583 cs = queue->device->ws->cs_create(queue->device->ws,
1584 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1585 if (!cs)
1586 goto fail;
1587
1588 dest_cs[i] = cs;
1589
1590 if (scratch_bo)
1591 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo, 8);
1592
1593 if (esgs_ring_bo)
1594 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo, 8);
1595
1596 if (gsvs_ring_bo)
1597 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo, 8);
1598
1599 if (tess_factor_ring_bo)
1600 radv_cs_add_buffer(queue->device->ws, cs, tess_factor_ring_bo, 8);
1601
1602 if (tess_offchip_ring_bo)
1603 radv_cs_add_buffer(queue->device->ws, cs, tess_offchip_ring_bo, 8);
1604
1605 if (descriptor_bo)
1606 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo, 8);
1607
1608 if (descriptor_bo != queue->descriptor_bo) {
1609 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1610
1611 if (scratch_bo) {
1612 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
1613 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1614 S_008F04_SWIZZLE_ENABLE(1);
1615 map[0] = scratch_va;
1616 map[1] = rsrc1;
1617 }
1618
1619 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo ||
1620 add_sample_positions)
1621 fill_geom_tess_rings(queue, map, add_sample_positions,
1622 esgs_ring_size, esgs_ring_bo,
1623 gsvs_ring_size, gsvs_ring_bo,
1624 tess_factor_ring_size, tess_factor_ring_bo,
1625 tess_offchip_ring_size, tess_offchip_ring_bo);
1626
1627 queue->device->ws->buffer_unmap(descriptor_bo);
1628 }
1629
1630 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo) {
1631 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1632 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1633 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1634 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1635 }
1636
1637 if (esgs_ring_bo || gsvs_ring_bo) {
1638 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1639 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1640 radeon_emit(cs, esgs_ring_size >> 8);
1641 radeon_emit(cs, gsvs_ring_size >> 8);
1642 } else {
1643 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1644 radeon_emit(cs, esgs_ring_size >> 8);
1645 radeon_emit(cs, gsvs_ring_size >> 8);
1646 }
1647 }
1648
1649 if (tess_factor_ring_bo) {
1650 uint64_t tf_va = radv_buffer_get_va(tess_factor_ring_bo);
1651 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1652 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1653 S_030938_SIZE(tess_factor_ring_size / 4));
1654 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1655 tf_va >> 8);
1656 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1657 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1658 tf_va >> 40);
1659 }
1660 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
1661 } else {
1662 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1663 S_008988_SIZE(tess_factor_ring_size / 4));
1664 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1665 tf_va >> 8);
1666 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1667 hs_offchip_param);
1668 }
1669 }
1670
1671 if (descriptor_bo) {
1672 uint64_t va = radv_buffer_get_va(descriptor_bo);
1673 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1674 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1675 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1676 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
1677 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
1678
1679 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1680 radeon_set_sh_reg_seq(cs, regs[i], 2);
1681 radeon_emit(cs, va);
1682 radeon_emit(cs, va >> 32);
1683 }
1684 } else {
1685 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1686 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1687 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1688 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1689 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1690 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1691
1692 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1693 radeon_set_sh_reg_seq(cs, regs[i], 2);
1694 radeon_emit(cs, va);
1695 radeon_emit(cs, va >> 32);
1696 }
1697 }
1698 }
1699
1700 if (compute_scratch_bo) {
1701 uint64_t scratch_va = radv_buffer_get_va(compute_scratch_bo);
1702 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1703 S_008F04_SWIZZLE_ENABLE(1);
1704
1705 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo, 8);
1706
1707 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1708 radeon_emit(cs, scratch_va);
1709 radeon_emit(cs, rsrc1);
1710 }
1711
1712 if (i == 0) {
1713 si_cs_emit_cache_flush(cs,
1714 false,
1715 queue->device->physical_device->rad_info.chip_class,
1716 NULL, 0,
1717 queue->queue_family_index == RING_COMPUTE &&
1718 queue->device->physical_device->rad_info.chip_class >= CIK,
1719 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
1720 RADV_CMD_FLAG_INV_ICACHE |
1721 RADV_CMD_FLAG_INV_SMEM_L1 |
1722 RADV_CMD_FLAG_INV_VMEM_L1 |
1723 RADV_CMD_FLAG_INV_GLOBAL_L2);
1724 } else if (i == 1) {
1725 si_cs_emit_cache_flush(cs,
1726 false,
1727 queue->device->physical_device->rad_info.chip_class,
1728 NULL, 0,
1729 queue->queue_family_index == RING_COMPUTE &&
1730 queue->device->physical_device->rad_info.chip_class >= CIK,
1731 RADV_CMD_FLAG_INV_ICACHE |
1732 RADV_CMD_FLAG_INV_SMEM_L1 |
1733 RADV_CMD_FLAG_INV_VMEM_L1 |
1734 RADV_CMD_FLAG_INV_GLOBAL_L2);
1735 }
1736
1737 if (!queue->device->ws->cs_finalize(cs))
1738 goto fail;
1739 }
1740
1741 if (queue->initial_full_flush_preamble_cs)
1742 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1743
1744 if (queue->initial_preamble_cs)
1745 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1746
1747 if (queue->continue_preamble_cs)
1748 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1749
1750 queue->initial_full_flush_preamble_cs = dest_cs[0];
1751 queue->initial_preamble_cs = dest_cs[1];
1752 queue->continue_preamble_cs = dest_cs[2];
1753
1754 if (scratch_bo != queue->scratch_bo) {
1755 if (queue->scratch_bo)
1756 queue->device->ws->buffer_destroy(queue->scratch_bo);
1757 queue->scratch_bo = scratch_bo;
1758 queue->scratch_size = scratch_size;
1759 }
1760
1761 if (compute_scratch_bo != queue->compute_scratch_bo) {
1762 if (queue->compute_scratch_bo)
1763 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1764 queue->compute_scratch_bo = compute_scratch_bo;
1765 queue->compute_scratch_size = compute_scratch_size;
1766 }
1767
1768 if (esgs_ring_bo != queue->esgs_ring_bo) {
1769 if (queue->esgs_ring_bo)
1770 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1771 queue->esgs_ring_bo = esgs_ring_bo;
1772 queue->esgs_ring_size = esgs_ring_size;
1773 }
1774
1775 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
1776 if (queue->gsvs_ring_bo)
1777 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1778 queue->gsvs_ring_bo = gsvs_ring_bo;
1779 queue->gsvs_ring_size = gsvs_ring_size;
1780 }
1781
1782 if (tess_factor_ring_bo != queue->tess_factor_ring_bo) {
1783 queue->tess_factor_ring_bo = tess_factor_ring_bo;
1784 }
1785
1786 if (tess_offchip_ring_bo != queue->tess_offchip_ring_bo) {
1787 queue->tess_offchip_ring_bo = tess_offchip_ring_bo;
1788 queue->has_tess_rings = true;
1789 }
1790
1791 if (descriptor_bo != queue->descriptor_bo) {
1792 if (queue->descriptor_bo)
1793 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1794
1795 queue->descriptor_bo = descriptor_bo;
1796 }
1797
1798 if (add_sample_positions)
1799 queue->has_sample_positions = true;
1800
1801 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1802 *initial_preamble_cs = queue->initial_preamble_cs;
1803 *continue_preamble_cs = queue->continue_preamble_cs;
1804 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1805 *continue_preamble_cs = NULL;
1806 return VK_SUCCESS;
1807 fail:
1808 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
1809 if (dest_cs[i])
1810 queue->device->ws->cs_destroy(dest_cs[i]);
1811 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
1812 queue->device->ws->buffer_destroy(descriptor_bo);
1813 if (scratch_bo && scratch_bo != queue->scratch_bo)
1814 queue->device->ws->buffer_destroy(scratch_bo);
1815 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
1816 queue->device->ws->buffer_destroy(compute_scratch_bo);
1817 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
1818 queue->device->ws->buffer_destroy(esgs_ring_bo);
1819 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
1820 queue->device->ws->buffer_destroy(gsvs_ring_bo);
1821 if (tess_factor_ring_bo && tess_factor_ring_bo != queue->tess_factor_ring_bo)
1822 queue->device->ws->buffer_destroy(tess_factor_ring_bo);
1823 if (tess_offchip_ring_bo && tess_offchip_ring_bo != queue->tess_offchip_ring_bo)
1824 queue->device->ws->buffer_destroy(tess_offchip_ring_bo);
1825 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
1826 }
1827
1828 static VkResult radv_alloc_sem_counts(struct radv_winsys_sem_counts *counts,
1829 int num_sems,
1830 const VkSemaphore *sems,
1831 bool reset_temp)
1832 {
1833 int syncobj_idx = 0, sem_idx = 0;
1834
1835 if (num_sems == 0)
1836 return VK_SUCCESS;
1837 for (uint32_t i = 0; i < num_sems; i++) {
1838 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1839
1840 if (sem->temp_syncobj || sem->syncobj)
1841 counts->syncobj_count++;
1842 else
1843 counts->sem_count++;
1844 }
1845
1846 if (counts->syncobj_count) {
1847 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
1848 if (!counts->syncobj)
1849 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1850 }
1851
1852 if (counts->sem_count) {
1853 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
1854 if (!counts->sem) {
1855 free(counts->syncobj);
1856 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1857 }
1858 }
1859
1860 for (uint32_t i = 0; i < num_sems; i++) {
1861 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1862
1863 if (sem->temp_syncobj) {
1864 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
1865 }
1866 else if (sem->syncobj)
1867 counts->syncobj[syncobj_idx++] = sem->syncobj;
1868 else {
1869 assert(sem->sem);
1870 counts->sem[sem_idx++] = sem->sem;
1871 }
1872 }
1873
1874 return VK_SUCCESS;
1875 }
1876
1877 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
1878 {
1879 free(sem_info->wait.syncobj);
1880 free(sem_info->wait.sem);
1881 free(sem_info->signal.syncobj);
1882 free(sem_info->signal.sem);
1883 }
1884
1885
1886 static void radv_free_temp_syncobjs(struct radv_device *device,
1887 int num_sems,
1888 const VkSemaphore *sems)
1889 {
1890 for (uint32_t i = 0; i < num_sems; i++) {
1891 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1892
1893 if (sem->temp_syncobj) {
1894 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
1895 sem->temp_syncobj = 0;
1896 }
1897 }
1898 }
1899
1900 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1901 int num_wait_sems,
1902 const VkSemaphore *wait_sems,
1903 int num_signal_sems,
1904 const VkSemaphore *signal_sems)
1905 {
1906 VkResult ret;
1907 memset(sem_info, 0, sizeof(*sem_info));
1908
1909 ret = radv_alloc_sem_counts(&sem_info->wait, num_wait_sems, wait_sems, true);
1910 if (ret)
1911 return ret;
1912 ret = radv_alloc_sem_counts(&sem_info->signal, num_signal_sems, signal_sems, false);
1913 if (ret)
1914 radv_free_sem_info(sem_info);
1915
1916 /* caller can override these */
1917 sem_info->cs_emit_wait = true;
1918 sem_info->cs_emit_signal = true;
1919 return ret;
1920 }
1921
1922 VkResult radv_QueueSubmit(
1923 VkQueue _queue,
1924 uint32_t submitCount,
1925 const VkSubmitInfo* pSubmits,
1926 VkFence _fence)
1927 {
1928 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1929 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1930 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
1931 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
1932 int ret;
1933 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
1934 uint32_t scratch_size = 0;
1935 uint32_t compute_scratch_size = 0;
1936 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
1937 struct radeon_winsys_cs *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
1938 VkResult result;
1939 bool fence_emitted = false;
1940 bool tess_rings_needed = false;
1941 bool sample_positions_needed = false;
1942
1943 /* Do this first so failing to allocate scratch buffers can't result in
1944 * partially executed submissions. */
1945 for (uint32_t i = 0; i < submitCount; i++) {
1946 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1947 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
1948 pSubmits[i].pCommandBuffers[j]);
1949
1950 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
1951 compute_scratch_size = MAX2(compute_scratch_size,
1952 cmd_buffer->compute_scratch_size_needed);
1953 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
1954 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
1955 tess_rings_needed |= cmd_buffer->tess_rings_needed;
1956 sample_positions_needed |= cmd_buffer->sample_positions_needed;
1957 }
1958 }
1959
1960 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
1961 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
1962 sample_positions_needed, &initial_flush_preamble_cs,
1963 &initial_preamble_cs, &continue_preamble_cs);
1964 if (result != VK_SUCCESS)
1965 return result;
1966
1967 for (uint32_t i = 0; i < submitCount; i++) {
1968 struct radeon_winsys_cs **cs_array;
1969 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
1970 bool can_patch = true;
1971 uint32_t advance;
1972 struct radv_winsys_sem_info sem_info;
1973
1974 result = radv_alloc_sem_info(&sem_info,
1975 pSubmits[i].waitSemaphoreCount,
1976 pSubmits[i].pWaitSemaphores,
1977 pSubmits[i].signalSemaphoreCount,
1978 pSubmits[i].pSignalSemaphores);
1979 if (result != VK_SUCCESS)
1980 return result;
1981
1982 if (!pSubmits[i].commandBufferCount) {
1983 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
1984 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
1985 &queue->device->empty_cs[queue->queue_family_index],
1986 1, NULL, NULL,
1987 &sem_info,
1988 false, base_fence);
1989 if (ret) {
1990 radv_loge("failed to submit CS %d\n", i);
1991 abort();
1992 }
1993 fence_emitted = true;
1994 }
1995 radv_free_sem_info(&sem_info);
1996 continue;
1997 }
1998
1999 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
2000 (pSubmits[i].commandBufferCount));
2001
2002 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2003 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2004 pSubmits[i].pCommandBuffers[j]);
2005 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2006
2007 cs_array[j] = cmd_buffer->cs;
2008 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2009 can_patch = false;
2010 }
2011
2012 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2013 struct radeon_winsys_cs *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2014 advance = MIN2(max_cs_submission,
2015 pSubmits[i].commandBufferCount - j);
2016
2017 if (queue->device->trace_bo)
2018 *queue->device->trace_id_ptr = 0;
2019
2020 sem_info.cs_emit_wait = j == 0;
2021 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2022
2023 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2024 advance, initial_preamble, continue_preamble_cs,
2025 &sem_info,
2026 can_patch, base_fence);
2027
2028 if (ret) {
2029 radv_loge("failed to submit CS %d\n", i);
2030 abort();
2031 }
2032 fence_emitted = true;
2033 if (queue->device->trace_bo) {
2034 radv_check_gpu_hangs(queue, cs_array[j]);
2035 }
2036 }
2037
2038 radv_free_temp_syncobjs(queue->device,
2039 pSubmits[i].waitSemaphoreCount,
2040 pSubmits[i].pWaitSemaphores);
2041 radv_free_sem_info(&sem_info);
2042 free(cs_array);
2043 }
2044
2045 if (fence) {
2046 if (!fence_emitted) {
2047 struct radv_winsys_sem_info sem_info = {0};
2048 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2049 &queue->device->empty_cs[queue->queue_family_index],
2050 1, NULL, NULL, &sem_info,
2051 false, base_fence);
2052 }
2053 fence->submitted = true;
2054 }
2055
2056 return VK_SUCCESS;
2057 }
2058
2059 VkResult radv_QueueWaitIdle(
2060 VkQueue _queue)
2061 {
2062 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2063
2064 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2065 radv_queue_family_to_ring(queue->queue_family_index),
2066 queue->queue_idx);
2067 return VK_SUCCESS;
2068 }
2069
2070 VkResult radv_DeviceWaitIdle(
2071 VkDevice _device)
2072 {
2073 RADV_FROM_HANDLE(radv_device, device, _device);
2074
2075 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2076 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2077 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2078 }
2079 }
2080 return VK_SUCCESS;
2081 }
2082
2083 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2084 VkInstance instance,
2085 const char* pName)
2086 {
2087 return radv_lookup_entrypoint(pName);
2088 }
2089
2090 /* The loader wants us to expose a second GetInstanceProcAddr function
2091 * to work around certain LD_PRELOAD issues seen in apps.
2092 */
2093 PUBLIC
2094 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2095 VkInstance instance,
2096 const char* pName);
2097
2098 PUBLIC
2099 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2100 VkInstance instance,
2101 const char* pName)
2102 {
2103 return radv_GetInstanceProcAddr(instance, pName);
2104 }
2105
2106 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2107 VkDevice device,
2108 const char* pName)
2109 {
2110 return radv_lookup_entrypoint(pName);
2111 }
2112
2113 bool radv_get_memory_fd(struct radv_device *device,
2114 struct radv_device_memory *memory,
2115 int *pFD)
2116 {
2117 struct radeon_bo_metadata metadata;
2118
2119 if (memory->image) {
2120 radv_init_metadata(device, memory->image, &metadata);
2121 device->ws->buffer_set_metadata(memory->bo, &metadata);
2122 }
2123
2124 return device->ws->buffer_get_fd(device->ws, memory->bo,
2125 pFD);
2126 }
2127
2128 VkResult radv_alloc_memory(VkDevice _device,
2129 const VkMemoryAllocateInfo* pAllocateInfo,
2130 const VkAllocationCallbacks* pAllocator,
2131 enum radv_mem_flags_bits mem_flags,
2132 VkDeviceMemory* pMem)
2133 {
2134 RADV_FROM_HANDLE(radv_device, device, _device);
2135 struct radv_device_memory *mem;
2136 VkResult result;
2137 enum radeon_bo_domain domain;
2138 uint32_t flags = 0;
2139 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
2140
2141 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2142
2143 if (pAllocateInfo->allocationSize == 0) {
2144 /* Apparently, this is allowed */
2145 *pMem = VK_NULL_HANDLE;
2146 return VK_SUCCESS;
2147 }
2148
2149 const VkImportMemoryFdInfoKHR *import_info =
2150 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2151 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2152 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2153
2154 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2155 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2156 if (mem == NULL)
2157 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2158
2159 if (dedicate_info) {
2160 mem->image = radv_image_from_handle(dedicate_info->image);
2161 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2162 } else {
2163 mem->image = NULL;
2164 mem->buffer = NULL;
2165 }
2166
2167 if (import_info) {
2168 assert(import_info->handleType ==
2169 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
2170 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2171 NULL, NULL);
2172 if (!mem->bo) {
2173 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2174 goto fail;
2175 } else {
2176 close(import_info->fd);
2177 goto out_success;
2178 }
2179 }
2180
2181 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2182 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2183 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
2184 domain = RADEON_DOMAIN_GTT;
2185 else
2186 domain = RADEON_DOMAIN_VRAM;
2187
2188 if (mem_type_index == RADV_MEM_TYPE_VRAM)
2189 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2190 else
2191 flags |= RADEON_FLAG_CPU_ACCESS;
2192
2193 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2194 flags |= RADEON_FLAG_GTT_WC;
2195
2196 if (mem_flags & RADV_MEM_IMPLICIT_SYNC)
2197 flags |= RADEON_FLAG_IMPLICIT_SYNC;
2198
2199 if (!dedicate_info && !import_info)
2200 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
2201
2202 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2203 domain, flags);
2204
2205 if (!mem->bo) {
2206 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2207 goto fail;
2208 }
2209 mem->type_index = mem_type_index;
2210 out_success:
2211 *pMem = radv_device_memory_to_handle(mem);
2212
2213 return VK_SUCCESS;
2214
2215 fail:
2216 vk_free2(&device->alloc, pAllocator, mem);
2217
2218 return result;
2219 }
2220
2221 VkResult radv_AllocateMemory(
2222 VkDevice _device,
2223 const VkMemoryAllocateInfo* pAllocateInfo,
2224 const VkAllocationCallbacks* pAllocator,
2225 VkDeviceMemory* pMem)
2226 {
2227 return radv_alloc_memory(_device, pAllocateInfo, pAllocator, 0, pMem);
2228 }
2229
2230 void radv_FreeMemory(
2231 VkDevice _device,
2232 VkDeviceMemory _mem,
2233 const VkAllocationCallbacks* pAllocator)
2234 {
2235 RADV_FROM_HANDLE(radv_device, device, _device);
2236 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2237
2238 if (mem == NULL)
2239 return;
2240
2241 device->ws->buffer_destroy(mem->bo);
2242 mem->bo = NULL;
2243
2244 vk_free2(&device->alloc, pAllocator, mem);
2245 }
2246
2247 VkResult radv_MapMemory(
2248 VkDevice _device,
2249 VkDeviceMemory _memory,
2250 VkDeviceSize offset,
2251 VkDeviceSize size,
2252 VkMemoryMapFlags flags,
2253 void** ppData)
2254 {
2255 RADV_FROM_HANDLE(radv_device, device, _device);
2256 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2257
2258 if (mem == NULL) {
2259 *ppData = NULL;
2260 return VK_SUCCESS;
2261 }
2262
2263 *ppData = device->ws->buffer_map(mem->bo);
2264 if (*ppData) {
2265 *ppData += offset;
2266 return VK_SUCCESS;
2267 }
2268
2269 return vk_error(VK_ERROR_MEMORY_MAP_FAILED);
2270 }
2271
2272 void radv_UnmapMemory(
2273 VkDevice _device,
2274 VkDeviceMemory _memory)
2275 {
2276 RADV_FROM_HANDLE(radv_device, device, _device);
2277 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2278
2279 if (mem == NULL)
2280 return;
2281
2282 device->ws->buffer_unmap(mem->bo);
2283 }
2284
2285 VkResult radv_FlushMappedMemoryRanges(
2286 VkDevice _device,
2287 uint32_t memoryRangeCount,
2288 const VkMappedMemoryRange* pMemoryRanges)
2289 {
2290 return VK_SUCCESS;
2291 }
2292
2293 VkResult radv_InvalidateMappedMemoryRanges(
2294 VkDevice _device,
2295 uint32_t memoryRangeCount,
2296 const VkMappedMemoryRange* pMemoryRanges)
2297 {
2298 return VK_SUCCESS;
2299 }
2300
2301 void radv_GetBufferMemoryRequirements(
2302 VkDevice _device,
2303 VkBuffer _buffer,
2304 VkMemoryRequirements* pMemoryRequirements)
2305 {
2306 RADV_FROM_HANDLE(radv_device, device, _device);
2307 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2308
2309 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2310
2311 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2312 pMemoryRequirements->alignment = 4096;
2313 else
2314 pMemoryRequirements->alignment = 16;
2315
2316 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2317 }
2318
2319 void radv_GetBufferMemoryRequirements2KHR(
2320 VkDevice device,
2321 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2322 VkMemoryRequirements2KHR* pMemoryRequirements)
2323 {
2324 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2325 &pMemoryRequirements->memoryRequirements);
2326 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
2327 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2328 switch (ext->sType) {
2329 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2330 VkMemoryDedicatedRequirementsKHR *req =
2331 (VkMemoryDedicatedRequirementsKHR *) ext;
2332 req->requiresDedicatedAllocation = buffer->shareable;
2333 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2334 break;
2335 }
2336 default:
2337 break;
2338 }
2339 }
2340 }
2341
2342 void radv_GetImageMemoryRequirements(
2343 VkDevice _device,
2344 VkImage _image,
2345 VkMemoryRequirements* pMemoryRequirements)
2346 {
2347 RADV_FROM_HANDLE(radv_device, device, _device);
2348 RADV_FROM_HANDLE(radv_image, image, _image);
2349
2350 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2351
2352 pMemoryRequirements->size = image->size;
2353 pMemoryRequirements->alignment = image->alignment;
2354 }
2355
2356 void radv_GetImageMemoryRequirements2KHR(
2357 VkDevice device,
2358 const VkImageMemoryRequirementsInfo2KHR* pInfo,
2359 VkMemoryRequirements2KHR* pMemoryRequirements)
2360 {
2361 radv_GetImageMemoryRequirements(device, pInfo->image,
2362 &pMemoryRequirements->memoryRequirements);
2363
2364 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
2365
2366 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2367 switch (ext->sType) {
2368 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2369 VkMemoryDedicatedRequirementsKHR *req =
2370 (VkMemoryDedicatedRequirementsKHR *) ext;
2371 req->requiresDedicatedAllocation = image->shareable;
2372 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2373 break;
2374 }
2375 default:
2376 break;
2377 }
2378 }
2379 }
2380
2381 void radv_GetImageSparseMemoryRequirements(
2382 VkDevice device,
2383 VkImage image,
2384 uint32_t* pSparseMemoryRequirementCount,
2385 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2386 {
2387 stub();
2388 }
2389
2390 void radv_GetImageSparseMemoryRequirements2KHR(
2391 VkDevice device,
2392 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
2393 uint32_t* pSparseMemoryRequirementCount,
2394 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
2395 {
2396 stub();
2397 }
2398
2399 void radv_GetDeviceMemoryCommitment(
2400 VkDevice device,
2401 VkDeviceMemory memory,
2402 VkDeviceSize* pCommittedMemoryInBytes)
2403 {
2404 *pCommittedMemoryInBytes = 0;
2405 }
2406
2407 VkResult radv_BindBufferMemory2KHR(VkDevice device,
2408 uint32_t bindInfoCount,
2409 const VkBindBufferMemoryInfoKHR *pBindInfos)
2410 {
2411 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2412 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2413 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
2414
2415 if (mem) {
2416 buffer->bo = mem->bo;
2417 buffer->offset = pBindInfos[i].memoryOffset;
2418 } else {
2419 buffer->bo = NULL;
2420 }
2421 }
2422 return VK_SUCCESS;
2423 }
2424
2425 VkResult radv_BindBufferMemory(
2426 VkDevice device,
2427 VkBuffer buffer,
2428 VkDeviceMemory memory,
2429 VkDeviceSize memoryOffset)
2430 {
2431 const VkBindBufferMemoryInfoKHR info = {
2432 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2433 .buffer = buffer,
2434 .memory = memory,
2435 .memoryOffset = memoryOffset
2436 };
2437
2438 return radv_BindBufferMemory2KHR(device, 1, &info);
2439 }
2440
2441 VkResult radv_BindImageMemory2KHR(VkDevice device,
2442 uint32_t bindInfoCount,
2443 const VkBindImageMemoryInfoKHR *pBindInfos)
2444 {
2445 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2446 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2447 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
2448
2449 if (mem) {
2450 image->bo = mem->bo;
2451 image->offset = pBindInfos[i].memoryOffset;
2452 } else {
2453 image->bo = NULL;
2454 image->offset = 0;
2455 }
2456 }
2457 return VK_SUCCESS;
2458 }
2459
2460
2461 VkResult radv_BindImageMemory(
2462 VkDevice device,
2463 VkImage image,
2464 VkDeviceMemory memory,
2465 VkDeviceSize memoryOffset)
2466 {
2467 const VkBindImageMemoryInfoKHR info = {
2468 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2469 .image = image,
2470 .memory = memory,
2471 .memoryOffset = memoryOffset
2472 };
2473
2474 return radv_BindImageMemory2KHR(device, 1, &info);
2475 }
2476
2477
2478 static void
2479 radv_sparse_buffer_bind_memory(struct radv_device *device,
2480 const VkSparseBufferMemoryBindInfo *bind)
2481 {
2482 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
2483
2484 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2485 struct radv_device_memory *mem = NULL;
2486
2487 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2488 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2489
2490 device->ws->buffer_virtual_bind(buffer->bo,
2491 bind->pBinds[i].resourceOffset,
2492 bind->pBinds[i].size,
2493 mem ? mem->bo : NULL,
2494 bind->pBinds[i].memoryOffset);
2495 }
2496 }
2497
2498 static void
2499 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
2500 const VkSparseImageOpaqueMemoryBindInfo *bind)
2501 {
2502 RADV_FROM_HANDLE(radv_image, image, bind->image);
2503
2504 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2505 struct radv_device_memory *mem = NULL;
2506
2507 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2508 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2509
2510 device->ws->buffer_virtual_bind(image->bo,
2511 bind->pBinds[i].resourceOffset,
2512 bind->pBinds[i].size,
2513 mem ? mem->bo : NULL,
2514 bind->pBinds[i].memoryOffset);
2515 }
2516 }
2517
2518 VkResult radv_QueueBindSparse(
2519 VkQueue _queue,
2520 uint32_t bindInfoCount,
2521 const VkBindSparseInfo* pBindInfo,
2522 VkFence _fence)
2523 {
2524 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2525 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2526 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2527 bool fence_emitted = false;
2528
2529 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2530 struct radv_winsys_sem_info sem_info;
2531 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
2532 radv_sparse_buffer_bind_memory(queue->device,
2533 pBindInfo[i].pBufferBinds + j);
2534 }
2535
2536 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
2537 radv_sparse_image_opaque_bind_memory(queue->device,
2538 pBindInfo[i].pImageOpaqueBinds + j);
2539 }
2540
2541 VkResult result;
2542 result = radv_alloc_sem_info(&sem_info,
2543 pBindInfo[i].waitSemaphoreCount,
2544 pBindInfo[i].pWaitSemaphores,
2545 pBindInfo[i].signalSemaphoreCount,
2546 pBindInfo[i].pSignalSemaphores);
2547 if (result != VK_SUCCESS)
2548 return result;
2549
2550 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
2551 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2552 &queue->device->empty_cs[queue->queue_family_index],
2553 1, NULL, NULL,
2554 &sem_info,
2555 false, base_fence);
2556 fence_emitted = true;
2557 if (fence)
2558 fence->submitted = true;
2559 }
2560
2561 radv_free_sem_info(&sem_info);
2562
2563 }
2564
2565 if (fence && !fence_emitted) {
2566 fence->signalled = true;
2567 }
2568
2569 return VK_SUCCESS;
2570 }
2571
2572 VkResult radv_CreateFence(
2573 VkDevice _device,
2574 const VkFenceCreateInfo* pCreateInfo,
2575 const VkAllocationCallbacks* pAllocator,
2576 VkFence* pFence)
2577 {
2578 RADV_FROM_HANDLE(radv_device, device, _device);
2579 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
2580 sizeof(*fence), 8,
2581 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2582
2583 if (!fence)
2584 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2585
2586 fence->submitted = false;
2587 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
2588 fence->fence = device->ws->create_fence();
2589 if (!fence->fence) {
2590 vk_free2(&device->alloc, pAllocator, fence);
2591 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2592 }
2593
2594 *pFence = radv_fence_to_handle(fence);
2595
2596 return VK_SUCCESS;
2597 }
2598
2599 void radv_DestroyFence(
2600 VkDevice _device,
2601 VkFence _fence,
2602 const VkAllocationCallbacks* pAllocator)
2603 {
2604 RADV_FROM_HANDLE(radv_device, device, _device);
2605 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2606
2607 if (!fence)
2608 return;
2609 device->ws->destroy_fence(fence->fence);
2610 vk_free2(&device->alloc, pAllocator, fence);
2611 }
2612
2613 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
2614 {
2615 uint64_t current_time;
2616 struct timespec tv;
2617
2618 clock_gettime(CLOCK_MONOTONIC, &tv);
2619 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
2620
2621 timeout = MIN2(UINT64_MAX - current_time, timeout);
2622
2623 return current_time + timeout;
2624 }
2625
2626 VkResult radv_WaitForFences(
2627 VkDevice _device,
2628 uint32_t fenceCount,
2629 const VkFence* pFences,
2630 VkBool32 waitAll,
2631 uint64_t timeout)
2632 {
2633 RADV_FROM_HANDLE(radv_device, device, _device);
2634 timeout = radv_get_absolute_timeout(timeout);
2635
2636 if (!waitAll && fenceCount > 1) {
2637 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
2638 }
2639
2640 for (uint32_t i = 0; i < fenceCount; ++i) {
2641 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2642 bool expired = false;
2643
2644 if (fence->signalled)
2645 continue;
2646
2647 if (!fence->submitted)
2648 return VK_TIMEOUT;
2649
2650 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
2651 if (!expired)
2652 return VK_TIMEOUT;
2653
2654 fence->signalled = true;
2655 }
2656
2657 return VK_SUCCESS;
2658 }
2659
2660 VkResult radv_ResetFences(VkDevice device,
2661 uint32_t fenceCount,
2662 const VkFence *pFences)
2663 {
2664 for (unsigned i = 0; i < fenceCount; ++i) {
2665 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2666 fence->submitted = fence->signalled = false;
2667 }
2668
2669 return VK_SUCCESS;
2670 }
2671
2672 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
2673 {
2674 RADV_FROM_HANDLE(radv_device, device, _device);
2675 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2676
2677 if (fence->signalled)
2678 return VK_SUCCESS;
2679 if (!fence->submitted)
2680 return VK_NOT_READY;
2681
2682 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
2683 return VK_NOT_READY;
2684
2685 return VK_SUCCESS;
2686 }
2687
2688
2689 // Queue semaphore functions
2690
2691 VkResult radv_CreateSemaphore(
2692 VkDevice _device,
2693 const VkSemaphoreCreateInfo* pCreateInfo,
2694 const VkAllocationCallbacks* pAllocator,
2695 VkSemaphore* pSemaphore)
2696 {
2697 RADV_FROM_HANDLE(radv_device, device, _device);
2698 const VkExportSemaphoreCreateInfoKHR *export =
2699 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
2700 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
2701 export ? export->handleTypes : 0;
2702
2703 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
2704 sizeof(*sem), 8,
2705 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2706 if (!sem)
2707 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2708
2709 sem->temp_syncobj = 0;
2710 /* create a syncobject if we are going to export this semaphore */
2711 if (handleTypes) {
2712 assert (device->physical_device->rad_info.has_syncobj);
2713 assert (handleTypes == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
2714 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
2715 if (ret) {
2716 vk_free2(&device->alloc, pAllocator, sem);
2717 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2718 }
2719 sem->sem = NULL;
2720 } else {
2721 sem->sem = device->ws->create_sem(device->ws);
2722 if (!sem->sem) {
2723 vk_free2(&device->alloc, pAllocator, sem);
2724 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2725 }
2726 sem->syncobj = 0;
2727 }
2728
2729 *pSemaphore = radv_semaphore_to_handle(sem);
2730 return VK_SUCCESS;
2731 }
2732
2733 void radv_DestroySemaphore(
2734 VkDevice _device,
2735 VkSemaphore _semaphore,
2736 const VkAllocationCallbacks* pAllocator)
2737 {
2738 RADV_FROM_HANDLE(radv_device, device, _device);
2739 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
2740 if (!_semaphore)
2741 return;
2742
2743 if (sem->syncobj)
2744 device->ws->destroy_syncobj(device->ws, sem->syncobj);
2745 else
2746 device->ws->destroy_sem(sem->sem);
2747 vk_free2(&device->alloc, pAllocator, sem);
2748 }
2749
2750 VkResult radv_CreateEvent(
2751 VkDevice _device,
2752 const VkEventCreateInfo* pCreateInfo,
2753 const VkAllocationCallbacks* pAllocator,
2754 VkEvent* pEvent)
2755 {
2756 RADV_FROM_HANDLE(radv_device, device, _device);
2757 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
2758 sizeof(*event), 8,
2759 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2760
2761 if (!event)
2762 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2763
2764 event->bo = device->ws->buffer_create(device->ws, 8, 8,
2765 RADEON_DOMAIN_GTT,
2766 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
2767 if (!event->bo) {
2768 vk_free2(&device->alloc, pAllocator, event);
2769 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2770 }
2771
2772 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
2773
2774 *pEvent = radv_event_to_handle(event);
2775
2776 return VK_SUCCESS;
2777 }
2778
2779 void radv_DestroyEvent(
2780 VkDevice _device,
2781 VkEvent _event,
2782 const VkAllocationCallbacks* pAllocator)
2783 {
2784 RADV_FROM_HANDLE(radv_device, device, _device);
2785 RADV_FROM_HANDLE(radv_event, event, _event);
2786
2787 if (!event)
2788 return;
2789 device->ws->buffer_destroy(event->bo);
2790 vk_free2(&device->alloc, pAllocator, event);
2791 }
2792
2793 VkResult radv_GetEventStatus(
2794 VkDevice _device,
2795 VkEvent _event)
2796 {
2797 RADV_FROM_HANDLE(radv_event, event, _event);
2798
2799 if (*event->map == 1)
2800 return VK_EVENT_SET;
2801 return VK_EVENT_RESET;
2802 }
2803
2804 VkResult radv_SetEvent(
2805 VkDevice _device,
2806 VkEvent _event)
2807 {
2808 RADV_FROM_HANDLE(radv_event, event, _event);
2809 *event->map = 1;
2810
2811 return VK_SUCCESS;
2812 }
2813
2814 VkResult radv_ResetEvent(
2815 VkDevice _device,
2816 VkEvent _event)
2817 {
2818 RADV_FROM_HANDLE(radv_event, event, _event);
2819 *event->map = 0;
2820
2821 return VK_SUCCESS;
2822 }
2823
2824 VkResult radv_CreateBuffer(
2825 VkDevice _device,
2826 const VkBufferCreateInfo* pCreateInfo,
2827 const VkAllocationCallbacks* pAllocator,
2828 VkBuffer* pBuffer)
2829 {
2830 RADV_FROM_HANDLE(radv_device, device, _device);
2831 struct radv_buffer *buffer;
2832
2833 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
2834
2835 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
2836 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2837 if (buffer == NULL)
2838 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2839
2840 buffer->size = pCreateInfo->size;
2841 buffer->usage = pCreateInfo->usage;
2842 buffer->bo = NULL;
2843 buffer->offset = 0;
2844 buffer->flags = pCreateInfo->flags;
2845
2846 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
2847 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR) != NULL;
2848
2849 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
2850 buffer->bo = device->ws->buffer_create(device->ws,
2851 align64(buffer->size, 4096),
2852 4096, 0, RADEON_FLAG_VIRTUAL);
2853 if (!buffer->bo) {
2854 vk_free2(&device->alloc, pAllocator, buffer);
2855 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2856 }
2857 }
2858
2859 *pBuffer = radv_buffer_to_handle(buffer);
2860
2861 return VK_SUCCESS;
2862 }
2863
2864 void radv_DestroyBuffer(
2865 VkDevice _device,
2866 VkBuffer _buffer,
2867 const VkAllocationCallbacks* pAllocator)
2868 {
2869 RADV_FROM_HANDLE(radv_device, device, _device);
2870 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2871
2872 if (!buffer)
2873 return;
2874
2875 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2876 device->ws->buffer_destroy(buffer->bo);
2877
2878 vk_free2(&device->alloc, pAllocator, buffer);
2879 }
2880
2881 static inline unsigned
2882 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
2883 {
2884 if (stencil)
2885 return image->surface.u.legacy.stencil_tiling_index[level];
2886 else
2887 return image->surface.u.legacy.tiling_index[level];
2888 }
2889
2890 static uint32_t radv_surface_layer_count(struct radv_image_view *iview)
2891 {
2892 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : iview->layer_count;
2893 }
2894
2895 static void
2896 radv_initialise_color_surface(struct radv_device *device,
2897 struct radv_color_buffer_info *cb,
2898 struct radv_image_view *iview)
2899 {
2900 const struct vk_format_description *desc;
2901 unsigned ntype, format, swap, endian;
2902 unsigned blend_clamp = 0, blend_bypass = 0;
2903 uint64_t va;
2904 const struct radeon_surf *surf = &iview->image->surface;
2905
2906 desc = vk_format_description(iview->vk_format);
2907
2908 memset(cb, 0, sizeof(*cb));
2909
2910 /* Intensity is implemented as Red, so treat it that way. */
2911 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
2912
2913 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
2914
2915 cb->cb_color_base = va >> 8;
2916
2917 if (device->physical_device->rad_info.chip_class >= GFX9) {
2918 struct gfx9_surf_meta_flags meta;
2919 if (iview->image->dcc_offset)
2920 meta = iview->image->surface.u.gfx9.dcc;
2921 else
2922 meta = iview->image->surface.u.gfx9.cmask;
2923
2924 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
2925 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
2926 S_028C74_RB_ALIGNED(meta.rb_aligned) |
2927 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
2928
2929 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
2930 cb->cb_color_base |= iview->image->surface.tile_swizzle;
2931 } else {
2932 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
2933 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2934
2935 cb->cb_color_base += level_info->offset >> 8;
2936 if (level_info->mode == RADEON_SURF_MODE_2D)
2937 cb->cb_color_base |= iview->image->surface.tile_swizzle;
2938
2939 pitch_tile_max = level_info->nblk_x / 8 - 1;
2940 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
2941 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
2942
2943 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2944 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2945 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
2946
2947 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
2948 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
2949
2950 if (iview->image->fmask.size) {
2951 if (device->physical_device->rad_info.chip_class >= CIK)
2952 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
2953 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
2954 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
2955 } else {
2956 /* This must be set for fast clear to work without FMASK. */
2957 if (device->physical_device->rad_info.chip_class >= CIK)
2958 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2959 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2960 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2961 }
2962 }
2963
2964 /* CMASK variables */
2965 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
2966 va += iview->image->cmask.offset;
2967 cb->cb_color_cmask = va >> 8;
2968
2969 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
2970 va += iview->image->dcc_offset;
2971 cb->cb_dcc_base = va >> 8;
2972 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
2973
2974 uint32_t max_slice = radv_surface_layer_count(iview);
2975 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
2976 S_028C6C_SLICE_MAX(iview->base_layer + max_slice - 1);
2977
2978 if (iview->image->info.samples > 1) {
2979 unsigned log_samples = util_logbase2(iview->image->info.samples);
2980
2981 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2982 S_028C74_NUM_FRAGMENTS(log_samples);
2983 }
2984
2985 if (iview->image->fmask.size) {
2986 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
2987 cb->cb_color_fmask = va >> 8;
2988 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
2989 } else {
2990 cb->cb_color_fmask = cb->cb_color_base;
2991 }
2992
2993 ntype = radv_translate_color_numformat(iview->vk_format,
2994 desc,
2995 vk_format_get_first_non_void_channel(iview->vk_format));
2996 format = radv_translate_colorformat(iview->vk_format);
2997 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
2998 radv_finishme("Illegal color\n");
2999 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3000 endian = radv_colorformat_endian_swap(format);
3001
3002 /* blend clamp should be set for all NORM/SRGB types */
3003 if (ntype == V_028C70_NUMBER_UNORM ||
3004 ntype == V_028C70_NUMBER_SNORM ||
3005 ntype == V_028C70_NUMBER_SRGB)
3006 blend_clamp = 1;
3007
3008 /* set blend bypass according to docs if SINT/UINT or
3009 8/24 COLOR variants */
3010 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3011 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3012 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3013 blend_clamp = 0;
3014 blend_bypass = 1;
3015 }
3016 #if 0
3017 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3018 (format == V_028C70_COLOR_8 ||
3019 format == V_028C70_COLOR_8_8 ||
3020 format == V_028C70_COLOR_8_8_8_8))
3021 ->color_is_int8 = true;
3022 #endif
3023 cb->cb_color_info = S_028C70_FORMAT(format) |
3024 S_028C70_COMP_SWAP(swap) |
3025 S_028C70_BLEND_CLAMP(blend_clamp) |
3026 S_028C70_BLEND_BYPASS(blend_bypass) |
3027 S_028C70_SIMPLE_FLOAT(1) |
3028 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3029 ntype != V_028C70_NUMBER_SNORM &&
3030 ntype != V_028C70_NUMBER_SRGB &&
3031 format != V_028C70_COLOR_8_24 &&
3032 format != V_028C70_COLOR_24_8) |
3033 S_028C70_NUMBER_TYPE(ntype) |
3034 S_028C70_ENDIAN(endian);
3035 if ((iview->image->info.samples > 1) && iview->image->fmask.size) {
3036 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3037 if (device->physical_device->rad_info.chip_class == SI) {
3038 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3039 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3040 }
3041 }
3042
3043 if (iview->image->cmask.size &&
3044 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3045 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3046
3047 if (radv_vi_dcc_enabled(iview->image, iview->base_mip))
3048 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3049
3050 if (device->physical_device->rad_info.chip_class >= VI) {
3051 unsigned max_uncompressed_block_size = 2;
3052 if (iview->image->info.samples > 1) {
3053 if (iview->image->surface.bpe == 1)
3054 max_uncompressed_block_size = 0;
3055 else if (iview->image->surface.bpe == 2)
3056 max_uncompressed_block_size = 1;
3057 }
3058
3059 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3060 S_028C78_INDEPENDENT_64B_BLOCKS(1);
3061 }
3062
3063 /* This must be set for fast clear to work without FMASK. */
3064 if (!iview->image->fmask.size &&
3065 device->physical_device->rad_info.chip_class == SI) {
3066 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3067 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3068 }
3069
3070 if (device->physical_device->rad_info.chip_class >= GFX9) {
3071 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
3072 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
3073
3074 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3075 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3076 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3077 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
3078 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
3079 S_028C68_MAX_MIP(iview->image->info.levels - 1);
3080
3081 cb->gfx9_epitch = S_0287A0_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3082
3083 }
3084 }
3085
3086 static void
3087 radv_initialise_ds_surface(struct radv_device *device,
3088 struct radv_ds_buffer_info *ds,
3089 struct radv_image_view *iview)
3090 {
3091 unsigned level = iview->base_mip;
3092 unsigned format, stencil_format;
3093 uint64_t va, s_offs, z_offs;
3094 bool stencil_only = false;
3095 memset(ds, 0, sizeof(*ds));
3096 switch (iview->image->vk_format) {
3097 case VK_FORMAT_D24_UNORM_S8_UINT:
3098 case VK_FORMAT_X8_D24_UNORM_PACK32:
3099 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3100 ds->offset_scale = 2.0f;
3101 break;
3102 case VK_FORMAT_D16_UNORM:
3103 case VK_FORMAT_D16_UNORM_S8_UINT:
3104 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3105 ds->offset_scale = 4.0f;
3106 break;
3107 case VK_FORMAT_D32_SFLOAT:
3108 case VK_FORMAT_D32_SFLOAT_S8_UINT:
3109 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3110 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3111 ds->offset_scale = 1.0f;
3112 break;
3113 case VK_FORMAT_S8_UINT:
3114 stencil_only = true;
3115 break;
3116 default:
3117 break;
3118 }
3119
3120 format = radv_translate_dbformat(iview->image->vk_format);
3121 stencil_format = iview->image->surface.has_stencil ?
3122 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
3123
3124 uint32_t max_slice = radv_surface_layer_count(iview);
3125 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
3126 S_028008_SLICE_MAX(iview->base_layer + max_slice - 1);
3127
3128 ds->db_htile_data_base = 0;
3129 ds->db_htile_surface = 0;
3130
3131 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3132 s_offs = z_offs = va;
3133
3134 if (device->physical_device->rad_info.chip_class >= GFX9) {
3135 assert(iview->image->surface.u.gfx9.surf_offset == 0);
3136 s_offs += iview->image->surface.u.gfx9.stencil_offset;
3137
3138 ds->db_z_info = S_028038_FORMAT(format) |
3139 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
3140 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3141 S_028038_MAXMIP(iview->image->info.levels - 1);
3142 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
3143 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
3144
3145 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3146 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
3147 ds->db_depth_view |= S_028008_MIPID(level);
3148
3149 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
3150 S_02801C_Y_MAX(iview->image->info.height - 1);
3151
3152 if (radv_htile_enabled(iview->image, level)) {
3153 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
3154
3155 if (iview->image->tc_compatible_htile) {
3156 unsigned max_zplanes = 4;
3157
3158 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
3159 iview->image->info.samples > 1)
3160 max_zplanes = 2;
3161
3162 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
3163 S_028038_ITERATE_FLUSH(1);
3164 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
3165 }
3166
3167 if (!iview->image->surface.has_stencil)
3168 /* Use all of the htile_buffer for depth if there's no stencil. */
3169 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
3170 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3171 iview->image->htile_offset;
3172 ds->db_htile_data_base = va >> 8;
3173 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
3174 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
3175 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
3176 }
3177 } else {
3178 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
3179
3180 if (stencil_only)
3181 level_info = &iview->image->surface.u.legacy.stencil_level[level];
3182
3183 z_offs += iview->image->surface.u.legacy.level[level].offset;
3184 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
3185
3186 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!iview->image->tc_compatible_htile);
3187 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
3188 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
3189
3190 if (iview->image->info.samples > 1)
3191 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
3192
3193 if (device->physical_device->rad_info.chip_class >= CIK) {
3194 struct radeon_info *info = &device->physical_device->rad_info;
3195 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
3196 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
3197 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
3198 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
3199 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
3200 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
3201
3202 if (stencil_only)
3203 tile_mode = stencil_tile_mode;
3204
3205 ds->db_depth_info |=
3206 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
3207 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
3208 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
3209 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
3210 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
3211 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
3212 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
3213 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
3214 } else {
3215 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
3216 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3217 tile_mode_index = si_tile_mode_index(iview->image, level, true);
3218 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
3219 if (stencil_only)
3220 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3221 }
3222
3223 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
3224 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
3225 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
3226
3227 if (radv_htile_enabled(iview->image, level)) {
3228 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
3229
3230 if (!iview->image->surface.has_stencil &&
3231 !iview->image->tc_compatible_htile)
3232 /* Use all of the htile_buffer for depth if there's no stencil. */
3233 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
3234
3235 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3236 iview->image->htile_offset;
3237 ds->db_htile_data_base = va >> 8;
3238 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
3239
3240 if (iview->image->tc_compatible_htile) {
3241 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
3242
3243 if (iview->image->info.samples <= 1)
3244 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
3245 else if (iview->image->info.samples <= 4)
3246 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
3247 else
3248 ds->db_z_info|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
3249 }
3250 }
3251 }
3252
3253 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
3254 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
3255 }
3256
3257 VkResult radv_CreateFramebuffer(
3258 VkDevice _device,
3259 const VkFramebufferCreateInfo* pCreateInfo,
3260 const VkAllocationCallbacks* pAllocator,
3261 VkFramebuffer* pFramebuffer)
3262 {
3263 RADV_FROM_HANDLE(radv_device, device, _device);
3264 struct radv_framebuffer *framebuffer;
3265
3266 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
3267
3268 size_t size = sizeof(*framebuffer) +
3269 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
3270 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
3271 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3272 if (framebuffer == NULL)
3273 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3274
3275 framebuffer->attachment_count = pCreateInfo->attachmentCount;
3276 framebuffer->width = pCreateInfo->width;
3277 framebuffer->height = pCreateInfo->height;
3278 framebuffer->layers = pCreateInfo->layers;
3279 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
3280 VkImageView _iview = pCreateInfo->pAttachments[i];
3281 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
3282 framebuffer->attachments[i].attachment = iview;
3283 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
3284 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
3285 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3286 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
3287 }
3288 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
3289 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
3290 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_layer_count(iview));
3291 }
3292
3293 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
3294 return VK_SUCCESS;
3295 }
3296
3297 void radv_DestroyFramebuffer(
3298 VkDevice _device,
3299 VkFramebuffer _fb,
3300 const VkAllocationCallbacks* pAllocator)
3301 {
3302 RADV_FROM_HANDLE(radv_device, device, _device);
3303 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
3304
3305 if (!fb)
3306 return;
3307 vk_free2(&device->alloc, pAllocator, fb);
3308 }
3309
3310 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
3311 {
3312 switch (address_mode) {
3313 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
3314 return V_008F30_SQ_TEX_WRAP;
3315 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
3316 return V_008F30_SQ_TEX_MIRROR;
3317 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
3318 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
3319 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
3320 return V_008F30_SQ_TEX_CLAMP_BORDER;
3321 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
3322 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
3323 default:
3324 unreachable("illegal tex wrap mode");
3325 break;
3326 }
3327 }
3328
3329 static unsigned
3330 radv_tex_compare(VkCompareOp op)
3331 {
3332 switch (op) {
3333 case VK_COMPARE_OP_NEVER:
3334 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
3335 case VK_COMPARE_OP_LESS:
3336 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
3337 case VK_COMPARE_OP_EQUAL:
3338 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
3339 case VK_COMPARE_OP_LESS_OR_EQUAL:
3340 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
3341 case VK_COMPARE_OP_GREATER:
3342 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
3343 case VK_COMPARE_OP_NOT_EQUAL:
3344 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
3345 case VK_COMPARE_OP_GREATER_OR_EQUAL:
3346 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
3347 case VK_COMPARE_OP_ALWAYS:
3348 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
3349 default:
3350 unreachable("illegal compare mode");
3351 break;
3352 }
3353 }
3354
3355 static unsigned
3356 radv_tex_filter(VkFilter filter, unsigned max_ansio)
3357 {
3358 switch (filter) {
3359 case VK_FILTER_NEAREST:
3360 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
3361 V_008F38_SQ_TEX_XY_FILTER_POINT);
3362 case VK_FILTER_LINEAR:
3363 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
3364 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
3365 case VK_FILTER_CUBIC_IMG:
3366 default:
3367 fprintf(stderr, "illegal texture filter");
3368 return 0;
3369 }
3370 }
3371
3372 static unsigned
3373 radv_tex_mipfilter(VkSamplerMipmapMode mode)
3374 {
3375 switch (mode) {
3376 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
3377 return V_008F38_SQ_TEX_Z_FILTER_POINT;
3378 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
3379 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
3380 default:
3381 return V_008F38_SQ_TEX_Z_FILTER_NONE;
3382 }
3383 }
3384
3385 static unsigned
3386 radv_tex_bordercolor(VkBorderColor bcolor)
3387 {
3388 switch (bcolor) {
3389 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
3390 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
3391 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3392 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
3393 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
3394 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3395 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
3396 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
3397 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3398 default:
3399 break;
3400 }
3401 return 0;
3402 }
3403
3404 static unsigned
3405 radv_tex_aniso_filter(unsigned filter)
3406 {
3407 if (filter < 2)
3408 return 0;
3409 if (filter < 4)
3410 return 1;
3411 if (filter < 8)
3412 return 2;
3413 if (filter < 16)
3414 return 3;
3415 return 4;
3416 }
3417
3418 static void
3419 radv_init_sampler(struct radv_device *device,
3420 struct radv_sampler *sampler,
3421 const VkSamplerCreateInfo *pCreateInfo)
3422 {
3423 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
3424 (uint32_t) pCreateInfo->maxAnisotropy : 0;
3425 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
3426 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
3427
3428 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
3429 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
3430 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
3431 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3432 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
3433 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
3434 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3435 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3436 S_008F30_DISABLE_CUBE_WRAP(0) |
3437 S_008F30_COMPAT_MODE(is_vi));
3438 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
3439 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
3440 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3441 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
3442 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
3443 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
3444 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
3445 S_008F38_MIP_POINT_PRECLAMP(0) |
3446 S_008F38_DISABLE_LSB_CEIL(1) |
3447 S_008F38_FILTER_PREC_FIX(1) |
3448 S_008F38_ANISO_OVERRIDE(is_vi));
3449 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3450 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
3451 }
3452
3453 VkResult radv_CreateSampler(
3454 VkDevice _device,
3455 const VkSamplerCreateInfo* pCreateInfo,
3456 const VkAllocationCallbacks* pAllocator,
3457 VkSampler* pSampler)
3458 {
3459 RADV_FROM_HANDLE(radv_device, device, _device);
3460 struct radv_sampler *sampler;
3461
3462 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
3463
3464 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
3465 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3466 if (!sampler)
3467 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3468
3469 radv_init_sampler(device, sampler, pCreateInfo);
3470 *pSampler = radv_sampler_to_handle(sampler);
3471
3472 return VK_SUCCESS;
3473 }
3474
3475 void radv_DestroySampler(
3476 VkDevice _device,
3477 VkSampler _sampler,
3478 const VkAllocationCallbacks* pAllocator)
3479 {
3480 RADV_FROM_HANDLE(radv_device, device, _device);
3481 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
3482
3483 if (!sampler)
3484 return;
3485 vk_free2(&device->alloc, pAllocator, sampler);
3486 }
3487
3488 /* vk_icd.h does not declare this function, so we declare it here to
3489 * suppress Wmissing-prototypes.
3490 */
3491 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3492 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
3493
3494 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3495 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
3496 {
3497 /* For the full details on loader interface versioning, see
3498 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3499 * What follows is a condensed summary, to help you navigate the large and
3500 * confusing official doc.
3501 *
3502 * - Loader interface v0 is incompatible with later versions. We don't
3503 * support it.
3504 *
3505 * - In loader interface v1:
3506 * - The first ICD entrypoint called by the loader is
3507 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3508 * entrypoint.
3509 * - The ICD must statically expose no other Vulkan symbol unless it is
3510 * linked with -Bsymbolic.
3511 * - Each dispatchable Vulkan handle created by the ICD must be
3512 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3513 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3514 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3515 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3516 * such loader-managed surfaces.
3517 *
3518 * - Loader interface v2 differs from v1 in:
3519 * - The first ICD entrypoint called by the loader is
3520 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3521 * statically expose this entrypoint.
3522 *
3523 * - Loader interface v3 differs from v2 in:
3524 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3525 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3526 * because the loader no longer does so.
3527 */
3528 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
3529 return VK_SUCCESS;
3530 }
3531
3532 VkResult radv_GetMemoryFdKHR(VkDevice _device,
3533 const VkMemoryGetFdInfoKHR *pGetFdInfo,
3534 int *pFD)
3535 {
3536 RADV_FROM_HANDLE(radv_device, device, _device);
3537 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
3538
3539 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
3540
3541 /* We support only one handle type. */
3542 assert(pGetFdInfo->handleType ==
3543 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3544
3545 bool ret = radv_get_memory_fd(device, memory, pFD);
3546 if (ret == false)
3547 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
3548 return VK_SUCCESS;
3549 }
3550
3551 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
3552 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
3553 int fd,
3554 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
3555 {
3556 /* The valid usage section for this function says:
3557 *
3558 * "handleType must not be one of the handle types defined as opaque."
3559 *
3560 * Since we only handle opaque handles for now, there are no FD properties.
3561 */
3562 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3563 }
3564
3565 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
3566 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
3567 {
3568 RADV_FROM_HANDLE(radv_device, device, _device);
3569 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
3570 uint32_t syncobj_handle = 0;
3571 uint32_t *syncobj_dst = NULL;
3572 assert(pImportSemaphoreFdInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3573
3574 int ret = device->ws->import_syncobj(device->ws, pImportSemaphoreFdInfo->fd, &syncobj_handle);
3575 if (ret != 0)
3576 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3577
3578 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
3579 syncobj_dst = &sem->temp_syncobj;
3580 } else {
3581 syncobj_dst = &sem->syncobj;
3582 }
3583
3584 if (*syncobj_dst)
3585 device->ws->destroy_syncobj(device->ws, *syncobj_dst);
3586
3587 *syncobj_dst = syncobj_handle;
3588 close(pImportSemaphoreFdInfo->fd);
3589 return VK_SUCCESS;
3590 }
3591
3592 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
3593 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
3594 int *pFd)
3595 {
3596 RADV_FROM_HANDLE(radv_device, device, _device);
3597 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
3598 int ret;
3599 uint32_t syncobj_handle;
3600
3601 assert(pGetFdInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3602 if (sem->temp_syncobj)
3603 syncobj_handle = sem->temp_syncobj;
3604 else
3605 syncobj_handle = sem->syncobj;
3606 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
3607 if (ret)
3608 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3609 return VK_SUCCESS;
3610 }
3611
3612 void radv_GetPhysicalDeviceExternalSemaphorePropertiesKHR(
3613 VkPhysicalDevice physicalDevice,
3614 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
3615 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
3616 {
3617 if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
3618 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3619 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3620 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
3621 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
3622 } else {
3623 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
3624 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
3625 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
3626 }
3627 }