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radv: split the device local memory heap into two
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_private.h"
33 #include "util/strtod.h"
34
35 #include <xf86drm.h>
36 #include <amdgpu.h>
37 #include <amdgpu_drm.h>
38 #include "amdgpu_id.h"
39 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
40 #include "ac_llvm_util.h"
41 #include "vk_format.h"
42 #include "sid.h"
43 #include "radv_timestamp.h"
44 #include "util/debug.h"
45 struct radv_dispatch_table dtable;
46
47 static VkResult
48 radv_physical_device_init(struct radv_physical_device *device,
49 struct radv_instance *instance,
50 const char *path)
51 {
52 VkResult result;
53 drmVersionPtr version;
54 int fd;
55
56 fd = open(path, O_RDWR | O_CLOEXEC);
57 if (fd < 0)
58 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
59 "failed to open %s: %m", path);
60
61 version = drmGetVersion(fd);
62 if (!version) {
63 close(fd);
64 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
65 "failed to get version %s: %m", path);
66 }
67
68 if (strcmp(version->name, "amdgpu")) {
69 drmFreeVersion(version);
70 close(fd);
71 return VK_ERROR_INCOMPATIBLE_DRIVER;
72 }
73 drmFreeVersion(version);
74
75 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
76 device->instance = instance;
77 assert(strlen(path) < ARRAY_SIZE(device->path));
78 strncpy(device->path, path, ARRAY_SIZE(device->path));
79
80 device->ws = radv_amdgpu_winsys_create(fd);
81 if (!device->ws) {
82 result = VK_ERROR_INCOMPATIBLE_DRIVER;
83 goto fail;
84 }
85 device->ws->query_info(device->ws, &device->rad_info);
86 result = radv_init_wsi(device);
87 if (result != VK_SUCCESS) {
88 device->ws->destroy(device->ws);
89 goto fail;
90 }
91
92 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
93 device->name = device->rad_info.name;
94 return VK_SUCCESS;
95
96 fail:
97 close(fd);
98 return result;
99 }
100
101 static void
102 radv_physical_device_finish(struct radv_physical_device *device)
103 {
104 radv_finish_wsi(device);
105 device->ws->destroy(device->ws);
106 }
107
108 static const VkExtensionProperties global_extensions[] = {
109 {
110 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
111 .specVersion = 25,
112 },
113 #ifdef VK_USE_PLATFORM_XCB_KHR
114 {
115 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
116 .specVersion = 5,
117 },
118 #endif
119 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
120 {
121 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
122 .specVersion = 4,
123 },
124 #endif
125 };
126
127 static const VkExtensionProperties device_extensions[] = {
128 {
129 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
130 .specVersion = 67,
131 },
132 };
133
134 static void *
135 default_alloc_func(void *pUserData, size_t size, size_t align,
136 VkSystemAllocationScope allocationScope)
137 {
138 return malloc(size);
139 }
140
141 static void *
142 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
143 size_t align, VkSystemAllocationScope allocationScope)
144 {
145 return realloc(pOriginal, size);
146 }
147
148 static void
149 default_free_func(void *pUserData, void *pMemory)
150 {
151 free(pMemory);
152 }
153
154 static const VkAllocationCallbacks default_alloc = {
155 .pUserData = NULL,
156 .pfnAllocation = default_alloc_func,
157 .pfnReallocation = default_realloc_func,
158 .pfnFree = default_free_func,
159 };
160
161 VkResult radv_CreateInstance(
162 const VkInstanceCreateInfo* pCreateInfo,
163 const VkAllocationCallbacks* pAllocator,
164 VkInstance* pInstance)
165 {
166 struct radv_instance *instance;
167
168 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
169
170 uint32_t client_version;
171 if (pCreateInfo->pApplicationInfo &&
172 pCreateInfo->pApplicationInfo->apiVersion != 0) {
173 client_version = pCreateInfo->pApplicationInfo->apiVersion;
174 } else {
175 client_version = VK_MAKE_VERSION(1, 0, 0);
176 }
177
178 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
179 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
180 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
181 "Client requested version %d.%d.%d",
182 VK_VERSION_MAJOR(client_version),
183 VK_VERSION_MINOR(client_version),
184 VK_VERSION_PATCH(client_version));
185 }
186
187 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
188 bool found = false;
189 for (uint32_t j = 0; j < ARRAY_SIZE(global_extensions); j++) {
190 if (strcmp(pCreateInfo->ppEnabledExtensionNames[i],
191 global_extensions[j].extensionName) == 0) {
192 found = true;
193 break;
194 }
195 }
196 if (!found)
197 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
198 }
199
200 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
201 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
202 if (!instance)
203 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
204
205 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
206
207 if (pAllocator)
208 instance->alloc = *pAllocator;
209 else
210 instance->alloc = default_alloc;
211
212 instance->apiVersion = client_version;
213 instance->physicalDeviceCount = -1;
214
215 _mesa_locale_init();
216
217 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
218
219 *pInstance = radv_instance_to_handle(instance);
220
221 return VK_SUCCESS;
222 }
223
224 void radv_DestroyInstance(
225 VkInstance _instance,
226 const VkAllocationCallbacks* pAllocator)
227 {
228 RADV_FROM_HANDLE(radv_instance, instance, _instance);
229
230 if (instance->physicalDeviceCount > 0) {
231 /* We support at most one physical device. */
232 assert(instance->physicalDeviceCount == 1);
233 radv_physical_device_finish(&instance->physicalDevice);
234 }
235
236 VG(VALGRIND_DESTROY_MEMPOOL(instance));
237
238 _mesa_locale_fini();
239
240 vk_free(&instance->alloc, instance);
241 }
242
243 VkResult radv_EnumeratePhysicalDevices(
244 VkInstance _instance,
245 uint32_t* pPhysicalDeviceCount,
246 VkPhysicalDevice* pPhysicalDevices)
247 {
248 RADV_FROM_HANDLE(radv_instance, instance, _instance);
249 VkResult result;
250
251 if (instance->physicalDeviceCount < 0) {
252 char path[20];
253 for (unsigned i = 0; i < 8; i++) {
254 snprintf(path, sizeof(path), "/dev/dri/renderD%d", 128 + i);
255 result = radv_physical_device_init(&instance->physicalDevice,
256 instance, path);
257 if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
258 break;
259 }
260
261 if (result == VK_ERROR_INCOMPATIBLE_DRIVER) {
262 instance->physicalDeviceCount = 0;
263 } else if (result == VK_SUCCESS) {
264 instance->physicalDeviceCount = 1;
265 } else {
266 return result;
267 }
268 }
269
270 /* pPhysicalDeviceCount is an out parameter if pPhysicalDevices is NULL;
271 * otherwise it's an inout parameter.
272 *
273 * The Vulkan spec (git aaed022) says:
274 *
275 * pPhysicalDeviceCount is a pointer to an unsigned integer variable
276 * that is initialized with the number of devices the application is
277 * prepared to receive handles to. pname:pPhysicalDevices is pointer to
278 * an array of at least this many VkPhysicalDevice handles [...].
279 *
280 * Upon success, if pPhysicalDevices is NULL, vkEnumeratePhysicalDevices
281 * overwrites the contents of the variable pointed to by
282 * pPhysicalDeviceCount with the number of physical devices in in the
283 * instance; otherwise, vkEnumeratePhysicalDevices overwrites
284 * pPhysicalDeviceCount with the number of physical handles written to
285 * pPhysicalDevices.
286 */
287 if (!pPhysicalDevices) {
288 *pPhysicalDeviceCount = instance->physicalDeviceCount;
289 } else if (*pPhysicalDeviceCount >= 1) {
290 pPhysicalDevices[0] = radv_physical_device_to_handle(&instance->physicalDevice);
291 *pPhysicalDeviceCount = 1;
292 } else if (*pPhysicalDeviceCount < instance->physicalDeviceCount) {
293 return VK_INCOMPLETE;
294 } else {
295 *pPhysicalDeviceCount = 0;
296 }
297
298 return VK_SUCCESS;
299 }
300
301 void radv_GetPhysicalDeviceFeatures(
302 VkPhysicalDevice physicalDevice,
303 VkPhysicalDeviceFeatures* pFeatures)
304 {
305 // RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
306
307 memset(pFeatures, 0, sizeof(*pFeatures));
308
309 *pFeatures = (VkPhysicalDeviceFeatures) {
310 .robustBufferAccess = true,
311 .fullDrawIndexUint32 = true,
312 .imageCubeArray = true,
313 .independentBlend = true,
314 .geometryShader = false,
315 .tessellationShader = false,
316 .sampleRateShading = false,
317 .dualSrcBlend = true,
318 .logicOp = true,
319 .multiDrawIndirect = true,
320 .drawIndirectFirstInstance = true,
321 .depthClamp = true,
322 .depthBiasClamp = true,
323 .fillModeNonSolid = true,
324 .depthBounds = true,
325 .wideLines = true,
326 .largePoints = true,
327 .alphaToOne = true,
328 .multiViewport = false,
329 .samplerAnisotropy = false, /* FINISHME */
330 .textureCompressionETC2 = false,
331 .textureCompressionASTC_LDR = false,
332 .textureCompressionBC = true,
333 .occlusionQueryPrecise = true,
334 .pipelineStatisticsQuery = false,
335 .vertexPipelineStoresAndAtomics = true,
336 .fragmentStoresAndAtomics = true,
337 .shaderTessellationAndGeometryPointSize = true,
338 .shaderImageGatherExtended = false,
339 .shaderStorageImageExtendedFormats = false,
340 .shaderStorageImageMultisample = false,
341 .shaderUniformBufferArrayDynamicIndexing = true,
342 .shaderSampledImageArrayDynamicIndexing = true,
343 .shaderStorageBufferArrayDynamicIndexing = true,
344 .shaderStorageImageArrayDynamicIndexing = true,
345 .shaderStorageImageReadWithoutFormat = false,
346 .shaderStorageImageWriteWithoutFormat = true,
347 .shaderClipDistance = true,
348 .shaderCullDistance = true,
349 .shaderFloat64 = false,
350 .shaderInt64 = false,
351 .shaderInt16 = false,
352 .alphaToOne = true,
353 .variableMultisampleRate = false,
354 .inheritedQueries = false,
355 };
356 }
357
358 void
359 radv_device_get_cache_uuid(void *uuid)
360 {
361 memset(uuid, 0, VK_UUID_SIZE);
362 snprintf(uuid, VK_UUID_SIZE, "radv-%s", RADV_TIMESTAMP);
363 }
364
365 void radv_GetPhysicalDeviceProperties(
366 VkPhysicalDevice physicalDevice,
367 VkPhysicalDeviceProperties* pProperties)
368 {
369 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
370 VkSampleCountFlags sample_counts = 0xf;
371 VkPhysicalDeviceLimits limits = {
372 .maxImageDimension1D = (1 << 14),
373 .maxImageDimension2D = (1 << 14),
374 .maxImageDimension3D = (1 << 11),
375 .maxImageDimensionCube = (1 << 14),
376 .maxImageArrayLayers = (1 << 11),
377 .maxTexelBufferElements = 128 * 1024 * 1024,
378 .maxUniformBufferRange = UINT32_MAX,
379 .maxStorageBufferRange = UINT32_MAX,
380 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
381 .maxMemoryAllocationCount = UINT32_MAX,
382 .maxSamplerAllocationCount = 64 * 1024,
383 .bufferImageGranularity = 64, /* A cache line */
384 .sparseAddressSpaceSize = 0,
385 .maxBoundDescriptorSets = MAX_SETS,
386 .maxPerStageDescriptorSamplers = 64,
387 .maxPerStageDescriptorUniformBuffers = 64,
388 .maxPerStageDescriptorStorageBuffers = 64,
389 .maxPerStageDescriptorSampledImages = 64,
390 .maxPerStageDescriptorStorageImages = 64,
391 .maxPerStageDescriptorInputAttachments = 64,
392 .maxPerStageResources = 128,
393 .maxDescriptorSetSamplers = 256,
394 .maxDescriptorSetUniformBuffers = 256,
395 .maxDescriptorSetUniformBuffersDynamic = 256,
396 .maxDescriptorSetStorageBuffers = 256,
397 .maxDescriptorSetStorageBuffersDynamic = 256,
398 .maxDescriptorSetSampledImages = 256,
399 .maxDescriptorSetStorageImages = 256,
400 .maxDescriptorSetInputAttachments = 256,
401 .maxVertexInputAttributes = 32,
402 .maxVertexInputBindings = 32,
403 .maxVertexInputAttributeOffset = 2047,
404 .maxVertexInputBindingStride = 2048,
405 .maxVertexOutputComponents = 128,
406 .maxTessellationGenerationLevel = 0,
407 .maxTessellationPatchSize = 0,
408 .maxTessellationControlPerVertexInputComponents = 0,
409 .maxTessellationControlPerVertexOutputComponents = 0,
410 .maxTessellationControlPerPatchOutputComponents = 0,
411 .maxTessellationControlTotalOutputComponents = 0,
412 .maxTessellationEvaluationInputComponents = 0,
413 .maxTessellationEvaluationOutputComponents = 0,
414 .maxGeometryShaderInvocations = 32,
415 .maxGeometryInputComponents = 64,
416 .maxGeometryOutputComponents = 128,
417 .maxGeometryOutputVertices = 256,
418 .maxGeometryTotalOutputComponents = 1024,
419 .maxFragmentInputComponents = 128,
420 .maxFragmentOutputAttachments = 8,
421 .maxFragmentDualSrcAttachments = 2,
422 .maxFragmentCombinedOutputResources = 8,
423 .maxComputeSharedMemorySize = 32768,
424 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
425 .maxComputeWorkGroupInvocations = 16 * 1024,
426 .maxComputeWorkGroupSize = {
427 16 * 1024/*devinfo->max_cs_threads*/,
428 16 * 1024,
429 16 * 1024
430 },
431 .subPixelPrecisionBits = 4 /* FIXME */,
432 .subTexelPrecisionBits = 4 /* FIXME */,
433 .mipmapPrecisionBits = 4 /* FIXME */,
434 .maxDrawIndexedIndexValue = UINT32_MAX,
435 .maxDrawIndirectCount = UINT32_MAX,
436 .maxSamplerLodBias = 16,
437 .maxSamplerAnisotropy = 16,
438 .maxViewports = MAX_VIEWPORTS,
439 .maxViewportDimensions = { (1 << 14), (1 << 14) },
440 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
441 .viewportSubPixelBits = 13, /* We take a float? */
442 .minMemoryMapAlignment = 4096, /* A page */
443 .minTexelBufferOffsetAlignment = 1,
444 .minUniformBufferOffsetAlignment = 4,
445 .minStorageBufferOffsetAlignment = 4,
446 .minTexelOffset = -8,
447 .maxTexelOffset = 7,
448 .minTexelGatherOffset = -8,
449 .maxTexelGatherOffset = 7,
450 .minInterpolationOffset = 0, /* FIXME */
451 .maxInterpolationOffset = 0, /* FIXME */
452 .subPixelInterpolationOffsetBits = 0, /* FIXME */
453 .maxFramebufferWidth = (1 << 14),
454 .maxFramebufferHeight = (1 << 14),
455 .maxFramebufferLayers = (1 << 10),
456 .framebufferColorSampleCounts = sample_counts,
457 .framebufferDepthSampleCounts = sample_counts,
458 .framebufferStencilSampleCounts = sample_counts,
459 .framebufferNoAttachmentsSampleCounts = sample_counts,
460 .maxColorAttachments = MAX_RTS,
461 .sampledImageColorSampleCounts = sample_counts,
462 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
463 .sampledImageDepthSampleCounts = sample_counts,
464 .sampledImageStencilSampleCounts = sample_counts,
465 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
466 .maxSampleMaskWords = 1,
467 .timestampComputeAndGraphics = false,
468 .timestampPeriod = 100000.0 / pdevice->rad_info.clock_crystal_freq,
469 .maxClipDistances = 8,
470 .maxCullDistances = 8,
471 .maxCombinedClipAndCullDistances = 8,
472 .discreteQueuePriorities = 1,
473 .pointSizeRange = { 0.125, 255.875 },
474 .lineWidthRange = { 0.0, 7.9921875 },
475 .pointSizeGranularity = (1.0 / 8.0),
476 .lineWidthGranularity = (1.0 / 128.0),
477 .strictLines = false, /* FINISHME */
478 .standardSampleLocations = true,
479 .optimalBufferCopyOffsetAlignment = 128,
480 .optimalBufferCopyRowPitchAlignment = 128,
481 .nonCoherentAtomSize = 64,
482 };
483
484 *pProperties = (VkPhysicalDeviceProperties) {
485 .apiVersion = VK_MAKE_VERSION(1, 0, 5),
486 .driverVersion = 1,
487 .vendorID = 0x1002,
488 .deviceID = pdevice->rad_info.pci_id,
489 .deviceType = VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU,
490 .limits = limits,
491 .sparseProperties = {0}, /* Broadwell doesn't do sparse. */
492 };
493
494 strcpy(pProperties->deviceName, pdevice->name);
495 radv_device_get_cache_uuid(pProperties->pipelineCacheUUID);
496 }
497
498 void radv_GetPhysicalDeviceQueueFamilyProperties(
499 VkPhysicalDevice physicalDevice,
500 uint32_t* pCount,
501 VkQueueFamilyProperties* pQueueFamilyProperties)
502 {
503 if (pQueueFamilyProperties == NULL) {
504 *pCount = 1;
505 return;
506 }
507 assert(*pCount >= 1);
508
509 *pQueueFamilyProperties = (VkQueueFamilyProperties) {
510 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
511 VK_QUEUE_COMPUTE_BIT |
512 VK_QUEUE_TRANSFER_BIT,
513 .queueCount = 1,
514 .timestampValidBits = 64,
515 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
516 };
517 }
518
519 void radv_GetPhysicalDeviceMemoryProperties(
520 VkPhysicalDevice physicalDevice,
521 VkPhysicalDeviceMemoryProperties* pMemoryProperties)
522 {
523 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
524
525 pMemoryProperties->memoryTypeCount = 4;
526 pMemoryProperties->memoryTypes[0] = (VkMemoryType) {
527 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
528 .heapIndex = 0,
529 };
530 pMemoryProperties->memoryTypes[1] = (VkMemoryType) {
531 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
532 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
533 .heapIndex = 2,
534 };
535 pMemoryProperties->memoryTypes[2] = (VkMemoryType) {
536 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
537 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
538 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
539 .heapIndex = 1,
540 };
541 pMemoryProperties->memoryTypes[3] = (VkMemoryType) {
542 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
543 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
544 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
545 .heapIndex = 2,
546 };
547
548 pMemoryProperties->memoryHeapCount = 3;
549 pMemoryProperties->memoryHeaps[0] = (VkMemoryHeap) {
550 .size = physical_device->rad_info.vram_size -
551 physical_device->rad_info.visible_vram_size,
552 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
553 };
554 pMemoryProperties->memoryHeaps[1] = (VkMemoryHeap) {
555 .size = physical_device->rad_info.visible_vram_size,
556 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
557 };
558 pMemoryProperties->memoryHeaps[2] = (VkMemoryHeap) {
559 .size = physical_device->rad_info.gart_size,
560 .flags = 0,
561 };
562 }
563
564 static VkResult
565 radv_queue_init(struct radv_device *device, struct radv_queue *queue)
566 {
567 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
568 queue->device = device;
569
570 return VK_SUCCESS;
571 }
572
573 static void
574 radv_queue_finish(struct radv_queue *queue)
575 {
576 }
577
578 VkResult radv_CreateDevice(
579 VkPhysicalDevice physicalDevice,
580 const VkDeviceCreateInfo* pCreateInfo,
581 const VkAllocationCallbacks* pAllocator,
582 VkDevice* pDevice)
583 {
584 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
585 VkResult result;
586 struct radv_device *device;
587
588 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
589 bool found = false;
590 for (uint32_t j = 0; j < ARRAY_SIZE(device_extensions); j++) {
591 if (strcmp(pCreateInfo->ppEnabledExtensionNames[i],
592 device_extensions[j].extensionName) == 0) {
593 found = true;
594 break;
595 }
596 }
597 if (!found)
598 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
599 }
600
601 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
602 sizeof(*device), 8,
603 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
604 if (!device)
605 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
606
607 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
608 device->instance = physical_device->instance;
609
610 device->ws = physical_device->ws;
611 if (pAllocator)
612 device->alloc = *pAllocator;
613 else
614 device->alloc = physical_device->instance->alloc;
615
616 device->hw_ctx = device->ws->ctx_create(device->ws);
617 if (!device->hw_ctx) {
618 result = VK_ERROR_OUT_OF_HOST_MEMORY;
619 goto fail_free;
620 }
621
622 radv_queue_init(device, &device->queue);
623
624 result = radv_device_init_meta(device);
625 if (result != VK_SUCCESS) {
626 device->ws->ctx_destroy(device->hw_ctx);
627 goto fail_free;
628 }
629 device->allow_fast_clears = env_var_as_boolean("RADV_FAST_CLEARS", false);
630 device->allow_dcc = !env_var_as_boolean("RADV_DCC_DISABLE", false);
631
632 if (device->allow_fast_clears && device->allow_dcc)
633 radv_finishme("DCC fast clears have not been tested\n");
634
635 radv_device_init_msaa(device);
636 device->empty_cs = device->ws->cs_create(device->ws, RING_GFX);
637 radeon_emit(device->empty_cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
638 radeon_emit(device->empty_cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
639 radeon_emit(device->empty_cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
640 device->ws->cs_finalize(device->empty_cs);
641 *pDevice = radv_device_to_handle(device);
642 return VK_SUCCESS;
643 fail_free:
644 vk_free(&device->alloc, device);
645 return result;
646 }
647
648 void radv_DestroyDevice(
649 VkDevice _device,
650 const VkAllocationCallbacks* pAllocator)
651 {
652 RADV_FROM_HANDLE(radv_device, device, _device);
653
654 device->ws->ctx_destroy(device->hw_ctx);
655 radv_queue_finish(&device->queue);
656 radv_device_finish_meta(device);
657
658 vk_free(&device->alloc, device);
659 }
660
661 VkResult radv_EnumerateInstanceExtensionProperties(
662 const char* pLayerName,
663 uint32_t* pPropertyCount,
664 VkExtensionProperties* pProperties)
665 {
666 unsigned i;
667 if (pProperties == NULL) {
668 *pPropertyCount = ARRAY_SIZE(global_extensions);
669 return VK_SUCCESS;
670 }
671
672 for (i = 0; i < *pPropertyCount; i++)
673 memcpy(&pProperties[i], &global_extensions[i], sizeof(VkExtensionProperties));
674
675 *pPropertyCount = i;
676 if (i < ARRAY_SIZE(global_extensions))
677 return VK_INCOMPLETE;
678
679 return VK_SUCCESS;
680 }
681
682 VkResult radv_EnumerateDeviceExtensionProperties(
683 VkPhysicalDevice physicalDevice,
684 const char* pLayerName,
685 uint32_t* pPropertyCount,
686 VkExtensionProperties* pProperties)
687 {
688 unsigned i;
689
690 if (pProperties == NULL) {
691 *pPropertyCount = ARRAY_SIZE(device_extensions);
692 return VK_SUCCESS;
693 }
694
695 for (i = 0; i < *pPropertyCount; i++)
696 memcpy(&pProperties[i], &device_extensions[i], sizeof(VkExtensionProperties));
697
698 *pPropertyCount = i;
699 if (i < ARRAY_SIZE(device_extensions))
700 return VK_INCOMPLETE;
701 return VK_SUCCESS;
702 }
703
704 VkResult radv_EnumerateInstanceLayerProperties(
705 uint32_t* pPropertyCount,
706 VkLayerProperties* pProperties)
707 {
708 if (pProperties == NULL) {
709 *pPropertyCount = 0;
710 return VK_SUCCESS;
711 }
712
713 /* None supported at this time */
714 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
715 }
716
717 VkResult radv_EnumerateDeviceLayerProperties(
718 VkPhysicalDevice physicalDevice,
719 uint32_t* pPropertyCount,
720 VkLayerProperties* pProperties)
721 {
722 if (pProperties == NULL) {
723 *pPropertyCount = 0;
724 return VK_SUCCESS;
725 }
726
727 /* None supported at this time */
728 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
729 }
730
731 void radv_GetDeviceQueue(
732 VkDevice _device,
733 uint32_t queueNodeIndex,
734 uint32_t queueIndex,
735 VkQueue* pQueue)
736 {
737 RADV_FROM_HANDLE(radv_device, device, _device);
738
739 assert(queueIndex == 0);
740
741 *pQueue = radv_queue_to_handle(&device->queue);
742 }
743
744 VkResult radv_QueueSubmit(
745 VkQueue _queue,
746 uint32_t submitCount,
747 const VkSubmitInfo* pSubmits,
748 VkFence _fence)
749 {
750 RADV_FROM_HANDLE(radv_queue, queue, _queue);
751 RADV_FROM_HANDLE(radv_fence, fence, _fence);
752 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
753 struct radeon_winsys_ctx *ctx = queue->device->hw_ctx;
754 int ret;
755
756 for (uint32_t i = 0; i < submitCount; i++) {
757 struct radeon_winsys_cs **cs_array;
758 bool can_patch = true;
759
760 if (!pSubmits[i].commandBufferCount)
761 continue;
762
763 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
764 pSubmits[i].commandBufferCount);
765
766 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
767 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
768 pSubmits[i].pCommandBuffers[j]);
769 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
770
771 cs_array[j] = cmd_buffer->cs;
772 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
773 can_patch = false;
774 }
775 ret = queue->device->ws->cs_submit(ctx, cs_array,
776 pSubmits[i].commandBufferCount,
777 can_patch, base_fence);
778 if (ret)
779 radv_loge("failed to submit CS %d\n", i);
780 free(cs_array);
781 }
782
783 if (fence) {
784 if (!submitCount)
785 ret = queue->device->ws->cs_submit(ctx, &queue->device->empty_cs,
786 1, false, base_fence);
787
788 fence->submitted = true;
789 }
790
791 return VK_SUCCESS;
792 }
793
794 VkResult radv_QueueWaitIdle(
795 VkQueue _queue)
796 {
797 RADV_FROM_HANDLE(radv_queue, queue, _queue);
798
799 queue->device->ws->ctx_wait_idle(queue->device->hw_ctx);
800 return VK_SUCCESS;
801 }
802
803 VkResult radv_DeviceWaitIdle(
804 VkDevice _device)
805 {
806 RADV_FROM_HANDLE(radv_device, device, _device);
807
808 device->ws->ctx_wait_idle(device->hw_ctx);
809 return VK_SUCCESS;
810 }
811
812 PFN_vkVoidFunction radv_GetInstanceProcAddr(
813 VkInstance instance,
814 const char* pName)
815 {
816 return radv_lookup_entrypoint(pName);
817 }
818
819 /* The loader wants us to expose a second GetInstanceProcAddr function
820 * to work around certain LD_PRELOAD issues seen in apps.
821 */
822 PUBLIC
823 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
824 VkInstance instance,
825 const char* pName);
826
827 PUBLIC
828 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
829 VkInstance instance,
830 const char* pName)
831 {
832 return radv_GetInstanceProcAddr(instance, pName);
833 }
834
835 PFN_vkVoidFunction radv_GetDeviceProcAddr(
836 VkDevice device,
837 const char* pName)
838 {
839 return radv_lookup_entrypoint(pName);
840 }
841
842 VkResult radv_AllocateMemory(
843 VkDevice _device,
844 const VkMemoryAllocateInfo* pAllocateInfo,
845 const VkAllocationCallbacks* pAllocator,
846 VkDeviceMemory* pMem)
847 {
848 RADV_FROM_HANDLE(radv_device, device, _device);
849 struct radv_device_memory *mem;
850 VkResult result;
851 enum radeon_bo_domain domain;
852 uint32_t flags = 0;
853 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
854
855 if (pAllocateInfo->allocationSize == 0) {
856 /* Apparently, this is allowed */
857 *pMem = VK_NULL_HANDLE;
858 return VK_SUCCESS;
859 }
860
861 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
862 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
863 if (mem == NULL)
864 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
865
866 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
867 if (pAllocateInfo->memoryTypeIndex == 1 || pAllocateInfo->memoryTypeIndex == 3)
868 domain = RADEON_DOMAIN_GTT;
869 else
870 domain = RADEON_DOMAIN_VRAM;
871
872 if (pAllocateInfo->memoryTypeIndex == 0)
873 flags |= RADEON_FLAG_NO_CPU_ACCESS;
874 else
875 flags |= RADEON_FLAG_CPU_ACCESS;
876
877 if (pAllocateInfo->memoryTypeIndex == 1)
878 flags |= RADEON_FLAG_GTT_WC;
879
880 mem->bo = device->ws->buffer_create(device->ws, alloc_size, 32768,
881 domain, flags);
882
883 if (!mem->bo) {
884 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
885 goto fail;
886 }
887 mem->type_index = pAllocateInfo->memoryTypeIndex;
888
889 *pMem = radv_device_memory_to_handle(mem);
890
891 return VK_SUCCESS;
892
893 fail:
894 vk_free2(&device->alloc, pAllocator, mem);
895
896 return result;
897 }
898
899 void radv_FreeMemory(
900 VkDevice _device,
901 VkDeviceMemory _mem,
902 const VkAllocationCallbacks* pAllocator)
903 {
904 RADV_FROM_HANDLE(radv_device, device, _device);
905 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
906
907 if (mem == NULL)
908 return;
909
910 device->ws->buffer_destroy(mem->bo);
911 mem->bo = NULL;
912
913 vk_free2(&device->alloc, pAllocator, mem);
914 }
915
916 VkResult radv_MapMemory(
917 VkDevice _device,
918 VkDeviceMemory _memory,
919 VkDeviceSize offset,
920 VkDeviceSize size,
921 VkMemoryMapFlags flags,
922 void** ppData)
923 {
924 RADV_FROM_HANDLE(radv_device, device, _device);
925 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
926
927 if (mem == NULL) {
928 *ppData = NULL;
929 return VK_SUCCESS;
930 }
931
932 *ppData = device->ws->buffer_map(mem->bo);
933 if (*ppData) {
934 *ppData += offset;
935 return VK_SUCCESS;
936 }
937
938 return VK_ERROR_MEMORY_MAP_FAILED;
939 }
940
941 void radv_UnmapMemory(
942 VkDevice _device,
943 VkDeviceMemory _memory)
944 {
945 RADV_FROM_HANDLE(radv_device, device, _device);
946 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
947
948 if (mem == NULL)
949 return;
950
951 device->ws->buffer_unmap(mem->bo);
952 }
953
954 VkResult radv_FlushMappedMemoryRanges(
955 VkDevice _device,
956 uint32_t memoryRangeCount,
957 const VkMappedMemoryRange* pMemoryRanges)
958 {
959 return VK_SUCCESS;
960 }
961
962 VkResult radv_InvalidateMappedMemoryRanges(
963 VkDevice _device,
964 uint32_t memoryRangeCount,
965 const VkMappedMemoryRange* pMemoryRanges)
966 {
967 return VK_SUCCESS;
968 }
969
970 void radv_GetBufferMemoryRequirements(
971 VkDevice device,
972 VkBuffer _buffer,
973 VkMemoryRequirements* pMemoryRequirements)
974 {
975 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
976
977 /* The Vulkan spec (git aaed022) says:
978 *
979 * memoryTypeBits is a bitfield and contains one bit set for every
980 * supported memory type for the resource. The bit `1<<i` is set if and
981 * only if the memory type `i` in the VkPhysicalDeviceMemoryProperties
982 * structure for the physical device is supported.
983 *
984 * We support exactly one memory type.
985 */
986 pMemoryRequirements->memoryTypeBits = 0x7;
987
988 pMemoryRequirements->size = buffer->size;
989 pMemoryRequirements->alignment = 16;
990 }
991
992 void radv_GetImageMemoryRequirements(
993 VkDevice device,
994 VkImage _image,
995 VkMemoryRequirements* pMemoryRequirements)
996 {
997 RADV_FROM_HANDLE(radv_image, image, _image);
998
999 /* The Vulkan spec (git aaed022) says:
1000 *
1001 * memoryTypeBits is a bitfield and contains one bit set for every
1002 * supported memory type for the resource. The bit `1<<i` is set if and
1003 * only if the memory type `i` in the VkPhysicalDeviceMemoryProperties
1004 * structure for the physical device is supported.
1005 *
1006 * We support exactly one memory type.
1007 */
1008 pMemoryRequirements->memoryTypeBits = 0x7;
1009
1010 pMemoryRequirements->size = image->size;
1011 pMemoryRequirements->alignment = image->alignment;
1012 }
1013
1014 void radv_GetImageSparseMemoryRequirements(
1015 VkDevice device,
1016 VkImage image,
1017 uint32_t* pSparseMemoryRequirementCount,
1018 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
1019 {
1020 stub();
1021 }
1022
1023 void radv_GetDeviceMemoryCommitment(
1024 VkDevice device,
1025 VkDeviceMemory memory,
1026 VkDeviceSize* pCommittedMemoryInBytes)
1027 {
1028 *pCommittedMemoryInBytes = 0;
1029 }
1030
1031 VkResult radv_BindBufferMemory(
1032 VkDevice device,
1033 VkBuffer _buffer,
1034 VkDeviceMemory _memory,
1035 VkDeviceSize memoryOffset)
1036 {
1037 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1038 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1039
1040 if (mem) {
1041 buffer->bo = mem->bo;
1042 buffer->offset = memoryOffset;
1043 } else {
1044 buffer->bo = NULL;
1045 buffer->offset = 0;
1046 }
1047
1048 return VK_SUCCESS;
1049 }
1050
1051 VkResult radv_BindImageMemory(
1052 VkDevice device,
1053 VkImage _image,
1054 VkDeviceMemory _memory,
1055 VkDeviceSize memoryOffset)
1056 {
1057 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1058 RADV_FROM_HANDLE(radv_image, image, _image);
1059
1060 if (mem) {
1061 image->bo = mem->bo;
1062 image->offset = memoryOffset;
1063 } else {
1064 image->bo = NULL;
1065 image->offset = 0;
1066 }
1067
1068 return VK_SUCCESS;
1069 }
1070
1071 VkResult radv_QueueBindSparse(
1072 VkQueue queue,
1073 uint32_t bindInfoCount,
1074 const VkBindSparseInfo* pBindInfo,
1075 VkFence fence)
1076 {
1077 stub_return(VK_ERROR_INCOMPATIBLE_DRIVER);
1078 }
1079
1080 VkResult radv_CreateFence(
1081 VkDevice _device,
1082 const VkFenceCreateInfo* pCreateInfo,
1083 const VkAllocationCallbacks* pAllocator,
1084 VkFence* pFence)
1085 {
1086 RADV_FROM_HANDLE(radv_device, device, _device);
1087 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
1088 sizeof(*fence), 8,
1089 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1090
1091 if (!fence)
1092 return VK_ERROR_OUT_OF_HOST_MEMORY;
1093
1094 memset(fence, 0, sizeof(*fence));
1095 fence->submitted = false;
1096 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
1097 fence->fence = device->ws->create_fence();
1098
1099
1100 *pFence = radv_fence_to_handle(fence);
1101
1102 return VK_SUCCESS;
1103 }
1104
1105 void radv_DestroyFence(
1106 VkDevice _device,
1107 VkFence _fence,
1108 const VkAllocationCallbacks* pAllocator)
1109 {
1110 RADV_FROM_HANDLE(radv_device, device, _device);
1111 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1112
1113 if (!fence)
1114 return;
1115 device->ws->destroy_fence(fence->fence);
1116 vk_free2(&device->alloc, pAllocator, fence);
1117 }
1118
1119 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
1120 {
1121 uint64_t current_time;
1122 struct timespec tv;
1123
1124 clock_gettime(CLOCK_MONOTONIC, &tv);
1125 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
1126
1127 timeout = MIN2(UINT64_MAX - current_time, timeout);
1128
1129 return current_time + timeout;
1130 }
1131
1132 VkResult radv_WaitForFences(
1133 VkDevice _device,
1134 uint32_t fenceCount,
1135 const VkFence* pFences,
1136 VkBool32 waitAll,
1137 uint64_t timeout)
1138 {
1139 RADV_FROM_HANDLE(radv_device, device, _device);
1140 timeout = radv_get_absolute_timeout(timeout);
1141
1142 if (!waitAll && fenceCount > 1) {
1143 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
1144 }
1145
1146 for (uint32_t i = 0; i < fenceCount; ++i) {
1147 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1148 bool expired = false;
1149
1150 if (fence->signalled)
1151 continue;
1152
1153 if (!fence->submitted)
1154 return VK_TIMEOUT;
1155
1156 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
1157 if (!expired)
1158 return VK_TIMEOUT;
1159
1160 fence->signalled = true;
1161 }
1162
1163 return VK_SUCCESS;
1164 }
1165
1166 VkResult radv_ResetFences(VkDevice device,
1167 uint32_t fenceCount,
1168 const VkFence *pFences)
1169 {
1170 for (unsigned i = 0; i < fenceCount; ++i) {
1171 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1172 fence->submitted = fence->signalled = false;
1173 }
1174
1175 return VK_SUCCESS;
1176 }
1177
1178 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
1179 {
1180 RADV_FROM_HANDLE(radv_device, device, _device);
1181 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1182
1183 if (!fence->submitted)
1184 return VK_NOT_READY;
1185
1186 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
1187 return VK_NOT_READY;
1188
1189 return VK_SUCCESS;
1190 }
1191
1192
1193 // Queue semaphore functions
1194
1195 VkResult radv_CreateSemaphore(
1196 VkDevice device,
1197 const VkSemaphoreCreateInfo* pCreateInfo,
1198 const VkAllocationCallbacks* pAllocator,
1199 VkSemaphore* pSemaphore)
1200 {
1201 /* The DRM execbuffer ioctl always execute in-oder, even between different
1202 * rings. As such, there's nothing to do for the user space semaphore.
1203 */
1204
1205 *pSemaphore = (VkSemaphore)1;
1206
1207 return VK_SUCCESS;
1208 }
1209
1210 void radv_DestroySemaphore(
1211 VkDevice device,
1212 VkSemaphore semaphore,
1213 const VkAllocationCallbacks* pAllocator)
1214 {
1215 }
1216
1217 VkResult radv_CreateEvent(
1218 VkDevice _device,
1219 const VkEventCreateInfo* pCreateInfo,
1220 const VkAllocationCallbacks* pAllocator,
1221 VkEvent* pEvent)
1222 {
1223 RADV_FROM_HANDLE(radv_device, device, _device);
1224 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
1225 sizeof(*event), 8,
1226 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1227
1228 if (!event)
1229 return VK_ERROR_OUT_OF_HOST_MEMORY;
1230
1231 event->bo = device->ws->buffer_create(device->ws, 8, 8,
1232 RADEON_DOMAIN_GTT,
1233 RADEON_FLAG_CPU_ACCESS);
1234 if (!event->bo) {
1235 vk_free2(&device->alloc, pAllocator, event);
1236 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1237 }
1238
1239 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
1240
1241 *pEvent = radv_event_to_handle(event);
1242
1243 return VK_SUCCESS;
1244 }
1245
1246 void radv_DestroyEvent(
1247 VkDevice _device,
1248 VkEvent _event,
1249 const VkAllocationCallbacks* pAllocator)
1250 {
1251 RADV_FROM_HANDLE(radv_device, device, _device);
1252 RADV_FROM_HANDLE(radv_event, event, _event);
1253
1254 if (!event)
1255 return;
1256 device->ws->buffer_destroy(event->bo);
1257 vk_free2(&device->alloc, pAllocator, event);
1258 }
1259
1260 VkResult radv_GetEventStatus(
1261 VkDevice _device,
1262 VkEvent _event)
1263 {
1264 RADV_FROM_HANDLE(radv_event, event, _event);
1265
1266 if (*event->map == 1)
1267 return VK_EVENT_SET;
1268 return VK_EVENT_RESET;
1269 }
1270
1271 VkResult radv_SetEvent(
1272 VkDevice _device,
1273 VkEvent _event)
1274 {
1275 RADV_FROM_HANDLE(radv_event, event, _event);
1276 *event->map = 1;
1277
1278 return VK_SUCCESS;
1279 }
1280
1281 VkResult radv_ResetEvent(
1282 VkDevice _device,
1283 VkEvent _event)
1284 {
1285 RADV_FROM_HANDLE(radv_event, event, _event);
1286 *event->map = 0;
1287
1288 return VK_SUCCESS;
1289 }
1290
1291 VkResult radv_CreateBuffer(
1292 VkDevice _device,
1293 const VkBufferCreateInfo* pCreateInfo,
1294 const VkAllocationCallbacks* pAllocator,
1295 VkBuffer* pBuffer)
1296 {
1297 RADV_FROM_HANDLE(radv_device, device, _device);
1298 struct radv_buffer *buffer;
1299
1300 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
1301
1302 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
1303 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1304 if (buffer == NULL)
1305 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1306
1307 buffer->size = pCreateInfo->size;
1308 buffer->usage = pCreateInfo->usage;
1309 buffer->bo = NULL;
1310 buffer->offset = 0;
1311
1312 *pBuffer = radv_buffer_to_handle(buffer);
1313
1314 return VK_SUCCESS;
1315 }
1316
1317 void radv_DestroyBuffer(
1318 VkDevice _device,
1319 VkBuffer _buffer,
1320 const VkAllocationCallbacks* pAllocator)
1321 {
1322 RADV_FROM_HANDLE(radv_device, device, _device);
1323 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1324
1325 if (!buffer)
1326 return;
1327
1328 vk_free2(&device->alloc, pAllocator, buffer);
1329 }
1330
1331 static inline unsigned
1332 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
1333 {
1334 if (stencil)
1335 return image->surface.stencil_tiling_index[level];
1336 else
1337 return image->surface.tiling_index[level];
1338 }
1339
1340 static void
1341 radv_initialise_color_surface(struct radv_device *device,
1342 struct radv_color_buffer_info *cb,
1343 struct radv_image_view *iview)
1344 {
1345 const struct vk_format_description *desc;
1346 unsigned ntype, format, swap, endian;
1347 unsigned blend_clamp = 0, blend_bypass = 0;
1348 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
1349 uint64_t va;
1350 const struct radeon_surf *surf = &iview->image->surface;
1351 const struct radeon_surf_level *level_info = &surf->level[iview->base_mip];
1352
1353 desc = vk_format_description(iview->vk_format);
1354
1355 memset(cb, 0, sizeof(*cb));
1356
1357 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1358 va += level_info->offset;
1359 cb->cb_color_base = va >> 8;
1360
1361 /* CMASK variables */
1362 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1363 va += iview->image->cmask.offset;
1364 cb->cb_color_cmask = va >> 8;
1365 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
1366
1367 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1368 va += iview->image->dcc_offset;
1369 cb->cb_dcc_base = va >> 8;
1370
1371 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
1372 S_028C6C_SLICE_MAX(iview->base_layer + iview->extent.depth - 1);
1373
1374 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
1375 pitch_tile_max = level_info->nblk_x / 8 - 1;
1376 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
1377 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
1378
1379 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
1380 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
1381
1382 /* Intensity is implemented as Red, so treat it that way. */
1383 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1) |
1384 S_028C74_TILE_MODE_INDEX(tile_mode_index);
1385
1386 if (iview->image->samples > 1) {
1387 unsigned log_samples = util_logbase2(iview->image->samples);
1388
1389 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1390 S_028C74_NUM_FRAGMENTS(log_samples);
1391 }
1392
1393 if (iview->image->fmask.size) {
1394 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
1395 if (device->instance->physicalDevice.rad_info.chip_class >= CIK)
1396 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
1397 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
1398 cb->cb_color_fmask = va >> 8;
1399 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
1400 } else {
1401 /* This must be set for fast clear to work without FMASK. */
1402 if (device->instance->physicalDevice.rad_info.chip_class >= CIK)
1403 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
1404 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
1405 cb->cb_color_fmask = cb->cb_color_base;
1406 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
1407 }
1408
1409 ntype = radv_translate_color_numformat(iview->vk_format,
1410 desc,
1411 vk_format_get_first_non_void_channel(iview->vk_format));
1412 format = radv_translate_colorformat(iview->vk_format);
1413 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
1414 radv_finishme("Illegal color\n");
1415 swap = radv_translate_colorswap(iview->vk_format, FALSE);
1416 endian = radv_colorformat_endian_swap(format);
1417
1418 /* blend clamp should be set for all NORM/SRGB types */
1419 if (ntype == V_028C70_NUMBER_UNORM ||
1420 ntype == V_028C70_NUMBER_SNORM ||
1421 ntype == V_028C70_NUMBER_SRGB)
1422 blend_clamp = 1;
1423
1424 /* set blend bypass according to docs if SINT/UINT or
1425 8/24 COLOR variants */
1426 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1427 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1428 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1429 blend_clamp = 0;
1430 blend_bypass = 1;
1431 }
1432 #if 0
1433 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
1434 (format == V_028C70_COLOR_8 ||
1435 format == V_028C70_COLOR_8_8 ||
1436 format == V_028C70_COLOR_8_8_8_8))
1437 ->color_is_int8 = true;
1438 #endif
1439 cb->cb_color_info = S_028C70_FORMAT(format) |
1440 S_028C70_COMP_SWAP(swap) |
1441 S_028C70_BLEND_CLAMP(blend_clamp) |
1442 S_028C70_BLEND_BYPASS(blend_bypass) |
1443 S_028C70_SIMPLE_FLOAT(1) |
1444 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
1445 ntype != V_028C70_NUMBER_SNORM &&
1446 ntype != V_028C70_NUMBER_SRGB &&
1447 format != V_028C70_COLOR_8_24 &&
1448 format != V_028C70_COLOR_24_8) |
1449 S_028C70_NUMBER_TYPE(ntype) |
1450 S_028C70_ENDIAN(endian);
1451 if (iview->image->samples > 1)
1452 if (iview->image->fmask.size)
1453 cb->cb_color_info |= S_028C70_COMPRESSION(1);
1454
1455 if (iview->image->cmask.size && device->allow_fast_clears)
1456 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
1457
1458 if (iview->image->surface.dcc_size && level_info->dcc_enabled)
1459 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
1460
1461 if (device->instance->physicalDevice.rad_info.chip_class >= VI) {
1462 unsigned max_uncompressed_block_size = 2;
1463 if (iview->image->samples > 1) {
1464 if (iview->image->surface.bpe == 1)
1465 max_uncompressed_block_size = 0;
1466 else if (iview->image->surface.bpe == 2)
1467 max_uncompressed_block_size = 1;
1468 }
1469
1470 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
1471 S_028C78_INDEPENDENT_64B_BLOCKS(1);
1472 }
1473
1474 /* This must be set for fast clear to work without FMASK. */
1475 if (!iview->image->fmask.size &&
1476 device->instance->physicalDevice.rad_info.chip_class == SI) {
1477 unsigned bankh = util_logbase2(iview->image->surface.bankh);
1478 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
1479 }
1480 }
1481
1482 static void
1483 radv_initialise_ds_surface(struct radv_device *device,
1484 struct radv_ds_buffer_info *ds,
1485 struct radv_image_view *iview)
1486 {
1487 unsigned level = iview->base_mip;
1488 unsigned format;
1489 uint64_t va, s_offs, z_offs;
1490 const struct radeon_surf_level *level_info = &iview->image->surface.level[level];
1491 memset(ds, 0, sizeof(*ds));
1492 switch (iview->vk_format) {
1493 case VK_FORMAT_D24_UNORM_S8_UINT:
1494 case VK_FORMAT_X8_D24_UNORM_PACK32:
1495 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1496 ds->offset_scale = 2.0f;
1497 break;
1498 case VK_FORMAT_D16_UNORM:
1499 case VK_FORMAT_D16_UNORM_S8_UINT:
1500 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1501 ds->offset_scale = 4.0f;
1502 break;
1503 case VK_FORMAT_D32_SFLOAT:
1504 case VK_FORMAT_D32_SFLOAT_S8_UINT:
1505 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1506 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1507 ds->offset_scale = 1.0f;
1508 break;
1509 default:
1510 break;
1511 }
1512
1513 format = radv_translate_dbformat(iview->vk_format);
1514 if (format == V_028040_Z_INVALID) {
1515 fprintf(stderr, "Invalid DB format: %d, disabling DB.\n", iview->vk_format);
1516 }
1517
1518 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1519 s_offs = z_offs = va;
1520 z_offs += iview->image->surface.level[level].offset;
1521 s_offs += iview->image->surface.stencil_level[level].offset;
1522
1523 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
1524 S_028008_SLICE_MAX(iview->base_layer + iview->extent.depth - 1);
1525 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1526 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
1527
1528 if (iview->image->samples > 1)
1529 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->samples));
1530
1531 if (iview->image->surface.flags & RADEON_SURF_SBUFFER)
1532 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8);
1533 else
1534 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1535
1536 if (device->instance->physicalDevice.rad_info.chip_class >= CIK) {
1537 struct radeon_info *info = &device->instance->physicalDevice.rad_info;
1538 unsigned tiling_index = iview->image->surface.tiling_index[level];
1539 unsigned stencil_index = iview->image->surface.stencil_tiling_index[level];
1540 unsigned macro_index = iview->image->surface.macro_tile_index;
1541 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
1542 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
1543 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
1544
1545 ds->db_depth_info |=
1546 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
1547 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
1548 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
1549 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
1550 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
1551 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
1552 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
1553 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
1554 } else {
1555 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
1556 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1557 tile_mode_index = si_tile_mode_index(iview->image, level, true);
1558 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1559 }
1560
1561 if (iview->image->htile.size && !level) {
1562 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
1563 S_028040_ALLOW_EXPCLEAR(1);
1564
1565 if (iview->image->surface.flags & RADEON_SURF_SBUFFER) {
1566 /* Workaround: For a not yet understood reason, the
1567 * combination of MSAA, fast stencil clear and stencil
1568 * decompress messes with subsequent stencil buffer
1569 * uses. Problem was reproduced on Verde, Bonaire,
1570 * Tonga, and Carrizo.
1571 *
1572 * Disabling EXPCLEAR works around the problem.
1573 *
1574 * Check piglit's arb_texture_multisample-stencil-clear
1575 * test if you want to try changing this.
1576 */
1577 if (iview->image->samples <= 1)
1578 ds->db_stencil_info |= S_028044_ALLOW_EXPCLEAR(1);
1579 } else
1580 /* Use all of the htile_buffer for depth if there's no stencil. */
1581 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1582
1583 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
1584 iview->image->htile.offset;
1585 ds->db_htile_data_base = va >> 8;
1586 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
1587 } else {
1588 ds->db_htile_data_base = 0;
1589 ds->db_htile_surface = 0;
1590 }
1591
1592 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
1593 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
1594
1595 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
1596 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
1597 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
1598 }
1599
1600 VkResult radv_CreateFramebuffer(
1601 VkDevice _device,
1602 const VkFramebufferCreateInfo* pCreateInfo,
1603 const VkAllocationCallbacks* pAllocator,
1604 VkFramebuffer* pFramebuffer)
1605 {
1606 RADV_FROM_HANDLE(radv_device, device, _device);
1607 struct radv_framebuffer *framebuffer;
1608
1609 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
1610
1611 size_t size = sizeof(*framebuffer) +
1612 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
1613 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
1614 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1615 if (framebuffer == NULL)
1616 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1617
1618 framebuffer->attachment_count = pCreateInfo->attachmentCount;
1619 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
1620 VkImageView _iview = pCreateInfo->pAttachments[i];
1621 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
1622 framebuffer->attachments[i].attachment = iview;
1623 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
1624 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
1625 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
1626 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
1627 }
1628 }
1629
1630 framebuffer->width = pCreateInfo->width;
1631 framebuffer->height = pCreateInfo->height;
1632 framebuffer->layers = pCreateInfo->layers;
1633
1634 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
1635 return VK_SUCCESS;
1636 }
1637
1638 void radv_DestroyFramebuffer(
1639 VkDevice _device,
1640 VkFramebuffer _fb,
1641 const VkAllocationCallbacks* pAllocator)
1642 {
1643 RADV_FROM_HANDLE(radv_device, device, _device);
1644 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
1645
1646 if (!fb)
1647 return;
1648 vk_free2(&device->alloc, pAllocator, fb);
1649 }
1650
1651 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
1652 {
1653 switch (address_mode) {
1654 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
1655 return V_008F30_SQ_TEX_WRAP;
1656 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
1657 return V_008F30_SQ_TEX_MIRROR;
1658 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
1659 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1660 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
1661 return V_008F30_SQ_TEX_CLAMP_BORDER;
1662 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
1663 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1664 default:
1665 unreachable("illegal tex wrap mode");
1666 break;
1667 }
1668 }
1669
1670 static unsigned
1671 radv_tex_compare(VkCompareOp op)
1672 {
1673 switch (op) {
1674 case VK_COMPARE_OP_NEVER:
1675 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1676 case VK_COMPARE_OP_LESS:
1677 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1678 case VK_COMPARE_OP_EQUAL:
1679 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1680 case VK_COMPARE_OP_LESS_OR_EQUAL:
1681 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1682 case VK_COMPARE_OP_GREATER:
1683 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1684 case VK_COMPARE_OP_NOT_EQUAL:
1685 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1686 case VK_COMPARE_OP_GREATER_OR_EQUAL:
1687 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1688 case VK_COMPARE_OP_ALWAYS:
1689 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1690 default:
1691 unreachable("illegal compare mode");
1692 break;
1693 }
1694 }
1695
1696 static unsigned
1697 radv_tex_filter(VkFilter filter, unsigned max_ansio)
1698 {
1699 switch (filter) {
1700 case VK_FILTER_NEAREST:
1701 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
1702 V_008F38_SQ_TEX_XY_FILTER_POINT);
1703 case VK_FILTER_LINEAR:
1704 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
1705 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
1706 case VK_FILTER_CUBIC_IMG:
1707 default:
1708 fprintf(stderr, "illegal texture filter");
1709 return 0;
1710 }
1711 }
1712
1713 static unsigned
1714 radv_tex_mipfilter(VkSamplerMipmapMode mode)
1715 {
1716 switch (mode) {
1717 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
1718 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1719 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
1720 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1721 default:
1722 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1723 }
1724 }
1725
1726 static unsigned
1727 radv_tex_bordercolor(VkBorderColor bcolor)
1728 {
1729 switch (bcolor) {
1730 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
1731 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
1732 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
1733 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
1734 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
1735 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
1736 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
1737 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
1738 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
1739 default:
1740 break;
1741 }
1742 return 0;
1743 }
1744
1745 static void
1746 radv_init_sampler(struct radv_device *device,
1747 struct radv_sampler *sampler,
1748 const VkSamplerCreateInfo *pCreateInfo)
1749 {
1750 uint32_t max_aniso = 0;
1751 uint32_t max_aniso_ratio = 0;//TODO
1752 bool is_vi;
1753 is_vi = (device->instance->physicalDevice.rad_info.chip_class >= VI);
1754
1755 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
1756 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
1757 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
1758 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
1759 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
1760 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
1761 S_008F30_DISABLE_CUBE_WRAP(0) |
1762 S_008F30_COMPAT_MODE(is_vi));
1763 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
1764 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)));
1765 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
1766 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
1767 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
1768 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
1769 S_008F38_MIP_POINT_PRECLAMP(1) |
1770 S_008F38_DISABLE_LSB_CEIL(1) |
1771 S_008F38_FILTER_PREC_FIX(1) |
1772 S_008F38_ANISO_OVERRIDE(is_vi));
1773 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
1774 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
1775 }
1776
1777 VkResult radv_CreateSampler(
1778 VkDevice _device,
1779 const VkSamplerCreateInfo* pCreateInfo,
1780 const VkAllocationCallbacks* pAllocator,
1781 VkSampler* pSampler)
1782 {
1783 RADV_FROM_HANDLE(radv_device, device, _device);
1784 struct radv_sampler *sampler;
1785
1786 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
1787
1788 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
1789 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1790 if (!sampler)
1791 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1792
1793 radv_init_sampler(device, sampler, pCreateInfo);
1794 *pSampler = radv_sampler_to_handle(sampler);
1795
1796 return VK_SUCCESS;
1797 }
1798
1799 void radv_DestroySampler(
1800 VkDevice _device,
1801 VkSampler _sampler,
1802 const VkAllocationCallbacks* pAllocator)
1803 {
1804 RADV_FROM_HANDLE(radv_device, device, _device);
1805 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
1806
1807 if (!sampler)
1808 return;
1809 vk_free2(&device->alloc, pAllocator, sampler);
1810 }