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radv/gfx9: do not load VGPR1 when GS uses points or lines
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "gfx9d.h"
47 #include "util/debug.h"
48
49 static int
50 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
51 {
52 uint32_t mesa_timestamp, llvm_timestamp;
53 uint16_t f = family;
54 memset(uuid, 0, VK_UUID_SIZE);
55 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
56 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
57 return -1;
58
59 memcpy(uuid, &mesa_timestamp, 4);
60 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
61 memcpy((char*)uuid + 8, &f, 2);
62 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
63 return 0;
64 }
65
66 static void
67 radv_get_driver_uuid(void *uuid)
68 {
69 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
70 }
71
72 static void
73 radv_get_device_uuid(struct radeon_info *info, void *uuid)
74 {
75 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
76 }
77
78 static void
79 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
80 {
81 const char *chip_string;
82 char llvm_string[32] = {};
83
84 switch (family) {
85 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
86 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
87 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
88 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
89 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
90 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
91 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
92 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
93 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
94 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
95 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
96 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
97 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
98 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
99 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
100 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
101 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
102 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
103 case CHIP_VEGA10: chip_string = "AMD RADV VEGA"; break;
104 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
105 default: chip_string = "AMD RADV unknown"; break;
106 }
107
108 if (HAVE_LLVM > 0) {
109 snprintf(llvm_string, sizeof(llvm_string),
110 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
111 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
112 }
113
114 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
115 }
116
117 static void
118 radv_physical_device_init_mem_types(struct radv_physical_device *device)
119 {
120 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
121 uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
122 device->rad_info.vram_vis_size);
123
124 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
125 device->memory_properties.memoryHeapCount = 0;
126 if (device->rad_info.vram_size - visible_vram_size > 0) {
127 vram_index = device->memory_properties.memoryHeapCount++;
128 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
129 .size = device->rad_info.vram_size - visible_vram_size,
130 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
131 };
132 }
133 if (visible_vram_size) {
134 visible_vram_index = device->memory_properties.memoryHeapCount++;
135 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
136 .size = visible_vram_size,
137 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
138 };
139 }
140 if (device->rad_info.gart_size > 0) {
141 gart_index = device->memory_properties.memoryHeapCount++;
142 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
143 .size = device->rad_info.gart_size,
144 .flags = 0,
145 };
146 }
147
148 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
149 unsigned type_count = 0;
150 if (vram_index >= 0) {
151 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
152 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
153 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
154 .heapIndex = vram_index,
155 };
156 }
157 if (gart_index >= 0) {
158 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
159 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
160 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
161 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
162 .heapIndex = gart_index,
163 };
164 }
165 if (visible_vram_index >= 0) {
166 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
167 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
168 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
169 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
170 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
171 .heapIndex = visible_vram_index,
172 };
173 }
174 if (gart_index >= 0) {
175 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
176 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
177 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
178 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
179 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
180 .heapIndex = gart_index,
181 };
182 }
183 device->memory_properties.memoryTypeCount = type_count;
184 }
185
186 static VkResult
187 radv_physical_device_init(struct radv_physical_device *device,
188 struct radv_instance *instance,
189 drmDevicePtr drm_device)
190 {
191 const char *path = drm_device->nodes[DRM_NODE_RENDER];
192 VkResult result;
193 drmVersionPtr version;
194 int fd;
195
196 fd = open(path, O_RDWR | O_CLOEXEC);
197 if (fd < 0)
198 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
199
200 version = drmGetVersion(fd);
201 if (!version) {
202 close(fd);
203 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
204 "failed to get version %s: %m", path);
205 }
206
207 if (strcmp(version->name, "amdgpu")) {
208 drmFreeVersion(version);
209 close(fd);
210 return VK_ERROR_INCOMPATIBLE_DRIVER;
211 }
212 drmFreeVersion(version);
213
214 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
215 device->instance = instance;
216 assert(strlen(path) < ARRAY_SIZE(device->path));
217 strncpy(device->path, path, ARRAY_SIZE(device->path));
218
219 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
220 instance->perftest_flags);
221 if (!device->ws) {
222 result = VK_ERROR_INCOMPATIBLE_DRIVER;
223 goto fail;
224 }
225
226 device->local_fd = fd;
227 device->ws->query_info(device->ws, &device->rad_info);
228
229 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
230
231 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
232 device->ws->destroy(device->ws);
233 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
234 "cannot generate UUID");
235 goto fail;
236 }
237
238 /* These flags affect shader compilation. */
239 uint64_t shader_env_flags =
240 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
241 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
242
243 /* The gpu id is already embeded in the uuid so we just pass "radv"
244 * when creating the cache.
245 */
246 char buf[VK_UUID_SIZE * 2 + 1];
247 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
248 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
249
250 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
251
252 radv_get_driver_uuid(&device->device_uuid);
253 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
254
255 if (device->rad_info.family == CHIP_STONEY ||
256 device->rad_info.chip_class >= GFX9) {
257 device->has_rbplus = true;
258 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY;
259 }
260
261 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
262 * on SI.
263 */
264 device->has_clear_state = device->rad_info.chip_class >= CIK;
265
266 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
267
268 radv_physical_device_init_mem_types(device);
269
270 result = radv_init_wsi(device);
271 if (result != VK_SUCCESS) {
272 device->ws->destroy(device->ws);
273 goto fail;
274 }
275
276 return VK_SUCCESS;
277
278 fail:
279 close(fd);
280 return result;
281 }
282
283 static void
284 radv_physical_device_finish(struct radv_physical_device *device)
285 {
286 radv_finish_wsi(device);
287 device->ws->destroy(device->ws);
288 disk_cache_destroy(device->disk_cache);
289 close(device->local_fd);
290 }
291
292 static void *
293 default_alloc_func(void *pUserData, size_t size, size_t align,
294 VkSystemAllocationScope allocationScope)
295 {
296 return malloc(size);
297 }
298
299 static void *
300 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
301 size_t align, VkSystemAllocationScope allocationScope)
302 {
303 return realloc(pOriginal, size);
304 }
305
306 static void
307 default_free_func(void *pUserData, void *pMemory)
308 {
309 free(pMemory);
310 }
311
312 static const VkAllocationCallbacks default_alloc = {
313 .pUserData = NULL,
314 .pfnAllocation = default_alloc_func,
315 .pfnReallocation = default_realloc_func,
316 .pfnFree = default_free_func,
317 };
318
319 static const struct debug_control radv_debug_options[] = {
320 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
321 {"nodcc", RADV_DEBUG_NO_DCC},
322 {"shaders", RADV_DEBUG_DUMP_SHADERS},
323 {"nocache", RADV_DEBUG_NO_CACHE},
324 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
325 {"nohiz", RADV_DEBUG_NO_HIZ},
326 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
327 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
328 {"allbos", RADV_DEBUG_ALL_BOS},
329 {"noibs", RADV_DEBUG_NO_IBS},
330 {"spirv", RADV_DEBUG_DUMP_SPIRV},
331 {"vmfaults", RADV_DEBUG_VM_FAULTS},
332 {"zerovram", RADV_DEBUG_ZERO_VRAM},
333 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
334 {"nosisched", RADV_DEBUG_NO_SISCHED},
335 {NULL, 0}
336 };
337
338 const char *
339 radv_get_debug_option_name(int id)
340 {
341 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
342 return radv_debug_options[id].string;
343 }
344
345 static const struct debug_control radv_perftest_options[] = {
346 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
347 {"sisched", RADV_PERFTEST_SISCHED},
348 {"localbos", RADV_PERFTEST_LOCAL_BOS},
349 {"binning", RADV_PERFTEST_BINNING},
350 {NULL, 0}
351 };
352
353 const char *
354 radv_get_perftest_option_name(int id)
355 {
356 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
357 return radv_perftest_options[id].string;
358 }
359
360 static void
361 radv_handle_per_app_options(struct radv_instance *instance,
362 const VkApplicationInfo *info)
363 {
364 const char *name = info ? info->pApplicationName : NULL;
365
366 if (!name)
367 return;
368
369 if (!strcmp(name, "Talos - Linux - 32bit") ||
370 !strcmp(name, "Talos - Linux - 64bit")) {
371 /* Force enable LLVM sisched for Talos because it looks safe
372 * and it gives few more FPS.
373 */
374 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
375 }
376 }
377
378 VkResult radv_CreateInstance(
379 const VkInstanceCreateInfo* pCreateInfo,
380 const VkAllocationCallbacks* pAllocator,
381 VkInstance* pInstance)
382 {
383 struct radv_instance *instance;
384
385 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
386
387 uint32_t client_version;
388 if (pCreateInfo->pApplicationInfo &&
389 pCreateInfo->pApplicationInfo->apiVersion != 0) {
390 client_version = pCreateInfo->pApplicationInfo->apiVersion;
391 } else {
392 client_version = VK_MAKE_VERSION(1, 0, 0);
393 }
394
395 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
396 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
397 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
398 "Client requested version %d.%d.%d",
399 VK_VERSION_MAJOR(client_version),
400 VK_VERSION_MINOR(client_version),
401 VK_VERSION_PATCH(client_version));
402 }
403
404 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
405 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
406 if (!radv_instance_extension_supported(ext_name))
407 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
408 }
409
410 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
411 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
412 if (!instance)
413 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
414
415 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
416
417 if (pAllocator)
418 instance->alloc = *pAllocator;
419 else
420 instance->alloc = default_alloc;
421
422 instance->apiVersion = client_version;
423 instance->physicalDeviceCount = -1;
424
425 _mesa_locale_init();
426
427 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
428
429 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
430 radv_debug_options);
431
432 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
433 radv_perftest_options);
434
435 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
436
437 if (instance->debug_flags & RADV_DEBUG_NO_SISCHED) {
438 /* Disable sisched when the user requests it, this is mostly
439 * useful when the driver force-enable sisched for the given
440 * application.
441 */
442 instance->perftest_flags &= ~RADV_PERFTEST_SISCHED;
443 }
444
445 *pInstance = radv_instance_to_handle(instance);
446
447 return VK_SUCCESS;
448 }
449
450 void radv_DestroyInstance(
451 VkInstance _instance,
452 const VkAllocationCallbacks* pAllocator)
453 {
454 RADV_FROM_HANDLE(radv_instance, instance, _instance);
455
456 if (!instance)
457 return;
458
459 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
460 radv_physical_device_finish(instance->physicalDevices + i);
461 }
462
463 VG(VALGRIND_DESTROY_MEMPOOL(instance));
464
465 _mesa_locale_fini();
466
467 vk_free(&instance->alloc, instance);
468 }
469
470 static VkResult
471 radv_enumerate_devices(struct radv_instance *instance)
472 {
473 /* TODO: Check for more devices ? */
474 drmDevicePtr devices[8];
475 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
476 int max_devices;
477
478 instance->physicalDeviceCount = 0;
479
480 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
481 if (max_devices < 1)
482 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
483
484 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
485 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
486 devices[i]->bustype == DRM_BUS_PCI &&
487 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
488
489 result = radv_physical_device_init(instance->physicalDevices +
490 instance->physicalDeviceCount,
491 instance,
492 devices[i]);
493 if (result == VK_SUCCESS)
494 ++instance->physicalDeviceCount;
495 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
496 break;
497 }
498 }
499 drmFreeDevices(devices, max_devices);
500
501 return result;
502 }
503
504 VkResult radv_EnumeratePhysicalDevices(
505 VkInstance _instance,
506 uint32_t* pPhysicalDeviceCount,
507 VkPhysicalDevice* pPhysicalDevices)
508 {
509 RADV_FROM_HANDLE(radv_instance, instance, _instance);
510 VkResult result;
511
512 if (instance->physicalDeviceCount < 0) {
513 result = radv_enumerate_devices(instance);
514 if (result != VK_SUCCESS &&
515 result != VK_ERROR_INCOMPATIBLE_DRIVER)
516 return result;
517 }
518
519 if (!pPhysicalDevices) {
520 *pPhysicalDeviceCount = instance->physicalDeviceCount;
521 } else {
522 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
523 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
524 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
525 }
526
527 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
528 : VK_SUCCESS;
529 }
530
531 void radv_GetPhysicalDeviceFeatures(
532 VkPhysicalDevice physicalDevice,
533 VkPhysicalDeviceFeatures* pFeatures)
534 {
535 memset(pFeatures, 0, sizeof(*pFeatures));
536
537 *pFeatures = (VkPhysicalDeviceFeatures) {
538 .robustBufferAccess = true,
539 .fullDrawIndexUint32 = true,
540 .imageCubeArray = true,
541 .independentBlend = true,
542 .geometryShader = true,
543 .tessellationShader = true,
544 .sampleRateShading = true,
545 .dualSrcBlend = true,
546 .logicOp = true,
547 .multiDrawIndirect = true,
548 .drawIndirectFirstInstance = true,
549 .depthClamp = true,
550 .depthBiasClamp = true,
551 .fillModeNonSolid = true,
552 .depthBounds = true,
553 .wideLines = true,
554 .largePoints = true,
555 .alphaToOne = true,
556 .multiViewport = true,
557 .samplerAnisotropy = true,
558 .textureCompressionETC2 = false,
559 .textureCompressionASTC_LDR = false,
560 .textureCompressionBC = true,
561 .occlusionQueryPrecise = true,
562 .pipelineStatisticsQuery = true,
563 .vertexPipelineStoresAndAtomics = true,
564 .fragmentStoresAndAtomics = true,
565 .shaderTessellationAndGeometryPointSize = true,
566 .shaderImageGatherExtended = true,
567 .shaderStorageImageExtendedFormats = true,
568 .shaderStorageImageMultisample = false,
569 .shaderUniformBufferArrayDynamicIndexing = true,
570 .shaderSampledImageArrayDynamicIndexing = true,
571 .shaderStorageBufferArrayDynamicIndexing = true,
572 .shaderStorageImageArrayDynamicIndexing = true,
573 .shaderStorageImageReadWithoutFormat = true,
574 .shaderStorageImageWriteWithoutFormat = true,
575 .shaderClipDistance = true,
576 .shaderCullDistance = true,
577 .shaderFloat64 = true,
578 .shaderInt64 = true,
579 .shaderInt16 = false,
580 .sparseBinding = true,
581 .variableMultisampleRate = true,
582 .inheritedQueries = true,
583 };
584 }
585
586 void radv_GetPhysicalDeviceFeatures2KHR(
587 VkPhysicalDevice physicalDevice,
588 VkPhysicalDeviceFeatures2KHR *pFeatures)
589 {
590 vk_foreach_struct(ext, pFeatures->pNext) {
591 switch (ext->sType) {
592 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
593 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
594 features->variablePointersStorageBuffer = true;
595 features->variablePointers = false;
596 break;
597 }
598 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHX: {
599 VkPhysicalDeviceMultiviewFeaturesKHX *features = (VkPhysicalDeviceMultiviewFeaturesKHX*)ext;
600 features->multiview = true;
601 features->multiviewGeometryShader = true;
602 features->multiviewTessellationShader = true;
603 break;
604 }
605 default:
606 break;
607 }
608 }
609 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
610 }
611
612 void radv_GetPhysicalDeviceProperties(
613 VkPhysicalDevice physicalDevice,
614 VkPhysicalDeviceProperties* pProperties)
615 {
616 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
617 VkSampleCountFlags sample_counts = 0xf;
618
619 /* make sure that the entire descriptor set is addressable with a signed
620 * 32-bit int. So the sum of all limits scaled by descriptor size has to
621 * be at most 2 GiB. the combined image & samples object count as one of
622 * both. This limit is for the pipeline layout, not for the set layout, but
623 * there is no set limit, so we just set a pipeline limit. I don't think
624 * any app is going to hit this soon. */
625 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
626 (32 /* uniform buffer, 32 due to potential space wasted on alignement */ +
627 32 /* storage buffer, 32 due to potential space wasted on alignement */ +
628 32 /* sampler, largest when combined with image */ +
629 64 /* sampled image */ +
630 64 /* storage image */);
631
632 VkPhysicalDeviceLimits limits = {
633 .maxImageDimension1D = (1 << 14),
634 .maxImageDimension2D = (1 << 14),
635 .maxImageDimension3D = (1 << 11),
636 .maxImageDimensionCube = (1 << 14),
637 .maxImageArrayLayers = (1 << 11),
638 .maxTexelBufferElements = 128 * 1024 * 1024,
639 .maxUniformBufferRange = UINT32_MAX,
640 .maxStorageBufferRange = UINT32_MAX,
641 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
642 .maxMemoryAllocationCount = UINT32_MAX,
643 .maxSamplerAllocationCount = 64 * 1024,
644 .bufferImageGranularity = 64, /* A cache line */
645 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
646 .maxBoundDescriptorSets = MAX_SETS,
647 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
648 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
649 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
650 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
651 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
652 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
653 .maxPerStageResources = max_descriptor_set_size,
654 .maxDescriptorSetSamplers = max_descriptor_set_size,
655 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
656 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
657 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
658 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
659 .maxDescriptorSetSampledImages = max_descriptor_set_size,
660 .maxDescriptorSetStorageImages = max_descriptor_set_size,
661 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
662 .maxVertexInputAttributes = 32,
663 .maxVertexInputBindings = 32,
664 .maxVertexInputAttributeOffset = 2047,
665 .maxVertexInputBindingStride = 2048,
666 .maxVertexOutputComponents = 128,
667 .maxTessellationGenerationLevel = 64,
668 .maxTessellationPatchSize = 32,
669 .maxTessellationControlPerVertexInputComponents = 128,
670 .maxTessellationControlPerVertexOutputComponents = 128,
671 .maxTessellationControlPerPatchOutputComponents = 120,
672 .maxTessellationControlTotalOutputComponents = 4096,
673 .maxTessellationEvaluationInputComponents = 128,
674 .maxTessellationEvaluationOutputComponents = 128,
675 .maxGeometryShaderInvocations = 127,
676 .maxGeometryInputComponents = 64,
677 .maxGeometryOutputComponents = 128,
678 .maxGeometryOutputVertices = 256,
679 .maxGeometryTotalOutputComponents = 1024,
680 .maxFragmentInputComponents = 128,
681 .maxFragmentOutputAttachments = 8,
682 .maxFragmentDualSrcAttachments = 1,
683 .maxFragmentCombinedOutputResources = 8,
684 .maxComputeSharedMemorySize = 32768,
685 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
686 .maxComputeWorkGroupInvocations = 2048,
687 .maxComputeWorkGroupSize = {
688 2048,
689 2048,
690 2048
691 },
692 .subPixelPrecisionBits = 4 /* FIXME */,
693 .subTexelPrecisionBits = 4 /* FIXME */,
694 .mipmapPrecisionBits = 4 /* FIXME */,
695 .maxDrawIndexedIndexValue = UINT32_MAX,
696 .maxDrawIndirectCount = UINT32_MAX,
697 .maxSamplerLodBias = 16,
698 .maxSamplerAnisotropy = 16,
699 .maxViewports = MAX_VIEWPORTS,
700 .maxViewportDimensions = { (1 << 14), (1 << 14) },
701 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
702 .viewportSubPixelBits = 13, /* We take a float? */
703 .minMemoryMapAlignment = 4096, /* A page */
704 .minTexelBufferOffsetAlignment = 1,
705 .minUniformBufferOffsetAlignment = 4,
706 .minStorageBufferOffsetAlignment = 4,
707 .minTexelOffset = -32,
708 .maxTexelOffset = 31,
709 .minTexelGatherOffset = -32,
710 .maxTexelGatherOffset = 31,
711 .minInterpolationOffset = -2,
712 .maxInterpolationOffset = 2,
713 .subPixelInterpolationOffsetBits = 8,
714 .maxFramebufferWidth = (1 << 14),
715 .maxFramebufferHeight = (1 << 14),
716 .maxFramebufferLayers = (1 << 10),
717 .framebufferColorSampleCounts = sample_counts,
718 .framebufferDepthSampleCounts = sample_counts,
719 .framebufferStencilSampleCounts = sample_counts,
720 .framebufferNoAttachmentsSampleCounts = sample_counts,
721 .maxColorAttachments = MAX_RTS,
722 .sampledImageColorSampleCounts = sample_counts,
723 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
724 .sampledImageDepthSampleCounts = sample_counts,
725 .sampledImageStencilSampleCounts = sample_counts,
726 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
727 .maxSampleMaskWords = 1,
728 .timestampComputeAndGraphics = true,
729 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
730 .maxClipDistances = 8,
731 .maxCullDistances = 8,
732 .maxCombinedClipAndCullDistances = 8,
733 .discreteQueuePriorities = 1,
734 .pointSizeRange = { 0.125, 255.875 },
735 .lineWidthRange = { 0.0, 7.9921875 },
736 .pointSizeGranularity = (1.0 / 8.0),
737 .lineWidthGranularity = (1.0 / 128.0),
738 .strictLines = false, /* FINISHME */
739 .standardSampleLocations = true,
740 .optimalBufferCopyOffsetAlignment = 128,
741 .optimalBufferCopyRowPitchAlignment = 128,
742 .nonCoherentAtomSize = 64,
743 };
744
745 *pProperties = (VkPhysicalDeviceProperties) {
746 .apiVersion = radv_physical_device_api_version(pdevice),
747 .driverVersion = vk_get_driver_version(),
748 .vendorID = ATI_VENDOR_ID,
749 .deviceID = pdevice->rad_info.pci_id,
750 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
751 .limits = limits,
752 .sparseProperties = {0},
753 };
754
755 strcpy(pProperties->deviceName, pdevice->name);
756 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
757 }
758
759 void radv_GetPhysicalDeviceProperties2KHR(
760 VkPhysicalDevice physicalDevice,
761 VkPhysicalDeviceProperties2KHR *pProperties)
762 {
763 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
764 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
765
766 vk_foreach_struct(ext, pProperties->pNext) {
767 switch (ext->sType) {
768 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
769 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
770 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
771 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
772 break;
773 }
774 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
775 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
776 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
777 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
778 properties->deviceLUIDValid = false;
779 break;
780 }
781 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHX: {
782 VkPhysicalDeviceMultiviewPropertiesKHX *properties = (VkPhysicalDeviceMultiviewPropertiesKHX*)ext;
783 properties->maxMultiviewViewCount = MAX_VIEWS;
784 properties->maxMultiviewInstanceIndex = INT_MAX;
785 break;
786 }
787 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
788 VkPhysicalDevicePointClippingPropertiesKHR *properties =
789 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
790 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
791 break;
792 }
793 default:
794 break;
795 }
796 }
797 }
798
799 static void radv_get_physical_device_queue_family_properties(
800 struct radv_physical_device* pdevice,
801 uint32_t* pCount,
802 VkQueueFamilyProperties** pQueueFamilyProperties)
803 {
804 int num_queue_families = 1;
805 int idx;
806 if (pdevice->rad_info.num_compute_rings > 0 &&
807 pdevice->rad_info.chip_class >= CIK &&
808 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
809 num_queue_families++;
810
811 if (pQueueFamilyProperties == NULL) {
812 *pCount = num_queue_families;
813 return;
814 }
815
816 if (!*pCount)
817 return;
818
819 idx = 0;
820 if (*pCount >= 1) {
821 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
822 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
823 VK_QUEUE_COMPUTE_BIT |
824 VK_QUEUE_TRANSFER_BIT |
825 VK_QUEUE_SPARSE_BINDING_BIT,
826 .queueCount = 1,
827 .timestampValidBits = 64,
828 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
829 };
830 idx++;
831 }
832
833 if (pdevice->rad_info.num_compute_rings > 0 &&
834 pdevice->rad_info.chip_class >= CIK &&
835 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
836 if (*pCount > idx) {
837 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
838 .queueFlags = VK_QUEUE_COMPUTE_BIT |
839 VK_QUEUE_TRANSFER_BIT |
840 VK_QUEUE_SPARSE_BINDING_BIT,
841 .queueCount = pdevice->rad_info.num_compute_rings,
842 .timestampValidBits = 64,
843 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
844 };
845 idx++;
846 }
847 }
848 *pCount = idx;
849 }
850
851 void radv_GetPhysicalDeviceQueueFamilyProperties(
852 VkPhysicalDevice physicalDevice,
853 uint32_t* pCount,
854 VkQueueFamilyProperties* pQueueFamilyProperties)
855 {
856 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
857 if (!pQueueFamilyProperties) {
858 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
859 return;
860 }
861 VkQueueFamilyProperties *properties[] = {
862 pQueueFamilyProperties + 0,
863 pQueueFamilyProperties + 1,
864 pQueueFamilyProperties + 2,
865 };
866 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
867 assert(*pCount <= 3);
868 }
869
870 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
871 VkPhysicalDevice physicalDevice,
872 uint32_t* pCount,
873 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
874 {
875 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
876 if (!pQueueFamilyProperties) {
877 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
878 return;
879 }
880 VkQueueFamilyProperties *properties[] = {
881 &pQueueFamilyProperties[0].queueFamilyProperties,
882 &pQueueFamilyProperties[1].queueFamilyProperties,
883 &pQueueFamilyProperties[2].queueFamilyProperties,
884 };
885 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
886 assert(*pCount <= 3);
887 }
888
889 void radv_GetPhysicalDeviceMemoryProperties(
890 VkPhysicalDevice physicalDevice,
891 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
892 {
893 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
894
895 *pMemoryProperties = physical_device->memory_properties;
896 }
897
898 void radv_GetPhysicalDeviceMemoryProperties2KHR(
899 VkPhysicalDevice physicalDevice,
900 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
901 {
902 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
903 &pMemoryProperties->memoryProperties);
904 }
905
906 static enum radeon_ctx_priority
907 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
908 {
909 /* Default to MEDIUM when a specific global priority isn't requested */
910 if (!pObj)
911 return RADEON_CTX_PRIORITY_MEDIUM;
912
913 switch(pObj->globalPriority) {
914 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
915 return RADEON_CTX_PRIORITY_REALTIME;
916 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
917 return RADEON_CTX_PRIORITY_HIGH;
918 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
919 return RADEON_CTX_PRIORITY_MEDIUM;
920 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
921 return RADEON_CTX_PRIORITY_LOW;
922 default:
923 unreachable("Illegal global priority value");
924 return RADEON_CTX_PRIORITY_INVALID;
925 }
926 }
927
928 static int
929 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
930 uint32_t queue_family_index, int idx,
931 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
932 {
933 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
934 queue->device = device;
935 queue->queue_family_index = queue_family_index;
936 queue->queue_idx = idx;
937 queue->priority = radv_get_queue_global_priority(global_priority);
938
939 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
940 if (!queue->hw_ctx)
941 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
942
943 return VK_SUCCESS;
944 }
945
946 static void
947 radv_queue_finish(struct radv_queue *queue)
948 {
949 if (queue->hw_ctx)
950 queue->device->ws->ctx_destroy(queue->hw_ctx);
951
952 if (queue->initial_full_flush_preamble_cs)
953 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
954 if (queue->initial_preamble_cs)
955 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
956 if (queue->continue_preamble_cs)
957 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
958 if (queue->descriptor_bo)
959 queue->device->ws->buffer_destroy(queue->descriptor_bo);
960 if (queue->scratch_bo)
961 queue->device->ws->buffer_destroy(queue->scratch_bo);
962 if (queue->esgs_ring_bo)
963 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
964 if (queue->gsvs_ring_bo)
965 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
966 if (queue->tess_factor_ring_bo)
967 queue->device->ws->buffer_destroy(queue->tess_factor_ring_bo);
968 if (queue->tess_offchip_ring_bo)
969 queue->device->ws->buffer_destroy(queue->tess_offchip_ring_bo);
970 if (queue->compute_scratch_bo)
971 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
972 }
973
974 static void
975 radv_device_init_gs_info(struct radv_device *device)
976 {
977 switch (device->physical_device->rad_info.family) {
978 case CHIP_OLAND:
979 case CHIP_HAINAN:
980 case CHIP_KAVERI:
981 case CHIP_KABINI:
982 case CHIP_MULLINS:
983 case CHIP_ICELAND:
984 case CHIP_CARRIZO:
985 case CHIP_STONEY:
986 device->gs_table_depth = 16;
987 return;
988 case CHIP_TAHITI:
989 case CHIP_PITCAIRN:
990 case CHIP_VERDE:
991 case CHIP_BONAIRE:
992 case CHIP_HAWAII:
993 case CHIP_TONGA:
994 case CHIP_FIJI:
995 case CHIP_POLARIS10:
996 case CHIP_POLARIS11:
997 case CHIP_POLARIS12:
998 case CHIP_VEGA10:
999 case CHIP_RAVEN:
1000 device->gs_table_depth = 32;
1001 return;
1002 default:
1003 unreachable("unknown GPU");
1004 }
1005 }
1006
1007 VkResult radv_CreateDevice(
1008 VkPhysicalDevice physicalDevice,
1009 const VkDeviceCreateInfo* pCreateInfo,
1010 const VkAllocationCallbacks* pAllocator,
1011 VkDevice* pDevice)
1012 {
1013 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1014 VkResult result;
1015 struct radv_device *device;
1016
1017 bool keep_shader_info = false;
1018
1019 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1020 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1021 if (!radv_physical_device_extension_supported(physical_device, ext_name))
1022 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
1023
1024 if (strcmp(ext_name, VK_AMD_SHADER_INFO_EXTENSION_NAME) == 0)
1025 keep_shader_info = true;
1026 }
1027
1028 /* Check enabled features */
1029 if (pCreateInfo->pEnabledFeatures) {
1030 VkPhysicalDeviceFeatures supported_features;
1031 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1032 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1033 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1034 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1035 for (uint32_t i = 0; i < num_features; i++) {
1036 if (enabled_feature[i] && !supported_feature[i])
1037 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
1038 }
1039 }
1040
1041 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1042 sizeof(*device), 8,
1043 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1044 if (!device)
1045 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1046
1047 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1048 device->instance = physical_device->instance;
1049 device->physical_device = physical_device;
1050
1051 device->ws = physical_device->ws;
1052 if (pAllocator)
1053 device->alloc = *pAllocator;
1054 else
1055 device->alloc = physical_device->instance->alloc;
1056
1057 mtx_init(&device->shader_slab_mutex, mtx_plain);
1058 list_inithead(&device->shader_slabs);
1059
1060 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1061 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1062 uint32_t qfi = queue_create->queueFamilyIndex;
1063 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1064 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1065
1066 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1067
1068 device->queues[qfi] = vk_alloc(&device->alloc,
1069 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1070 if (!device->queues[qfi]) {
1071 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1072 goto fail;
1073 }
1074
1075 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1076
1077 device->queue_count[qfi] = queue_create->queueCount;
1078
1079 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1080 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q, global_priority);
1081 if (result != VK_SUCCESS)
1082 goto fail;
1083 }
1084 }
1085
1086 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1087 (device->instance->perftest_flags & RADV_PERFTEST_BINNING);
1088
1089 /* Disabled and not implemented for now. */
1090 device->dfsm_allowed = device->pbb_allowed && false;
1091
1092
1093 #if HAVE_LLVM < 0x0400
1094 device->llvm_supports_spill = false;
1095 #else
1096 device->llvm_supports_spill = true;
1097 #endif
1098
1099 /* The maximum number of scratch waves. Scratch space isn't divided
1100 * evenly between CUs. The number is only a function of the number of CUs.
1101 * We can decrease the constant to decrease the scratch buffer size.
1102 *
1103 * sctx->scratch_waves must be >= the maximum posible size of
1104 * 1 threadgroup, so that the hw doesn't hang from being unable
1105 * to start any.
1106 *
1107 * The recommended value is 4 per CU at most. Higher numbers don't
1108 * bring much benefit, but they still occupy chip resources (think
1109 * async compute). I've seen ~2% performance difference between 4 and 32.
1110 */
1111 uint32_t max_threads_per_block = 2048;
1112 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1113 max_threads_per_block / 64);
1114
1115 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) |
1116 S_00B800_FORCE_START_AT_000(1);
1117
1118 if (device->physical_device->rad_info.chip_class >= CIK) {
1119 /* If the KMD allows it (there is a KMD hw register for it),
1120 * allow launching waves out-of-order.
1121 */
1122 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1123 }
1124
1125 radv_device_init_gs_info(device);
1126
1127 device->tess_offchip_block_dw_size =
1128 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1129 device->has_distributed_tess =
1130 device->physical_device->rad_info.chip_class >= VI &&
1131 device->physical_device->rad_info.max_se >= 2;
1132
1133 if (getenv("RADV_TRACE_FILE")) {
1134 keep_shader_info = true;
1135
1136 if (!radv_init_trace(device))
1137 goto fail;
1138 }
1139
1140 device->keep_shader_info = keep_shader_info;
1141
1142 result = radv_device_init_meta(device);
1143 if (result != VK_SUCCESS)
1144 goto fail;
1145
1146 radv_device_init_msaa(device);
1147
1148 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1149 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1150 switch (family) {
1151 case RADV_QUEUE_GENERAL:
1152 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1153 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1154 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1155 break;
1156 case RADV_QUEUE_COMPUTE:
1157 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1158 radeon_emit(device->empty_cs[family], 0);
1159 break;
1160 }
1161 device->ws->cs_finalize(device->empty_cs[family]);
1162 }
1163
1164 if (device->physical_device->rad_info.chip_class >= CIK)
1165 cik_create_gfx_config(device);
1166
1167 VkPipelineCacheCreateInfo ci;
1168 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1169 ci.pNext = NULL;
1170 ci.flags = 0;
1171 ci.pInitialData = NULL;
1172 ci.initialDataSize = 0;
1173 VkPipelineCache pc;
1174 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1175 &ci, NULL, &pc);
1176 if (result != VK_SUCCESS)
1177 goto fail;
1178
1179 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1180
1181 *pDevice = radv_device_to_handle(device);
1182 return VK_SUCCESS;
1183
1184 fail:
1185 if (device->trace_bo)
1186 device->ws->buffer_destroy(device->trace_bo);
1187
1188 if (device->gfx_init)
1189 device->ws->buffer_destroy(device->gfx_init);
1190
1191 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1192 for (unsigned q = 0; q < device->queue_count[i]; q++)
1193 radv_queue_finish(&device->queues[i][q]);
1194 if (device->queue_count[i])
1195 vk_free(&device->alloc, device->queues[i]);
1196 }
1197
1198 vk_free(&device->alloc, device);
1199 return result;
1200 }
1201
1202 void radv_DestroyDevice(
1203 VkDevice _device,
1204 const VkAllocationCallbacks* pAllocator)
1205 {
1206 RADV_FROM_HANDLE(radv_device, device, _device);
1207
1208 if (!device)
1209 return;
1210
1211 if (device->trace_bo)
1212 device->ws->buffer_destroy(device->trace_bo);
1213
1214 if (device->gfx_init)
1215 device->ws->buffer_destroy(device->gfx_init);
1216
1217 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1218 for (unsigned q = 0; q < device->queue_count[i]; q++)
1219 radv_queue_finish(&device->queues[i][q]);
1220 if (device->queue_count[i])
1221 vk_free(&device->alloc, device->queues[i]);
1222 if (device->empty_cs[i])
1223 device->ws->cs_destroy(device->empty_cs[i]);
1224 }
1225 radv_device_finish_meta(device);
1226
1227 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1228 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1229
1230 radv_destroy_shader_slabs(device);
1231
1232 vk_free(&device->alloc, device);
1233 }
1234
1235 VkResult radv_EnumerateInstanceLayerProperties(
1236 uint32_t* pPropertyCount,
1237 VkLayerProperties* pProperties)
1238 {
1239 if (pProperties == NULL) {
1240 *pPropertyCount = 0;
1241 return VK_SUCCESS;
1242 }
1243
1244 /* None supported at this time */
1245 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1246 }
1247
1248 VkResult radv_EnumerateDeviceLayerProperties(
1249 VkPhysicalDevice physicalDevice,
1250 uint32_t* pPropertyCount,
1251 VkLayerProperties* pProperties)
1252 {
1253 if (pProperties == NULL) {
1254 *pPropertyCount = 0;
1255 return VK_SUCCESS;
1256 }
1257
1258 /* None supported at this time */
1259 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1260 }
1261
1262 void radv_GetDeviceQueue(
1263 VkDevice _device,
1264 uint32_t queueFamilyIndex,
1265 uint32_t queueIndex,
1266 VkQueue* pQueue)
1267 {
1268 RADV_FROM_HANDLE(radv_device, device, _device);
1269
1270 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
1271 }
1272
1273 static void
1274 fill_geom_tess_rings(struct radv_queue *queue,
1275 uint32_t *map,
1276 bool add_sample_positions,
1277 uint32_t esgs_ring_size,
1278 struct radeon_winsys_bo *esgs_ring_bo,
1279 uint32_t gsvs_ring_size,
1280 struct radeon_winsys_bo *gsvs_ring_bo,
1281 uint32_t tess_factor_ring_size,
1282 struct radeon_winsys_bo *tess_factor_ring_bo,
1283 uint32_t tess_offchip_ring_size,
1284 struct radeon_winsys_bo *tess_offchip_ring_bo)
1285 {
1286 uint64_t esgs_va = 0, gsvs_va = 0;
1287 uint64_t tess_factor_va = 0, tess_offchip_va = 0;
1288 uint32_t *desc = &map[4];
1289
1290 if (esgs_ring_bo)
1291 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1292 if (gsvs_ring_bo)
1293 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1294 if (tess_factor_ring_bo)
1295 tess_factor_va = radv_buffer_get_va(tess_factor_ring_bo);
1296 if (tess_offchip_ring_bo)
1297 tess_offchip_va = radv_buffer_get_va(tess_offchip_ring_bo);
1298
1299 /* stride 0, num records - size, add tid, swizzle, elsize4,
1300 index stride 64 */
1301 desc[0] = esgs_va;
1302 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1303 S_008F04_STRIDE(0) |
1304 S_008F04_SWIZZLE_ENABLE(true);
1305 desc[2] = esgs_ring_size;
1306 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1307 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1308 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1309 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1310 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1311 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1312 S_008F0C_ELEMENT_SIZE(1) |
1313 S_008F0C_INDEX_STRIDE(3) |
1314 S_008F0C_ADD_TID_ENABLE(true);
1315
1316 desc += 4;
1317 /* GS entry for ES->GS ring */
1318 /* stride 0, num records - size, elsize0,
1319 index stride 0 */
1320 desc[0] = esgs_va;
1321 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1322 S_008F04_STRIDE(0) |
1323 S_008F04_SWIZZLE_ENABLE(false);
1324 desc[2] = esgs_ring_size;
1325 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1326 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1327 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1328 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1329 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1330 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1331 S_008F0C_ELEMENT_SIZE(0) |
1332 S_008F0C_INDEX_STRIDE(0) |
1333 S_008F0C_ADD_TID_ENABLE(false);
1334
1335 desc += 4;
1336 /* VS entry for GS->VS ring */
1337 /* stride 0, num records - size, elsize0,
1338 index stride 0 */
1339 desc[0] = gsvs_va;
1340 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1341 S_008F04_STRIDE(0) |
1342 S_008F04_SWIZZLE_ENABLE(false);
1343 desc[2] = gsvs_ring_size;
1344 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1345 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1346 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1347 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1348 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1349 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1350 S_008F0C_ELEMENT_SIZE(0) |
1351 S_008F0C_INDEX_STRIDE(0) |
1352 S_008F0C_ADD_TID_ENABLE(false);
1353 desc += 4;
1354
1355 /* stride gsvs_itemsize, num records 64
1356 elsize 4, index stride 16 */
1357 /* shader will patch stride and desc[2] */
1358 desc[0] = gsvs_va;
1359 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1360 S_008F04_STRIDE(0) |
1361 S_008F04_SWIZZLE_ENABLE(true);
1362 desc[2] = 0;
1363 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1364 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1365 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1366 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1367 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1368 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1369 S_008F0C_ELEMENT_SIZE(1) |
1370 S_008F0C_INDEX_STRIDE(1) |
1371 S_008F0C_ADD_TID_ENABLE(true);
1372 desc += 4;
1373
1374 desc[0] = tess_factor_va;
1375 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va >> 32) |
1376 S_008F04_STRIDE(0) |
1377 S_008F04_SWIZZLE_ENABLE(false);
1378 desc[2] = tess_factor_ring_size;
1379 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1380 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1381 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1382 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1383 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1384 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1385 S_008F0C_ELEMENT_SIZE(0) |
1386 S_008F0C_INDEX_STRIDE(0) |
1387 S_008F0C_ADD_TID_ENABLE(false);
1388 desc += 4;
1389
1390 desc[0] = tess_offchip_va;
1391 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1392 S_008F04_STRIDE(0) |
1393 S_008F04_SWIZZLE_ENABLE(false);
1394 desc[2] = tess_offchip_ring_size;
1395 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1396 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1397 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1398 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1399 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1400 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1401 S_008F0C_ELEMENT_SIZE(0) |
1402 S_008F0C_INDEX_STRIDE(0) |
1403 S_008F0C_ADD_TID_ENABLE(false);
1404 desc += 4;
1405
1406 /* add sample positions after all rings */
1407 memcpy(desc, queue->device->sample_locations_1x, 8);
1408 desc += 2;
1409 memcpy(desc, queue->device->sample_locations_2x, 16);
1410 desc += 4;
1411 memcpy(desc, queue->device->sample_locations_4x, 32);
1412 desc += 8;
1413 memcpy(desc, queue->device->sample_locations_8x, 64);
1414 desc += 16;
1415 memcpy(desc, queue->device->sample_locations_16x, 128);
1416 }
1417
1418 static unsigned
1419 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1420 {
1421 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1422 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1423 device->physical_device->rad_info.family != CHIP_STONEY;
1424 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1425 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1426 device->physical_device->rad_info.max_se;
1427 unsigned offchip_granularity;
1428 unsigned hs_offchip_param;
1429 switch (device->tess_offchip_block_dw_size) {
1430 default:
1431 assert(0);
1432 /* fall through */
1433 case 8192:
1434 offchip_granularity = V_03093C_X_8K_DWORDS;
1435 break;
1436 case 4096:
1437 offchip_granularity = V_03093C_X_4K_DWORDS;
1438 break;
1439 }
1440
1441 switch (device->physical_device->rad_info.chip_class) {
1442 case SI:
1443 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1444 break;
1445 case CIK:
1446 case VI:
1447 case GFX9:
1448 default:
1449 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1450 break;
1451 }
1452
1453 *max_offchip_buffers_p = max_offchip_buffers;
1454 if (device->physical_device->rad_info.chip_class >= CIK) {
1455 if (device->physical_device->rad_info.chip_class >= VI)
1456 --max_offchip_buffers;
1457 hs_offchip_param =
1458 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1459 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1460 } else {
1461 hs_offchip_param =
1462 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1463 }
1464 return hs_offchip_param;
1465 }
1466
1467 static VkResult
1468 radv_get_preamble_cs(struct radv_queue *queue,
1469 uint32_t scratch_size,
1470 uint32_t compute_scratch_size,
1471 uint32_t esgs_ring_size,
1472 uint32_t gsvs_ring_size,
1473 bool needs_tess_rings,
1474 bool needs_sample_positions,
1475 struct radeon_winsys_cs **initial_full_flush_preamble_cs,
1476 struct radeon_winsys_cs **initial_preamble_cs,
1477 struct radeon_winsys_cs **continue_preamble_cs)
1478 {
1479 struct radeon_winsys_bo *scratch_bo = NULL;
1480 struct radeon_winsys_bo *descriptor_bo = NULL;
1481 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1482 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1483 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1484 struct radeon_winsys_bo *tess_factor_ring_bo = NULL;
1485 struct radeon_winsys_bo *tess_offchip_ring_bo = NULL;
1486 struct radeon_winsys_cs *dest_cs[3] = {0};
1487 bool add_tess_rings = false, add_sample_positions = false;
1488 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1489 unsigned max_offchip_buffers;
1490 unsigned hs_offchip_param = 0;
1491 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
1492 if (!queue->has_tess_rings) {
1493 if (needs_tess_rings)
1494 add_tess_rings = true;
1495 }
1496 if (!queue->has_sample_positions) {
1497 if (needs_sample_positions)
1498 add_sample_positions = true;
1499 }
1500 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1501 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1502 &max_offchip_buffers);
1503 tess_offchip_ring_size = max_offchip_buffers *
1504 queue->device->tess_offchip_block_dw_size * 4;
1505
1506 if (scratch_size <= queue->scratch_size &&
1507 compute_scratch_size <= queue->compute_scratch_size &&
1508 esgs_ring_size <= queue->esgs_ring_size &&
1509 gsvs_ring_size <= queue->gsvs_ring_size &&
1510 !add_tess_rings && !add_sample_positions &&
1511 queue->initial_preamble_cs) {
1512 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1513 *initial_preamble_cs = queue->initial_preamble_cs;
1514 *continue_preamble_cs = queue->continue_preamble_cs;
1515 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1516 *continue_preamble_cs = NULL;
1517 return VK_SUCCESS;
1518 }
1519
1520 if (scratch_size > queue->scratch_size) {
1521 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1522 scratch_size,
1523 4096,
1524 RADEON_DOMAIN_VRAM,
1525 ring_bo_flags);
1526 if (!scratch_bo)
1527 goto fail;
1528 } else
1529 scratch_bo = queue->scratch_bo;
1530
1531 if (compute_scratch_size > queue->compute_scratch_size) {
1532 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1533 compute_scratch_size,
1534 4096,
1535 RADEON_DOMAIN_VRAM,
1536 ring_bo_flags);
1537 if (!compute_scratch_bo)
1538 goto fail;
1539
1540 } else
1541 compute_scratch_bo = queue->compute_scratch_bo;
1542
1543 if (esgs_ring_size > queue->esgs_ring_size) {
1544 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1545 esgs_ring_size,
1546 4096,
1547 RADEON_DOMAIN_VRAM,
1548 ring_bo_flags);
1549 if (!esgs_ring_bo)
1550 goto fail;
1551 } else {
1552 esgs_ring_bo = queue->esgs_ring_bo;
1553 esgs_ring_size = queue->esgs_ring_size;
1554 }
1555
1556 if (gsvs_ring_size > queue->gsvs_ring_size) {
1557 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1558 gsvs_ring_size,
1559 4096,
1560 RADEON_DOMAIN_VRAM,
1561 ring_bo_flags);
1562 if (!gsvs_ring_bo)
1563 goto fail;
1564 } else {
1565 gsvs_ring_bo = queue->gsvs_ring_bo;
1566 gsvs_ring_size = queue->gsvs_ring_size;
1567 }
1568
1569 if (add_tess_rings) {
1570 tess_factor_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1571 tess_factor_ring_size,
1572 256,
1573 RADEON_DOMAIN_VRAM,
1574 ring_bo_flags);
1575 if (!tess_factor_ring_bo)
1576 goto fail;
1577 tess_offchip_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1578 tess_offchip_ring_size,
1579 256,
1580 RADEON_DOMAIN_VRAM,
1581 ring_bo_flags);
1582 if (!tess_offchip_ring_bo)
1583 goto fail;
1584 } else {
1585 tess_factor_ring_bo = queue->tess_factor_ring_bo;
1586 tess_offchip_ring_bo = queue->tess_offchip_ring_bo;
1587 }
1588
1589 if (scratch_bo != queue->scratch_bo ||
1590 esgs_ring_bo != queue->esgs_ring_bo ||
1591 gsvs_ring_bo != queue->gsvs_ring_bo ||
1592 tess_factor_ring_bo != queue->tess_factor_ring_bo ||
1593 tess_offchip_ring_bo != queue->tess_offchip_ring_bo || add_sample_positions) {
1594 uint32_t size = 0;
1595 if (gsvs_ring_bo || esgs_ring_bo ||
1596 tess_factor_ring_bo || tess_offchip_ring_bo || add_sample_positions) {
1597 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
1598 if (add_sample_positions)
1599 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1600 }
1601 else if (scratch_bo)
1602 size = 8; /* 2 dword */
1603
1604 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1605 size,
1606 4096,
1607 RADEON_DOMAIN_VRAM,
1608 RADEON_FLAG_CPU_ACCESS |
1609 RADEON_FLAG_NO_INTERPROCESS_SHARING |
1610 RADEON_FLAG_READ_ONLY);
1611 if (!descriptor_bo)
1612 goto fail;
1613 } else
1614 descriptor_bo = queue->descriptor_bo;
1615
1616 for(int i = 0; i < 3; ++i) {
1617 struct radeon_winsys_cs *cs = NULL;
1618 cs = queue->device->ws->cs_create(queue->device->ws,
1619 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1620 if (!cs)
1621 goto fail;
1622
1623 dest_cs[i] = cs;
1624
1625 if (scratch_bo)
1626 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo, 8);
1627
1628 if (esgs_ring_bo)
1629 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo, 8);
1630
1631 if (gsvs_ring_bo)
1632 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo, 8);
1633
1634 if (tess_factor_ring_bo)
1635 radv_cs_add_buffer(queue->device->ws, cs, tess_factor_ring_bo, 8);
1636
1637 if (tess_offchip_ring_bo)
1638 radv_cs_add_buffer(queue->device->ws, cs, tess_offchip_ring_bo, 8);
1639
1640 if (descriptor_bo)
1641 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo, 8);
1642
1643 if (descriptor_bo != queue->descriptor_bo) {
1644 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1645
1646 if (scratch_bo) {
1647 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
1648 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1649 S_008F04_SWIZZLE_ENABLE(1);
1650 map[0] = scratch_va;
1651 map[1] = rsrc1;
1652 }
1653
1654 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo ||
1655 add_sample_positions)
1656 fill_geom_tess_rings(queue, map, add_sample_positions,
1657 esgs_ring_size, esgs_ring_bo,
1658 gsvs_ring_size, gsvs_ring_bo,
1659 tess_factor_ring_size, tess_factor_ring_bo,
1660 tess_offchip_ring_size, tess_offchip_ring_bo);
1661
1662 queue->device->ws->buffer_unmap(descriptor_bo);
1663 }
1664
1665 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo) {
1666 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1667 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1668 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1669 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1670 }
1671
1672 if (esgs_ring_bo || gsvs_ring_bo) {
1673 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1674 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1675 radeon_emit(cs, esgs_ring_size >> 8);
1676 radeon_emit(cs, gsvs_ring_size >> 8);
1677 } else {
1678 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1679 radeon_emit(cs, esgs_ring_size >> 8);
1680 radeon_emit(cs, gsvs_ring_size >> 8);
1681 }
1682 }
1683
1684 if (tess_factor_ring_bo) {
1685 uint64_t tf_va = radv_buffer_get_va(tess_factor_ring_bo);
1686 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1687 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1688 S_030938_SIZE(tess_factor_ring_size / 4));
1689 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1690 tf_va >> 8);
1691 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1692 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1693 tf_va >> 40);
1694 }
1695 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
1696 } else {
1697 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1698 S_008988_SIZE(tess_factor_ring_size / 4));
1699 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1700 tf_va >> 8);
1701 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1702 hs_offchip_param);
1703 }
1704 }
1705
1706 if (descriptor_bo) {
1707 uint64_t va = radv_buffer_get_va(descriptor_bo);
1708 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1709 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1710 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1711 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
1712 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
1713
1714 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1715 radeon_set_sh_reg_seq(cs, regs[i], 2);
1716 radeon_emit(cs, va);
1717 radeon_emit(cs, va >> 32);
1718 }
1719 } else {
1720 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1721 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1722 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1723 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1724 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1725 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1726
1727 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1728 radeon_set_sh_reg_seq(cs, regs[i], 2);
1729 radeon_emit(cs, va);
1730 radeon_emit(cs, va >> 32);
1731 }
1732 }
1733 }
1734
1735 if (compute_scratch_bo) {
1736 uint64_t scratch_va = radv_buffer_get_va(compute_scratch_bo);
1737 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1738 S_008F04_SWIZZLE_ENABLE(1);
1739
1740 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo, 8);
1741
1742 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1743 radeon_emit(cs, scratch_va);
1744 radeon_emit(cs, rsrc1);
1745 }
1746
1747 if (i == 0) {
1748 si_cs_emit_cache_flush(cs,
1749 false,
1750 queue->device->physical_device->rad_info.chip_class,
1751 NULL, 0,
1752 queue->queue_family_index == RING_COMPUTE &&
1753 queue->device->physical_device->rad_info.chip_class >= CIK,
1754 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
1755 RADV_CMD_FLAG_INV_ICACHE |
1756 RADV_CMD_FLAG_INV_SMEM_L1 |
1757 RADV_CMD_FLAG_INV_VMEM_L1 |
1758 RADV_CMD_FLAG_INV_GLOBAL_L2);
1759 } else if (i == 1) {
1760 si_cs_emit_cache_flush(cs,
1761 false,
1762 queue->device->physical_device->rad_info.chip_class,
1763 NULL, 0,
1764 queue->queue_family_index == RING_COMPUTE &&
1765 queue->device->physical_device->rad_info.chip_class >= CIK,
1766 RADV_CMD_FLAG_INV_ICACHE |
1767 RADV_CMD_FLAG_INV_SMEM_L1 |
1768 RADV_CMD_FLAG_INV_VMEM_L1 |
1769 RADV_CMD_FLAG_INV_GLOBAL_L2);
1770 }
1771
1772 if (!queue->device->ws->cs_finalize(cs))
1773 goto fail;
1774 }
1775
1776 if (queue->initial_full_flush_preamble_cs)
1777 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1778
1779 if (queue->initial_preamble_cs)
1780 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1781
1782 if (queue->continue_preamble_cs)
1783 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1784
1785 queue->initial_full_flush_preamble_cs = dest_cs[0];
1786 queue->initial_preamble_cs = dest_cs[1];
1787 queue->continue_preamble_cs = dest_cs[2];
1788
1789 if (scratch_bo != queue->scratch_bo) {
1790 if (queue->scratch_bo)
1791 queue->device->ws->buffer_destroy(queue->scratch_bo);
1792 queue->scratch_bo = scratch_bo;
1793 queue->scratch_size = scratch_size;
1794 }
1795
1796 if (compute_scratch_bo != queue->compute_scratch_bo) {
1797 if (queue->compute_scratch_bo)
1798 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1799 queue->compute_scratch_bo = compute_scratch_bo;
1800 queue->compute_scratch_size = compute_scratch_size;
1801 }
1802
1803 if (esgs_ring_bo != queue->esgs_ring_bo) {
1804 if (queue->esgs_ring_bo)
1805 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1806 queue->esgs_ring_bo = esgs_ring_bo;
1807 queue->esgs_ring_size = esgs_ring_size;
1808 }
1809
1810 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
1811 if (queue->gsvs_ring_bo)
1812 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1813 queue->gsvs_ring_bo = gsvs_ring_bo;
1814 queue->gsvs_ring_size = gsvs_ring_size;
1815 }
1816
1817 if (tess_factor_ring_bo != queue->tess_factor_ring_bo) {
1818 queue->tess_factor_ring_bo = tess_factor_ring_bo;
1819 }
1820
1821 if (tess_offchip_ring_bo != queue->tess_offchip_ring_bo) {
1822 queue->tess_offchip_ring_bo = tess_offchip_ring_bo;
1823 queue->has_tess_rings = true;
1824 }
1825
1826 if (descriptor_bo != queue->descriptor_bo) {
1827 if (queue->descriptor_bo)
1828 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1829
1830 queue->descriptor_bo = descriptor_bo;
1831 }
1832
1833 if (add_sample_positions)
1834 queue->has_sample_positions = true;
1835
1836 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1837 *initial_preamble_cs = queue->initial_preamble_cs;
1838 *continue_preamble_cs = queue->continue_preamble_cs;
1839 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1840 *continue_preamble_cs = NULL;
1841 return VK_SUCCESS;
1842 fail:
1843 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
1844 if (dest_cs[i])
1845 queue->device->ws->cs_destroy(dest_cs[i]);
1846 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
1847 queue->device->ws->buffer_destroy(descriptor_bo);
1848 if (scratch_bo && scratch_bo != queue->scratch_bo)
1849 queue->device->ws->buffer_destroy(scratch_bo);
1850 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
1851 queue->device->ws->buffer_destroy(compute_scratch_bo);
1852 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
1853 queue->device->ws->buffer_destroy(esgs_ring_bo);
1854 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
1855 queue->device->ws->buffer_destroy(gsvs_ring_bo);
1856 if (tess_factor_ring_bo && tess_factor_ring_bo != queue->tess_factor_ring_bo)
1857 queue->device->ws->buffer_destroy(tess_factor_ring_bo);
1858 if (tess_offchip_ring_bo && tess_offchip_ring_bo != queue->tess_offchip_ring_bo)
1859 queue->device->ws->buffer_destroy(tess_offchip_ring_bo);
1860 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
1861 }
1862
1863 static VkResult radv_alloc_sem_counts(struct radv_winsys_sem_counts *counts,
1864 int num_sems,
1865 const VkSemaphore *sems,
1866 VkFence _fence,
1867 bool reset_temp)
1868 {
1869 int syncobj_idx = 0, sem_idx = 0;
1870
1871 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
1872 return VK_SUCCESS;
1873
1874 for (uint32_t i = 0; i < num_sems; i++) {
1875 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1876
1877 if (sem->temp_syncobj || sem->syncobj)
1878 counts->syncobj_count++;
1879 else
1880 counts->sem_count++;
1881 }
1882
1883 if (_fence != VK_NULL_HANDLE) {
1884 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1885 if (fence->temp_syncobj || fence->syncobj)
1886 counts->syncobj_count++;
1887 }
1888
1889 if (counts->syncobj_count) {
1890 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
1891 if (!counts->syncobj)
1892 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1893 }
1894
1895 if (counts->sem_count) {
1896 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
1897 if (!counts->sem) {
1898 free(counts->syncobj);
1899 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1900 }
1901 }
1902
1903 for (uint32_t i = 0; i < num_sems; i++) {
1904 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1905
1906 if (sem->temp_syncobj) {
1907 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
1908 }
1909 else if (sem->syncobj)
1910 counts->syncobj[syncobj_idx++] = sem->syncobj;
1911 else {
1912 assert(sem->sem);
1913 counts->sem[sem_idx++] = sem->sem;
1914 }
1915 }
1916
1917 if (_fence != VK_NULL_HANDLE) {
1918 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1919 if (fence->temp_syncobj)
1920 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
1921 else if (fence->syncobj)
1922 counts->syncobj[syncobj_idx++] = fence->syncobj;
1923 }
1924
1925 return VK_SUCCESS;
1926 }
1927
1928 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
1929 {
1930 free(sem_info->wait.syncobj);
1931 free(sem_info->wait.sem);
1932 free(sem_info->signal.syncobj);
1933 free(sem_info->signal.sem);
1934 }
1935
1936
1937 static void radv_free_temp_syncobjs(struct radv_device *device,
1938 int num_sems,
1939 const VkSemaphore *sems)
1940 {
1941 for (uint32_t i = 0; i < num_sems; i++) {
1942 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1943
1944 if (sem->temp_syncobj) {
1945 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
1946 sem->temp_syncobj = 0;
1947 }
1948 }
1949 }
1950
1951 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1952 int num_wait_sems,
1953 const VkSemaphore *wait_sems,
1954 int num_signal_sems,
1955 const VkSemaphore *signal_sems,
1956 VkFence fence)
1957 {
1958 VkResult ret;
1959 memset(sem_info, 0, sizeof(*sem_info));
1960
1961 ret = radv_alloc_sem_counts(&sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
1962 if (ret)
1963 return ret;
1964 ret = radv_alloc_sem_counts(&sem_info->signal, num_signal_sems, signal_sems, fence, false);
1965 if (ret)
1966 radv_free_sem_info(sem_info);
1967
1968 /* caller can override these */
1969 sem_info->cs_emit_wait = true;
1970 sem_info->cs_emit_signal = true;
1971 return ret;
1972 }
1973
1974 VkResult radv_QueueSubmit(
1975 VkQueue _queue,
1976 uint32_t submitCount,
1977 const VkSubmitInfo* pSubmits,
1978 VkFence _fence)
1979 {
1980 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1981 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1982 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
1983 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
1984 int ret;
1985 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
1986 uint32_t scratch_size = 0;
1987 uint32_t compute_scratch_size = 0;
1988 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
1989 struct radeon_winsys_cs *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
1990 VkResult result;
1991 bool fence_emitted = false;
1992 bool tess_rings_needed = false;
1993 bool sample_positions_needed = false;
1994
1995 /* Do this first so failing to allocate scratch buffers can't result in
1996 * partially executed submissions. */
1997 for (uint32_t i = 0; i < submitCount; i++) {
1998 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1999 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2000 pSubmits[i].pCommandBuffers[j]);
2001
2002 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2003 compute_scratch_size = MAX2(compute_scratch_size,
2004 cmd_buffer->compute_scratch_size_needed);
2005 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2006 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2007 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2008 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2009 }
2010 }
2011
2012 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2013 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2014 sample_positions_needed, &initial_flush_preamble_cs,
2015 &initial_preamble_cs, &continue_preamble_cs);
2016 if (result != VK_SUCCESS)
2017 return result;
2018
2019 for (uint32_t i = 0; i < submitCount; i++) {
2020 struct radeon_winsys_cs **cs_array;
2021 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2022 bool can_patch = true;
2023 uint32_t advance;
2024 struct radv_winsys_sem_info sem_info;
2025
2026 result = radv_alloc_sem_info(&sem_info,
2027 pSubmits[i].waitSemaphoreCount,
2028 pSubmits[i].pWaitSemaphores,
2029 pSubmits[i].signalSemaphoreCount,
2030 pSubmits[i].pSignalSemaphores,
2031 _fence);
2032 if (result != VK_SUCCESS)
2033 return result;
2034
2035 if (!pSubmits[i].commandBufferCount) {
2036 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2037 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2038 &queue->device->empty_cs[queue->queue_family_index],
2039 1, NULL, NULL,
2040 &sem_info,
2041 false, base_fence);
2042 if (ret) {
2043 radv_loge("failed to submit CS %d\n", i);
2044 abort();
2045 }
2046 fence_emitted = true;
2047 }
2048 radv_free_sem_info(&sem_info);
2049 continue;
2050 }
2051
2052 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
2053 (pSubmits[i].commandBufferCount));
2054
2055 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2056 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2057 pSubmits[i].pCommandBuffers[j]);
2058 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2059
2060 cs_array[j] = cmd_buffer->cs;
2061 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2062 can_patch = false;
2063
2064 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2065 }
2066
2067 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2068 struct radeon_winsys_cs *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2069 advance = MIN2(max_cs_submission,
2070 pSubmits[i].commandBufferCount - j);
2071
2072 if (queue->device->trace_bo)
2073 *queue->device->trace_id_ptr = 0;
2074
2075 sem_info.cs_emit_wait = j == 0;
2076 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2077
2078 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2079 advance, initial_preamble, continue_preamble_cs,
2080 &sem_info,
2081 can_patch, base_fence);
2082
2083 if (ret) {
2084 radv_loge("failed to submit CS %d\n", i);
2085 abort();
2086 }
2087 fence_emitted = true;
2088 if (queue->device->trace_bo) {
2089 radv_check_gpu_hangs(queue, cs_array[j]);
2090 }
2091 }
2092
2093 radv_free_temp_syncobjs(queue->device,
2094 pSubmits[i].waitSemaphoreCount,
2095 pSubmits[i].pWaitSemaphores);
2096 radv_free_sem_info(&sem_info);
2097 free(cs_array);
2098 }
2099
2100 if (fence) {
2101 if (!fence_emitted) {
2102 struct radv_winsys_sem_info sem_info;
2103
2104 result = radv_alloc_sem_info(&sem_info, 0, NULL, 0, NULL,
2105 _fence);
2106 if (result != VK_SUCCESS)
2107 return result;
2108
2109 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2110 &queue->device->empty_cs[queue->queue_family_index],
2111 1, NULL, NULL, &sem_info,
2112 false, base_fence);
2113 radv_free_sem_info(&sem_info);
2114 }
2115 fence->submitted = true;
2116 }
2117
2118 return VK_SUCCESS;
2119 }
2120
2121 VkResult radv_QueueWaitIdle(
2122 VkQueue _queue)
2123 {
2124 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2125
2126 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2127 radv_queue_family_to_ring(queue->queue_family_index),
2128 queue->queue_idx);
2129 return VK_SUCCESS;
2130 }
2131
2132 VkResult radv_DeviceWaitIdle(
2133 VkDevice _device)
2134 {
2135 RADV_FROM_HANDLE(radv_device, device, _device);
2136
2137 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2138 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2139 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2140 }
2141 }
2142 return VK_SUCCESS;
2143 }
2144
2145 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2146 VkInstance instance,
2147 const char* pName)
2148 {
2149 return radv_lookup_entrypoint(pName);
2150 }
2151
2152 /* The loader wants us to expose a second GetInstanceProcAddr function
2153 * to work around certain LD_PRELOAD issues seen in apps.
2154 */
2155 PUBLIC
2156 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2157 VkInstance instance,
2158 const char* pName);
2159
2160 PUBLIC
2161 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2162 VkInstance instance,
2163 const char* pName)
2164 {
2165 return radv_GetInstanceProcAddr(instance, pName);
2166 }
2167
2168 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2169 VkDevice device,
2170 const char* pName)
2171 {
2172 return radv_lookup_entrypoint(pName);
2173 }
2174
2175 bool radv_get_memory_fd(struct radv_device *device,
2176 struct radv_device_memory *memory,
2177 int *pFD)
2178 {
2179 struct radeon_bo_metadata metadata;
2180
2181 if (memory->image) {
2182 radv_init_metadata(device, memory->image, &metadata);
2183 device->ws->buffer_set_metadata(memory->bo, &metadata);
2184 }
2185
2186 return device->ws->buffer_get_fd(device->ws, memory->bo,
2187 pFD);
2188 }
2189
2190 static VkResult radv_alloc_memory(struct radv_device *device,
2191 const VkMemoryAllocateInfo* pAllocateInfo,
2192 const VkAllocationCallbacks* pAllocator,
2193 VkDeviceMemory* pMem)
2194 {
2195 struct radv_device_memory *mem;
2196 VkResult result;
2197 enum radeon_bo_domain domain;
2198 uint32_t flags = 0;
2199 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
2200
2201 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2202
2203 if (pAllocateInfo->allocationSize == 0) {
2204 /* Apparently, this is allowed */
2205 *pMem = VK_NULL_HANDLE;
2206 return VK_SUCCESS;
2207 }
2208
2209 const VkImportMemoryFdInfoKHR *import_info =
2210 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2211 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2212 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2213 const VkExportMemoryAllocateInfoKHR *export_info =
2214 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO_KHR);
2215
2216 const struct wsi_memory_allocate_info *wsi_info =
2217 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
2218
2219 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2220 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2221 if (mem == NULL)
2222 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2223
2224 if (wsi_info && wsi_info->implicit_sync)
2225 flags |= RADEON_FLAG_IMPLICIT_SYNC;
2226
2227 if (dedicate_info) {
2228 mem->image = radv_image_from_handle(dedicate_info->image);
2229 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2230 } else {
2231 mem->image = NULL;
2232 mem->buffer = NULL;
2233 }
2234
2235 if (import_info) {
2236 assert(import_info->handleType ==
2237 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
2238 import_info->handleType ==
2239 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
2240 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2241 NULL, NULL);
2242 if (!mem->bo) {
2243 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2244 goto fail;
2245 } else {
2246 close(import_info->fd);
2247 goto out_success;
2248 }
2249 }
2250
2251 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2252 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2253 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
2254 domain = RADEON_DOMAIN_GTT;
2255 else
2256 domain = RADEON_DOMAIN_VRAM;
2257
2258 if (mem_type_index == RADV_MEM_TYPE_VRAM)
2259 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2260 else
2261 flags |= RADEON_FLAG_CPU_ACCESS;
2262
2263 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2264 flags |= RADEON_FLAG_GTT_WC;
2265
2266 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
2267 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
2268
2269 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2270 domain, flags);
2271
2272 if (!mem->bo) {
2273 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2274 goto fail;
2275 }
2276 mem->type_index = mem_type_index;
2277 out_success:
2278 *pMem = radv_device_memory_to_handle(mem);
2279
2280 return VK_SUCCESS;
2281
2282 fail:
2283 vk_free2(&device->alloc, pAllocator, mem);
2284
2285 return result;
2286 }
2287
2288 VkResult radv_AllocateMemory(
2289 VkDevice _device,
2290 const VkMemoryAllocateInfo* pAllocateInfo,
2291 const VkAllocationCallbacks* pAllocator,
2292 VkDeviceMemory* pMem)
2293 {
2294 RADV_FROM_HANDLE(radv_device, device, _device);
2295 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
2296 }
2297
2298 void radv_FreeMemory(
2299 VkDevice _device,
2300 VkDeviceMemory _mem,
2301 const VkAllocationCallbacks* pAllocator)
2302 {
2303 RADV_FROM_HANDLE(radv_device, device, _device);
2304 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2305
2306 if (mem == NULL)
2307 return;
2308
2309 device->ws->buffer_destroy(mem->bo);
2310 mem->bo = NULL;
2311
2312 vk_free2(&device->alloc, pAllocator, mem);
2313 }
2314
2315 VkResult radv_MapMemory(
2316 VkDevice _device,
2317 VkDeviceMemory _memory,
2318 VkDeviceSize offset,
2319 VkDeviceSize size,
2320 VkMemoryMapFlags flags,
2321 void** ppData)
2322 {
2323 RADV_FROM_HANDLE(radv_device, device, _device);
2324 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2325
2326 if (mem == NULL) {
2327 *ppData = NULL;
2328 return VK_SUCCESS;
2329 }
2330
2331 *ppData = device->ws->buffer_map(mem->bo);
2332 if (*ppData) {
2333 *ppData += offset;
2334 return VK_SUCCESS;
2335 }
2336
2337 return vk_error(VK_ERROR_MEMORY_MAP_FAILED);
2338 }
2339
2340 void radv_UnmapMemory(
2341 VkDevice _device,
2342 VkDeviceMemory _memory)
2343 {
2344 RADV_FROM_HANDLE(radv_device, device, _device);
2345 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2346
2347 if (mem == NULL)
2348 return;
2349
2350 device->ws->buffer_unmap(mem->bo);
2351 }
2352
2353 VkResult radv_FlushMappedMemoryRanges(
2354 VkDevice _device,
2355 uint32_t memoryRangeCount,
2356 const VkMappedMemoryRange* pMemoryRanges)
2357 {
2358 return VK_SUCCESS;
2359 }
2360
2361 VkResult radv_InvalidateMappedMemoryRanges(
2362 VkDevice _device,
2363 uint32_t memoryRangeCount,
2364 const VkMappedMemoryRange* pMemoryRanges)
2365 {
2366 return VK_SUCCESS;
2367 }
2368
2369 void radv_GetBufferMemoryRequirements(
2370 VkDevice _device,
2371 VkBuffer _buffer,
2372 VkMemoryRequirements* pMemoryRequirements)
2373 {
2374 RADV_FROM_HANDLE(radv_device, device, _device);
2375 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2376
2377 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2378
2379 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2380 pMemoryRequirements->alignment = 4096;
2381 else
2382 pMemoryRequirements->alignment = 16;
2383
2384 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2385 }
2386
2387 void radv_GetBufferMemoryRequirements2KHR(
2388 VkDevice device,
2389 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2390 VkMemoryRequirements2KHR* pMemoryRequirements)
2391 {
2392 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2393 &pMemoryRequirements->memoryRequirements);
2394 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
2395 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2396 switch (ext->sType) {
2397 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2398 VkMemoryDedicatedRequirementsKHR *req =
2399 (VkMemoryDedicatedRequirementsKHR *) ext;
2400 req->requiresDedicatedAllocation = buffer->shareable;
2401 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2402 break;
2403 }
2404 default:
2405 break;
2406 }
2407 }
2408 }
2409
2410 void radv_GetImageMemoryRequirements(
2411 VkDevice _device,
2412 VkImage _image,
2413 VkMemoryRequirements* pMemoryRequirements)
2414 {
2415 RADV_FROM_HANDLE(radv_device, device, _device);
2416 RADV_FROM_HANDLE(radv_image, image, _image);
2417
2418 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2419
2420 pMemoryRequirements->size = image->size;
2421 pMemoryRequirements->alignment = image->alignment;
2422 }
2423
2424 void radv_GetImageMemoryRequirements2KHR(
2425 VkDevice device,
2426 const VkImageMemoryRequirementsInfo2KHR* pInfo,
2427 VkMemoryRequirements2KHR* pMemoryRequirements)
2428 {
2429 radv_GetImageMemoryRequirements(device, pInfo->image,
2430 &pMemoryRequirements->memoryRequirements);
2431
2432 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
2433
2434 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2435 switch (ext->sType) {
2436 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2437 VkMemoryDedicatedRequirementsKHR *req =
2438 (VkMemoryDedicatedRequirementsKHR *) ext;
2439 req->requiresDedicatedAllocation = image->shareable;
2440 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2441 break;
2442 }
2443 default:
2444 break;
2445 }
2446 }
2447 }
2448
2449 void radv_GetImageSparseMemoryRequirements(
2450 VkDevice device,
2451 VkImage image,
2452 uint32_t* pSparseMemoryRequirementCount,
2453 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2454 {
2455 stub();
2456 }
2457
2458 void radv_GetImageSparseMemoryRequirements2KHR(
2459 VkDevice device,
2460 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
2461 uint32_t* pSparseMemoryRequirementCount,
2462 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
2463 {
2464 stub();
2465 }
2466
2467 void radv_GetDeviceMemoryCommitment(
2468 VkDevice device,
2469 VkDeviceMemory memory,
2470 VkDeviceSize* pCommittedMemoryInBytes)
2471 {
2472 *pCommittedMemoryInBytes = 0;
2473 }
2474
2475 VkResult radv_BindBufferMemory2KHR(VkDevice device,
2476 uint32_t bindInfoCount,
2477 const VkBindBufferMemoryInfoKHR *pBindInfos)
2478 {
2479 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2480 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2481 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
2482
2483 if (mem) {
2484 buffer->bo = mem->bo;
2485 buffer->offset = pBindInfos[i].memoryOffset;
2486 } else {
2487 buffer->bo = NULL;
2488 }
2489 }
2490 return VK_SUCCESS;
2491 }
2492
2493 VkResult radv_BindBufferMemory(
2494 VkDevice device,
2495 VkBuffer buffer,
2496 VkDeviceMemory memory,
2497 VkDeviceSize memoryOffset)
2498 {
2499 const VkBindBufferMemoryInfoKHR info = {
2500 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2501 .buffer = buffer,
2502 .memory = memory,
2503 .memoryOffset = memoryOffset
2504 };
2505
2506 return radv_BindBufferMemory2KHR(device, 1, &info);
2507 }
2508
2509 VkResult radv_BindImageMemory2KHR(VkDevice device,
2510 uint32_t bindInfoCount,
2511 const VkBindImageMemoryInfoKHR *pBindInfos)
2512 {
2513 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2514 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2515 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
2516
2517 if (mem) {
2518 image->bo = mem->bo;
2519 image->offset = pBindInfos[i].memoryOffset;
2520 } else {
2521 image->bo = NULL;
2522 image->offset = 0;
2523 }
2524 }
2525 return VK_SUCCESS;
2526 }
2527
2528
2529 VkResult radv_BindImageMemory(
2530 VkDevice device,
2531 VkImage image,
2532 VkDeviceMemory memory,
2533 VkDeviceSize memoryOffset)
2534 {
2535 const VkBindImageMemoryInfoKHR info = {
2536 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2537 .image = image,
2538 .memory = memory,
2539 .memoryOffset = memoryOffset
2540 };
2541
2542 return radv_BindImageMemory2KHR(device, 1, &info);
2543 }
2544
2545
2546 static void
2547 radv_sparse_buffer_bind_memory(struct radv_device *device,
2548 const VkSparseBufferMemoryBindInfo *bind)
2549 {
2550 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
2551
2552 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2553 struct radv_device_memory *mem = NULL;
2554
2555 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2556 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2557
2558 device->ws->buffer_virtual_bind(buffer->bo,
2559 bind->pBinds[i].resourceOffset,
2560 bind->pBinds[i].size,
2561 mem ? mem->bo : NULL,
2562 bind->pBinds[i].memoryOffset);
2563 }
2564 }
2565
2566 static void
2567 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
2568 const VkSparseImageOpaqueMemoryBindInfo *bind)
2569 {
2570 RADV_FROM_HANDLE(radv_image, image, bind->image);
2571
2572 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2573 struct radv_device_memory *mem = NULL;
2574
2575 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2576 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2577
2578 device->ws->buffer_virtual_bind(image->bo,
2579 bind->pBinds[i].resourceOffset,
2580 bind->pBinds[i].size,
2581 mem ? mem->bo : NULL,
2582 bind->pBinds[i].memoryOffset);
2583 }
2584 }
2585
2586 VkResult radv_QueueBindSparse(
2587 VkQueue _queue,
2588 uint32_t bindInfoCount,
2589 const VkBindSparseInfo* pBindInfo,
2590 VkFence _fence)
2591 {
2592 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2593 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2594 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2595 bool fence_emitted = false;
2596
2597 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2598 struct radv_winsys_sem_info sem_info;
2599 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
2600 radv_sparse_buffer_bind_memory(queue->device,
2601 pBindInfo[i].pBufferBinds + j);
2602 }
2603
2604 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
2605 radv_sparse_image_opaque_bind_memory(queue->device,
2606 pBindInfo[i].pImageOpaqueBinds + j);
2607 }
2608
2609 VkResult result;
2610 result = radv_alloc_sem_info(&sem_info,
2611 pBindInfo[i].waitSemaphoreCount,
2612 pBindInfo[i].pWaitSemaphores,
2613 pBindInfo[i].signalSemaphoreCount,
2614 pBindInfo[i].pSignalSemaphores,
2615 _fence);
2616 if (result != VK_SUCCESS)
2617 return result;
2618
2619 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
2620 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2621 &queue->device->empty_cs[queue->queue_family_index],
2622 1, NULL, NULL,
2623 &sem_info,
2624 false, base_fence);
2625 fence_emitted = true;
2626 if (fence)
2627 fence->submitted = true;
2628 }
2629
2630 radv_free_sem_info(&sem_info);
2631
2632 }
2633
2634 if (fence && !fence_emitted) {
2635 fence->signalled = true;
2636 }
2637
2638 return VK_SUCCESS;
2639 }
2640
2641 VkResult radv_CreateFence(
2642 VkDevice _device,
2643 const VkFenceCreateInfo* pCreateInfo,
2644 const VkAllocationCallbacks* pAllocator,
2645 VkFence* pFence)
2646 {
2647 RADV_FROM_HANDLE(radv_device, device, _device);
2648 const VkExportFenceCreateInfoKHR *export =
2649 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO_KHR);
2650 VkExternalFenceHandleTypeFlagsKHR handleTypes =
2651 export ? export->handleTypes : 0;
2652
2653 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
2654 sizeof(*fence), 8,
2655 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2656
2657 if (!fence)
2658 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2659
2660 fence->submitted = false;
2661 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
2662 fence->temp_syncobj = 0;
2663 if (handleTypes) {
2664 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
2665 if (ret) {
2666 vk_free2(&device->alloc, pAllocator, fence);
2667 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2668 }
2669 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
2670 device->ws->signal_syncobj(device->ws, fence->syncobj);
2671 }
2672 fence->fence = NULL;
2673 } else {
2674 fence->fence = device->ws->create_fence();
2675 if (!fence->fence) {
2676 vk_free2(&device->alloc, pAllocator, fence);
2677 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2678 }
2679 fence->syncobj = 0;
2680 }
2681
2682 *pFence = radv_fence_to_handle(fence);
2683
2684 return VK_SUCCESS;
2685 }
2686
2687 void radv_DestroyFence(
2688 VkDevice _device,
2689 VkFence _fence,
2690 const VkAllocationCallbacks* pAllocator)
2691 {
2692 RADV_FROM_HANDLE(radv_device, device, _device);
2693 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2694
2695 if (!fence)
2696 return;
2697
2698 if (fence->temp_syncobj)
2699 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
2700 if (fence->syncobj)
2701 device->ws->destroy_syncobj(device->ws, fence->syncobj);
2702 if (fence->fence)
2703 device->ws->destroy_fence(fence->fence);
2704 vk_free2(&device->alloc, pAllocator, fence);
2705 }
2706
2707 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
2708 {
2709 uint64_t current_time;
2710 struct timespec tv;
2711
2712 clock_gettime(CLOCK_MONOTONIC, &tv);
2713 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
2714
2715 timeout = MIN2(UINT64_MAX - current_time, timeout);
2716
2717 return current_time + timeout;
2718 }
2719
2720 VkResult radv_WaitForFences(
2721 VkDevice _device,
2722 uint32_t fenceCount,
2723 const VkFence* pFences,
2724 VkBool32 waitAll,
2725 uint64_t timeout)
2726 {
2727 RADV_FROM_HANDLE(radv_device, device, _device);
2728 timeout = radv_get_absolute_timeout(timeout);
2729
2730 if (!waitAll && fenceCount > 1) {
2731 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
2732 }
2733
2734 for (uint32_t i = 0; i < fenceCount; ++i) {
2735 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2736 bool expired = false;
2737
2738 if (fence->temp_syncobj) {
2739 if (!device->ws->wait_syncobj(device->ws, fence->temp_syncobj, timeout))
2740 return VK_TIMEOUT;
2741 continue;
2742 }
2743
2744 if (fence->syncobj) {
2745 if (!device->ws->wait_syncobj(device->ws, fence->syncobj, timeout))
2746 return VK_TIMEOUT;
2747 continue;
2748 }
2749
2750 if (fence->signalled)
2751 continue;
2752
2753 if (!fence->submitted)
2754 return VK_TIMEOUT;
2755
2756 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
2757 if (!expired)
2758 return VK_TIMEOUT;
2759
2760 fence->signalled = true;
2761 }
2762
2763 return VK_SUCCESS;
2764 }
2765
2766 VkResult radv_ResetFences(VkDevice _device,
2767 uint32_t fenceCount,
2768 const VkFence *pFences)
2769 {
2770 RADV_FROM_HANDLE(radv_device, device, _device);
2771
2772 for (unsigned i = 0; i < fenceCount; ++i) {
2773 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2774 fence->submitted = fence->signalled = false;
2775
2776 /* Per spec, we first restore the permanent payload, and then reset, so
2777 * having a temp syncobj should not skip resetting the permanent syncobj. */
2778 if (fence->temp_syncobj) {
2779 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
2780 fence->temp_syncobj = 0;
2781 }
2782
2783 if (fence->syncobj) {
2784 device->ws->reset_syncobj(device->ws, fence->syncobj);
2785 }
2786 }
2787
2788 return VK_SUCCESS;
2789 }
2790
2791 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
2792 {
2793 RADV_FROM_HANDLE(radv_device, device, _device);
2794 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2795
2796 if (fence->temp_syncobj) {
2797 bool success = device->ws->wait_syncobj(device->ws, fence->temp_syncobj, 0);
2798 return success ? VK_SUCCESS : VK_NOT_READY;
2799 }
2800
2801 if (fence->syncobj) {
2802 bool success = device->ws->wait_syncobj(device->ws, fence->syncobj, 0);
2803 return success ? VK_SUCCESS : VK_NOT_READY;
2804 }
2805
2806 if (fence->signalled)
2807 return VK_SUCCESS;
2808 if (!fence->submitted)
2809 return VK_NOT_READY;
2810 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
2811 return VK_NOT_READY;
2812
2813 return VK_SUCCESS;
2814 }
2815
2816
2817 // Queue semaphore functions
2818
2819 VkResult radv_CreateSemaphore(
2820 VkDevice _device,
2821 const VkSemaphoreCreateInfo* pCreateInfo,
2822 const VkAllocationCallbacks* pAllocator,
2823 VkSemaphore* pSemaphore)
2824 {
2825 RADV_FROM_HANDLE(radv_device, device, _device);
2826 const VkExportSemaphoreCreateInfoKHR *export =
2827 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
2828 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
2829 export ? export->handleTypes : 0;
2830
2831 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
2832 sizeof(*sem), 8,
2833 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2834 if (!sem)
2835 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2836
2837 sem->temp_syncobj = 0;
2838 /* create a syncobject if we are going to export this semaphore */
2839 if (handleTypes) {
2840 assert (device->physical_device->rad_info.has_syncobj);
2841 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
2842 if (ret) {
2843 vk_free2(&device->alloc, pAllocator, sem);
2844 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2845 }
2846 sem->sem = NULL;
2847 } else {
2848 sem->sem = device->ws->create_sem(device->ws);
2849 if (!sem->sem) {
2850 vk_free2(&device->alloc, pAllocator, sem);
2851 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2852 }
2853 sem->syncobj = 0;
2854 }
2855
2856 *pSemaphore = radv_semaphore_to_handle(sem);
2857 return VK_SUCCESS;
2858 }
2859
2860 void radv_DestroySemaphore(
2861 VkDevice _device,
2862 VkSemaphore _semaphore,
2863 const VkAllocationCallbacks* pAllocator)
2864 {
2865 RADV_FROM_HANDLE(radv_device, device, _device);
2866 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
2867 if (!_semaphore)
2868 return;
2869
2870 if (sem->syncobj)
2871 device->ws->destroy_syncobj(device->ws, sem->syncobj);
2872 else
2873 device->ws->destroy_sem(sem->sem);
2874 vk_free2(&device->alloc, pAllocator, sem);
2875 }
2876
2877 VkResult radv_CreateEvent(
2878 VkDevice _device,
2879 const VkEventCreateInfo* pCreateInfo,
2880 const VkAllocationCallbacks* pAllocator,
2881 VkEvent* pEvent)
2882 {
2883 RADV_FROM_HANDLE(radv_device, device, _device);
2884 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
2885 sizeof(*event), 8,
2886 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2887
2888 if (!event)
2889 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2890
2891 event->bo = device->ws->buffer_create(device->ws, 8, 8,
2892 RADEON_DOMAIN_GTT,
2893 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
2894 if (!event->bo) {
2895 vk_free2(&device->alloc, pAllocator, event);
2896 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2897 }
2898
2899 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
2900
2901 *pEvent = radv_event_to_handle(event);
2902
2903 return VK_SUCCESS;
2904 }
2905
2906 void radv_DestroyEvent(
2907 VkDevice _device,
2908 VkEvent _event,
2909 const VkAllocationCallbacks* pAllocator)
2910 {
2911 RADV_FROM_HANDLE(radv_device, device, _device);
2912 RADV_FROM_HANDLE(radv_event, event, _event);
2913
2914 if (!event)
2915 return;
2916 device->ws->buffer_destroy(event->bo);
2917 vk_free2(&device->alloc, pAllocator, event);
2918 }
2919
2920 VkResult radv_GetEventStatus(
2921 VkDevice _device,
2922 VkEvent _event)
2923 {
2924 RADV_FROM_HANDLE(radv_event, event, _event);
2925
2926 if (*event->map == 1)
2927 return VK_EVENT_SET;
2928 return VK_EVENT_RESET;
2929 }
2930
2931 VkResult radv_SetEvent(
2932 VkDevice _device,
2933 VkEvent _event)
2934 {
2935 RADV_FROM_HANDLE(radv_event, event, _event);
2936 *event->map = 1;
2937
2938 return VK_SUCCESS;
2939 }
2940
2941 VkResult radv_ResetEvent(
2942 VkDevice _device,
2943 VkEvent _event)
2944 {
2945 RADV_FROM_HANDLE(radv_event, event, _event);
2946 *event->map = 0;
2947
2948 return VK_SUCCESS;
2949 }
2950
2951 VkResult radv_CreateBuffer(
2952 VkDevice _device,
2953 const VkBufferCreateInfo* pCreateInfo,
2954 const VkAllocationCallbacks* pAllocator,
2955 VkBuffer* pBuffer)
2956 {
2957 RADV_FROM_HANDLE(radv_device, device, _device);
2958 struct radv_buffer *buffer;
2959
2960 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
2961
2962 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
2963 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2964 if (buffer == NULL)
2965 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2966
2967 buffer->size = pCreateInfo->size;
2968 buffer->usage = pCreateInfo->usage;
2969 buffer->bo = NULL;
2970 buffer->offset = 0;
2971 buffer->flags = pCreateInfo->flags;
2972
2973 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
2974 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR) != NULL;
2975
2976 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
2977 buffer->bo = device->ws->buffer_create(device->ws,
2978 align64(buffer->size, 4096),
2979 4096, 0, RADEON_FLAG_VIRTUAL);
2980 if (!buffer->bo) {
2981 vk_free2(&device->alloc, pAllocator, buffer);
2982 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2983 }
2984 }
2985
2986 *pBuffer = radv_buffer_to_handle(buffer);
2987
2988 return VK_SUCCESS;
2989 }
2990
2991 void radv_DestroyBuffer(
2992 VkDevice _device,
2993 VkBuffer _buffer,
2994 const VkAllocationCallbacks* pAllocator)
2995 {
2996 RADV_FROM_HANDLE(radv_device, device, _device);
2997 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2998
2999 if (!buffer)
3000 return;
3001
3002 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3003 device->ws->buffer_destroy(buffer->bo);
3004
3005 vk_free2(&device->alloc, pAllocator, buffer);
3006 }
3007
3008 static inline unsigned
3009 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
3010 {
3011 if (stencil)
3012 return image->surface.u.legacy.stencil_tiling_index[level];
3013 else
3014 return image->surface.u.legacy.tiling_index[level];
3015 }
3016
3017 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
3018 {
3019 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
3020 }
3021
3022 static void
3023 radv_initialise_color_surface(struct radv_device *device,
3024 struct radv_color_buffer_info *cb,
3025 struct radv_image_view *iview)
3026 {
3027 const struct vk_format_description *desc;
3028 unsigned ntype, format, swap, endian;
3029 unsigned blend_clamp = 0, blend_bypass = 0;
3030 uint64_t va;
3031 const struct radeon_surf *surf = &iview->image->surface;
3032
3033 desc = vk_format_description(iview->vk_format);
3034
3035 memset(cb, 0, sizeof(*cb));
3036
3037 /* Intensity is implemented as Red, so treat it that way. */
3038 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
3039
3040 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3041
3042 cb->cb_color_base = va >> 8;
3043
3044 if (device->physical_device->rad_info.chip_class >= GFX9) {
3045 struct gfx9_surf_meta_flags meta;
3046 if (iview->image->dcc_offset)
3047 meta = iview->image->surface.u.gfx9.dcc;
3048 else
3049 meta = iview->image->surface.u.gfx9.cmask;
3050
3051 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3052 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
3053 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3054 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3055
3056 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
3057 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3058 } else {
3059 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
3060 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3061
3062 cb->cb_color_base += level_info->offset >> 8;
3063 if (level_info->mode == RADEON_SURF_MODE_2D)
3064 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3065
3066 pitch_tile_max = level_info->nblk_x / 8 - 1;
3067 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
3068 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
3069
3070 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3071 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3072 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
3073
3074 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3075
3076 if (iview->image->fmask.size) {
3077 if (device->physical_device->rad_info.chip_class >= CIK)
3078 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
3079 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
3080 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
3081 } else {
3082 /* This must be set for fast clear to work without FMASK. */
3083 if (device->physical_device->rad_info.chip_class >= CIK)
3084 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3085 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3086 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3087 }
3088 }
3089
3090 /* CMASK variables */
3091 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3092 va += iview->image->cmask.offset;
3093 cb->cb_color_cmask = va >> 8;
3094
3095 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3096 va += iview->image->dcc_offset;
3097 cb->cb_dcc_base = va >> 8;
3098 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
3099
3100 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3101 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3102 S_028C6C_SLICE_MAX(max_slice);
3103
3104 if (iview->image->info.samples > 1) {
3105 unsigned log_samples = util_logbase2(iview->image->info.samples);
3106
3107 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3108 S_028C74_NUM_FRAGMENTS(log_samples);
3109 }
3110
3111 if (iview->image->fmask.size) {
3112 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3113 cb->cb_color_fmask = va >> 8;
3114 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3115 } else {
3116 cb->cb_color_fmask = cb->cb_color_base;
3117 }
3118
3119 ntype = radv_translate_color_numformat(iview->vk_format,
3120 desc,
3121 vk_format_get_first_non_void_channel(iview->vk_format));
3122 format = radv_translate_colorformat(iview->vk_format);
3123 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3124 radv_finishme("Illegal color\n");
3125 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3126 endian = radv_colorformat_endian_swap(format);
3127
3128 /* blend clamp should be set for all NORM/SRGB types */
3129 if (ntype == V_028C70_NUMBER_UNORM ||
3130 ntype == V_028C70_NUMBER_SNORM ||
3131 ntype == V_028C70_NUMBER_SRGB)
3132 blend_clamp = 1;
3133
3134 /* set blend bypass according to docs if SINT/UINT or
3135 8/24 COLOR variants */
3136 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3137 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3138 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3139 blend_clamp = 0;
3140 blend_bypass = 1;
3141 }
3142 #if 0
3143 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3144 (format == V_028C70_COLOR_8 ||
3145 format == V_028C70_COLOR_8_8 ||
3146 format == V_028C70_COLOR_8_8_8_8))
3147 ->color_is_int8 = true;
3148 #endif
3149 cb->cb_color_info = S_028C70_FORMAT(format) |
3150 S_028C70_COMP_SWAP(swap) |
3151 S_028C70_BLEND_CLAMP(blend_clamp) |
3152 S_028C70_BLEND_BYPASS(blend_bypass) |
3153 S_028C70_SIMPLE_FLOAT(1) |
3154 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3155 ntype != V_028C70_NUMBER_SNORM &&
3156 ntype != V_028C70_NUMBER_SRGB &&
3157 format != V_028C70_COLOR_8_24 &&
3158 format != V_028C70_COLOR_24_8) |
3159 S_028C70_NUMBER_TYPE(ntype) |
3160 S_028C70_ENDIAN(endian);
3161 if ((iview->image->info.samples > 1) && iview->image->fmask.size) {
3162 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3163 if (device->physical_device->rad_info.chip_class == SI) {
3164 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3165 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3166 }
3167 }
3168
3169 if (iview->image->cmask.size &&
3170 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3171 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3172
3173 if (radv_vi_dcc_enabled(iview->image, iview->base_mip))
3174 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3175
3176 if (device->physical_device->rad_info.chip_class >= VI) {
3177 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
3178 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
3179 unsigned independent_64b_blocks = 0;
3180 unsigned max_compressed_block_size;
3181
3182 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
3183 64 for APU because all of our APUs to date use DIMMs which have
3184 a request granularity size of 64B while all other chips have a
3185 32B request size */
3186 if (!device->physical_device->rad_info.has_dedicated_vram)
3187 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
3188
3189 if (iview->image->info.samples > 1) {
3190 if (iview->image->surface.bpe == 1)
3191 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3192 else if (iview->image->surface.bpe == 2)
3193 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
3194 }
3195
3196 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT | VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
3197 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
3198 independent_64b_blocks = 1;
3199 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3200 } else
3201 max_compressed_block_size = max_uncompressed_block_size;
3202
3203 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3204 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
3205 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
3206 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
3207 }
3208
3209 /* This must be set for fast clear to work without FMASK. */
3210 if (!iview->image->fmask.size &&
3211 device->physical_device->rad_info.chip_class == SI) {
3212 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3213 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3214 }
3215
3216 if (device->physical_device->rad_info.chip_class >= GFX9) {
3217 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
3218 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
3219
3220 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3221 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3222 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3223 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
3224 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
3225 S_028C68_MAX_MIP(iview->image->info.levels - 1);
3226 }
3227 }
3228
3229 static void
3230 radv_initialise_ds_surface(struct radv_device *device,
3231 struct radv_ds_buffer_info *ds,
3232 struct radv_image_view *iview)
3233 {
3234 unsigned level = iview->base_mip;
3235 unsigned format, stencil_format;
3236 uint64_t va, s_offs, z_offs;
3237 bool stencil_only = false;
3238 memset(ds, 0, sizeof(*ds));
3239 switch (iview->image->vk_format) {
3240 case VK_FORMAT_D24_UNORM_S8_UINT:
3241 case VK_FORMAT_X8_D24_UNORM_PACK32:
3242 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3243 ds->offset_scale = 2.0f;
3244 break;
3245 case VK_FORMAT_D16_UNORM:
3246 case VK_FORMAT_D16_UNORM_S8_UINT:
3247 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3248 ds->offset_scale = 4.0f;
3249 break;
3250 case VK_FORMAT_D32_SFLOAT:
3251 case VK_FORMAT_D32_SFLOAT_S8_UINT:
3252 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3253 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3254 ds->offset_scale = 1.0f;
3255 break;
3256 case VK_FORMAT_S8_UINT:
3257 stencil_only = true;
3258 break;
3259 default:
3260 break;
3261 }
3262
3263 format = radv_translate_dbformat(iview->image->vk_format);
3264 stencil_format = iview->image->surface.has_stencil ?
3265 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
3266
3267 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3268 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
3269 S_028008_SLICE_MAX(max_slice);
3270
3271 ds->db_htile_data_base = 0;
3272 ds->db_htile_surface = 0;
3273
3274 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3275 s_offs = z_offs = va;
3276
3277 if (device->physical_device->rad_info.chip_class >= GFX9) {
3278 assert(iview->image->surface.u.gfx9.surf_offset == 0);
3279 s_offs += iview->image->surface.u.gfx9.stencil_offset;
3280
3281 ds->db_z_info = S_028038_FORMAT(format) |
3282 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
3283 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3284 S_028038_MAXMIP(iview->image->info.levels - 1);
3285 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
3286 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
3287
3288 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3289 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
3290 ds->db_depth_view |= S_028008_MIPID(level);
3291
3292 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
3293 S_02801C_Y_MAX(iview->image->info.height - 1);
3294
3295 if (radv_htile_enabled(iview->image, level)) {
3296 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
3297
3298 if (iview->image->tc_compatible_htile) {
3299 unsigned max_zplanes = 4;
3300
3301 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
3302 iview->image->info.samples > 1)
3303 max_zplanes = 2;
3304
3305 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
3306 S_028038_ITERATE_FLUSH(1);
3307 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
3308 }
3309
3310 if (!iview->image->surface.has_stencil)
3311 /* Use all of the htile_buffer for depth if there's no stencil. */
3312 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
3313 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3314 iview->image->htile_offset;
3315 ds->db_htile_data_base = va >> 8;
3316 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
3317 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
3318 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
3319 }
3320 } else {
3321 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
3322
3323 if (stencil_only)
3324 level_info = &iview->image->surface.u.legacy.stencil_level[level];
3325
3326 z_offs += iview->image->surface.u.legacy.level[level].offset;
3327 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
3328
3329 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!iview->image->tc_compatible_htile);
3330 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
3331 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
3332
3333 if (iview->image->info.samples > 1)
3334 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
3335
3336 if (device->physical_device->rad_info.chip_class >= CIK) {
3337 struct radeon_info *info = &device->physical_device->rad_info;
3338 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
3339 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
3340 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
3341 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
3342 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
3343 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
3344
3345 if (stencil_only)
3346 tile_mode = stencil_tile_mode;
3347
3348 ds->db_depth_info |=
3349 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
3350 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
3351 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
3352 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
3353 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
3354 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
3355 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
3356 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
3357 } else {
3358 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
3359 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3360 tile_mode_index = si_tile_mode_index(iview->image, level, true);
3361 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
3362 if (stencil_only)
3363 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3364 }
3365
3366 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
3367 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
3368 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
3369
3370 if (radv_htile_enabled(iview->image, level)) {
3371 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
3372
3373 if (!iview->image->surface.has_stencil &&
3374 !iview->image->tc_compatible_htile)
3375 /* Use all of the htile_buffer for depth if there's no stencil. */
3376 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
3377
3378 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3379 iview->image->htile_offset;
3380 ds->db_htile_data_base = va >> 8;
3381 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
3382
3383 if (iview->image->tc_compatible_htile) {
3384 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
3385
3386 if (iview->image->info.samples <= 1)
3387 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
3388 else if (iview->image->info.samples <= 4)
3389 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
3390 else
3391 ds->db_z_info|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
3392 }
3393 }
3394 }
3395
3396 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
3397 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
3398 }
3399
3400 VkResult radv_CreateFramebuffer(
3401 VkDevice _device,
3402 const VkFramebufferCreateInfo* pCreateInfo,
3403 const VkAllocationCallbacks* pAllocator,
3404 VkFramebuffer* pFramebuffer)
3405 {
3406 RADV_FROM_HANDLE(radv_device, device, _device);
3407 struct radv_framebuffer *framebuffer;
3408
3409 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
3410
3411 size_t size = sizeof(*framebuffer) +
3412 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
3413 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
3414 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3415 if (framebuffer == NULL)
3416 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3417
3418 framebuffer->attachment_count = pCreateInfo->attachmentCount;
3419 framebuffer->width = pCreateInfo->width;
3420 framebuffer->height = pCreateInfo->height;
3421 framebuffer->layers = pCreateInfo->layers;
3422 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
3423 VkImageView _iview = pCreateInfo->pAttachments[i];
3424 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
3425 framebuffer->attachments[i].attachment = iview;
3426 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
3427 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
3428 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3429 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
3430 }
3431 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
3432 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
3433 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
3434 }
3435
3436 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
3437 return VK_SUCCESS;
3438 }
3439
3440 void radv_DestroyFramebuffer(
3441 VkDevice _device,
3442 VkFramebuffer _fb,
3443 const VkAllocationCallbacks* pAllocator)
3444 {
3445 RADV_FROM_HANDLE(radv_device, device, _device);
3446 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
3447
3448 if (!fb)
3449 return;
3450 vk_free2(&device->alloc, pAllocator, fb);
3451 }
3452
3453 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
3454 {
3455 switch (address_mode) {
3456 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
3457 return V_008F30_SQ_TEX_WRAP;
3458 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
3459 return V_008F30_SQ_TEX_MIRROR;
3460 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
3461 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
3462 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
3463 return V_008F30_SQ_TEX_CLAMP_BORDER;
3464 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
3465 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
3466 default:
3467 unreachable("illegal tex wrap mode");
3468 break;
3469 }
3470 }
3471
3472 static unsigned
3473 radv_tex_compare(VkCompareOp op)
3474 {
3475 switch (op) {
3476 case VK_COMPARE_OP_NEVER:
3477 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
3478 case VK_COMPARE_OP_LESS:
3479 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
3480 case VK_COMPARE_OP_EQUAL:
3481 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
3482 case VK_COMPARE_OP_LESS_OR_EQUAL:
3483 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
3484 case VK_COMPARE_OP_GREATER:
3485 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
3486 case VK_COMPARE_OP_NOT_EQUAL:
3487 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
3488 case VK_COMPARE_OP_GREATER_OR_EQUAL:
3489 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
3490 case VK_COMPARE_OP_ALWAYS:
3491 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
3492 default:
3493 unreachable("illegal compare mode");
3494 break;
3495 }
3496 }
3497
3498 static unsigned
3499 radv_tex_filter(VkFilter filter, unsigned max_ansio)
3500 {
3501 switch (filter) {
3502 case VK_FILTER_NEAREST:
3503 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
3504 V_008F38_SQ_TEX_XY_FILTER_POINT);
3505 case VK_FILTER_LINEAR:
3506 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
3507 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
3508 case VK_FILTER_CUBIC_IMG:
3509 default:
3510 fprintf(stderr, "illegal texture filter");
3511 return 0;
3512 }
3513 }
3514
3515 static unsigned
3516 radv_tex_mipfilter(VkSamplerMipmapMode mode)
3517 {
3518 switch (mode) {
3519 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
3520 return V_008F38_SQ_TEX_Z_FILTER_POINT;
3521 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
3522 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
3523 default:
3524 return V_008F38_SQ_TEX_Z_FILTER_NONE;
3525 }
3526 }
3527
3528 static unsigned
3529 radv_tex_bordercolor(VkBorderColor bcolor)
3530 {
3531 switch (bcolor) {
3532 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
3533 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
3534 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3535 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
3536 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
3537 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3538 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
3539 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
3540 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3541 default:
3542 break;
3543 }
3544 return 0;
3545 }
3546
3547 static unsigned
3548 radv_tex_aniso_filter(unsigned filter)
3549 {
3550 if (filter < 2)
3551 return 0;
3552 if (filter < 4)
3553 return 1;
3554 if (filter < 8)
3555 return 2;
3556 if (filter < 16)
3557 return 3;
3558 return 4;
3559 }
3560
3561 static void
3562 radv_init_sampler(struct radv_device *device,
3563 struct radv_sampler *sampler,
3564 const VkSamplerCreateInfo *pCreateInfo)
3565 {
3566 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
3567 (uint32_t) pCreateInfo->maxAnisotropy : 0;
3568 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
3569 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
3570
3571 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
3572 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
3573 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
3574 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3575 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
3576 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
3577 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3578 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3579 S_008F30_DISABLE_CUBE_WRAP(0) |
3580 S_008F30_COMPAT_MODE(is_vi));
3581 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
3582 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
3583 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3584 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
3585 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
3586 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
3587 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
3588 S_008F38_MIP_POINT_PRECLAMP(0) |
3589 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
3590 S_008F38_FILTER_PREC_FIX(1) |
3591 S_008F38_ANISO_OVERRIDE(is_vi));
3592 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3593 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
3594 }
3595
3596 VkResult radv_CreateSampler(
3597 VkDevice _device,
3598 const VkSamplerCreateInfo* pCreateInfo,
3599 const VkAllocationCallbacks* pAllocator,
3600 VkSampler* pSampler)
3601 {
3602 RADV_FROM_HANDLE(radv_device, device, _device);
3603 struct radv_sampler *sampler;
3604
3605 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
3606
3607 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
3608 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3609 if (!sampler)
3610 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3611
3612 radv_init_sampler(device, sampler, pCreateInfo);
3613 *pSampler = radv_sampler_to_handle(sampler);
3614
3615 return VK_SUCCESS;
3616 }
3617
3618 void radv_DestroySampler(
3619 VkDevice _device,
3620 VkSampler _sampler,
3621 const VkAllocationCallbacks* pAllocator)
3622 {
3623 RADV_FROM_HANDLE(radv_device, device, _device);
3624 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
3625
3626 if (!sampler)
3627 return;
3628 vk_free2(&device->alloc, pAllocator, sampler);
3629 }
3630
3631 /* vk_icd.h does not declare this function, so we declare it here to
3632 * suppress Wmissing-prototypes.
3633 */
3634 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3635 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
3636
3637 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3638 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
3639 {
3640 /* For the full details on loader interface versioning, see
3641 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3642 * What follows is a condensed summary, to help you navigate the large and
3643 * confusing official doc.
3644 *
3645 * - Loader interface v0 is incompatible with later versions. We don't
3646 * support it.
3647 *
3648 * - In loader interface v1:
3649 * - The first ICD entrypoint called by the loader is
3650 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3651 * entrypoint.
3652 * - The ICD must statically expose no other Vulkan symbol unless it is
3653 * linked with -Bsymbolic.
3654 * - Each dispatchable Vulkan handle created by the ICD must be
3655 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3656 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3657 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3658 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3659 * such loader-managed surfaces.
3660 *
3661 * - Loader interface v2 differs from v1 in:
3662 * - The first ICD entrypoint called by the loader is
3663 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3664 * statically expose this entrypoint.
3665 *
3666 * - Loader interface v3 differs from v2 in:
3667 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3668 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3669 * because the loader no longer does so.
3670 */
3671 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
3672 return VK_SUCCESS;
3673 }
3674
3675 VkResult radv_GetMemoryFdKHR(VkDevice _device,
3676 const VkMemoryGetFdInfoKHR *pGetFdInfo,
3677 int *pFD)
3678 {
3679 RADV_FROM_HANDLE(radv_device, device, _device);
3680 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
3681
3682 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
3683
3684 /* At the moment, we support only the below handle types. */
3685 assert(pGetFdInfo->handleType ==
3686 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
3687 pGetFdInfo->handleType ==
3688 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3689
3690 bool ret = radv_get_memory_fd(device, memory, pFD);
3691 if (ret == false)
3692 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
3693 return VK_SUCCESS;
3694 }
3695
3696 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
3697 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
3698 int fd,
3699 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
3700 {
3701 switch (handleType) {
3702 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
3703 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
3704 return VK_SUCCESS;
3705
3706 default:
3707 /* The valid usage section for this function says:
3708 *
3709 * "handleType must not be one of the handle types defined as
3710 * opaque."
3711 *
3712 * So opaque handle types fall into the default "unsupported" case.
3713 */
3714 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3715 }
3716 }
3717
3718 static VkResult radv_import_opaque_fd(struct radv_device *device,
3719 int fd,
3720 uint32_t *syncobj)
3721 {
3722 uint32_t syncobj_handle = 0;
3723 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
3724 if (ret != 0)
3725 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3726
3727 if (*syncobj)
3728 device->ws->destroy_syncobj(device->ws, *syncobj);
3729
3730 *syncobj = syncobj_handle;
3731 close(fd);
3732
3733 return VK_SUCCESS;
3734 }
3735
3736 static VkResult radv_import_sync_fd(struct radv_device *device,
3737 int fd,
3738 uint32_t *syncobj)
3739 {
3740 /* If we create a syncobj we do it locally so that if we have an error, we don't
3741 * leave a syncobj in an undetermined state in the fence. */
3742 uint32_t syncobj_handle = *syncobj;
3743 if (!syncobj_handle) {
3744 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
3745 if (ret) {
3746 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3747 }
3748 }
3749
3750 if (fd == -1) {
3751 device->ws->signal_syncobj(device->ws, syncobj_handle);
3752 } else {
3753 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
3754 if (ret != 0)
3755 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3756 }
3757
3758 *syncobj = syncobj_handle;
3759 if (fd != -1)
3760 close(fd);
3761
3762 return VK_SUCCESS;
3763 }
3764
3765 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
3766 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
3767 {
3768 RADV_FROM_HANDLE(radv_device, device, _device);
3769 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
3770 uint32_t *syncobj_dst = NULL;
3771
3772 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
3773 syncobj_dst = &sem->temp_syncobj;
3774 } else {
3775 syncobj_dst = &sem->syncobj;
3776 }
3777
3778 switch(pImportSemaphoreFdInfo->handleType) {
3779 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
3780 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
3781 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
3782 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
3783 default:
3784 unreachable("Unhandled semaphore handle type");
3785 }
3786 }
3787
3788 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
3789 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
3790 int *pFd)
3791 {
3792 RADV_FROM_HANDLE(radv_device, device, _device);
3793 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
3794 int ret;
3795 uint32_t syncobj_handle;
3796
3797 if (sem->temp_syncobj)
3798 syncobj_handle = sem->temp_syncobj;
3799 else
3800 syncobj_handle = sem->syncobj;
3801
3802 switch(pGetFdInfo->handleType) {
3803 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
3804 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
3805 break;
3806 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
3807 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
3808 break;
3809 default:
3810 unreachable("Unhandled semaphore handle type");
3811 }
3812
3813 if (ret)
3814 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3815 return VK_SUCCESS;
3816 }
3817
3818 void radv_GetPhysicalDeviceExternalSemaphorePropertiesKHR(
3819 VkPhysicalDevice physicalDevice,
3820 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
3821 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
3822 {
3823 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
3824
3825 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
3826 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
3827 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
3828 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
3829 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
3830 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
3831 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
3832 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
3833 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
3834 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3835 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3836 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
3837 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
3838 } else {
3839 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
3840 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
3841 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
3842 }
3843 }
3844
3845 VkResult radv_ImportFenceFdKHR(VkDevice _device,
3846 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
3847 {
3848 RADV_FROM_HANDLE(radv_device, device, _device);
3849 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
3850 uint32_t *syncobj_dst = NULL;
3851
3852
3853 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT_KHR) {
3854 syncobj_dst = &fence->temp_syncobj;
3855 } else {
3856 syncobj_dst = &fence->syncobj;
3857 }
3858
3859 switch(pImportFenceFdInfo->handleType) {
3860 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
3861 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
3862 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
3863 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
3864 default:
3865 unreachable("Unhandled fence handle type");
3866 }
3867 }
3868
3869 VkResult radv_GetFenceFdKHR(VkDevice _device,
3870 const VkFenceGetFdInfoKHR *pGetFdInfo,
3871 int *pFd)
3872 {
3873 RADV_FROM_HANDLE(radv_device, device, _device);
3874 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
3875 int ret;
3876 uint32_t syncobj_handle;
3877
3878 if (fence->temp_syncobj)
3879 syncobj_handle = fence->temp_syncobj;
3880 else
3881 syncobj_handle = fence->syncobj;
3882
3883 switch(pGetFdInfo->handleType) {
3884 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
3885 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
3886 break;
3887 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
3888 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
3889 break;
3890 default:
3891 unreachable("Unhandled fence handle type");
3892 }
3893
3894 if (ret)
3895 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3896 return VK_SUCCESS;
3897 }
3898
3899 void radv_GetPhysicalDeviceExternalFencePropertiesKHR(
3900 VkPhysicalDevice physicalDevice,
3901 const VkPhysicalDeviceExternalFenceInfoKHR* pExternalFenceInfo,
3902 VkExternalFencePropertiesKHR* pExternalFenceProperties)
3903 {
3904 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
3905
3906 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
3907 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
3908 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
3909 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
3910 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
3911 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT_KHR |
3912 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
3913 } else {
3914 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
3915 pExternalFenceProperties->compatibleHandleTypes = 0;
3916 pExternalFenceProperties->externalFenceFeatures = 0;
3917 }
3918 }