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anv: set maxFragmentDualSrcAttachments to 1
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <dlfcn.h>
29 #include <stdbool.h>
30 #include <string.h>
31 #include <unistd.h>
32 #include <fcntl.h>
33 #include <sys/stat.h>
34 #include "radv_private.h"
35 #include "util/strtod.h"
36
37 #include <xf86drm.h>
38 #include <amdgpu.h>
39 #include <amdgpu_drm.h>
40 #include "amdgpu_id.h"
41 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
42 #include "ac_llvm_util.h"
43 #include "vk_format.h"
44 #include "sid.h"
45 #include "util/debug.h"
46 struct radv_dispatch_table dtable;
47
48 static int
49 radv_get_function_timestamp(void *ptr, uint32_t* timestamp)
50 {
51 Dl_info info;
52 struct stat st;
53 if (!dladdr(ptr, &info) || !info.dli_fname) {
54 return -1;
55 }
56 if (stat(info.dli_fname, &st)) {
57 return -1;
58 }
59 *timestamp = st.st_mtim.tv_sec;
60 return 0;
61 }
62
63 static int
64 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
65 {
66 uint32_t mesa_timestamp, llvm_timestamp;
67 uint16_t f = family;
68 memset(uuid, 0, VK_UUID_SIZE);
69 if (radv_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
70 radv_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
71 return -1;
72
73 memcpy(uuid, &mesa_timestamp, 4);
74 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
75 memcpy((char*)uuid + 8, &f, 2);
76 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
77 return 0;
78 }
79
80 static VkResult
81 radv_physical_device_init(struct radv_physical_device *device,
82 struct radv_instance *instance,
83 const char *path)
84 {
85 VkResult result;
86 drmVersionPtr version;
87 int fd;
88
89 fd = open(path, O_RDWR | O_CLOEXEC);
90 if (fd < 0)
91 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
92 "failed to open %s: %m", path);
93
94 version = drmGetVersion(fd);
95 if (!version) {
96 close(fd);
97 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
98 "failed to get version %s: %m", path);
99 }
100
101 if (strcmp(version->name, "amdgpu")) {
102 drmFreeVersion(version);
103 close(fd);
104 return VK_ERROR_INCOMPATIBLE_DRIVER;
105 }
106 drmFreeVersion(version);
107
108 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
109 device->instance = instance;
110 assert(strlen(path) < ARRAY_SIZE(device->path));
111 strncpy(device->path, path, ARRAY_SIZE(device->path));
112
113 device->ws = radv_amdgpu_winsys_create(fd);
114 if (!device->ws) {
115 result = VK_ERROR_INCOMPATIBLE_DRIVER;
116 goto fail;
117 }
118 device->ws->query_info(device->ws, &device->rad_info);
119 result = radv_init_wsi(device);
120 if (result != VK_SUCCESS) {
121 device->ws->destroy(device->ws);
122 goto fail;
123 }
124
125 if (radv_device_get_cache_uuid(device->rad_info.family, device->uuid)) {
126 radv_finish_wsi(device);
127 device->ws->destroy(device->ws);
128 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
129 "cannot generate UUID");
130 goto fail;
131 }
132
133 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
134 device->name = device->rad_info.name;
135 close(fd);
136 return VK_SUCCESS;
137
138 fail:
139 close(fd);
140 return result;
141 }
142
143 static void
144 radv_physical_device_finish(struct radv_physical_device *device)
145 {
146 radv_finish_wsi(device);
147 device->ws->destroy(device->ws);
148 }
149
150 static const VkExtensionProperties global_extensions[] = {
151 {
152 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
153 .specVersion = 25,
154 },
155 #ifdef VK_USE_PLATFORM_XCB_KHR
156 {
157 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
158 .specVersion = 6,
159 },
160 #endif
161 #ifdef VK_USE_PLATFORM_XLIB_KHR
162 {
163 .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
164 .specVersion = 6,
165 },
166 #endif
167 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
168 {
169 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
170 .specVersion = 5,
171 },
172 #endif
173 };
174
175 static const VkExtensionProperties device_extensions[] = {
176 {
177 .extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
178 .specVersion = 1,
179 },
180 {
181 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
182 .specVersion = 68,
183 },
184 {
185 .extensionName = VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME,
186 .specVersion = 1,
187 },
188 {
189 .extensionName = VK_AMD_NEGATIVE_VIEWPORT_HEIGHT_EXTENSION_NAME,
190 .specVersion = 1,
191 },
192 };
193
194 static void *
195 default_alloc_func(void *pUserData, size_t size, size_t align,
196 VkSystemAllocationScope allocationScope)
197 {
198 return malloc(size);
199 }
200
201 static void *
202 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
203 size_t align, VkSystemAllocationScope allocationScope)
204 {
205 return realloc(pOriginal, size);
206 }
207
208 static void
209 default_free_func(void *pUserData, void *pMemory)
210 {
211 free(pMemory);
212 }
213
214 static const VkAllocationCallbacks default_alloc = {
215 .pUserData = NULL,
216 .pfnAllocation = default_alloc_func,
217 .pfnReallocation = default_realloc_func,
218 .pfnFree = default_free_func,
219 };
220
221 VkResult radv_CreateInstance(
222 const VkInstanceCreateInfo* pCreateInfo,
223 const VkAllocationCallbacks* pAllocator,
224 VkInstance* pInstance)
225 {
226 struct radv_instance *instance;
227
228 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
229
230 uint32_t client_version;
231 if (pCreateInfo->pApplicationInfo &&
232 pCreateInfo->pApplicationInfo->apiVersion != 0) {
233 client_version = pCreateInfo->pApplicationInfo->apiVersion;
234 } else {
235 client_version = VK_MAKE_VERSION(1, 0, 0);
236 }
237
238 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
239 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
240 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
241 "Client requested version %d.%d.%d",
242 VK_VERSION_MAJOR(client_version),
243 VK_VERSION_MINOR(client_version),
244 VK_VERSION_PATCH(client_version));
245 }
246
247 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
248 bool found = false;
249 for (uint32_t j = 0; j < ARRAY_SIZE(global_extensions); j++) {
250 if (strcmp(pCreateInfo->ppEnabledExtensionNames[i],
251 global_extensions[j].extensionName) == 0) {
252 found = true;
253 break;
254 }
255 }
256 if (!found)
257 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
258 }
259
260 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
261 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
262 if (!instance)
263 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
264
265 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
266
267 if (pAllocator)
268 instance->alloc = *pAllocator;
269 else
270 instance->alloc = default_alloc;
271
272 instance->apiVersion = client_version;
273 instance->physicalDeviceCount = -1;
274
275 _mesa_locale_init();
276
277 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
278
279 *pInstance = radv_instance_to_handle(instance);
280
281 return VK_SUCCESS;
282 }
283
284 void radv_DestroyInstance(
285 VkInstance _instance,
286 const VkAllocationCallbacks* pAllocator)
287 {
288 RADV_FROM_HANDLE(radv_instance, instance, _instance);
289
290 if (instance->physicalDeviceCount > 0) {
291 /* We support at most one physical device. */
292 assert(instance->physicalDeviceCount == 1);
293 radv_physical_device_finish(&instance->physicalDevice);
294 }
295
296 VG(VALGRIND_DESTROY_MEMPOOL(instance));
297
298 _mesa_locale_fini();
299
300 vk_free(&instance->alloc, instance);
301 }
302
303 VkResult radv_EnumeratePhysicalDevices(
304 VkInstance _instance,
305 uint32_t* pPhysicalDeviceCount,
306 VkPhysicalDevice* pPhysicalDevices)
307 {
308 RADV_FROM_HANDLE(radv_instance, instance, _instance);
309 VkResult result;
310
311 if (instance->physicalDeviceCount < 0) {
312 char path[20];
313 for (unsigned i = 0; i < 8; i++) {
314 snprintf(path, sizeof(path), "/dev/dri/renderD%d", 128 + i);
315 result = radv_physical_device_init(&instance->physicalDevice,
316 instance, path);
317 if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
318 break;
319 }
320
321 if (result == VK_ERROR_INCOMPATIBLE_DRIVER) {
322 instance->physicalDeviceCount = 0;
323 } else if (result == VK_SUCCESS) {
324 instance->physicalDeviceCount = 1;
325 } else {
326 return result;
327 }
328 }
329
330 /* pPhysicalDeviceCount is an out parameter if pPhysicalDevices is NULL;
331 * otherwise it's an inout parameter.
332 *
333 * The Vulkan spec (git aaed022) says:
334 *
335 * pPhysicalDeviceCount is a pointer to an unsigned integer variable
336 * that is initialized with the number of devices the application is
337 * prepared to receive handles to. pname:pPhysicalDevices is pointer to
338 * an array of at least this many VkPhysicalDevice handles [...].
339 *
340 * Upon success, if pPhysicalDevices is NULL, vkEnumeratePhysicalDevices
341 * overwrites the contents of the variable pointed to by
342 * pPhysicalDeviceCount with the number of physical devices in in the
343 * instance; otherwise, vkEnumeratePhysicalDevices overwrites
344 * pPhysicalDeviceCount with the number of physical handles written to
345 * pPhysicalDevices.
346 */
347 if (!pPhysicalDevices) {
348 *pPhysicalDeviceCount = instance->physicalDeviceCount;
349 } else if (*pPhysicalDeviceCount >= 1) {
350 pPhysicalDevices[0] = radv_physical_device_to_handle(&instance->physicalDevice);
351 *pPhysicalDeviceCount = 1;
352 } else if (*pPhysicalDeviceCount < instance->physicalDeviceCount) {
353 return VK_INCOMPLETE;
354 } else {
355 *pPhysicalDeviceCount = 0;
356 }
357
358 return VK_SUCCESS;
359 }
360
361 void radv_GetPhysicalDeviceFeatures(
362 VkPhysicalDevice physicalDevice,
363 VkPhysicalDeviceFeatures* pFeatures)
364 {
365 // RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
366
367 memset(pFeatures, 0, sizeof(*pFeatures));
368
369 *pFeatures = (VkPhysicalDeviceFeatures) {
370 .robustBufferAccess = true,
371 .fullDrawIndexUint32 = true,
372 .imageCubeArray = true,
373 .independentBlend = true,
374 .geometryShader = false,
375 .tessellationShader = false,
376 .sampleRateShading = false,
377 .dualSrcBlend = true,
378 .logicOp = true,
379 .multiDrawIndirect = true,
380 .drawIndirectFirstInstance = true,
381 .depthClamp = true,
382 .depthBiasClamp = true,
383 .fillModeNonSolid = true,
384 .depthBounds = true,
385 .wideLines = true,
386 .largePoints = true,
387 .alphaToOne = true,
388 .multiViewport = false,
389 .samplerAnisotropy = true,
390 .textureCompressionETC2 = false,
391 .textureCompressionASTC_LDR = false,
392 .textureCompressionBC = true,
393 .occlusionQueryPrecise = true,
394 .pipelineStatisticsQuery = false,
395 .vertexPipelineStoresAndAtomics = true,
396 .fragmentStoresAndAtomics = true,
397 .shaderTessellationAndGeometryPointSize = true,
398 .shaderImageGatherExtended = false,
399 .shaderStorageImageExtendedFormats = false,
400 .shaderStorageImageMultisample = false,
401 .shaderUniformBufferArrayDynamicIndexing = true,
402 .shaderSampledImageArrayDynamicIndexing = true,
403 .shaderStorageBufferArrayDynamicIndexing = true,
404 .shaderStorageImageArrayDynamicIndexing = true,
405 .shaderStorageImageReadWithoutFormat = false,
406 .shaderStorageImageWriteWithoutFormat = true,
407 .shaderClipDistance = true,
408 .shaderCullDistance = true,
409 .shaderFloat64 = false,
410 .shaderInt64 = false,
411 .shaderInt16 = false,
412 .alphaToOne = true,
413 .variableMultisampleRate = false,
414 .inheritedQueries = false,
415 };
416 }
417
418 void radv_GetPhysicalDeviceProperties(
419 VkPhysicalDevice physicalDevice,
420 VkPhysicalDeviceProperties* pProperties)
421 {
422 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
423 VkSampleCountFlags sample_counts = 0xf;
424 VkPhysicalDeviceLimits limits = {
425 .maxImageDimension1D = (1 << 14),
426 .maxImageDimension2D = (1 << 14),
427 .maxImageDimension3D = (1 << 11),
428 .maxImageDimensionCube = (1 << 14),
429 .maxImageArrayLayers = (1 << 11),
430 .maxTexelBufferElements = 128 * 1024 * 1024,
431 .maxUniformBufferRange = UINT32_MAX,
432 .maxStorageBufferRange = UINT32_MAX,
433 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
434 .maxMemoryAllocationCount = UINT32_MAX,
435 .maxSamplerAllocationCount = 64 * 1024,
436 .bufferImageGranularity = 64, /* A cache line */
437 .sparseAddressSpaceSize = 0,
438 .maxBoundDescriptorSets = MAX_SETS,
439 .maxPerStageDescriptorSamplers = 64,
440 .maxPerStageDescriptorUniformBuffers = 64,
441 .maxPerStageDescriptorStorageBuffers = 64,
442 .maxPerStageDescriptorSampledImages = 64,
443 .maxPerStageDescriptorStorageImages = 64,
444 .maxPerStageDescriptorInputAttachments = 64,
445 .maxPerStageResources = 128,
446 .maxDescriptorSetSamplers = 256,
447 .maxDescriptorSetUniformBuffers = 256,
448 .maxDescriptorSetUniformBuffersDynamic = 256,
449 .maxDescriptorSetStorageBuffers = 256,
450 .maxDescriptorSetStorageBuffersDynamic = 256,
451 .maxDescriptorSetSampledImages = 256,
452 .maxDescriptorSetStorageImages = 256,
453 .maxDescriptorSetInputAttachments = 256,
454 .maxVertexInputAttributes = 32,
455 .maxVertexInputBindings = 32,
456 .maxVertexInputAttributeOffset = 2047,
457 .maxVertexInputBindingStride = 2048,
458 .maxVertexOutputComponents = 128,
459 .maxTessellationGenerationLevel = 0,
460 .maxTessellationPatchSize = 0,
461 .maxTessellationControlPerVertexInputComponents = 0,
462 .maxTessellationControlPerVertexOutputComponents = 0,
463 .maxTessellationControlPerPatchOutputComponents = 0,
464 .maxTessellationControlTotalOutputComponents = 0,
465 .maxTessellationEvaluationInputComponents = 0,
466 .maxTessellationEvaluationOutputComponents = 0,
467 .maxGeometryShaderInvocations = 32,
468 .maxGeometryInputComponents = 64,
469 .maxGeometryOutputComponents = 128,
470 .maxGeometryOutputVertices = 256,
471 .maxGeometryTotalOutputComponents = 1024,
472 .maxFragmentInputComponents = 128,
473 .maxFragmentOutputAttachments = 8,
474 .maxFragmentDualSrcAttachments = 1,
475 .maxFragmentCombinedOutputResources = 8,
476 .maxComputeSharedMemorySize = 32768,
477 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
478 .maxComputeWorkGroupInvocations = 16 * 1024,
479 .maxComputeWorkGroupSize = {
480 16 * 1024/*devinfo->max_cs_threads*/,
481 16 * 1024,
482 16 * 1024
483 },
484 .subPixelPrecisionBits = 4 /* FIXME */,
485 .subTexelPrecisionBits = 4 /* FIXME */,
486 .mipmapPrecisionBits = 4 /* FIXME */,
487 .maxDrawIndexedIndexValue = UINT32_MAX,
488 .maxDrawIndirectCount = UINT32_MAX,
489 .maxSamplerLodBias = 16,
490 .maxSamplerAnisotropy = 16,
491 .maxViewports = MAX_VIEWPORTS,
492 .maxViewportDimensions = { (1 << 14), (1 << 14) },
493 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
494 .viewportSubPixelBits = 13, /* We take a float? */
495 .minMemoryMapAlignment = 4096, /* A page */
496 .minTexelBufferOffsetAlignment = 1,
497 .minUniformBufferOffsetAlignment = 4,
498 .minStorageBufferOffsetAlignment = 4,
499 .minTexelOffset = -8,
500 .maxTexelOffset = 7,
501 .minTexelGatherOffset = -8,
502 .maxTexelGatherOffset = 7,
503 .minInterpolationOffset = 0, /* FIXME */
504 .maxInterpolationOffset = 0, /* FIXME */
505 .subPixelInterpolationOffsetBits = 0, /* FIXME */
506 .maxFramebufferWidth = (1 << 14),
507 .maxFramebufferHeight = (1 << 14),
508 .maxFramebufferLayers = (1 << 10),
509 .framebufferColorSampleCounts = sample_counts,
510 .framebufferDepthSampleCounts = sample_counts,
511 .framebufferStencilSampleCounts = sample_counts,
512 .framebufferNoAttachmentsSampleCounts = sample_counts,
513 .maxColorAttachments = MAX_RTS,
514 .sampledImageColorSampleCounts = sample_counts,
515 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
516 .sampledImageDepthSampleCounts = sample_counts,
517 .sampledImageStencilSampleCounts = sample_counts,
518 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
519 .maxSampleMaskWords = 1,
520 .timestampComputeAndGraphics = false,
521 .timestampPeriod = 100000.0 / pdevice->rad_info.clock_crystal_freq,
522 .maxClipDistances = 8,
523 .maxCullDistances = 8,
524 .maxCombinedClipAndCullDistances = 8,
525 .discreteQueuePriorities = 1,
526 .pointSizeRange = { 0.125, 255.875 },
527 .lineWidthRange = { 0.0, 7.9921875 },
528 .pointSizeGranularity = (1.0 / 8.0),
529 .lineWidthGranularity = (1.0 / 128.0),
530 .strictLines = false, /* FINISHME */
531 .standardSampleLocations = true,
532 .optimalBufferCopyOffsetAlignment = 128,
533 .optimalBufferCopyRowPitchAlignment = 128,
534 .nonCoherentAtomSize = 64,
535 };
536
537 *pProperties = (VkPhysicalDeviceProperties) {
538 .apiVersion = VK_MAKE_VERSION(1, 0, 5),
539 .driverVersion = 1,
540 .vendorID = 0x1002,
541 .deviceID = pdevice->rad_info.pci_id,
542 .deviceType = VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU,
543 .limits = limits,
544 .sparseProperties = {0}, /* Broadwell doesn't do sparse. */
545 };
546
547 strcpy(pProperties->deviceName, pdevice->name);
548 memcpy(pProperties->pipelineCacheUUID, pdevice->uuid, VK_UUID_SIZE);
549 }
550
551 void radv_GetPhysicalDeviceQueueFamilyProperties(
552 VkPhysicalDevice physicalDevice,
553 uint32_t* pCount,
554 VkQueueFamilyProperties* pQueueFamilyProperties)
555 {
556 if (pQueueFamilyProperties == NULL) {
557 *pCount = 1;
558 return;
559 }
560 assert(*pCount >= 1);
561
562 *pQueueFamilyProperties = (VkQueueFamilyProperties) {
563 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
564 VK_QUEUE_COMPUTE_BIT |
565 VK_QUEUE_TRANSFER_BIT,
566 .queueCount = 1,
567 .timestampValidBits = 64,
568 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
569 };
570 }
571
572 void radv_GetPhysicalDeviceMemoryProperties(
573 VkPhysicalDevice physicalDevice,
574 VkPhysicalDeviceMemoryProperties* pMemoryProperties)
575 {
576 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
577
578 pMemoryProperties->memoryTypeCount = 4;
579 pMemoryProperties->memoryTypes[0] = (VkMemoryType) {
580 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
581 .heapIndex = 0,
582 };
583 pMemoryProperties->memoryTypes[1] = (VkMemoryType) {
584 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
585 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
586 .heapIndex = 2,
587 };
588 pMemoryProperties->memoryTypes[2] = (VkMemoryType) {
589 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
590 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
591 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
592 .heapIndex = 1,
593 };
594 pMemoryProperties->memoryTypes[3] = (VkMemoryType) {
595 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
596 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
597 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
598 .heapIndex = 2,
599 };
600
601 pMemoryProperties->memoryHeapCount = 3;
602 pMemoryProperties->memoryHeaps[0] = (VkMemoryHeap) {
603 .size = physical_device->rad_info.vram_size -
604 physical_device->rad_info.visible_vram_size,
605 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
606 };
607 pMemoryProperties->memoryHeaps[1] = (VkMemoryHeap) {
608 .size = physical_device->rad_info.visible_vram_size,
609 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
610 };
611 pMemoryProperties->memoryHeaps[2] = (VkMemoryHeap) {
612 .size = physical_device->rad_info.gart_size,
613 .flags = 0,
614 };
615 }
616
617 static void
618 radv_queue_init(struct radv_device *device, struct radv_queue *queue)
619 {
620 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
621 queue->device = device;
622 }
623
624 static void
625 radv_queue_finish(struct radv_queue *queue)
626 {
627 }
628
629 VkResult radv_CreateDevice(
630 VkPhysicalDevice physicalDevice,
631 const VkDeviceCreateInfo* pCreateInfo,
632 const VkAllocationCallbacks* pAllocator,
633 VkDevice* pDevice)
634 {
635 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
636 VkResult result;
637 struct radv_device *device;
638
639 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
640 bool found = false;
641 for (uint32_t j = 0; j < ARRAY_SIZE(device_extensions); j++) {
642 if (strcmp(pCreateInfo->ppEnabledExtensionNames[i],
643 device_extensions[j].extensionName) == 0) {
644 found = true;
645 break;
646 }
647 }
648 if (!found)
649 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
650 }
651
652 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
653 sizeof(*device), 8,
654 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
655 if (!device)
656 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
657
658 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
659 device->instance = physical_device->instance;
660
661 device->ws = physical_device->ws;
662 if (pAllocator)
663 device->alloc = *pAllocator;
664 else
665 device->alloc = physical_device->instance->alloc;
666
667 device->hw_ctx = device->ws->ctx_create(device->ws);
668 if (!device->hw_ctx) {
669 result = VK_ERROR_OUT_OF_HOST_MEMORY;
670 goto fail_free;
671 }
672
673 radv_queue_init(device, &device->queue);
674
675 result = radv_device_init_meta(device);
676 if (result != VK_SUCCESS) {
677 device->ws->ctx_destroy(device->hw_ctx);
678 goto fail_free;
679 }
680 device->allow_fast_clears = env_var_as_boolean("RADV_FAST_CLEARS", false);
681 device->allow_dcc = !env_var_as_boolean("RADV_DCC_DISABLE", false);
682 device->shader_stats_dump = env_var_as_boolean("RADV_SHADER_STATS", false);
683
684 if (device->allow_fast_clears && device->allow_dcc)
685 radv_finishme("DCC fast clears have not been tested\n");
686
687 radv_device_init_msaa(device);
688 device->empty_cs = device->ws->cs_create(device->ws, RING_GFX);
689 radeon_emit(device->empty_cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
690 radeon_emit(device->empty_cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
691 radeon_emit(device->empty_cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
692 device->ws->cs_finalize(device->empty_cs);
693 *pDevice = radv_device_to_handle(device);
694 return VK_SUCCESS;
695 fail_free:
696 vk_free(&device->alloc, device);
697 return result;
698 }
699
700 void radv_DestroyDevice(
701 VkDevice _device,
702 const VkAllocationCallbacks* pAllocator)
703 {
704 RADV_FROM_HANDLE(radv_device, device, _device);
705
706 device->ws->ctx_destroy(device->hw_ctx);
707 radv_queue_finish(&device->queue);
708 radv_device_finish_meta(device);
709
710 vk_free(&device->alloc, device);
711 }
712
713 VkResult radv_EnumerateInstanceExtensionProperties(
714 const char* pLayerName,
715 uint32_t* pPropertyCount,
716 VkExtensionProperties* pProperties)
717 {
718 if (pProperties == NULL) {
719 *pPropertyCount = ARRAY_SIZE(global_extensions);
720 return VK_SUCCESS;
721 }
722
723 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(global_extensions));
724 typed_memcpy(pProperties, global_extensions, *pPropertyCount);
725
726 if (*pPropertyCount < ARRAY_SIZE(global_extensions))
727 return VK_INCOMPLETE;
728
729 return VK_SUCCESS;
730 }
731
732 VkResult radv_EnumerateDeviceExtensionProperties(
733 VkPhysicalDevice physicalDevice,
734 const char* pLayerName,
735 uint32_t* pPropertyCount,
736 VkExtensionProperties* pProperties)
737 {
738 if (pProperties == NULL) {
739 *pPropertyCount = ARRAY_SIZE(device_extensions);
740 return VK_SUCCESS;
741 }
742
743 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(device_extensions));
744 typed_memcpy(pProperties, device_extensions, *pPropertyCount);
745
746 if (*pPropertyCount < ARRAY_SIZE(device_extensions))
747 return VK_INCOMPLETE;
748
749 return VK_SUCCESS;
750 }
751
752 VkResult radv_EnumerateInstanceLayerProperties(
753 uint32_t* pPropertyCount,
754 VkLayerProperties* pProperties)
755 {
756 if (pProperties == NULL) {
757 *pPropertyCount = 0;
758 return VK_SUCCESS;
759 }
760
761 /* None supported at this time */
762 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
763 }
764
765 VkResult radv_EnumerateDeviceLayerProperties(
766 VkPhysicalDevice physicalDevice,
767 uint32_t* pPropertyCount,
768 VkLayerProperties* pProperties)
769 {
770 if (pProperties == NULL) {
771 *pPropertyCount = 0;
772 return VK_SUCCESS;
773 }
774
775 /* None supported at this time */
776 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
777 }
778
779 void radv_GetDeviceQueue(
780 VkDevice _device,
781 uint32_t queueNodeIndex,
782 uint32_t queueIndex,
783 VkQueue* pQueue)
784 {
785 RADV_FROM_HANDLE(radv_device, device, _device);
786
787 assert(queueIndex == 0);
788
789 *pQueue = radv_queue_to_handle(&device->queue);
790 }
791
792 VkResult radv_QueueSubmit(
793 VkQueue _queue,
794 uint32_t submitCount,
795 const VkSubmitInfo* pSubmits,
796 VkFence _fence)
797 {
798 RADV_FROM_HANDLE(radv_queue, queue, _queue);
799 RADV_FROM_HANDLE(radv_fence, fence, _fence);
800 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
801 struct radeon_winsys_ctx *ctx = queue->device->hw_ctx;
802 int ret;
803
804 for (uint32_t i = 0; i < submitCount; i++) {
805 struct radeon_winsys_cs **cs_array;
806 bool can_patch = true;
807
808 if (!pSubmits[i].commandBufferCount)
809 continue;
810
811 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
812 pSubmits[i].commandBufferCount);
813
814 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
815 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
816 pSubmits[i].pCommandBuffers[j]);
817 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
818
819 cs_array[j] = cmd_buffer->cs;
820 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
821 can_patch = false;
822 }
823 ret = queue->device->ws->cs_submit(ctx, cs_array,
824 pSubmits[i].commandBufferCount,
825 can_patch, base_fence);
826 if (ret)
827 radv_loge("failed to submit CS %d\n", i);
828 free(cs_array);
829 }
830
831 if (fence) {
832 if (!submitCount)
833 ret = queue->device->ws->cs_submit(ctx, &queue->device->empty_cs,
834 1, false, base_fence);
835
836 fence->submitted = true;
837 }
838
839 return VK_SUCCESS;
840 }
841
842 VkResult radv_QueueWaitIdle(
843 VkQueue _queue)
844 {
845 RADV_FROM_HANDLE(radv_queue, queue, _queue);
846
847 queue->device->ws->ctx_wait_idle(queue->device->hw_ctx);
848 return VK_SUCCESS;
849 }
850
851 VkResult radv_DeviceWaitIdle(
852 VkDevice _device)
853 {
854 RADV_FROM_HANDLE(radv_device, device, _device);
855
856 device->ws->ctx_wait_idle(device->hw_ctx);
857 return VK_SUCCESS;
858 }
859
860 PFN_vkVoidFunction radv_GetInstanceProcAddr(
861 VkInstance instance,
862 const char* pName)
863 {
864 return radv_lookup_entrypoint(pName);
865 }
866
867 /* The loader wants us to expose a second GetInstanceProcAddr function
868 * to work around certain LD_PRELOAD issues seen in apps.
869 */
870 PUBLIC
871 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
872 VkInstance instance,
873 const char* pName);
874
875 PUBLIC
876 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
877 VkInstance instance,
878 const char* pName)
879 {
880 return radv_GetInstanceProcAddr(instance, pName);
881 }
882
883 PFN_vkVoidFunction radv_GetDeviceProcAddr(
884 VkDevice device,
885 const char* pName)
886 {
887 return radv_lookup_entrypoint(pName);
888 }
889
890 VkResult radv_AllocateMemory(
891 VkDevice _device,
892 const VkMemoryAllocateInfo* pAllocateInfo,
893 const VkAllocationCallbacks* pAllocator,
894 VkDeviceMemory* pMem)
895 {
896 RADV_FROM_HANDLE(radv_device, device, _device);
897 struct radv_device_memory *mem;
898 VkResult result;
899 enum radeon_bo_domain domain;
900 uint32_t flags = 0;
901 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
902
903 if (pAllocateInfo->allocationSize == 0) {
904 /* Apparently, this is allowed */
905 *pMem = VK_NULL_HANDLE;
906 return VK_SUCCESS;
907 }
908
909 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
910 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
911 if (mem == NULL)
912 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
913
914 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
915 if (pAllocateInfo->memoryTypeIndex == 1 || pAllocateInfo->memoryTypeIndex == 3)
916 domain = RADEON_DOMAIN_GTT;
917 else
918 domain = RADEON_DOMAIN_VRAM;
919
920 if (pAllocateInfo->memoryTypeIndex == 0)
921 flags |= RADEON_FLAG_NO_CPU_ACCESS;
922 else
923 flags |= RADEON_FLAG_CPU_ACCESS;
924
925 if (pAllocateInfo->memoryTypeIndex == 1)
926 flags |= RADEON_FLAG_GTT_WC;
927
928 mem->bo = device->ws->buffer_create(device->ws, alloc_size, 32768,
929 domain, flags);
930
931 if (!mem->bo) {
932 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
933 goto fail;
934 }
935 mem->type_index = pAllocateInfo->memoryTypeIndex;
936
937 *pMem = radv_device_memory_to_handle(mem);
938
939 return VK_SUCCESS;
940
941 fail:
942 vk_free2(&device->alloc, pAllocator, mem);
943
944 return result;
945 }
946
947 void radv_FreeMemory(
948 VkDevice _device,
949 VkDeviceMemory _mem,
950 const VkAllocationCallbacks* pAllocator)
951 {
952 RADV_FROM_HANDLE(radv_device, device, _device);
953 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
954
955 if (mem == NULL)
956 return;
957
958 device->ws->buffer_destroy(mem->bo);
959 mem->bo = NULL;
960
961 vk_free2(&device->alloc, pAllocator, mem);
962 }
963
964 VkResult radv_MapMemory(
965 VkDevice _device,
966 VkDeviceMemory _memory,
967 VkDeviceSize offset,
968 VkDeviceSize size,
969 VkMemoryMapFlags flags,
970 void** ppData)
971 {
972 RADV_FROM_HANDLE(radv_device, device, _device);
973 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
974
975 if (mem == NULL) {
976 *ppData = NULL;
977 return VK_SUCCESS;
978 }
979
980 *ppData = device->ws->buffer_map(mem->bo);
981 if (*ppData) {
982 *ppData += offset;
983 return VK_SUCCESS;
984 }
985
986 return VK_ERROR_MEMORY_MAP_FAILED;
987 }
988
989 void radv_UnmapMemory(
990 VkDevice _device,
991 VkDeviceMemory _memory)
992 {
993 RADV_FROM_HANDLE(radv_device, device, _device);
994 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
995
996 if (mem == NULL)
997 return;
998
999 device->ws->buffer_unmap(mem->bo);
1000 }
1001
1002 VkResult radv_FlushMappedMemoryRanges(
1003 VkDevice _device,
1004 uint32_t memoryRangeCount,
1005 const VkMappedMemoryRange* pMemoryRanges)
1006 {
1007 return VK_SUCCESS;
1008 }
1009
1010 VkResult radv_InvalidateMappedMemoryRanges(
1011 VkDevice _device,
1012 uint32_t memoryRangeCount,
1013 const VkMappedMemoryRange* pMemoryRanges)
1014 {
1015 return VK_SUCCESS;
1016 }
1017
1018 void radv_GetBufferMemoryRequirements(
1019 VkDevice device,
1020 VkBuffer _buffer,
1021 VkMemoryRequirements* pMemoryRequirements)
1022 {
1023 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1024
1025 /* The Vulkan spec (git aaed022) says:
1026 *
1027 * memoryTypeBits is a bitfield and contains one bit set for every
1028 * supported memory type for the resource. The bit `1<<i` is set if and
1029 * only if the memory type `i` in the VkPhysicalDeviceMemoryProperties
1030 * structure for the physical device is supported.
1031 *
1032 * We support exactly one memory type.
1033 */
1034 pMemoryRequirements->memoryTypeBits = 0x7;
1035
1036 pMemoryRequirements->size = buffer->size;
1037 pMemoryRequirements->alignment = 16;
1038 }
1039
1040 void radv_GetImageMemoryRequirements(
1041 VkDevice device,
1042 VkImage _image,
1043 VkMemoryRequirements* pMemoryRequirements)
1044 {
1045 RADV_FROM_HANDLE(radv_image, image, _image);
1046
1047 /* The Vulkan spec (git aaed022) says:
1048 *
1049 * memoryTypeBits is a bitfield and contains one bit set for every
1050 * supported memory type for the resource. The bit `1<<i` is set if and
1051 * only if the memory type `i` in the VkPhysicalDeviceMemoryProperties
1052 * structure for the physical device is supported.
1053 *
1054 * We support exactly one memory type.
1055 */
1056 pMemoryRequirements->memoryTypeBits = 0x7;
1057
1058 pMemoryRequirements->size = image->size;
1059 pMemoryRequirements->alignment = image->alignment;
1060 }
1061
1062 void radv_GetImageSparseMemoryRequirements(
1063 VkDevice device,
1064 VkImage image,
1065 uint32_t* pSparseMemoryRequirementCount,
1066 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
1067 {
1068 stub();
1069 }
1070
1071 void radv_GetDeviceMemoryCommitment(
1072 VkDevice device,
1073 VkDeviceMemory memory,
1074 VkDeviceSize* pCommittedMemoryInBytes)
1075 {
1076 *pCommittedMemoryInBytes = 0;
1077 }
1078
1079 VkResult radv_BindBufferMemory(
1080 VkDevice device,
1081 VkBuffer _buffer,
1082 VkDeviceMemory _memory,
1083 VkDeviceSize memoryOffset)
1084 {
1085 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1086 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1087
1088 if (mem) {
1089 buffer->bo = mem->bo;
1090 buffer->offset = memoryOffset;
1091 } else {
1092 buffer->bo = NULL;
1093 buffer->offset = 0;
1094 }
1095
1096 return VK_SUCCESS;
1097 }
1098
1099 VkResult radv_BindImageMemory(
1100 VkDevice device,
1101 VkImage _image,
1102 VkDeviceMemory _memory,
1103 VkDeviceSize memoryOffset)
1104 {
1105 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1106 RADV_FROM_HANDLE(radv_image, image, _image);
1107
1108 if (mem) {
1109 image->bo = mem->bo;
1110 image->offset = memoryOffset;
1111 } else {
1112 image->bo = NULL;
1113 image->offset = 0;
1114 }
1115
1116 return VK_SUCCESS;
1117 }
1118
1119 VkResult radv_QueueBindSparse(
1120 VkQueue queue,
1121 uint32_t bindInfoCount,
1122 const VkBindSparseInfo* pBindInfo,
1123 VkFence fence)
1124 {
1125 stub_return(VK_ERROR_INCOMPATIBLE_DRIVER);
1126 }
1127
1128 VkResult radv_CreateFence(
1129 VkDevice _device,
1130 const VkFenceCreateInfo* pCreateInfo,
1131 const VkAllocationCallbacks* pAllocator,
1132 VkFence* pFence)
1133 {
1134 RADV_FROM_HANDLE(radv_device, device, _device);
1135 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
1136 sizeof(*fence), 8,
1137 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1138
1139 if (!fence)
1140 return VK_ERROR_OUT_OF_HOST_MEMORY;
1141
1142 memset(fence, 0, sizeof(*fence));
1143 fence->submitted = false;
1144 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
1145 fence->fence = device->ws->create_fence();
1146
1147
1148 *pFence = radv_fence_to_handle(fence);
1149
1150 return VK_SUCCESS;
1151 }
1152
1153 void radv_DestroyFence(
1154 VkDevice _device,
1155 VkFence _fence,
1156 const VkAllocationCallbacks* pAllocator)
1157 {
1158 RADV_FROM_HANDLE(radv_device, device, _device);
1159 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1160
1161 if (!fence)
1162 return;
1163 device->ws->destroy_fence(fence->fence);
1164 vk_free2(&device->alloc, pAllocator, fence);
1165 }
1166
1167 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
1168 {
1169 uint64_t current_time;
1170 struct timespec tv;
1171
1172 clock_gettime(CLOCK_MONOTONIC, &tv);
1173 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
1174
1175 timeout = MIN2(UINT64_MAX - current_time, timeout);
1176
1177 return current_time + timeout;
1178 }
1179
1180 VkResult radv_WaitForFences(
1181 VkDevice _device,
1182 uint32_t fenceCount,
1183 const VkFence* pFences,
1184 VkBool32 waitAll,
1185 uint64_t timeout)
1186 {
1187 RADV_FROM_HANDLE(radv_device, device, _device);
1188 timeout = radv_get_absolute_timeout(timeout);
1189
1190 if (!waitAll && fenceCount > 1) {
1191 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
1192 }
1193
1194 for (uint32_t i = 0; i < fenceCount; ++i) {
1195 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1196 bool expired = false;
1197
1198 if (fence->signalled)
1199 continue;
1200
1201 if (!fence->submitted)
1202 return VK_TIMEOUT;
1203
1204 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
1205 if (!expired)
1206 return VK_TIMEOUT;
1207
1208 fence->signalled = true;
1209 }
1210
1211 return VK_SUCCESS;
1212 }
1213
1214 VkResult radv_ResetFences(VkDevice device,
1215 uint32_t fenceCount,
1216 const VkFence *pFences)
1217 {
1218 for (unsigned i = 0; i < fenceCount; ++i) {
1219 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1220 fence->submitted = fence->signalled = false;
1221 }
1222
1223 return VK_SUCCESS;
1224 }
1225
1226 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
1227 {
1228 RADV_FROM_HANDLE(radv_device, device, _device);
1229 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1230
1231 if (fence->signalled)
1232 return VK_SUCCESS;
1233 if (!fence->submitted)
1234 return VK_NOT_READY;
1235
1236 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
1237 return VK_NOT_READY;
1238
1239 return VK_SUCCESS;
1240 }
1241
1242
1243 // Queue semaphore functions
1244
1245 VkResult radv_CreateSemaphore(
1246 VkDevice device,
1247 const VkSemaphoreCreateInfo* pCreateInfo,
1248 const VkAllocationCallbacks* pAllocator,
1249 VkSemaphore* pSemaphore)
1250 {
1251 /* The DRM execbuffer ioctl always execute in-oder, even between different
1252 * rings. As such, there's nothing to do for the user space semaphore.
1253 */
1254
1255 *pSemaphore = (VkSemaphore)1;
1256
1257 return VK_SUCCESS;
1258 }
1259
1260 void radv_DestroySemaphore(
1261 VkDevice device,
1262 VkSemaphore semaphore,
1263 const VkAllocationCallbacks* pAllocator)
1264 {
1265 }
1266
1267 VkResult radv_CreateEvent(
1268 VkDevice _device,
1269 const VkEventCreateInfo* pCreateInfo,
1270 const VkAllocationCallbacks* pAllocator,
1271 VkEvent* pEvent)
1272 {
1273 RADV_FROM_HANDLE(radv_device, device, _device);
1274 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
1275 sizeof(*event), 8,
1276 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1277
1278 if (!event)
1279 return VK_ERROR_OUT_OF_HOST_MEMORY;
1280
1281 event->bo = device->ws->buffer_create(device->ws, 8, 8,
1282 RADEON_DOMAIN_GTT,
1283 RADEON_FLAG_CPU_ACCESS);
1284 if (!event->bo) {
1285 vk_free2(&device->alloc, pAllocator, event);
1286 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1287 }
1288
1289 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
1290
1291 *pEvent = radv_event_to_handle(event);
1292
1293 return VK_SUCCESS;
1294 }
1295
1296 void radv_DestroyEvent(
1297 VkDevice _device,
1298 VkEvent _event,
1299 const VkAllocationCallbacks* pAllocator)
1300 {
1301 RADV_FROM_HANDLE(radv_device, device, _device);
1302 RADV_FROM_HANDLE(radv_event, event, _event);
1303
1304 if (!event)
1305 return;
1306 device->ws->buffer_destroy(event->bo);
1307 vk_free2(&device->alloc, pAllocator, event);
1308 }
1309
1310 VkResult radv_GetEventStatus(
1311 VkDevice _device,
1312 VkEvent _event)
1313 {
1314 RADV_FROM_HANDLE(radv_event, event, _event);
1315
1316 if (*event->map == 1)
1317 return VK_EVENT_SET;
1318 return VK_EVENT_RESET;
1319 }
1320
1321 VkResult radv_SetEvent(
1322 VkDevice _device,
1323 VkEvent _event)
1324 {
1325 RADV_FROM_HANDLE(radv_event, event, _event);
1326 *event->map = 1;
1327
1328 return VK_SUCCESS;
1329 }
1330
1331 VkResult radv_ResetEvent(
1332 VkDevice _device,
1333 VkEvent _event)
1334 {
1335 RADV_FROM_HANDLE(radv_event, event, _event);
1336 *event->map = 0;
1337
1338 return VK_SUCCESS;
1339 }
1340
1341 VkResult radv_CreateBuffer(
1342 VkDevice _device,
1343 const VkBufferCreateInfo* pCreateInfo,
1344 const VkAllocationCallbacks* pAllocator,
1345 VkBuffer* pBuffer)
1346 {
1347 RADV_FROM_HANDLE(radv_device, device, _device);
1348 struct radv_buffer *buffer;
1349
1350 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
1351
1352 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
1353 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1354 if (buffer == NULL)
1355 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1356
1357 buffer->size = pCreateInfo->size;
1358 buffer->usage = pCreateInfo->usage;
1359 buffer->bo = NULL;
1360 buffer->offset = 0;
1361
1362 *pBuffer = radv_buffer_to_handle(buffer);
1363
1364 return VK_SUCCESS;
1365 }
1366
1367 void radv_DestroyBuffer(
1368 VkDevice _device,
1369 VkBuffer _buffer,
1370 const VkAllocationCallbacks* pAllocator)
1371 {
1372 RADV_FROM_HANDLE(radv_device, device, _device);
1373 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1374
1375 if (!buffer)
1376 return;
1377
1378 vk_free2(&device->alloc, pAllocator, buffer);
1379 }
1380
1381 static inline unsigned
1382 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
1383 {
1384 if (stencil)
1385 return image->surface.stencil_tiling_index[level];
1386 else
1387 return image->surface.tiling_index[level];
1388 }
1389
1390 static void
1391 radv_initialise_color_surface(struct radv_device *device,
1392 struct radv_color_buffer_info *cb,
1393 struct radv_image_view *iview)
1394 {
1395 const struct vk_format_description *desc;
1396 unsigned ntype, format, swap, endian;
1397 unsigned blend_clamp = 0, blend_bypass = 0;
1398 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
1399 uint64_t va;
1400 const struct radeon_surf *surf = &iview->image->surface;
1401 const struct radeon_surf_level *level_info = &surf->level[iview->base_mip];
1402
1403 desc = vk_format_description(iview->vk_format);
1404
1405 memset(cb, 0, sizeof(*cb));
1406
1407 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1408 va += level_info->offset;
1409 cb->cb_color_base = va >> 8;
1410
1411 /* CMASK variables */
1412 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1413 va += iview->image->cmask.offset;
1414 cb->cb_color_cmask = va >> 8;
1415 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
1416
1417 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1418 va += iview->image->dcc_offset;
1419 cb->cb_dcc_base = va >> 8;
1420
1421 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
1422 S_028C6C_SLICE_MAX(iview->base_layer + iview->extent.depth - 1);
1423
1424 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
1425 pitch_tile_max = level_info->nblk_x / 8 - 1;
1426 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
1427 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
1428
1429 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
1430 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
1431
1432 /* Intensity is implemented as Red, so treat it that way. */
1433 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1) |
1434 S_028C74_TILE_MODE_INDEX(tile_mode_index);
1435
1436 if (iview->image->samples > 1) {
1437 unsigned log_samples = util_logbase2(iview->image->samples);
1438
1439 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1440 S_028C74_NUM_FRAGMENTS(log_samples);
1441 }
1442
1443 if (iview->image->fmask.size) {
1444 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
1445 if (device->instance->physicalDevice.rad_info.chip_class >= CIK)
1446 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
1447 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
1448 cb->cb_color_fmask = va >> 8;
1449 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
1450 } else {
1451 /* This must be set for fast clear to work without FMASK. */
1452 if (device->instance->physicalDevice.rad_info.chip_class >= CIK)
1453 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
1454 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
1455 cb->cb_color_fmask = cb->cb_color_base;
1456 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
1457 }
1458
1459 ntype = radv_translate_color_numformat(iview->vk_format,
1460 desc,
1461 vk_format_get_first_non_void_channel(iview->vk_format));
1462 format = radv_translate_colorformat(iview->vk_format);
1463 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
1464 radv_finishme("Illegal color\n");
1465 swap = radv_translate_colorswap(iview->vk_format, FALSE);
1466 endian = radv_colorformat_endian_swap(format);
1467
1468 /* blend clamp should be set for all NORM/SRGB types */
1469 if (ntype == V_028C70_NUMBER_UNORM ||
1470 ntype == V_028C70_NUMBER_SNORM ||
1471 ntype == V_028C70_NUMBER_SRGB)
1472 blend_clamp = 1;
1473
1474 /* set blend bypass according to docs if SINT/UINT or
1475 8/24 COLOR variants */
1476 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1477 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1478 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1479 blend_clamp = 0;
1480 blend_bypass = 1;
1481 }
1482 #if 0
1483 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
1484 (format == V_028C70_COLOR_8 ||
1485 format == V_028C70_COLOR_8_8 ||
1486 format == V_028C70_COLOR_8_8_8_8))
1487 ->color_is_int8 = true;
1488 #endif
1489 cb->cb_color_info = S_028C70_FORMAT(format) |
1490 S_028C70_COMP_SWAP(swap) |
1491 S_028C70_BLEND_CLAMP(blend_clamp) |
1492 S_028C70_BLEND_BYPASS(blend_bypass) |
1493 S_028C70_SIMPLE_FLOAT(1) |
1494 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
1495 ntype != V_028C70_NUMBER_SNORM &&
1496 ntype != V_028C70_NUMBER_SRGB &&
1497 format != V_028C70_COLOR_8_24 &&
1498 format != V_028C70_COLOR_24_8) |
1499 S_028C70_NUMBER_TYPE(ntype) |
1500 S_028C70_ENDIAN(endian);
1501 if (iview->image->samples > 1)
1502 if (iview->image->fmask.size)
1503 cb->cb_color_info |= S_028C70_COMPRESSION(1);
1504
1505 if (iview->image->cmask.size && device->allow_fast_clears)
1506 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
1507
1508 if (iview->image->surface.dcc_size && level_info->dcc_enabled)
1509 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
1510
1511 if (device->instance->physicalDevice.rad_info.chip_class >= VI) {
1512 unsigned max_uncompressed_block_size = 2;
1513 if (iview->image->samples > 1) {
1514 if (iview->image->surface.bpe == 1)
1515 max_uncompressed_block_size = 0;
1516 else if (iview->image->surface.bpe == 2)
1517 max_uncompressed_block_size = 1;
1518 }
1519
1520 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
1521 S_028C78_INDEPENDENT_64B_BLOCKS(1);
1522 }
1523
1524 /* This must be set for fast clear to work without FMASK. */
1525 if (!iview->image->fmask.size &&
1526 device->instance->physicalDevice.rad_info.chip_class == SI) {
1527 unsigned bankh = util_logbase2(iview->image->surface.bankh);
1528 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
1529 }
1530 }
1531
1532 static void
1533 radv_initialise_ds_surface(struct radv_device *device,
1534 struct radv_ds_buffer_info *ds,
1535 struct radv_image_view *iview)
1536 {
1537 unsigned level = iview->base_mip;
1538 unsigned format;
1539 uint64_t va, s_offs, z_offs;
1540 const struct radeon_surf_level *level_info = &iview->image->surface.level[level];
1541 memset(ds, 0, sizeof(*ds));
1542 switch (iview->vk_format) {
1543 case VK_FORMAT_D24_UNORM_S8_UINT:
1544 case VK_FORMAT_X8_D24_UNORM_PACK32:
1545 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1546 ds->offset_scale = 2.0f;
1547 break;
1548 case VK_FORMAT_D16_UNORM:
1549 case VK_FORMAT_D16_UNORM_S8_UINT:
1550 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1551 ds->offset_scale = 4.0f;
1552 break;
1553 case VK_FORMAT_D32_SFLOAT:
1554 case VK_FORMAT_D32_SFLOAT_S8_UINT:
1555 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1556 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1557 ds->offset_scale = 1.0f;
1558 break;
1559 default:
1560 break;
1561 }
1562
1563 format = radv_translate_dbformat(iview->vk_format);
1564 if (format == V_028040_Z_INVALID) {
1565 fprintf(stderr, "Invalid DB format: %d, disabling DB.\n", iview->vk_format);
1566 }
1567
1568 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1569 s_offs = z_offs = va;
1570 z_offs += iview->image->surface.level[level].offset;
1571 s_offs += iview->image->surface.stencil_level[level].offset;
1572
1573 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
1574 S_028008_SLICE_MAX(iview->base_layer + iview->extent.depth - 1);
1575 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1576 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
1577
1578 if (iview->image->samples > 1)
1579 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->samples));
1580
1581 if (iview->image->surface.flags & RADEON_SURF_SBUFFER)
1582 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8);
1583 else
1584 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1585
1586 if (device->instance->physicalDevice.rad_info.chip_class >= CIK) {
1587 struct radeon_info *info = &device->instance->physicalDevice.rad_info;
1588 unsigned tiling_index = iview->image->surface.tiling_index[level];
1589 unsigned stencil_index = iview->image->surface.stencil_tiling_index[level];
1590 unsigned macro_index = iview->image->surface.macro_tile_index;
1591 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
1592 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
1593 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
1594
1595 ds->db_depth_info |=
1596 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
1597 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
1598 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
1599 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
1600 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
1601 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
1602 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
1603 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
1604 } else {
1605 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
1606 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1607 tile_mode_index = si_tile_mode_index(iview->image, level, true);
1608 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1609 }
1610
1611 if (iview->image->htile.size && !level) {
1612 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
1613 S_028040_ALLOW_EXPCLEAR(1);
1614
1615 if (iview->image->surface.flags & RADEON_SURF_SBUFFER) {
1616 /* Workaround: For a not yet understood reason, the
1617 * combination of MSAA, fast stencil clear and stencil
1618 * decompress messes with subsequent stencil buffer
1619 * uses. Problem was reproduced on Verde, Bonaire,
1620 * Tonga, and Carrizo.
1621 *
1622 * Disabling EXPCLEAR works around the problem.
1623 *
1624 * Check piglit's arb_texture_multisample-stencil-clear
1625 * test if you want to try changing this.
1626 */
1627 if (iview->image->samples <= 1)
1628 ds->db_stencil_info |= S_028044_ALLOW_EXPCLEAR(1);
1629 } else
1630 /* Use all of the htile_buffer for depth if there's no stencil. */
1631 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1632
1633 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
1634 iview->image->htile.offset;
1635 ds->db_htile_data_base = va >> 8;
1636 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
1637 } else {
1638 ds->db_htile_data_base = 0;
1639 ds->db_htile_surface = 0;
1640 }
1641
1642 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
1643 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
1644
1645 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
1646 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
1647 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
1648 }
1649
1650 VkResult radv_CreateFramebuffer(
1651 VkDevice _device,
1652 const VkFramebufferCreateInfo* pCreateInfo,
1653 const VkAllocationCallbacks* pAllocator,
1654 VkFramebuffer* pFramebuffer)
1655 {
1656 RADV_FROM_HANDLE(radv_device, device, _device);
1657 struct radv_framebuffer *framebuffer;
1658
1659 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
1660
1661 size_t size = sizeof(*framebuffer) +
1662 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
1663 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
1664 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1665 if (framebuffer == NULL)
1666 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1667
1668 framebuffer->attachment_count = pCreateInfo->attachmentCount;
1669 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
1670 VkImageView _iview = pCreateInfo->pAttachments[i];
1671 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
1672 framebuffer->attachments[i].attachment = iview;
1673 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
1674 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
1675 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
1676 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
1677 }
1678 }
1679
1680 framebuffer->width = pCreateInfo->width;
1681 framebuffer->height = pCreateInfo->height;
1682 framebuffer->layers = pCreateInfo->layers;
1683
1684 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
1685 return VK_SUCCESS;
1686 }
1687
1688 void radv_DestroyFramebuffer(
1689 VkDevice _device,
1690 VkFramebuffer _fb,
1691 const VkAllocationCallbacks* pAllocator)
1692 {
1693 RADV_FROM_HANDLE(radv_device, device, _device);
1694 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
1695
1696 if (!fb)
1697 return;
1698 vk_free2(&device->alloc, pAllocator, fb);
1699 }
1700
1701 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
1702 {
1703 switch (address_mode) {
1704 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
1705 return V_008F30_SQ_TEX_WRAP;
1706 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
1707 return V_008F30_SQ_TEX_MIRROR;
1708 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
1709 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1710 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
1711 return V_008F30_SQ_TEX_CLAMP_BORDER;
1712 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
1713 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1714 default:
1715 unreachable("illegal tex wrap mode");
1716 break;
1717 }
1718 }
1719
1720 static unsigned
1721 radv_tex_compare(VkCompareOp op)
1722 {
1723 switch (op) {
1724 case VK_COMPARE_OP_NEVER:
1725 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1726 case VK_COMPARE_OP_LESS:
1727 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1728 case VK_COMPARE_OP_EQUAL:
1729 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1730 case VK_COMPARE_OP_LESS_OR_EQUAL:
1731 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1732 case VK_COMPARE_OP_GREATER:
1733 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1734 case VK_COMPARE_OP_NOT_EQUAL:
1735 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1736 case VK_COMPARE_OP_GREATER_OR_EQUAL:
1737 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1738 case VK_COMPARE_OP_ALWAYS:
1739 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1740 default:
1741 unreachable("illegal compare mode");
1742 break;
1743 }
1744 }
1745
1746 static unsigned
1747 radv_tex_filter(VkFilter filter, unsigned max_ansio)
1748 {
1749 switch (filter) {
1750 case VK_FILTER_NEAREST:
1751 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
1752 V_008F38_SQ_TEX_XY_FILTER_POINT);
1753 case VK_FILTER_LINEAR:
1754 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
1755 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
1756 case VK_FILTER_CUBIC_IMG:
1757 default:
1758 fprintf(stderr, "illegal texture filter");
1759 return 0;
1760 }
1761 }
1762
1763 static unsigned
1764 radv_tex_mipfilter(VkSamplerMipmapMode mode)
1765 {
1766 switch (mode) {
1767 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
1768 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1769 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
1770 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1771 default:
1772 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1773 }
1774 }
1775
1776 static unsigned
1777 radv_tex_bordercolor(VkBorderColor bcolor)
1778 {
1779 switch (bcolor) {
1780 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
1781 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
1782 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
1783 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
1784 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
1785 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
1786 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
1787 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
1788 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
1789 default:
1790 break;
1791 }
1792 return 0;
1793 }
1794
1795 static unsigned
1796 radv_tex_aniso_filter(unsigned filter)
1797 {
1798 if (filter < 2)
1799 return 0;
1800 if (filter < 4)
1801 return 1;
1802 if (filter < 8)
1803 return 2;
1804 if (filter < 16)
1805 return 3;
1806 return 4;
1807 }
1808
1809 static void
1810 radv_init_sampler(struct radv_device *device,
1811 struct radv_sampler *sampler,
1812 const VkSamplerCreateInfo *pCreateInfo)
1813 {
1814 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
1815 (uint32_t) pCreateInfo->maxAnisotropy : 0;
1816 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
1817 bool is_vi = (device->instance->physicalDevice.rad_info.chip_class >= VI);
1818
1819 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
1820 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
1821 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
1822 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
1823 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
1824 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
1825 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
1826 S_008F30_ANISO_BIAS(max_aniso_ratio) |
1827 S_008F30_DISABLE_CUBE_WRAP(0) |
1828 S_008F30_COMPAT_MODE(is_vi));
1829 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
1830 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
1831 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
1832 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
1833 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
1834 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
1835 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
1836 S_008F38_MIP_POINT_PRECLAMP(1) |
1837 S_008F38_DISABLE_LSB_CEIL(1) |
1838 S_008F38_FILTER_PREC_FIX(1) |
1839 S_008F38_ANISO_OVERRIDE(is_vi));
1840 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
1841 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
1842 }
1843
1844 VkResult radv_CreateSampler(
1845 VkDevice _device,
1846 const VkSamplerCreateInfo* pCreateInfo,
1847 const VkAllocationCallbacks* pAllocator,
1848 VkSampler* pSampler)
1849 {
1850 RADV_FROM_HANDLE(radv_device, device, _device);
1851 struct radv_sampler *sampler;
1852
1853 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
1854
1855 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
1856 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1857 if (!sampler)
1858 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1859
1860 radv_init_sampler(device, sampler, pCreateInfo);
1861 *pSampler = radv_sampler_to_handle(sampler);
1862
1863 return VK_SUCCESS;
1864 }
1865
1866 void radv_DestroySampler(
1867 VkDevice _device,
1868 VkSampler _sampler,
1869 const VkAllocationCallbacks* pAllocator)
1870 {
1871 RADV_FROM_HANDLE(radv_device, device, _device);
1872 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
1873
1874 if (!sampler)
1875 return;
1876 vk_free2(&device->alloc, pAllocator, sampler);
1877 }