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radv: add radv_dump_pipeline_state() helper
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "gfx9d.h"
47 #include "addrlib/gfx9/chip/gfx9_enum.h"
48 #include "util/debug.h"
49
50 static int
51 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
52 {
53 uint32_t mesa_timestamp, llvm_timestamp;
54 uint16_t f = family;
55 memset(uuid, 0, VK_UUID_SIZE);
56 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
57 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
58 return -1;
59
60 memcpy(uuid, &mesa_timestamp, 4);
61 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
62 memcpy((char*)uuid + 8, &f, 2);
63 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
64 return 0;
65 }
66
67 static void
68 radv_get_driver_uuid(void *uuid)
69 {
70 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
71 }
72
73 static void
74 radv_get_device_uuid(struct radeon_info *info, void *uuid)
75 {
76 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
77 }
78
79 static void
80 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
81 {
82 const char *chip_string;
83 char llvm_string[32] = {};
84
85 switch (family) {
86 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
87 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
88 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
89 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
90 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
91 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
92 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
93 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
94 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
95 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
96 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
97 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
98 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
99 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
100 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
101 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
102 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
103 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
104 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
105 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
106 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
107 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
108 default: chip_string = "AMD RADV unknown"; break;
109 }
110
111 snprintf(llvm_string, sizeof(llvm_string),
112 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
113 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
114 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
115 }
116
117 static void
118 radv_physical_device_init_mem_types(struct radv_physical_device *device)
119 {
120 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
121 uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
122 device->rad_info.vram_vis_size);
123
124 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
125 device->memory_properties.memoryHeapCount = 0;
126 if (device->rad_info.vram_size - visible_vram_size > 0) {
127 vram_index = device->memory_properties.memoryHeapCount++;
128 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
129 .size = device->rad_info.vram_size - visible_vram_size,
130 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
131 };
132 }
133 if (visible_vram_size) {
134 visible_vram_index = device->memory_properties.memoryHeapCount++;
135 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
136 .size = visible_vram_size,
137 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
138 };
139 }
140 if (device->rad_info.gart_size > 0) {
141 gart_index = device->memory_properties.memoryHeapCount++;
142 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
143 .size = device->rad_info.gart_size,
144 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
145 };
146 }
147
148 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
149 unsigned type_count = 0;
150 if (vram_index >= 0) {
151 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
152 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
153 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
154 .heapIndex = vram_index,
155 };
156 }
157 if (gart_index >= 0) {
158 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
159 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
160 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
161 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
162 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
163 .heapIndex = gart_index,
164 };
165 }
166 if (visible_vram_index >= 0) {
167 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
168 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
169 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
170 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
171 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
172 .heapIndex = visible_vram_index,
173 };
174 }
175 if (gart_index >= 0) {
176 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
177 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
178 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
179 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
180 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
181 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
182 .heapIndex = gart_index,
183 };
184 }
185 device->memory_properties.memoryTypeCount = type_count;
186 }
187
188 static void
189 radv_handle_env_var_force_family(struct radv_physical_device *device)
190 {
191 const char *family = getenv("RADV_FORCE_FAMILY");
192 unsigned i;
193
194 if (!family)
195 return;
196
197 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
198 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
199 /* Override family and chip_class. */
200 device->rad_info.family = i;
201
202 if (i >= CHIP_VEGA10)
203 device->rad_info.chip_class = GFX9;
204 else if (i >= CHIP_TONGA)
205 device->rad_info.chip_class = VI;
206 else if (i >= CHIP_BONAIRE)
207 device->rad_info.chip_class = CIK;
208 else
209 device->rad_info.chip_class = SI;
210
211 return;
212 }
213 }
214
215 fprintf(stderr, "radv: Unknown family: %s\n", family);
216 exit(1);
217 }
218
219 static VkResult
220 radv_physical_device_init(struct radv_physical_device *device,
221 struct radv_instance *instance,
222 drmDevicePtr drm_device)
223 {
224 const char *path = drm_device->nodes[DRM_NODE_RENDER];
225 VkResult result;
226 drmVersionPtr version;
227 int fd;
228
229 fd = open(path, O_RDWR | O_CLOEXEC);
230 if (fd < 0)
231 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
232
233 version = drmGetVersion(fd);
234 if (!version) {
235 close(fd);
236 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
237 "failed to get version %s: %m", path);
238 }
239
240 if (strcmp(version->name, "amdgpu")) {
241 drmFreeVersion(version);
242 close(fd);
243 return VK_ERROR_INCOMPATIBLE_DRIVER;
244 }
245 drmFreeVersion(version);
246
247 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
248 device->instance = instance;
249 assert(strlen(path) < ARRAY_SIZE(device->path));
250 strncpy(device->path, path, ARRAY_SIZE(device->path));
251
252 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
253 instance->perftest_flags);
254 if (!device->ws) {
255 result = VK_ERROR_INCOMPATIBLE_DRIVER;
256 goto fail;
257 }
258
259 device->local_fd = fd;
260 device->ws->query_info(device->ws, &device->rad_info);
261
262 radv_handle_env_var_force_family(device);
263
264 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
265
266 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
267 device->ws->destroy(device->ws);
268 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
269 "cannot generate UUID");
270 goto fail;
271 }
272
273 /* These flags affect shader compilation. */
274 uint64_t shader_env_flags =
275 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
276 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
277
278 /* The gpu id is already embedded in the uuid so we just pass "radv"
279 * when creating the cache.
280 */
281 char buf[VK_UUID_SIZE * 2 + 1];
282 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
283 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
284
285 if (device->rad_info.chip_class < VI ||
286 device->rad_info.chip_class > GFX9)
287 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
288
289 radv_get_driver_uuid(&device->device_uuid);
290 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
291
292 if (device->rad_info.family == CHIP_STONEY ||
293 device->rad_info.chip_class >= GFX9) {
294 device->has_rbplus = true;
295 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
296 device->rad_info.family == CHIP_VEGA12 ||
297 device->rad_info.family == CHIP_RAVEN;
298 }
299
300 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
301 * on SI.
302 */
303 device->has_clear_state = device->rad_info.chip_class >= CIK;
304
305 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
306
307 /* Vega10/Raven need a special workaround for a hardware bug. */
308 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
309 device->rad_info.family == CHIP_RAVEN;
310
311 /* Out-of-order primitive rasterization. */
312 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
313 device->rad_info.max_se >= 2;
314 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
315 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
316
317 device->dcc_msaa_allowed = device->rad_info.chip_class == VI &&
318 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
319
320 radv_physical_device_init_mem_types(device);
321 radv_fill_device_extension_table(device, &device->supported_extensions);
322
323 result = radv_init_wsi(device);
324 if (result != VK_SUCCESS) {
325 device->ws->destroy(device->ws);
326 goto fail;
327 }
328
329 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
330 ac_print_gpu_info(&device->rad_info);
331
332 return VK_SUCCESS;
333
334 fail:
335 close(fd);
336 return result;
337 }
338
339 static void
340 radv_physical_device_finish(struct radv_physical_device *device)
341 {
342 radv_finish_wsi(device);
343 device->ws->destroy(device->ws);
344 disk_cache_destroy(device->disk_cache);
345 close(device->local_fd);
346 }
347
348 static void *
349 default_alloc_func(void *pUserData, size_t size, size_t align,
350 VkSystemAllocationScope allocationScope)
351 {
352 return malloc(size);
353 }
354
355 static void *
356 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
357 size_t align, VkSystemAllocationScope allocationScope)
358 {
359 return realloc(pOriginal, size);
360 }
361
362 static void
363 default_free_func(void *pUserData, void *pMemory)
364 {
365 free(pMemory);
366 }
367
368 static const VkAllocationCallbacks default_alloc = {
369 .pUserData = NULL,
370 .pfnAllocation = default_alloc_func,
371 .pfnReallocation = default_realloc_func,
372 .pfnFree = default_free_func,
373 };
374
375 static const struct debug_control radv_debug_options[] = {
376 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
377 {"nodcc", RADV_DEBUG_NO_DCC},
378 {"shaders", RADV_DEBUG_DUMP_SHADERS},
379 {"nocache", RADV_DEBUG_NO_CACHE},
380 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
381 {"nohiz", RADV_DEBUG_NO_HIZ},
382 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
383 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
384 {"allbos", RADV_DEBUG_ALL_BOS},
385 {"noibs", RADV_DEBUG_NO_IBS},
386 {"spirv", RADV_DEBUG_DUMP_SPIRV},
387 {"vmfaults", RADV_DEBUG_VM_FAULTS},
388 {"zerovram", RADV_DEBUG_ZERO_VRAM},
389 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
390 {"nosisched", RADV_DEBUG_NO_SISCHED},
391 {"preoptir", RADV_DEBUG_PREOPTIR},
392 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
393 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
394 {"info", RADV_DEBUG_INFO},
395 {NULL, 0}
396 };
397
398 const char *
399 radv_get_debug_option_name(int id)
400 {
401 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
402 return radv_debug_options[id].string;
403 }
404
405 static const struct debug_control radv_perftest_options[] = {
406 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
407 {"sisched", RADV_PERFTEST_SISCHED},
408 {"localbos", RADV_PERFTEST_LOCAL_BOS},
409 {"binning", RADV_PERFTEST_BINNING},
410 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
411 {NULL, 0}
412 };
413
414 const char *
415 radv_get_perftest_option_name(int id)
416 {
417 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
418 return radv_perftest_options[id].string;
419 }
420
421 static void
422 radv_handle_per_app_options(struct radv_instance *instance,
423 const VkApplicationInfo *info)
424 {
425 const char *name = info ? info->pApplicationName : NULL;
426
427 if (!name)
428 return;
429
430 if (!strcmp(name, "Talos - Linux - 32bit") ||
431 !strcmp(name, "Talos - Linux - 64bit")) {
432 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
433 /* Force enable LLVM sisched for Talos because it looks
434 * safe and it gives few more FPS.
435 */
436 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
437 }
438 }
439 }
440
441 static int radv_get_instance_extension_index(const char *name)
442 {
443 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
444 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
445 return i;
446 }
447 return -1;
448 }
449
450
451 VkResult radv_CreateInstance(
452 const VkInstanceCreateInfo* pCreateInfo,
453 const VkAllocationCallbacks* pAllocator,
454 VkInstance* pInstance)
455 {
456 struct radv_instance *instance;
457 VkResult result;
458
459 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
460
461 uint32_t client_version;
462 if (pCreateInfo->pApplicationInfo &&
463 pCreateInfo->pApplicationInfo->apiVersion != 0) {
464 client_version = pCreateInfo->pApplicationInfo->apiVersion;
465 } else {
466 radv_EnumerateInstanceVersion(&client_version);
467 }
468
469 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
470 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
471 if (!instance)
472 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
473
474 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
475
476 if (pAllocator)
477 instance->alloc = *pAllocator;
478 else
479 instance->alloc = default_alloc;
480
481 instance->apiVersion = client_version;
482 instance->physicalDeviceCount = -1;
483
484 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
485 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
486 int index = radv_get_instance_extension_index(ext_name);
487
488 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
489 vk_free2(&default_alloc, pAllocator, instance);
490 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
491 }
492
493 instance->enabled_extensions.extensions[index] = true;
494 }
495
496 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
497 if (result != VK_SUCCESS) {
498 vk_free2(&default_alloc, pAllocator, instance);
499 return vk_error(result);
500 }
501
502 _mesa_locale_init();
503
504 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
505
506 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
507 radv_debug_options);
508
509 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
510 radv_perftest_options);
511
512 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
513
514 *pInstance = radv_instance_to_handle(instance);
515
516 return VK_SUCCESS;
517 }
518
519 void radv_DestroyInstance(
520 VkInstance _instance,
521 const VkAllocationCallbacks* pAllocator)
522 {
523 RADV_FROM_HANDLE(radv_instance, instance, _instance);
524
525 if (!instance)
526 return;
527
528 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
529 radv_physical_device_finish(instance->physicalDevices + i);
530 }
531
532 VG(VALGRIND_DESTROY_MEMPOOL(instance));
533
534 _mesa_locale_fini();
535
536 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
537
538 vk_free(&instance->alloc, instance);
539 }
540
541 static VkResult
542 radv_enumerate_devices(struct radv_instance *instance)
543 {
544 /* TODO: Check for more devices ? */
545 drmDevicePtr devices[8];
546 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
547 int max_devices;
548
549 instance->physicalDeviceCount = 0;
550
551 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
552 if (max_devices < 1)
553 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
554
555 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
556 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
557 devices[i]->bustype == DRM_BUS_PCI &&
558 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
559
560 result = radv_physical_device_init(instance->physicalDevices +
561 instance->physicalDeviceCount,
562 instance,
563 devices[i]);
564 if (result == VK_SUCCESS)
565 ++instance->physicalDeviceCount;
566 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
567 break;
568 }
569 }
570 drmFreeDevices(devices, max_devices);
571
572 return result;
573 }
574
575 VkResult radv_EnumeratePhysicalDevices(
576 VkInstance _instance,
577 uint32_t* pPhysicalDeviceCount,
578 VkPhysicalDevice* pPhysicalDevices)
579 {
580 RADV_FROM_HANDLE(radv_instance, instance, _instance);
581 VkResult result;
582
583 if (instance->physicalDeviceCount < 0) {
584 result = radv_enumerate_devices(instance);
585 if (result != VK_SUCCESS &&
586 result != VK_ERROR_INCOMPATIBLE_DRIVER)
587 return result;
588 }
589
590 if (!pPhysicalDevices) {
591 *pPhysicalDeviceCount = instance->physicalDeviceCount;
592 } else {
593 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
594 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
595 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
596 }
597
598 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
599 : VK_SUCCESS;
600 }
601
602 VkResult radv_EnumeratePhysicalDeviceGroups(
603 VkInstance _instance,
604 uint32_t* pPhysicalDeviceGroupCount,
605 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
606 {
607 RADV_FROM_HANDLE(radv_instance, instance, _instance);
608 VkResult result;
609
610 if (instance->physicalDeviceCount < 0) {
611 result = radv_enumerate_devices(instance);
612 if (result != VK_SUCCESS &&
613 result != VK_ERROR_INCOMPATIBLE_DRIVER)
614 return result;
615 }
616
617 if (!pPhysicalDeviceGroupProperties) {
618 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
619 } else {
620 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
621 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
622 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
623 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
624 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
625 }
626 }
627 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
628 : VK_SUCCESS;
629 }
630
631 void radv_GetPhysicalDeviceFeatures(
632 VkPhysicalDevice physicalDevice,
633 VkPhysicalDeviceFeatures* pFeatures)
634 {
635 memset(pFeatures, 0, sizeof(*pFeatures));
636
637 *pFeatures = (VkPhysicalDeviceFeatures) {
638 .robustBufferAccess = true,
639 .fullDrawIndexUint32 = true,
640 .imageCubeArray = true,
641 .independentBlend = true,
642 .geometryShader = true,
643 .tessellationShader = true,
644 .sampleRateShading = true,
645 .dualSrcBlend = true,
646 .logicOp = true,
647 .multiDrawIndirect = true,
648 .drawIndirectFirstInstance = true,
649 .depthClamp = true,
650 .depthBiasClamp = true,
651 .fillModeNonSolid = true,
652 .depthBounds = true,
653 .wideLines = true,
654 .largePoints = true,
655 .alphaToOne = true,
656 .multiViewport = true,
657 .samplerAnisotropy = true,
658 .textureCompressionETC2 = false,
659 .textureCompressionASTC_LDR = false,
660 .textureCompressionBC = true,
661 .occlusionQueryPrecise = true,
662 .pipelineStatisticsQuery = true,
663 .vertexPipelineStoresAndAtomics = true,
664 .fragmentStoresAndAtomics = true,
665 .shaderTessellationAndGeometryPointSize = true,
666 .shaderImageGatherExtended = true,
667 .shaderStorageImageExtendedFormats = true,
668 .shaderStorageImageMultisample = false,
669 .shaderUniformBufferArrayDynamicIndexing = true,
670 .shaderSampledImageArrayDynamicIndexing = true,
671 .shaderStorageBufferArrayDynamicIndexing = true,
672 .shaderStorageImageArrayDynamicIndexing = true,
673 .shaderStorageImageReadWithoutFormat = true,
674 .shaderStorageImageWriteWithoutFormat = true,
675 .shaderClipDistance = true,
676 .shaderCullDistance = true,
677 .shaderFloat64 = true,
678 .shaderInt64 = true,
679 .shaderInt16 = false,
680 .sparseBinding = true,
681 .variableMultisampleRate = true,
682 .inheritedQueries = true,
683 };
684 }
685
686 void radv_GetPhysicalDeviceFeatures2(
687 VkPhysicalDevice physicalDevice,
688 VkPhysicalDeviceFeatures2KHR *pFeatures)
689 {
690 vk_foreach_struct(ext, pFeatures->pNext) {
691 switch (ext->sType) {
692 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
693 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
694 features->variablePointersStorageBuffer = true;
695 features->variablePointers = false;
696 break;
697 }
698 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHR: {
699 VkPhysicalDeviceMultiviewFeaturesKHR *features = (VkPhysicalDeviceMultiviewFeaturesKHR*)ext;
700 features->multiview = true;
701 features->multiviewGeometryShader = true;
702 features->multiviewTessellationShader = true;
703 break;
704 }
705 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
706 VkPhysicalDeviceShaderDrawParameterFeatures *features =
707 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
708 features->shaderDrawParameters = true;
709 break;
710 }
711 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
712 VkPhysicalDeviceProtectedMemoryFeatures *features =
713 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
714 features->protectedMemory = false;
715 break;
716 }
717 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
718 VkPhysicalDevice16BitStorageFeatures *features =
719 (VkPhysicalDevice16BitStorageFeatures*)ext;
720 features->storageBuffer16BitAccess = false;
721 features->uniformAndStorageBuffer16BitAccess = false;
722 features->storagePushConstant16 = false;
723 features->storageInputOutput16 = false;
724 break;
725 }
726 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
727 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
728 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
729 features->samplerYcbcrConversion = false;
730 break;
731 }
732 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
733 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
734 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
735 features->shaderInputAttachmentArrayDynamicIndexing = true;
736 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
737 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
738 features->shaderUniformBufferArrayNonUniformIndexing = false;
739 features->shaderSampledImageArrayNonUniformIndexing = false;
740 features->shaderStorageBufferArrayNonUniformIndexing = false;
741 features->shaderStorageImageArrayNonUniformIndexing = false;
742 features->shaderInputAttachmentArrayNonUniformIndexing = false;
743 features->shaderUniformTexelBufferArrayNonUniformIndexing = false;
744 features->shaderStorageTexelBufferArrayNonUniformIndexing = false;
745 features->descriptorBindingUniformBufferUpdateAfterBind = true;
746 features->descriptorBindingSampledImageUpdateAfterBind = true;
747 features->descriptorBindingStorageImageUpdateAfterBind = true;
748 features->descriptorBindingStorageBufferUpdateAfterBind = true;
749 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
750 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
751 features->descriptorBindingUpdateUnusedWhilePending = true;
752 features->descriptorBindingPartiallyBound = true;
753 features->descriptorBindingVariableDescriptorCount = true;
754 features->runtimeDescriptorArray = true;
755 break;
756 }
757 default:
758 break;
759 }
760 }
761 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
762 }
763
764 void radv_GetPhysicalDeviceProperties(
765 VkPhysicalDevice physicalDevice,
766 VkPhysicalDeviceProperties* pProperties)
767 {
768 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
769 VkSampleCountFlags sample_counts = 0xf;
770
771 /* make sure that the entire descriptor set is addressable with a signed
772 * 32-bit int. So the sum of all limits scaled by descriptor size has to
773 * be at most 2 GiB. the combined image & samples object count as one of
774 * both. This limit is for the pipeline layout, not for the set layout, but
775 * there is no set limit, so we just set a pipeline limit. I don't think
776 * any app is going to hit this soon. */
777 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
778 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
779 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
780 32 /* sampler, largest when combined with image */ +
781 64 /* sampled image */ +
782 64 /* storage image */);
783
784 VkPhysicalDeviceLimits limits = {
785 .maxImageDimension1D = (1 << 14),
786 .maxImageDimension2D = (1 << 14),
787 .maxImageDimension3D = (1 << 11),
788 .maxImageDimensionCube = (1 << 14),
789 .maxImageArrayLayers = (1 << 11),
790 .maxTexelBufferElements = 128 * 1024 * 1024,
791 .maxUniformBufferRange = UINT32_MAX,
792 .maxStorageBufferRange = UINT32_MAX,
793 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
794 .maxMemoryAllocationCount = UINT32_MAX,
795 .maxSamplerAllocationCount = 64 * 1024,
796 .bufferImageGranularity = 64, /* A cache line */
797 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
798 .maxBoundDescriptorSets = MAX_SETS,
799 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
800 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
801 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
802 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
803 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
804 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
805 .maxPerStageResources = max_descriptor_set_size,
806 .maxDescriptorSetSamplers = max_descriptor_set_size,
807 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
808 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
809 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
810 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
811 .maxDescriptorSetSampledImages = max_descriptor_set_size,
812 .maxDescriptorSetStorageImages = max_descriptor_set_size,
813 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
814 .maxVertexInputAttributes = 32,
815 .maxVertexInputBindings = 32,
816 .maxVertexInputAttributeOffset = 2047,
817 .maxVertexInputBindingStride = 2048,
818 .maxVertexOutputComponents = 128,
819 .maxTessellationGenerationLevel = 64,
820 .maxTessellationPatchSize = 32,
821 .maxTessellationControlPerVertexInputComponents = 128,
822 .maxTessellationControlPerVertexOutputComponents = 128,
823 .maxTessellationControlPerPatchOutputComponents = 120,
824 .maxTessellationControlTotalOutputComponents = 4096,
825 .maxTessellationEvaluationInputComponents = 128,
826 .maxTessellationEvaluationOutputComponents = 128,
827 .maxGeometryShaderInvocations = 127,
828 .maxGeometryInputComponents = 64,
829 .maxGeometryOutputComponents = 128,
830 .maxGeometryOutputVertices = 256,
831 .maxGeometryTotalOutputComponents = 1024,
832 .maxFragmentInputComponents = 128,
833 .maxFragmentOutputAttachments = 8,
834 .maxFragmentDualSrcAttachments = 1,
835 .maxFragmentCombinedOutputResources = 8,
836 .maxComputeSharedMemorySize = 32768,
837 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
838 .maxComputeWorkGroupInvocations = 2048,
839 .maxComputeWorkGroupSize = {
840 2048,
841 2048,
842 2048
843 },
844 .subPixelPrecisionBits = 4 /* FIXME */,
845 .subTexelPrecisionBits = 4 /* FIXME */,
846 .mipmapPrecisionBits = 4 /* FIXME */,
847 .maxDrawIndexedIndexValue = UINT32_MAX,
848 .maxDrawIndirectCount = UINT32_MAX,
849 .maxSamplerLodBias = 16,
850 .maxSamplerAnisotropy = 16,
851 .maxViewports = MAX_VIEWPORTS,
852 .maxViewportDimensions = { (1 << 14), (1 << 14) },
853 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
854 .viewportSubPixelBits = 8,
855 .minMemoryMapAlignment = 4096, /* A page */
856 .minTexelBufferOffsetAlignment = 1,
857 .minUniformBufferOffsetAlignment = 4,
858 .minStorageBufferOffsetAlignment = 4,
859 .minTexelOffset = -32,
860 .maxTexelOffset = 31,
861 .minTexelGatherOffset = -32,
862 .maxTexelGatherOffset = 31,
863 .minInterpolationOffset = -2,
864 .maxInterpolationOffset = 2,
865 .subPixelInterpolationOffsetBits = 8,
866 .maxFramebufferWidth = (1 << 14),
867 .maxFramebufferHeight = (1 << 14),
868 .maxFramebufferLayers = (1 << 10),
869 .framebufferColorSampleCounts = sample_counts,
870 .framebufferDepthSampleCounts = sample_counts,
871 .framebufferStencilSampleCounts = sample_counts,
872 .framebufferNoAttachmentsSampleCounts = sample_counts,
873 .maxColorAttachments = MAX_RTS,
874 .sampledImageColorSampleCounts = sample_counts,
875 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
876 .sampledImageDepthSampleCounts = sample_counts,
877 .sampledImageStencilSampleCounts = sample_counts,
878 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
879 .maxSampleMaskWords = 1,
880 .timestampComputeAndGraphics = true,
881 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
882 .maxClipDistances = 8,
883 .maxCullDistances = 8,
884 .maxCombinedClipAndCullDistances = 8,
885 .discreteQueuePriorities = 1,
886 .pointSizeRange = { 0.125, 255.875 },
887 .lineWidthRange = { 0.0, 7.9921875 },
888 .pointSizeGranularity = (1.0 / 8.0),
889 .lineWidthGranularity = (1.0 / 128.0),
890 .strictLines = false, /* FINISHME */
891 .standardSampleLocations = true,
892 .optimalBufferCopyOffsetAlignment = 128,
893 .optimalBufferCopyRowPitchAlignment = 128,
894 .nonCoherentAtomSize = 64,
895 };
896
897 *pProperties = (VkPhysicalDeviceProperties) {
898 .apiVersion = radv_physical_device_api_version(pdevice),
899 .driverVersion = vk_get_driver_version(),
900 .vendorID = ATI_VENDOR_ID,
901 .deviceID = pdevice->rad_info.pci_id,
902 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
903 .limits = limits,
904 .sparseProperties = {0},
905 };
906
907 strcpy(pProperties->deviceName, pdevice->name);
908 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
909 }
910
911 void radv_GetPhysicalDeviceProperties2(
912 VkPhysicalDevice physicalDevice,
913 VkPhysicalDeviceProperties2KHR *pProperties)
914 {
915 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
916 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
917
918 vk_foreach_struct(ext, pProperties->pNext) {
919 switch (ext->sType) {
920 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
921 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
922 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
923 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
924 break;
925 }
926 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
927 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
928 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
929 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
930 properties->deviceLUIDValid = false;
931 break;
932 }
933 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHR: {
934 VkPhysicalDeviceMultiviewPropertiesKHR *properties = (VkPhysicalDeviceMultiviewPropertiesKHR*)ext;
935 properties->maxMultiviewViewCount = MAX_VIEWS;
936 properties->maxMultiviewInstanceIndex = INT_MAX;
937 break;
938 }
939 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
940 VkPhysicalDevicePointClippingPropertiesKHR *properties =
941 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
942 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
943 break;
944 }
945 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
946 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
947 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
948 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
949 break;
950 }
951 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
952 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
953 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
954 properties->minImportedHostPointerAlignment = 4096;
955 break;
956 }
957 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
958 VkPhysicalDeviceSubgroupProperties *properties =
959 (VkPhysicalDeviceSubgroupProperties*)ext;
960 properties->subgroupSize = 64;
961 properties->supportedStages = VK_SHADER_STAGE_ALL;
962 properties->supportedOperations =
963 VK_SUBGROUP_FEATURE_BASIC_BIT |
964 VK_SUBGROUP_FEATURE_BALLOT_BIT |
965 VK_SUBGROUP_FEATURE_QUAD_BIT |
966 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
967 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT |
968 VK_SUBGROUP_FEATURE_VOTE_BIT;
969 properties->quadOperationsInAllStages = true;
970 break;
971 }
972 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
973 VkPhysicalDeviceMaintenance3Properties *properties =
974 (VkPhysicalDeviceMaintenance3Properties*)ext;
975 /* Make sure everything is addressable by a signed 32-bit int, and
976 * our largest descriptors are 96 bytes. */
977 properties->maxPerSetDescriptors = (1ull << 31) / 96;
978 /* Our buffer size fields allow only this much */
979 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
980 break;
981 }
982 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
983 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
984 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
985 /* GFX6-8 only support single channel min/max filter. */
986 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
987 properties->filterMinmaxSingleComponentFormats = true;
988 break;
989 }
990 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
991 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
992 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
993
994 /* Shader engines. */
995 properties->shaderEngineCount =
996 pdevice->rad_info.max_se;
997 properties->shaderArraysPerEngineCount =
998 pdevice->rad_info.max_sh_per_se;
999 properties->computeUnitsPerShaderArray =
1000 pdevice->rad_info.num_good_compute_units /
1001 (pdevice->rad_info.max_se *
1002 pdevice->rad_info.max_sh_per_se);
1003 properties->simdPerComputeUnit = 4;
1004 properties->wavefrontsPerSimd =
1005 pdevice->rad_info.family == CHIP_TONGA ||
1006 pdevice->rad_info.family == CHIP_ICELAND ||
1007 pdevice->rad_info.family == CHIP_POLARIS10 ||
1008 pdevice->rad_info.family == CHIP_POLARIS11 ||
1009 pdevice->rad_info.family == CHIP_POLARIS12 ||
1010 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1011 properties->wavefrontSize = 64;
1012
1013 /* SGPR. */
1014 properties->sgprsPerSimd =
1015 radv_get_num_physical_sgprs(pdevice);
1016 properties->minSgprAllocation =
1017 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1018 properties->maxSgprAllocation =
1019 pdevice->rad_info.family == CHIP_TONGA ||
1020 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1021 properties->sgprAllocationGranularity =
1022 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1023
1024 /* VGPR. */
1025 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1026 properties->minVgprAllocation = 4;
1027 properties->maxVgprAllocation = 256;
1028 properties->vgprAllocationGranularity = 4;
1029 break;
1030 }
1031 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1032 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1033 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1034 properties->maxVertexAttribDivisor = UINT32_MAX;
1035 break;
1036 }
1037 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1038 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1039 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1040 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1041 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1042 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1043 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1044 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1045 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1046 properties->robustBufferAccessUpdateAfterBind = false;
1047 properties->quadDivergentImplicitLod = false;
1048
1049 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1050 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1051 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1052 32 /* sampler, largest when combined with image */ +
1053 64 /* sampled image */ +
1054 64 /* storage image */);
1055 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1056 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1057 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1058 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1059 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1060 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1061 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1062 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1063 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1064 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1065 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1066 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1067 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1068 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1069 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1070 break;
1071 }
1072 default:
1073 break;
1074 }
1075 }
1076 }
1077
1078 static void radv_get_physical_device_queue_family_properties(
1079 struct radv_physical_device* pdevice,
1080 uint32_t* pCount,
1081 VkQueueFamilyProperties** pQueueFamilyProperties)
1082 {
1083 int num_queue_families = 1;
1084 int idx;
1085 if (pdevice->rad_info.num_compute_rings > 0 &&
1086 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1087 num_queue_families++;
1088
1089 if (pQueueFamilyProperties == NULL) {
1090 *pCount = num_queue_families;
1091 return;
1092 }
1093
1094 if (!*pCount)
1095 return;
1096
1097 idx = 0;
1098 if (*pCount >= 1) {
1099 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1100 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1101 VK_QUEUE_COMPUTE_BIT |
1102 VK_QUEUE_TRANSFER_BIT |
1103 VK_QUEUE_SPARSE_BINDING_BIT,
1104 .queueCount = 1,
1105 .timestampValidBits = 64,
1106 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1107 };
1108 idx++;
1109 }
1110
1111 if (pdevice->rad_info.num_compute_rings > 0 &&
1112 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1113 if (*pCount > idx) {
1114 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1115 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1116 VK_QUEUE_TRANSFER_BIT |
1117 VK_QUEUE_SPARSE_BINDING_BIT,
1118 .queueCount = pdevice->rad_info.num_compute_rings,
1119 .timestampValidBits = 64,
1120 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1121 };
1122 idx++;
1123 }
1124 }
1125 *pCount = idx;
1126 }
1127
1128 void radv_GetPhysicalDeviceQueueFamilyProperties(
1129 VkPhysicalDevice physicalDevice,
1130 uint32_t* pCount,
1131 VkQueueFamilyProperties* pQueueFamilyProperties)
1132 {
1133 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1134 if (!pQueueFamilyProperties) {
1135 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1136 return;
1137 }
1138 VkQueueFamilyProperties *properties[] = {
1139 pQueueFamilyProperties + 0,
1140 pQueueFamilyProperties + 1,
1141 pQueueFamilyProperties + 2,
1142 };
1143 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1144 assert(*pCount <= 3);
1145 }
1146
1147 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1148 VkPhysicalDevice physicalDevice,
1149 uint32_t* pCount,
1150 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
1151 {
1152 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1153 if (!pQueueFamilyProperties) {
1154 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1155 return;
1156 }
1157 VkQueueFamilyProperties *properties[] = {
1158 &pQueueFamilyProperties[0].queueFamilyProperties,
1159 &pQueueFamilyProperties[1].queueFamilyProperties,
1160 &pQueueFamilyProperties[2].queueFamilyProperties,
1161 };
1162 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1163 assert(*pCount <= 3);
1164 }
1165
1166 void radv_GetPhysicalDeviceMemoryProperties(
1167 VkPhysicalDevice physicalDevice,
1168 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1169 {
1170 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1171
1172 *pMemoryProperties = physical_device->memory_properties;
1173 }
1174
1175 void radv_GetPhysicalDeviceMemoryProperties2(
1176 VkPhysicalDevice physicalDevice,
1177 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
1178 {
1179 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1180 &pMemoryProperties->memoryProperties);
1181 }
1182
1183 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1184 VkDevice _device,
1185 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
1186 const void *pHostPointer,
1187 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1188 {
1189 RADV_FROM_HANDLE(radv_device, device, _device);
1190
1191 switch (handleType)
1192 {
1193 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1194 const struct radv_physical_device *physical_device = device->physical_device;
1195 uint32_t memoryTypeBits = 0;
1196 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1197 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1198 memoryTypeBits = (1 << i);
1199 break;
1200 }
1201 }
1202 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1203 return VK_SUCCESS;
1204 }
1205 default:
1206 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
1207 }
1208 }
1209
1210 static enum radeon_ctx_priority
1211 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1212 {
1213 /* Default to MEDIUM when a specific global priority isn't requested */
1214 if (!pObj)
1215 return RADEON_CTX_PRIORITY_MEDIUM;
1216
1217 switch(pObj->globalPriority) {
1218 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1219 return RADEON_CTX_PRIORITY_REALTIME;
1220 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1221 return RADEON_CTX_PRIORITY_HIGH;
1222 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1223 return RADEON_CTX_PRIORITY_MEDIUM;
1224 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1225 return RADEON_CTX_PRIORITY_LOW;
1226 default:
1227 unreachable("Illegal global priority value");
1228 return RADEON_CTX_PRIORITY_INVALID;
1229 }
1230 }
1231
1232 static int
1233 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1234 uint32_t queue_family_index, int idx,
1235 VkDeviceQueueCreateFlags flags,
1236 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1237 {
1238 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1239 queue->device = device;
1240 queue->queue_family_index = queue_family_index;
1241 queue->queue_idx = idx;
1242 queue->priority = radv_get_queue_global_priority(global_priority);
1243 queue->flags = flags;
1244
1245 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1246 if (!queue->hw_ctx)
1247 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1248
1249 return VK_SUCCESS;
1250 }
1251
1252 static void
1253 radv_queue_finish(struct radv_queue *queue)
1254 {
1255 if (queue->hw_ctx)
1256 queue->device->ws->ctx_destroy(queue->hw_ctx);
1257
1258 if (queue->initial_full_flush_preamble_cs)
1259 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1260 if (queue->initial_preamble_cs)
1261 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1262 if (queue->continue_preamble_cs)
1263 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1264 if (queue->descriptor_bo)
1265 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1266 if (queue->scratch_bo)
1267 queue->device->ws->buffer_destroy(queue->scratch_bo);
1268 if (queue->esgs_ring_bo)
1269 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1270 if (queue->gsvs_ring_bo)
1271 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1272 if (queue->tess_rings_bo)
1273 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1274 if (queue->compute_scratch_bo)
1275 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1276 }
1277
1278 static void
1279 radv_bo_list_init(struct radv_bo_list *bo_list)
1280 {
1281 pthread_mutex_init(&bo_list->mutex, NULL);
1282 bo_list->list.count = bo_list->capacity = 0;
1283 bo_list->list.bos = NULL;
1284 }
1285
1286 static void
1287 radv_bo_list_finish(struct radv_bo_list *bo_list)
1288 {
1289 free(bo_list->list.bos);
1290 pthread_mutex_destroy(&bo_list->mutex);
1291 }
1292
1293 static VkResult radv_bo_list_add(struct radv_device *device,
1294 struct radeon_winsys_bo *bo)
1295 {
1296 struct radv_bo_list *bo_list = &device->bo_list;
1297
1298 if (unlikely(!device->use_global_bo_list))
1299 return VK_SUCCESS;
1300
1301 pthread_mutex_lock(&bo_list->mutex);
1302 if (bo_list->list.count == bo_list->capacity) {
1303 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1304 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1305
1306 if (!data) {
1307 pthread_mutex_unlock(&bo_list->mutex);
1308 return VK_ERROR_OUT_OF_HOST_MEMORY;
1309 }
1310
1311 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1312 bo_list->capacity = capacity;
1313 }
1314
1315 bo_list->list.bos[bo_list->list.count++] = bo;
1316 pthread_mutex_unlock(&bo_list->mutex);
1317 return VK_SUCCESS;
1318 }
1319
1320 static void radv_bo_list_remove(struct radv_device *device,
1321 struct radeon_winsys_bo *bo)
1322 {
1323 struct radv_bo_list *bo_list = &device->bo_list;
1324
1325 if (unlikely(!device->use_global_bo_list))
1326 return;
1327
1328 pthread_mutex_lock(&bo_list->mutex);
1329 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1330 if (bo_list->list.bos[i] == bo) {
1331 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1332 --bo_list->list.count;
1333 break;
1334 }
1335 }
1336 pthread_mutex_unlock(&bo_list->mutex);
1337 }
1338
1339 static void
1340 radv_device_init_gs_info(struct radv_device *device)
1341 {
1342 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1343 device->physical_device->rad_info.family);
1344 }
1345
1346 static int radv_get_device_extension_index(const char *name)
1347 {
1348 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1349 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1350 return i;
1351 }
1352 return -1;
1353 }
1354
1355 VkResult radv_CreateDevice(
1356 VkPhysicalDevice physicalDevice,
1357 const VkDeviceCreateInfo* pCreateInfo,
1358 const VkAllocationCallbacks* pAllocator,
1359 VkDevice* pDevice)
1360 {
1361 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1362 VkResult result;
1363 struct radv_device *device;
1364
1365 bool keep_shader_info = false;
1366
1367 /* Check enabled features */
1368 if (pCreateInfo->pEnabledFeatures) {
1369 VkPhysicalDeviceFeatures supported_features;
1370 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1371 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1372 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1373 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1374 for (uint32_t i = 0; i < num_features; i++) {
1375 if (enabled_feature[i] && !supported_feature[i])
1376 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
1377 }
1378 }
1379
1380 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1381 sizeof(*device), 8,
1382 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1383 if (!device)
1384 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1385
1386 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1387 device->instance = physical_device->instance;
1388 device->physical_device = physical_device;
1389
1390 device->ws = physical_device->ws;
1391 if (pAllocator)
1392 device->alloc = *pAllocator;
1393 else
1394 device->alloc = physical_device->instance->alloc;
1395
1396 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1397 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1398 int index = radv_get_device_extension_index(ext_name);
1399 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1400 vk_free(&device->alloc, device);
1401 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
1402 }
1403
1404 device->enabled_extensions.extensions[index] = true;
1405 }
1406
1407 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1408
1409 /* With update after bind we can't attach bo's to the command buffer
1410 * from the descriptor set anymore, so we have to use a global BO list.
1411 */
1412 device->use_global_bo_list =
1413 device->enabled_extensions.EXT_descriptor_indexing;
1414
1415 mtx_init(&device->shader_slab_mutex, mtx_plain);
1416 list_inithead(&device->shader_slabs);
1417
1418 radv_bo_list_init(&device->bo_list);
1419
1420 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1421 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1422 uint32_t qfi = queue_create->queueFamilyIndex;
1423 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1424 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1425
1426 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1427
1428 device->queues[qfi] = vk_alloc(&device->alloc,
1429 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1430 if (!device->queues[qfi]) {
1431 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1432 goto fail;
1433 }
1434
1435 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1436
1437 device->queue_count[qfi] = queue_create->queueCount;
1438
1439 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1440 result = radv_queue_init(device, &device->queues[qfi][q],
1441 qfi, q, queue_create->flags,
1442 global_priority);
1443 if (result != VK_SUCCESS)
1444 goto fail;
1445 }
1446 }
1447
1448 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1449 (device->instance->perftest_flags & RADV_PERFTEST_BINNING);
1450
1451 /* Disabled and not implemented for now. */
1452 device->dfsm_allowed = device->pbb_allowed && false;
1453
1454 #ifdef ANDROID
1455 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1456 #endif
1457
1458 /* The maximum number of scratch waves. Scratch space isn't divided
1459 * evenly between CUs. The number is only a function of the number of CUs.
1460 * We can decrease the constant to decrease the scratch buffer size.
1461 *
1462 * sctx->scratch_waves must be >= the maximum possible size of
1463 * 1 threadgroup, so that the hw doesn't hang from being unable
1464 * to start any.
1465 *
1466 * The recommended value is 4 per CU at most. Higher numbers don't
1467 * bring much benefit, but they still occupy chip resources (think
1468 * async compute). I've seen ~2% performance difference between 4 and 32.
1469 */
1470 uint32_t max_threads_per_block = 2048;
1471 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1472 max_threads_per_block / 64);
1473
1474 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1475
1476 if (device->physical_device->rad_info.chip_class >= CIK) {
1477 /* If the KMD allows it (there is a KMD hw register for it),
1478 * allow launching waves out-of-order.
1479 */
1480 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1481 }
1482
1483 radv_device_init_gs_info(device);
1484
1485 device->tess_offchip_block_dw_size =
1486 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1487 device->has_distributed_tess =
1488 device->physical_device->rad_info.chip_class >= VI &&
1489 device->physical_device->rad_info.max_se >= 2;
1490
1491 if (getenv("RADV_TRACE_FILE")) {
1492 const char *filename = getenv("RADV_TRACE_FILE");
1493
1494 keep_shader_info = true;
1495
1496 if (!radv_init_trace(device))
1497 goto fail;
1498
1499 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1500 radv_dump_enabled_options(device, stderr);
1501 }
1502
1503 device->keep_shader_info = keep_shader_info;
1504
1505 result = radv_device_init_meta(device);
1506 if (result != VK_SUCCESS)
1507 goto fail;
1508
1509 radv_device_init_msaa(device);
1510
1511 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1512 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1513 switch (family) {
1514 case RADV_QUEUE_GENERAL:
1515 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1516 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1517 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1518 break;
1519 case RADV_QUEUE_COMPUTE:
1520 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1521 radeon_emit(device->empty_cs[family], 0);
1522 break;
1523 }
1524 device->ws->cs_finalize(device->empty_cs[family]);
1525 }
1526
1527 if (device->physical_device->rad_info.chip_class >= CIK)
1528 cik_create_gfx_config(device);
1529
1530 VkPipelineCacheCreateInfo ci;
1531 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1532 ci.pNext = NULL;
1533 ci.flags = 0;
1534 ci.pInitialData = NULL;
1535 ci.initialDataSize = 0;
1536 VkPipelineCache pc;
1537 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1538 &ci, NULL, &pc);
1539 if (result != VK_SUCCESS)
1540 goto fail_meta;
1541
1542 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1543
1544 *pDevice = radv_device_to_handle(device);
1545 return VK_SUCCESS;
1546
1547 fail_meta:
1548 radv_device_finish_meta(device);
1549 fail:
1550 radv_bo_list_finish(&device->bo_list);
1551
1552 if (device->trace_bo)
1553 device->ws->buffer_destroy(device->trace_bo);
1554
1555 if (device->gfx_init)
1556 device->ws->buffer_destroy(device->gfx_init);
1557
1558 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1559 for (unsigned q = 0; q < device->queue_count[i]; q++)
1560 radv_queue_finish(&device->queues[i][q]);
1561 if (device->queue_count[i])
1562 vk_free(&device->alloc, device->queues[i]);
1563 }
1564
1565 vk_free(&device->alloc, device);
1566 return result;
1567 }
1568
1569 void radv_DestroyDevice(
1570 VkDevice _device,
1571 const VkAllocationCallbacks* pAllocator)
1572 {
1573 RADV_FROM_HANDLE(radv_device, device, _device);
1574
1575 if (!device)
1576 return;
1577
1578 if (device->trace_bo)
1579 device->ws->buffer_destroy(device->trace_bo);
1580
1581 if (device->gfx_init)
1582 device->ws->buffer_destroy(device->gfx_init);
1583
1584 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1585 for (unsigned q = 0; q < device->queue_count[i]; q++)
1586 radv_queue_finish(&device->queues[i][q]);
1587 if (device->queue_count[i])
1588 vk_free(&device->alloc, device->queues[i]);
1589 if (device->empty_cs[i])
1590 device->ws->cs_destroy(device->empty_cs[i]);
1591 }
1592 radv_device_finish_meta(device);
1593
1594 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1595 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1596
1597 radv_destroy_shader_slabs(device);
1598
1599 radv_bo_list_finish(&device->bo_list);
1600 vk_free(&device->alloc, device);
1601 }
1602
1603 VkResult radv_EnumerateInstanceLayerProperties(
1604 uint32_t* pPropertyCount,
1605 VkLayerProperties* pProperties)
1606 {
1607 if (pProperties == NULL) {
1608 *pPropertyCount = 0;
1609 return VK_SUCCESS;
1610 }
1611
1612 /* None supported at this time */
1613 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1614 }
1615
1616 VkResult radv_EnumerateDeviceLayerProperties(
1617 VkPhysicalDevice physicalDevice,
1618 uint32_t* pPropertyCount,
1619 VkLayerProperties* pProperties)
1620 {
1621 if (pProperties == NULL) {
1622 *pPropertyCount = 0;
1623 return VK_SUCCESS;
1624 }
1625
1626 /* None supported at this time */
1627 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1628 }
1629
1630 void radv_GetDeviceQueue2(
1631 VkDevice _device,
1632 const VkDeviceQueueInfo2* pQueueInfo,
1633 VkQueue* pQueue)
1634 {
1635 RADV_FROM_HANDLE(radv_device, device, _device);
1636 struct radv_queue *queue;
1637
1638 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
1639 if (pQueueInfo->flags != queue->flags) {
1640 /* From the Vulkan 1.1.70 spec:
1641 *
1642 * "The queue returned by vkGetDeviceQueue2 must have the same
1643 * flags value from this structure as that used at device
1644 * creation time in a VkDeviceQueueCreateInfo instance. If no
1645 * matching flags were specified at device creation time then
1646 * pQueue will return VK_NULL_HANDLE."
1647 */
1648 *pQueue = VK_NULL_HANDLE;
1649 return;
1650 }
1651
1652 *pQueue = radv_queue_to_handle(queue);
1653 }
1654
1655 void radv_GetDeviceQueue(
1656 VkDevice _device,
1657 uint32_t queueFamilyIndex,
1658 uint32_t queueIndex,
1659 VkQueue* pQueue)
1660 {
1661 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
1662 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
1663 .queueFamilyIndex = queueFamilyIndex,
1664 .queueIndex = queueIndex
1665 };
1666
1667 radv_GetDeviceQueue2(_device, &info, pQueue);
1668 }
1669
1670 static void
1671 fill_geom_tess_rings(struct radv_queue *queue,
1672 uint32_t *map,
1673 bool add_sample_positions,
1674 uint32_t esgs_ring_size,
1675 struct radeon_winsys_bo *esgs_ring_bo,
1676 uint32_t gsvs_ring_size,
1677 struct radeon_winsys_bo *gsvs_ring_bo,
1678 uint32_t tess_factor_ring_size,
1679 uint32_t tess_offchip_ring_offset,
1680 uint32_t tess_offchip_ring_size,
1681 struct radeon_winsys_bo *tess_rings_bo)
1682 {
1683 uint64_t esgs_va = 0, gsvs_va = 0;
1684 uint64_t tess_va = 0, tess_offchip_va = 0;
1685 uint32_t *desc = &map[4];
1686
1687 if (esgs_ring_bo)
1688 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1689 if (gsvs_ring_bo)
1690 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1691 if (tess_rings_bo) {
1692 tess_va = radv_buffer_get_va(tess_rings_bo);
1693 tess_offchip_va = tess_va + tess_offchip_ring_offset;
1694 }
1695
1696 /* stride 0, num records - size, add tid, swizzle, elsize4,
1697 index stride 64 */
1698 desc[0] = esgs_va;
1699 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1700 S_008F04_STRIDE(0) |
1701 S_008F04_SWIZZLE_ENABLE(true);
1702 desc[2] = esgs_ring_size;
1703 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1704 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1705 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1706 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1707 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1708 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1709 S_008F0C_ELEMENT_SIZE(1) |
1710 S_008F0C_INDEX_STRIDE(3) |
1711 S_008F0C_ADD_TID_ENABLE(true);
1712
1713 desc += 4;
1714 /* GS entry for ES->GS ring */
1715 /* stride 0, num records - size, elsize0,
1716 index stride 0 */
1717 desc[0] = esgs_va;
1718 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1719 S_008F04_STRIDE(0) |
1720 S_008F04_SWIZZLE_ENABLE(false);
1721 desc[2] = esgs_ring_size;
1722 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1723 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1724 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1725 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1726 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1727 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1728 S_008F0C_ELEMENT_SIZE(0) |
1729 S_008F0C_INDEX_STRIDE(0) |
1730 S_008F0C_ADD_TID_ENABLE(false);
1731
1732 desc += 4;
1733 /* VS entry for GS->VS ring */
1734 /* stride 0, num records - size, elsize0,
1735 index stride 0 */
1736 desc[0] = gsvs_va;
1737 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1738 S_008F04_STRIDE(0) |
1739 S_008F04_SWIZZLE_ENABLE(false);
1740 desc[2] = gsvs_ring_size;
1741 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1742 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1743 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1744 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1745 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1746 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1747 S_008F0C_ELEMENT_SIZE(0) |
1748 S_008F0C_INDEX_STRIDE(0) |
1749 S_008F0C_ADD_TID_ENABLE(false);
1750 desc += 4;
1751
1752 /* stride gsvs_itemsize, num records 64
1753 elsize 4, index stride 16 */
1754 /* shader will patch stride and desc[2] */
1755 desc[0] = gsvs_va;
1756 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1757 S_008F04_STRIDE(0) |
1758 S_008F04_SWIZZLE_ENABLE(true);
1759 desc[2] = 0;
1760 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1761 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1762 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1763 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1764 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1765 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1766 S_008F0C_ELEMENT_SIZE(1) |
1767 S_008F0C_INDEX_STRIDE(1) |
1768 S_008F0C_ADD_TID_ENABLE(true);
1769 desc += 4;
1770
1771 desc[0] = tess_va;
1772 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
1773 S_008F04_STRIDE(0) |
1774 S_008F04_SWIZZLE_ENABLE(false);
1775 desc[2] = tess_factor_ring_size;
1776 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1777 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1778 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1779 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1780 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1781 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1782 S_008F0C_ELEMENT_SIZE(0) |
1783 S_008F0C_INDEX_STRIDE(0) |
1784 S_008F0C_ADD_TID_ENABLE(false);
1785 desc += 4;
1786
1787 desc[0] = tess_offchip_va;
1788 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1789 S_008F04_STRIDE(0) |
1790 S_008F04_SWIZZLE_ENABLE(false);
1791 desc[2] = tess_offchip_ring_size;
1792 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1793 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1794 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1795 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1796 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1797 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1798 S_008F0C_ELEMENT_SIZE(0) |
1799 S_008F0C_INDEX_STRIDE(0) |
1800 S_008F0C_ADD_TID_ENABLE(false);
1801 desc += 4;
1802
1803 /* add sample positions after all rings */
1804 memcpy(desc, queue->device->sample_locations_1x, 8);
1805 desc += 2;
1806 memcpy(desc, queue->device->sample_locations_2x, 16);
1807 desc += 4;
1808 memcpy(desc, queue->device->sample_locations_4x, 32);
1809 desc += 8;
1810 memcpy(desc, queue->device->sample_locations_8x, 64);
1811 desc += 16;
1812 memcpy(desc, queue->device->sample_locations_16x, 128);
1813 }
1814
1815 static unsigned
1816 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1817 {
1818 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1819 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1820 device->physical_device->rad_info.family != CHIP_STONEY;
1821 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1822 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1823 device->physical_device->rad_info.max_se;
1824 unsigned offchip_granularity;
1825 unsigned hs_offchip_param;
1826 switch (device->tess_offchip_block_dw_size) {
1827 default:
1828 assert(0);
1829 /* fall through */
1830 case 8192:
1831 offchip_granularity = V_03093C_X_8K_DWORDS;
1832 break;
1833 case 4096:
1834 offchip_granularity = V_03093C_X_4K_DWORDS;
1835 break;
1836 }
1837
1838 switch (device->physical_device->rad_info.chip_class) {
1839 case SI:
1840 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1841 break;
1842 case CIK:
1843 case VI:
1844 case GFX9:
1845 default:
1846 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1847 break;
1848 }
1849
1850 *max_offchip_buffers_p = max_offchip_buffers;
1851 if (device->physical_device->rad_info.chip_class >= CIK) {
1852 if (device->physical_device->rad_info.chip_class >= VI)
1853 --max_offchip_buffers;
1854 hs_offchip_param =
1855 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1856 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1857 } else {
1858 hs_offchip_param =
1859 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1860 }
1861 return hs_offchip_param;
1862 }
1863
1864 static void
1865 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_winsys_cs *cs,
1866 struct radeon_winsys_bo *esgs_ring_bo,
1867 uint32_t esgs_ring_size,
1868 struct radeon_winsys_bo *gsvs_ring_bo,
1869 uint32_t gsvs_ring_size)
1870 {
1871 if (!esgs_ring_bo && !gsvs_ring_bo)
1872 return;
1873
1874 if (esgs_ring_bo)
1875 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo, 8);
1876
1877 if (gsvs_ring_bo)
1878 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo, 8);
1879
1880 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1881 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1882 radeon_emit(cs, esgs_ring_size >> 8);
1883 radeon_emit(cs, gsvs_ring_size >> 8);
1884 } else {
1885 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1886 radeon_emit(cs, esgs_ring_size >> 8);
1887 radeon_emit(cs, gsvs_ring_size >> 8);
1888 }
1889 }
1890
1891 static void
1892 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_winsys_cs *cs,
1893 unsigned hs_offchip_param, unsigned tf_ring_size,
1894 struct radeon_winsys_bo *tess_rings_bo)
1895 {
1896 uint64_t tf_va;
1897
1898 if (!tess_rings_bo)
1899 return;
1900
1901 tf_va = radv_buffer_get_va(tess_rings_bo);
1902
1903 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo, 8);
1904
1905 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1906 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1907 S_030938_SIZE(tf_ring_size / 4));
1908 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1909 tf_va >> 8);
1910 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1911 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1912 S_030944_BASE_HI(tf_va >> 40));
1913 }
1914 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
1915 hs_offchip_param);
1916 } else {
1917 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1918 S_008988_SIZE(tf_ring_size / 4));
1919 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1920 tf_va >> 8);
1921 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1922 hs_offchip_param);
1923 }
1924 }
1925
1926 static void
1927 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_winsys_cs *cs,
1928 struct radeon_winsys_bo *compute_scratch_bo)
1929 {
1930 uint64_t scratch_va;
1931
1932 if (!compute_scratch_bo)
1933 return;
1934
1935 scratch_va = radv_buffer_get_va(compute_scratch_bo);
1936
1937 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo, 8);
1938
1939 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1940 radeon_emit(cs, scratch_va);
1941 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1942 S_008F04_SWIZZLE_ENABLE(1));
1943 }
1944
1945 static void
1946 radv_emit_global_shader_pointers(struct radv_queue *queue,
1947 struct radeon_winsys_cs *cs,
1948 struct radeon_winsys_bo *descriptor_bo)
1949 {
1950 uint64_t va;
1951
1952 if (!descriptor_bo)
1953 return;
1954
1955 va = radv_buffer_get_va(descriptor_bo);
1956
1957 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo, 8);
1958
1959 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1960 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1961 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1962 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
1963 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
1964
1965 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1966 radv_emit_shader_pointer(queue->device, cs, regs[i],
1967 va, true);
1968 }
1969 } else {
1970 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1971 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1972 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1973 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1974 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1975 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1976
1977 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1978 radv_emit_shader_pointer(queue->device, cs, regs[i],
1979 va, true);
1980 }
1981 }
1982 }
1983
1984 static VkResult
1985 radv_get_preamble_cs(struct radv_queue *queue,
1986 uint32_t scratch_size,
1987 uint32_t compute_scratch_size,
1988 uint32_t esgs_ring_size,
1989 uint32_t gsvs_ring_size,
1990 bool needs_tess_rings,
1991 bool needs_sample_positions,
1992 struct radeon_winsys_cs **initial_full_flush_preamble_cs,
1993 struct radeon_winsys_cs **initial_preamble_cs,
1994 struct radeon_winsys_cs **continue_preamble_cs)
1995 {
1996 struct radeon_winsys_bo *scratch_bo = NULL;
1997 struct radeon_winsys_bo *descriptor_bo = NULL;
1998 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1999 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2000 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2001 struct radeon_winsys_bo *tess_rings_bo = NULL;
2002 struct radeon_winsys_cs *dest_cs[3] = {0};
2003 bool add_tess_rings = false, add_sample_positions = false;
2004 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2005 unsigned max_offchip_buffers;
2006 unsigned hs_offchip_param = 0;
2007 unsigned tess_offchip_ring_offset;
2008 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2009 if (!queue->has_tess_rings) {
2010 if (needs_tess_rings)
2011 add_tess_rings = true;
2012 }
2013 if (!queue->has_sample_positions) {
2014 if (needs_sample_positions)
2015 add_sample_positions = true;
2016 }
2017 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2018 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2019 &max_offchip_buffers);
2020 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2021 tess_offchip_ring_size = max_offchip_buffers *
2022 queue->device->tess_offchip_block_dw_size * 4;
2023
2024 if (scratch_size <= queue->scratch_size &&
2025 compute_scratch_size <= queue->compute_scratch_size &&
2026 esgs_ring_size <= queue->esgs_ring_size &&
2027 gsvs_ring_size <= queue->gsvs_ring_size &&
2028 !add_tess_rings && !add_sample_positions &&
2029 queue->initial_preamble_cs) {
2030 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2031 *initial_preamble_cs = queue->initial_preamble_cs;
2032 *continue_preamble_cs = queue->continue_preamble_cs;
2033 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2034 *continue_preamble_cs = NULL;
2035 return VK_SUCCESS;
2036 }
2037
2038 if (scratch_size > queue->scratch_size) {
2039 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2040 scratch_size,
2041 4096,
2042 RADEON_DOMAIN_VRAM,
2043 ring_bo_flags);
2044 if (!scratch_bo)
2045 goto fail;
2046 } else
2047 scratch_bo = queue->scratch_bo;
2048
2049 if (compute_scratch_size > queue->compute_scratch_size) {
2050 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2051 compute_scratch_size,
2052 4096,
2053 RADEON_DOMAIN_VRAM,
2054 ring_bo_flags);
2055 if (!compute_scratch_bo)
2056 goto fail;
2057
2058 } else
2059 compute_scratch_bo = queue->compute_scratch_bo;
2060
2061 if (esgs_ring_size > queue->esgs_ring_size) {
2062 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2063 esgs_ring_size,
2064 4096,
2065 RADEON_DOMAIN_VRAM,
2066 ring_bo_flags);
2067 if (!esgs_ring_bo)
2068 goto fail;
2069 } else {
2070 esgs_ring_bo = queue->esgs_ring_bo;
2071 esgs_ring_size = queue->esgs_ring_size;
2072 }
2073
2074 if (gsvs_ring_size > queue->gsvs_ring_size) {
2075 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2076 gsvs_ring_size,
2077 4096,
2078 RADEON_DOMAIN_VRAM,
2079 ring_bo_flags);
2080 if (!gsvs_ring_bo)
2081 goto fail;
2082 } else {
2083 gsvs_ring_bo = queue->gsvs_ring_bo;
2084 gsvs_ring_size = queue->gsvs_ring_size;
2085 }
2086
2087 if (add_tess_rings) {
2088 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2089 tess_offchip_ring_offset + tess_offchip_ring_size,
2090 256,
2091 RADEON_DOMAIN_VRAM,
2092 ring_bo_flags);
2093 if (!tess_rings_bo)
2094 goto fail;
2095 } else {
2096 tess_rings_bo = queue->tess_rings_bo;
2097 }
2098
2099 if (scratch_bo != queue->scratch_bo ||
2100 esgs_ring_bo != queue->esgs_ring_bo ||
2101 gsvs_ring_bo != queue->gsvs_ring_bo ||
2102 tess_rings_bo != queue->tess_rings_bo ||
2103 add_sample_positions) {
2104 uint32_t size = 0;
2105 if (gsvs_ring_bo || esgs_ring_bo ||
2106 tess_rings_bo || add_sample_positions) {
2107 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2108 if (add_sample_positions)
2109 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
2110 }
2111 else if (scratch_bo)
2112 size = 8; /* 2 dword */
2113
2114 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2115 size,
2116 4096,
2117 RADEON_DOMAIN_VRAM,
2118 RADEON_FLAG_CPU_ACCESS |
2119 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2120 RADEON_FLAG_READ_ONLY);
2121 if (!descriptor_bo)
2122 goto fail;
2123 } else
2124 descriptor_bo = queue->descriptor_bo;
2125
2126 for(int i = 0; i < 3; ++i) {
2127 struct radeon_winsys_cs *cs = NULL;
2128 cs = queue->device->ws->cs_create(queue->device->ws,
2129 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2130 if (!cs)
2131 goto fail;
2132
2133 dest_cs[i] = cs;
2134
2135 if (scratch_bo)
2136 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo, 8);
2137
2138 if (descriptor_bo != queue->descriptor_bo) {
2139 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2140
2141 if (scratch_bo) {
2142 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2143 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2144 S_008F04_SWIZZLE_ENABLE(1);
2145 map[0] = scratch_va;
2146 map[1] = rsrc1;
2147 }
2148
2149 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo ||
2150 add_sample_positions)
2151 fill_geom_tess_rings(queue, map, add_sample_positions,
2152 esgs_ring_size, esgs_ring_bo,
2153 gsvs_ring_size, gsvs_ring_bo,
2154 tess_factor_ring_size,
2155 tess_offchip_ring_offset,
2156 tess_offchip_ring_size,
2157 tess_rings_bo);
2158
2159 queue->device->ws->buffer_unmap(descriptor_bo);
2160 }
2161
2162 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2163 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2164 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2165 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2166 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2167 }
2168
2169 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2170 gsvs_ring_bo, gsvs_ring_size);
2171 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2172 tess_factor_ring_size, tess_rings_bo);
2173 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2174 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2175
2176 if (i == 0) {
2177 si_cs_emit_cache_flush(cs,
2178 queue->device->physical_device->rad_info.chip_class,
2179 NULL, 0,
2180 queue->queue_family_index == RING_COMPUTE &&
2181 queue->device->physical_device->rad_info.chip_class >= CIK,
2182 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2183 RADV_CMD_FLAG_INV_ICACHE |
2184 RADV_CMD_FLAG_INV_SMEM_L1 |
2185 RADV_CMD_FLAG_INV_VMEM_L1 |
2186 RADV_CMD_FLAG_INV_GLOBAL_L2);
2187 } else if (i == 1) {
2188 si_cs_emit_cache_flush(cs,
2189 queue->device->physical_device->rad_info.chip_class,
2190 NULL, 0,
2191 queue->queue_family_index == RING_COMPUTE &&
2192 queue->device->physical_device->rad_info.chip_class >= CIK,
2193 RADV_CMD_FLAG_INV_ICACHE |
2194 RADV_CMD_FLAG_INV_SMEM_L1 |
2195 RADV_CMD_FLAG_INV_VMEM_L1 |
2196 RADV_CMD_FLAG_INV_GLOBAL_L2);
2197 }
2198
2199 if (!queue->device->ws->cs_finalize(cs))
2200 goto fail;
2201 }
2202
2203 if (queue->initial_full_flush_preamble_cs)
2204 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2205
2206 if (queue->initial_preamble_cs)
2207 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2208
2209 if (queue->continue_preamble_cs)
2210 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2211
2212 queue->initial_full_flush_preamble_cs = dest_cs[0];
2213 queue->initial_preamble_cs = dest_cs[1];
2214 queue->continue_preamble_cs = dest_cs[2];
2215
2216 if (scratch_bo != queue->scratch_bo) {
2217 if (queue->scratch_bo)
2218 queue->device->ws->buffer_destroy(queue->scratch_bo);
2219 queue->scratch_bo = scratch_bo;
2220 queue->scratch_size = scratch_size;
2221 }
2222
2223 if (compute_scratch_bo != queue->compute_scratch_bo) {
2224 if (queue->compute_scratch_bo)
2225 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2226 queue->compute_scratch_bo = compute_scratch_bo;
2227 queue->compute_scratch_size = compute_scratch_size;
2228 }
2229
2230 if (esgs_ring_bo != queue->esgs_ring_bo) {
2231 if (queue->esgs_ring_bo)
2232 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2233 queue->esgs_ring_bo = esgs_ring_bo;
2234 queue->esgs_ring_size = esgs_ring_size;
2235 }
2236
2237 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2238 if (queue->gsvs_ring_bo)
2239 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2240 queue->gsvs_ring_bo = gsvs_ring_bo;
2241 queue->gsvs_ring_size = gsvs_ring_size;
2242 }
2243
2244 if (tess_rings_bo != queue->tess_rings_bo) {
2245 queue->tess_rings_bo = tess_rings_bo;
2246 queue->has_tess_rings = true;
2247 }
2248
2249 if (descriptor_bo != queue->descriptor_bo) {
2250 if (queue->descriptor_bo)
2251 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2252
2253 queue->descriptor_bo = descriptor_bo;
2254 }
2255
2256 if (add_sample_positions)
2257 queue->has_sample_positions = true;
2258
2259 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2260 *initial_preamble_cs = queue->initial_preamble_cs;
2261 *continue_preamble_cs = queue->continue_preamble_cs;
2262 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2263 *continue_preamble_cs = NULL;
2264 return VK_SUCCESS;
2265 fail:
2266 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2267 if (dest_cs[i])
2268 queue->device->ws->cs_destroy(dest_cs[i]);
2269 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2270 queue->device->ws->buffer_destroy(descriptor_bo);
2271 if (scratch_bo && scratch_bo != queue->scratch_bo)
2272 queue->device->ws->buffer_destroy(scratch_bo);
2273 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2274 queue->device->ws->buffer_destroy(compute_scratch_bo);
2275 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2276 queue->device->ws->buffer_destroy(esgs_ring_bo);
2277 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2278 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2279 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2280 queue->device->ws->buffer_destroy(tess_rings_bo);
2281 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2282 }
2283
2284 static VkResult radv_alloc_sem_counts(struct radv_winsys_sem_counts *counts,
2285 int num_sems,
2286 const VkSemaphore *sems,
2287 VkFence _fence,
2288 bool reset_temp)
2289 {
2290 int syncobj_idx = 0, sem_idx = 0;
2291
2292 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2293 return VK_SUCCESS;
2294
2295 for (uint32_t i = 0; i < num_sems; i++) {
2296 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2297
2298 if (sem->temp_syncobj || sem->syncobj)
2299 counts->syncobj_count++;
2300 else
2301 counts->sem_count++;
2302 }
2303
2304 if (_fence != VK_NULL_HANDLE) {
2305 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2306 if (fence->temp_syncobj || fence->syncobj)
2307 counts->syncobj_count++;
2308 }
2309
2310 if (counts->syncobj_count) {
2311 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2312 if (!counts->syncobj)
2313 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2314 }
2315
2316 if (counts->sem_count) {
2317 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2318 if (!counts->sem) {
2319 free(counts->syncobj);
2320 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2321 }
2322 }
2323
2324 for (uint32_t i = 0; i < num_sems; i++) {
2325 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2326
2327 if (sem->temp_syncobj) {
2328 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2329 }
2330 else if (sem->syncobj)
2331 counts->syncobj[syncobj_idx++] = sem->syncobj;
2332 else {
2333 assert(sem->sem);
2334 counts->sem[sem_idx++] = sem->sem;
2335 }
2336 }
2337
2338 if (_fence != VK_NULL_HANDLE) {
2339 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2340 if (fence->temp_syncobj)
2341 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2342 else if (fence->syncobj)
2343 counts->syncobj[syncobj_idx++] = fence->syncobj;
2344 }
2345
2346 return VK_SUCCESS;
2347 }
2348
2349 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2350 {
2351 free(sem_info->wait.syncobj);
2352 free(sem_info->wait.sem);
2353 free(sem_info->signal.syncobj);
2354 free(sem_info->signal.sem);
2355 }
2356
2357
2358 static void radv_free_temp_syncobjs(struct radv_device *device,
2359 int num_sems,
2360 const VkSemaphore *sems)
2361 {
2362 for (uint32_t i = 0; i < num_sems; i++) {
2363 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2364
2365 if (sem->temp_syncobj) {
2366 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2367 sem->temp_syncobj = 0;
2368 }
2369 }
2370 }
2371
2372 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
2373 int num_wait_sems,
2374 const VkSemaphore *wait_sems,
2375 int num_signal_sems,
2376 const VkSemaphore *signal_sems,
2377 VkFence fence)
2378 {
2379 VkResult ret;
2380 memset(sem_info, 0, sizeof(*sem_info));
2381
2382 ret = radv_alloc_sem_counts(&sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2383 if (ret)
2384 return ret;
2385 ret = radv_alloc_sem_counts(&sem_info->signal, num_signal_sems, signal_sems, fence, false);
2386 if (ret)
2387 radv_free_sem_info(sem_info);
2388
2389 /* caller can override these */
2390 sem_info->cs_emit_wait = true;
2391 sem_info->cs_emit_signal = true;
2392 return ret;
2393 }
2394
2395 /* Signals fence as soon as all the work currently put on queue is done. */
2396 static VkResult radv_signal_fence(struct radv_queue *queue,
2397 struct radv_fence *fence)
2398 {
2399 int ret;
2400 VkResult result;
2401 struct radv_winsys_sem_info sem_info;
2402
2403 result = radv_alloc_sem_info(&sem_info, 0, NULL, 0, NULL,
2404 radv_fence_to_handle(fence));
2405 if (result != VK_SUCCESS)
2406 return result;
2407
2408 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2409 &queue->device->empty_cs[queue->queue_family_index],
2410 1, NULL, NULL, &sem_info, NULL,
2411 false, fence->fence);
2412 radv_free_sem_info(&sem_info);
2413
2414 /* TODO: find a better error */
2415 if (ret)
2416 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2417
2418 return VK_SUCCESS;
2419 }
2420
2421 VkResult radv_QueueSubmit(
2422 VkQueue _queue,
2423 uint32_t submitCount,
2424 const VkSubmitInfo* pSubmits,
2425 VkFence _fence)
2426 {
2427 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2428 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2429 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2430 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2431 int ret;
2432 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2433 uint32_t scratch_size = 0;
2434 uint32_t compute_scratch_size = 0;
2435 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2436 struct radeon_winsys_cs *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2437 VkResult result;
2438 bool fence_emitted = false;
2439 bool tess_rings_needed = false;
2440 bool sample_positions_needed = false;
2441
2442 /* Do this first so failing to allocate scratch buffers can't result in
2443 * partially executed submissions. */
2444 for (uint32_t i = 0; i < submitCount; i++) {
2445 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2446 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2447 pSubmits[i].pCommandBuffers[j]);
2448
2449 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2450 compute_scratch_size = MAX2(compute_scratch_size,
2451 cmd_buffer->compute_scratch_size_needed);
2452 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2453 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2454 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2455 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2456 }
2457 }
2458
2459 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2460 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2461 sample_positions_needed, &initial_flush_preamble_cs,
2462 &initial_preamble_cs, &continue_preamble_cs);
2463 if (result != VK_SUCCESS)
2464 return result;
2465
2466 for (uint32_t i = 0; i < submitCount; i++) {
2467 struct radeon_winsys_cs **cs_array;
2468 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2469 bool can_patch = true;
2470 uint32_t advance;
2471 struct radv_winsys_sem_info sem_info;
2472
2473 result = radv_alloc_sem_info(&sem_info,
2474 pSubmits[i].waitSemaphoreCount,
2475 pSubmits[i].pWaitSemaphores,
2476 pSubmits[i].signalSemaphoreCount,
2477 pSubmits[i].pSignalSemaphores,
2478 _fence);
2479 if (result != VK_SUCCESS)
2480 return result;
2481
2482 if (!pSubmits[i].commandBufferCount) {
2483 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2484 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2485 &queue->device->empty_cs[queue->queue_family_index],
2486 1, NULL, NULL,
2487 &sem_info, NULL,
2488 false, base_fence);
2489 if (ret) {
2490 radv_loge("failed to submit CS %d\n", i);
2491 abort();
2492 }
2493 fence_emitted = true;
2494 }
2495 radv_free_sem_info(&sem_info);
2496 continue;
2497 }
2498
2499 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
2500 (pSubmits[i].commandBufferCount));
2501
2502 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2503 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2504 pSubmits[i].pCommandBuffers[j]);
2505 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2506
2507 cs_array[j] = cmd_buffer->cs;
2508 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2509 can_patch = false;
2510
2511 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2512 }
2513
2514 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2515 struct radeon_winsys_cs *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2516 const struct radv_winsys_bo_list *bo_list = NULL;
2517
2518 advance = MIN2(max_cs_submission,
2519 pSubmits[i].commandBufferCount - j);
2520
2521 if (queue->device->trace_bo)
2522 *queue->device->trace_id_ptr = 0;
2523
2524 sem_info.cs_emit_wait = j == 0;
2525 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2526
2527 if (unlikely(queue->device->use_global_bo_list)) {
2528 pthread_mutex_lock(&queue->device->bo_list.mutex);
2529 bo_list = &queue->device->bo_list.list;
2530 }
2531
2532 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2533 advance, initial_preamble, continue_preamble_cs,
2534 &sem_info, bo_list,
2535 can_patch, base_fence);
2536
2537 if (unlikely(queue->device->use_global_bo_list))
2538 pthread_mutex_unlock(&queue->device->bo_list.mutex);
2539
2540 if (ret) {
2541 radv_loge("failed to submit CS %d\n", i);
2542 abort();
2543 }
2544 fence_emitted = true;
2545 if (queue->device->trace_bo) {
2546 radv_check_gpu_hangs(queue, cs_array[j]);
2547 }
2548 }
2549
2550 radv_free_temp_syncobjs(queue->device,
2551 pSubmits[i].waitSemaphoreCount,
2552 pSubmits[i].pWaitSemaphores);
2553 radv_free_sem_info(&sem_info);
2554 free(cs_array);
2555 }
2556
2557 if (fence) {
2558 if (!fence_emitted) {
2559 radv_signal_fence(queue, fence);
2560 }
2561 fence->submitted = true;
2562 }
2563
2564 return VK_SUCCESS;
2565 }
2566
2567 VkResult radv_QueueWaitIdle(
2568 VkQueue _queue)
2569 {
2570 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2571
2572 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2573 radv_queue_family_to_ring(queue->queue_family_index),
2574 queue->queue_idx);
2575 return VK_SUCCESS;
2576 }
2577
2578 VkResult radv_DeviceWaitIdle(
2579 VkDevice _device)
2580 {
2581 RADV_FROM_HANDLE(radv_device, device, _device);
2582
2583 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2584 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2585 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2586 }
2587 }
2588 return VK_SUCCESS;
2589 }
2590
2591 VkResult radv_EnumerateInstanceExtensionProperties(
2592 const char* pLayerName,
2593 uint32_t* pPropertyCount,
2594 VkExtensionProperties* pProperties)
2595 {
2596 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2597
2598 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
2599 if (radv_supported_instance_extensions.extensions[i]) {
2600 vk_outarray_append(&out, prop) {
2601 *prop = radv_instance_extensions[i];
2602 }
2603 }
2604 }
2605
2606 return vk_outarray_status(&out);
2607 }
2608
2609 VkResult radv_EnumerateDeviceExtensionProperties(
2610 VkPhysicalDevice physicalDevice,
2611 const char* pLayerName,
2612 uint32_t* pPropertyCount,
2613 VkExtensionProperties* pProperties)
2614 {
2615 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2616 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2617
2618 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
2619 if (device->supported_extensions.extensions[i]) {
2620 vk_outarray_append(&out, prop) {
2621 *prop = radv_device_extensions[i];
2622 }
2623 }
2624 }
2625
2626 return vk_outarray_status(&out);
2627 }
2628
2629 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2630 VkInstance _instance,
2631 const char* pName)
2632 {
2633 RADV_FROM_HANDLE(radv_instance, instance, _instance);
2634
2635 return radv_lookup_entrypoint_checked(pName,
2636 instance ? instance->apiVersion : 0,
2637 instance ? &instance->enabled_extensions : NULL,
2638 NULL);
2639 }
2640
2641 /* The loader wants us to expose a second GetInstanceProcAddr function
2642 * to work around certain LD_PRELOAD issues seen in apps.
2643 */
2644 PUBLIC
2645 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2646 VkInstance instance,
2647 const char* pName);
2648
2649 PUBLIC
2650 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2651 VkInstance instance,
2652 const char* pName)
2653 {
2654 return radv_GetInstanceProcAddr(instance, pName);
2655 }
2656
2657 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2658 VkDevice _device,
2659 const char* pName)
2660 {
2661 RADV_FROM_HANDLE(radv_device, device, _device);
2662
2663 return radv_lookup_entrypoint_checked(pName,
2664 device->instance->apiVersion,
2665 &device->instance->enabled_extensions,
2666 &device->enabled_extensions);
2667 }
2668
2669 bool radv_get_memory_fd(struct radv_device *device,
2670 struct radv_device_memory *memory,
2671 int *pFD)
2672 {
2673 struct radeon_bo_metadata metadata;
2674
2675 if (memory->image) {
2676 radv_init_metadata(device, memory->image, &metadata);
2677 device->ws->buffer_set_metadata(memory->bo, &metadata);
2678 }
2679
2680 return device->ws->buffer_get_fd(device->ws, memory->bo,
2681 pFD);
2682 }
2683
2684 static VkResult radv_alloc_memory(struct radv_device *device,
2685 const VkMemoryAllocateInfo* pAllocateInfo,
2686 const VkAllocationCallbacks* pAllocator,
2687 VkDeviceMemory* pMem)
2688 {
2689 struct radv_device_memory *mem;
2690 VkResult result;
2691 enum radeon_bo_domain domain;
2692 uint32_t flags = 0;
2693 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
2694
2695 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2696
2697 if (pAllocateInfo->allocationSize == 0) {
2698 /* Apparently, this is allowed */
2699 *pMem = VK_NULL_HANDLE;
2700 return VK_SUCCESS;
2701 }
2702
2703 const VkImportMemoryFdInfoKHR *import_info =
2704 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2705 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2706 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2707 const VkExportMemoryAllocateInfoKHR *export_info =
2708 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO_KHR);
2709 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
2710 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
2711
2712 const struct wsi_memory_allocate_info *wsi_info =
2713 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
2714
2715 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2716 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2717 if (mem == NULL)
2718 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2719
2720 if (wsi_info && wsi_info->implicit_sync)
2721 flags |= RADEON_FLAG_IMPLICIT_SYNC;
2722
2723 if (dedicate_info) {
2724 mem->image = radv_image_from_handle(dedicate_info->image);
2725 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2726 } else {
2727 mem->image = NULL;
2728 mem->buffer = NULL;
2729 }
2730
2731 mem->user_ptr = NULL;
2732
2733 if (import_info) {
2734 assert(import_info->handleType ==
2735 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
2736 import_info->handleType ==
2737 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
2738 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2739 NULL, NULL);
2740 if (!mem->bo) {
2741 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2742 goto fail;
2743 } else {
2744 close(import_info->fd);
2745 }
2746 } else if (host_ptr_info) {
2747 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
2748 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
2749 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
2750 pAllocateInfo->allocationSize);
2751 if (!mem->bo) {
2752 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2753 goto fail;
2754 } else {
2755 mem->user_ptr = host_ptr_info->pHostPointer;
2756 }
2757 } else {
2758 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2759 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2760 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
2761 domain = RADEON_DOMAIN_GTT;
2762 else
2763 domain = RADEON_DOMAIN_VRAM;
2764
2765 if (mem_type_index == RADV_MEM_TYPE_VRAM)
2766 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2767 else
2768 flags |= RADEON_FLAG_CPU_ACCESS;
2769
2770 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2771 flags |= RADEON_FLAG_GTT_WC;
2772
2773 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
2774 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
2775
2776 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2777 domain, flags);
2778
2779 if (!mem->bo) {
2780 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2781 goto fail;
2782 }
2783 mem->type_index = mem_type_index;
2784 }
2785
2786 result = radv_bo_list_add(device, mem->bo);
2787 if (result != VK_SUCCESS)
2788 goto fail_bo;
2789
2790 *pMem = radv_device_memory_to_handle(mem);
2791
2792 return VK_SUCCESS;
2793
2794 fail_bo:
2795 device->ws->buffer_destroy(mem->bo);
2796 fail:
2797 vk_free2(&device->alloc, pAllocator, mem);
2798
2799 return result;
2800 }
2801
2802 VkResult radv_AllocateMemory(
2803 VkDevice _device,
2804 const VkMemoryAllocateInfo* pAllocateInfo,
2805 const VkAllocationCallbacks* pAllocator,
2806 VkDeviceMemory* pMem)
2807 {
2808 RADV_FROM_HANDLE(radv_device, device, _device);
2809 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
2810 }
2811
2812 void radv_FreeMemory(
2813 VkDevice _device,
2814 VkDeviceMemory _mem,
2815 const VkAllocationCallbacks* pAllocator)
2816 {
2817 RADV_FROM_HANDLE(radv_device, device, _device);
2818 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2819
2820 if (mem == NULL)
2821 return;
2822
2823 radv_bo_list_remove(device, mem->bo);
2824 device->ws->buffer_destroy(mem->bo);
2825 mem->bo = NULL;
2826
2827 vk_free2(&device->alloc, pAllocator, mem);
2828 }
2829
2830 VkResult radv_MapMemory(
2831 VkDevice _device,
2832 VkDeviceMemory _memory,
2833 VkDeviceSize offset,
2834 VkDeviceSize size,
2835 VkMemoryMapFlags flags,
2836 void** ppData)
2837 {
2838 RADV_FROM_HANDLE(radv_device, device, _device);
2839 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2840
2841 if (mem == NULL) {
2842 *ppData = NULL;
2843 return VK_SUCCESS;
2844 }
2845
2846 if (mem->user_ptr)
2847 *ppData = mem->user_ptr;
2848 else
2849 *ppData = device->ws->buffer_map(mem->bo);
2850
2851 if (*ppData) {
2852 *ppData += offset;
2853 return VK_SUCCESS;
2854 }
2855
2856 return vk_error(VK_ERROR_MEMORY_MAP_FAILED);
2857 }
2858
2859 void radv_UnmapMemory(
2860 VkDevice _device,
2861 VkDeviceMemory _memory)
2862 {
2863 RADV_FROM_HANDLE(radv_device, device, _device);
2864 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2865
2866 if (mem == NULL)
2867 return;
2868
2869 if (mem->user_ptr == NULL)
2870 device->ws->buffer_unmap(mem->bo);
2871 }
2872
2873 VkResult radv_FlushMappedMemoryRanges(
2874 VkDevice _device,
2875 uint32_t memoryRangeCount,
2876 const VkMappedMemoryRange* pMemoryRanges)
2877 {
2878 return VK_SUCCESS;
2879 }
2880
2881 VkResult radv_InvalidateMappedMemoryRanges(
2882 VkDevice _device,
2883 uint32_t memoryRangeCount,
2884 const VkMappedMemoryRange* pMemoryRanges)
2885 {
2886 return VK_SUCCESS;
2887 }
2888
2889 void radv_GetBufferMemoryRequirements(
2890 VkDevice _device,
2891 VkBuffer _buffer,
2892 VkMemoryRequirements* pMemoryRequirements)
2893 {
2894 RADV_FROM_HANDLE(radv_device, device, _device);
2895 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2896
2897 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2898
2899 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2900 pMemoryRequirements->alignment = 4096;
2901 else
2902 pMemoryRequirements->alignment = 16;
2903
2904 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2905 }
2906
2907 void radv_GetBufferMemoryRequirements2(
2908 VkDevice device,
2909 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2910 VkMemoryRequirements2KHR* pMemoryRequirements)
2911 {
2912 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2913 &pMemoryRequirements->memoryRequirements);
2914 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
2915 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2916 switch (ext->sType) {
2917 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2918 VkMemoryDedicatedRequirementsKHR *req =
2919 (VkMemoryDedicatedRequirementsKHR *) ext;
2920 req->requiresDedicatedAllocation = buffer->shareable;
2921 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2922 break;
2923 }
2924 default:
2925 break;
2926 }
2927 }
2928 }
2929
2930 void radv_GetImageMemoryRequirements(
2931 VkDevice _device,
2932 VkImage _image,
2933 VkMemoryRequirements* pMemoryRequirements)
2934 {
2935 RADV_FROM_HANDLE(radv_device, device, _device);
2936 RADV_FROM_HANDLE(radv_image, image, _image);
2937
2938 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2939
2940 pMemoryRequirements->size = image->size;
2941 pMemoryRequirements->alignment = image->alignment;
2942 }
2943
2944 void radv_GetImageMemoryRequirements2(
2945 VkDevice device,
2946 const VkImageMemoryRequirementsInfo2KHR* pInfo,
2947 VkMemoryRequirements2KHR* pMemoryRequirements)
2948 {
2949 radv_GetImageMemoryRequirements(device, pInfo->image,
2950 &pMemoryRequirements->memoryRequirements);
2951
2952 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
2953
2954 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2955 switch (ext->sType) {
2956 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2957 VkMemoryDedicatedRequirementsKHR *req =
2958 (VkMemoryDedicatedRequirementsKHR *) ext;
2959 req->requiresDedicatedAllocation = image->shareable;
2960 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2961 break;
2962 }
2963 default:
2964 break;
2965 }
2966 }
2967 }
2968
2969 void radv_GetImageSparseMemoryRequirements(
2970 VkDevice device,
2971 VkImage image,
2972 uint32_t* pSparseMemoryRequirementCount,
2973 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2974 {
2975 stub();
2976 }
2977
2978 void radv_GetImageSparseMemoryRequirements2(
2979 VkDevice device,
2980 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
2981 uint32_t* pSparseMemoryRequirementCount,
2982 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
2983 {
2984 stub();
2985 }
2986
2987 void radv_GetDeviceMemoryCommitment(
2988 VkDevice device,
2989 VkDeviceMemory memory,
2990 VkDeviceSize* pCommittedMemoryInBytes)
2991 {
2992 *pCommittedMemoryInBytes = 0;
2993 }
2994
2995 VkResult radv_BindBufferMemory2(VkDevice device,
2996 uint32_t bindInfoCount,
2997 const VkBindBufferMemoryInfoKHR *pBindInfos)
2998 {
2999 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3000 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3001 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3002
3003 if (mem) {
3004 buffer->bo = mem->bo;
3005 buffer->offset = pBindInfos[i].memoryOffset;
3006 } else {
3007 buffer->bo = NULL;
3008 }
3009 }
3010 return VK_SUCCESS;
3011 }
3012
3013 VkResult radv_BindBufferMemory(
3014 VkDevice device,
3015 VkBuffer buffer,
3016 VkDeviceMemory memory,
3017 VkDeviceSize memoryOffset)
3018 {
3019 const VkBindBufferMemoryInfoKHR info = {
3020 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3021 .buffer = buffer,
3022 .memory = memory,
3023 .memoryOffset = memoryOffset
3024 };
3025
3026 return radv_BindBufferMemory2(device, 1, &info);
3027 }
3028
3029 VkResult radv_BindImageMemory2(VkDevice device,
3030 uint32_t bindInfoCount,
3031 const VkBindImageMemoryInfoKHR *pBindInfos)
3032 {
3033 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3034 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3035 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3036
3037 if (mem) {
3038 image->bo = mem->bo;
3039 image->offset = pBindInfos[i].memoryOffset;
3040 } else {
3041 image->bo = NULL;
3042 image->offset = 0;
3043 }
3044 }
3045 return VK_SUCCESS;
3046 }
3047
3048
3049 VkResult radv_BindImageMemory(
3050 VkDevice device,
3051 VkImage image,
3052 VkDeviceMemory memory,
3053 VkDeviceSize memoryOffset)
3054 {
3055 const VkBindImageMemoryInfoKHR info = {
3056 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3057 .image = image,
3058 .memory = memory,
3059 .memoryOffset = memoryOffset
3060 };
3061
3062 return radv_BindImageMemory2(device, 1, &info);
3063 }
3064
3065
3066 static void
3067 radv_sparse_buffer_bind_memory(struct radv_device *device,
3068 const VkSparseBufferMemoryBindInfo *bind)
3069 {
3070 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3071
3072 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3073 struct radv_device_memory *mem = NULL;
3074
3075 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3076 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3077
3078 device->ws->buffer_virtual_bind(buffer->bo,
3079 bind->pBinds[i].resourceOffset,
3080 bind->pBinds[i].size,
3081 mem ? mem->bo : NULL,
3082 bind->pBinds[i].memoryOffset);
3083 }
3084 }
3085
3086 static void
3087 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3088 const VkSparseImageOpaqueMemoryBindInfo *bind)
3089 {
3090 RADV_FROM_HANDLE(radv_image, image, bind->image);
3091
3092 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3093 struct radv_device_memory *mem = NULL;
3094
3095 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3096 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3097
3098 device->ws->buffer_virtual_bind(image->bo,
3099 bind->pBinds[i].resourceOffset,
3100 bind->pBinds[i].size,
3101 mem ? mem->bo : NULL,
3102 bind->pBinds[i].memoryOffset);
3103 }
3104 }
3105
3106 VkResult radv_QueueBindSparse(
3107 VkQueue _queue,
3108 uint32_t bindInfoCount,
3109 const VkBindSparseInfo* pBindInfo,
3110 VkFence _fence)
3111 {
3112 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3113 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3114 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3115 bool fence_emitted = false;
3116
3117 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3118 struct radv_winsys_sem_info sem_info;
3119 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3120 radv_sparse_buffer_bind_memory(queue->device,
3121 pBindInfo[i].pBufferBinds + j);
3122 }
3123
3124 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3125 radv_sparse_image_opaque_bind_memory(queue->device,
3126 pBindInfo[i].pImageOpaqueBinds + j);
3127 }
3128
3129 VkResult result;
3130 result = radv_alloc_sem_info(&sem_info,
3131 pBindInfo[i].waitSemaphoreCount,
3132 pBindInfo[i].pWaitSemaphores,
3133 pBindInfo[i].signalSemaphoreCount,
3134 pBindInfo[i].pSignalSemaphores,
3135 _fence);
3136 if (result != VK_SUCCESS)
3137 return result;
3138
3139 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3140 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3141 &queue->device->empty_cs[queue->queue_family_index],
3142 1, NULL, NULL,
3143 &sem_info, NULL,
3144 false, base_fence);
3145 fence_emitted = true;
3146 if (fence)
3147 fence->submitted = true;
3148 }
3149
3150 radv_free_sem_info(&sem_info);
3151
3152 }
3153
3154 if (fence) {
3155 if (!fence_emitted) {
3156 radv_signal_fence(queue, fence);
3157 }
3158 fence->submitted = true;
3159 }
3160
3161 return VK_SUCCESS;
3162 }
3163
3164 VkResult radv_CreateFence(
3165 VkDevice _device,
3166 const VkFenceCreateInfo* pCreateInfo,
3167 const VkAllocationCallbacks* pAllocator,
3168 VkFence* pFence)
3169 {
3170 RADV_FROM_HANDLE(radv_device, device, _device);
3171 const VkExportFenceCreateInfoKHR *export =
3172 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO_KHR);
3173 VkExternalFenceHandleTypeFlagsKHR handleTypes =
3174 export ? export->handleTypes : 0;
3175
3176 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3177 sizeof(*fence), 8,
3178 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3179
3180 if (!fence)
3181 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3182
3183 fence->submitted = false;
3184 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3185 fence->temp_syncobj = 0;
3186 if (device->always_use_syncobj || handleTypes) {
3187 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3188 if (ret) {
3189 vk_free2(&device->alloc, pAllocator, fence);
3190 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3191 }
3192 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3193 device->ws->signal_syncobj(device->ws, fence->syncobj);
3194 }
3195 fence->fence = NULL;
3196 } else {
3197 fence->fence = device->ws->create_fence();
3198 if (!fence->fence) {
3199 vk_free2(&device->alloc, pAllocator, fence);
3200 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3201 }
3202 fence->syncobj = 0;
3203 }
3204
3205 *pFence = radv_fence_to_handle(fence);
3206
3207 return VK_SUCCESS;
3208 }
3209
3210 void radv_DestroyFence(
3211 VkDevice _device,
3212 VkFence _fence,
3213 const VkAllocationCallbacks* pAllocator)
3214 {
3215 RADV_FROM_HANDLE(radv_device, device, _device);
3216 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3217
3218 if (!fence)
3219 return;
3220
3221 if (fence->temp_syncobj)
3222 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3223 if (fence->syncobj)
3224 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3225 if (fence->fence)
3226 device->ws->destroy_fence(fence->fence);
3227 vk_free2(&device->alloc, pAllocator, fence);
3228 }
3229
3230
3231 static uint64_t radv_get_current_time()
3232 {
3233 struct timespec tv;
3234 clock_gettime(CLOCK_MONOTONIC, &tv);
3235 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3236 }
3237
3238 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3239 {
3240 uint64_t current_time = radv_get_current_time();
3241
3242 timeout = MIN2(UINT64_MAX - current_time, timeout);
3243
3244 return current_time + timeout;
3245 }
3246
3247
3248 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3249 {
3250 for (uint32_t i = 0; i < fenceCount; ++i) {
3251 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3252 if (fence->syncobj || fence->temp_syncobj || (!fence->signalled && !fence->submitted))
3253 return false;
3254 }
3255 return true;
3256 }
3257
3258 VkResult radv_WaitForFences(
3259 VkDevice _device,
3260 uint32_t fenceCount,
3261 const VkFence* pFences,
3262 VkBool32 waitAll,
3263 uint64_t timeout)
3264 {
3265 RADV_FROM_HANDLE(radv_device, device, _device);
3266 timeout = radv_get_absolute_timeout(timeout);
3267
3268 if (device->always_use_syncobj) {
3269 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3270 if (!handles)
3271 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3272
3273 for (uint32_t i = 0; i < fenceCount; ++i) {
3274 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3275 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3276 }
3277
3278 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3279
3280 free(handles);
3281 return success ? VK_SUCCESS : VK_TIMEOUT;
3282 }
3283
3284 if (!waitAll && fenceCount > 1) {
3285 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3286 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3287 uint32_t wait_count = 0;
3288 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3289 if (!fences)
3290 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3291
3292 for (uint32_t i = 0; i < fenceCount; ++i) {
3293 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3294
3295 if (fence->signalled) {
3296 free(fences);
3297 return VK_SUCCESS;
3298 }
3299
3300 fences[wait_count++] = fence->fence;
3301 }
3302
3303 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3304 waitAll, timeout - radv_get_current_time());
3305
3306 free(fences);
3307 return success ? VK_SUCCESS : VK_TIMEOUT;
3308 }
3309
3310 while(radv_get_current_time() <= timeout) {
3311 for (uint32_t i = 0; i < fenceCount; ++i) {
3312 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3313 return VK_SUCCESS;
3314 }
3315 }
3316 return VK_TIMEOUT;
3317 }
3318
3319 for (uint32_t i = 0; i < fenceCount; ++i) {
3320 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3321 bool expired = false;
3322
3323 if (fence->temp_syncobj) {
3324 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3325 return VK_TIMEOUT;
3326 continue;
3327 }
3328
3329 if (fence->syncobj) {
3330 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3331 return VK_TIMEOUT;
3332 continue;
3333 }
3334
3335 if (fence->signalled)
3336 continue;
3337
3338 if (!fence->submitted) {
3339 while(radv_get_current_time() <= timeout && !fence->submitted)
3340 /* Do nothing */;
3341
3342 if (!fence->submitted)
3343 return VK_TIMEOUT;
3344
3345 /* Recheck as it may have been set by submitting operations. */
3346 if (fence->signalled)
3347 continue;
3348 }
3349
3350 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
3351 if (!expired)
3352 return VK_TIMEOUT;
3353
3354 fence->signalled = true;
3355 }
3356
3357 return VK_SUCCESS;
3358 }
3359
3360 VkResult radv_ResetFences(VkDevice _device,
3361 uint32_t fenceCount,
3362 const VkFence *pFences)
3363 {
3364 RADV_FROM_HANDLE(radv_device, device, _device);
3365
3366 for (unsigned i = 0; i < fenceCount; ++i) {
3367 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3368 fence->submitted = fence->signalled = false;
3369
3370 /* Per spec, we first restore the permanent payload, and then reset, so
3371 * having a temp syncobj should not skip resetting the permanent syncobj. */
3372 if (fence->temp_syncobj) {
3373 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3374 fence->temp_syncobj = 0;
3375 }
3376
3377 if (fence->syncobj) {
3378 device->ws->reset_syncobj(device->ws, fence->syncobj);
3379 }
3380 }
3381
3382 return VK_SUCCESS;
3383 }
3384
3385 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3386 {
3387 RADV_FROM_HANDLE(radv_device, device, _device);
3388 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3389
3390 if (fence->temp_syncobj) {
3391 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3392 return success ? VK_SUCCESS : VK_NOT_READY;
3393 }
3394
3395 if (fence->syncobj) {
3396 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3397 return success ? VK_SUCCESS : VK_NOT_READY;
3398 }
3399
3400 if (fence->signalled)
3401 return VK_SUCCESS;
3402 if (!fence->submitted)
3403 return VK_NOT_READY;
3404 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3405 return VK_NOT_READY;
3406
3407 return VK_SUCCESS;
3408 }
3409
3410
3411 // Queue semaphore functions
3412
3413 VkResult radv_CreateSemaphore(
3414 VkDevice _device,
3415 const VkSemaphoreCreateInfo* pCreateInfo,
3416 const VkAllocationCallbacks* pAllocator,
3417 VkSemaphore* pSemaphore)
3418 {
3419 RADV_FROM_HANDLE(radv_device, device, _device);
3420 const VkExportSemaphoreCreateInfoKHR *export =
3421 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
3422 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
3423 export ? export->handleTypes : 0;
3424
3425 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3426 sizeof(*sem), 8,
3427 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3428 if (!sem)
3429 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3430
3431 sem->temp_syncobj = 0;
3432 /* create a syncobject if we are going to export this semaphore */
3433 if (device->always_use_syncobj || handleTypes) {
3434 assert (device->physical_device->rad_info.has_syncobj);
3435 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3436 if (ret) {
3437 vk_free2(&device->alloc, pAllocator, sem);
3438 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3439 }
3440 sem->sem = NULL;
3441 } else {
3442 sem->sem = device->ws->create_sem(device->ws);
3443 if (!sem->sem) {
3444 vk_free2(&device->alloc, pAllocator, sem);
3445 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3446 }
3447 sem->syncobj = 0;
3448 }
3449
3450 *pSemaphore = radv_semaphore_to_handle(sem);
3451 return VK_SUCCESS;
3452 }
3453
3454 void radv_DestroySemaphore(
3455 VkDevice _device,
3456 VkSemaphore _semaphore,
3457 const VkAllocationCallbacks* pAllocator)
3458 {
3459 RADV_FROM_HANDLE(radv_device, device, _device);
3460 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3461 if (!_semaphore)
3462 return;
3463
3464 if (sem->syncobj)
3465 device->ws->destroy_syncobj(device->ws, sem->syncobj);
3466 else
3467 device->ws->destroy_sem(sem->sem);
3468 vk_free2(&device->alloc, pAllocator, sem);
3469 }
3470
3471 VkResult radv_CreateEvent(
3472 VkDevice _device,
3473 const VkEventCreateInfo* pCreateInfo,
3474 const VkAllocationCallbacks* pAllocator,
3475 VkEvent* pEvent)
3476 {
3477 RADV_FROM_HANDLE(radv_device, device, _device);
3478 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
3479 sizeof(*event), 8,
3480 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3481
3482 if (!event)
3483 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3484
3485 event->bo = device->ws->buffer_create(device->ws, 8, 8,
3486 RADEON_DOMAIN_GTT,
3487 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
3488 if (!event->bo) {
3489 vk_free2(&device->alloc, pAllocator, event);
3490 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
3491 }
3492
3493 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
3494
3495 *pEvent = radv_event_to_handle(event);
3496
3497 return VK_SUCCESS;
3498 }
3499
3500 void radv_DestroyEvent(
3501 VkDevice _device,
3502 VkEvent _event,
3503 const VkAllocationCallbacks* pAllocator)
3504 {
3505 RADV_FROM_HANDLE(radv_device, device, _device);
3506 RADV_FROM_HANDLE(radv_event, event, _event);
3507
3508 if (!event)
3509 return;
3510 device->ws->buffer_destroy(event->bo);
3511 vk_free2(&device->alloc, pAllocator, event);
3512 }
3513
3514 VkResult radv_GetEventStatus(
3515 VkDevice _device,
3516 VkEvent _event)
3517 {
3518 RADV_FROM_HANDLE(radv_event, event, _event);
3519
3520 if (*event->map == 1)
3521 return VK_EVENT_SET;
3522 return VK_EVENT_RESET;
3523 }
3524
3525 VkResult radv_SetEvent(
3526 VkDevice _device,
3527 VkEvent _event)
3528 {
3529 RADV_FROM_HANDLE(radv_event, event, _event);
3530 *event->map = 1;
3531
3532 return VK_SUCCESS;
3533 }
3534
3535 VkResult radv_ResetEvent(
3536 VkDevice _device,
3537 VkEvent _event)
3538 {
3539 RADV_FROM_HANDLE(radv_event, event, _event);
3540 *event->map = 0;
3541
3542 return VK_SUCCESS;
3543 }
3544
3545 VkResult radv_CreateBuffer(
3546 VkDevice _device,
3547 const VkBufferCreateInfo* pCreateInfo,
3548 const VkAllocationCallbacks* pAllocator,
3549 VkBuffer* pBuffer)
3550 {
3551 RADV_FROM_HANDLE(radv_device, device, _device);
3552 struct radv_buffer *buffer;
3553
3554 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
3555
3556 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
3557 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3558 if (buffer == NULL)
3559 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3560
3561 buffer->size = pCreateInfo->size;
3562 buffer->usage = pCreateInfo->usage;
3563 buffer->bo = NULL;
3564 buffer->offset = 0;
3565 buffer->flags = pCreateInfo->flags;
3566
3567 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
3568 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR) != NULL;
3569
3570 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
3571 buffer->bo = device->ws->buffer_create(device->ws,
3572 align64(buffer->size, 4096),
3573 4096, 0, RADEON_FLAG_VIRTUAL);
3574 if (!buffer->bo) {
3575 vk_free2(&device->alloc, pAllocator, buffer);
3576 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
3577 }
3578 }
3579
3580 *pBuffer = radv_buffer_to_handle(buffer);
3581
3582 return VK_SUCCESS;
3583 }
3584
3585 void radv_DestroyBuffer(
3586 VkDevice _device,
3587 VkBuffer _buffer,
3588 const VkAllocationCallbacks* pAllocator)
3589 {
3590 RADV_FROM_HANDLE(radv_device, device, _device);
3591 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3592
3593 if (!buffer)
3594 return;
3595
3596 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3597 device->ws->buffer_destroy(buffer->bo);
3598
3599 vk_free2(&device->alloc, pAllocator, buffer);
3600 }
3601
3602 static inline unsigned
3603 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
3604 {
3605 if (stencil)
3606 return image->surface.u.legacy.stencil_tiling_index[level];
3607 else
3608 return image->surface.u.legacy.tiling_index[level];
3609 }
3610
3611 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
3612 {
3613 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
3614 }
3615
3616 static uint32_t
3617 radv_init_dcc_control_reg(struct radv_device *device,
3618 struct radv_image_view *iview)
3619 {
3620 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
3621 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
3622 unsigned max_compressed_block_size;
3623 unsigned independent_64b_blocks;
3624
3625 if (device->physical_device->rad_info.chip_class < VI)
3626 return 0;
3627
3628 if (iview->image->info.samples > 1) {
3629 if (iview->image->surface.bpe == 1)
3630 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3631 else if (iview->image->surface.bpe == 2)
3632 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
3633 }
3634
3635 if (!device->physical_device->rad_info.has_dedicated_vram) {
3636 /* amdvlk: [min-compressed-block-size] should be set to 32 for
3637 * dGPU and 64 for APU because all of our APUs to date use
3638 * DIMMs which have a request granularity size of 64B while all
3639 * other chips have a 32B request size.
3640 */
3641 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
3642 }
3643
3644 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
3645 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
3646 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
3647 /* If this DCC image is potentially going to be used in texture
3648 * fetches, we need some special settings.
3649 */
3650 independent_64b_blocks = 1;
3651 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3652 } else {
3653 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
3654 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
3655 * big as possible for better compression state.
3656 */
3657 independent_64b_blocks = 0;
3658 max_compressed_block_size = max_uncompressed_block_size;
3659 }
3660
3661 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3662 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
3663 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
3664 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
3665 }
3666
3667 static void
3668 radv_initialise_color_surface(struct radv_device *device,
3669 struct radv_color_buffer_info *cb,
3670 struct radv_image_view *iview)
3671 {
3672 const struct vk_format_description *desc;
3673 unsigned ntype, format, swap, endian;
3674 unsigned blend_clamp = 0, blend_bypass = 0;
3675 uint64_t va;
3676 const struct radeon_surf *surf = &iview->image->surface;
3677
3678 desc = vk_format_description(iview->vk_format);
3679
3680 memset(cb, 0, sizeof(*cb));
3681
3682 /* Intensity is implemented as Red, so treat it that way. */
3683 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
3684
3685 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3686
3687 cb->cb_color_base = va >> 8;
3688
3689 if (device->physical_device->rad_info.chip_class >= GFX9) {
3690 struct gfx9_surf_meta_flags meta;
3691 if (iview->image->dcc_offset)
3692 meta = iview->image->surface.u.gfx9.dcc;
3693 else
3694 meta = iview->image->surface.u.gfx9.cmask;
3695
3696 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3697 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
3698 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3699 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3700
3701 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
3702 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3703 } else {
3704 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
3705 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3706
3707 cb->cb_color_base += level_info->offset >> 8;
3708 if (level_info->mode == RADEON_SURF_MODE_2D)
3709 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3710
3711 pitch_tile_max = level_info->nblk_x / 8 - 1;
3712 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
3713 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
3714
3715 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3716 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3717 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
3718
3719 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3720
3721 if (radv_image_has_fmask(iview->image)) {
3722 if (device->physical_device->rad_info.chip_class >= CIK)
3723 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
3724 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
3725 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
3726 } else {
3727 /* This must be set for fast clear to work without FMASK. */
3728 if (device->physical_device->rad_info.chip_class >= CIK)
3729 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3730 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3731 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3732 }
3733 }
3734
3735 /* CMASK variables */
3736 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3737 va += iview->image->cmask.offset;
3738 cb->cb_color_cmask = va >> 8;
3739
3740 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3741 va += iview->image->dcc_offset;
3742 cb->cb_dcc_base = va >> 8;
3743 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
3744
3745 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3746 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3747 S_028C6C_SLICE_MAX(max_slice);
3748
3749 if (iview->image->info.samples > 1) {
3750 unsigned log_samples = util_logbase2(iview->image->info.samples);
3751
3752 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3753 S_028C74_NUM_FRAGMENTS(log_samples);
3754 }
3755
3756 if (radv_image_has_fmask(iview->image)) {
3757 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3758 cb->cb_color_fmask = va >> 8;
3759 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3760 } else {
3761 cb->cb_color_fmask = cb->cb_color_base;
3762 }
3763
3764 ntype = radv_translate_color_numformat(iview->vk_format,
3765 desc,
3766 vk_format_get_first_non_void_channel(iview->vk_format));
3767 format = radv_translate_colorformat(iview->vk_format);
3768 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3769 radv_finishme("Illegal color\n");
3770 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3771 endian = radv_colorformat_endian_swap(format);
3772
3773 /* blend clamp should be set for all NORM/SRGB types */
3774 if (ntype == V_028C70_NUMBER_UNORM ||
3775 ntype == V_028C70_NUMBER_SNORM ||
3776 ntype == V_028C70_NUMBER_SRGB)
3777 blend_clamp = 1;
3778
3779 /* set blend bypass according to docs if SINT/UINT or
3780 8/24 COLOR variants */
3781 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3782 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3783 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3784 blend_clamp = 0;
3785 blend_bypass = 1;
3786 }
3787 #if 0
3788 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3789 (format == V_028C70_COLOR_8 ||
3790 format == V_028C70_COLOR_8_8 ||
3791 format == V_028C70_COLOR_8_8_8_8))
3792 ->color_is_int8 = true;
3793 #endif
3794 cb->cb_color_info = S_028C70_FORMAT(format) |
3795 S_028C70_COMP_SWAP(swap) |
3796 S_028C70_BLEND_CLAMP(blend_clamp) |
3797 S_028C70_BLEND_BYPASS(blend_bypass) |
3798 S_028C70_SIMPLE_FLOAT(1) |
3799 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3800 ntype != V_028C70_NUMBER_SNORM &&
3801 ntype != V_028C70_NUMBER_SRGB &&
3802 format != V_028C70_COLOR_8_24 &&
3803 format != V_028C70_COLOR_24_8) |
3804 S_028C70_NUMBER_TYPE(ntype) |
3805 S_028C70_ENDIAN(endian);
3806 if (radv_image_has_fmask(iview->image)) {
3807 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3808 if (device->physical_device->rad_info.chip_class == SI) {
3809 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3810 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3811 }
3812 }
3813
3814 if (radv_image_has_cmask(iview->image) &&
3815 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3816 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3817
3818 if (radv_dcc_enabled(iview->image, iview->base_mip))
3819 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3820
3821 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
3822
3823 /* This must be set for fast clear to work without FMASK. */
3824 if (!radv_image_has_fmask(iview->image) &&
3825 device->physical_device->rad_info.chip_class == SI) {
3826 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3827 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3828 }
3829
3830 if (device->physical_device->rad_info.chip_class >= GFX9) {
3831 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
3832 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
3833
3834 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3835 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3836 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3837 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
3838 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
3839 S_028C68_MAX_MIP(iview->image->info.levels - 1);
3840 }
3841 }
3842
3843 static unsigned
3844 radv_calc_decompress_on_z_planes(struct radv_device *device,
3845 struct radv_image_view *iview)
3846 {
3847 unsigned max_zplanes = 0;
3848
3849 assert(radv_image_is_tc_compat_htile(iview->image));
3850
3851 if (device->physical_device->rad_info.chip_class >= GFX9) {
3852 /* Default value for 32-bit depth surfaces. */
3853 max_zplanes = 4;
3854
3855 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
3856 iview->image->info.samples > 1)
3857 max_zplanes = 2;
3858
3859 max_zplanes = max_zplanes + 1;
3860 } else {
3861 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
3862 /* Do not enable Z plane compression for 16-bit depth
3863 * surfaces because isn't supported on GFX8. Only
3864 * 32-bit depth surfaces are supported by the hardware.
3865 * This allows to maintain shader compatibility and to
3866 * reduce the number of depth decompressions.
3867 */
3868 max_zplanes = 1;
3869 } else {
3870 if (iview->image->info.samples <= 1)
3871 max_zplanes = 5;
3872 else if (iview->image->info.samples <= 4)
3873 max_zplanes = 3;
3874 else
3875 max_zplanes = 2;
3876 }
3877 }
3878
3879 return max_zplanes;
3880 }
3881
3882 static void
3883 radv_initialise_ds_surface(struct radv_device *device,
3884 struct radv_ds_buffer_info *ds,
3885 struct radv_image_view *iview)
3886 {
3887 unsigned level = iview->base_mip;
3888 unsigned format, stencil_format;
3889 uint64_t va, s_offs, z_offs;
3890 bool stencil_only = false;
3891 memset(ds, 0, sizeof(*ds));
3892 switch (iview->image->vk_format) {
3893 case VK_FORMAT_D24_UNORM_S8_UINT:
3894 case VK_FORMAT_X8_D24_UNORM_PACK32:
3895 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3896 ds->offset_scale = 2.0f;
3897 break;
3898 case VK_FORMAT_D16_UNORM:
3899 case VK_FORMAT_D16_UNORM_S8_UINT:
3900 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3901 ds->offset_scale = 4.0f;
3902 break;
3903 case VK_FORMAT_D32_SFLOAT:
3904 case VK_FORMAT_D32_SFLOAT_S8_UINT:
3905 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3906 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3907 ds->offset_scale = 1.0f;
3908 break;
3909 case VK_FORMAT_S8_UINT:
3910 stencil_only = true;
3911 break;
3912 default:
3913 break;
3914 }
3915
3916 format = radv_translate_dbformat(iview->image->vk_format);
3917 stencil_format = iview->image->surface.has_stencil ?
3918 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
3919
3920 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3921 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
3922 S_028008_SLICE_MAX(max_slice);
3923
3924 ds->db_htile_data_base = 0;
3925 ds->db_htile_surface = 0;
3926
3927 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3928 s_offs = z_offs = va;
3929
3930 if (device->physical_device->rad_info.chip_class >= GFX9) {
3931 assert(iview->image->surface.u.gfx9.surf_offset == 0);
3932 s_offs += iview->image->surface.u.gfx9.stencil_offset;
3933
3934 ds->db_z_info = S_028038_FORMAT(format) |
3935 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
3936 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3937 S_028038_MAXMIP(iview->image->info.levels - 1);
3938 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
3939 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
3940
3941 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3942 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
3943 ds->db_depth_view |= S_028008_MIPID(level);
3944
3945 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
3946 S_02801C_Y_MAX(iview->image->info.height - 1);
3947
3948 if (radv_htile_enabled(iview->image, level)) {
3949 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
3950
3951 if (radv_image_is_tc_compat_htile(iview->image)) {
3952 unsigned max_zplanes =
3953 radv_calc_decompress_on_z_planes(device, iview);
3954
3955 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
3956 S_028038_ITERATE_FLUSH(1);
3957 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
3958 }
3959
3960 if (!iview->image->surface.has_stencil)
3961 /* Use all of the htile_buffer for depth if there's no stencil. */
3962 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
3963 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3964 iview->image->htile_offset;
3965 ds->db_htile_data_base = va >> 8;
3966 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
3967 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
3968 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
3969 }
3970 } else {
3971 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
3972
3973 if (stencil_only)
3974 level_info = &iview->image->surface.u.legacy.stencil_level[level];
3975
3976 z_offs += iview->image->surface.u.legacy.level[level].offset;
3977 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
3978
3979 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
3980 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
3981 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
3982
3983 if (iview->image->info.samples > 1)
3984 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
3985
3986 if (device->physical_device->rad_info.chip_class >= CIK) {
3987 struct radeon_info *info = &device->physical_device->rad_info;
3988 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
3989 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
3990 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
3991 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
3992 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
3993 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
3994
3995 if (stencil_only)
3996 tile_mode = stencil_tile_mode;
3997
3998 ds->db_depth_info |=
3999 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4000 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4001 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4002 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4003 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4004 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4005 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4006 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4007 } else {
4008 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
4009 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4010 tile_mode_index = si_tile_mode_index(iview->image, level, true);
4011 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4012 if (stencil_only)
4013 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4014 }
4015
4016 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4017 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4018 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4019
4020 if (radv_htile_enabled(iview->image, level)) {
4021 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4022
4023 if (!iview->image->surface.has_stencil &&
4024 !radv_image_is_tc_compat_htile(iview->image))
4025 /* Use all of the htile_buffer for depth if there's no stencil. */
4026 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4027
4028 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4029 iview->image->htile_offset;
4030 ds->db_htile_data_base = va >> 8;
4031 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4032
4033 if (radv_image_is_tc_compat_htile(iview->image)) {
4034 unsigned max_zplanes =
4035 radv_calc_decompress_on_z_planes(device, iview);
4036
4037 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4038 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4039 }
4040 }
4041 }
4042
4043 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4044 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4045 }
4046
4047 VkResult radv_CreateFramebuffer(
4048 VkDevice _device,
4049 const VkFramebufferCreateInfo* pCreateInfo,
4050 const VkAllocationCallbacks* pAllocator,
4051 VkFramebuffer* pFramebuffer)
4052 {
4053 RADV_FROM_HANDLE(radv_device, device, _device);
4054 struct radv_framebuffer *framebuffer;
4055
4056 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4057
4058 size_t size = sizeof(*framebuffer) +
4059 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4060 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4061 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4062 if (framebuffer == NULL)
4063 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
4064
4065 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4066 framebuffer->width = pCreateInfo->width;
4067 framebuffer->height = pCreateInfo->height;
4068 framebuffer->layers = pCreateInfo->layers;
4069 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4070 VkImageView _iview = pCreateInfo->pAttachments[i];
4071 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4072 framebuffer->attachments[i].attachment = iview;
4073 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
4074 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4075 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4076 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4077 }
4078 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4079 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4080 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4081 }
4082
4083 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4084 return VK_SUCCESS;
4085 }
4086
4087 void radv_DestroyFramebuffer(
4088 VkDevice _device,
4089 VkFramebuffer _fb,
4090 const VkAllocationCallbacks* pAllocator)
4091 {
4092 RADV_FROM_HANDLE(radv_device, device, _device);
4093 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4094
4095 if (!fb)
4096 return;
4097 vk_free2(&device->alloc, pAllocator, fb);
4098 }
4099
4100 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4101 {
4102 switch (address_mode) {
4103 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4104 return V_008F30_SQ_TEX_WRAP;
4105 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4106 return V_008F30_SQ_TEX_MIRROR;
4107 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4108 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4109 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4110 return V_008F30_SQ_TEX_CLAMP_BORDER;
4111 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4112 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4113 default:
4114 unreachable("illegal tex wrap mode");
4115 break;
4116 }
4117 }
4118
4119 static unsigned
4120 radv_tex_compare(VkCompareOp op)
4121 {
4122 switch (op) {
4123 case VK_COMPARE_OP_NEVER:
4124 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4125 case VK_COMPARE_OP_LESS:
4126 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4127 case VK_COMPARE_OP_EQUAL:
4128 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4129 case VK_COMPARE_OP_LESS_OR_EQUAL:
4130 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4131 case VK_COMPARE_OP_GREATER:
4132 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4133 case VK_COMPARE_OP_NOT_EQUAL:
4134 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4135 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4136 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4137 case VK_COMPARE_OP_ALWAYS:
4138 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4139 default:
4140 unreachable("illegal compare mode");
4141 break;
4142 }
4143 }
4144
4145 static unsigned
4146 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4147 {
4148 switch (filter) {
4149 case VK_FILTER_NEAREST:
4150 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4151 V_008F38_SQ_TEX_XY_FILTER_POINT);
4152 case VK_FILTER_LINEAR:
4153 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4154 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4155 case VK_FILTER_CUBIC_IMG:
4156 default:
4157 fprintf(stderr, "illegal texture filter");
4158 return 0;
4159 }
4160 }
4161
4162 static unsigned
4163 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4164 {
4165 switch (mode) {
4166 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4167 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4168 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4169 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4170 default:
4171 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4172 }
4173 }
4174
4175 static unsigned
4176 radv_tex_bordercolor(VkBorderColor bcolor)
4177 {
4178 switch (bcolor) {
4179 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4180 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4181 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4182 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4183 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4184 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4185 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4186 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4187 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4188 default:
4189 break;
4190 }
4191 return 0;
4192 }
4193
4194 static unsigned
4195 radv_tex_aniso_filter(unsigned filter)
4196 {
4197 if (filter < 2)
4198 return 0;
4199 if (filter < 4)
4200 return 1;
4201 if (filter < 8)
4202 return 2;
4203 if (filter < 16)
4204 return 3;
4205 return 4;
4206 }
4207
4208 static unsigned
4209 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4210 {
4211 switch (mode) {
4212 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4213 return SQ_IMG_FILTER_MODE_BLEND;
4214 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4215 return SQ_IMG_FILTER_MODE_MIN;
4216 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4217 return SQ_IMG_FILTER_MODE_MAX;
4218 default:
4219 break;
4220 }
4221 return 0;
4222 }
4223
4224 static void
4225 radv_init_sampler(struct radv_device *device,
4226 struct radv_sampler *sampler,
4227 const VkSamplerCreateInfo *pCreateInfo)
4228 {
4229 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
4230 (uint32_t) pCreateInfo->maxAnisotropy : 0;
4231 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4232 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4233 unsigned filter_mode = SQ_IMG_FILTER_MODE_BLEND;
4234
4235 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4236 vk_find_struct_const(pCreateInfo->pNext,
4237 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4238 if (sampler_reduction)
4239 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4240
4241 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4242 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4243 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4244 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4245 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4246 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4247 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4248 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4249 S_008F30_DISABLE_CUBE_WRAP(0) |
4250 S_008F30_COMPAT_MODE(is_vi) |
4251 S_008F30_FILTER_MODE(filter_mode));
4252 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4253 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4254 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4255 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4256 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4257 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4258 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4259 S_008F38_MIP_POINT_PRECLAMP(0) |
4260 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4261 S_008F38_FILTER_PREC_FIX(1) |
4262 S_008F38_ANISO_OVERRIDE(is_vi));
4263 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4264 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4265 }
4266
4267 VkResult radv_CreateSampler(
4268 VkDevice _device,
4269 const VkSamplerCreateInfo* pCreateInfo,
4270 const VkAllocationCallbacks* pAllocator,
4271 VkSampler* pSampler)
4272 {
4273 RADV_FROM_HANDLE(radv_device, device, _device);
4274 struct radv_sampler *sampler;
4275
4276 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4277
4278 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4279 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4280 if (!sampler)
4281 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
4282
4283 radv_init_sampler(device, sampler, pCreateInfo);
4284 *pSampler = radv_sampler_to_handle(sampler);
4285
4286 return VK_SUCCESS;
4287 }
4288
4289 void radv_DestroySampler(
4290 VkDevice _device,
4291 VkSampler _sampler,
4292 const VkAllocationCallbacks* pAllocator)
4293 {
4294 RADV_FROM_HANDLE(radv_device, device, _device);
4295 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4296
4297 if (!sampler)
4298 return;
4299 vk_free2(&device->alloc, pAllocator, sampler);
4300 }
4301
4302 /* vk_icd.h does not declare this function, so we declare it here to
4303 * suppress Wmissing-prototypes.
4304 */
4305 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4306 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4307
4308 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4309 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4310 {
4311 /* For the full details on loader interface versioning, see
4312 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4313 * What follows is a condensed summary, to help you navigate the large and
4314 * confusing official doc.
4315 *
4316 * - Loader interface v0 is incompatible with later versions. We don't
4317 * support it.
4318 *
4319 * - In loader interface v1:
4320 * - The first ICD entrypoint called by the loader is
4321 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4322 * entrypoint.
4323 * - The ICD must statically expose no other Vulkan symbol unless it is
4324 * linked with -Bsymbolic.
4325 * - Each dispatchable Vulkan handle created by the ICD must be
4326 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4327 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4328 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4329 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4330 * such loader-managed surfaces.
4331 *
4332 * - Loader interface v2 differs from v1 in:
4333 * - The first ICD entrypoint called by the loader is
4334 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4335 * statically expose this entrypoint.
4336 *
4337 * - Loader interface v3 differs from v2 in:
4338 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4339 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4340 * because the loader no longer does so.
4341 */
4342 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4343 return VK_SUCCESS;
4344 }
4345
4346 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4347 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4348 int *pFD)
4349 {
4350 RADV_FROM_HANDLE(radv_device, device, _device);
4351 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4352
4353 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4354
4355 /* At the moment, we support only the below handle types. */
4356 assert(pGetFdInfo->handleType ==
4357 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4358 pGetFdInfo->handleType ==
4359 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4360
4361 bool ret = radv_get_memory_fd(device, memory, pFD);
4362 if (ret == false)
4363 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
4364 return VK_SUCCESS;
4365 }
4366
4367 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4368 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
4369 int fd,
4370 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4371 {
4372 switch (handleType) {
4373 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4374 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4375 return VK_SUCCESS;
4376
4377 default:
4378 /* The valid usage section for this function says:
4379 *
4380 * "handleType must not be one of the handle types defined as
4381 * opaque."
4382 *
4383 * So opaque handle types fall into the default "unsupported" case.
4384 */
4385 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4386 }
4387 }
4388
4389 static VkResult radv_import_opaque_fd(struct radv_device *device,
4390 int fd,
4391 uint32_t *syncobj)
4392 {
4393 uint32_t syncobj_handle = 0;
4394 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4395 if (ret != 0)
4396 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4397
4398 if (*syncobj)
4399 device->ws->destroy_syncobj(device->ws, *syncobj);
4400
4401 *syncobj = syncobj_handle;
4402 close(fd);
4403
4404 return VK_SUCCESS;
4405 }
4406
4407 static VkResult radv_import_sync_fd(struct radv_device *device,
4408 int fd,
4409 uint32_t *syncobj)
4410 {
4411 /* If we create a syncobj we do it locally so that if we have an error, we don't
4412 * leave a syncobj in an undetermined state in the fence. */
4413 uint32_t syncobj_handle = *syncobj;
4414 if (!syncobj_handle) {
4415 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4416 if (ret) {
4417 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4418 }
4419 }
4420
4421 if (fd == -1) {
4422 device->ws->signal_syncobj(device->ws, syncobj_handle);
4423 } else {
4424 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
4425 if (ret != 0)
4426 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4427 }
4428
4429 *syncobj = syncobj_handle;
4430 if (fd != -1)
4431 close(fd);
4432
4433 return VK_SUCCESS;
4434 }
4435
4436 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
4437 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
4438 {
4439 RADV_FROM_HANDLE(radv_device, device, _device);
4440 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
4441 uint32_t *syncobj_dst = NULL;
4442
4443 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
4444 syncobj_dst = &sem->temp_syncobj;
4445 } else {
4446 syncobj_dst = &sem->syncobj;
4447 }
4448
4449 switch(pImportSemaphoreFdInfo->handleType) {
4450 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4451 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4452 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4453 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4454 default:
4455 unreachable("Unhandled semaphore handle type");
4456 }
4457 }
4458
4459 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
4460 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
4461 int *pFd)
4462 {
4463 RADV_FROM_HANDLE(radv_device, device, _device);
4464 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
4465 int ret;
4466 uint32_t syncobj_handle;
4467
4468 if (sem->temp_syncobj)
4469 syncobj_handle = sem->temp_syncobj;
4470 else
4471 syncobj_handle = sem->syncobj;
4472
4473 switch(pGetFdInfo->handleType) {
4474 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4475 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4476 break;
4477 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4478 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4479 if (!ret) {
4480 if (sem->temp_syncobj) {
4481 close (sem->temp_syncobj);
4482 sem->temp_syncobj = 0;
4483 } else {
4484 device->ws->reset_syncobj(device->ws, syncobj_handle);
4485 }
4486 }
4487 break;
4488 default:
4489 unreachable("Unhandled semaphore handle type");
4490 }
4491
4492 if (ret)
4493 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4494 return VK_SUCCESS;
4495 }
4496
4497 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
4498 VkPhysicalDevice physicalDevice,
4499 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
4500 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
4501 {
4502 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4503
4504 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
4505 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4506 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4507 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4508 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4509 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4510 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4511 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4512 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
4513 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4514 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4515 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4516 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4517 } else {
4518 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
4519 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
4520 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
4521 }
4522 }
4523
4524 VkResult radv_ImportFenceFdKHR(VkDevice _device,
4525 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
4526 {
4527 RADV_FROM_HANDLE(radv_device, device, _device);
4528 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
4529 uint32_t *syncobj_dst = NULL;
4530
4531
4532 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT_KHR) {
4533 syncobj_dst = &fence->temp_syncobj;
4534 } else {
4535 syncobj_dst = &fence->syncobj;
4536 }
4537
4538 switch(pImportFenceFdInfo->handleType) {
4539 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4540 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4541 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4542 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4543 default:
4544 unreachable("Unhandled fence handle type");
4545 }
4546 }
4547
4548 VkResult radv_GetFenceFdKHR(VkDevice _device,
4549 const VkFenceGetFdInfoKHR *pGetFdInfo,
4550 int *pFd)
4551 {
4552 RADV_FROM_HANDLE(radv_device, device, _device);
4553 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
4554 int ret;
4555 uint32_t syncobj_handle;
4556
4557 if (fence->temp_syncobj)
4558 syncobj_handle = fence->temp_syncobj;
4559 else
4560 syncobj_handle = fence->syncobj;
4561
4562 switch(pGetFdInfo->handleType) {
4563 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4564 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4565 break;
4566 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4567 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4568 if (!ret) {
4569 if (fence->temp_syncobj) {
4570 close (fence->temp_syncobj);
4571 fence->temp_syncobj = 0;
4572 } else {
4573 device->ws->reset_syncobj(device->ws, syncobj_handle);
4574 }
4575 }
4576 break;
4577 default:
4578 unreachable("Unhandled fence handle type");
4579 }
4580
4581 if (ret)
4582 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4583 return VK_SUCCESS;
4584 }
4585
4586 void radv_GetPhysicalDeviceExternalFenceProperties(
4587 VkPhysicalDevice physicalDevice,
4588 const VkPhysicalDeviceExternalFenceInfoKHR* pExternalFenceInfo,
4589 VkExternalFencePropertiesKHR* pExternalFenceProperties)
4590 {
4591 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4592
4593 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4594 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4595 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4596 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4597 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4598 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT_KHR |
4599 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4600 } else {
4601 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
4602 pExternalFenceProperties->compatibleHandleTypes = 0;
4603 pExternalFenceProperties->externalFenceFeatures = 0;
4604 }
4605 }
4606
4607 VkResult
4608 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
4609 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
4610 const VkAllocationCallbacks* pAllocator,
4611 VkDebugReportCallbackEXT* pCallback)
4612 {
4613 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4614 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
4615 pCreateInfo, pAllocator, &instance->alloc,
4616 pCallback);
4617 }
4618
4619 void
4620 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
4621 VkDebugReportCallbackEXT _callback,
4622 const VkAllocationCallbacks* pAllocator)
4623 {
4624 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4625 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
4626 _callback, pAllocator, &instance->alloc);
4627 }
4628
4629 void
4630 radv_DebugReportMessageEXT(VkInstance _instance,
4631 VkDebugReportFlagsEXT flags,
4632 VkDebugReportObjectTypeEXT objectType,
4633 uint64_t object,
4634 size_t location,
4635 int32_t messageCode,
4636 const char* pLayerPrefix,
4637 const char* pMessage)
4638 {
4639 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4640 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
4641 object, location, messageCode, pLayerPrefix, pMessage);
4642 }
4643
4644 void
4645 radv_GetDeviceGroupPeerMemoryFeatures(
4646 VkDevice device,
4647 uint32_t heapIndex,
4648 uint32_t localDeviceIndex,
4649 uint32_t remoteDeviceIndex,
4650 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
4651 {
4652 assert(localDeviceIndex == remoteDeviceIndex);
4653
4654 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
4655 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
4656 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
4657 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
4658 }