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gallium/u_transfer_helper: Add support for separate Z24/S8 as well.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "gfx9d.h"
47 #include "addrlib/gfx9/chip/gfx9_enum.h"
48 #include "util/build_id.h"
49 #include "util/debug.h"
50 #include "util/mesa-sha1.h"
51
52 static bool
53 radv_get_build_id(void *ptr, struct mesa_sha1 *ctx)
54 {
55 uint32_t timestamp;
56
57 #ifdef HAVE_DL_ITERATE_PHDR
58 const struct build_id_note *note = NULL;
59 if ((note = build_id_find_nhdr_for_addr(ptr))) {
60 _mesa_sha1_update(ctx, build_id_data(note), build_id_length(note));
61 } else
62 #endif
63 if (disk_cache_get_function_timestamp(ptr, &timestamp)) {
64 _mesa_sha1_update(ctx, &timestamp, sizeof(timestamp));
65 } else
66 return false;
67 return true;
68 }
69
70 static int
71 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
72 {
73 struct mesa_sha1 ctx;
74 unsigned char sha1[20];
75 unsigned ptr_size = sizeof(void*);
76
77 memset(uuid, 0, VK_UUID_SIZE);
78 _mesa_sha1_init(&ctx);
79
80 if (!radv_get_build_id(radv_device_get_cache_uuid, &ctx) ||
81 !radv_get_build_id(LLVMInitializeAMDGPUTargetInfo, &ctx))
82 return -1;
83
84 _mesa_sha1_update(&ctx, &family, sizeof(family));
85 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
86 _mesa_sha1_final(&ctx, sha1);
87
88 memcpy(uuid, sha1, VK_UUID_SIZE);
89 return 0;
90 }
91
92 static void
93 radv_get_driver_uuid(void *uuid)
94 {
95 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
96 }
97
98 static void
99 radv_get_device_uuid(struct radeon_info *info, void *uuid)
100 {
101 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
102 }
103
104 static void
105 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
106 {
107 const char *chip_string;
108 char llvm_string[32] = {};
109
110 switch (family) {
111 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
112 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
113 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
114 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
115 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
116 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
117 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
118 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
119 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
120 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
121 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
122 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
123 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
124 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
125 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
126 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
127 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
128 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
129 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
130 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
131 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
132 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
133 default: chip_string = "AMD RADV unknown"; break;
134 }
135
136 snprintf(llvm_string, sizeof(llvm_string),
137 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
138 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
139 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
140 }
141
142 static void
143 radv_physical_device_init_mem_types(struct radv_physical_device *device)
144 {
145 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
146 uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
147 device->rad_info.vram_vis_size);
148
149 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
150 device->memory_properties.memoryHeapCount = 0;
151 if (device->rad_info.vram_size - visible_vram_size > 0) {
152 vram_index = device->memory_properties.memoryHeapCount++;
153 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
154 .size = device->rad_info.vram_size - visible_vram_size,
155 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
156 };
157 }
158 if (visible_vram_size) {
159 visible_vram_index = device->memory_properties.memoryHeapCount++;
160 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
161 .size = visible_vram_size,
162 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
163 };
164 }
165 if (device->rad_info.gart_size > 0) {
166 gart_index = device->memory_properties.memoryHeapCount++;
167 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
168 .size = device->rad_info.gart_size,
169 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
170 };
171 }
172
173 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
174 unsigned type_count = 0;
175 if (vram_index >= 0) {
176 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
177 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
178 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
179 .heapIndex = vram_index,
180 };
181 }
182 if (gart_index >= 0) {
183 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
184 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
185 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
186 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
187 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
188 .heapIndex = gart_index,
189 };
190 }
191 if (visible_vram_index >= 0) {
192 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
193 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
194 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
195 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
196 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
197 .heapIndex = visible_vram_index,
198 };
199 }
200 if (gart_index >= 0) {
201 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
202 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
203 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
204 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
205 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
206 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
207 .heapIndex = gart_index,
208 };
209 }
210 device->memory_properties.memoryTypeCount = type_count;
211 }
212
213 static void
214 radv_handle_env_var_force_family(struct radv_physical_device *device)
215 {
216 const char *family = getenv("RADV_FORCE_FAMILY");
217 unsigned i;
218
219 if (!family)
220 return;
221
222 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
223 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
224 /* Override family and chip_class. */
225 device->rad_info.family = i;
226
227 if (i >= CHIP_VEGA10)
228 device->rad_info.chip_class = GFX9;
229 else if (i >= CHIP_TONGA)
230 device->rad_info.chip_class = VI;
231 else if (i >= CHIP_BONAIRE)
232 device->rad_info.chip_class = CIK;
233 else
234 device->rad_info.chip_class = SI;
235
236 return;
237 }
238 }
239
240 fprintf(stderr, "radv: Unknown family: %s\n", family);
241 exit(1);
242 }
243
244 static VkResult
245 radv_physical_device_init(struct radv_physical_device *device,
246 struct radv_instance *instance,
247 drmDevicePtr drm_device)
248 {
249 const char *path = drm_device->nodes[DRM_NODE_RENDER];
250 VkResult result;
251 drmVersionPtr version;
252 int fd;
253 int master_fd = -1;
254
255 fd = open(path, O_RDWR | O_CLOEXEC);
256 if (fd < 0) {
257 if (instance->debug_flags & RADV_DEBUG_STARTUP)
258 radv_logi("Could not open device '%s'", path);
259
260 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
261 }
262
263 version = drmGetVersion(fd);
264 if (!version) {
265 close(fd);
266
267 if (instance->debug_flags & RADV_DEBUG_STARTUP)
268 radv_logi("Could not get the kernel driver version for device '%s'", path);
269
270 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
271 "failed to get version %s: %m", path);
272 }
273
274 if (strcmp(version->name, "amdgpu")) {
275 drmFreeVersion(version);
276 close(fd);
277
278 if (instance->debug_flags & RADV_DEBUG_STARTUP)
279 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
280
281 return VK_ERROR_INCOMPATIBLE_DRIVER;
282 }
283 drmFreeVersion(version);
284
285 if (instance->debug_flags & RADV_DEBUG_STARTUP)
286 radv_logi("Found compatible device '%s'.", path);
287
288 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
289 device->instance = instance;
290 assert(strlen(path) < ARRAY_SIZE(device->path));
291 strncpy(device->path, path, ARRAY_SIZE(device->path));
292
293 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
294 instance->perftest_flags);
295 if (!device->ws) {
296 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
297 goto fail;
298 }
299
300 if (instance->enabled_extensions.KHR_display) {
301 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
302 if (master_fd >= 0) {
303 uint32_t accel_working = 0;
304 struct drm_amdgpu_info request = {
305 .return_pointer = (uintptr_t)&accel_working,
306 .return_size = sizeof(accel_working),
307 .query = AMDGPU_INFO_ACCEL_WORKING
308 };
309
310 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
311 close(master_fd);
312 master_fd = -1;
313 }
314 }
315 }
316
317 device->master_fd = master_fd;
318 device->local_fd = fd;
319 device->ws->query_info(device->ws, &device->rad_info);
320
321 radv_handle_env_var_force_family(device);
322
323 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
324
325 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
326 device->ws->destroy(device->ws);
327 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
328 "cannot generate UUID");
329 goto fail;
330 }
331
332 /* These flags affect shader compilation. */
333 uint64_t shader_env_flags =
334 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
335 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
336
337 /* The gpu id is already embedded in the uuid so we just pass "radv"
338 * when creating the cache.
339 */
340 char buf[VK_UUID_SIZE * 2 + 1];
341 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
342 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
343
344 if (device->rad_info.chip_class < VI ||
345 device->rad_info.chip_class > GFX9)
346 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
347
348 radv_get_driver_uuid(&device->device_uuid);
349 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
350
351 if (device->rad_info.family == CHIP_STONEY ||
352 device->rad_info.chip_class >= GFX9) {
353 device->has_rbplus = true;
354 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
355 device->rad_info.family == CHIP_VEGA12 ||
356 device->rad_info.family == CHIP_RAVEN;
357 }
358
359 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
360 * on SI.
361 */
362 device->has_clear_state = device->rad_info.chip_class >= CIK;
363
364 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
365
366 /* Vega10/Raven need a special workaround for a hardware bug. */
367 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
368 device->rad_info.family == CHIP_RAVEN;
369
370 /* Out-of-order primitive rasterization. */
371 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
372 device->rad_info.max_se >= 2;
373 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
374 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
375
376 device->dcc_msaa_allowed =
377 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
378
379 radv_physical_device_init_mem_types(device);
380 radv_fill_device_extension_table(device, &device->supported_extensions);
381
382 result = radv_init_wsi(device);
383 if (result != VK_SUCCESS) {
384 device->ws->destroy(device->ws);
385 vk_error(instance, result);
386 goto fail;
387 }
388
389 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
390 ac_print_gpu_info(&device->rad_info);
391
392 return VK_SUCCESS;
393
394 fail:
395 close(fd);
396 if (master_fd != -1)
397 close(master_fd);
398 return result;
399 }
400
401 static void
402 radv_physical_device_finish(struct radv_physical_device *device)
403 {
404 radv_finish_wsi(device);
405 device->ws->destroy(device->ws);
406 disk_cache_destroy(device->disk_cache);
407 close(device->local_fd);
408 if (device->master_fd != -1)
409 close(device->master_fd);
410 }
411
412 static void *
413 default_alloc_func(void *pUserData, size_t size, size_t align,
414 VkSystemAllocationScope allocationScope)
415 {
416 return malloc(size);
417 }
418
419 static void *
420 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
421 size_t align, VkSystemAllocationScope allocationScope)
422 {
423 return realloc(pOriginal, size);
424 }
425
426 static void
427 default_free_func(void *pUserData, void *pMemory)
428 {
429 free(pMemory);
430 }
431
432 static const VkAllocationCallbacks default_alloc = {
433 .pUserData = NULL,
434 .pfnAllocation = default_alloc_func,
435 .pfnReallocation = default_realloc_func,
436 .pfnFree = default_free_func,
437 };
438
439 static const struct debug_control radv_debug_options[] = {
440 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
441 {"nodcc", RADV_DEBUG_NO_DCC},
442 {"shaders", RADV_DEBUG_DUMP_SHADERS},
443 {"nocache", RADV_DEBUG_NO_CACHE},
444 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
445 {"nohiz", RADV_DEBUG_NO_HIZ},
446 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
447 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
448 {"allbos", RADV_DEBUG_ALL_BOS},
449 {"noibs", RADV_DEBUG_NO_IBS},
450 {"spirv", RADV_DEBUG_DUMP_SPIRV},
451 {"vmfaults", RADV_DEBUG_VM_FAULTS},
452 {"zerovram", RADV_DEBUG_ZERO_VRAM},
453 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
454 {"nosisched", RADV_DEBUG_NO_SISCHED},
455 {"preoptir", RADV_DEBUG_PREOPTIR},
456 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
457 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
458 {"info", RADV_DEBUG_INFO},
459 {"errors", RADV_DEBUG_ERRORS},
460 {"startup", RADV_DEBUG_STARTUP},
461 {"checkir", RADV_DEBUG_CHECKIR},
462 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
463 {NULL, 0}
464 };
465
466 const char *
467 radv_get_debug_option_name(int id)
468 {
469 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
470 return radv_debug_options[id].string;
471 }
472
473 static const struct debug_control radv_perftest_options[] = {
474 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
475 {"sisched", RADV_PERFTEST_SISCHED},
476 {"localbos", RADV_PERFTEST_LOCAL_BOS},
477 {"binning", RADV_PERFTEST_BINNING},
478 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
479 {NULL, 0}
480 };
481
482 const char *
483 radv_get_perftest_option_name(int id)
484 {
485 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
486 return radv_perftest_options[id].string;
487 }
488
489 static void
490 radv_handle_per_app_options(struct radv_instance *instance,
491 const VkApplicationInfo *info)
492 {
493 const char *name = info ? info->pApplicationName : NULL;
494
495 if (!name)
496 return;
497
498 if (!strcmp(name, "Talos - Linux - 32bit") ||
499 !strcmp(name, "Talos - Linux - 64bit")) {
500 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
501 /* Force enable LLVM sisched for Talos because it looks
502 * safe and it gives few more FPS.
503 */
504 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
505 }
506 } else if (!strcmp(name, "DOOM_VFR")) {
507 /* Work around a Doom VFR game bug */
508 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
509 }
510 }
511
512 static int radv_get_instance_extension_index(const char *name)
513 {
514 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
515 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
516 return i;
517 }
518 return -1;
519 }
520
521
522 VkResult radv_CreateInstance(
523 const VkInstanceCreateInfo* pCreateInfo,
524 const VkAllocationCallbacks* pAllocator,
525 VkInstance* pInstance)
526 {
527 struct radv_instance *instance;
528 VkResult result;
529
530 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
531
532 uint32_t client_version;
533 if (pCreateInfo->pApplicationInfo &&
534 pCreateInfo->pApplicationInfo->apiVersion != 0) {
535 client_version = pCreateInfo->pApplicationInfo->apiVersion;
536 } else {
537 radv_EnumerateInstanceVersion(&client_version);
538 }
539
540 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
541 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
542 if (!instance)
543 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
544
545 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
546
547 if (pAllocator)
548 instance->alloc = *pAllocator;
549 else
550 instance->alloc = default_alloc;
551
552 instance->apiVersion = client_version;
553 instance->physicalDeviceCount = -1;
554
555 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
556 radv_debug_options);
557
558 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
559 radv_perftest_options);
560
561
562 if (instance->debug_flags & RADV_DEBUG_STARTUP)
563 radv_logi("Created an instance");
564
565 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
566 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
567 int index = radv_get_instance_extension_index(ext_name);
568
569 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
570 vk_free2(&default_alloc, pAllocator, instance);
571 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
572 }
573
574 instance->enabled_extensions.extensions[index] = true;
575 }
576
577 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
578 if (result != VK_SUCCESS) {
579 vk_free2(&default_alloc, pAllocator, instance);
580 return vk_error(instance, result);
581 }
582
583 _mesa_locale_init();
584
585 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
586
587 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
588
589 *pInstance = radv_instance_to_handle(instance);
590
591 return VK_SUCCESS;
592 }
593
594 void radv_DestroyInstance(
595 VkInstance _instance,
596 const VkAllocationCallbacks* pAllocator)
597 {
598 RADV_FROM_HANDLE(radv_instance, instance, _instance);
599
600 if (!instance)
601 return;
602
603 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
604 radv_physical_device_finish(instance->physicalDevices + i);
605 }
606
607 VG(VALGRIND_DESTROY_MEMPOOL(instance));
608
609 _mesa_locale_fini();
610
611 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
612
613 vk_free(&instance->alloc, instance);
614 }
615
616 static VkResult
617 radv_enumerate_devices(struct radv_instance *instance)
618 {
619 /* TODO: Check for more devices ? */
620 drmDevicePtr devices[8];
621 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
622 int max_devices;
623
624 instance->physicalDeviceCount = 0;
625
626 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
627
628 if (instance->debug_flags & RADV_DEBUG_STARTUP)
629 radv_logi("Found %d drm nodes", max_devices);
630
631 if (max_devices < 1)
632 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
633
634 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
635 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
636 devices[i]->bustype == DRM_BUS_PCI &&
637 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
638
639 result = radv_physical_device_init(instance->physicalDevices +
640 instance->physicalDeviceCount,
641 instance,
642 devices[i]);
643 if (result == VK_SUCCESS)
644 ++instance->physicalDeviceCount;
645 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
646 break;
647 }
648 }
649 drmFreeDevices(devices, max_devices);
650
651 return result;
652 }
653
654 VkResult radv_EnumeratePhysicalDevices(
655 VkInstance _instance,
656 uint32_t* pPhysicalDeviceCount,
657 VkPhysicalDevice* pPhysicalDevices)
658 {
659 RADV_FROM_HANDLE(radv_instance, instance, _instance);
660 VkResult result;
661
662 if (instance->physicalDeviceCount < 0) {
663 result = radv_enumerate_devices(instance);
664 if (result != VK_SUCCESS &&
665 result != VK_ERROR_INCOMPATIBLE_DRIVER)
666 return result;
667 }
668
669 if (!pPhysicalDevices) {
670 *pPhysicalDeviceCount = instance->physicalDeviceCount;
671 } else {
672 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
673 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
674 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
675 }
676
677 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
678 : VK_SUCCESS;
679 }
680
681 VkResult radv_EnumeratePhysicalDeviceGroups(
682 VkInstance _instance,
683 uint32_t* pPhysicalDeviceGroupCount,
684 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
685 {
686 RADV_FROM_HANDLE(radv_instance, instance, _instance);
687 VkResult result;
688
689 if (instance->physicalDeviceCount < 0) {
690 result = radv_enumerate_devices(instance);
691 if (result != VK_SUCCESS &&
692 result != VK_ERROR_INCOMPATIBLE_DRIVER)
693 return result;
694 }
695
696 if (!pPhysicalDeviceGroupProperties) {
697 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
698 } else {
699 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
700 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
701 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
702 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
703 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
704 }
705 }
706 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
707 : VK_SUCCESS;
708 }
709
710 void radv_GetPhysicalDeviceFeatures(
711 VkPhysicalDevice physicalDevice,
712 VkPhysicalDeviceFeatures* pFeatures)
713 {
714 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
715 memset(pFeatures, 0, sizeof(*pFeatures));
716
717 *pFeatures = (VkPhysicalDeviceFeatures) {
718 .robustBufferAccess = true,
719 .fullDrawIndexUint32 = true,
720 .imageCubeArray = true,
721 .independentBlend = true,
722 .geometryShader = true,
723 .tessellationShader = true,
724 .sampleRateShading = true,
725 .dualSrcBlend = true,
726 .logicOp = true,
727 .multiDrawIndirect = true,
728 .drawIndirectFirstInstance = true,
729 .depthClamp = true,
730 .depthBiasClamp = true,
731 .fillModeNonSolid = true,
732 .depthBounds = true,
733 .wideLines = true,
734 .largePoints = true,
735 .alphaToOne = true,
736 .multiViewport = true,
737 .samplerAnisotropy = true,
738 .textureCompressionETC2 = pdevice->rad_info.chip_class >= GFX9 ||
739 pdevice->rad_info.family == CHIP_STONEY,
740 .textureCompressionASTC_LDR = false,
741 .textureCompressionBC = true,
742 .occlusionQueryPrecise = true,
743 .pipelineStatisticsQuery = true,
744 .vertexPipelineStoresAndAtomics = true,
745 .fragmentStoresAndAtomics = true,
746 .shaderTessellationAndGeometryPointSize = true,
747 .shaderImageGatherExtended = true,
748 .shaderStorageImageExtendedFormats = true,
749 .shaderStorageImageMultisample = false,
750 .shaderUniformBufferArrayDynamicIndexing = true,
751 .shaderSampledImageArrayDynamicIndexing = true,
752 .shaderStorageBufferArrayDynamicIndexing = true,
753 .shaderStorageImageArrayDynamicIndexing = true,
754 .shaderStorageImageReadWithoutFormat = true,
755 .shaderStorageImageWriteWithoutFormat = true,
756 .shaderClipDistance = true,
757 .shaderCullDistance = true,
758 .shaderFloat64 = true,
759 .shaderInt64 = true,
760 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9 && HAVE_LLVM >= 0x700,
761 .sparseBinding = true,
762 .variableMultisampleRate = true,
763 .inheritedQueries = true,
764 };
765 }
766
767 void radv_GetPhysicalDeviceFeatures2(
768 VkPhysicalDevice physicalDevice,
769 VkPhysicalDeviceFeatures2KHR *pFeatures)
770 {
771 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
772 vk_foreach_struct(ext, pFeatures->pNext) {
773 switch (ext->sType) {
774 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
775 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
776 features->variablePointersStorageBuffer = true;
777 features->variablePointers = false;
778 break;
779 }
780 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHR: {
781 VkPhysicalDeviceMultiviewFeaturesKHR *features = (VkPhysicalDeviceMultiviewFeaturesKHR*)ext;
782 features->multiview = true;
783 features->multiviewGeometryShader = true;
784 features->multiviewTessellationShader = true;
785 break;
786 }
787 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
788 VkPhysicalDeviceShaderDrawParameterFeatures *features =
789 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
790 features->shaderDrawParameters = true;
791 break;
792 }
793 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
794 VkPhysicalDeviceProtectedMemoryFeatures *features =
795 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
796 features->protectedMemory = false;
797 break;
798 }
799 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
800 VkPhysicalDevice16BitStorageFeatures *features =
801 (VkPhysicalDevice16BitStorageFeatures*)ext;
802 bool enabled = HAVE_LLVM >= 0x0700 && pdevice->rad_info.chip_class >= VI;
803 features->storageBuffer16BitAccess = enabled;
804 features->uniformAndStorageBuffer16BitAccess = enabled;
805 features->storagePushConstant16 = enabled;
806 features->storageInputOutput16 = enabled;
807 break;
808 }
809 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
810 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
811 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
812 features->samplerYcbcrConversion = false;
813 break;
814 }
815 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
816 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
817 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
818 features->shaderInputAttachmentArrayDynamicIndexing = true;
819 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
820 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
821 features->shaderUniformBufferArrayNonUniformIndexing = false;
822 features->shaderSampledImageArrayNonUniformIndexing = false;
823 features->shaderStorageBufferArrayNonUniformIndexing = false;
824 features->shaderStorageImageArrayNonUniformIndexing = false;
825 features->shaderInputAttachmentArrayNonUniformIndexing = false;
826 features->shaderUniformTexelBufferArrayNonUniformIndexing = false;
827 features->shaderStorageTexelBufferArrayNonUniformIndexing = false;
828 features->descriptorBindingUniformBufferUpdateAfterBind = true;
829 features->descriptorBindingSampledImageUpdateAfterBind = true;
830 features->descriptorBindingStorageImageUpdateAfterBind = true;
831 features->descriptorBindingStorageBufferUpdateAfterBind = true;
832 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
833 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
834 features->descriptorBindingUpdateUnusedWhilePending = true;
835 features->descriptorBindingPartiallyBound = true;
836 features->descriptorBindingVariableDescriptorCount = true;
837 features->runtimeDescriptorArray = true;
838 break;
839 }
840 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
841 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
842 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
843 features->conditionalRendering = true;
844 features->inheritedConditionalRendering = false;
845 break;
846 }
847 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
848 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
849 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
850 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
851 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
852 break;
853 }
854 default:
855 break;
856 }
857 }
858 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
859 }
860
861 void radv_GetPhysicalDeviceProperties(
862 VkPhysicalDevice physicalDevice,
863 VkPhysicalDeviceProperties* pProperties)
864 {
865 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
866 VkSampleCountFlags sample_counts = 0xf;
867
868 /* make sure that the entire descriptor set is addressable with a signed
869 * 32-bit int. So the sum of all limits scaled by descriptor size has to
870 * be at most 2 GiB. the combined image & samples object count as one of
871 * both. This limit is for the pipeline layout, not for the set layout, but
872 * there is no set limit, so we just set a pipeline limit. I don't think
873 * any app is going to hit this soon. */
874 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
875 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
876 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
877 32 /* sampler, largest when combined with image */ +
878 64 /* sampled image */ +
879 64 /* storage image */);
880
881 VkPhysicalDeviceLimits limits = {
882 .maxImageDimension1D = (1 << 14),
883 .maxImageDimension2D = (1 << 14),
884 .maxImageDimension3D = (1 << 11),
885 .maxImageDimensionCube = (1 << 14),
886 .maxImageArrayLayers = (1 << 11),
887 .maxTexelBufferElements = 128 * 1024 * 1024,
888 .maxUniformBufferRange = UINT32_MAX,
889 .maxStorageBufferRange = UINT32_MAX,
890 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
891 .maxMemoryAllocationCount = UINT32_MAX,
892 .maxSamplerAllocationCount = 64 * 1024,
893 .bufferImageGranularity = 64, /* A cache line */
894 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
895 .maxBoundDescriptorSets = MAX_SETS,
896 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
897 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
898 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
899 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
900 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
901 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
902 .maxPerStageResources = max_descriptor_set_size,
903 .maxDescriptorSetSamplers = max_descriptor_set_size,
904 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
905 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
906 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
907 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
908 .maxDescriptorSetSampledImages = max_descriptor_set_size,
909 .maxDescriptorSetStorageImages = max_descriptor_set_size,
910 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
911 .maxVertexInputAttributes = 32,
912 .maxVertexInputBindings = 32,
913 .maxVertexInputAttributeOffset = 2047,
914 .maxVertexInputBindingStride = 2048,
915 .maxVertexOutputComponents = 128,
916 .maxTessellationGenerationLevel = 64,
917 .maxTessellationPatchSize = 32,
918 .maxTessellationControlPerVertexInputComponents = 128,
919 .maxTessellationControlPerVertexOutputComponents = 128,
920 .maxTessellationControlPerPatchOutputComponents = 120,
921 .maxTessellationControlTotalOutputComponents = 4096,
922 .maxTessellationEvaluationInputComponents = 128,
923 .maxTessellationEvaluationOutputComponents = 128,
924 .maxGeometryShaderInvocations = 127,
925 .maxGeometryInputComponents = 64,
926 .maxGeometryOutputComponents = 128,
927 .maxGeometryOutputVertices = 256,
928 .maxGeometryTotalOutputComponents = 1024,
929 .maxFragmentInputComponents = 128,
930 .maxFragmentOutputAttachments = 8,
931 .maxFragmentDualSrcAttachments = 1,
932 .maxFragmentCombinedOutputResources = 8,
933 .maxComputeSharedMemorySize = 32768,
934 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
935 .maxComputeWorkGroupInvocations = 2048,
936 .maxComputeWorkGroupSize = {
937 2048,
938 2048,
939 2048
940 },
941 .subPixelPrecisionBits = 4 /* FIXME */,
942 .subTexelPrecisionBits = 4 /* FIXME */,
943 .mipmapPrecisionBits = 4 /* FIXME */,
944 .maxDrawIndexedIndexValue = UINT32_MAX,
945 .maxDrawIndirectCount = UINT32_MAX,
946 .maxSamplerLodBias = 16,
947 .maxSamplerAnisotropy = 16,
948 .maxViewports = MAX_VIEWPORTS,
949 .maxViewportDimensions = { (1 << 14), (1 << 14) },
950 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
951 .viewportSubPixelBits = 8,
952 .minMemoryMapAlignment = 4096, /* A page */
953 .minTexelBufferOffsetAlignment = 1,
954 .minUniformBufferOffsetAlignment = 4,
955 .minStorageBufferOffsetAlignment = 4,
956 .minTexelOffset = -32,
957 .maxTexelOffset = 31,
958 .minTexelGatherOffset = -32,
959 .maxTexelGatherOffset = 31,
960 .minInterpolationOffset = -2,
961 .maxInterpolationOffset = 2,
962 .subPixelInterpolationOffsetBits = 8,
963 .maxFramebufferWidth = (1 << 14),
964 .maxFramebufferHeight = (1 << 14),
965 .maxFramebufferLayers = (1 << 10),
966 .framebufferColorSampleCounts = sample_counts,
967 .framebufferDepthSampleCounts = sample_counts,
968 .framebufferStencilSampleCounts = sample_counts,
969 .framebufferNoAttachmentsSampleCounts = sample_counts,
970 .maxColorAttachments = MAX_RTS,
971 .sampledImageColorSampleCounts = sample_counts,
972 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
973 .sampledImageDepthSampleCounts = sample_counts,
974 .sampledImageStencilSampleCounts = sample_counts,
975 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
976 .maxSampleMaskWords = 1,
977 .timestampComputeAndGraphics = true,
978 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
979 .maxClipDistances = 8,
980 .maxCullDistances = 8,
981 .maxCombinedClipAndCullDistances = 8,
982 .discreteQueuePriorities = 1,
983 .pointSizeRange = { 0.125, 255.875 },
984 .lineWidthRange = { 0.0, 7.9921875 },
985 .pointSizeGranularity = (1.0 / 8.0),
986 .lineWidthGranularity = (1.0 / 128.0),
987 .strictLines = false, /* FINISHME */
988 .standardSampleLocations = true,
989 .optimalBufferCopyOffsetAlignment = 128,
990 .optimalBufferCopyRowPitchAlignment = 128,
991 .nonCoherentAtomSize = 64,
992 };
993
994 *pProperties = (VkPhysicalDeviceProperties) {
995 .apiVersion = radv_physical_device_api_version(pdevice),
996 .driverVersion = vk_get_driver_version(),
997 .vendorID = ATI_VENDOR_ID,
998 .deviceID = pdevice->rad_info.pci_id,
999 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1000 .limits = limits,
1001 .sparseProperties = {0},
1002 };
1003
1004 strcpy(pProperties->deviceName, pdevice->name);
1005 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1006 }
1007
1008 void radv_GetPhysicalDeviceProperties2(
1009 VkPhysicalDevice physicalDevice,
1010 VkPhysicalDeviceProperties2KHR *pProperties)
1011 {
1012 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1013 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1014
1015 vk_foreach_struct(ext, pProperties->pNext) {
1016 switch (ext->sType) {
1017 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1018 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1019 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1020 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1021 break;
1022 }
1023 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
1024 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
1025 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1026 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1027 properties->deviceLUIDValid = false;
1028 break;
1029 }
1030 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHR: {
1031 VkPhysicalDeviceMultiviewPropertiesKHR *properties = (VkPhysicalDeviceMultiviewPropertiesKHR*)ext;
1032 properties->maxMultiviewViewCount = MAX_VIEWS;
1033 properties->maxMultiviewInstanceIndex = INT_MAX;
1034 break;
1035 }
1036 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
1037 VkPhysicalDevicePointClippingPropertiesKHR *properties =
1038 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
1039 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
1040 break;
1041 }
1042 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1043 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1044 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1045 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1046 break;
1047 }
1048 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1049 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1050 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1051 properties->minImportedHostPointerAlignment = 4096;
1052 break;
1053 }
1054 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1055 VkPhysicalDeviceSubgroupProperties *properties =
1056 (VkPhysicalDeviceSubgroupProperties*)ext;
1057 properties->subgroupSize = 64;
1058 properties->supportedStages = VK_SHADER_STAGE_ALL;
1059 properties->supportedOperations =
1060 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1061 VK_SUBGROUP_FEATURE_BASIC_BIT |
1062 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1063 VK_SUBGROUP_FEATURE_QUAD_BIT |
1064 VK_SUBGROUP_FEATURE_VOTE_BIT;
1065 if (pdevice->rad_info.chip_class >= VI) {
1066 properties->supportedOperations |=
1067 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1068 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1069 }
1070 properties->quadOperationsInAllStages = true;
1071 break;
1072 }
1073 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1074 VkPhysicalDeviceMaintenance3Properties *properties =
1075 (VkPhysicalDeviceMaintenance3Properties*)ext;
1076 /* Make sure everything is addressable by a signed 32-bit int, and
1077 * our largest descriptors are 96 bytes. */
1078 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1079 /* Our buffer size fields allow only this much */
1080 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1081 break;
1082 }
1083 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1084 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1085 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1086 /* GFX6-8 only support single channel min/max filter. */
1087 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1088 properties->filterMinmaxSingleComponentFormats = true;
1089 break;
1090 }
1091 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1092 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1093 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1094
1095 /* Shader engines. */
1096 properties->shaderEngineCount =
1097 pdevice->rad_info.max_se;
1098 properties->shaderArraysPerEngineCount =
1099 pdevice->rad_info.max_sh_per_se;
1100 properties->computeUnitsPerShaderArray =
1101 pdevice->rad_info.num_good_compute_units /
1102 (pdevice->rad_info.max_se *
1103 pdevice->rad_info.max_sh_per_se);
1104 properties->simdPerComputeUnit = 4;
1105 properties->wavefrontsPerSimd =
1106 pdevice->rad_info.family == CHIP_TONGA ||
1107 pdevice->rad_info.family == CHIP_ICELAND ||
1108 pdevice->rad_info.family == CHIP_POLARIS10 ||
1109 pdevice->rad_info.family == CHIP_POLARIS11 ||
1110 pdevice->rad_info.family == CHIP_POLARIS12 ||
1111 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1112 properties->wavefrontSize = 64;
1113
1114 /* SGPR. */
1115 properties->sgprsPerSimd =
1116 radv_get_num_physical_sgprs(pdevice);
1117 properties->minSgprAllocation =
1118 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1119 properties->maxSgprAllocation =
1120 pdevice->rad_info.family == CHIP_TONGA ||
1121 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1122 properties->sgprAllocationGranularity =
1123 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1124
1125 /* VGPR. */
1126 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1127 properties->minVgprAllocation = 4;
1128 properties->maxVgprAllocation = 256;
1129 properties->vgprAllocationGranularity = 4;
1130 break;
1131 }
1132 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1133 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1134 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1135 properties->maxVertexAttribDivisor = UINT32_MAX;
1136 break;
1137 }
1138 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1139 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1140 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1141 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1142 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1143 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1144 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1145 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1146 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1147 properties->robustBufferAccessUpdateAfterBind = false;
1148 properties->quadDivergentImplicitLod = false;
1149
1150 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1151 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1152 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1153 32 /* sampler, largest when combined with image */ +
1154 64 /* sampled image */ +
1155 64 /* storage image */);
1156 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1157 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1158 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1159 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1160 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1161 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1162 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1163 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1164 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1165 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1166 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1167 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1168 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1169 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1170 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1171 break;
1172 }
1173 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1174 VkPhysicalDeviceProtectedMemoryProperties *properties =
1175 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1176 properties->protectedNoFault = false;
1177 break;
1178 }
1179 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1180 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1181 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1182 properties->primitiveOverestimationSize = 0;
1183 properties->maxExtraPrimitiveOverestimationSize = 0;
1184 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1185 properties->primitiveUnderestimation = VK_FALSE;
1186 properties->conservativePointAndLineRasterization = VK_FALSE;
1187 properties->degenerateTrianglesRasterized = VK_FALSE;
1188 properties->degenerateLinesRasterized = VK_FALSE;
1189 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1190 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1191 break;
1192 }
1193 default:
1194 break;
1195 }
1196 }
1197 }
1198
1199 static void radv_get_physical_device_queue_family_properties(
1200 struct radv_physical_device* pdevice,
1201 uint32_t* pCount,
1202 VkQueueFamilyProperties** pQueueFamilyProperties)
1203 {
1204 int num_queue_families = 1;
1205 int idx;
1206 if (pdevice->rad_info.num_compute_rings > 0 &&
1207 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1208 num_queue_families++;
1209
1210 if (pQueueFamilyProperties == NULL) {
1211 *pCount = num_queue_families;
1212 return;
1213 }
1214
1215 if (!*pCount)
1216 return;
1217
1218 idx = 0;
1219 if (*pCount >= 1) {
1220 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1221 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1222 VK_QUEUE_COMPUTE_BIT |
1223 VK_QUEUE_TRANSFER_BIT |
1224 VK_QUEUE_SPARSE_BINDING_BIT,
1225 .queueCount = 1,
1226 .timestampValidBits = 64,
1227 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1228 };
1229 idx++;
1230 }
1231
1232 if (pdevice->rad_info.num_compute_rings > 0 &&
1233 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1234 if (*pCount > idx) {
1235 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1236 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1237 VK_QUEUE_TRANSFER_BIT |
1238 VK_QUEUE_SPARSE_BINDING_BIT,
1239 .queueCount = pdevice->rad_info.num_compute_rings,
1240 .timestampValidBits = 64,
1241 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1242 };
1243 idx++;
1244 }
1245 }
1246 *pCount = idx;
1247 }
1248
1249 void radv_GetPhysicalDeviceQueueFamilyProperties(
1250 VkPhysicalDevice physicalDevice,
1251 uint32_t* pCount,
1252 VkQueueFamilyProperties* pQueueFamilyProperties)
1253 {
1254 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1255 if (!pQueueFamilyProperties) {
1256 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1257 return;
1258 }
1259 VkQueueFamilyProperties *properties[] = {
1260 pQueueFamilyProperties + 0,
1261 pQueueFamilyProperties + 1,
1262 pQueueFamilyProperties + 2,
1263 };
1264 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1265 assert(*pCount <= 3);
1266 }
1267
1268 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1269 VkPhysicalDevice physicalDevice,
1270 uint32_t* pCount,
1271 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
1272 {
1273 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1274 if (!pQueueFamilyProperties) {
1275 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1276 return;
1277 }
1278 VkQueueFamilyProperties *properties[] = {
1279 &pQueueFamilyProperties[0].queueFamilyProperties,
1280 &pQueueFamilyProperties[1].queueFamilyProperties,
1281 &pQueueFamilyProperties[2].queueFamilyProperties,
1282 };
1283 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1284 assert(*pCount <= 3);
1285 }
1286
1287 void radv_GetPhysicalDeviceMemoryProperties(
1288 VkPhysicalDevice physicalDevice,
1289 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1290 {
1291 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1292
1293 *pMemoryProperties = physical_device->memory_properties;
1294 }
1295
1296 void radv_GetPhysicalDeviceMemoryProperties2(
1297 VkPhysicalDevice physicalDevice,
1298 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
1299 {
1300 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1301 &pMemoryProperties->memoryProperties);
1302 }
1303
1304 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1305 VkDevice _device,
1306 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
1307 const void *pHostPointer,
1308 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1309 {
1310 RADV_FROM_HANDLE(radv_device, device, _device);
1311
1312 switch (handleType)
1313 {
1314 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1315 const struct radv_physical_device *physical_device = device->physical_device;
1316 uint32_t memoryTypeBits = 0;
1317 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1318 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1319 memoryTypeBits = (1 << i);
1320 break;
1321 }
1322 }
1323 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1324 return VK_SUCCESS;
1325 }
1326 default:
1327 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
1328 }
1329 }
1330
1331 static enum radeon_ctx_priority
1332 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1333 {
1334 /* Default to MEDIUM when a specific global priority isn't requested */
1335 if (!pObj)
1336 return RADEON_CTX_PRIORITY_MEDIUM;
1337
1338 switch(pObj->globalPriority) {
1339 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1340 return RADEON_CTX_PRIORITY_REALTIME;
1341 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1342 return RADEON_CTX_PRIORITY_HIGH;
1343 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1344 return RADEON_CTX_PRIORITY_MEDIUM;
1345 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1346 return RADEON_CTX_PRIORITY_LOW;
1347 default:
1348 unreachable("Illegal global priority value");
1349 return RADEON_CTX_PRIORITY_INVALID;
1350 }
1351 }
1352
1353 static int
1354 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1355 uint32_t queue_family_index, int idx,
1356 VkDeviceQueueCreateFlags flags,
1357 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1358 {
1359 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1360 queue->device = device;
1361 queue->queue_family_index = queue_family_index;
1362 queue->queue_idx = idx;
1363 queue->priority = radv_get_queue_global_priority(global_priority);
1364 queue->flags = flags;
1365
1366 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1367 if (!queue->hw_ctx)
1368 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1369
1370 return VK_SUCCESS;
1371 }
1372
1373 static void
1374 radv_queue_finish(struct radv_queue *queue)
1375 {
1376 if (queue->hw_ctx)
1377 queue->device->ws->ctx_destroy(queue->hw_ctx);
1378
1379 if (queue->initial_full_flush_preamble_cs)
1380 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1381 if (queue->initial_preamble_cs)
1382 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1383 if (queue->continue_preamble_cs)
1384 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1385 if (queue->descriptor_bo)
1386 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1387 if (queue->scratch_bo)
1388 queue->device->ws->buffer_destroy(queue->scratch_bo);
1389 if (queue->esgs_ring_bo)
1390 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1391 if (queue->gsvs_ring_bo)
1392 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1393 if (queue->tess_rings_bo)
1394 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1395 if (queue->compute_scratch_bo)
1396 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1397 }
1398
1399 static void
1400 radv_bo_list_init(struct radv_bo_list *bo_list)
1401 {
1402 pthread_mutex_init(&bo_list->mutex, NULL);
1403 bo_list->list.count = bo_list->capacity = 0;
1404 bo_list->list.bos = NULL;
1405 }
1406
1407 static void
1408 radv_bo_list_finish(struct radv_bo_list *bo_list)
1409 {
1410 free(bo_list->list.bos);
1411 pthread_mutex_destroy(&bo_list->mutex);
1412 }
1413
1414 static VkResult radv_bo_list_add(struct radv_device *device,
1415 struct radeon_winsys_bo *bo)
1416 {
1417 struct radv_bo_list *bo_list = &device->bo_list;
1418
1419 if (unlikely(!device->use_global_bo_list))
1420 return VK_SUCCESS;
1421
1422 pthread_mutex_lock(&bo_list->mutex);
1423 if (bo_list->list.count == bo_list->capacity) {
1424 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1425 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1426
1427 if (!data) {
1428 pthread_mutex_unlock(&bo_list->mutex);
1429 return VK_ERROR_OUT_OF_HOST_MEMORY;
1430 }
1431
1432 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1433 bo_list->capacity = capacity;
1434 }
1435
1436 bo_list->list.bos[bo_list->list.count++] = bo;
1437 pthread_mutex_unlock(&bo_list->mutex);
1438 return VK_SUCCESS;
1439 }
1440
1441 static void radv_bo_list_remove(struct radv_device *device,
1442 struct radeon_winsys_bo *bo)
1443 {
1444 struct radv_bo_list *bo_list = &device->bo_list;
1445
1446 if (unlikely(!device->use_global_bo_list))
1447 return;
1448
1449 pthread_mutex_lock(&bo_list->mutex);
1450 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1451 if (bo_list->list.bos[i] == bo) {
1452 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1453 --bo_list->list.count;
1454 break;
1455 }
1456 }
1457 pthread_mutex_unlock(&bo_list->mutex);
1458 }
1459
1460 static void
1461 radv_device_init_gs_info(struct radv_device *device)
1462 {
1463 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1464 device->physical_device->rad_info.family);
1465 }
1466
1467 static int radv_get_device_extension_index(const char *name)
1468 {
1469 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1470 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1471 return i;
1472 }
1473 return -1;
1474 }
1475
1476 static int
1477 radv_get_int_debug_option(const char *name, int default_value)
1478 {
1479 const char *str;
1480 int result;
1481
1482 str = getenv(name);
1483 if (!str) {
1484 result = default_value;
1485 } else {
1486 char *endptr;
1487
1488 result = strtol(str, &endptr, 0);
1489 if (str == endptr) {
1490 /* No digits founs. */
1491 result = default_value;
1492 }
1493 }
1494
1495 return result;
1496 }
1497
1498 VkResult radv_CreateDevice(
1499 VkPhysicalDevice physicalDevice,
1500 const VkDeviceCreateInfo* pCreateInfo,
1501 const VkAllocationCallbacks* pAllocator,
1502 VkDevice* pDevice)
1503 {
1504 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1505 VkResult result;
1506 struct radv_device *device;
1507
1508 bool keep_shader_info = false;
1509
1510 /* Check enabled features */
1511 if (pCreateInfo->pEnabledFeatures) {
1512 VkPhysicalDeviceFeatures supported_features;
1513 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1514 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1515 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1516 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1517 for (uint32_t i = 0; i < num_features; i++) {
1518 if (enabled_feature[i] && !supported_feature[i])
1519 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1520 }
1521 }
1522
1523 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1524 sizeof(*device), 8,
1525 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1526 if (!device)
1527 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1528
1529 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1530 device->instance = physical_device->instance;
1531 device->physical_device = physical_device;
1532
1533 device->ws = physical_device->ws;
1534 if (pAllocator)
1535 device->alloc = *pAllocator;
1536 else
1537 device->alloc = physical_device->instance->alloc;
1538
1539 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1540 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1541 int index = radv_get_device_extension_index(ext_name);
1542 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1543 vk_free(&device->alloc, device);
1544 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1545 }
1546
1547 device->enabled_extensions.extensions[index] = true;
1548 }
1549
1550 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1551
1552 /* With update after bind we can't attach bo's to the command buffer
1553 * from the descriptor set anymore, so we have to use a global BO list.
1554 */
1555 device->use_global_bo_list =
1556 device->enabled_extensions.EXT_descriptor_indexing;
1557
1558 mtx_init(&device->shader_slab_mutex, mtx_plain);
1559 list_inithead(&device->shader_slabs);
1560
1561 radv_bo_list_init(&device->bo_list);
1562
1563 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1564 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1565 uint32_t qfi = queue_create->queueFamilyIndex;
1566 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1567 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1568
1569 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1570
1571 device->queues[qfi] = vk_alloc(&device->alloc,
1572 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1573 if (!device->queues[qfi]) {
1574 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1575 goto fail;
1576 }
1577
1578 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1579
1580 device->queue_count[qfi] = queue_create->queueCount;
1581
1582 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1583 result = radv_queue_init(device, &device->queues[qfi][q],
1584 qfi, q, queue_create->flags,
1585 global_priority);
1586 if (result != VK_SUCCESS)
1587 goto fail;
1588 }
1589 }
1590
1591 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1592 ((device->instance->perftest_flags & RADV_PERFTEST_BINNING) ||
1593 device->physical_device->rad_info.family == CHIP_RAVEN);
1594
1595 /* Disabled and not implemented for now. */
1596 device->dfsm_allowed = device->pbb_allowed &&
1597 device->physical_device->rad_info.family == CHIP_RAVEN;
1598
1599 #ifdef ANDROID
1600 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1601 #endif
1602
1603 /* The maximum number of scratch waves. Scratch space isn't divided
1604 * evenly between CUs. The number is only a function of the number of CUs.
1605 * We can decrease the constant to decrease the scratch buffer size.
1606 *
1607 * sctx->scratch_waves must be >= the maximum possible size of
1608 * 1 threadgroup, so that the hw doesn't hang from being unable
1609 * to start any.
1610 *
1611 * The recommended value is 4 per CU at most. Higher numbers don't
1612 * bring much benefit, but they still occupy chip resources (think
1613 * async compute). I've seen ~2% performance difference between 4 and 32.
1614 */
1615 uint32_t max_threads_per_block = 2048;
1616 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1617 max_threads_per_block / 64);
1618
1619 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1620
1621 if (device->physical_device->rad_info.chip_class >= CIK) {
1622 /* If the KMD allows it (there is a KMD hw register for it),
1623 * allow launching waves out-of-order.
1624 */
1625 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1626 }
1627
1628 radv_device_init_gs_info(device);
1629
1630 device->tess_offchip_block_dw_size =
1631 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1632 device->has_distributed_tess =
1633 device->physical_device->rad_info.chip_class >= VI &&
1634 device->physical_device->rad_info.max_se >= 2;
1635
1636 if (getenv("RADV_TRACE_FILE")) {
1637 const char *filename = getenv("RADV_TRACE_FILE");
1638
1639 keep_shader_info = true;
1640
1641 if (!radv_init_trace(device))
1642 goto fail;
1643
1644 fprintf(stderr, "*****************************************************************************\n");
1645 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1646 fprintf(stderr, "*****************************************************************************\n");
1647
1648 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1649 radv_dump_enabled_options(device, stderr);
1650 }
1651
1652 device->keep_shader_info = keep_shader_info;
1653
1654 result = radv_device_init_meta(device);
1655 if (result != VK_SUCCESS)
1656 goto fail;
1657
1658 radv_device_init_msaa(device);
1659
1660 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1661 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1662 switch (family) {
1663 case RADV_QUEUE_GENERAL:
1664 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1665 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1666 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1667 break;
1668 case RADV_QUEUE_COMPUTE:
1669 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1670 radeon_emit(device->empty_cs[family], 0);
1671 break;
1672 }
1673 device->ws->cs_finalize(device->empty_cs[family]);
1674 }
1675
1676 if (device->physical_device->rad_info.chip_class >= CIK)
1677 cik_create_gfx_config(device);
1678
1679 VkPipelineCacheCreateInfo ci;
1680 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1681 ci.pNext = NULL;
1682 ci.flags = 0;
1683 ci.pInitialData = NULL;
1684 ci.initialDataSize = 0;
1685 VkPipelineCache pc;
1686 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1687 &ci, NULL, &pc);
1688 if (result != VK_SUCCESS)
1689 goto fail_meta;
1690
1691 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1692
1693 device->force_aniso =
1694 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
1695 if (device->force_aniso >= 0) {
1696 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
1697 1 << util_logbase2(device->force_aniso));
1698 }
1699
1700 *pDevice = radv_device_to_handle(device);
1701 return VK_SUCCESS;
1702
1703 fail_meta:
1704 radv_device_finish_meta(device);
1705 fail:
1706 radv_bo_list_finish(&device->bo_list);
1707
1708 if (device->trace_bo)
1709 device->ws->buffer_destroy(device->trace_bo);
1710
1711 if (device->gfx_init)
1712 device->ws->buffer_destroy(device->gfx_init);
1713
1714 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1715 for (unsigned q = 0; q < device->queue_count[i]; q++)
1716 radv_queue_finish(&device->queues[i][q]);
1717 if (device->queue_count[i])
1718 vk_free(&device->alloc, device->queues[i]);
1719 }
1720
1721 vk_free(&device->alloc, device);
1722 return result;
1723 }
1724
1725 void radv_DestroyDevice(
1726 VkDevice _device,
1727 const VkAllocationCallbacks* pAllocator)
1728 {
1729 RADV_FROM_HANDLE(radv_device, device, _device);
1730
1731 if (!device)
1732 return;
1733
1734 if (device->trace_bo)
1735 device->ws->buffer_destroy(device->trace_bo);
1736
1737 if (device->gfx_init)
1738 device->ws->buffer_destroy(device->gfx_init);
1739
1740 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1741 for (unsigned q = 0; q < device->queue_count[i]; q++)
1742 radv_queue_finish(&device->queues[i][q]);
1743 if (device->queue_count[i])
1744 vk_free(&device->alloc, device->queues[i]);
1745 if (device->empty_cs[i])
1746 device->ws->cs_destroy(device->empty_cs[i]);
1747 }
1748 radv_device_finish_meta(device);
1749
1750 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1751 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1752
1753 radv_destroy_shader_slabs(device);
1754
1755 radv_bo_list_finish(&device->bo_list);
1756 vk_free(&device->alloc, device);
1757 }
1758
1759 VkResult radv_EnumerateInstanceLayerProperties(
1760 uint32_t* pPropertyCount,
1761 VkLayerProperties* pProperties)
1762 {
1763 if (pProperties == NULL) {
1764 *pPropertyCount = 0;
1765 return VK_SUCCESS;
1766 }
1767
1768 /* None supported at this time */
1769 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1770 }
1771
1772 VkResult radv_EnumerateDeviceLayerProperties(
1773 VkPhysicalDevice physicalDevice,
1774 uint32_t* pPropertyCount,
1775 VkLayerProperties* pProperties)
1776 {
1777 if (pProperties == NULL) {
1778 *pPropertyCount = 0;
1779 return VK_SUCCESS;
1780 }
1781
1782 /* None supported at this time */
1783 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1784 }
1785
1786 void radv_GetDeviceQueue2(
1787 VkDevice _device,
1788 const VkDeviceQueueInfo2* pQueueInfo,
1789 VkQueue* pQueue)
1790 {
1791 RADV_FROM_HANDLE(radv_device, device, _device);
1792 struct radv_queue *queue;
1793
1794 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
1795 if (pQueueInfo->flags != queue->flags) {
1796 /* From the Vulkan 1.1.70 spec:
1797 *
1798 * "The queue returned by vkGetDeviceQueue2 must have the same
1799 * flags value from this structure as that used at device
1800 * creation time in a VkDeviceQueueCreateInfo instance. If no
1801 * matching flags were specified at device creation time then
1802 * pQueue will return VK_NULL_HANDLE."
1803 */
1804 *pQueue = VK_NULL_HANDLE;
1805 return;
1806 }
1807
1808 *pQueue = radv_queue_to_handle(queue);
1809 }
1810
1811 void radv_GetDeviceQueue(
1812 VkDevice _device,
1813 uint32_t queueFamilyIndex,
1814 uint32_t queueIndex,
1815 VkQueue* pQueue)
1816 {
1817 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
1818 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
1819 .queueFamilyIndex = queueFamilyIndex,
1820 .queueIndex = queueIndex
1821 };
1822
1823 radv_GetDeviceQueue2(_device, &info, pQueue);
1824 }
1825
1826 static void
1827 fill_geom_tess_rings(struct radv_queue *queue,
1828 uint32_t *map,
1829 bool add_sample_positions,
1830 uint32_t esgs_ring_size,
1831 struct radeon_winsys_bo *esgs_ring_bo,
1832 uint32_t gsvs_ring_size,
1833 struct radeon_winsys_bo *gsvs_ring_bo,
1834 uint32_t tess_factor_ring_size,
1835 uint32_t tess_offchip_ring_offset,
1836 uint32_t tess_offchip_ring_size,
1837 struct radeon_winsys_bo *tess_rings_bo)
1838 {
1839 uint64_t esgs_va = 0, gsvs_va = 0;
1840 uint64_t tess_va = 0, tess_offchip_va = 0;
1841 uint32_t *desc = &map[4];
1842
1843 if (esgs_ring_bo)
1844 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1845 if (gsvs_ring_bo)
1846 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1847 if (tess_rings_bo) {
1848 tess_va = radv_buffer_get_va(tess_rings_bo);
1849 tess_offchip_va = tess_va + tess_offchip_ring_offset;
1850 }
1851
1852 /* stride 0, num records - size, add tid, swizzle, elsize4,
1853 index stride 64 */
1854 desc[0] = esgs_va;
1855 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1856 S_008F04_STRIDE(0) |
1857 S_008F04_SWIZZLE_ENABLE(true);
1858 desc[2] = esgs_ring_size;
1859 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1860 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1861 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1862 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1863 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1864 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1865 S_008F0C_ELEMENT_SIZE(1) |
1866 S_008F0C_INDEX_STRIDE(3) |
1867 S_008F0C_ADD_TID_ENABLE(true);
1868
1869 desc += 4;
1870 /* GS entry for ES->GS ring */
1871 /* stride 0, num records - size, elsize0,
1872 index stride 0 */
1873 desc[0] = esgs_va;
1874 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1875 S_008F04_STRIDE(0) |
1876 S_008F04_SWIZZLE_ENABLE(false);
1877 desc[2] = esgs_ring_size;
1878 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1879 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1880 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1881 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1882 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1883 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1884 S_008F0C_ELEMENT_SIZE(0) |
1885 S_008F0C_INDEX_STRIDE(0) |
1886 S_008F0C_ADD_TID_ENABLE(false);
1887
1888 desc += 4;
1889 /* VS entry for GS->VS ring */
1890 /* stride 0, num records - size, elsize0,
1891 index stride 0 */
1892 desc[0] = gsvs_va;
1893 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1894 S_008F04_STRIDE(0) |
1895 S_008F04_SWIZZLE_ENABLE(false);
1896 desc[2] = gsvs_ring_size;
1897 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1898 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1899 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1900 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1901 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1902 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1903 S_008F0C_ELEMENT_SIZE(0) |
1904 S_008F0C_INDEX_STRIDE(0) |
1905 S_008F0C_ADD_TID_ENABLE(false);
1906 desc += 4;
1907
1908 /* stride gsvs_itemsize, num records 64
1909 elsize 4, index stride 16 */
1910 /* shader will patch stride and desc[2] */
1911 desc[0] = gsvs_va;
1912 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1913 S_008F04_STRIDE(0) |
1914 S_008F04_SWIZZLE_ENABLE(true);
1915 desc[2] = 0;
1916 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1917 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1918 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1919 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1920 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1921 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1922 S_008F0C_ELEMENT_SIZE(1) |
1923 S_008F0C_INDEX_STRIDE(1) |
1924 S_008F0C_ADD_TID_ENABLE(true);
1925 desc += 4;
1926
1927 desc[0] = tess_va;
1928 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
1929 S_008F04_STRIDE(0) |
1930 S_008F04_SWIZZLE_ENABLE(false);
1931 desc[2] = tess_factor_ring_size;
1932 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1933 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1934 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1935 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1936 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1937 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1938 S_008F0C_ELEMENT_SIZE(0) |
1939 S_008F0C_INDEX_STRIDE(0) |
1940 S_008F0C_ADD_TID_ENABLE(false);
1941 desc += 4;
1942
1943 desc[0] = tess_offchip_va;
1944 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1945 S_008F04_STRIDE(0) |
1946 S_008F04_SWIZZLE_ENABLE(false);
1947 desc[2] = tess_offchip_ring_size;
1948 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1949 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1950 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1951 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1952 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1953 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1954 S_008F0C_ELEMENT_SIZE(0) |
1955 S_008F0C_INDEX_STRIDE(0) |
1956 S_008F0C_ADD_TID_ENABLE(false);
1957 desc += 4;
1958
1959 /* add sample positions after all rings */
1960 memcpy(desc, queue->device->sample_locations_1x, 8);
1961 desc += 2;
1962 memcpy(desc, queue->device->sample_locations_2x, 16);
1963 desc += 4;
1964 memcpy(desc, queue->device->sample_locations_4x, 32);
1965 desc += 8;
1966 memcpy(desc, queue->device->sample_locations_8x, 64);
1967 desc += 16;
1968 memcpy(desc, queue->device->sample_locations_16x, 128);
1969 }
1970
1971 static unsigned
1972 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1973 {
1974 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1975 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1976 device->physical_device->rad_info.family != CHIP_STONEY;
1977 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1978 unsigned max_offchip_buffers;
1979 unsigned offchip_granularity;
1980 unsigned hs_offchip_param;
1981
1982 /*
1983 * Per RadeonSI:
1984 * This must be one less than the maximum number due to a hw limitation.
1985 * Various hardware bugs in SI, CIK, and GFX9 need this.
1986 *
1987 * Per AMDVLK:
1988 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
1989 * Gfx7 should limit max_offchip_buffers to 508
1990 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
1991 *
1992 * Follow AMDVLK here.
1993 */
1994 if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
1995 device->physical_device->rad_info.chip_class == CIK ||
1996 device->physical_device->rad_info.chip_class == SI)
1997 --max_offchip_buffers_per_se;
1998
1999 max_offchip_buffers = max_offchip_buffers_per_se *
2000 device->physical_device->rad_info.max_se;
2001
2002 switch (device->tess_offchip_block_dw_size) {
2003 default:
2004 assert(0);
2005 /* fall through */
2006 case 8192:
2007 offchip_granularity = V_03093C_X_8K_DWORDS;
2008 break;
2009 case 4096:
2010 offchip_granularity = V_03093C_X_4K_DWORDS;
2011 break;
2012 }
2013
2014 switch (device->physical_device->rad_info.chip_class) {
2015 case SI:
2016 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2017 break;
2018 case CIK:
2019 case VI:
2020 case GFX9:
2021 default:
2022 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2023 break;
2024 }
2025
2026 *max_offchip_buffers_p = max_offchip_buffers;
2027 if (device->physical_device->rad_info.chip_class >= CIK) {
2028 if (device->physical_device->rad_info.chip_class >= VI)
2029 --max_offchip_buffers;
2030 hs_offchip_param =
2031 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2032 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2033 } else {
2034 hs_offchip_param =
2035 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2036 }
2037 return hs_offchip_param;
2038 }
2039
2040 static void
2041 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2042 struct radeon_winsys_bo *esgs_ring_bo,
2043 uint32_t esgs_ring_size,
2044 struct radeon_winsys_bo *gsvs_ring_bo,
2045 uint32_t gsvs_ring_size)
2046 {
2047 if (!esgs_ring_bo && !gsvs_ring_bo)
2048 return;
2049
2050 if (esgs_ring_bo)
2051 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2052
2053 if (gsvs_ring_bo)
2054 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2055
2056 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2057 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2058 radeon_emit(cs, esgs_ring_size >> 8);
2059 radeon_emit(cs, gsvs_ring_size >> 8);
2060 } else {
2061 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2062 radeon_emit(cs, esgs_ring_size >> 8);
2063 radeon_emit(cs, gsvs_ring_size >> 8);
2064 }
2065 }
2066
2067 static void
2068 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2069 unsigned hs_offchip_param, unsigned tf_ring_size,
2070 struct radeon_winsys_bo *tess_rings_bo)
2071 {
2072 uint64_t tf_va;
2073
2074 if (!tess_rings_bo)
2075 return;
2076
2077 tf_va = radv_buffer_get_va(tess_rings_bo);
2078
2079 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2080
2081 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2082 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2083 S_030938_SIZE(tf_ring_size / 4));
2084 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2085 tf_va >> 8);
2086 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2087 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2088 S_030944_BASE_HI(tf_va >> 40));
2089 }
2090 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2091 hs_offchip_param);
2092 } else {
2093 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2094 S_008988_SIZE(tf_ring_size / 4));
2095 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2096 tf_va >> 8);
2097 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2098 hs_offchip_param);
2099 }
2100 }
2101
2102 static void
2103 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2104 struct radeon_winsys_bo *compute_scratch_bo)
2105 {
2106 uint64_t scratch_va;
2107
2108 if (!compute_scratch_bo)
2109 return;
2110
2111 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2112
2113 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2114
2115 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2116 radeon_emit(cs, scratch_va);
2117 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2118 S_008F04_SWIZZLE_ENABLE(1));
2119 }
2120
2121 static void
2122 radv_emit_global_shader_pointers(struct radv_queue *queue,
2123 struct radeon_cmdbuf *cs,
2124 struct radeon_winsys_bo *descriptor_bo)
2125 {
2126 uint64_t va;
2127
2128 if (!descriptor_bo)
2129 return;
2130
2131 va = radv_buffer_get_va(descriptor_bo);
2132
2133 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2134
2135 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2136 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2137 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2138 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2139 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2140
2141 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2142 radv_emit_shader_pointer(queue->device, cs, regs[i],
2143 va, true);
2144 }
2145 } else {
2146 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2147 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2148 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2149 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2150 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2151 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2152
2153 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2154 radv_emit_shader_pointer(queue->device, cs, regs[i],
2155 va, true);
2156 }
2157 }
2158 }
2159
2160 static void
2161 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2162 {
2163 struct radv_device *device = queue->device;
2164
2165 if (device->gfx_init) {
2166 uint64_t va = radv_buffer_get_va(device->gfx_init);
2167
2168 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2169 radeon_emit(cs, va);
2170 radeon_emit(cs, va >> 32);
2171 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2172
2173 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2174 } else {
2175 struct radv_physical_device *physical_device = device->physical_device;
2176 si_emit_graphics(physical_device, cs);
2177 }
2178 }
2179
2180 static void
2181 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2182 {
2183 struct radv_physical_device *physical_device = queue->device->physical_device;
2184 si_emit_compute(physical_device, cs);
2185 }
2186
2187 static VkResult
2188 radv_get_preamble_cs(struct radv_queue *queue,
2189 uint32_t scratch_size,
2190 uint32_t compute_scratch_size,
2191 uint32_t esgs_ring_size,
2192 uint32_t gsvs_ring_size,
2193 bool needs_tess_rings,
2194 bool needs_sample_positions,
2195 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2196 struct radeon_cmdbuf **initial_preamble_cs,
2197 struct radeon_cmdbuf **continue_preamble_cs)
2198 {
2199 struct radeon_winsys_bo *scratch_bo = NULL;
2200 struct radeon_winsys_bo *descriptor_bo = NULL;
2201 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2202 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2203 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2204 struct radeon_winsys_bo *tess_rings_bo = NULL;
2205 struct radeon_cmdbuf *dest_cs[3] = {0};
2206 bool add_tess_rings = false, add_sample_positions = false;
2207 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2208 unsigned max_offchip_buffers;
2209 unsigned hs_offchip_param = 0;
2210 unsigned tess_offchip_ring_offset;
2211 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2212 if (!queue->has_tess_rings) {
2213 if (needs_tess_rings)
2214 add_tess_rings = true;
2215 }
2216 if (!queue->has_sample_positions) {
2217 if (needs_sample_positions)
2218 add_sample_positions = true;
2219 }
2220 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2221 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2222 &max_offchip_buffers);
2223 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2224 tess_offchip_ring_size = max_offchip_buffers *
2225 queue->device->tess_offchip_block_dw_size * 4;
2226
2227 if (scratch_size <= queue->scratch_size &&
2228 compute_scratch_size <= queue->compute_scratch_size &&
2229 esgs_ring_size <= queue->esgs_ring_size &&
2230 gsvs_ring_size <= queue->gsvs_ring_size &&
2231 !add_tess_rings && !add_sample_positions &&
2232 queue->initial_preamble_cs) {
2233 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2234 *initial_preamble_cs = queue->initial_preamble_cs;
2235 *continue_preamble_cs = queue->continue_preamble_cs;
2236 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2237 *continue_preamble_cs = NULL;
2238 return VK_SUCCESS;
2239 }
2240
2241 if (scratch_size > queue->scratch_size) {
2242 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2243 scratch_size,
2244 4096,
2245 RADEON_DOMAIN_VRAM,
2246 ring_bo_flags);
2247 if (!scratch_bo)
2248 goto fail;
2249 } else
2250 scratch_bo = queue->scratch_bo;
2251
2252 if (compute_scratch_size > queue->compute_scratch_size) {
2253 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2254 compute_scratch_size,
2255 4096,
2256 RADEON_DOMAIN_VRAM,
2257 ring_bo_flags);
2258 if (!compute_scratch_bo)
2259 goto fail;
2260
2261 } else
2262 compute_scratch_bo = queue->compute_scratch_bo;
2263
2264 if (esgs_ring_size > queue->esgs_ring_size) {
2265 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2266 esgs_ring_size,
2267 4096,
2268 RADEON_DOMAIN_VRAM,
2269 ring_bo_flags);
2270 if (!esgs_ring_bo)
2271 goto fail;
2272 } else {
2273 esgs_ring_bo = queue->esgs_ring_bo;
2274 esgs_ring_size = queue->esgs_ring_size;
2275 }
2276
2277 if (gsvs_ring_size > queue->gsvs_ring_size) {
2278 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2279 gsvs_ring_size,
2280 4096,
2281 RADEON_DOMAIN_VRAM,
2282 ring_bo_flags);
2283 if (!gsvs_ring_bo)
2284 goto fail;
2285 } else {
2286 gsvs_ring_bo = queue->gsvs_ring_bo;
2287 gsvs_ring_size = queue->gsvs_ring_size;
2288 }
2289
2290 if (add_tess_rings) {
2291 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2292 tess_offchip_ring_offset + tess_offchip_ring_size,
2293 256,
2294 RADEON_DOMAIN_VRAM,
2295 ring_bo_flags);
2296 if (!tess_rings_bo)
2297 goto fail;
2298 } else {
2299 tess_rings_bo = queue->tess_rings_bo;
2300 }
2301
2302 if (scratch_bo != queue->scratch_bo ||
2303 esgs_ring_bo != queue->esgs_ring_bo ||
2304 gsvs_ring_bo != queue->gsvs_ring_bo ||
2305 tess_rings_bo != queue->tess_rings_bo ||
2306 add_sample_positions) {
2307 uint32_t size = 0;
2308 if (gsvs_ring_bo || esgs_ring_bo ||
2309 tess_rings_bo || add_sample_positions) {
2310 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2311 if (add_sample_positions)
2312 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
2313 }
2314 else if (scratch_bo)
2315 size = 8; /* 2 dword */
2316
2317 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2318 size,
2319 4096,
2320 RADEON_DOMAIN_VRAM,
2321 RADEON_FLAG_CPU_ACCESS |
2322 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2323 RADEON_FLAG_READ_ONLY);
2324 if (!descriptor_bo)
2325 goto fail;
2326 } else
2327 descriptor_bo = queue->descriptor_bo;
2328
2329 for(int i = 0; i < 3; ++i) {
2330 struct radeon_cmdbuf *cs = NULL;
2331 cs = queue->device->ws->cs_create(queue->device->ws,
2332 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2333 if (!cs)
2334 goto fail;
2335
2336 dest_cs[i] = cs;
2337
2338 if (scratch_bo)
2339 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2340
2341 /* Emit initial configuration. */
2342 switch (queue->queue_family_index) {
2343 case RADV_QUEUE_GENERAL:
2344 radv_init_graphics_state(cs, queue);
2345 break;
2346 case RADV_QUEUE_COMPUTE:
2347 radv_init_compute_state(cs, queue);
2348 break;
2349 case RADV_QUEUE_TRANSFER:
2350 break;
2351 }
2352
2353 if (descriptor_bo != queue->descriptor_bo) {
2354 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2355
2356 if (scratch_bo) {
2357 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2358 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2359 S_008F04_SWIZZLE_ENABLE(1);
2360 map[0] = scratch_va;
2361 map[1] = rsrc1;
2362 }
2363
2364 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo ||
2365 add_sample_positions)
2366 fill_geom_tess_rings(queue, map, add_sample_positions,
2367 esgs_ring_size, esgs_ring_bo,
2368 gsvs_ring_size, gsvs_ring_bo,
2369 tess_factor_ring_size,
2370 tess_offchip_ring_offset,
2371 tess_offchip_ring_size,
2372 tess_rings_bo);
2373
2374 queue->device->ws->buffer_unmap(descriptor_bo);
2375 }
2376
2377 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2378 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2379 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2380 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2381 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2382 }
2383
2384 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2385 gsvs_ring_bo, gsvs_ring_size);
2386 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2387 tess_factor_ring_size, tess_rings_bo);
2388 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2389 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2390
2391 if (i == 0) {
2392 si_cs_emit_cache_flush(cs,
2393 queue->device->physical_device->rad_info.chip_class,
2394 NULL, 0,
2395 queue->queue_family_index == RING_COMPUTE &&
2396 queue->device->physical_device->rad_info.chip_class >= CIK,
2397 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2398 RADV_CMD_FLAG_INV_ICACHE |
2399 RADV_CMD_FLAG_INV_SMEM_L1 |
2400 RADV_CMD_FLAG_INV_VMEM_L1 |
2401 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2402 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2403 } else if (i == 1) {
2404 si_cs_emit_cache_flush(cs,
2405 queue->device->physical_device->rad_info.chip_class,
2406 NULL, 0,
2407 queue->queue_family_index == RING_COMPUTE &&
2408 queue->device->physical_device->rad_info.chip_class >= CIK,
2409 RADV_CMD_FLAG_INV_ICACHE |
2410 RADV_CMD_FLAG_INV_SMEM_L1 |
2411 RADV_CMD_FLAG_INV_VMEM_L1 |
2412 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2413 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2414 }
2415
2416 if (!queue->device->ws->cs_finalize(cs))
2417 goto fail;
2418 }
2419
2420 if (queue->initial_full_flush_preamble_cs)
2421 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2422
2423 if (queue->initial_preamble_cs)
2424 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2425
2426 if (queue->continue_preamble_cs)
2427 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2428
2429 queue->initial_full_flush_preamble_cs = dest_cs[0];
2430 queue->initial_preamble_cs = dest_cs[1];
2431 queue->continue_preamble_cs = dest_cs[2];
2432
2433 if (scratch_bo != queue->scratch_bo) {
2434 if (queue->scratch_bo)
2435 queue->device->ws->buffer_destroy(queue->scratch_bo);
2436 queue->scratch_bo = scratch_bo;
2437 queue->scratch_size = scratch_size;
2438 }
2439
2440 if (compute_scratch_bo != queue->compute_scratch_bo) {
2441 if (queue->compute_scratch_bo)
2442 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2443 queue->compute_scratch_bo = compute_scratch_bo;
2444 queue->compute_scratch_size = compute_scratch_size;
2445 }
2446
2447 if (esgs_ring_bo != queue->esgs_ring_bo) {
2448 if (queue->esgs_ring_bo)
2449 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2450 queue->esgs_ring_bo = esgs_ring_bo;
2451 queue->esgs_ring_size = esgs_ring_size;
2452 }
2453
2454 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2455 if (queue->gsvs_ring_bo)
2456 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2457 queue->gsvs_ring_bo = gsvs_ring_bo;
2458 queue->gsvs_ring_size = gsvs_ring_size;
2459 }
2460
2461 if (tess_rings_bo != queue->tess_rings_bo) {
2462 queue->tess_rings_bo = tess_rings_bo;
2463 queue->has_tess_rings = true;
2464 }
2465
2466 if (descriptor_bo != queue->descriptor_bo) {
2467 if (queue->descriptor_bo)
2468 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2469
2470 queue->descriptor_bo = descriptor_bo;
2471 }
2472
2473 if (add_sample_positions)
2474 queue->has_sample_positions = true;
2475
2476 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2477 *initial_preamble_cs = queue->initial_preamble_cs;
2478 *continue_preamble_cs = queue->continue_preamble_cs;
2479 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2480 *continue_preamble_cs = NULL;
2481 return VK_SUCCESS;
2482 fail:
2483 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2484 if (dest_cs[i])
2485 queue->device->ws->cs_destroy(dest_cs[i]);
2486 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2487 queue->device->ws->buffer_destroy(descriptor_bo);
2488 if (scratch_bo && scratch_bo != queue->scratch_bo)
2489 queue->device->ws->buffer_destroy(scratch_bo);
2490 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2491 queue->device->ws->buffer_destroy(compute_scratch_bo);
2492 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2493 queue->device->ws->buffer_destroy(esgs_ring_bo);
2494 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2495 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2496 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2497 queue->device->ws->buffer_destroy(tess_rings_bo);
2498 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2499 }
2500
2501 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2502 struct radv_winsys_sem_counts *counts,
2503 int num_sems,
2504 const VkSemaphore *sems,
2505 VkFence _fence,
2506 bool reset_temp)
2507 {
2508 int syncobj_idx = 0, sem_idx = 0;
2509
2510 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2511 return VK_SUCCESS;
2512
2513 for (uint32_t i = 0; i < num_sems; i++) {
2514 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2515
2516 if (sem->temp_syncobj || sem->syncobj)
2517 counts->syncobj_count++;
2518 else
2519 counts->sem_count++;
2520 }
2521
2522 if (_fence != VK_NULL_HANDLE) {
2523 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2524 if (fence->temp_syncobj || fence->syncobj)
2525 counts->syncobj_count++;
2526 }
2527
2528 if (counts->syncobj_count) {
2529 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2530 if (!counts->syncobj)
2531 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2532 }
2533
2534 if (counts->sem_count) {
2535 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2536 if (!counts->sem) {
2537 free(counts->syncobj);
2538 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2539 }
2540 }
2541
2542 for (uint32_t i = 0; i < num_sems; i++) {
2543 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2544
2545 if (sem->temp_syncobj) {
2546 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2547 }
2548 else if (sem->syncobj)
2549 counts->syncobj[syncobj_idx++] = sem->syncobj;
2550 else {
2551 assert(sem->sem);
2552 counts->sem[sem_idx++] = sem->sem;
2553 }
2554 }
2555
2556 if (_fence != VK_NULL_HANDLE) {
2557 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2558 if (fence->temp_syncobj)
2559 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2560 else if (fence->syncobj)
2561 counts->syncobj[syncobj_idx++] = fence->syncobj;
2562 }
2563
2564 return VK_SUCCESS;
2565 }
2566
2567 static void
2568 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2569 {
2570 free(sem_info->wait.syncobj);
2571 free(sem_info->wait.sem);
2572 free(sem_info->signal.syncobj);
2573 free(sem_info->signal.sem);
2574 }
2575
2576
2577 static void radv_free_temp_syncobjs(struct radv_device *device,
2578 int num_sems,
2579 const VkSemaphore *sems)
2580 {
2581 for (uint32_t i = 0; i < num_sems; i++) {
2582 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2583
2584 if (sem->temp_syncobj) {
2585 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2586 sem->temp_syncobj = 0;
2587 }
2588 }
2589 }
2590
2591 static VkResult
2592 radv_alloc_sem_info(struct radv_instance *instance,
2593 struct radv_winsys_sem_info *sem_info,
2594 int num_wait_sems,
2595 const VkSemaphore *wait_sems,
2596 int num_signal_sems,
2597 const VkSemaphore *signal_sems,
2598 VkFence fence)
2599 {
2600 VkResult ret;
2601 memset(sem_info, 0, sizeof(*sem_info));
2602
2603 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2604 if (ret)
2605 return ret;
2606 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2607 if (ret)
2608 radv_free_sem_info(sem_info);
2609
2610 /* caller can override these */
2611 sem_info->cs_emit_wait = true;
2612 sem_info->cs_emit_signal = true;
2613 return ret;
2614 }
2615
2616 /* Signals fence as soon as all the work currently put on queue is done. */
2617 static VkResult radv_signal_fence(struct radv_queue *queue,
2618 struct radv_fence *fence)
2619 {
2620 int ret;
2621 VkResult result;
2622 struct radv_winsys_sem_info sem_info;
2623
2624 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2625 radv_fence_to_handle(fence));
2626 if (result != VK_SUCCESS)
2627 return result;
2628
2629 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2630 &queue->device->empty_cs[queue->queue_family_index],
2631 1, NULL, NULL, &sem_info, NULL,
2632 false, fence->fence);
2633 radv_free_sem_info(&sem_info);
2634
2635 if (ret)
2636 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2637
2638 return VK_SUCCESS;
2639 }
2640
2641 VkResult radv_QueueSubmit(
2642 VkQueue _queue,
2643 uint32_t submitCount,
2644 const VkSubmitInfo* pSubmits,
2645 VkFence _fence)
2646 {
2647 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2648 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2649 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2650 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2651 int ret;
2652 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2653 uint32_t scratch_size = 0;
2654 uint32_t compute_scratch_size = 0;
2655 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2656 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2657 VkResult result;
2658 bool fence_emitted = false;
2659 bool tess_rings_needed = false;
2660 bool sample_positions_needed = false;
2661
2662 /* Do this first so failing to allocate scratch buffers can't result in
2663 * partially executed submissions. */
2664 for (uint32_t i = 0; i < submitCount; i++) {
2665 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2666 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2667 pSubmits[i].pCommandBuffers[j]);
2668
2669 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2670 compute_scratch_size = MAX2(compute_scratch_size,
2671 cmd_buffer->compute_scratch_size_needed);
2672 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2673 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2674 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2675 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2676 }
2677 }
2678
2679 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2680 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2681 sample_positions_needed, &initial_flush_preamble_cs,
2682 &initial_preamble_cs, &continue_preamble_cs);
2683 if (result != VK_SUCCESS)
2684 return result;
2685
2686 for (uint32_t i = 0; i < submitCount; i++) {
2687 struct radeon_cmdbuf **cs_array;
2688 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2689 bool can_patch = true;
2690 uint32_t advance;
2691 struct radv_winsys_sem_info sem_info;
2692
2693 result = radv_alloc_sem_info(queue->device->instance,
2694 &sem_info,
2695 pSubmits[i].waitSemaphoreCount,
2696 pSubmits[i].pWaitSemaphores,
2697 pSubmits[i].signalSemaphoreCount,
2698 pSubmits[i].pSignalSemaphores,
2699 _fence);
2700 if (result != VK_SUCCESS)
2701 return result;
2702
2703 if (!pSubmits[i].commandBufferCount) {
2704 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2705 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2706 &queue->device->empty_cs[queue->queue_family_index],
2707 1, NULL, NULL,
2708 &sem_info, NULL,
2709 false, base_fence);
2710 if (ret) {
2711 radv_loge("failed to submit CS %d\n", i);
2712 abort();
2713 }
2714 fence_emitted = true;
2715 }
2716 radv_free_sem_info(&sem_info);
2717 continue;
2718 }
2719
2720 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
2721 (pSubmits[i].commandBufferCount));
2722
2723 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2724 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2725 pSubmits[i].pCommandBuffers[j]);
2726 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2727
2728 cs_array[j] = cmd_buffer->cs;
2729 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2730 can_patch = false;
2731
2732 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2733 }
2734
2735 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2736 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2737 const struct radv_winsys_bo_list *bo_list = NULL;
2738
2739 advance = MIN2(max_cs_submission,
2740 pSubmits[i].commandBufferCount - j);
2741
2742 if (queue->device->trace_bo)
2743 *queue->device->trace_id_ptr = 0;
2744
2745 sem_info.cs_emit_wait = j == 0;
2746 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2747
2748 if (unlikely(queue->device->use_global_bo_list)) {
2749 pthread_mutex_lock(&queue->device->bo_list.mutex);
2750 bo_list = &queue->device->bo_list.list;
2751 }
2752
2753 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2754 advance, initial_preamble, continue_preamble_cs,
2755 &sem_info, bo_list,
2756 can_patch, base_fence);
2757
2758 if (unlikely(queue->device->use_global_bo_list))
2759 pthread_mutex_unlock(&queue->device->bo_list.mutex);
2760
2761 if (ret) {
2762 radv_loge("failed to submit CS %d\n", i);
2763 abort();
2764 }
2765 fence_emitted = true;
2766 if (queue->device->trace_bo) {
2767 radv_check_gpu_hangs(queue, cs_array[j]);
2768 }
2769 }
2770
2771 radv_free_temp_syncobjs(queue->device,
2772 pSubmits[i].waitSemaphoreCount,
2773 pSubmits[i].pWaitSemaphores);
2774 radv_free_sem_info(&sem_info);
2775 free(cs_array);
2776 }
2777
2778 if (fence) {
2779 if (!fence_emitted) {
2780 result = radv_signal_fence(queue, fence);
2781 if (result != VK_SUCCESS)
2782 return result;
2783 }
2784 fence->submitted = true;
2785 }
2786
2787 return VK_SUCCESS;
2788 }
2789
2790 VkResult radv_QueueWaitIdle(
2791 VkQueue _queue)
2792 {
2793 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2794
2795 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2796 radv_queue_family_to_ring(queue->queue_family_index),
2797 queue->queue_idx);
2798 return VK_SUCCESS;
2799 }
2800
2801 VkResult radv_DeviceWaitIdle(
2802 VkDevice _device)
2803 {
2804 RADV_FROM_HANDLE(radv_device, device, _device);
2805
2806 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2807 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2808 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2809 }
2810 }
2811 return VK_SUCCESS;
2812 }
2813
2814 VkResult radv_EnumerateInstanceExtensionProperties(
2815 const char* pLayerName,
2816 uint32_t* pPropertyCount,
2817 VkExtensionProperties* pProperties)
2818 {
2819 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2820
2821 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
2822 if (radv_supported_instance_extensions.extensions[i]) {
2823 vk_outarray_append(&out, prop) {
2824 *prop = radv_instance_extensions[i];
2825 }
2826 }
2827 }
2828
2829 return vk_outarray_status(&out);
2830 }
2831
2832 VkResult radv_EnumerateDeviceExtensionProperties(
2833 VkPhysicalDevice physicalDevice,
2834 const char* pLayerName,
2835 uint32_t* pPropertyCount,
2836 VkExtensionProperties* pProperties)
2837 {
2838 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2839 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2840
2841 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
2842 if (device->supported_extensions.extensions[i]) {
2843 vk_outarray_append(&out, prop) {
2844 *prop = radv_device_extensions[i];
2845 }
2846 }
2847 }
2848
2849 return vk_outarray_status(&out);
2850 }
2851
2852 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2853 VkInstance _instance,
2854 const char* pName)
2855 {
2856 RADV_FROM_HANDLE(radv_instance, instance, _instance);
2857
2858 return radv_lookup_entrypoint_checked(pName,
2859 instance ? instance->apiVersion : 0,
2860 instance ? &instance->enabled_extensions : NULL,
2861 NULL);
2862 }
2863
2864 /* The loader wants us to expose a second GetInstanceProcAddr function
2865 * to work around certain LD_PRELOAD issues seen in apps.
2866 */
2867 PUBLIC
2868 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2869 VkInstance instance,
2870 const char* pName);
2871
2872 PUBLIC
2873 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2874 VkInstance instance,
2875 const char* pName)
2876 {
2877 return radv_GetInstanceProcAddr(instance, pName);
2878 }
2879
2880 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2881 VkDevice _device,
2882 const char* pName)
2883 {
2884 RADV_FROM_HANDLE(radv_device, device, _device);
2885
2886 return radv_lookup_entrypoint_checked(pName,
2887 device->instance->apiVersion,
2888 &device->instance->enabled_extensions,
2889 &device->enabled_extensions);
2890 }
2891
2892 bool radv_get_memory_fd(struct radv_device *device,
2893 struct radv_device_memory *memory,
2894 int *pFD)
2895 {
2896 struct radeon_bo_metadata metadata;
2897
2898 if (memory->image) {
2899 radv_init_metadata(device, memory->image, &metadata);
2900 device->ws->buffer_set_metadata(memory->bo, &metadata);
2901 }
2902
2903 return device->ws->buffer_get_fd(device->ws, memory->bo,
2904 pFD);
2905 }
2906
2907 static VkResult radv_alloc_memory(struct radv_device *device,
2908 const VkMemoryAllocateInfo* pAllocateInfo,
2909 const VkAllocationCallbacks* pAllocator,
2910 VkDeviceMemory* pMem)
2911 {
2912 struct radv_device_memory *mem;
2913 VkResult result;
2914 enum radeon_bo_domain domain;
2915 uint32_t flags = 0;
2916 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
2917
2918 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2919
2920 if (pAllocateInfo->allocationSize == 0) {
2921 /* Apparently, this is allowed */
2922 *pMem = VK_NULL_HANDLE;
2923 return VK_SUCCESS;
2924 }
2925
2926 const VkImportMemoryFdInfoKHR *import_info =
2927 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2928 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2929 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2930 const VkExportMemoryAllocateInfoKHR *export_info =
2931 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO_KHR);
2932 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
2933 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
2934
2935 const struct wsi_memory_allocate_info *wsi_info =
2936 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
2937
2938 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2939 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2940 if (mem == NULL)
2941 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2942
2943 if (wsi_info && wsi_info->implicit_sync)
2944 flags |= RADEON_FLAG_IMPLICIT_SYNC;
2945
2946 if (dedicate_info) {
2947 mem->image = radv_image_from_handle(dedicate_info->image);
2948 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2949 } else {
2950 mem->image = NULL;
2951 mem->buffer = NULL;
2952 }
2953
2954 mem->user_ptr = NULL;
2955
2956 if (import_info) {
2957 assert(import_info->handleType ==
2958 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
2959 import_info->handleType ==
2960 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
2961 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2962 NULL, NULL);
2963 if (!mem->bo) {
2964 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2965 goto fail;
2966 } else {
2967 close(import_info->fd);
2968 }
2969 } else if (host_ptr_info) {
2970 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
2971 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
2972 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
2973 pAllocateInfo->allocationSize);
2974 if (!mem->bo) {
2975 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2976 goto fail;
2977 } else {
2978 mem->user_ptr = host_ptr_info->pHostPointer;
2979 }
2980 } else {
2981 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2982 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2983 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
2984 domain = RADEON_DOMAIN_GTT;
2985 else
2986 domain = RADEON_DOMAIN_VRAM;
2987
2988 if (mem_type_index == RADV_MEM_TYPE_VRAM)
2989 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2990 else
2991 flags |= RADEON_FLAG_CPU_ACCESS;
2992
2993 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2994 flags |= RADEON_FLAG_GTT_WC;
2995
2996 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
2997 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
2998
2999 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3000 domain, flags);
3001
3002 if (!mem->bo) {
3003 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3004 goto fail;
3005 }
3006 mem->type_index = mem_type_index;
3007 }
3008
3009 result = radv_bo_list_add(device, mem->bo);
3010 if (result != VK_SUCCESS)
3011 goto fail_bo;
3012
3013 *pMem = radv_device_memory_to_handle(mem);
3014
3015 return VK_SUCCESS;
3016
3017 fail_bo:
3018 device->ws->buffer_destroy(mem->bo);
3019 fail:
3020 vk_free2(&device->alloc, pAllocator, mem);
3021
3022 return result;
3023 }
3024
3025 VkResult radv_AllocateMemory(
3026 VkDevice _device,
3027 const VkMemoryAllocateInfo* pAllocateInfo,
3028 const VkAllocationCallbacks* pAllocator,
3029 VkDeviceMemory* pMem)
3030 {
3031 RADV_FROM_HANDLE(radv_device, device, _device);
3032 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3033 }
3034
3035 void radv_FreeMemory(
3036 VkDevice _device,
3037 VkDeviceMemory _mem,
3038 const VkAllocationCallbacks* pAllocator)
3039 {
3040 RADV_FROM_HANDLE(radv_device, device, _device);
3041 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3042
3043 if (mem == NULL)
3044 return;
3045
3046 radv_bo_list_remove(device, mem->bo);
3047 device->ws->buffer_destroy(mem->bo);
3048 mem->bo = NULL;
3049
3050 vk_free2(&device->alloc, pAllocator, mem);
3051 }
3052
3053 VkResult radv_MapMemory(
3054 VkDevice _device,
3055 VkDeviceMemory _memory,
3056 VkDeviceSize offset,
3057 VkDeviceSize size,
3058 VkMemoryMapFlags flags,
3059 void** ppData)
3060 {
3061 RADV_FROM_HANDLE(radv_device, device, _device);
3062 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3063
3064 if (mem == NULL) {
3065 *ppData = NULL;
3066 return VK_SUCCESS;
3067 }
3068
3069 if (mem->user_ptr)
3070 *ppData = mem->user_ptr;
3071 else
3072 *ppData = device->ws->buffer_map(mem->bo);
3073
3074 if (*ppData) {
3075 *ppData += offset;
3076 return VK_SUCCESS;
3077 }
3078
3079 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3080 }
3081
3082 void radv_UnmapMemory(
3083 VkDevice _device,
3084 VkDeviceMemory _memory)
3085 {
3086 RADV_FROM_HANDLE(radv_device, device, _device);
3087 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3088
3089 if (mem == NULL)
3090 return;
3091
3092 if (mem->user_ptr == NULL)
3093 device->ws->buffer_unmap(mem->bo);
3094 }
3095
3096 VkResult radv_FlushMappedMemoryRanges(
3097 VkDevice _device,
3098 uint32_t memoryRangeCount,
3099 const VkMappedMemoryRange* pMemoryRanges)
3100 {
3101 return VK_SUCCESS;
3102 }
3103
3104 VkResult radv_InvalidateMappedMemoryRanges(
3105 VkDevice _device,
3106 uint32_t memoryRangeCount,
3107 const VkMappedMemoryRange* pMemoryRanges)
3108 {
3109 return VK_SUCCESS;
3110 }
3111
3112 void radv_GetBufferMemoryRequirements(
3113 VkDevice _device,
3114 VkBuffer _buffer,
3115 VkMemoryRequirements* pMemoryRequirements)
3116 {
3117 RADV_FROM_HANDLE(radv_device, device, _device);
3118 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3119
3120 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3121
3122 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3123 pMemoryRequirements->alignment = 4096;
3124 else
3125 pMemoryRequirements->alignment = 16;
3126
3127 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3128 }
3129
3130 void radv_GetBufferMemoryRequirements2(
3131 VkDevice device,
3132 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
3133 VkMemoryRequirements2KHR* pMemoryRequirements)
3134 {
3135 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3136 &pMemoryRequirements->memoryRequirements);
3137 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3138 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3139 switch (ext->sType) {
3140 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
3141 VkMemoryDedicatedRequirementsKHR *req =
3142 (VkMemoryDedicatedRequirementsKHR *) ext;
3143 req->requiresDedicatedAllocation = buffer->shareable;
3144 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3145 break;
3146 }
3147 default:
3148 break;
3149 }
3150 }
3151 }
3152
3153 void radv_GetImageMemoryRequirements(
3154 VkDevice _device,
3155 VkImage _image,
3156 VkMemoryRequirements* pMemoryRequirements)
3157 {
3158 RADV_FROM_HANDLE(radv_device, device, _device);
3159 RADV_FROM_HANDLE(radv_image, image, _image);
3160
3161 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3162
3163 pMemoryRequirements->size = image->size;
3164 pMemoryRequirements->alignment = image->alignment;
3165 }
3166
3167 void radv_GetImageMemoryRequirements2(
3168 VkDevice device,
3169 const VkImageMemoryRequirementsInfo2KHR* pInfo,
3170 VkMemoryRequirements2KHR* pMemoryRequirements)
3171 {
3172 radv_GetImageMemoryRequirements(device, pInfo->image,
3173 &pMemoryRequirements->memoryRequirements);
3174
3175 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3176
3177 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3178 switch (ext->sType) {
3179 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
3180 VkMemoryDedicatedRequirementsKHR *req =
3181 (VkMemoryDedicatedRequirementsKHR *) ext;
3182 req->requiresDedicatedAllocation = image->shareable;
3183 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3184 break;
3185 }
3186 default:
3187 break;
3188 }
3189 }
3190 }
3191
3192 void radv_GetImageSparseMemoryRequirements(
3193 VkDevice device,
3194 VkImage image,
3195 uint32_t* pSparseMemoryRequirementCount,
3196 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3197 {
3198 stub();
3199 }
3200
3201 void radv_GetImageSparseMemoryRequirements2(
3202 VkDevice device,
3203 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
3204 uint32_t* pSparseMemoryRequirementCount,
3205 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
3206 {
3207 stub();
3208 }
3209
3210 void radv_GetDeviceMemoryCommitment(
3211 VkDevice device,
3212 VkDeviceMemory memory,
3213 VkDeviceSize* pCommittedMemoryInBytes)
3214 {
3215 *pCommittedMemoryInBytes = 0;
3216 }
3217
3218 VkResult radv_BindBufferMemory2(VkDevice device,
3219 uint32_t bindInfoCount,
3220 const VkBindBufferMemoryInfoKHR *pBindInfos)
3221 {
3222 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3223 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3224 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3225
3226 if (mem) {
3227 buffer->bo = mem->bo;
3228 buffer->offset = pBindInfos[i].memoryOffset;
3229 } else {
3230 buffer->bo = NULL;
3231 }
3232 }
3233 return VK_SUCCESS;
3234 }
3235
3236 VkResult radv_BindBufferMemory(
3237 VkDevice device,
3238 VkBuffer buffer,
3239 VkDeviceMemory memory,
3240 VkDeviceSize memoryOffset)
3241 {
3242 const VkBindBufferMemoryInfoKHR info = {
3243 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3244 .buffer = buffer,
3245 .memory = memory,
3246 .memoryOffset = memoryOffset
3247 };
3248
3249 return radv_BindBufferMemory2(device, 1, &info);
3250 }
3251
3252 VkResult radv_BindImageMemory2(VkDevice device,
3253 uint32_t bindInfoCount,
3254 const VkBindImageMemoryInfoKHR *pBindInfos)
3255 {
3256 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3257 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3258 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3259
3260 if (mem) {
3261 image->bo = mem->bo;
3262 image->offset = pBindInfos[i].memoryOffset;
3263 } else {
3264 image->bo = NULL;
3265 image->offset = 0;
3266 }
3267 }
3268 return VK_SUCCESS;
3269 }
3270
3271
3272 VkResult radv_BindImageMemory(
3273 VkDevice device,
3274 VkImage image,
3275 VkDeviceMemory memory,
3276 VkDeviceSize memoryOffset)
3277 {
3278 const VkBindImageMemoryInfoKHR info = {
3279 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3280 .image = image,
3281 .memory = memory,
3282 .memoryOffset = memoryOffset
3283 };
3284
3285 return radv_BindImageMemory2(device, 1, &info);
3286 }
3287
3288
3289 static void
3290 radv_sparse_buffer_bind_memory(struct radv_device *device,
3291 const VkSparseBufferMemoryBindInfo *bind)
3292 {
3293 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3294
3295 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3296 struct radv_device_memory *mem = NULL;
3297
3298 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3299 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3300
3301 device->ws->buffer_virtual_bind(buffer->bo,
3302 bind->pBinds[i].resourceOffset,
3303 bind->pBinds[i].size,
3304 mem ? mem->bo : NULL,
3305 bind->pBinds[i].memoryOffset);
3306 }
3307 }
3308
3309 static void
3310 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3311 const VkSparseImageOpaqueMemoryBindInfo *bind)
3312 {
3313 RADV_FROM_HANDLE(radv_image, image, bind->image);
3314
3315 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3316 struct radv_device_memory *mem = NULL;
3317
3318 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3319 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3320
3321 device->ws->buffer_virtual_bind(image->bo,
3322 bind->pBinds[i].resourceOffset,
3323 bind->pBinds[i].size,
3324 mem ? mem->bo : NULL,
3325 bind->pBinds[i].memoryOffset);
3326 }
3327 }
3328
3329 VkResult radv_QueueBindSparse(
3330 VkQueue _queue,
3331 uint32_t bindInfoCount,
3332 const VkBindSparseInfo* pBindInfo,
3333 VkFence _fence)
3334 {
3335 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3336 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3337 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3338 bool fence_emitted = false;
3339 VkResult result;
3340 int ret;
3341
3342 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3343 struct radv_winsys_sem_info sem_info;
3344 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3345 radv_sparse_buffer_bind_memory(queue->device,
3346 pBindInfo[i].pBufferBinds + j);
3347 }
3348
3349 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3350 radv_sparse_image_opaque_bind_memory(queue->device,
3351 pBindInfo[i].pImageOpaqueBinds + j);
3352 }
3353
3354 VkResult result;
3355 result = radv_alloc_sem_info(queue->device->instance,
3356 &sem_info,
3357 pBindInfo[i].waitSemaphoreCount,
3358 pBindInfo[i].pWaitSemaphores,
3359 pBindInfo[i].signalSemaphoreCount,
3360 pBindInfo[i].pSignalSemaphores,
3361 _fence);
3362 if (result != VK_SUCCESS)
3363 return result;
3364
3365 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3366 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3367 &queue->device->empty_cs[queue->queue_family_index],
3368 1, NULL, NULL,
3369 &sem_info, NULL,
3370 false, base_fence);
3371 if (ret) {
3372 radv_loge("failed to submit CS %d\n", i);
3373 abort();
3374 }
3375
3376 fence_emitted = true;
3377 if (fence)
3378 fence->submitted = true;
3379 }
3380
3381 radv_free_sem_info(&sem_info);
3382
3383 }
3384
3385 if (fence) {
3386 if (!fence_emitted) {
3387 result = radv_signal_fence(queue, fence);
3388 if (result != VK_SUCCESS)
3389 return result;
3390 }
3391 fence->submitted = true;
3392 }
3393
3394 return VK_SUCCESS;
3395 }
3396
3397 VkResult radv_CreateFence(
3398 VkDevice _device,
3399 const VkFenceCreateInfo* pCreateInfo,
3400 const VkAllocationCallbacks* pAllocator,
3401 VkFence* pFence)
3402 {
3403 RADV_FROM_HANDLE(radv_device, device, _device);
3404 const VkExportFenceCreateInfoKHR *export =
3405 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO_KHR);
3406 VkExternalFenceHandleTypeFlagsKHR handleTypes =
3407 export ? export->handleTypes : 0;
3408
3409 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3410 sizeof(*fence), 8,
3411 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3412
3413 if (!fence)
3414 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3415
3416 fence->fence_wsi = NULL;
3417 fence->submitted = false;
3418 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3419 fence->temp_syncobj = 0;
3420 if (device->always_use_syncobj || handleTypes) {
3421 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3422 if (ret) {
3423 vk_free2(&device->alloc, pAllocator, fence);
3424 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3425 }
3426 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3427 device->ws->signal_syncobj(device->ws, fence->syncobj);
3428 }
3429 fence->fence = NULL;
3430 } else {
3431 fence->fence = device->ws->create_fence();
3432 if (!fence->fence) {
3433 vk_free2(&device->alloc, pAllocator, fence);
3434 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3435 }
3436 fence->syncobj = 0;
3437 }
3438
3439 *pFence = radv_fence_to_handle(fence);
3440
3441 return VK_SUCCESS;
3442 }
3443
3444 void radv_DestroyFence(
3445 VkDevice _device,
3446 VkFence _fence,
3447 const VkAllocationCallbacks* pAllocator)
3448 {
3449 RADV_FROM_HANDLE(radv_device, device, _device);
3450 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3451
3452 if (!fence)
3453 return;
3454
3455 if (fence->temp_syncobj)
3456 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3457 if (fence->syncobj)
3458 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3459 if (fence->fence)
3460 device->ws->destroy_fence(fence->fence);
3461 if (fence->fence_wsi)
3462 fence->fence_wsi->destroy(fence->fence_wsi);
3463 vk_free2(&device->alloc, pAllocator, fence);
3464 }
3465
3466
3467 static uint64_t radv_get_current_time()
3468 {
3469 struct timespec tv;
3470 clock_gettime(CLOCK_MONOTONIC, &tv);
3471 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3472 }
3473
3474 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3475 {
3476 uint64_t current_time = radv_get_current_time();
3477
3478 timeout = MIN2(UINT64_MAX - current_time, timeout);
3479
3480 return current_time + timeout;
3481 }
3482
3483
3484 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3485 {
3486 for (uint32_t i = 0; i < fenceCount; ++i) {
3487 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3488 if (fence->fence == NULL || fence->syncobj ||
3489 fence->temp_syncobj ||
3490 (!fence->signalled && !fence->submitted))
3491 return false;
3492 }
3493 return true;
3494 }
3495
3496 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3497 {
3498 for (uint32_t i = 0; i < fenceCount; ++i) {
3499 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3500 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3501 return false;
3502 }
3503 return true;
3504 }
3505
3506 VkResult radv_WaitForFences(
3507 VkDevice _device,
3508 uint32_t fenceCount,
3509 const VkFence* pFences,
3510 VkBool32 waitAll,
3511 uint64_t timeout)
3512 {
3513 RADV_FROM_HANDLE(radv_device, device, _device);
3514 timeout = radv_get_absolute_timeout(timeout);
3515
3516 if (device->always_use_syncobj &&
3517 radv_all_fences_syncobj(fenceCount, pFences))
3518 {
3519 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3520 if (!handles)
3521 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3522
3523 for (uint32_t i = 0; i < fenceCount; ++i) {
3524 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3525 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3526 }
3527
3528 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3529
3530 free(handles);
3531 return success ? VK_SUCCESS : VK_TIMEOUT;
3532 }
3533
3534 if (!waitAll && fenceCount > 1) {
3535 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3536 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3537 uint32_t wait_count = 0;
3538 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3539 if (!fences)
3540 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3541
3542 for (uint32_t i = 0; i < fenceCount; ++i) {
3543 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3544
3545 if (fence->signalled) {
3546 free(fences);
3547 return VK_SUCCESS;
3548 }
3549
3550 fences[wait_count++] = fence->fence;
3551 }
3552
3553 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3554 waitAll, timeout - radv_get_current_time());
3555
3556 free(fences);
3557 return success ? VK_SUCCESS : VK_TIMEOUT;
3558 }
3559
3560 while(radv_get_current_time() <= timeout) {
3561 for (uint32_t i = 0; i < fenceCount; ++i) {
3562 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3563 return VK_SUCCESS;
3564 }
3565 }
3566 return VK_TIMEOUT;
3567 }
3568
3569 for (uint32_t i = 0; i < fenceCount; ++i) {
3570 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3571 bool expired = false;
3572
3573 if (fence->temp_syncobj) {
3574 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3575 return VK_TIMEOUT;
3576 continue;
3577 }
3578
3579 if (fence->syncobj) {
3580 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3581 return VK_TIMEOUT;
3582 continue;
3583 }
3584
3585 if (fence->signalled)
3586 continue;
3587
3588 if (fence->fence) {
3589 if (!fence->submitted) {
3590 while(radv_get_current_time() <= timeout &&
3591 !fence->submitted)
3592 /* Do nothing */;
3593
3594 if (!fence->submitted)
3595 return VK_TIMEOUT;
3596
3597 /* Recheck as it may have been set by
3598 * submitting operations. */
3599
3600 if (fence->signalled)
3601 continue;
3602 }
3603
3604 expired = device->ws->fence_wait(device->ws,
3605 fence->fence,
3606 true, timeout);
3607 if (!expired)
3608 return VK_TIMEOUT;
3609 }
3610
3611 if (fence->fence_wsi) {
3612 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3613 if (result != VK_SUCCESS)
3614 return result;
3615 }
3616
3617 fence->signalled = true;
3618 }
3619
3620 return VK_SUCCESS;
3621 }
3622
3623 VkResult radv_ResetFences(VkDevice _device,
3624 uint32_t fenceCount,
3625 const VkFence *pFences)
3626 {
3627 RADV_FROM_HANDLE(radv_device, device, _device);
3628
3629 for (unsigned i = 0; i < fenceCount; ++i) {
3630 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3631 fence->submitted = fence->signalled = false;
3632
3633 /* Per spec, we first restore the permanent payload, and then reset, so
3634 * having a temp syncobj should not skip resetting the permanent syncobj. */
3635 if (fence->temp_syncobj) {
3636 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3637 fence->temp_syncobj = 0;
3638 }
3639
3640 if (fence->syncobj) {
3641 device->ws->reset_syncobj(device->ws, fence->syncobj);
3642 }
3643 }
3644
3645 return VK_SUCCESS;
3646 }
3647
3648 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3649 {
3650 RADV_FROM_HANDLE(radv_device, device, _device);
3651 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3652
3653 if (fence->temp_syncobj) {
3654 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3655 return success ? VK_SUCCESS : VK_NOT_READY;
3656 }
3657
3658 if (fence->syncobj) {
3659 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3660 return success ? VK_SUCCESS : VK_NOT_READY;
3661 }
3662
3663 if (fence->signalled)
3664 return VK_SUCCESS;
3665 if (!fence->submitted)
3666 return VK_NOT_READY;
3667 if (fence->fence) {
3668 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3669 return VK_NOT_READY;
3670 }
3671 if (fence->fence_wsi) {
3672 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
3673
3674 if (result != VK_SUCCESS) {
3675 if (result == VK_TIMEOUT)
3676 return VK_NOT_READY;
3677 return result;
3678 }
3679 }
3680 return VK_SUCCESS;
3681 }
3682
3683
3684 // Queue semaphore functions
3685
3686 VkResult radv_CreateSemaphore(
3687 VkDevice _device,
3688 const VkSemaphoreCreateInfo* pCreateInfo,
3689 const VkAllocationCallbacks* pAllocator,
3690 VkSemaphore* pSemaphore)
3691 {
3692 RADV_FROM_HANDLE(radv_device, device, _device);
3693 const VkExportSemaphoreCreateInfoKHR *export =
3694 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
3695 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
3696 export ? export->handleTypes : 0;
3697
3698 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3699 sizeof(*sem), 8,
3700 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3701 if (!sem)
3702 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3703
3704 sem->temp_syncobj = 0;
3705 /* create a syncobject if we are going to export this semaphore */
3706 if (device->always_use_syncobj || handleTypes) {
3707 assert (device->physical_device->rad_info.has_syncobj);
3708 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3709 if (ret) {
3710 vk_free2(&device->alloc, pAllocator, sem);
3711 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3712 }
3713 sem->sem = NULL;
3714 } else {
3715 sem->sem = device->ws->create_sem(device->ws);
3716 if (!sem->sem) {
3717 vk_free2(&device->alloc, pAllocator, sem);
3718 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3719 }
3720 sem->syncobj = 0;
3721 }
3722
3723 *pSemaphore = radv_semaphore_to_handle(sem);
3724 return VK_SUCCESS;
3725 }
3726
3727 void radv_DestroySemaphore(
3728 VkDevice _device,
3729 VkSemaphore _semaphore,
3730 const VkAllocationCallbacks* pAllocator)
3731 {
3732 RADV_FROM_HANDLE(radv_device, device, _device);
3733 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3734 if (!_semaphore)
3735 return;
3736
3737 if (sem->syncobj)
3738 device->ws->destroy_syncobj(device->ws, sem->syncobj);
3739 else
3740 device->ws->destroy_sem(sem->sem);
3741 vk_free2(&device->alloc, pAllocator, sem);
3742 }
3743
3744 VkResult radv_CreateEvent(
3745 VkDevice _device,
3746 const VkEventCreateInfo* pCreateInfo,
3747 const VkAllocationCallbacks* pAllocator,
3748 VkEvent* pEvent)
3749 {
3750 RADV_FROM_HANDLE(radv_device, device, _device);
3751 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
3752 sizeof(*event), 8,
3753 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3754
3755 if (!event)
3756 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3757
3758 event->bo = device->ws->buffer_create(device->ws, 8, 8,
3759 RADEON_DOMAIN_GTT,
3760 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
3761 if (!event->bo) {
3762 vk_free2(&device->alloc, pAllocator, event);
3763 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3764 }
3765
3766 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
3767
3768 *pEvent = radv_event_to_handle(event);
3769
3770 return VK_SUCCESS;
3771 }
3772
3773 void radv_DestroyEvent(
3774 VkDevice _device,
3775 VkEvent _event,
3776 const VkAllocationCallbacks* pAllocator)
3777 {
3778 RADV_FROM_HANDLE(radv_device, device, _device);
3779 RADV_FROM_HANDLE(radv_event, event, _event);
3780
3781 if (!event)
3782 return;
3783 device->ws->buffer_destroy(event->bo);
3784 vk_free2(&device->alloc, pAllocator, event);
3785 }
3786
3787 VkResult radv_GetEventStatus(
3788 VkDevice _device,
3789 VkEvent _event)
3790 {
3791 RADV_FROM_HANDLE(radv_event, event, _event);
3792
3793 if (*event->map == 1)
3794 return VK_EVENT_SET;
3795 return VK_EVENT_RESET;
3796 }
3797
3798 VkResult radv_SetEvent(
3799 VkDevice _device,
3800 VkEvent _event)
3801 {
3802 RADV_FROM_HANDLE(radv_event, event, _event);
3803 *event->map = 1;
3804
3805 return VK_SUCCESS;
3806 }
3807
3808 VkResult radv_ResetEvent(
3809 VkDevice _device,
3810 VkEvent _event)
3811 {
3812 RADV_FROM_HANDLE(radv_event, event, _event);
3813 *event->map = 0;
3814
3815 return VK_SUCCESS;
3816 }
3817
3818 VkResult radv_CreateBuffer(
3819 VkDevice _device,
3820 const VkBufferCreateInfo* pCreateInfo,
3821 const VkAllocationCallbacks* pAllocator,
3822 VkBuffer* pBuffer)
3823 {
3824 RADV_FROM_HANDLE(radv_device, device, _device);
3825 struct radv_buffer *buffer;
3826
3827 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
3828
3829 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
3830 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3831 if (buffer == NULL)
3832 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3833
3834 buffer->size = pCreateInfo->size;
3835 buffer->usage = pCreateInfo->usage;
3836 buffer->bo = NULL;
3837 buffer->offset = 0;
3838 buffer->flags = pCreateInfo->flags;
3839
3840 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
3841 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR) != NULL;
3842
3843 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
3844 buffer->bo = device->ws->buffer_create(device->ws,
3845 align64(buffer->size, 4096),
3846 4096, 0, RADEON_FLAG_VIRTUAL);
3847 if (!buffer->bo) {
3848 vk_free2(&device->alloc, pAllocator, buffer);
3849 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3850 }
3851 }
3852
3853 *pBuffer = radv_buffer_to_handle(buffer);
3854
3855 return VK_SUCCESS;
3856 }
3857
3858 void radv_DestroyBuffer(
3859 VkDevice _device,
3860 VkBuffer _buffer,
3861 const VkAllocationCallbacks* pAllocator)
3862 {
3863 RADV_FROM_HANDLE(radv_device, device, _device);
3864 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3865
3866 if (!buffer)
3867 return;
3868
3869 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3870 device->ws->buffer_destroy(buffer->bo);
3871
3872 vk_free2(&device->alloc, pAllocator, buffer);
3873 }
3874
3875 static inline unsigned
3876 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
3877 {
3878 if (stencil)
3879 return image->surface.u.legacy.stencil_tiling_index[level];
3880 else
3881 return image->surface.u.legacy.tiling_index[level];
3882 }
3883
3884 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
3885 {
3886 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
3887 }
3888
3889 static uint32_t
3890 radv_init_dcc_control_reg(struct radv_device *device,
3891 struct radv_image_view *iview)
3892 {
3893 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
3894 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
3895 unsigned max_compressed_block_size;
3896 unsigned independent_64b_blocks;
3897
3898 if (!radv_image_has_dcc(iview->image))
3899 return 0;
3900
3901 if (iview->image->info.samples > 1) {
3902 if (iview->image->surface.bpe == 1)
3903 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3904 else if (iview->image->surface.bpe == 2)
3905 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
3906 }
3907
3908 if (!device->physical_device->rad_info.has_dedicated_vram) {
3909 /* amdvlk: [min-compressed-block-size] should be set to 32 for
3910 * dGPU and 64 for APU because all of our APUs to date use
3911 * DIMMs which have a request granularity size of 64B while all
3912 * other chips have a 32B request size.
3913 */
3914 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
3915 }
3916
3917 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
3918 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
3919 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
3920 /* If this DCC image is potentially going to be used in texture
3921 * fetches, we need some special settings.
3922 */
3923 independent_64b_blocks = 1;
3924 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3925 } else {
3926 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
3927 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
3928 * big as possible for better compression state.
3929 */
3930 independent_64b_blocks = 0;
3931 max_compressed_block_size = max_uncompressed_block_size;
3932 }
3933
3934 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3935 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
3936 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
3937 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
3938 }
3939
3940 static void
3941 radv_initialise_color_surface(struct radv_device *device,
3942 struct radv_color_buffer_info *cb,
3943 struct radv_image_view *iview)
3944 {
3945 const struct vk_format_description *desc;
3946 unsigned ntype, format, swap, endian;
3947 unsigned blend_clamp = 0, blend_bypass = 0;
3948 uint64_t va;
3949 const struct radeon_surf *surf = &iview->image->surface;
3950
3951 desc = vk_format_description(iview->vk_format);
3952
3953 memset(cb, 0, sizeof(*cb));
3954
3955 /* Intensity is implemented as Red, so treat it that way. */
3956 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
3957
3958 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3959
3960 cb->cb_color_base = va >> 8;
3961
3962 if (device->physical_device->rad_info.chip_class >= GFX9) {
3963 struct gfx9_surf_meta_flags meta;
3964 if (iview->image->dcc_offset)
3965 meta = iview->image->surface.u.gfx9.dcc;
3966 else
3967 meta = iview->image->surface.u.gfx9.cmask;
3968
3969 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3970 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
3971 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3972 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3973
3974 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
3975 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3976 } else {
3977 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
3978 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3979
3980 cb->cb_color_base += level_info->offset >> 8;
3981 if (level_info->mode == RADEON_SURF_MODE_2D)
3982 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3983
3984 pitch_tile_max = level_info->nblk_x / 8 - 1;
3985 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
3986 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
3987
3988 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3989 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3990 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
3991
3992 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3993
3994 if (radv_image_has_fmask(iview->image)) {
3995 if (device->physical_device->rad_info.chip_class >= CIK)
3996 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
3997 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
3998 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
3999 } else {
4000 /* This must be set for fast clear to work without FMASK. */
4001 if (device->physical_device->rad_info.chip_class >= CIK)
4002 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4003 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4004 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4005 }
4006 }
4007
4008 /* CMASK variables */
4009 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4010 va += iview->image->cmask.offset;
4011 cb->cb_color_cmask = va >> 8;
4012
4013 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4014 va += iview->image->dcc_offset;
4015 cb->cb_dcc_base = va >> 8;
4016 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
4017
4018 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4019 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4020 S_028C6C_SLICE_MAX(max_slice);
4021
4022 if (iview->image->info.samples > 1) {
4023 unsigned log_samples = util_logbase2(iview->image->info.samples);
4024
4025 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4026 S_028C74_NUM_FRAGMENTS(log_samples);
4027 }
4028
4029 if (radv_image_has_fmask(iview->image)) {
4030 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
4031 cb->cb_color_fmask = va >> 8;
4032 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
4033 } else {
4034 cb->cb_color_fmask = cb->cb_color_base;
4035 }
4036
4037 ntype = radv_translate_color_numformat(iview->vk_format,
4038 desc,
4039 vk_format_get_first_non_void_channel(iview->vk_format));
4040 format = radv_translate_colorformat(iview->vk_format);
4041 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4042 radv_finishme("Illegal color\n");
4043 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4044 endian = radv_colorformat_endian_swap(format);
4045
4046 /* blend clamp should be set for all NORM/SRGB types */
4047 if (ntype == V_028C70_NUMBER_UNORM ||
4048 ntype == V_028C70_NUMBER_SNORM ||
4049 ntype == V_028C70_NUMBER_SRGB)
4050 blend_clamp = 1;
4051
4052 /* set blend bypass according to docs if SINT/UINT or
4053 8/24 COLOR variants */
4054 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4055 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4056 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4057 blend_clamp = 0;
4058 blend_bypass = 1;
4059 }
4060 #if 0
4061 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4062 (format == V_028C70_COLOR_8 ||
4063 format == V_028C70_COLOR_8_8 ||
4064 format == V_028C70_COLOR_8_8_8_8))
4065 ->color_is_int8 = true;
4066 #endif
4067 cb->cb_color_info = S_028C70_FORMAT(format) |
4068 S_028C70_COMP_SWAP(swap) |
4069 S_028C70_BLEND_CLAMP(blend_clamp) |
4070 S_028C70_BLEND_BYPASS(blend_bypass) |
4071 S_028C70_SIMPLE_FLOAT(1) |
4072 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4073 ntype != V_028C70_NUMBER_SNORM &&
4074 ntype != V_028C70_NUMBER_SRGB &&
4075 format != V_028C70_COLOR_8_24 &&
4076 format != V_028C70_COLOR_24_8) |
4077 S_028C70_NUMBER_TYPE(ntype) |
4078 S_028C70_ENDIAN(endian);
4079 if (radv_image_has_fmask(iview->image)) {
4080 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4081 if (device->physical_device->rad_info.chip_class == SI) {
4082 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
4083 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4084 }
4085 }
4086
4087 if (radv_image_has_cmask(iview->image) &&
4088 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4089 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4090
4091 if (radv_dcc_enabled(iview->image, iview->base_mip))
4092 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4093
4094 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4095
4096 /* This must be set for fast clear to work without FMASK. */
4097 if (!radv_image_has_fmask(iview->image) &&
4098 device->physical_device->rad_info.chip_class == SI) {
4099 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
4100 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4101 }
4102
4103 if (device->physical_device->rad_info.chip_class >= GFX9) {
4104 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4105 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4106
4107 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
4108 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4109 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
4110 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
4111 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
4112 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4113 }
4114 }
4115
4116 static unsigned
4117 radv_calc_decompress_on_z_planes(struct radv_device *device,
4118 struct radv_image_view *iview)
4119 {
4120 unsigned max_zplanes = 0;
4121
4122 assert(radv_image_is_tc_compat_htile(iview->image));
4123
4124 if (device->physical_device->rad_info.chip_class >= GFX9) {
4125 /* Default value for 32-bit depth surfaces. */
4126 max_zplanes = 4;
4127
4128 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4129 iview->image->info.samples > 1)
4130 max_zplanes = 2;
4131
4132 max_zplanes = max_zplanes + 1;
4133 } else {
4134 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4135 /* Do not enable Z plane compression for 16-bit depth
4136 * surfaces because isn't supported on GFX8. Only
4137 * 32-bit depth surfaces are supported by the hardware.
4138 * This allows to maintain shader compatibility and to
4139 * reduce the number of depth decompressions.
4140 */
4141 max_zplanes = 1;
4142 } else {
4143 if (iview->image->info.samples <= 1)
4144 max_zplanes = 5;
4145 else if (iview->image->info.samples <= 4)
4146 max_zplanes = 3;
4147 else
4148 max_zplanes = 2;
4149 }
4150 }
4151
4152 return max_zplanes;
4153 }
4154
4155 static void
4156 radv_initialise_ds_surface(struct radv_device *device,
4157 struct radv_ds_buffer_info *ds,
4158 struct radv_image_view *iview)
4159 {
4160 unsigned level = iview->base_mip;
4161 unsigned format, stencil_format;
4162 uint64_t va, s_offs, z_offs;
4163 bool stencil_only = false;
4164 memset(ds, 0, sizeof(*ds));
4165 switch (iview->image->vk_format) {
4166 case VK_FORMAT_D24_UNORM_S8_UINT:
4167 case VK_FORMAT_X8_D24_UNORM_PACK32:
4168 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4169 ds->offset_scale = 2.0f;
4170 break;
4171 case VK_FORMAT_D16_UNORM:
4172 case VK_FORMAT_D16_UNORM_S8_UINT:
4173 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4174 ds->offset_scale = 4.0f;
4175 break;
4176 case VK_FORMAT_D32_SFLOAT:
4177 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4178 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4179 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4180 ds->offset_scale = 1.0f;
4181 break;
4182 case VK_FORMAT_S8_UINT:
4183 stencil_only = true;
4184 break;
4185 default:
4186 break;
4187 }
4188
4189 format = radv_translate_dbformat(iview->image->vk_format);
4190 stencil_format = iview->image->surface.has_stencil ?
4191 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4192
4193 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4194 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4195 S_028008_SLICE_MAX(max_slice);
4196
4197 ds->db_htile_data_base = 0;
4198 ds->db_htile_surface = 0;
4199
4200 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4201 s_offs = z_offs = va;
4202
4203 if (device->physical_device->rad_info.chip_class >= GFX9) {
4204 assert(iview->image->surface.u.gfx9.surf_offset == 0);
4205 s_offs += iview->image->surface.u.gfx9.stencil_offset;
4206
4207 ds->db_z_info = S_028038_FORMAT(format) |
4208 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4209 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
4210 S_028038_MAXMIP(iview->image->info.levels - 1) |
4211 S_028038_ZRANGE_PRECISION(1);
4212 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4213 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
4214
4215 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
4216 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
4217 ds->db_depth_view |= S_028008_MIPID(level);
4218
4219 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4220 S_02801C_Y_MAX(iview->image->info.height - 1);
4221
4222 if (radv_htile_enabled(iview->image, level)) {
4223 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4224
4225 if (radv_image_is_tc_compat_htile(iview->image)) {
4226 unsigned max_zplanes =
4227 radv_calc_decompress_on_z_planes(device, iview);
4228
4229 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
4230 S_028038_ITERATE_FLUSH(1);
4231 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4232 }
4233
4234 if (!iview->image->surface.has_stencil)
4235 /* Use all of the htile_buffer for depth if there's no stencil. */
4236 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4237 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4238 iview->image->htile_offset;
4239 ds->db_htile_data_base = va >> 8;
4240 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4241 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
4242 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
4243 }
4244 } else {
4245 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
4246
4247 if (stencil_only)
4248 level_info = &iview->image->surface.u.legacy.stencil_level[level];
4249
4250 z_offs += iview->image->surface.u.legacy.level[level].offset;
4251 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
4252
4253 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4254 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4255 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4256
4257 if (iview->image->info.samples > 1)
4258 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4259
4260 if (device->physical_device->rad_info.chip_class >= CIK) {
4261 struct radeon_info *info = &device->physical_device->rad_info;
4262 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
4263 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
4264 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
4265 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4266 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4267 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4268
4269 if (stencil_only)
4270 tile_mode = stencil_tile_mode;
4271
4272 ds->db_depth_info |=
4273 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4274 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4275 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4276 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4277 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4278 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4279 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4280 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4281 } else {
4282 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
4283 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4284 tile_mode_index = si_tile_mode_index(iview->image, level, true);
4285 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4286 if (stencil_only)
4287 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4288 }
4289
4290 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4291 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4292 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4293
4294 if (radv_htile_enabled(iview->image, level)) {
4295 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4296
4297 if (!iview->image->surface.has_stencil &&
4298 !radv_image_is_tc_compat_htile(iview->image))
4299 /* Use all of the htile_buffer for depth if there's no stencil. */
4300 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4301
4302 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4303 iview->image->htile_offset;
4304 ds->db_htile_data_base = va >> 8;
4305 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4306
4307 if (radv_image_is_tc_compat_htile(iview->image)) {
4308 unsigned max_zplanes =
4309 radv_calc_decompress_on_z_planes(device, iview);
4310
4311 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4312 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4313 }
4314 }
4315 }
4316
4317 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4318 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4319 }
4320
4321 VkResult radv_CreateFramebuffer(
4322 VkDevice _device,
4323 const VkFramebufferCreateInfo* pCreateInfo,
4324 const VkAllocationCallbacks* pAllocator,
4325 VkFramebuffer* pFramebuffer)
4326 {
4327 RADV_FROM_HANDLE(radv_device, device, _device);
4328 struct radv_framebuffer *framebuffer;
4329
4330 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4331
4332 size_t size = sizeof(*framebuffer) +
4333 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4334 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4335 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4336 if (framebuffer == NULL)
4337 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4338
4339 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4340 framebuffer->width = pCreateInfo->width;
4341 framebuffer->height = pCreateInfo->height;
4342 framebuffer->layers = pCreateInfo->layers;
4343 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4344 VkImageView _iview = pCreateInfo->pAttachments[i];
4345 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4346 framebuffer->attachments[i].attachment = iview;
4347 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
4348 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4349 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4350 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4351 }
4352 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4353 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4354 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4355 }
4356
4357 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4358 return VK_SUCCESS;
4359 }
4360
4361 void radv_DestroyFramebuffer(
4362 VkDevice _device,
4363 VkFramebuffer _fb,
4364 const VkAllocationCallbacks* pAllocator)
4365 {
4366 RADV_FROM_HANDLE(radv_device, device, _device);
4367 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4368
4369 if (!fb)
4370 return;
4371 vk_free2(&device->alloc, pAllocator, fb);
4372 }
4373
4374 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4375 {
4376 switch (address_mode) {
4377 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4378 return V_008F30_SQ_TEX_WRAP;
4379 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4380 return V_008F30_SQ_TEX_MIRROR;
4381 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4382 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4383 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4384 return V_008F30_SQ_TEX_CLAMP_BORDER;
4385 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4386 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4387 default:
4388 unreachable("illegal tex wrap mode");
4389 break;
4390 }
4391 }
4392
4393 static unsigned
4394 radv_tex_compare(VkCompareOp op)
4395 {
4396 switch (op) {
4397 case VK_COMPARE_OP_NEVER:
4398 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4399 case VK_COMPARE_OP_LESS:
4400 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4401 case VK_COMPARE_OP_EQUAL:
4402 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4403 case VK_COMPARE_OP_LESS_OR_EQUAL:
4404 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4405 case VK_COMPARE_OP_GREATER:
4406 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4407 case VK_COMPARE_OP_NOT_EQUAL:
4408 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4409 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4410 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4411 case VK_COMPARE_OP_ALWAYS:
4412 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4413 default:
4414 unreachable("illegal compare mode");
4415 break;
4416 }
4417 }
4418
4419 static unsigned
4420 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4421 {
4422 switch (filter) {
4423 case VK_FILTER_NEAREST:
4424 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4425 V_008F38_SQ_TEX_XY_FILTER_POINT);
4426 case VK_FILTER_LINEAR:
4427 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4428 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4429 case VK_FILTER_CUBIC_IMG:
4430 default:
4431 fprintf(stderr, "illegal texture filter");
4432 return 0;
4433 }
4434 }
4435
4436 static unsigned
4437 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4438 {
4439 switch (mode) {
4440 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4441 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4442 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4443 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4444 default:
4445 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4446 }
4447 }
4448
4449 static unsigned
4450 radv_tex_bordercolor(VkBorderColor bcolor)
4451 {
4452 switch (bcolor) {
4453 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4454 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4455 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4456 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4457 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4458 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4459 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4460 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4461 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4462 default:
4463 break;
4464 }
4465 return 0;
4466 }
4467
4468 static unsigned
4469 radv_tex_aniso_filter(unsigned filter)
4470 {
4471 if (filter < 2)
4472 return 0;
4473 if (filter < 4)
4474 return 1;
4475 if (filter < 8)
4476 return 2;
4477 if (filter < 16)
4478 return 3;
4479 return 4;
4480 }
4481
4482 static unsigned
4483 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4484 {
4485 switch (mode) {
4486 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4487 return SQ_IMG_FILTER_MODE_BLEND;
4488 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4489 return SQ_IMG_FILTER_MODE_MIN;
4490 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4491 return SQ_IMG_FILTER_MODE_MAX;
4492 default:
4493 break;
4494 }
4495 return 0;
4496 }
4497
4498 static uint32_t
4499 radv_get_max_anisotropy(struct radv_device *device,
4500 const VkSamplerCreateInfo *pCreateInfo)
4501 {
4502 if (device->force_aniso >= 0)
4503 return device->force_aniso;
4504
4505 if (pCreateInfo->anisotropyEnable &&
4506 pCreateInfo->maxAnisotropy > 1.0f)
4507 return (uint32_t)pCreateInfo->maxAnisotropy;
4508
4509 return 0;
4510 }
4511
4512 static void
4513 radv_init_sampler(struct radv_device *device,
4514 struct radv_sampler *sampler,
4515 const VkSamplerCreateInfo *pCreateInfo)
4516 {
4517 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
4518 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4519 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4520 unsigned filter_mode = SQ_IMG_FILTER_MODE_BLEND;
4521
4522 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4523 vk_find_struct_const(pCreateInfo->pNext,
4524 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4525 if (sampler_reduction)
4526 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4527
4528 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4529 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4530 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4531 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4532 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4533 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4534 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4535 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4536 S_008F30_DISABLE_CUBE_WRAP(0) |
4537 S_008F30_COMPAT_MODE(is_vi) |
4538 S_008F30_FILTER_MODE(filter_mode));
4539 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4540 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4541 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4542 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4543 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4544 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4545 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4546 S_008F38_MIP_POINT_PRECLAMP(0) |
4547 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4548 S_008F38_FILTER_PREC_FIX(1) |
4549 S_008F38_ANISO_OVERRIDE(is_vi));
4550 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4551 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4552 }
4553
4554 VkResult radv_CreateSampler(
4555 VkDevice _device,
4556 const VkSamplerCreateInfo* pCreateInfo,
4557 const VkAllocationCallbacks* pAllocator,
4558 VkSampler* pSampler)
4559 {
4560 RADV_FROM_HANDLE(radv_device, device, _device);
4561 struct radv_sampler *sampler;
4562
4563 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4564
4565 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4566 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4567 if (!sampler)
4568 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4569
4570 radv_init_sampler(device, sampler, pCreateInfo);
4571 *pSampler = radv_sampler_to_handle(sampler);
4572
4573 return VK_SUCCESS;
4574 }
4575
4576 void radv_DestroySampler(
4577 VkDevice _device,
4578 VkSampler _sampler,
4579 const VkAllocationCallbacks* pAllocator)
4580 {
4581 RADV_FROM_HANDLE(radv_device, device, _device);
4582 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4583
4584 if (!sampler)
4585 return;
4586 vk_free2(&device->alloc, pAllocator, sampler);
4587 }
4588
4589 /* vk_icd.h does not declare this function, so we declare it here to
4590 * suppress Wmissing-prototypes.
4591 */
4592 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4593 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4594
4595 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4596 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4597 {
4598 /* For the full details on loader interface versioning, see
4599 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4600 * What follows is a condensed summary, to help you navigate the large and
4601 * confusing official doc.
4602 *
4603 * - Loader interface v0 is incompatible with later versions. We don't
4604 * support it.
4605 *
4606 * - In loader interface v1:
4607 * - The first ICD entrypoint called by the loader is
4608 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4609 * entrypoint.
4610 * - The ICD must statically expose no other Vulkan symbol unless it is
4611 * linked with -Bsymbolic.
4612 * - Each dispatchable Vulkan handle created by the ICD must be
4613 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4614 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4615 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4616 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4617 * such loader-managed surfaces.
4618 *
4619 * - Loader interface v2 differs from v1 in:
4620 * - The first ICD entrypoint called by the loader is
4621 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4622 * statically expose this entrypoint.
4623 *
4624 * - Loader interface v3 differs from v2 in:
4625 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4626 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4627 * because the loader no longer does so.
4628 */
4629 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4630 return VK_SUCCESS;
4631 }
4632
4633 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4634 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4635 int *pFD)
4636 {
4637 RADV_FROM_HANDLE(radv_device, device, _device);
4638 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4639
4640 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4641
4642 /* At the moment, we support only the below handle types. */
4643 assert(pGetFdInfo->handleType ==
4644 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4645 pGetFdInfo->handleType ==
4646 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4647
4648 bool ret = radv_get_memory_fd(device, memory, pFD);
4649 if (ret == false)
4650 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4651 return VK_SUCCESS;
4652 }
4653
4654 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4655 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
4656 int fd,
4657 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4658 {
4659 RADV_FROM_HANDLE(radv_device, device, _device);
4660
4661 switch (handleType) {
4662 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4663 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4664 return VK_SUCCESS;
4665
4666 default:
4667 /* The valid usage section for this function says:
4668 *
4669 * "handleType must not be one of the handle types defined as
4670 * opaque."
4671 *
4672 * So opaque handle types fall into the default "unsupported" case.
4673 */
4674 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4675 }
4676 }
4677
4678 static VkResult radv_import_opaque_fd(struct radv_device *device,
4679 int fd,
4680 uint32_t *syncobj)
4681 {
4682 uint32_t syncobj_handle = 0;
4683 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4684 if (ret != 0)
4685 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4686
4687 if (*syncobj)
4688 device->ws->destroy_syncobj(device->ws, *syncobj);
4689
4690 *syncobj = syncobj_handle;
4691 close(fd);
4692
4693 return VK_SUCCESS;
4694 }
4695
4696 static VkResult radv_import_sync_fd(struct radv_device *device,
4697 int fd,
4698 uint32_t *syncobj)
4699 {
4700 /* If we create a syncobj we do it locally so that if we have an error, we don't
4701 * leave a syncobj in an undetermined state in the fence. */
4702 uint32_t syncobj_handle = *syncobj;
4703 if (!syncobj_handle) {
4704 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4705 if (ret) {
4706 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4707 }
4708 }
4709
4710 if (fd == -1) {
4711 device->ws->signal_syncobj(device->ws, syncobj_handle);
4712 } else {
4713 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
4714 if (ret != 0)
4715 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4716 }
4717
4718 *syncobj = syncobj_handle;
4719 if (fd != -1)
4720 close(fd);
4721
4722 return VK_SUCCESS;
4723 }
4724
4725 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
4726 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
4727 {
4728 RADV_FROM_HANDLE(radv_device, device, _device);
4729 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
4730 uint32_t *syncobj_dst = NULL;
4731
4732 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
4733 syncobj_dst = &sem->temp_syncobj;
4734 } else {
4735 syncobj_dst = &sem->syncobj;
4736 }
4737
4738 switch(pImportSemaphoreFdInfo->handleType) {
4739 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4740 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4741 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4742 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4743 default:
4744 unreachable("Unhandled semaphore handle type");
4745 }
4746 }
4747
4748 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
4749 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
4750 int *pFd)
4751 {
4752 RADV_FROM_HANDLE(radv_device, device, _device);
4753 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
4754 int ret;
4755 uint32_t syncobj_handle;
4756
4757 if (sem->temp_syncobj)
4758 syncobj_handle = sem->temp_syncobj;
4759 else
4760 syncobj_handle = sem->syncobj;
4761
4762 switch(pGetFdInfo->handleType) {
4763 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4764 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4765 break;
4766 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4767 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4768 if (!ret) {
4769 if (sem->temp_syncobj) {
4770 close (sem->temp_syncobj);
4771 sem->temp_syncobj = 0;
4772 } else {
4773 device->ws->reset_syncobj(device->ws, syncobj_handle);
4774 }
4775 }
4776 break;
4777 default:
4778 unreachable("Unhandled semaphore handle type");
4779 }
4780
4781 if (ret)
4782 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4783 return VK_SUCCESS;
4784 }
4785
4786 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
4787 VkPhysicalDevice physicalDevice,
4788 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
4789 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
4790 {
4791 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4792
4793 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
4794 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4795 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4796 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4797 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4798 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4799 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4800 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4801 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
4802 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4803 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4804 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4805 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4806 } else {
4807 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
4808 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
4809 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
4810 }
4811 }
4812
4813 VkResult radv_ImportFenceFdKHR(VkDevice _device,
4814 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
4815 {
4816 RADV_FROM_HANDLE(radv_device, device, _device);
4817 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
4818 uint32_t *syncobj_dst = NULL;
4819
4820
4821 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT_KHR) {
4822 syncobj_dst = &fence->temp_syncobj;
4823 } else {
4824 syncobj_dst = &fence->syncobj;
4825 }
4826
4827 switch(pImportFenceFdInfo->handleType) {
4828 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4829 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4830 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4831 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4832 default:
4833 unreachable("Unhandled fence handle type");
4834 }
4835 }
4836
4837 VkResult radv_GetFenceFdKHR(VkDevice _device,
4838 const VkFenceGetFdInfoKHR *pGetFdInfo,
4839 int *pFd)
4840 {
4841 RADV_FROM_HANDLE(radv_device, device, _device);
4842 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
4843 int ret;
4844 uint32_t syncobj_handle;
4845
4846 if (fence->temp_syncobj)
4847 syncobj_handle = fence->temp_syncobj;
4848 else
4849 syncobj_handle = fence->syncobj;
4850
4851 switch(pGetFdInfo->handleType) {
4852 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4853 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4854 break;
4855 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4856 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4857 if (!ret) {
4858 if (fence->temp_syncobj) {
4859 close (fence->temp_syncobj);
4860 fence->temp_syncobj = 0;
4861 } else {
4862 device->ws->reset_syncobj(device->ws, syncobj_handle);
4863 }
4864 }
4865 break;
4866 default:
4867 unreachable("Unhandled fence handle type");
4868 }
4869
4870 if (ret)
4871 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4872 return VK_SUCCESS;
4873 }
4874
4875 void radv_GetPhysicalDeviceExternalFenceProperties(
4876 VkPhysicalDevice physicalDevice,
4877 const VkPhysicalDeviceExternalFenceInfoKHR* pExternalFenceInfo,
4878 VkExternalFencePropertiesKHR* pExternalFenceProperties)
4879 {
4880 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4881
4882 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4883 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4884 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4885 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4886 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4887 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT_KHR |
4888 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4889 } else {
4890 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
4891 pExternalFenceProperties->compatibleHandleTypes = 0;
4892 pExternalFenceProperties->externalFenceFeatures = 0;
4893 }
4894 }
4895
4896 VkResult
4897 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
4898 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
4899 const VkAllocationCallbacks* pAllocator,
4900 VkDebugReportCallbackEXT* pCallback)
4901 {
4902 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4903 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
4904 pCreateInfo, pAllocator, &instance->alloc,
4905 pCallback);
4906 }
4907
4908 void
4909 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
4910 VkDebugReportCallbackEXT _callback,
4911 const VkAllocationCallbacks* pAllocator)
4912 {
4913 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4914 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
4915 _callback, pAllocator, &instance->alloc);
4916 }
4917
4918 void
4919 radv_DebugReportMessageEXT(VkInstance _instance,
4920 VkDebugReportFlagsEXT flags,
4921 VkDebugReportObjectTypeEXT objectType,
4922 uint64_t object,
4923 size_t location,
4924 int32_t messageCode,
4925 const char* pLayerPrefix,
4926 const char* pMessage)
4927 {
4928 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4929 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
4930 object, location, messageCode, pLayerPrefix, pMessage);
4931 }
4932
4933 void
4934 radv_GetDeviceGroupPeerMemoryFeatures(
4935 VkDevice device,
4936 uint32_t heapIndex,
4937 uint32_t localDeviceIndex,
4938 uint32_t remoteDeviceIndex,
4939 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
4940 {
4941 assert(localDeviceIndex == remoteDeviceIndex);
4942
4943 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
4944 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
4945 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
4946 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
4947 }